diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index ad540ea63536ed6f0e83edf8f41f35b8ce8fc66b..bc2b437bd99905151c17b2aea99b955c971b3f20 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -261,6 +261,9 @@ stages: evb_ast2500: TEST_PY_BD: "evb-ast2500" TEST_PY_ID: "--id qemu" + evb_ast2600: + TEST_PY_BD: "evb-ast2600" + TEST_PY_ID: "--id qemu" vexpress_ca9x4: TEST_PY_BD: "vexpress_ca9x4" TEST_PY_ID: "--id qemu" @@ -473,6 +476,12 @@ stages: BUILDMAN: "imx8" keystone2_keystone3: BUILDMAN: "k2 k3" + sandbox_asan: + BUILDMAN: "sandbox" + OVERRIDE: "-a ASAN" + sandbox_clang_asan: + BUILDMAN: "sandbox" + OVERRIDE: "-O clang-13 -a ASAN" samsung_socfpga: BUILDMAN: "samsung socfpga" sun4i: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c6a608f7e2a74763dc6e533bff3cf4157f7cd06d..f9cd417507916d07e610a6e8fe044904b3071fb5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -272,6 +272,12 @@ evb-ast2500 test.py: TEST_PY_ID: "--id qemu" <<: *buildman_and_testpy_dfn +evb-ast2600 test.py: + variables: + TEST_PY_BD: "evb-ast2600" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + sandbox_flattree test.py: variables: TEST_PY_BD: "sandbox_flattree" diff --git a/Kconfig b/Kconfig index f7e3c332f0785d261be5afc2d35ef7dd762adc61..991b260182e8960c9ed4f560ee7993f2d489b739 100644 --- a/Kconfig +++ b/Kconfig @@ -154,6 +154,22 @@ config CC_COVERAGE Enabling this option will pass "--coverage" to gcc to compile and link code instrumented for coverage analysis. +config ASAN + bool "Enable AddressSanitizer" + depends on SANDBOX + help + Enables AddressSanitizer to discover out-of-bounds accesses, + use-after-free, double-free and memory leaks. + +config FUZZ + bool "Enable fuzzing" + depends on CC_IS_CLANG + depends on DM_FUZZING_ENGINE + select ASAN + help + Enables the fuzzing infrastructure to generate fuzzing data and run + fuzz tests. + config CC_HAS_ASM_INLINE def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null) @@ -228,12 +244,38 @@ config SYS_BOOT_GET_CMDLINE Enables allocating and saving kernel cmdline in space between "bootm_low" and "bootm_low" + BOOTMAPSZ. +config SYS_BARGSIZE + int "Size of kernel command line buffer in bytes" + depends on SYS_BOOT_GET_CMDLINE + default 512 + help + Buffer size for Boot Arguments which are passed to the application + (usually a Linux kernel) when it is booted + config SYS_BOOT_GET_KBD bool "Enable kernel board information setup" help Enables allocating and saving a kernel copy of the bd_info in space between "bootm_low" and "bootm_low" + BOOTMAPSZ. +config HAS_CUSTOM_SYS_INIT_SP_ADDR + bool "Use a custom location for the initial stack pointer address" + depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV + default y if TFABOOT + help + Typically, we use an initial stack pointer address that is calculated + by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the + statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the + build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different + but statica calculation is performed. However, some platforms will + take a different approach. Say Y here to define the address statically + instead. + +config CUSTOM_SYS_INIT_SP_ADDR + hex "Static location for the initial stack pointer" + depends on HAS_CUSTOM_SYS_INIT_SP_ADDR + default SYS_TEXT_BASE if TFABOOT + config SYS_MALLOC_F bool "Enable malloc() pool before relocation" default y if DM diff --git a/MAINTAINERS b/MAINTAINERS index 7f27ff4c20fcf0c5934125a06db23c4107535796..1baa038da790602ad1c58993418fd32abdf158f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -207,6 +207,17 @@ F: drivers/pinctrl/broadcom/ F: configs/rpi_* T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git +ARM BROADCOM BCMBCA +M: Anand Gore +M: William Zhang +M: Kursad Oney +M: Joel Peshkin +S: Maintained +F: arch/arm/mach-bcmbca/ +F: board/broadcom/bcmbca/ +F: configs/bcm947622_defconfig +F: include/configs/bcm947622.h + ARM BROADCOM BCMSTB M: Thomas Fitzsimmons S: Maintained @@ -269,6 +280,19 @@ F: arch/arm/cpu/armv8/hisilicon F: arch/arm/include/asm/arch-hi6220/ F: arch/arm/include/asm/arch-hi3660/ +ARM HPE GXP ARCHITECTURE +M: Jean-Marie Verdun +M: Nick Hawkins +S: Maintained +F: arch/arm/dts/hpe-bmc* +F: arch/arm/dts/hpe-gxp* +F: arch/arm/mach-hpe/ +F: board/hpe/ +F: configs/gxp_defconfig +F: doc/device-tree-bindings/spi/hpe,gxp-spi.yaml +F: drivers/timer/gxp-timer.c +F: drivers/spi/gxp_spi.c + ARM IPQ40XX M: Robert Marko M: Luka Kovacic @@ -283,6 +307,11 @@ F: drivers/spi/spi-qup.c F: drivers/net/mdio-ipq4019.c F: drivers/rng/msm_rng.c +ARM LAYERSCAPE SFP +M: Sean Anderson +S: Maintained +F: drivers/misc/ls2_sfp.c + ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese S: Maintained @@ -320,13 +349,6 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/serial/serial_mvebu_a3700.c -ARM MARVELL PXA -M: Marek Vasut -S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-pxa.git -F: arch/arm/cpu/pxa/ -F: arch/arm/include/asm/arch-pxa/ - ARM MEDIATEK M: Ryder Lee M: Weijie Gao @@ -481,7 +503,7 @@ S: Maintained F: arch/arm/mach-stm32mp/ F: doc/board/st/ F: drivers/adc/stm32-adc* -F: drivers/clk/clk_stm32mp1.c +F: drivers/clk/stm32/ F: drivers/gpio/stm32_gpio.c F: drivers/hwspinlock/stm32_hwspinlock.c F: drivers/i2c/stm32f7_i2c.c @@ -612,6 +634,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ F: drivers/net/xilinx_axi_mrmac.* F: drivers/soc/soc_xilinx_versal.c +F: drivers/spi/cadence_ospi_versal.c F: drivers/watchdog/xilinx_wwdt.c N: (? +S: Maintained +F: doc/api/nvmem.rst +F: drivers/misc/nvmem.c +F: include/nvmem.h + NXP C45 TJA11XX PHY DRIVER M: Radu Pirea S: Maintained @@ -1244,6 +1275,11 @@ F: drivers/gpio/sl28cpld-gpio.c F: drivers/misc/sl28cpld.c F: drivers/watchdog/sl28cpld-wdt.c +SMCCC TRNG +M: Etienne Carriere +S: Maintained +F: drivers/rng/smccc_trng.c + SPI M: Jagan Teki S: Maintained diff --git a/Makefile b/Makefile index 98867fbe06b440e590c621bdcb89b52298efba2f..80cddddddec35efecc4cd678f699f23d7b40aec8 100644 --- a/Makefile +++ b/Makefile @@ -673,6 +673,12 @@ else include/config/auto.conf: ; endif # $(dot-config) +ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG +KBUILD_HOSTCFLAGS := -Wall -Wstrict-prototypes -Og -g -fomit-frame-pointer \ + $(HOST_LFS_CFLAGS) $(HOSTCFLAGS) +KBUILD_HOSTCXXFLAGS := -Og -g $(HOST_LFS_CFLAGS) $(HOSTCXXFLAGS) +endif + # # Xtensa linker script cannot be preprocessed with -ansi because of # preprocessor operations on strings that don't make C identifiers. @@ -922,12 +928,10 @@ endif # the raw binary, but certain simulators only accept an ELF file (but don't # do the relocation). ifneq ($(CONFIG_STATIC_RELA),) -# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base +# $(2) is u-boot ELF, $(3) is u-boot bin, $(4) is text base quiet_cmd_static_rela = RELOC $@ cmd_static_rela = \ - start=$$($(NM) $(2) | grep __rel_dyn_start | cut -f 1 -d ' '); \ - end=$$($(NM) $(2) | grep __rel_dyn_end | cut -f 1 -d ' '); \ - tools/relocate-rela $(3) $(4) $$start $$end + tools/relocate-rela $(3) $(2) else quiet_cmd_static_rela = cmd_static_rela = @@ -2209,7 +2213,7 @@ CLEAN_DIRS += $(MODVERDIR) \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ - include/generated/env.in drivers/video/u_boot_logo.S \ + include/generated/env.* drivers/video/u_boot_logo.S \ tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \ u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \ diff --git a/README b/README index b7ab6e50708d57fb77c2433fa29e9c273009f5b7..ff0df3797d21e63343c4caadf5093423c710368d 100644 --- a/README +++ b/README @@ -293,33 +293,6 @@ board_init_r(): SPL-specific notes: - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and - CONFIG_SPL_STACK_R_ADDR points into SDRAM - - preloader_console_init() can be called here - typically this is - done by selecting CONFIG_SPL_BOARD_INIT and then supplying a - spl_board_init() function containing this call - - loads U-Boot or (in falcon mode) Linux - - -Configuration Options: ----------------------- - -Configuration depends on the combination of board and CPU type; all -such information is kept in a configuration file -"include/configs/.h". - -Example: For a TQM823L module, all configuration settings are in -"include/configs/TQM823L.h". - - -Many of the options are named exactly as the corresponding Linux -kernel configuration options. The intention is to make it easier to -build a config tool - later. - -- ARM Platform Bus Type(CCI): - CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which - provides full cache coherency between two clusters of multi-core - CPUs and I/O coherency for devices and I/O masters - CONFIG_SYS_FSL_HAS_CCI400 Defined For SoC that has cache coherent interconnect @@ -398,10 +371,6 @@ The following options need to be configured: In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. - CONFIG_SYS_CPC_REINIT_F - This CONFIG is defined when the CPC is configured as SRAM at the - time of U-Boot entry and is required to be re-initialized. - - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN @@ -415,10 +384,6 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base. - CONFIG_SYS_FSL_DDR_EMU - Specify emulator support for DDR. Some DDR features such as - deskew training are not available. - CONFIG_SYS_FSL_DDRC_GEN1 Freescale DDR1 controller. @@ -493,12 +458,6 @@ The following options need to be configured: Defines the SEC controller register space as Little Endian - MIPS CPU options: - CONFIG_SYS_INIT_SP_OFFSET - - Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack - pointer. This is needed for the temporary stack before - relocation. - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq @@ -697,18 +656,6 @@ The following options need to be configured: CONFIG_SCSI) you must configure support for at least one non-MTD partition type as well. -- LBA48 Support - CONFIG_LBA48 - - Set this to enable support for disks larger than 137GB - Also look at CONFIG_SYS_64BIT_LBA. - Whithout these , LBA48 support uses 32bit variables and will 'only' - support disks up to 2.1TB. - - CONFIG_SYS_64BIT_LBA: - When enabled, makes the IDE subsystem use 64bit sector addresses. - Default is 32bit. - - NETWORK Support (PCI): CONFIG_E1000_SPI Utility code for direct access to the SPI bus on Intel 8257x. @@ -826,9 +773,6 @@ The following options need to be configured: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). - CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the - txfilltuning field in the EHCI controller on reset. - CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 HW module registers. @@ -902,13 +846,6 @@ The following options need to be configured: the appropriate value in Hz. - MMC Support: - The MMC controller on the Intel PXA is supported. To - enable this define CONFIG_MMC. The MMC can be - accessed from the boot prompt by mapping the device - to physical memory similar to flash. Command line is - enabled with CONFIG_CMD_MMC. The MMC driver also works with - the FAT fs. This is enabled with CONFIG_CMD_FAT. - CONFIG_SH_MMCIF Support for Renesas on-chip MMCIF controller @@ -1354,11 +1291,6 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CONFIG_SYS_SPD_BUS_NUM - - If defined, then this indicates the I2C bus number for DDR SPD. - If not defined, then U-Boot assumes that SPD is on I2C bus 0. - CONFIG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. @@ -1398,10 +1330,6 @@ The following options need to be configured: Enables support for FPGA family. (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) - CONFIG_FPGA_COUNT - - Specify the number of FPGA devices to support. - CONFIG_SYS_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. @@ -1570,20 +1498,6 @@ The following options need to be configured: overwriting the architecture dependent default settings. -- Frame Buffer Address: - CONFIG_FB_ADDR - - Define CONFIG_FB_ADDR if you want to use specific - address for frame buffer. This is typically the case - when using a graphics controller has separate video - memory. U-Boot will then place the frame buffer at - the given address instead of dynamically reserving it - in system RAM by calling lcd_setmem(), which grabs - the memory for the frame buffer depending on the - configured panel size. - - Please see board_init_f function. - - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX @@ -1658,36 +1572,6 @@ The following options need to be configured: CONFIG_SPL Enable building of SPL globally. - CONFIG_SPL_MAX_FOOTPRINT - Maximum size in memory allocated to the SPL, BSS included. - When defined, the linker checks that the actual memory - used by SPL from _start to __bss_end does not exceed it. - CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE - must not be both defined at the same time. - - CONFIG_SPL_MAX_SIZE - Maximum size of the SPL image (text, data, rodata, and - linker lists sections), BSS excluded. - When defined, the linker checks that the actual size does - not exceed it. - - CONFIG_SPL_RELOC_TEXT_BASE - Address to relocate to. If unspecified, this is equal to - CONFIG_SPL_TEXT_BASE (i.e. no relocation is done). - - CONFIG_SPL_BSS_START_ADDR - Link address for the BSS within the SPL binary. - - CONFIG_SPL_BSS_MAX_SIZE - Maximum size in memory allocated to the SPL BSS. - When defined, the linker checks that the actual memory used - by SPL from __bss_start to __bss_end does not exceed it. - CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE - must not be both defined at the same time. - - CONFIG_SPL_STACK - Adress of the start of the stack SPL will use - CONFIG_SPL_PANIC_ON_RAW_IMAGE When defined, SPL will panic() if the image it has loaded does not have a signature. @@ -1698,65 +1582,20 @@ The following options need to be configured: consider that a completely unreadable NAND block is bad, and thus should be skipped silently. - CONFIG_SPL_RELOC_STACK - Adress of the start of the stack SPL will use after - relocation. If unspecified, this is equal to - CONFIG_SPL_STACK. - - CONFIG_SYS_SPL_MALLOC_START - Starting address of the malloc pool used in SPL. - When this option is set the full malloc is used in SPL and - it is set up by spl_init() and before that, the simple malloc() - can be used if CONFIG_SYS_MALLOC_F is defined. - - CONFIG_SYS_SPL_MALLOC_SIZE - The size of the malloc pool used in SPL. - CONFIG_SPL_DISPLAY_PRINT For ARM, enable an optional function to print more information about the running system. - CONFIG_SPL_INIT_MINIMAL - Arch init code should be built for a very small image - - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS - Sector and number of sectors to load kernel argument - parameters from when MMC is being used in raw mode - (for falcon mode) - - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - Filename to read to load U-Boot when reading from filesystem - - CONFIG_SPL_FS_LOAD_KERNEL_NAME - Filename to read to load kernel uImage when reading - from filesystem (for Falcon mode) - - CONFIG_SPL_FS_LOAD_ARGS_NAME - Filename to read to load kernel argument parameters - when reading from filesystem (for Falcon mode) - CONFIG_SPL_MPC83XX_WAIT_FOR_NAND Set this for NAND SPL on PPC mpc83xx targets, so that start.S waits for the rest of the SPL to load before continuing (the hardware starts execution after just loading the first page rather than the full 4K). - CONFIG_SPL_SKIP_RELOCATE - Avoid SPL relocation - CONFIG_SPL_UBI Support for a lightweight UBI (fastmap) scanner and loader - CONFIG_SPL_NAND_RAW_ONLY - Support to boot only raw u-boot.bin images. Use this only - if you need to save space. - - CONFIG_SPL_COMMON_INIT_DDR - Set for common ddr init with serial presence detect in - SPL binary. - CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, @@ -1781,35 +1620,12 @@ The following options need to be configured: CONFIG_SPL_RAM_DEVICE Support for running image already present in ram, in SPL binary - CONFIG_SPL_PAD_TO - Image offset to which the SPL should be padded before appending - the SPL payload. By default, this is defined as - CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. - CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL - payload without any padding, or >= CONFIG_SPL_MAX_SIZE. - - CONFIG_SPL_TARGET - Final target image containing SPL and payload. Some SPLs - use an arch-specific makefile fragment instead, for - example if more than one image needs to be produced. - CONFIG_SPL_FIT_PRINT Printing information about a FIT image adds quite a bit of code to SPL. So this is normally disabled in SPL. Use this option to re-enable it. This will affect the output of the bootm command when booting a FIT image. -- TPL framework - CONFIG_TPL - Enable building of TPL globally. - - CONFIG_TPL_PAD_TO - Image offset to which the TPL should be padded before appending - the TPL payload. By default, this is defined as - CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. - CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL - payload without any padding, or >= CONFIG_SPL_MAX_SIZE. - - Interrupt support (PPC): There are common interrupt_init() and timer_interrupt() @@ -1853,16 +1669,6 @@ Configuration Settings: - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to prompt for user input. -- CONFIG_SYS_CBSIZE: Buffer size for input from the Console - -- CONFIG_SYS_PBSIZE: Buffer size for Console output - -- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands - -- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to - the application (usually a Linux kernel) when it is - booted - - CONFIG_SYS_BAUDRATE_TABLE: List of legal baudrate settings for this board. @@ -1909,7 +1715,7 @@ Configuration Settings: - CONFIG_SYS_MALLOC_SIMPLE Provides a simple and small malloc() and calloc() for those boards which do not use the full malloc in SPL (which is - enabled with CONFIG_SYS_SPL_MALLOC_START). + enabled with CONFIG_SYS_SPL_MALLOC). - CONFIG_SYS_NONCACHED_MEMORY: Size of non-cached memory area. This area of memory will be @@ -1930,12 +1736,6 @@ Configuration Settings: Non-cached memory is only supported on 32-bit ARM at present. -- CONFIG_SYS_BOOTM_LEN: - Normally compressed uImages are limited to an - uncompressed size of 8 MBytes. If this is not enough, - you can define CONFIG_SYS_BOOTM_LEN in your board config file - to adjust this setting to your needs. - - CONFIG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by @@ -1948,11 +1748,6 @@ Configuration Settings: CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead. -- CONFIG_SYS_BOOT_RAMDISK_HIGH: - Enable initrd_high functionality. If defined then the - initrd_high feature is enabled and the bootm ramdisk subcommand - is enabled. - - CONFIG_SYS_BOOT_GET_CMDLINE: Enables allocating and saving kernel cmdline in space between "bootm_low" and "bootm_low" + BOOTMAPSZ. @@ -2033,14 +1828,6 @@ Configuration Settings: while unprotecting/erasing/programming. Please only enable this option if you really know what you are doing. -- CONFIG_ENV_MAX_ENTRIES - - Maximum number of entries in the hash table that is used - internally to store the environment settings. The default - setting is supposed to be generous and should work in most - cases. This setting can be used to tune behaviour; see - lib/hashtable.c for details. - - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when @@ -2186,10 +1973,6 @@ Low Level (hardware related) configuration options: used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL"). -- CONFIG_SYS_CCSR_DO_NOT_RELOCATE: - If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be - forced to a value that ensures that CCSR is not relocated. - - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx systems only] @@ -2207,24 +1990,6 @@ Low Level (hardware related) configuration options: U-Boot uses the following memory types: - MPC8xx: IMMR (internal memory of the CPU) -- CONFIG_SYS_GBL_DATA_OFFSET: - - Offset of the initial data structure in the memory - area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually - CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial - data is located at the end of the available space - (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE - - GENERATED_GBL_DATA_SIZE), and the initial stack is just - below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR + - CONFIG_SYS_GBL_DATA_OFFSET) downward. - - Note: - On the MPC824X (or other systems that use the data - cache for initial memory) the address chosen for - CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must - point to an otherwise UNUSED address space between - the top of RAM and the start of the PCI space. - - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27) - CONFIG_SYS_OR_TIMING_SDRAM: @@ -2278,12 +2043,6 @@ Low Level (hardware related) configuration options: one, specify here. Note that the value must resolve to something your driver can deal with. -- CONFIG_SYS_DDR_RAW_TIMING - Get DDR timing information from other than SPD. Common with - soldered DDR chips onboard without SPD. DDR raw timing - parameters are extracted from datasheet and hard-coded into - header files or board specific files. - - CONFIG_FSL_DDR_INTERACTIVE Enable interactive DDR debugging. See doc/README.fsl-ddr. @@ -2293,10 +2052,6 @@ Low Level (hardware related) configuration options: - CONFIG_FSL_DDR_BIST Enable built-in memory test for Freescale DDR controllers. -- CONFIG_SYS_83XX_DDR_USES_CS0 - Only for 83xx systems. If specified, then DDR should - be configured using CS0 and CS1 instead of CS2 and CS3. - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't @@ -2342,11 +2097,6 @@ Low Level (hardware related) configuration options: proper). Code that needs stage-specific behavior should check this. -- CONFIG_SYS_MPC85XX_NO_RESETVEC - Only for 85xx systems. If this variable is specified, the section - .resetvec is not kept and the section .bootpg is placed in the - previous 4k of the .text section. - - CONFIG_ARCH_MAP_SYSMEM Generally U-Boot (and in particular the md command) uses effective address. It is therefore not necessary to regard @@ -2578,6 +2328,7 @@ rarpboot- boot image via network using RARP/TFTP protocol diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' loads - load S-Record file over serial line loadb - load binary file over serial line (kermit mode) +loadm - load binary blob from source address to destination address md - memory display mm - memory modify (auto-incrementing) nm - memory modify (constant address) diff --git a/arch/Kconfig b/arch/Kconfig index 12de8a11650dd3b267df523f611d5d07089be44c..6495e780fec98715774721c93edc7ba9515c2e8f 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -8,9 +8,6 @@ config CREATE_ARCH_SYMLINK config HAVE_ARCH_IOREMAP bool -config NEEDS_MANUAL_RELOC - bool - config SYS_CACHE_SHIFT_4 bool @@ -76,9 +73,12 @@ config M68K config MICROBLAZE bool "MicroBlaze architecture" - select NEEDS_MANUAL_RELOC select SUPPORT_OF_CONTROL - imply CMD_IRQ + imply CMD_TIMER + imply SPL_REGMAP if SPL + imply SPL_TIMER if SPL + imply TIMER + imply XILINX_TIMER config MIPS bool "MIPS architecture" @@ -135,6 +135,7 @@ config SANDBOX select BZIP2 select CMD_POWEROFF select DM + select DM_FUZZING_ENGINE select DM_GPIO select DM_I2C select DM_KEYBOARD @@ -170,6 +171,7 @@ config SANDBOX imply CRC32_VERIFY imply FAT_WRITE imply FIRMWARE + imply FUZZING_ENGINE_SANDBOX imply HASH_VERIFY imply LZMA imply TEE @@ -371,6 +373,9 @@ config SYS_IMMR default 0xF0000000 if ARCH_MPC8313 default 0xE0000000 if MPC83xx && !ARCH_MPC8313 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ + ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ + ARCH_P2020 default SYS_CCSRBAR_DEFAULT help Address for the Internal Memory-Mapped Registers (IMMR) window used @@ -446,4 +451,32 @@ source "arch/x86/Kconfig" source "arch/xtensa/Kconfig" source "arch/riscv/Kconfig" +if ARM || M68K || PPC + +source "arch/Kconfig.nxp" + +endif + source "board/keymile/Kconfig" + +if MIPS || MICROBLAZE + +choice + prompt "Endianness selection" + help + Some MIPS boards can be configured for either little or big endian + byte order. These modes require different U-Boot images. In general there + is one preferred byteorder for a particular system but some systems are + just as commonly used in the one or the other endianness. + +config SYS_BIG_ENDIAN + bool "Big endian" + depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE + +config SYS_LITTLE_ENDIAN + bool "Little endian" + depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE + +endchoice + +endif diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp new file mode 100644 index 0000000000000000000000000000000000000000..d3ebbff43be18bee3c48c6d2b253d813297b8c89 --- /dev/null +++ b/arch/Kconfig.nxp @@ -0,0 +1,241 @@ +config NXP_ESBC + bool "NXP ESBC (secure boot) functionality" + help + Enable Freescale Secure Boot feature. Normally selected by defconfig. + If unsure, do not change. + +menu "Chain of trust / secure boot options" + depends on !FIT_SIGNATURE && NXP_ESBC + +config CHAIN_OF_TRUST + select FSL_CAAM + select ARCH_MISC_INIT + select FSL_SEC_MON + select SPL_BOARD_INIT if (ARM && SPL) + select SPL_HASH if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + select ENV_IS_NOWHERE + select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT + select CMD_EXT4 if ARM + select CMD_EXT4_WRITE if ARM + imply CMD_BLOB + imply CMD_HASH if ARM + def_bool y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) + +config ESBC_HDR_LS + bool + +config ESBC_ADDR_64BIT + def_bool y + depends on ESBC_HDR_LS && FSL_LAYERSCAPE + help + For Layerscape based platforms, ESBC image Address in Header is 64bit. + +config SYS_FSL_SFP_BE + def_bool y + depends on PPC || FSL_LSCH2 || ARCH_LS1021A + +config SYS_FSL_SFP_LE + def_bool y + depends on !SYS_FSL_SFP_BE + +choice + prompt "SFP IP revision" + default SYS_FSL_SFP_VER_3_0 if PPC + default SYS_FSL_SFP_VER_3_4 + +config SYS_FSL_SFP_VER_3_0 + bool "SFP version 3.0" + +config SYS_FSL_SFP_VER_3_2 + bool "SFP version 3.2" + +config SYS_FSL_SFP_VER_3_4 + bool "SFP version 3.4" + +endchoice + +config SPL_UBOOT_KEY_HASH + string "Non-SRK key hash for U-Boot public/private key pair" + depends on SPL + default "" + help + Set the key hash for U-Boot here if public/private key pair used to + sign U-boot are different from the SRK hash put in the fuse. Example + of a key hash is + 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. + Otherwise leave this empty. + +if PPC + +config BOOTSCRIPT_COPY_RAM + bool "Secure boot copies boot script to RAM" + help + On systems that support chain of trust booting, a number of addresses + are required to set variables that are used in the copying and then + verification of different parts of the system. If enabled, the subsequent + options are for what location to use in each step. + +config BS_ADDR_DEVICE + hex "Address in RAM for bs_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_SIZE + hex "The size of bs_size which is the amount read from bs_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_ADDR_RAM + hex "Address in RAM for bs_ram" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_ADDR_DEVICE + hex "Address in RAM for bs_hdr_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_SIZE + hex "The size of bs_hdr_size which is the amount read from bs_hdr_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_ADDR_RAM + hex "Address in RAM for bs_hdr_ram" + depends on BOOTSCRIPT_COPY_RAM + +config BOOTSCRIPT_HDR_ADDR + hex "CONFIG_BOOTSCRIPT_HDR_ADDR" + default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM + +endif + +config SYS_FSL_SRK_LE + def_bool y + depends on ARM + +config KEY_REVOCATION + def_bool y + +endmenu + +comment "Other functionality shared between NXP SoCs" + +config DEEP_SLEEP + bool "Enable SoC deep sleep feature" + depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A + default y + help + Indicates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + +config LAYERSCAPE_NS_ACCESS + bool "Layerscape non-secure access support" + depends on ARCH_LS1021A || FSL_LSCH2 + +config PCIE1 + bool "PCIe controller #1" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config PCIE2 + bool "PCIe controller #2" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config PCIE3 + bool "PCIe controller #3" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config PCIE4 + bool "PCIe controller #4" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config FSL_USE_PCA9547_MUX + bool "Enable PCA9547 I2C Mux on Freescale boards" + depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + help + This option enables the PCA9547 I2C mux on Freescale boards. + +config VID + bool "Enable Freescale VID" + depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C) + help + This option enables setting core voltage based on individual + values saved in SoC fuses. + +config SPL_VID + bool "Enable Freescale VID in SPL" + depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C) + help + This option enables setting core voltage based on individual + values saved in SoC fuses, in SPL. + +if VID || SPL_VID + +config VID_FLS_ENV + string "Environment variable for overriding VDD" + help + This option allows for specifying the environment variable + to check to override VDD information. + +config VOL_MONITOR_INA220 + bool "Enable the INA220 voltage monitor read" + help + This option enables INA220 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_IR36021_READ + bool "Enable the IR36021 voltage monitor read" + help + This option enables IR36021 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_IR36021_SET + bool "Enable the IR36021 voltage monitor set" + help + This option enables IR36021 voltage monitor set + functionality. It is used by the common VID driver. + +config VOL_MONITOR_LTC3882_READ + bool "Enable the LTC3882 voltage monitor read" + help + This option enables LTC3882 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_LTC3882_SET + bool "Enable the LTC3882 voltage monitor set" + help + This option enables LTC3882 voltage monitor set + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_READ + bool "Enable the ISL68233 voltage monitor read" + help + This option enables ISL68233 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_SET + bool "Enable the ISL68233 voltage monitor set" + help + This option enables ISL68233 voltage monitor set + functionality. It is used by the common VID driver. + +endif + +config FSL_QIXIS + bool "Enable QIXIS support" + depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + +config QIXIS_I2C_ACCESS + bool "Access to QIXIS is over i2c" + depends on FSL_QIXIS + default y + +config HAS_FSL_DR_USB + def_bool y + depends on USB_EHCI_HCD && PPC diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds index e12145c76849e894efb7b4c15506c5935ebad997..9f2973da6598587410e7ac80bacb4c5cc4696330 100644 --- a/arch/arc/cpu/u-boot.lds +++ b/arch/arc/cpu/u-boot.lds @@ -39,8 +39,8 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h index 46e94be141b937ca276bf094e85a69eae85c98a6..afdfcaa78b57693e736af71ade1c8197332e1db7 100644 --- a/arch/arc/include/asm/config.h +++ b/arch/arc/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef __ASM_ARC_CONFIG_H_ #define __ASM_ARC_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif /*__ASM_ARC_CONFIG_H_ */ diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 016ae85be23b687ebf8d7ba130e84f950daa2e47..9f5547e552d830b335b44aafb925f3256f899d04 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -7,6 +7,7 @@ #include #include #include +#include ENTRY(_start) /* Setup interrupt vector base that matches "__text_start" */ @@ -86,7 +87,7 @@ ENTRY(_start) #endif /* Establish C runtime stack and frame */ - mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %sp, SYS_INIT_SP_ADDR mov %fp, %sp /* Allocate reserved area from current top of stack */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9898c7d68e1bf3c9d9b10abb6c752c564d8d53c7..163e94fec0c14c11913ebf59f8e7b4b0fba4afa1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -330,20 +330,6 @@ config CPU_V7R select SYS_ARM_MPU select SYS_CACHE_SHIFT_6 -config CPU_PXA - bool - select SYS_CACHE_SHIFT_5 - imply SYS_ARM_MMU - -config CPU_PXA27X - bool - select CPU_PXA - -config CPU_SA1100 - bool - select SYS_CACHE_SHIFT_5 - imply SYS_ARM_MMU - config SYS_CPU default "arm720t" if CPU_ARM720T default "arm920t" if CPU_ARM920T @@ -354,8 +340,6 @@ config SYS_CPU default "armv7" if CPU_V7A default "armv7" if CPU_V7R default "armv7m" if CPU_V7M - default "pxa" if CPU_PXA - default "sa1100" if CPU_SA1100 default "armv8" if ARM64 config SYS_ARM_ARCH @@ -369,14 +353,11 @@ config SYS_ARM_ARCH default 7 if CPU_V7A default 7 if CPU_V7M default 7 if CPU_V7R - default 5 if CPU_PXA - default 4 if CPU_SA1100 default 8 if ARM64 choice prompt "Select the ARM data write cache policy" - default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ - CPU_PXA || RZA1 + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1 default SYS_ARM_CACHE_WRITEBACK config SYS_ARM_CACHE_WRITEBACK @@ -609,6 +590,9 @@ config ARM64_SUPPORT_AARCH32 help This ARM64 system supports AArch32 execution state. +config S5P + def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX + choice prompt "Target select" default TARGET_HIKEY @@ -718,6 +702,11 @@ config ARCH_BCMSTB This enables support for Broadcom ARM-based set-top box chipsets, including the 7445 family of chips. +config ARCH_BCMBCA + bool "Broadcom broadband chip family" + select DM + select OF_CONTROL + config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" select CPU_V7A @@ -991,11 +980,6 @@ config ARCH_MX6 imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS -if ARCH_MX6 -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" -endif - config ARCH_MX5 bool "Freescale MX5" select BOARD_EARLY_INIT_F @@ -1116,7 +1100,6 @@ config ARCH_SOCFPGA select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT - select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 select SPL_SERIAL @@ -1347,6 +1330,12 @@ config ARCH_VEXPRESS64 select ENV_IS_IN_FLASH if MTD imply DISTRO_DEFAULTS +config TARGET_CORSTONE1000 + bool "Support Corstone1000 Platform" + select ARM64 + select PL01X_SERIAL + select DM + config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" select ARM64 @@ -1923,7 +1912,7 @@ config ARCH_STM32 imply CMD_DM config ARCH_STI - bool "Support STMicrolectronics SoCs" + bool "Support STMicroelectronics SoCs" select BLK select CPU_V7A select DM @@ -1951,7 +1940,6 @@ config ARCH_STM32MP select OF_SYSTEM_SETUP select PINCTRL select REGMAP - select SUPPORT_SPL select SYSCON select SYSRESET select SYS_THUMB_BUILD @@ -2085,6 +2073,12 @@ config TARGET_XENGUEST_ARM64 select SSCANF imply OF_HAS_PRIOR_STAGE +config ARCH_GXP + bool "Support HPE GXP SoCs" + select DM + select OF_CONTROL + imply CMD_DM + endchoice config SUPPORT_PASSING_ATAGS @@ -2187,12 +2181,16 @@ source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-bcm283x/Kconfig" +source "arch/arm/mach-bcmbca/Kconfig" + source "arch/arm/mach-bcmstb/Kconfig" source "arch/arm/mach-davinci/Kconfig" source "arch/arm/mach-exynos/Kconfig" +source "arch/arm/mach-hpe/gxp/Kconfig" + source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-integrator/Kconfig" @@ -2294,7 +2292,7 @@ source "arch/arm/mach-nexell/Kconfig" source "arch/arm/mach-npcm/Kconfig" source "board/armltd/total_compute/Kconfig" - +source "board/armltd/corstone1000/Kconfig" source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" source "board/Marvell/octeontx/Kconfig" @@ -2334,6 +2332,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" source "board/st/stv0991/Kconfig" @@ -2348,8 +2347,3 @@ source "board/xen/xenguest_arm64/Kconfig" source "arch/arm/Kconfig.debug" endmenu - -config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK - default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 85c23bcf775b7607278a58ff75777565d6e617f0..a37603035d8a5b7ed9cc62493e592ab547c1664b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -10,8 +10,6 @@ arch-$(CONFIG_CPU_ARM720T) =-march=armv4 arch-$(CONFIG_CPU_ARM920T) =-march=armv4t arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te -arch-$(CONFIG_CPU_SA1100) =-march=armv4 -arch-$(CONFIG_CPU_PXA) = arch-$(CONFIG_CPU_ARM1136) =-march=armv5t arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ @@ -40,8 +38,6 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM920T) = tune-$(CONFIG_CPU_ARM926EJS) = tune-$(CONFIG_CPU_ARM946ES) = -tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 -tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a @@ -59,9 +55,11 @@ machine-$(CONFIG_ARCH_APPLE) += apple machine-$(CONFIG_ARCH_ASPEED) += aspeed machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_BCM283X) += bcm283x +machine-$(CONFIG_ARCH_BCMBCA) += bcmbca machine-$(CONFIG_ARCH_BCMSTB) += bcmstb machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_EXYNOS) += exynos +machine-$(CONFIG_ARCH_GXP) += hpe machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx machine-$(CONFIG_ARCH_K3) += k3 @@ -103,8 +101,8 @@ libs-y += $(machdirs) head-y := arch/arm/cpu/$(CPU)/start.o ifeq ($(CONFIG_SPL_BUILD),y) -ifneq ($(CONFIG_SPL_START_S_PATH),) -head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o +ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs") +head-y := arch/arm/cpu/arm926ejs/mxs/start.o endif endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index b107b1af27ac07571144532eda80fb86c9b223c1..b3548ce2439242a66bc62a7a39359fa336a283f2 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -141,11 +141,11 @@ endif # limit ourselves to the sections we want in the .bin. ifdef CONFIG_ARM64 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \ - -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \ + -j __u_boot_list -j .rela.dyn -j .got -j .got.plt \ -j .binman_sym_table -j .text_rest else OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \ - -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \ + -j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \ -j .binman_sym_table -j .text_rest endif diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index adec2c8ada676b88dda3f4962d14cbe664f7ad4a..61982e38a1d4a017873b95ce69e7da262bedaa0d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -21,6 +21,7 @@ #include #include #include +#include /* ************************************************************************* @@ -44,7 +45,7 @@ reset: * it point to the end of OCRAM if the SP is zero. */ cmp sp, #0x00000000 - ldreq sp, =CONFIG_SYS_INIT_SP_ADDR + ldreq sp, =SYS_INIT_SP_ADDR /* * Store all registers on old stack pointer, this will allow us later to diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds index 9a000ac5d385e4394854563902db26dcf12d6864..c108736811578f4a665873b12327807ff7b8df6b 100644 --- a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds @@ -29,8 +29,8 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .sram . = ALIGN(4); diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index ba4b374a8bd9a5315bf3065e5e7715a72458d50c..3c8c07fe016401dbff0c1cdb94f80b80cb88b705 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -13,6 +13,7 @@ #include #include #include +#include .pushsection .text.s_init, "ax" WEAK(s_init) @@ -28,7 +29,7 @@ WEAK(lowlevel_init) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr sp, =CONFIG_SPL_STACK #else - ldr sp, =CONFIG_SYS_INIT_SP_ADDR + ldr sp, =SYS_INIT_SP_ADDR #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_DM diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index c496e6439199125cddb3a5c0d04578c7a3494aff..a901360fa7d8e6db0716288fd26f6be9b4c5a598 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -41,12 +41,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. - config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index bfe02389cd9403480c09aba42ffb0324d75cdd88..0985420fe5c8e92f41a33e9b19ca634f2f45060e 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -3,14 +3,13 @@ # Copyright (C) 2009 Samsung Electronics # Minkyu Kang +obj-$(CONFIG_PWM_S5P) += pwm.o ifdef CONFIG_ARCH_NEXELL -obj-$(CONFIG_PWM_NX) += pwm.o obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o else obj-y += cpu_info.o ifndef CONFIG_SPL_BUILD obj-y += timer.o obj-y += sromc.o -obj-$(CONFIG_PWM) += pwm.o endif endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 37036128a785454f957f9a5553d2b18b26a493b6..4f6327fe3ab734b9fda979f294f62e586e775f13 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -17,6 +17,7 @@ #include #include #include +#include /************************************************************************* * @@ -254,7 +255,7 @@ ENTRY(cpu_init_cp15) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else - ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0, =(SYS_INIT_SP_ADDR) #endif bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ mov sp, r0 diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S index 218ac70f328848b361de7726173c3863d16ca91a..5733eaa15c0b99f0b34248453560a37d9dcbf0f9 100644 --- a/arch/arm/cpu/armv7/stv0991/lowlevel.S +++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2014 stmicroelectronics + * (C) Copyright 2014 STMicroelectronics */ #include diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds index 942c29fc959dfaac8ac0105307fe55012b715756..306a4ddf3cd2973c59b2eaa334765b168e1951c0 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -38,8 +38,8 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .sram . = ALIGN(4); diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 09f3f50fa22f34fe42b9500cd13a8f076f88fbc7..1305238c9d26bbb2addeab0eddea7968daa6ae66 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -76,6 +76,7 @@ config ARMV8_SEC_FIRMWARE_SUPPORT config SPL_ARMV8_SEC_FIRMWARE_SUPPORT bool "Enable ARMv8 secure monitor firmware framework support for SPL" + depends on SPL select SPL_FIT select SPL_OF_LIBFDT help @@ -83,6 +84,7 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT config SPL_RECOVER_DATA_SECTION bool "save/restore SPL data section" + depends on SPL help Say Y here to save SPL data section for cold boot, and restore at warm boot in SPL phase. @@ -185,4 +187,19 @@ config ARMV8_EA_EL3_FIRST Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. +menuconfig ARMV8_CRYPTO + bool "ARM64 Accelerated Cryptographic Algorithms" + +if ARMV8_CRYPTO + +config ARMV8_CE_SHA1 + bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)" + default y if SHA1 + +config ARMV8_CE_SHA256 + bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)" + default y if SHA256 + +endif + endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 85fe0475c86915ab540c60c3d1fbc541cc3ecec8..2e4bf9e038c7af921cb8413e08ad0e1615fdd180 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -44,3 +44,5 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ +obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o +obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 80a1642447d60c8fd46a785b451cc8da720666c4..602b624dca529fa5e4277ecd798a8080987d28e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -26,6 +26,7 @@ config ARCH_LS1012A config ARCH_LS1028A bool select ARMV8_SET_SMPEN + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 @@ -138,6 +139,7 @@ config ARCH_LS1088A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 @@ -187,6 +189,7 @@ config ARCH_LS2080A select ARM_ERRATA_828024 select ARM_ERRATA_829520 select ARM_ERRATA_833471 + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 @@ -239,6 +242,7 @@ config ARCH_LS2080A config ARCH_LX2162A bool select ARMV8_SET_SMPEN + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_DDR_BIST select FSL_DDR_INTERACTIVE select FSL_LAYERSCAPE @@ -277,6 +281,7 @@ config ARCH_LX2162A config ARCH_LX2160A bool select ARMV8_SET_SMPEN + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_DDR_BIST select FSL_DDR_INTERACTIVE select FSL_LAYERSCAPE @@ -456,11 +461,6 @@ config EMC2305 Enable the EMC2305 fan controller for configuration of fan speed. -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature - config QSPI_AHB_INIT bool "Init the QSPI AHB bus" help @@ -511,6 +511,11 @@ config DP_DDR_CTRL depends on SYS_FSL_HAS_DP_DDR default 2 if ARCH_LS2080A +config DP_DDR_DIMM_SLOTS_PER_CTLR + int + depends on SYS_FSL_HAS_DP_DDR + default 1 if ARCH_LS2080A + config DP_DDR_NUM_CTRLS int depends on SYS_FSL_HAS_DP_DDR @@ -701,9 +706,6 @@ config SYS_FSL_HAS_RGMII bool depends on SYS_FSL_EC1 || SYS_FSL_EC2 -config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A - config HAS_FSL_XHCI_USB bool help diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 570105a75ed1b87bde174a1a59fd4b2c059fef29..840e6d412b30754a23cdd5f9b8ccd369bb33aad2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -29,8 +29,8 @@ void get_sys_info(struct sys_info *sys_info) * mux 2 clock for LS1043A/LS1046A. */ #if defined(CONFIG_SYS_DPAA_FMAN) || \ - defined(CONFIG_TARGET_LS1046ARDB) || \ - defined(CONFIG_TARGET_LS1043ARDB) + defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1043A) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -129,13 +129,13 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) +#if defined(CONFIG_ARCH_LS1046A) || defined(CONFIG_ARCH_LS1043A) rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { case 1: sys_info->freq_cga_m2 = freq_c_pll[1]; break; -#if defined(CONFIG_TARGET_LS1046ARDB) +#if defined(CONFIG_ARCH_LS1046A) case 2: sys_info->freq_cga_m2 = freq_c_pll[1] / 2; break; @@ -143,7 +143,7 @@ void get_sys_info(struct sys_info *sys_info) case 3: sys_info->freq_cga_m2 = freq_c_pll[1] / 3; break; -#if defined(CONFIG_TARGET_LS1046ARDB) +#if defined(CONFIG_ARCH_LS1046A) case 6: sys_info->freq_cga_m2 = freq_c_pll[0] / 2; break; diff --git a/arch/arm/cpu/armv8/sha1_ce_core.S b/arch/arm/cpu/armv8/sha1_ce_core.S new file mode 100644 index 0000000000000000000000000000000000000000..fbf2714206edc6e6c47317e038148d2f34201422 --- /dev/null +++ b/arch/arm/cpu/armv8/sha1_ce_core.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2014 Linaro Ltd + * Copyright (C) 2022 Linaro Ltd + */ + +#include +#include +#include +#include + + .text + .arch armv8-a+crypto + + k0 .req v0 + k1 .req v1 + k2 .req v2 + k3 .req v3 + + t0 .req v4 + t1 .req v5 + + dga .req q6 + dgav .req v6 + dgb .req s7 + dgbv .req v7 + + dg0q .req q12 + dg0s .req s12 + dg0v .req v12 + dg1s .req s13 + dg1v .req v13 + dg2s .req s14 + + .macro add_only, op, ev, rc, s0, dg1 + .ifc \ev, ev + add t1.4s, v\s0\().4s, \rc\().4s + sha1h dg2s, dg0s + .ifnb \dg1 + sha1\op dg0q, \dg1, t0.4s + .else + sha1\op dg0q, dg1s, t0.4s + .endif + .else + .ifnb \s0 + add t0.4s, v\s0\().4s, \rc\().4s + .endif + sha1h dg1s, dg0s + sha1\op dg0q, dg2s, t1.4s + .endif + .endm + + .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 + sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s + add_only \op, \ev, \rc, \s1, \dg1 + sha1su1 v\s0\().4s, v\s3\().4s + .endm + + .macro loadrc, k, val, tmp + movz \tmp, :abs_g0_nc:\val + movk \tmp, :abs_g1:\val + dup \k, \tmp + .endm + + /* + * void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, + * uint32_t blocks) + */ +ENTRY(sha1_armv8_ce_process) + /* load round constants */ + loadrc k0.4s, 0x5a827999, w6 + loadrc k1.4s, 0x6ed9eba1, w6 + loadrc k2.4s, 0x8f1bbcdc, w6 + loadrc k3.4s, 0xca62c1d6, w6 + + /* load state (4+1 digest states) */ + ld1 {dgav.4s}, [x0] + ldr dgb, [x0, #16] + + /* load input (64 bytes into v8->v11 16B vectors) */ +0: ld1 {v8.4s-v11.4s}, [x1], #64 + sub w2, w2, #1 +#if __BYTE_ORDER == __LITTLE_ENDIAN + rev32 v8.16b, v8.16b + rev32 v9.16b, v9.16b + rev32 v10.16b, v10.16b + rev32 v11.16b, v11.16b +#endif + +1: add t0.4s, v8.4s, k0.4s + mov dg0v.16b, dgav.16b + + add_update c, ev, k0, 8, 9, 10, 11, dgb + add_update c, od, k0, 9, 10, 11, 8 + add_update c, ev, k0, 10, 11, 8, 9 + add_update c, od, k0, 11, 8, 9, 10 + add_update c, ev, k1, 8, 9, 10, 11 + + add_update p, od, k1, 9, 10, 11, 8 + add_update p, ev, k1, 10, 11, 8, 9 + add_update p, od, k1, 11, 8, 9, 10 + add_update p, ev, k1, 8, 9, 10, 11 + add_update p, od, k2, 9, 10, 11, 8 + + add_update m, ev, k2, 10, 11, 8, 9 + add_update m, od, k2, 11, 8, 9, 10 + add_update m, ev, k2, 8, 9, 10, 11 + add_update m, od, k2, 9, 10, 11, 8 + add_update m, ev, k3, 10, 11, 8, 9 + + add_update p, od, k3, 11, 8, 9, 10 + add_only p, ev, k3, 9 + add_only p, od, k3, 10 + add_only p, ev, k3, 11 + add_only p, od + + /* update state */ + add dgbv.2s, dgbv.2s, dg1v.2s + add dgav.4s, dgav.4s, dg0v.4s + + /* loop on next block? */ + cbz w2, 2f + b 0b + + /* store new state */ +2: st1 {dgav.4s}, [x0] + str dgb, [x0, #16] + mov w0, w2 + ret +ENDPROC(sha1_armv8_ce_process) diff --git a/arch/arm/cpu/armv8/sha1_ce_glue.c b/arch/arm/cpu/armv8/sha1_ce_glue.c new file mode 100644 index 0000000000000000000000000000000000000000..780b119a90bf47cb1a77f4cc881ca2e3e0823ded --- /dev/null +++ b/arch/arm/cpu/armv8/sha1_ce_glue.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha1_ce_glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2022 Linaro Ltd + */ + +#include +#include + +extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, + uint32_t blocks); + +void sha1_process(sha1_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + sha1_armv8_ce_process(ctx->state, data, blocks); +} diff --git a/arch/arm/cpu/armv8/sha256_ce_core.S b/arch/arm/cpu/armv8/sha256_ce_core.S new file mode 100644 index 0000000000000000000000000000000000000000..fbae3ca362bc1118123a90cda87b9a28518ca509 --- /dev/null +++ b/arch/arm/cpu/armv8/sha256_ce_core.S @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha256-ce-core.S - core SHA-256 transform using v8 Crypto Extensions + * + * Copyright (C) 2014 Linaro Ltd + * Copyright (C) 2022 Linaro Ltd + */ + + #include + #include + #include + #include + + .text + .arch armv8-a+crypto + + dga .req q20 + dgav .req v20 + dgb .req q21 + dgbv .req v21 + + t0 .req v22 + t1 .req v23 + + dg0q .req q24 + dg0v .req v24 + dg1q .req q25 + dg1v .req v25 + dg2q .req q26 + dg2v .req v26 + + .macro add_only, ev, rc, s0 + mov dg2v.16b, dg0v.16b + .ifeq \ev + add t1.4s, v\s0\().4s, \rc\().4s + sha256h dg0q, dg1q, t0.4s + sha256h2 dg1q, dg2q, t0.4s + .else + .ifnb \s0 + add t0.4s, v\s0\().4s, \rc\().4s + .endif + sha256h dg0q, dg1q, t1.4s + sha256h2 dg1q, dg2q, t1.4s + .endif + .endm + + .macro add_update, ev, rc, s0, s1, s2, s3 + sha256su0 v\s0\().4s, v\s1\().4s + add_only \ev, \rc, \s1 + sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s + .endm + + /* + * The SHA-256 round constants + */ + .align 4 +.Lsha2_rcon: + .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5 + .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5 + .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3 + .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174 + .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc + .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da + .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7 + .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967 + .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13 + .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85 + .word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3 + .word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070 + .word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5 + .word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3 + .word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208 + .word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 + + /* + * void sha256_armv8_ce_process(struct sha256_ce_state *sst, + * uint8_t const *src, uint32_t blocks) + */ +ENTRY(sha256_armv8_ce_process) + /* load round constants */ + adr x8, .Lsha2_rcon + ld1 { v0.4s- v3.4s}, [x8], #64 + ld1 { v4.4s- v7.4s}, [x8], #64 + ld1 { v8.4s-v11.4s}, [x8], #64 + ld1 {v12.4s-v15.4s}, [x8] + + /* load state */ + ldp dga, dgb, [x0] + + /* load input */ +0: ld1 {v16.4s-v19.4s}, [x1], #64 + sub w2, w2, #1 +#if __BYTE_ORDER == __LITTLE_ENDIAN + rev32 v16.16b, v16.16b + rev32 v17.16b, v17.16b + rev32 v18.16b, v18.16b + rev32 v19.16b, v19.16b +#endif + +1: add t0.4s, v16.4s, v0.4s + mov dg0v.16b, dgav.16b + mov dg1v.16b, dgbv.16b + + add_update 0, v1, 16, 17, 18, 19 + add_update 1, v2, 17, 18, 19, 16 + add_update 0, v3, 18, 19, 16, 17 + add_update 1, v4, 19, 16, 17, 18 + + add_update 0, v5, 16, 17, 18, 19 + add_update 1, v6, 17, 18, 19, 16 + add_update 0, v7, 18, 19, 16, 17 + add_update 1, v8, 19, 16, 17, 18 + + add_update 0, v9, 16, 17, 18, 19 + add_update 1, v10, 17, 18, 19, 16 + add_update 0, v11, 18, 19, 16, 17 + add_update 1, v12, 19, 16, 17, 18 + + add_only 0, v13, 17 + add_only 1, v14, 18 + add_only 0, v15, 19 + add_only 1 + + /* update state */ + add dgav.4s, dgav.4s, dg0v.4s + add dgbv.4s, dgbv.4s, dg1v.4s + + /* handled all input blocks? */ + cbnz w2, 0b + + /* store new state */ +3: stp dga, dgb, [x0] + ret +ENDPROC(sha256_armv8_ce_process) diff --git a/arch/arm/cpu/armv8/sha256_ce_glue.c b/arch/arm/cpu/armv8/sha256_ce_glue.c new file mode 100644 index 0000000000000000000000000000000000000000..67dd796c122d267709b0022abb924c881aa0fac2 --- /dev/null +++ b/arch/arm/cpu/armv8/sha256_ce_glue.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha256_ce_glue.c - SHA-256 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2022 Linaro Ltd + */ + +#include +#include + +extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src, + uint32_t blocks); + +void sha256_process(sha256_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + sha256_armv8_ce_process(ctx->state, data, blocks); +} diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index 730eb93dbc3bc355f884d67a186787b23b7008ed..7cb9d731246d0fe98b4d330d79c02a3daf9bd46e 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -23,7 +23,7 @@ SECTIONS { .text : { . = ALIGN(8); - *(.__image_copy_start) + __image_copy_start = .; CPUDIR/start.o (.text*) *(.text*) } >.sram @@ -46,9 +46,9 @@ SECTIONS } >.sram #endif - .u_boot_list : { + __u_boot_list : { . = ALIGN(8); - KEEP(*(SORT(.u_boot_list*))); + KEEP(*(SORT(__u_boot_list*))); } >.sram .image_copy_end : { diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 2554980595b14cf9a1f5b13db03f147f73048305..8fe4682dd2aed64bc80d06122f5cb1f0ee00aeea 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -109,8 +109,8 @@ SECTIONS . = .; . = ALIGN(8); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(8); diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile deleted file mode 100644 index 263d9ddb4a01741b3923949c31f2f652bb181542..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -extra-y = start.o - -obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o -obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o - -obj-y += cpuinfo.o -obj-y += timer.o -obj-y += usb.o -obj-y += relocate.o -obj-y += cache.o diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c deleted file mode 100644 index a2ec5e28c7dcef6236258f547909ced3eeb1eedf..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/cache.c +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Vasily Khoruzhick - */ - -#include -#include -#include -#include - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void invalidate_dcache_all(void) -{ - /* Flush/Invalidate I cache */ - asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0)); - /* Flush/Invalidate D cache */ - asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); -} - -void flush_dcache_all(void) -{ - return invalidate_dcache_all(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ - start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); - stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); - - while (start <= stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); - start += CONFIG_SYS_CACHELINE_SIZE; - } -} - -void flush_dcache_range(unsigned long start, unsigned long stop) -{ - return invalidate_dcache_range(start, stop); -} -#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ -void invalidate_dcache_all(void) -{ -} - -void flush_dcache_all(void) -{ -} -#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ - -/* - * Stub implementations for l2 cache operations - */ - -__weak void l2_cache_disable(void) {} - -#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) -__weak void invalidate_l2_cache(void) {} -#endif diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk deleted file mode 100644 index e7b183674a2c44680fc966e18d183ec052c1d77e..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger - -# -# !WARNING! -# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from -# really small OneNAND memories where the mmap'd window is only 1KiB big. The -# .text.0 contains only the bare minimum needed to load the real SPL into SRAM. -# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd, -# they are not discarded. -# - -#ifdef CONFIG_SPL_BUILD -OBJCOPYFLAGS += -j .text.0 -j .text.1 -#endif diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c deleted file mode 100644 index 0d9542f998e439124b2d283d412c2194212f1a62..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PXA CPU information display - * - * Copyright (C) 2011 Marek Vasut - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_CPU_PXA25X -#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) -#error "Init SP address must be set to 0xfffff800 for PXA250" -#endif -#endif - -#define CPU_MASK_PXA_PRODID 0x000003f0 -#define CPU_MASK_PXA_REVID 0x0000000f - -#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID) - -#define CPU_VALUE_PXA25X 0x100 -#define CPU_VALUE_PXA27X 0x110 - -static uint32_t pxa_get_cpuid(void) -{ - uint32_t cpuid; - asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); - return cpuid; -} - -int cpu_is_pxa25x(void) -{ - uint32_t id = pxa_get_cpuid(); - id &= CPU_MASK_PXA_PRODID; - return id == CPU_VALUE_PXA25X; -} - -int cpu_is_pxa27x(void) -{ - uint32_t id = pxa_get_cpuid(); - id &= CPU_MASK_PXA_PRODID; - return id == CPU_VALUE_PXA27X; -} - -int cpu_is_pxa27xm(void) -{ - uint32_t id = pxa_get_cpuid(); - return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) && - ((id & CPU_MASK_PXA_REVID) == 8); -} - -uint32_t pxa_get_cpu_revision(void) -{ - return pxa_get_cpuid() & CPU_MASK_PRODREV; -} - -#ifdef CONFIG_DISPLAY_CPUINFO -static const char *pxa25x_get_revision(void) -{ - static __maybe_unused const char * const revs_25x[] = { "A0" }; - static __maybe_unused const char * const revs_26x[] = { - "A0", "B0", "B1" - }; - static const char *unknown = "Unknown"; - uint32_t id; - - if (!cpu_is_pxa25x()) - return unknown; - - id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; - -/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */ -#ifdef CONFIG_CPU_PXA26X - switch (id) { - case 3: return revs_26x[0]; - case 5: return revs_26x[1]; - case 6: return revs_26x[2]; - } -#else - if (id == 6) - return revs_25x[0]; -#endif - return unknown; -} - -static const char *pxa27x_get_revision(void) -{ - static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" }; - static const char *unknown = "Unknown"; - uint32_t id; - - if (!cpu_is_pxa27x()) - return unknown; - - id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; - - if ((id == 5) || (id == 6) || (id > 8)) - return unknown; - - /* Cap the special PXA270 C5 case. */ - if (id == 7) - id = 5; - - /* Cap the special PXA270M A1 case. */ - if (id == 8) - id = 1; - - return rev[id]; -} - -static int print_cpuinfo_pxa2xx(void) -{ - if (cpu_is_pxa25x()) { - puts("Marvell PXA25x rev. "); - puts(pxa25x_get_revision()); - } else if (cpu_is_pxa27x()) { - puts("Marvell PXA27x"); - if (cpu_is_pxa27xm()) puts("M"); - puts(" rev. "); - puts(pxa27x_get_revision()); - } else - return -EINVAL; - - puts("\n"); - - return 0; -} - -int print_cpuinfo(void) -{ - int ret; - - puts("CPU: "); - - ret = print_cpuinfo_pxa2xx(); - if (!ret) - return ret; - - return ret; -} -#endif diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c deleted file mode 100644 index c7efb67754e6b47a6324a1eee1c837cddb649eba..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Flush I/D-cache */ -static void cache_flush(void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); -} - -int cleanup_before_linux(void) -{ - /* - * This function is called just before we call Linux. It prepares - * the processor for Linux by just disabling everything that can - * disturb booting Linux. - */ - - disable_interrupts(); - icache_disable(); - dcache_disable(); - cache_flush(); - - return 0; -} - -inline void writelrb(uint32_t val, uint32_t addr) -{ - writel(val, addr); - asm volatile("" : : : "memory"); - readl(addr); - asm volatile("" : : : "memory"); -} - -void pxa2xx_dram_init(void) -{ - uint32_t tmp; - int i; - /* - * 1) Initialize Asynchronous static memory controller - */ - - writelrb(CONFIG_SYS_MSC0_VAL, MSC0); - writelrb(CONFIG_SYS_MSC1_VAL, MSC1); - writelrb(CONFIG_SYS_MSC2_VAL, MSC2); - /* - * 2) Initialize Card Interface - */ - - /* MECR: Memory Expansion Card Register */ - writelrb(CONFIG_SYS_MECR_VAL, MECR); - /* MCMEM0: Card Interface slot 0 timing */ - writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0); - /* MCMEM1: Card Interface slot 1 timing */ - writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1); - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0); - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1); - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0); - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1); - - /* - * 3) Configure Fly-By DMA register - */ - - writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG); - - /* - * 4) Initialize Timing for Sync Memory (SDCLK0) - */ - - /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. - */ - - /* Read current MDREFR config and zero out DRI */ - tmp = readl(MDREFR) & ~0xfff; - /* Add user-specified DRI */ - tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff; - /* Configure important bits */ - tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; - tmp &= ~(MDREFR_APD | MDREFR_E1PIN); - - /* Write MDREFR back */ - writelrb(tmp, MDREFR); - - /* - * 5) Initialize Synchronous Static Memory (Flash/Peripherals) - */ - - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. - */ - writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG); - - /* - * 6) Initialize SDRAM - */ - - writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR); - writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR); - - /* - * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure - * but not enable each SDRAM partition pair. - */ - - writelrb(CONFIG_SYS_MDCNFG_VAL & - ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG); - - /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ - writel(0, OSCR); - while (readl(OSCR) < 0x300) - asm volatile("" : : : "memory"); - - /* - * 8) Trigger a number (usually 8) refresh cycles by attempting - * non-burst read or write accesses to disabled SDRAM, as commonly - * specified in the power up sequence documented in SDRAM data - * sheets. The address(es) used for this purpose must not be - * cacheable. - */ - for (i = 9; i >= 0; i--) { - writel(i, 0xa0000000); - asm volatile("" : : : "memory"); - } - /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). - */ - - tmp = CONFIG_SYS_MDCNFG_VAL & - (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); - tmp |= readl(MDCNFG); - writelrb(tmp, MDCNFG); - - /* - * 10) Write MDMRS. - */ - - writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS); - - /* - * 11) Enable APD - */ - - if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) { - tmp = readl(MDREFR); - tmp |= MDREFR_APD; - writelrb(tmp, MDREFR); - } -} - -void pxa_gpio_setup(void) -{ - writel(CONFIG_SYS_GPSR0_VAL, GPSR0); - writel(CONFIG_SYS_GPSR1_VAL, GPSR1); - writel(CONFIG_SYS_GPSR2_VAL, GPSR2); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GPSR3_VAL, GPSR3); -#endif - - writel(CONFIG_SYS_GPCR0_VAL, GPCR0); - writel(CONFIG_SYS_GPCR1_VAL, GPCR1); - writel(CONFIG_SYS_GPCR2_VAL, GPCR2); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GPCR3_VAL, GPCR3); -#endif - - writel(CONFIG_SYS_GPDR0_VAL, GPDR0); - writel(CONFIG_SYS_GPDR1_VAL, GPDR1); - writel(CONFIG_SYS_GPDR2_VAL, GPDR2); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GPDR3_VAL, GPDR3); -#endif - - writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L); - writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U); - writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L); - writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); - writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); - writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); - writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); -#endif - - writel(CONFIG_SYS_PSSR_VAL, PSSR); -} - -void pxa_interrupt_setup(void) -{ - writel(0, ICLR); - writel(0, ICMR); -#if defined(CONFIG_CPU_PXA27X) - writel(0, ICLR2); - writel(0, ICMR2); -#endif -} - -void pxa_clock_setup(void) -{ - writel(CONFIG_SYS_CKEN, CKEN); - writel(CONFIG_SYS_CCCR, CCCR); - asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b)); - - /* enable the 32Khz oscillator for RTC and PowerManager */ - writel(OSCC_OON, OSCC); - while (!(readl(OSCC) & OSCC_OOK)) - asm volatile("" : : : "memory"); -} - -void pxa_wakeup(void) -{ - uint32_t rcsr; - - rcsr = readl(RCSR); - writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR); - - /* Wakeup */ - if (rcsr & RCSR_SMR) { - writel(PSSR_PH, PSSR); - pxa2xx_dram_init(); - icache_disable(); - dcache_disable(); - asm volatile("mov pc, %0" : : "r"(readl(PSPR))); - } -} - -int arch_cpu_init(void) -{ - pxa_gpio_setup(); - pxa_wakeup(); - pxa_interrupt_setup(); - pxa_clock_setup(); - return 0; -} - -void i2c_clk_enable(void) -{ - /* Set the global I2C clock on */ - writel(readl(CKEN) | CKEN14_I2C, CKEN); -} - -void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn)); - -void reset_cpu(void) -{ - uint32_t tmp; - - setbits_le32(OWER, OWER_WME); - - tmp = readl(OSCR); - tmp += 0x1000; - writel(tmp, OSMR3); - writel(MDREFR_SLFRSH, MDREFR); - - for (;;) - ; -} - -void enable_caches(void) -{ -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) - icache_enable(); -#endif -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - dcache_enable(); -#endif -} diff --git a/arch/arm/cpu/pxa/relocate.S b/arch/arm/cpu/pxa/relocate.S deleted file mode 100644 index 778cd45e9c2628d25998a7a13f2848aea2d020f2..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/relocate.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - PXA270 vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD - */ - -#include - -/* - * The PXA SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM, so let's avoid relocating the vectors. - */ - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S deleted file mode 100644 index 896e05f1fda48d9b256791ff13f25dc101fd9f44..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/start.S +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * armboot - Startup Code for XScale CPU-core - * - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 Wolfgang Denk - * Copyright (C) 2001 Alex Zuepke - * Copyright (C) 2001 Marius Groger - * Copyright (C) 2002 Alex Zupke - * Copyright (C) 2002 Gary Jennejohn - * Copyright (C) 2002 Kyle Harris - * Copyright (C) 2003 Kai-Uwe Bloem - * Copyright (C) 2003 Kshitij - * Copyright (C) 2003 Richard Woodruff - * Copyright (C) 2003 Robert Schwebel - * Copyright (C) 2004 Texas Instruments - * Copyright (C) 2010 Marek Vasut - */ - -#include -#include - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - - .globl reset - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) - bl cpu_init_crit -#endif - -#ifdef CONFIG_CPU_PXA25X - bl lock_cache_for_stack -#endif -#ifdef CONFIG_CPU_PXA27X - /* - * enable clock for SRAM - */ - ldr r0,=CKEN - ldr r1,[r0] - orr r1,r1,#(1 << 20) - str r1,[r0] -#endif - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - -#ifdef CONFIG_CPU_PXA25X - /* - * Unlock (actually, disable) the cache now that board_init_f - * is done. We could do this earlier but we would need to add - * a new C runtime hook, whereas c_runtime_cpu_setup already - * exists. - * As this routine is just a call to cpu_init_crit, let us - * tail-optimize and do a simple branch here. - */ - b cpu_init_crit -#else - bx lr -#endif - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ - mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 1 (A) Align - mcr p15, 0, r0, c1, c0, 0 - - mov pc, lr /* back to my caller */ -#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */ - -/* - * Enable MMU to use DCache as DRAM. - * - * This is useful on PXA25x and PXA26x in early bootstages, where there is no - * other possible memory available to hold stack. - */ -#ifdef CONFIG_CPU_PXA25X -.macro CPWAIT reg - mrc p15, 0, \reg, c2, c0, 0 - mov \reg, \reg - sub pc, pc, #4 -.endm -lock_cache_for_stack: - /* Domain access -- enable for all CPs */ - ldr r0, =0x0000ffff - mcr p15, 0, r0, c3, c0, 0 - - /* Point TTBR to MMU table */ - ldr r0, =mmutable - mcr p15, 0, r0, c2, c0, 0 - - /* Kick in MMU, ICache, DCache, BTB */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, #0x1b00 - bic r0, #0x0087 - orr r0, #0x1800 - orr r0, #0x0005 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* Unlock Icache, Dcache */ - mcr p15, 0, r0, c9, c1, 1 - mcr p15, 0, r0, c9, c2, 1 - - /* Flush Icache, Dcache, BTB */ - mcr p15, 0, r0, c7, c7, 0 - - /* Unlock I-TLB, D-TLB */ - mcr p15, 0, r0, c10, c4, 1 - mcr p15, 0, r0, c10, c8, 1 - - /* Flush TLB */ - mcr p15, 0, r0, c8, c7, 0 - - /* Allocate 4096 bytes of Dcache as RAM */ - - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - - mov r4, #0x00 - mov r5, #0x00 - mov r2, #0x01 - mcr p15, 0, r0, c9, c2, 0 - CPWAIT r0 - - /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ - mov r0, #128 - ldr r1, =0xfffff000 - -alloc: - mcr p15, 0, r1, c7, c2, 5 - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - strd r4, [r1], #8 - strd r4, [r1], #8 - strd r4, [r1], #8 - strd r4, [r1], #8 - subs r0, #0x01 - bne alloc - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - mov r2, #0x00 - mcr p15, 0, r2, c9, c2, 0 - CPWAIT r0 - - mov pc, lr - -.section .mmutable, "a" -mmutable: - .align 14 - /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ - .set __base, 0 - .rept 0xfff - .word (__base << 20) | 0xc12 - .set __base, __base + 1 - .endr - - /* 0xfff00000 : 1:1, cached mapping */ - .word (0xfff << 20) | 0x1c1e -#endif /* CONFIG_CPU_PXA25X */ diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c deleted file mode 100644 index 8e9d610441ee85e463e4f1b9ee7ebc3e4038974e..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/timer.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Marvell PXA2xx/3xx timer driver - * - * Copyright (C) 2011 Marek Vasut - */ - -#include -#include -#include - -int timer_init(void) -{ - writel(0, CONFIG_SYS_TIMER_COUNTER); - return 0; -} diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c deleted file mode 100644 index 13e010d91ec4ede75418fb74925267d87af75574..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/pxa/usb.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering - */ - -#include -#include - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) - -#include -#include -#include - -int usb_cpu_init(void) -{ -#if defined(CONFIG_CPU_MONAHANS) - /* Enable USB host clock. */ - writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); - udelay(100); -#endif -#if defined(CONFIG_CPU_PXA27X) - /* Enable USB host clock. */ - writel(readl(CKEN) | CKEN10_USBHOST, CKEN); -#endif - -#if defined(CONFIG_CPU_MONAHANS) - /* Configure Port 2 for Host (USB Client Registers) */ - writel(0x3000c, UP2OCR); -#endif - - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - mdelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (readl(UHCHR) & UHCHR_FSBIR) - udelay(1); - -#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) - writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); -#endif -#if defined(CONFIG_CPU_PXA27X) - writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); -#endif - writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); - - return 0; -} - -int usb_cpu_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS); - udelay(10); - -#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) - writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); -#endif -#if defined(CONFIG_CPU_PXA27X) - writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); -#endif - writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); - -#if defined(CONFIG_CPU_MONAHANS) - /* Disable USB host clock. */ - writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); - udelay(100); -#endif -#if defined(CONFIG_CPU_PXA27X) - /* Disable USB host clock. */ - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); -#endif - - return 0; -} - -int usb_cpu_init_fail(void) -{ - return usb_cpu_stop(); -} - -# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/arm/cpu/sa1100/Makefile b/arch/arm/cpu/sa1100/Makefile deleted file mode 100644 index 38193092cdb0a618c26aebffba81701232b2e55a..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/sa1100/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -extra-y = start.o - -obj-y += cpu.o -obj-y += timer.o diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c deleted file mode 100644 index 6f67f7fc228473b1c04dff00c3f2a792685d152a..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/sa1100/cpu.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include -#include -#include - -static void cache_flush(void); - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - disable_interrupts(); - - /* turn off I-cache */ - icache_disable(); - dcache_disable(); - - /* flush I-cache */ - cache_flush(); - - return (0); -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -#define RST_BASE 0x90030000 -#define RSRR 0x00 -#define RCSR 0x04 - -__attribute__((noreturn)) void reset_cpu(void) -{ - /* repeat endlessly */ - while (1) { - writel(0, RST_BASE + RCSR); - writel(1, RST_BASE + RSRR); - } -} diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S deleted file mode 100644 index 2f84f20575c98b3361a1108d260d32dbbda347b9..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/sa1100/start.S +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * armboot - Startup Code for SA1100 CPU - * - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 Wolfgang Denk - * Copyright (c) 2001 Alex Züpke - */ - -#include -#include - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - - .globl reset - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) - bl cpu_init_crit -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - mov pc, lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -/* Interrupt-Controller base address */ -IC_BASE: .word 0x90050000 -#define ICMR 0x04 - - -/* Reset-Controller */ -RST_BASE: .word 0x90030000 -#define RSRR 0x00 -#define RCSR 0x04 - - -/* PWR */ -PWR_BASE: .word 0x90020000 -#define PSPR 0x08 -#define PPCR 0x14 -cpuspeed: .word CONFIG_SYS_CPUSPEED - - -cpu_init_crit: - /* - * mask all IRQs - */ - ldr r0, IC_BASE - mov r1, #0x00 - str r1, [r0, #ICMR] - - /* set clock speed */ - ldr r0, PWR_BASE - ldr r1, cpuspeed - str r1, [r0, #PPCR] - -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip -#endif - - /* - * disable MMU stuff and enable I-cache - */ - mrc p15,0,r0,c1,c0 - bic r0, r0, #0x00002000 @ clear bit 13 (X) - bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) - orr r0, r0, #0x00001000 @ set bit 12 (I) Icache - orr r0, r0, #0x00000002 @ set bit 1 (A) Align - mcr p15,0,r0,c1,c0 - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov pc, lr diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c deleted file mode 100644 index a5cdaf5a66c4593f2b967031445cb9a9babec669..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/sa1100/timer.c +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - */ - -#include -#include -#include -#include - -static ulong get_timer_masked (void) -{ - return OSCR; -} - -ulong get_timer (ulong base) -{ - return get_timer_masked (); -} - -void __udelay(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 97899a567ff5ce526c95cd429e0094bf3ab6ca96..fb2189d50dea6ee75fa1fa4573932fc154f13ee9 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -32,8 +32,8 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 0eb164d2e694d44e03e1313d41ba2a03435c91a6..f25f72b2e0d807894c99b489109b6a131a717a86 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -15,7 +15,7 @@ ENTRY(_start) SECTIONS { #ifndef CONFIG_CMDLINE - /DISCARD/ : { *(.u_boot_list_2_cmd_*) } + /DISCARD/ : { *(__u_boot_list_2_cmd_*) } #endif #if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) /* @@ -149,8 +149,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a7e0d9f6c0e8152db7ece9e3a46519ebdeba3ff3..c2435d8cba46155a9ce22f4b740c58edfe0bb78f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb -dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb -dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb -dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ +dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb +dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ @@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb -dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ +dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-spring.dtb \ exynos5250-smdk5250.dtb \ @@ -342,6 +342,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-qspi.dtb \ zynqmp-sm-k26-revA.dtb \ zynqmp-smk-k26-revA.dtb \ + zynqmp-sck-kr-g-revA.dtbo \ + zynqmp-sck-kr-g-revB.dtbo \ zynqmp-sck-kv-g-revA.dtbo \ zynqmp-sck-kv-g-revB.dtbo \ zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ @@ -412,7 +414,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am437x-cm-t43.dtb dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb dtb-$(CONFIG_TI816X) += dm8168-evm.dtb -dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb +dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ @@ -1072,6 +1074,8 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ omap3-beagle-xm.dtb \ omap3-beagle.dtb +dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb + dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \ omap3-igep0020.dtb @@ -1157,11 +1161,17 @@ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb +dtb-$(CONFIG_BCM47622) += \ + bcm947622.dtb + dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb +dtb-$(CONFIG_STM32MP13x) += \ + stm32mp135f-dk.dtb + dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ @@ -1199,6 +1209,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ k3-am642-sk.dtb \ k3-am642-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ + k3-am625-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ @@ -1239,6 +1252,8 @@ dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb +dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts + dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \ imx8mm-cl-iot-gate-ied.dtbo \ imx8mm-cl-iot-gate-ied-adc0.dtbo \ @@ -1265,6 +1280,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb +dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ + corstone1000-fvp.dtb + include $(srctree)/scripts/Makefile.dts targets += $(dtb-y) diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index 4796ed445f57484885b1f1718b661b430efcf17e..cc577761fa678d0ea7ab0b2c25d98e4fc0e1ea53 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -60,6 +60,10 @@ pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>; }; +&sdmmc { + status = "okay"; +}; + &sdhci0 { status = "okay"; @@ -73,3 +77,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd2_default>; }; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index ea60e4c8db92e93ad9fda01d674e4cde0a9ccb81..057390fe707e6d575549ab38999bcc4642bd755a 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -28,31 +28,6 @@ clocks = <&scu ASPEED_CLK_MPLL>; resets = <&rst ASPEED_RESET_SDRAM>; }; - - ahb { - u-boot,dm-pre-reloc; - - apb { - u-boot,dm-pre-reloc; - - sdhci0: sdhci@1e740100 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x1e740100>; - #reset-cells = <1>; - clocks = <&scu ASPEED_CLK_SDIO>; - resets = <&rst ASPEED_RESET_SDIO>; - }; - - sdhci1: sdhci@1e740200 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x1e740200>; - #reset-cells = <1>; - clocks = <&scu ASPEED_CLK_SDIO>; - resets = <&rst ASPEED_RESET_SDIO>; - }; - }; - - }; }; &uart1 { diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index ee66ef67042b1814dca8591019f074c5987773ca..cea08e6f08dfe8626c53198801f451ad5818d942 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -207,6 +207,34 @@ reg = <0x1e720000 0x9000>; // 36K }; + sdmmc: sd-controller@1e740000 { + compatible = "aspeed,ast2500-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&scu ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@100 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x100 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&scu ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@200 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x200 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&scu ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + gpio: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index 0d650543134ac7fee96667ecf3c342643195e090..a9bba9681604f22d39d4fe204f8829afaf20cd67 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -15,9 +15,9 @@ }; aliases { - mmc0 = &emmc_slot0; - mmc1 = &sdhci_slot0; - mmc2 = &sdhci_slot1; + mmc0 = &emmc; + mmc1 = &sdhci0; + mmc2 = &sdhci1; spi0 = &fmc; spi1 = &spi1; spi2 = &spi2; @@ -134,53 +134,52 @@ }; }; -&emmc { - u-boot,dm-pre-reloc; - timing-phase = <0x700ff>; + +&emmc_controller { + status = "okay"; }; -&emmc_slot0 { - u-boot,dm-pre-reloc; - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc_default>; - sdhci-drive-type = <1>; +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; }; &i2c4 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; }; &i2c5 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; }; &i2c6 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; }; &i2c7 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; }; &i2c8 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; }; &mdio0 { diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 64074309b7b2393d7b39ab8168eaabb0b73194ee..ac8cd4d67d803f051c1777bbbe59c33627fcec6b 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -416,60 +416,51 @@ status = "disabled"; }; - sdhci: sdhci@1e740000 { - #interrupt-cells = <1>; - compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; - reg = <0x1e740000 0x1000>; - interrupts = ; - interrupt-controller; - clocks = <&scu ASPEED_CLK_GATE_SDCLK>, - <&scu ASPEED_CLK_GATE_SDEXTCLK>; - clock-names = "ctrlclk", "extclk"; + sdc: sdc@1e740000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e740000 0x100>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x1e740000 0x1000>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&scu ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; - sdhci_slot0: sdhci_slot0@100 { - compatible = "aspeed,sdhci-ast2600"; + sdhci0: sdhci@1e740100 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; reg = <0x100 0x100>; - interrupts = <0>; - interrupt-parent = <&sdhci>; + interrupts = ; sdhci,auto-cmd12; clocks = <&scu ASPEED_CLK_SDIO>; status = "disabled"; }; - sdhci_slot1: sdhci_slot1@200 { - compatible = "aspeed,sdhci-ast2600"; + sdhci1: sdhci@1e740200 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; reg = <0x200 0x100>; - interrupts = <1>; - interrupt-parent = <&sdhci>; + interrupts = ; sdhci,auto-cmd12; clocks = <&scu ASPEED_CLK_SDIO>; status = "disabled"; }; }; - emmc: emmc@1e750000 { - #interrupt-cells = <1>; - compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; - reg = <0x1e750000 0x1000>; - interrupts = ; - interrupt-controller; - clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, - <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; - clock-names = "ctrlclk", "extclk"; + emmc_controller: sdc@1e750000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e750000 0x100>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x1e750000 0x1000>; + ranges = <0 0x1e750000 0x10000>; + clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>; + status = "disabled"; - emmc_slot0: emmc_slot0@100 { - compatible = "aspeed,emmc-ast2600"; + emmc: sdhci@1e750100 { + compatible = "aspeed,ast2600-sdhci"; reg = <0x100 0x100>; - interrupts = <0>; - interrupt-parent = <&emmc>; + sdhci,auto-cmd12; + interrupts = ; clocks = <&scu ASPEED_CLK_EMMC>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_default>; }; }; @@ -832,7 +823,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; status = "disabled"; }; @@ -845,7 +839,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; status = "disabled"; }; @@ -858,7 +855,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; }; i2c3: i2c@200 { @@ -870,7 +871,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; }; i2c4: i2c@280 { @@ -882,7 +887,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; }; i2c5: i2c@300 { @@ -894,7 +903,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; }; i2c6: i2c@380 { @@ -906,7 +919,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; }; i2c7: i2c@400 { @@ -918,7 +935,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; }; i2c8: i2c@480 { @@ -930,7 +951,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; }; i2c9: i2c@500 { @@ -942,7 +967,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; status = "disabled"; }; @@ -955,7 +983,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; status = "disabled"; }; @@ -968,7 +999,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; status = "disabled"; }; @@ -981,7 +1015,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; status = "disabled"; }; @@ -994,7 +1031,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; status = "disabled"; }; @@ -1007,7 +1047,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; status = "disabled"; }; @@ -1020,7 +1063,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = ; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; status = "disabled"; }; @@ -1246,6 +1292,7 @@ function = "I2C1"; groups = "I2C1"; }; + pinctrl_i2c2_default: i2c2_default { function = "I2C2"; groups = "I2C2"; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index 44522197ff67ebc72b68df8be4a011b23cda5dff..0b0db1b2be88ad1c2ec13cecdba9c14abcc79bde 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -68,19 +68,19 @@ status = "okay"; eeprom@50 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x50>; pagesize = <16>; }; eeprom@52 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x52>; pagesize = <16>; }; eeprom@53 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x53>; pagesize = <16>; }; diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index ee46112b08b0424f4dee14c30419c58cf1c59411..eaba0de3f7ff04ce1f97b1a24e80d54c0120ab95 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "Microchip SAMA7G5-EK"; @@ -404,13 +405,13 @@ status = "okay"; eeprom@52 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x52>; pagesize = <16>; }; eeprom@53 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x53>; pagesize = <16>; }; @@ -468,7 +469,7 @@ &pinctrl_gmac1_mdio_default &pinctrl_gmac1_phy_irq>; phy-mode = "rmii"; - status = "okay"; + status = "okay"; /* Conflict with pdmc0. */ ethernet-phy@0 { reg = <0x0>; @@ -482,6 +483,17 @@ pinctrl-0 = <&pinctrl_i2s0_default>; }; +&pdmc0 { + #sound-dai-cells = <0>; + microchip,mic-pos = , /* MIC 1 */ + , /* MIC 2 */ + , /* MIC 3 */ + ; /* MIC 4 */ + status = "disabled"; /* Conflict with gmac1. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdmc0_default>; +}; + &pioA { pinctrl_can0_default: can0_default { @@ -651,6 +663,13 @@ bias-disable; }; + pinctrl_pdmc0_default: pdmc0_default { + pinmux = , + , + ; + bias_disable; + }; + pinctrl_qspi: qspi { pinmux = , , diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c016e12b73729ce4382c1be68449aff5691dc6d1 --- /dev/null +++ b/arch/arm/dts/bcm47622.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm47622", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x818000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm947622.dts b/arch/arm/dts/bcm947622.dts new file mode 100644 index 0000000000000000000000000000000000000000..6f083724ab8ea3989dfb55e3d04f5f9b5613c2df --- /dev/null +++ b/arch/arm/dts/bcm947622.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts new file mode 100644 index 0000000000000000000000000000000000000000..26b0f1b3cea6e0fb7e5f1745d83238d4826fe02d --- /dev/null +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; + + vmmc_v3_3d: fixed_v3_3d { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts new file mode 100644 index 0000000000000000000000000000000000000000..e3146747c2d9326ae577aa513c6ab4463b52779c --- /dev/null +++ b/arch/arm/dts/corstone1000-mps3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb_host: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = ; + bus-width = <16>; + dr_mode = "host"; + }; +}; diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4e46826f883af7c1978157a5ceb05acc79ae0d10 --- /dev/null +++ b/arch/arm/dts/corstone1000.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = ; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + timer@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <50000000>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = ; + reg = <0x1a230000 0x1000>; + }; + }; + + uart0: serial@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + mhu_hse1: mailbox@1b820000 { + compatible = "arm,mhuv2-tx", "arm,primecell"; + reg = <0x1b820000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + + mhu_seh1: mailbox@1b830000 { + compatible = "arm,mhuv2-rx", "arm,primecell"; + reg = <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 1cdcc99c1ee65a4f077e04dd9ef13e2cefa12eec..796d72fc9edb91f230883aa80dde434ff59747d9 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -34,6 +34,13 @@ #size-cells = <2>; ranges; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1012a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 72877d2ff58e5201e529236c468b25c576095ff0..4960973a60355806f3bd82ed883788fa0b9f476e 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -38,6 +38,13 @@ #size-cells = <2>; ranges; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1043a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index c655e002aa0825e56b51186cee9438dd66f379ef..060dc399c2f6b939ae9c501514951b9c8c4f2df4 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -38,6 +38,13 @@ #size-cells = <2>; ranges; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1046a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/hpe-bmc-dl360gen10.dts b/arch/arm/dts/hpe-bmc-dl360gen10.dts new file mode 100644 index 0000000000000000000000000000000000000000..b8030d9d9fd704d2b96e4968c282fb4f705e2666 --- /dev/null +++ b/arch/arm/dts/hpe-bmc-dl360gen10.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE DL360Gen10 + */ + +/include/ "hpe-gxp-u-boot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "hpe,gxp-dl360gen10", "hpe,gxp"; + model = "Hewlett Packard Enterprise ProLiant dl360 Gen10"; + + aliases { + serial0 = &uartc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; diff --git a/arch/arm/dts/hpe-gxp-u-boot.dtsi b/arch/arm/dts/hpe-gxp-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..7a2b488521fadd071acdd908e15aae92f23e66a6 --- /dev/null +++ b/arch/arm/dts/hpe-gxp-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GXP + */ + +/include/ "hpe-gxp.dtsi" + +/ { + + axi { + u-boot,dm-pre-reloc; + + ahb@c0000000 { + u-boot,dm-pre-reloc; + + spi0: spi@200 { + compatible = "hpe,gxp-spi"; + reg = <0x200 0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/hpe-gxp.dtsi b/arch/arm/dts/hpe-gxp.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cf735b3c4f3565280cdf4baeef09f480f4bd4b2e --- /dev/null +++ b/arch/arm/dts/hpe-gxp.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GXP + */ + +/dts-v1/; +/ { + model = "Hewlett Packard Enterprise GXP BMC"; + compatible = "hpe,gxp"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + clocks { + pll: clock-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1600000000>; + }; + + iopclk: clock-1 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + L2: cache-controller@b0040000 { + compatible = "arm,pl310-cache"; + reg = <0xb0040000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + ahb@c0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000000 0x30000000>; + dma-ranges; + + vic0: interrupt-controller@eff0000 { + compatible = "arm,pl192-vic"; + reg = <0xeff0000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@80f00000 { + compatible = "arm,pl192-vic"; + reg = <0x80f00000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uarta: serial@e0 { + compatible = "ns16550a"; + reg = <0xe0 0x8>; + interrupts = <17>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartb: serial@e8 { + compatible = "ns16550a"; + reg = <0xe8 0x8>; + interrupts = <18>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartc: serial@f0 { + compatible = "ns16550a"; + reg = <0xf0 0x8>; + interrupts = <19>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + usb0: usb@efe0000 { + compatible = "hpe,gxp-ehci", "generic-ehci"; + reg = <0xefe0000 0x100>; + interrupts = <7>; + interrupt-parent = <&vic0>; + }; + + st: timer@80 { + compatible = "hpe,gxp-timer"; + reg = <0x80 0x16>; + interrupts = <0>; + interrupt-parent = <&vic0>; + clocks = <&iopclk>; + clock-names = "iop"; + }; + + usb1: usb@efe0100 { + compatible = "hpe,gxp-ohci", "generic-ohci"; + reg = <0xefe0100 0x110>; + interrupts = <6>; + interrupt-parent = <&vic0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index e33e10ac1294d3109a767da29e8e4d7c62827225..c94b4ffa4c30f0f629204f0a990b7392099efc1d 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -73,6 +73,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &uart2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi index 433b02cceeef069dcdf68318bd76dfcc8050b173..a7044b63699ff04c77e6ca4c1c6c3409d460ef3b 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi @@ -84,6 +84,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &uart3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi index 8cd3b23793c455ab5ad211ecffc59e2adf68d5be..955e5d2edf2be4931bef73bac1cbe5071d68e799 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi @@ -139,3 +139,7 @@ &wdog1 { u-boot,dm-spl; }; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi index c61c6de935fb53a010f683f12a8383f760bac443..68978a0413ec7890ff278ddd3d87c965bce5a1c3 100644 --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi @@ -72,3 +72,7 @@ &wdog1 { u-boot,dm-spl; }; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi index 69fd69c8d0255557d1e3c711e8ca8b33904e0a2a..eb1dd8debbaf238227d0ee8f4d0708fd2a1a5da0 100644 --- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi @@ -132,6 +132,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { filename = "u-boot-spl-ddr.bin"; diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi index 4f23da356763625194e482075408adb72d8caa1f..358195538797e27ffa80e8208a32e6dbb4421e0e 100644 --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi @@ -110,6 +110,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { align = <4>; diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index 2848b24f65530369598de50d46f6c2c9b79d01fe..4419967ee42dceafb5e8ad991117133643ddaa31 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -89,6 +89,14 @@ u-boot,dm-spl; }; +&wdog1 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi index 37f3edc981777fc526725c89b68598acd31c2f53..96b9fa89cf46bfa92ee4ad4b232b7c7a78cdd57e 100644 --- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -72,3 +72,7 @@ &wdog1 { u-boot,dm-spl; }; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am62-ddr.dtsi b/arch/arm/dts/k3-am62-ddr.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0a8ced8f382676e76070870d55ae3a827c2d4d20 --- /dev/null +++ b/arch/arm/dts/k3-am62-ddr.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am64-ddr.dtsi" +&memorycontroller { + power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>, + <&k3_pds 55 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 170 0>, <&k3_clks 16 4>; +}; diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4b6ba98dd0a20e939f54cbcd09941a63f5816d2f --- /dev/null +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Main Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@100000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + }; + + dmss: bus@48000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = ; + }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <4 68 36>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + }; + + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 174 0>; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + ti,trm-icp = <0x2>; + bus-width = <8>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x9>; + ti,otap-del-sel-hs200 = <0x6>; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + bus-width = <4>; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&wkup_conf 0x200>; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 13 1>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; +}; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d103824c963ffee902d609a154b523f0cfaa2b4e --- /dev/null +++ b/arch/arm/dts/k3-am62-mcu.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + }; +}; diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4090134676cf679af44856f55343c01f352d2827 --- /dev/null +++ b/arch/arm/dts/k3-am62-wakeup.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..bc2997b18556b990966c8afce0094b73c4955aa7 --- /dev/null +++ b/arch/arm/dts/k3-am62.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62 SoC Family + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM625 SoC"; + compatible = "ti,am625"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + + /* Wakeup Domain Range */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ + }; + + cbass_wakeup: bus@2b000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62-main.dtsi" +#include "k3-am62-mcu.dtsi" +#include "k3-am62-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts new file mode 100644 index 0000000000000000000000000000000000000000..5aab858edd149540e187419c6f070c649733dbb3 --- /dev/null +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 SK dts file for R5 SPL + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625-sk.dts" +#include "k3-am62x-sk-ddr4-1600MTs.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am625-sk-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + u-boot,dm-spl; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + u-boot,dm-spl; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + u-boot,dm-spl; + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "rt", "scfg", "target_data"; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x0 0x44860000 0x0 0x20000>, + <0x0 0x43600000 0x0 0x10000>; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + u-boot,dm-spl; + }; +}; + +&mcu_pmx0 { + u-boot,dm-spl; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ + >; + u-boot,dm-spl; + }; +}; + +&main_pmx0 { + u-boot,dm-spl; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + u-boot,dm-spl; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "okay"; + u-boot,dm-spl; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "okay"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..159fa36bbe9f163e6eedd0232d30c13acd6aa910 --- /dev/null +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM625 SK dts file for SPLs + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + aliases { + mmc1 = &sdhci1; + }; + + memory@80000000 { + u-boot,dm-spl; + }; +}; + +&cbass_main{ + u-boot,dm-spl; + + timer1: timer@2400000 { + compatible = "ti,omap5430-timer"; + reg = <0x00 0x2400000 0x00 0x80>; + ti,timer-alwon; + clock-frequency = <25000000>; + u-boot,dm-spl; + }; +}; + +&dmss { + u-boot,dm-spl; +}; + +&secure_proxy_main { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&wkup_conf { + u-boot,dm-spl; +}; + +&chipid { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; +}; + +&main_uart0_pins_default { + u-boot,dm-spl; +}; + +&main_uart1 { + u-boot,dm-spl; +}; + +&cbass_mcu { + u-boot,dm-spl; +}; + +&cbass_wakeup { + u-boot,dm-spl; +}; + +&mcu_pmx0 { + u-boot,dm-spl; +}; + +&wkup_uart0 { + u-boot,dm-spl; +}; + +&sdhci1 { + u-boot,dm-spl; +}; + +&main_mmc1_pins_default { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts new file mode 100644 index 0000000000000000000000000000000000000000..76b06ea2395360d2a120ce043fe981b463d4f2a2 --- /dev/null +++ b/arch/arm/dts/k3-am625-sk.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 SK: https://www.ti.com/lit/zip/sprr448 + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "ti,am625-sk", "ti,am625"; + model = "Texas Instruments AM625 SK"; + + aliases { + serial2 = &main_uart0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&mcu_uart0 { + status = "disabled"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_uart2 { + status = "disabled"; +}; + +&main_uart3 { + status = "disabled"; +}; + +&main_uart4 { + status = "disabled"; +}; + +&main_uart5 { + status = "disabled"; +}; + +&main_uart6 { + status = "disabled"; +}; + +&mcu_i2c0 { + status = "disabled"; +}; + +&wkup_i2c0 { + status = "disabled"; +}; + +&main_i2c0 { + status = "disabled"; +}; + +&main_i2c1 { + status = "disabled"; +}; + +&main_i2c2 { + status = "disabled"; +}; + +&main_i2c3 { + status = "disabled"; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..887f31c23fef64d6f3fb83cfdde708ad55cce6a6 --- /dev/null +++ b/arch/arm/dts/k3-am625.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/pdf/spruiv7 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d92e3ce048b92fc0786161f24a6cb8684df55815 --- /dev/null +++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi @@ -0,0 +1,2189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60 + * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time) + * DDR Type: DDR4 + * Frequency = 800MHz (1600MTs) + * Density: 16Gb + * Number of Ranks: 1 + */ + +#define DDRSS_PLL_FHS_CNT 6 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + +#define DDRSS_CTL_0_DATA 0x00000A00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x000890B8 +#define DDRSS_CTL_8_DATA 0x00000000 +#define DDRSS_CTL_9_DATA 0x00000000 +#define DDRSS_CTL_10_DATA 0x00000000 +#define DDRSS_CTL_11_DATA 0x000890B8 +#define DDRSS_CTL_12_DATA 0x00000000 +#define DDRSS_CTL_13_DATA 0x00000000 +#define DDRSS_CTL_14_DATA 0x00000000 +#define DDRSS_CTL_15_DATA 0x000890B8 +#define DDRSS_CTL_16_DATA 0x00000000 +#define DDRSS_CTL_17_DATA 0x00000000 +#define DDRSS_CTL_18_DATA 0x00000000 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01000100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x00027100 +#define DDRSS_CTL_24_DATA 0x00061A80 +#define DDRSS_CTL_25_DATA 0x02550255 +#define DDRSS_CTL_26_DATA 0x00000255 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00000000 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x00000000 +#define DDRSS_CTL_35_DATA 0x00000000 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0400091C +#define DDRSS_CTL_39_DATA 0x1C1C1C1C +#define DDRSS_CTL_40_DATA 0x0400091C +#define DDRSS_CTL_41_DATA 0x1C1C1C1C +#define DDRSS_CTL_42_DATA 0x0400091C +#define DDRSS_CTL_43_DATA 0x1C1C1C1C +#define DDRSS_CTL_44_DATA 0x05050404 +#define DDRSS_CTL_45_DATA 0x00002706 +#define DDRSS_CTL_46_DATA 0x0602001D +#define DDRSS_CTL_47_DATA 0x05001D0B +#define DDRSS_CTL_48_DATA 0x00270605 +#define DDRSS_CTL_49_DATA 0x0602001D +#define DDRSS_CTL_50_DATA 0x05001D0B +#define DDRSS_CTL_51_DATA 0x00270605 +#define DDRSS_CTL_52_DATA 0x0602001D +#define DDRSS_CTL_53_DATA 0x07001D0B +#define DDRSS_CTL_54_DATA 0x00180807 +#define DDRSS_CTL_55_DATA 0x0400DB60 +#define DDRSS_CTL_56_DATA 0x07070009 +#define DDRSS_CTL_57_DATA 0x00001808 +#define DDRSS_CTL_58_DATA 0x0400DB60 +#define DDRSS_CTL_59_DATA 0x07070009 +#define DDRSS_CTL_60_DATA 0x00001808 +#define DDRSS_CTL_61_DATA 0x0400DB60 +#define DDRSS_CTL_62_DATA 0x03000009 +#define DDRSS_CTL_63_DATA 0x0D0C0002 +#define DDRSS_CTL_64_DATA 0x0D0C0D0C +#define DDRSS_CTL_65_DATA 0x01010000 +#define DDRSS_CTL_66_DATA 0x03191919 +#define DDRSS_CTL_67_DATA 0x0B0B0B0B +#define DDRSS_CTL_68_DATA 0x00000B0B +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x01180803 +#define DDRSS_CTL_73_DATA 0x00001860 +#define DDRSS_CTL_74_DATA 0x00000118 +#define DDRSS_CTL_75_DATA 0x00001860 +#define DDRSS_CTL_76_DATA 0x00000118 +#define DDRSS_CTL_77_DATA 0x00001860 +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x00000000 +#define DDRSS_CTL_80_DATA 0x00000000 +#define DDRSS_CTL_81_DATA 0x00000000 +#define DDRSS_CTL_82_DATA 0x00000000 +#define DDRSS_CTL_83_DATA 0x00000000 +#define DDRSS_CTL_84_DATA 0x00000000 +#define DDRSS_CTL_85_DATA 0x00000000 +#define DDRSS_CTL_86_DATA 0x00000000 +#define DDRSS_CTL_87_DATA 0x00090009 +#define DDRSS_CTL_88_DATA 0x00000009 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x00000000 +#define DDRSS_CTL_91_DATA 0x00000000 +#define DDRSS_CTL_92_DATA 0x00000000 +#define DDRSS_CTL_93_DATA 0x00000000 +#define DDRSS_CTL_94_DATA 0x00010001 +#define DDRSS_CTL_95_DATA 0x00025501 +#define DDRSS_CTL_96_DATA 0x02550120 +#define DDRSS_CTL_97_DATA 0x02550120 +#define DDRSS_CTL_98_DATA 0x01200120 +#define DDRSS_CTL_99_DATA 0x01200120 +#define DDRSS_CTL_100_DATA 0x00000000 +#define DDRSS_CTL_101_DATA 0x00000000 +#define DDRSS_CTL_102_DATA 0x00000000 +#define DDRSS_CTL_103_DATA 0x00000000 +#define DDRSS_CTL_104_DATA 0x00000000 +#define DDRSS_CTL_105_DATA 0x00000000 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00061800 +#define DDRSS_CTL_120_DATA 0x00061800 +#define DDRSS_CTL_121_DATA 0x00061800 +#define DDRSS_CTL_122_DATA 0x00061800 +#define DDRSS_CTL_123_DATA 0x00061800 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000AAA0 +#define DDRSS_CTL_126_DATA 0x00061800 +#define DDRSS_CTL_127_DATA 0x00061800 +#define DDRSS_CTL_128_DATA 0x00061800 +#define DDRSS_CTL_129_DATA 0x00061800 +#define DDRSS_CTL_130_DATA 0x00061800 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AAA0 +#define DDRSS_CTL_133_DATA 0x00061800 +#define DDRSS_CTL_134_DATA 0x00061800 +#define DDRSS_CTL_135_DATA 0x00061800 +#define DDRSS_CTL_136_DATA 0x00061800 +#define DDRSS_CTL_137_DATA 0x00061800 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AAA0 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x080C0000 +#define DDRSS_CTL_157_DATA 0x080C080C +#define DDRSS_CTL_158_DATA 0x08000000 +#define DDRSS_CTL_159_DATA 0x00000808 +#define DDRSS_CTL_160_DATA 0x000E0000 +#define DDRSS_CTL_161_DATA 0x00080808 +#define DDRSS_CTL_162_DATA 0x0E000000 +#define DDRSS_CTL_163_DATA 0x08080800 +#define DDRSS_CTL_164_DATA 0x00000000 +#define DDRSS_CTL_165_DATA 0x0000080E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000000 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x00000000 +#define DDRSS_CTL_196_DATA 0x00000000 +#define DDRSS_CTL_197_DATA 0x00000000 +#define DDRSS_CTL_198_DATA 0x00000000 +#define DDRSS_CTL_199_DATA 0x00000000 +#define DDRSS_CTL_200_DATA 0x00000000 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00042400 +#define DDRSS_CTL_205_DATA 0x00000301 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000424 +#define DDRSS_CTL_208_DATA 0x00000301 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000424 +#define DDRSS_CTL_211_DATA 0x00000301 +#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_213_DATA 0x00000424 +#define DDRSS_CTL_214_DATA 0x00000301 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000424 +#define DDRSS_CTL_217_DATA 0x00000301 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000424 +#define DDRSS_CTL_220_DATA 0x00000301 +#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000000 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000000 +#define DDRSS_CTL_228_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0x00000000 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00001401 +#define DDRSS_CTL_237_DATA 0x00001401 +#define DDRSS_CTL_238_DATA 0x00001401 +#define DDRSS_CTL_239_DATA 0x00001401 +#define DDRSS_CTL_240_DATA 0x00001401 +#define DDRSS_CTL_241_DATA 0x00001401 +#define DDRSS_CTL_242_DATA 0x00000493 +#define DDRSS_CTL_243_DATA 0x00000493 +#define DDRSS_CTL_244_DATA 0x00000493 +#define DDRSS_CTL_245_DATA 0x00000493 +#define DDRSS_CTL_246_DATA 0x00000493 +#define DDRSS_CTL_247_DATA 0x00000493 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x00000000 +#define DDRSS_CTL_258_DATA 0x00000000 +#define DDRSS_CTL_259_DATA 0x00000000 +#define DDRSS_CTL_260_DATA 0x00000000 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x00000000 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x00000000 +#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_268_DATA 0x00000000 +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00000000 +#define DDRSS_CTL_271_DATA 0x00000000 +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000000 +#define DDRSS_CTL_275_DATA 0x00000000 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000000 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00040000 +#define DDRSS_CTL_306_DATA 0x00800200 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x02000400 +#define DDRSS_CTL_309_DATA 0x00000080 +#define DDRSS_CTL_310_DATA 0x00040000 +#define DDRSS_CTL_311_DATA 0x00800200 +#define DDRSS_CTL_312_DATA 0x00000000 +#define DDRSS_CTL_313_DATA 0x00000000 +#define DDRSS_CTL_314_DATA 0x00000000 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000000 +#define DDRSS_CTL_318_DATA 0x3FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_322_DATA 0x0A000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x00000000 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x00000000 +#define DDRSS_CTL_331_DATA 0x01000000 +#define DDRSS_CTL_332_DATA 0x00000100 +#define DDRSS_CTL_333_DATA 0x00010000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x0C000000 +#define DDRSS_CTL_371_DATA 0x060C0606 +#define DDRSS_CTL_372_DATA 0x06060C06 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x02000000 +#define DDRSS_CTL_375_DATA 0x05020101 +#define DDRSS_CTL_376_DATA 0x00000505 +#define DDRSS_CTL_377_DATA 0x02020200 +#define DDRSS_CTL_378_DATA 0x02020202 +#define DDRSS_CTL_379_DATA 0x02020202 +#define DDRSS_CTL_380_DATA 0x02020202 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x04000100 +#define DDRSS_CTL_384_DATA 0x1E000004 +#define DDRSS_CTL_385_DATA 0x000030C0 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x0000DB60 +#define DDRSS_CTL_391_DATA 0x0001E780 +#define DDRSS_CTL_392_DATA 0x0C0D0302 +#define DDRSS_CTL_393_DATA 0x001E090A +#define DDRSS_CTL_394_DATA 0x000030C0 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x0000DB60 +#define DDRSS_CTL_400_DATA 0x0001E780 +#define DDRSS_CTL_401_DATA 0x0C0D0302 +#define DDRSS_CTL_402_DATA 0x001E090A +#define DDRSS_CTL_403_DATA 0x000030C0 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x0000DB60 +#define DDRSS_CTL_409_DATA 0x0001E780 +#define DDRSS_CTL_410_DATA 0x0C0D0302 +#define DDRSS_CTL_411_DATA 0x0000090A +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x00000000 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000A00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000000 +#define DDRSS_PI_12_DATA 0x00000000 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x00000000 +#define DDRSS_PI_15_DATA 0x00010001 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x280D0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x00060602 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x00000055 +#define DDRSS_PI_36_DATA 0x000000AA +#define DDRSS_PI_37_DATA 0x000000AD +#define DDRSS_PI_38_DATA 0x00000052 +#define DDRSS_PI_39_DATA 0x0000006A +#define DDRSS_PI_40_DATA 0x00000095 +#define DDRSS_PI_41_DATA 0x00000095 +#define DDRSS_PI_42_DATA 0x000000AD +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000014 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x00000000 +#define DDRSS_PI_55_DATA 0x00010000 +#define DDRSS_PI_56_DATA 0x00000000 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x00001400 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x01000000 +#define DDRSS_PI_63_DATA 0x00000404 +#define DDRSS_PI_64_DATA 0x00000001 +#define DDRSS_PI_65_DATA 0x0001010E +#define DDRSS_PI_66_DATA 0x02040100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000005 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x04000100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000300 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010100 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00027100 +#define DDRSS_PI_137_DATA 0x00061A80 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00007800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00141414 +#define DDRSS_PI_167_DATA 0x0000003A +#define DDRSS_PI_168_DATA 0x0000003A +#define DDRSS_PI_169_DATA 0x0004003A +#define DDRSS_PI_170_DATA 0x04000400 +#define DDRSS_PI_171_DATA 0xC8040009 +#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_173_DATA 0x00091CC8 +#define DDRSS_PI_174_DATA 0x001CC804 +#define DDRSS_PI_175_DATA 0x00000118 +#define DDRSS_PI_176_DATA 0x00001860 +#define DDRSS_PI_177_DATA 0x00000118 +#define DDRSS_PI_178_DATA 0x00001860 +#define DDRSS_PI_179_DATA 0x00000118 +#define DDRSS_PI_180_DATA 0x04001860 +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001901 +#define DDRSS_PI_183_DATA 0x00190019 +#define DDRSS_PI_184_DATA 0x010C010C +#define DDRSS_PI_185_DATA 0x0000010C +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05000000 +#define DDRSS_PI_188_DATA 0x01010505 +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x00181818 +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x0D000000 +#define DDRSS_PI_194_DATA 0x0A0A0D0D +#define DDRSS_PI_195_DATA 0x0303030A +#define DDRSS_PI_196_DATA 0x00000000 +#define DDRSS_PI_197_DATA 0x00000000 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x00000000 +#define DDRSS_PI_200_DATA 0x00000000 +#define DDRSS_PI_201_DATA 0x00000000 +#define DDRSS_PI_202_DATA 0x00000000 +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x00000000 +#define DDRSS_PI_206_DATA 0x00000000 +#define DDRSS_PI_207_DATA 0x00000000 +#define DDRSS_PI_208_DATA 0x00000000 +#define DDRSS_PI_209_DATA 0x0D090000 +#define DDRSS_PI_210_DATA 0x0D09000D +#define DDRSS_PI_211_DATA 0x0D09000D +#define DDRSS_PI_212_DATA 0x0000000D +#define DDRSS_PI_213_DATA 0x00000000 +#define DDRSS_PI_214_DATA 0x00000000 +#define DDRSS_PI_215_DATA 0x00000000 +#define DDRSS_PI_216_DATA 0x00000000 +#define DDRSS_PI_217_DATA 0x16000000 +#define DDRSS_PI_218_DATA 0x001600C8 +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x010100C8 +#define DDRSS_PI_221_DATA 0x00001B01 +#define DDRSS_PI_222_DATA 0x1F0F0053 +#define DDRSS_PI_223_DATA 0x05000001 +#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_225_DATA 0x1F0F0053 +#define DDRSS_PI_226_DATA 0x05000001 +#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_228_DATA 0x1F0F0053 +#define DDRSS_PI_229_DATA 0x05000001 +#define DDRSS_PI_230_DATA 0x00010A0D +#define DDRSS_PI_231_DATA 0x0C0B0700 +#define DDRSS_PI_232_DATA 0x000D0605 +#define DDRSS_PI_233_DATA 0x0000C570 +#define DDRSS_PI_234_DATA 0x0000001D +#define DDRSS_PI_235_DATA 0x180A0800 +#define DDRSS_PI_236_DATA 0x0B071C1C +#define DDRSS_PI_237_DATA 0x0D06050C +#define DDRSS_PI_238_DATA 0x0000C570 +#define DDRSS_PI_239_DATA 0x0000001D +#define DDRSS_PI_240_DATA 0x180A0800 +#define DDRSS_PI_241_DATA 0x0B071C1C +#define DDRSS_PI_242_DATA 0x0D06050C +#define DDRSS_PI_243_DATA 0x0000C570 +#define DDRSS_PI_244_DATA 0x0000001D +#define DDRSS_PI_245_DATA 0x180A0800 +#define DDRSS_PI_246_DATA 0x00001C1C +#define DDRSS_PI_247_DATA 0x000030C0 +#define DDRSS_PI_248_DATA 0x0001E780 +#define DDRSS_PI_249_DATA 0x000030C0 +#define DDRSS_PI_250_DATA 0x0001E780 +#define DDRSS_PI_251_DATA 0x000030C0 +#define DDRSS_PI_252_DATA 0x0001E780 +#define DDRSS_PI_253_DATA 0x02550255 +#define DDRSS_PI_254_DATA 0x03030255 +#define DDRSS_PI_255_DATA 0x00025503 +#define DDRSS_PI_256_DATA 0x02550255 +#define DDRSS_PI_257_DATA 0x0C080C08 +#define DDRSS_PI_258_DATA 0x00000C08 +#define DDRSS_PI_259_DATA 0x000890B8 +#define DDRSS_PI_260_DATA 0x00000000 +#define DDRSS_PI_261_DATA 0x00000000 +#define DDRSS_PI_262_DATA 0x00000000 +#define DDRSS_PI_263_DATA 0x00000120 +#define DDRSS_PI_264_DATA 0x000890B8 +#define DDRSS_PI_265_DATA 0x00000000 +#define DDRSS_PI_266_DATA 0x00000000 +#define DDRSS_PI_267_DATA 0x00000000 +#define DDRSS_PI_268_DATA 0x00000120 +#define DDRSS_PI_269_DATA 0x000890B8 +#define DDRSS_PI_270_DATA 0x00000000 +#define DDRSS_PI_271_DATA 0x00000000 +#define DDRSS_PI_272_DATA 0x00000000 +#define DDRSS_PI_273_DATA 0x02000120 +#define DDRSS_PI_274_DATA 0x00000080 +#define DDRSS_PI_275_DATA 0x00020000 +#define DDRSS_PI_276_DATA 0x00000080 +#define DDRSS_PI_277_DATA 0x00020000 +#define DDRSS_PI_278_DATA 0x00000080 +#define DDRSS_PI_279_DATA 0x00000000 +#define DDRSS_PI_280_DATA 0x00000000 +#define DDRSS_PI_281_DATA 0x00040404 +#define DDRSS_PI_282_DATA 0x00000000 +#define DDRSS_PI_283_DATA 0x02010102 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000202 +#define DDRSS_PI_286_DATA 0x00000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x00000000 +#define DDRSS_PI_289_DATA 0x00000000 +#define DDRSS_PI_290_DATA 0x00000000 +#define DDRSS_PI_291_DATA 0x0D100F00 +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000424 +#define DDRSS_PI_298_DATA 0x00000301 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000000 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00001401 +#define DDRSS_PI_303_DATA 0x00000493 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000424 +#define DDRSS_PI_306_DATA 0x00000301 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x00000000 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00001401 +#define DDRSS_PI_311_DATA 0x00000493 +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x00000424 +#define DDRSS_PI_314_DATA 0x00000301 +#define DDRSS_PI_315_DATA 0x00000000 +#define DDRSS_PI_316_DATA 0x00000000 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00001401 +#define DDRSS_PI_319_DATA 0x00000493 +#define DDRSS_PI_320_DATA 0x00000000 +#define DDRSS_PI_321_DATA 0x00000424 +#define DDRSS_PI_322_DATA 0x00000301 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000000 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00001401 +#define DDRSS_PI_327_DATA 0x00000493 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000424 +#define DDRSS_PI_330_DATA 0x00000301 +#define DDRSS_PI_331_DATA 0x00000000 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00001401 +#define DDRSS_PI_335_DATA 0x00000493 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000424 +#define DDRSS_PI_338_DATA 0x00000301 +#define DDRSS_PI_339_DATA 0x00000000 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00001401 +#define DDRSS_PI_343_DATA 0x00000493 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PHY_0_DATA 0x04C00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00000200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x00000000 +#define DDRSS_PHY_6_DATA 0x00000000 +#define DDRSS_PHY_7_DATA 0x00000000 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x010101FF +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00004 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660201 +#define DDRSS_PHY_16_DATA 0x00000000 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00070820 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CCB001 +#define DDRSS_PHY_75_DATA 0x2000CCB0 +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x10100303 +#define DDRSS_PHY_80_DATA 0x10101010 +#define DDRSS_PHY_81_DATA 0x10101010 +#define DDRSS_PHY_82_DATA 0x00021010 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51515041 +#define DDRSS_PHY_89_DATA 0x31804000 +#define DDRSS_PHY_90_DATA 0x04BF0340 +#define DDRSS_PHY_91_DATA 0x01008080 +#define DDRSS_PHY_92_DATA 0x04050001 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C14 +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x76543210 +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x02800280 +#define DDRSS_PHY_106_DATA 0x02800280 +#define DDRSS_PHY_107_DATA 0x02800280 +#define DDRSS_PHY_108_DATA 0x02800280 +#define DDRSS_PHY_109_DATA 0x00000280 +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01000080 +#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x00000000 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04C00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00000200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x00000000 +#define DDRSS_PHY_262_DATA 0x00000000 +#define DDRSS_PHY_263_DATA 0x00000000 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x010101FF +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00004 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660201 +#define DDRSS_PHY_272_DATA 0x00000000 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00070820 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CCB001 +#define DDRSS_PHY_331_DATA 0x2000CCB0 +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x10100303 +#define DDRSS_PHY_336_DATA 0x10101010 +#define DDRSS_PHY_337_DATA 0x10101010 +#define DDRSS_PHY_338_DATA 0x00021010 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51515041 +#define DDRSS_PHY_345_DATA 0x31804000 +#define DDRSS_PHY_346_DATA 0x04BF0340 +#define DDRSS_PHY_347_DATA 0x01008080 +#define DDRSS_PHY_348_DATA 0x04050001 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C14 +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x76543210 +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x02800280 +#define DDRSS_PHY_362_DATA 0x02800280 +#define DDRSS_PHY_363_DATA 0x02800280 +#define DDRSS_PHY_364_DATA 0x02800280 +#define DDRSS_PHY_365_DATA 0x00000280 +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01000080 +#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x00000000 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000100 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000000 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x00000000 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x00000000 +#define DDRSS_PHY_527_DATA 0x00000000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x00000000 +#define DDRSS_PHY_533_DATA 0x00000000 +#define DDRSS_PHY_534_DATA 0x00000000 +#define DDRSS_PHY_535_DATA 0x00000000 +#define DDRSS_PHY_536_DATA 0x00000000 +#define DDRSS_PHY_537_DATA 0x00000000 +#define DDRSS_PHY_538_DATA 0x00000000 +#define DDRSS_PHY_539_DATA 0x00000000 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x103F0000 +#define DDRSS_PHY_542_DATA 0x000F0100 +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000003E +#define DDRSS_PHY_553_DATA 0x00000000 +#define DDRSS_PHY_554_DATA 0x00000000 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000100 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000000 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x00000000 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x00000000 +#define DDRSS_PHY_783_DATA 0x00000000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x00000000 +#define DDRSS_PHY_789_DATA 0x00000000 +#define DDRSS_PHY_790_DATA 0x00000000 +#define DDRSS_PHY_791_DATA 0x00000000 +#define DDRSS_PHY_792_DATA 0x00000000 +#define DDRSS_PHY_793_DATA 0x00000000 +#define DDRSS_PHY_794_DATA 0x00000000 +#define DDRSS_PHY_795_DATA 0x00000000 +#define DDRSS_PHY_796_DATA 0x16A4A0E6 +#define DDRSS_PHY_797_DATA 0x103F0000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000003E +#define DDRSS_PHY_809_DATA 0x00000000 +#define DDRSS_PHY_810_DATA 0x00000000 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000100 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000000 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00000000 +#define DDRSS_PHY_1036_DATA 0x00000000 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x00000000 +#define DDRSS_PHY_1039_DATA 0x00000000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x00000000 +#define DDRSS_PHY_1046_DATA 0x00000000 +#define DDRSS_PHY_1047_DATA 0x00000000 +#define DDRSS_PHY_1048_DATA 0x00000000 +#define DDRSS_PHY_1049_DATA 0x00000000 +#define DDRSS_PHY_1050_DATA 0x00000000 +#define DDRSS_PHY_1051_DATA 0x00000000 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10030000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000003E +#define DDRSS_PHY_1065_DATA 0x00000000 +#define DDRSS_PHY_1066_DATA 0x00000000 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000100 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x01002000 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x00010100 +#define DDRSS_PHY_1297_DATA 0x00000001 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00040000 +#define DDRSS_PHY_1312_DATA 0x00005201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07070001 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000046 +#define DDRSS_PHY_1334_DATA 0x00000400 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543210 +#define DDRSS_PHY_1360_DATA 0x00000098 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000100 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020400 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03900390 +#define DDRSS_PHY_1382_DATA 0x03900390 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x31823FC7 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000D3F +#define DDRSS_PHY_1390_DATA 0x30000D3F +#define DDRSS_PHY_1391_DATA 0x300D3F11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x000D3FCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x300D3F11 +#define DDRSS_PHY_1396_DATA 0x01990000 +#define DDRSS_PHY_1397_DATA 0x300C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x300C3F11 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x300D3F11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x300D3F11 +#define DDRSS_PHY_1404_DATA 0x01990000 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi index 26567f4167ffe491d6c5d67fba669234c9870c92..1d0659ea8fff6dda99c428a527f6c6e7e63ee388 100644 --- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi @@ -198,7 +198,7 @@ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&usb0_pins_default>; - dr_mode = "host"; + dr_mode = "peripheral"; u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 24881c86f2a8b8e48564b429243bbaf1ebcd4ba3..455698a93630aa366fe40192fea12d99fbd354ff 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -309,6 +309,7 @@ &dwc3_0 { status = "okay"; u-boot,dm-spl; + /delete-property/ clocks; /delete-property/ power-domains; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 677a72d2a241567b046733ae3640a690d76a6f7d..b2b81f804db1aee6249588d39e1c865cff89fe80 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -192,6 +192,22 @@ u-boot,dm-spl; }; +&hbmc { + u-boot,dm-spl; + + flash@0,0 { + u-boot,dm-spl; + }; +}; + +&hbmc_mux { + u-boot,dm-spl; +}; + +&wkup_gpio0 { + u-boot,dm-spl; +}; + &ospi0 { u-boot,dm-spl; @@ -208,6 +224,14 @@ }; }; +&mcu_fss0_hpb0_pins_default { + u-boot,dm-spl; +}; + +&wkup_gpio_pins_default { + u-boot,dm-spl; +}; + &mcu_fss0_ospi1_pins_default { u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index f3b6302a431751ab58dadb085a9d72cc8848a3e6..1b600547c064f852241e4c93b0dfbcebca090e9a 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -213,6 +213,12 @@ >; }; + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ + >; + }; + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ @@ -381,6 +387,11 @@ phy-names = "cdns3,usb3-phy"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss1_pins_default>; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index d2dceda72fe97783b4b4c082673a137c5802e79b..22166c79425d82daf4be30f67fc93bf6dc350636 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -170,12 +170,30 @@ }; fss: fss@47000000 { - compatible = "simple-bus"; + compatible = "syscon", "simple-mfd"; reg = <0x0 0x47000000 0x0 0x100>; #address-cells = <2>; #size-cells = <2>; ranges; + hbmc_mux: hbmc-mux { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,j721e-hbmc", "ti,am654-hbmc"; + reg = <0x0 0x47034000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + assigned-clocks = <&k3_clks 102 0>; + assigned-clock-rates = <250000000>; + }; + ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index a14b148e11f11be84f6f22dbd39435adb0871408..ab9d6e65d8e2677942ace3927720eca6ce157ed6 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -129,6 +129,31 @@ >; }; + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */ + >; + }; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ @@ -207,6 +232,11 @@ status = "okay"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &mcu_uart0 { /delete-property/ power-domains; /delete-property/ clocks; @@ -307,6 +337,21 @@ }; }; +&hbmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; + ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index 2fee2906183d10b184f7795fe4332288975577a7..a7254358496e0d4a60e83ceb35281831a6e09602 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -150,6 +150,25 @@ >; }; + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ @@ -167,6 +186,19 @@ }; }; +&hbmc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index be330c130f599c56942da15006a29e6008a908e4..4f65ee765e3f228536c36ebca9315c17376483ff 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -31,17 +31,24 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; cpu@f01 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf01>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; }; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -82,6 +89,13 @@ interrupts = ; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; reg = <0x1ee0000 0x10000>; @@ -185,41 +199,10 @@ }; clockgen: clocking@1ee1000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1ee1000 0x10000>; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sysclk"; - }; - - cga_pll1: pll@800 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0x800 0x10>; - clocks = <&sysclk>; - clock-output-names = "cga-pll1", "cga-pll1-div2", - "cga-pll1-div4"; - }; - - platform_clk: pll@c00 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0xc00 0x10>; - clocks = <&sysclk>; - clock-output-names = "platform-clk", "platform-clk-div2"; - }; - - cluster1_clk: clk0c0@0 { - compatible = "fsl,qoriq-core-mux-2.0"; - #clock-cells = <0>; - reg = <0x0 0x10>; - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; - clock-output-names = "cluster1-clk"; - }; + compatible = "fsl,ls1021a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; }; dspi0: dspi@2100000 { @@ -229,7 +212,7 @@ reg = <0x2100000 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -242,7 +225,7 @@ reg = <0x2110000 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -265,7 +248,7 @@ reg = <0x2180000 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -276,7 +259,7 @@ reg = <0x2190000 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -287,7 +270,7 @@ reg = <0x21a0000 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -336,7 +319,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2960000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -345,7 +328,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2970000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -354,7 +337,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2980000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -363,7 +346,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2990000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -372,7 +355,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x29a0000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -381,7 +364,7 @@ compatible = "fsl,imx21-wdt"; reg = <0x2ad0000 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "wdog-en"; big-endian; }; @@ -390,7 +373,7 @@ compatible = "fsl,vf610-sai"; reg = <0x2b50000 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "sai"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, @@ -403,7 +386,7 @@ compatible = "fsl,vf610-sai"; reg = <0x2b60000 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "sai"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, @@ -424,8 +407,8 @@ dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&platform_clk 1>, - <&platform_clk 1>; + clocks = <&clockgen 4 1>, + <&clockgen 4 1>; }; enet0: ethernet@2d10000 { diff --git a/arch/arm/dts/omap3-devkit8000-u-boot.dtsi b/arch/arm/dts/omap3-devkit8000-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a5768b7281d57e55d2c7e0e3ad87b418a358112d --- /dev/null +++ b/arch/arm/dts/omap3-devkit8000-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * (C) Copyright 2017 Derald D. Woods + */ + +#include "omap3-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + ethernet@2c000000 { + compatible = "davicom,dm9000"; + reg = <0x2c000000 2 0x2c000400 2>; + bank-width = <2>; + }; +}; diff --git a/arch/arm/dts/omap3-devkit8000.dts b/arch/arm/dts/omap3-devkit8000.dts new file mode 100644 index 0000000000000000000000000000000000000000..eee3ba073b181428425b9d1484dc01fab9435d1e --- /dev/null +++ b/arch/arm/dts/omap3-devkit8000.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Anthoine Bourgeois + */ +/dts-v1/; + +#include "omap34xx.dtsi" +/ { + model = "TimLL OMAP3 Devkit8000"; + compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3"; + + aliases { + display1 = &dvi0; + display2 = &tv0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "devkit8000::led1"; + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "devkit8000::led2"; + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ + default-state = "on"; + linux,default-trigger = "none"; + }; + + usr { + label = "devkit8000::led3"; + gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ + default-state = "on"; + linux,default-trigger = "usr"; + }; + + pmu_stat { + label = "devkit8000::pmu_stat"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "devkit8000"; + + ti,mcbsp = <&mcbsp2>; + ti,audio-routing = + "Ext Spk", "PREDRIVEL", + "Ext Spk", "PREDRIVER", + "MAINMIC", "Main Mic", + "Main Mic", "Mic Bias 1"; + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_dvi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c2>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + status = "disabled"; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&twl_gpio { + ti,use-leds; + /* + * pulldowns: + * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c6>; +}; + +&wdt2 { + status = "disabled"; +}; + +&mcbsp2 { + status = "okay"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "sw"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; + + ethernet@6,0 { + compatible = "davicom,dm9000"; + reg = <6 0x000 2 + 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ + bank-width = <2>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + davicom,no-eeprom; + + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <0>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + gpmc,cs-on-ns = <6>; + gpmc,cs-rd-off-ns = <180>; + gpmc,cs-wr-off-ns = <180>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <144>; + gpmc,page-burst-access-ns = <24>; + gpmc,bus-turnaround-ns = <90>; + gpmc,cycle2cycle-delay-ns = <90>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; +}; + +&omap3_pmx_core { + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&vpll1 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + vdds_dsi-supply = <&vpll1>; + vdda_dac-supply = <&vdac>; + + port { + #address-cells = <1>; + #size-cells = <0>; + dpi_dvi_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + + endpoint@1 { + reg = <1>; + }; + }; +}; + +&venc { + status = "okay"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff --git a/arch/arm/dts/omap3-u-boot.dtsi b/arch/arm/dts/omap3-u-boot.dtsi index 32bea6b6d9b8c4e15f0018a6df358753a6e11c4d..96d8ac54539915c36c66299fc59fe1d228854dd8 100644 --- a/arch/arm/dts/omap3-u-boot.dtsi +++ b/arch/arm/dts/omap3-u-boot.dtsi @@ -78,4 +78,5 @@ &i2c1 { u-boot,dm-spl; + clock-frequency = <100000>; }; diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 32ffe93b4d9f2ba5e25fbc280e81c748d1b6e8ec..54c694bd78482ca457dde3716151328b68d49ee5 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -49,7 +49,7 @@ status = "okay"; nor_flash: sst26vf064@0 { - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; spi-rx-bus-width = <4>; @@ -72,7 +72,7 @@ status = "okay"; eeprom@53 { - compatible = "atmel,24c32"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x53>; pagesize = <16>; }; diff --git a/arch/arm/dts/sama5d27_som1.dtsi b/arch/arm/dts/sama5d27_som1.dtsi index ea7540bcfcf7278ba73167002a860051ddb4dc83..db4fefadcd6727ce14a98b4b50ed7da0e579901a 100644 --- a/arch/arm/dts/sama5d27_som1.dtsi +++ b/arch/arm/dts/sama5d27_som1.dtsi @@ -92,7 +92,7 @@ status = "okay"; i2c_eeprom: i2c_eeprom@50 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa02e48 */ reg = <0x50>; }; }; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 4efecdb92c7228c59854658a3a2a1f7862a0753d..97400dc18e7678121de6d016ca673f0792e43fe0 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -33,6 +33,7 @@ reg = <0x0>; clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>; clock-names = "cpu", "master", "xtal"; + operating-points-v2 = <&cpu_opp_table>; }; }; @@ -225,7 +226,7 @@ status = "disabled"; }; - rtt: rtt@e001d020 { + rtt: rtc@e001d020 { compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xe001d020 0x30>; interrupts = ; @@ -490,6 +491,30 @@ status = "disabled"; }; + pdmc0: sound@e1608000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe1608000 0x1000>; + interrupts = ; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + pdmc1: sound@e160c000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe160c000 0x1000>; + interrupts = ; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + spdifrx: spdifrx@e1614000 { #sound-dai-cells = <0>; compatible = "microchip,sama7g5-spdifrx"; @@ -628,9 +653,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -814,9 +839,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, - <&dma0 AT91_XDMAC_DT_PERID(22)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -838,9 +863,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, - <&dma0 AT91_XDMAC_DT_PERID(24)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -885,7 +910,6 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - interrupt-parent; reg = <0xe8c11000 0x1000>, <0xe8c12000 0x2000>; }; diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d2472cd8f1d03126be8a928a692078567928193c --- /dev/null +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue + */ +#include + +&pinctrl { + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..1b5b3586905f182c1d5834388dc23ef71ae9b2c8 --- /dev/null +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + pinctrl0 = &pinctrl; + }; + + /* need PSCI for sysreset during board_f */ + psci { + u-boot,dm-pre-proper; + }; + + soc { + u-boot,dm-pre-reloc; + + ddr: ddr@5a003000 { + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp13-ddr"; + + reg = <0x5A003000 0x550 + 0x5A004000 0x234>; + + status = "okay"; + }; + }; +}; + +&bsec { + u-boot,dm-pre-reloc; +}; + +&gpioa { + u-boot,dm-pre-reloc; +}; + +&gpiob { + u-boot,dm-pre-reloc; +}; + +&gpioc { + u-boot,dm-pre-reloc; +}; + +&gpiod { + u-boot,dm-pre-reloc; +}; + +&gpioe { + u-boot,dm-pre-reloc; +}; + +&gpiof { + u-boot,dm-pre-reloc; +}; + +&gpiog { + u-boot,dm-pre-reloc; +}; + +&gpioh { + u-boot,dm-pre-reloc; +}; + +&gpioi { + u-boot,dm-pre-reloc; +}; + +&iwdg2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..950e172e455f8a9988a0c2a5c2276f02a9cab275 --- /dev/null +++ b/arch/arm/dts/stm32mp131.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + clocks { + clk_axi: clk-axi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <266500000>; + }; + + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_pclk3: clk-pclk3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104438965>; + }; + + clk_pclk4: clk-pclk4 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <133250000>; + }; + + clk_pll4_p: clk-pll4_p { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + clk_pll4_r: clk-pll4_r { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <99000000>; + }; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts = ; + clocks = <&clk_hsi>; + status = "disabled"; + }; + + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + clocks = <&clk_pclk4>; + #dma-cells = <3>; + dma-masters = <&dma1 &dma2>; + dma-requests = <128>; + dma-channels = <16>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&clk_pclk3>; + }; + + mdma: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&clk_pclk4>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&clk_pll4_p>; + clock-names = "apb_pclk"; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&clk_pll4_p>; + clock-names = "apb_pclk"; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&clk_pclk4>, <&clk_lsi>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + bsec: efuse@5c005000 { + compatible = "st,stm32mp13-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp: part_number_otp@4 { + reg = <0x4 0x2>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + }; + + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pin-controller@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp135-pinctrl"; + ranges = <0 0x50002000 0x8400>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOH"; + ngpios = <15>; + gpio-ranges = <&pinctrl 0 112 15>; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOI"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 128 8>; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0fb1386257cfababd413f6bf9ad29e6f634cb493 --- /dev/null +++ b/arch/arm/dts/stm32mp133.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp131.dtsi" + +/ { + soc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clk_hse>, <&clk_pll4_r>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clk_hse>, <&clk_pll4_r>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..abf2acd37b4ea01b819dd03ab050fea5a0f30490 --- /dev/null +++ b/arch/arm/dts/stm32mp135.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp133.dtsi" + +/ { + soc { + }; +}; diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..dfe5bbb2e34b615dea2215291b1f02ee1302f344 --- /dev/null +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#include "stm32mp13-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + }; + + config { + u-boot,mmc-env-partition = "u-boot-env"; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts new file mode 100644 index 0000000000000000000000000000000000000000..ee100d108ea2116f8492515e0252b58dee2280bc --- /dev/null +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + serial0 = &uart4; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + vdd_sd: vdd-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..fa6889e30591304f0421bf4a16de3e5fa94afba6 --- /dev/null +++ b/arch/arm/dts/stm32mp13xc.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&clk_axi>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..fa6889e30591304f0421bf4a16de3e5fa94afba6 --- /dev/null +++ b/arch/arm/dts/stm32mp13xf.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&clk_axi>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 9495911397eb9096cb38e54e2b1b8aa843a60ee8..37155df0fd42db3c995a557321a6220783b8aa5a 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -287,7 +287,7 @@ reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; }; nor0: flash@1,0 { status = "disabled"; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 726183782305b9569b627af35d5e94ba3652242c..37c56181c9cb5702cc1578b1d731ba0b411afe92 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -294,10 +294,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ + clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ - reg = <0xd8>; + reg = <0x6c>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; @@ -447,7 +447,7 @@ si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5f>; + reg = <0x5d>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index ee530ba3e1476091d20e00ae8dac5f1b8559e667..e00428351cbfdf8011b9271c2d981621ab170ba7 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -260,9 +260,9 @@ reg = <0x45>; shunt-resistor = <5000>; }; - tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ + tps53681@60 { /* u53 - 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; - reg = <0xc0>; + reg = <0x60>; }; }; i2c@3 { /* fmc1 via JA2G */ diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 7b3722f0808b21caa94a87394e7eeb90b2fe5051..1fa023ffb13cbc0b32161342eac1381b533fd4b0 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -247,9 +247,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - reg_vccint: tps53681@c0 { /* u69 */ + reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; - reg = <0xc0>; + reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 11b2a58a0f060d56d18d2528c17957182a068aa4..2271a6a49065ec17b199caebb43e47fb0b62b83d 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -190,10 +190,6 @@ compatible = "ti,tps544b25"; reg = <0x1e>; }; - reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ - compatible = "ti,tps544b25"; - reg = <0x17>; /* FIXME wrong in schematics */ - }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; @@ -239,9 +235,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - reg_vccint: tps53681@c0 { /* u69 */ + reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; - reg = <0xc0>; + reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index db199c467b0d5f27407e397f711cb2da9d91cb8a..a89046a818fd8abe9c88dd44f5f1d063c33e23a4 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -190,9 +190,9 @@ compatible = "ti,tps544b25"; reg = <0x1e>; }; - reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ + reg_vcc1v2_ddr4: tps544@18 { /* u3022 */ compatible = "ti,tps544b25"; - reg = <0x17>; /* FIXME wrong in schematics */ + reg = <0x18>; }; }; i2c@1 { /* PMBUS_INA226 */ @@ -239,9 +239,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - reg_vccint: tps53681@c0 { /* u69 */ + reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; - reg = <0xc0>; + reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts new file mode 100644 index 0000000000000000000000000000000000000000..735c1e3d1a88a02cb9ead47e3d05a181932c63f3 --- /dev/null +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revA Carrier Card + * + * (C) Copyright 2021, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revA", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + si5332_0: si5332_0 { /* u17 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + si5332_1: si5332_1 { /* u17 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + si5332_2: si5332_2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_3: si5332_3 { /* u17 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + si5332_4: si5332_4 { /* u17 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_5: si5332_5 { /* u17 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub0: usb-hub { /* u43 */ + i2c-bus = <&usbhub_i2c0>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + usb2244: usb-sd { /* u38 */ + compatible = "microchip,usb2244"; + reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub1: usb-hub { /* u84 */ + i2c-bus = <&usbhub_i2c1>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + is-internal-pcspma; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts new file mode 100644 index 0000000000000000000000000000000000000000..63590619d43e3fbe921cee59b68f679d847ee53a --- /dev/null +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revB Carrier Card (A03 revision) + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revB", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_125: clock0 { /* u87 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_27: clock1 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_26: clock2 { /* u89 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_156: clock3 { /* u90 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&clk_125>, <&clk_27>, <&clk_26>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub0: usb-hub { /* u43 */ + i2c-bus = <&usbhub_i2c0>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + usb2244: usb-sd { /* u38 */ + compatible = "microchip,usb2244"; + reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub1: usb-hub { /* u84 */ + i2c-bus = <&usbhub_i2c1>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + is-internal-pcspma; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 85994bef7cc03f9f32c2356a1509c33c58c9aeca..b714bd3eb1b1d0d18385cb3bcbb8e97ff4e0d606 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -112,7 +112,7 @@ }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; @@ -285,19 +285,22 @@ pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index b81c2e6b7543d6535685572fcd43bd66a7f230b5..a1d8f9f0e51f3e299f49b94f087d0be6a701b3d3 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -272,19 +272,22 @@ pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index d20f6675687bfc366a3d0f5b40d3f1edd8d3f9ee..7ea2a1c96f4e02cbde859772bcb85208459421c1 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -187,19 +187,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index f32f87acacb6f6981f0ad4a66b15351def4c7fcd..4e6160bcd8b96a14d6189b7aca59223597648f3c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -335,19 +335,22 @@ conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index ea630a43dc7f8cd18ae9d2f38202f8267ddfb74e..5e7bc7384fceb4963b0940b1cb7b046e2a4525cc 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -441,19 +441,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -465,19 +468,22 @@ conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index c13b52a6aeaac0c88aac6b862593b09645407a05..a4e92c8bb16b747a635fddf8aefbff5e9cb4f67c 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -795,19 +795,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 50bf479089135afa0a00bf5fd4d0d4b78b65ff6f..1418cffb20422c6971cccbe2681a957255a2cba2 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -402,20 +402,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 752a9e38f3d34845432059256b778bcdb7a36c6b..7fd19ca3a8c0be1c8d02640b46f2872f31553b7b 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -414,20 +414,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 6dfc8fe17bf218ae2501d75b55f8c9d9fa4f87f1..3e137676feb6a24c10b3766c6b2b7579986ac505 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -793,19 +793,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 021fe88670fb8af4f05da562a1e5b02c414f8efe..e412992ff1bd45c352b8f2db7eb7afcf8e60cf47 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -652,19 +652,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h index 7c5aab98b636104a1cbf0abbf3892b23d0ff73b9..251bfa269bf43f9d0c7509531514be08906e7842 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -87,6 +87,9 @@ #define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8 #define SCU_HWSTRAP1_MAC2_INTF BIT(7) #define SCU_HWSTRAP1_MAC1_INTF BIT(6) +#define SCU_HWSTRAP1_BOOT_EMMC BIT(2) + +#define SCU_HWSTRAP2_BOOT_UART BIT(8) #define SCU_EFUSE_DIS_DP BIT(17) #define SCU_EFUSE_DIS_VGA BIT(14) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1315bebb56f7c76155a2841ba501b445198f2445..cd795d6919ac49607e306a7e36e3634776860e2f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -55,17 +55,6 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -160,17 +149,6 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 @@ -215,17 +193,6 @@ /* SMMU Definitions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -274,20 +241,9 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - /* SEC */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -321,11 +277,6 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION /* SMMU Defintions */ #define SMMU_BASE 0x09000000 @@ -361,11 +312,6 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -380,11 +326,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 06adf669390f2041011978141ac6bf70d85c8a45..f2dbcdc8164fcdea6961271578392e0a49c8f708 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -13,10 +13,8 @@ #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) -#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) @@ -26,9 +24,7 @@ #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) -#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) @@ -37,7 +33,6 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) @@ -142,25 +137,6 @@ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ #define TP_INIT_PER_CLUSTER 4 -/* - * Define default values for some CCSR macros to make header files cleaner* - * - * To completely disable CCSR relocation in a board header file, define - * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. - */ - -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ -CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." -#endif - -#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 -#endif - #ifndef CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR 0x01000000 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 863618a5f3d0a65a00eeb96946b5cb5f9e9b4f88..570397b3c04ca757c2b474bafbd2c065a4046f2c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -52,7 +52,6 @@ #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL -#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) @@ -230,6 +229,10 @@ #define DCFG_BASE 0x01e00000 #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000 +#define DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000 +#define DCFG_PORSR1_RCW_SRC_I2C 0x05000000 +#define DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR12 0x12c #define DCFG_RCWSR12_SDHC_SHIFT 24 diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 653792c610cb7420ac9d2f48a65aee51b0961f47..32d68cbeb81af0ca50c6a4cd2c3023a1531ef9a4 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -52,11 +52,7 @@ /* USB OHCI */ #if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" #endif #endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 3b1d9a3f0c405a775682331b44cca7d242a65eb7..e5f61ea4a6ee65cc3b014834a828cb7a501647d5 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -32,15 +32,11 @@ #define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 -#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) @@ -80,23 +76,17 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_SEC_MON_LE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE #define DCU_LAYER_MAX_NUM 16 #ifdef CONFIG_ARCH_LS1021A -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index f2ba182346ef2429eac64155482d593320f2b87b..b0acf677984bd7ba5439e189b36ffd659538396d 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -42,24 +42,6 @@ #define DCFG_DCSR_PORCR1 0 -/* - * Define default values for some CCSR macros to make header files cleaner - * - * To completely disable CCSR relocation in a board header file, define - * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. - */ - -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." -#endif - -#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 -#endif - #ifndef CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR #endif diff --git a/arch/arm/include/asm/arch-npcm7xx/aes.h b/arch/arm/include/asm/arch-npcm7xx/aes.h new file mode 100644 index 0000000000000000000000000000000000000000..255efcb5ce09c85eedd0fdb37cf4c6effae36876 --- /dev/null +++ b/arch/arm/include/asm/arch-npcm7xx/aes.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _NPCM_AES_H_ +#define _NPCM_AES_H_ + +#define AES_OP_ENCRYPT 0 +#define AES_OP_DECRYPT 1 +#define SIZE_AES_BLOCK (AES128_KEY_LENGTH) + +struct npcm_aes_regs { + unsigned char reserved_0[0x400]; // 0x000 + unsigned int aes_key_0; // 0x400 + unsigned int aes_key_1; // 0x404 + unsigned int aes_key_2; // 0x408 + unsigned int aes_key_3; // 0x40c + unsigned char reserved_1[0x30]; // 0x410 + unsigned int aes_iv_0; // 0x440 + unsigned char reserved_2[0x1c]; // 0x444 + unsigned int aes_ctr_0; // 0x460 + unsigned char reserved_3[0x0c]; // 0x464 + unsigned int aes_busy; // 0x470 + unsigned char reserved_4[0x04]; // 0x474 + unsigned int aes_sk; // 0x478 + unsigned char reserved_5[0x14]; // 0x47c + unsigned int aes_prev_iv_0; // 0x490 + unsigned char reserved_6[0x0c]; // 0x494 + unsigned int aes_din_dout; // 0x4a0 + unsigned char reserved_7[0x1c]; // 0x4a4 + unsigned int aes_control; // 0x4c0 + unsigned int aes_version; // 0x4c4 + unsigned int aes_hw_flags; // 0x4c8 + unsigned char reserved_8[0x28]; // 0x4cc + unsigned int aes_sw_reset; // 0x4f4 + unsigned char reserved_9[0x08]; // 0x4f8 + unsigned int aes_fifo_data; // 0x500 + unsigned char reserved_10[0xfc]; // 0x504 + unsigned int aes_fifo_status; // 0x600 +}; + +#define AES_BUSY_BIT BIT(0) +#define SW_RESET_BIT BIT(0) +#define AES_SK_BIT BIT(0) + +#define DIN_FIFO_FULL BIT(0) +#define DIN_FIFO_EMPTY BIT(1) +#define DOUT_FIFO_FULL BIT(2) +#define DOUT_FIFO_EMPTY BIT(3) +#define DIN_FIFO_OVERFLOW BIT(4) +#define DOUT_FIFO_UNDERFLOW BIT(5) + +int npcm_aes_select_key(u8 fkeyind); + +#endif diff --git a/arch/arm/include/asm/arch-npcm7xx/otp.h b/arch/arm/include/asm/arch-npcm7xx/otp.h new file mode 100644 index 0000000000000000000000000000000000000000..11d1e8550c9a6408c0191968e7e906eaa4f1d2af --- /dev/null +++ b/arch/arm/include/asm/arch-npcm7xx/otp.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _NPCM_OTP_H_ +#define _NPCM_OTP_H_ + +#ifdef CONFIG_ARCH_NPCM8XX +enum { + NPCM_KEY_SA = 0, + NPCM_FUSE_SA = 0, + NPCM_NUM_OF_SA = 1 +}; +#else +enum { + NPCM_KEY_SA = 0, + NPCM_FUSE_SA = 1, + NPCM_NUM_OF_SA = 2 +}; +#endif + +struct npcm_otp_regs { + unsigned int fst; + unsigned int faddr; + unsigned int fdata; + unsigned int fcfg; + unsigned int fustrap_fkeyind; + unsigned int fctl; +}; + +#define FST_RDY BIT(0) +#define FST_RDST BIT(1) +#define FST_RIEN BIT(2) + +#ifdef CONFIG_ARCH_NPCM8XX +#define FADDR_BYTEADDR(addr) ((addr) << 3) +#define FADDR_BITPOS(pos) ((pos) << 0) +#define FADDR_VAL(addr, pos) (FADDR_BITPOS(pos) | FADDR_BYTEADDR(addr)) +#define FADDR_IN_PROG BIT(16) +#else +#define FADDR_BYTEADDR(addr) ((addr) << 0) +#define FADDR_BITPOS(pos) ((pos) << 10) +#define FADDR_VAL(addr, pos) (FADDR_BYTEADDR(addr) | FADDR_BITPOS(pos)) +#define FADDR_IN_PROG BIT(16) +#endif + +#define FDATA_MASK (0xff) + +#define FUSTRAP_O_SECBOOT BIT(23) + +#define FCFG_FDIS BIT(31) + +#define FKEYIND_KVAL BIT(0) +#define FKEYIND_KSIZE_MASK (0x00000070) +#define FKEYIND_KSIZE_128 (0x40) +#define FKEYIND_KSIZE_192 (0x50) +#define FKEYIND_KSIZE_256 (0x60) +#define FKEYIND_KIND_MASK (0x000c0000) +#define FKEYIND_KIND_KEY(indx) ((indx) << 18) + +// Program cycle initiation values (sequence of two adjacent writes) +#define PROGRAM_ARM 0x1 +#define PROGRAM_INIT 0xBF79E5D0 + +#define OTP2_BASE 0xF018A000 +#define FUSTRAP (OTP2_BASE + 0x10) + +// Read cycle initiation value +#define READ_INIT 0x02 + +// Value to clean FDATA contents +#define FDATA_CLEAN_VALUE 0x01 + +#ifdef CONFIG_ARCH_NPCM8XX +#define NPCM_OTP_ARR_BYTE_SIZE 8192 +#else +#define NPCM_OTP_ARR_BYTE_SIZE 1024 +#endif + +#define MIN_PROGRAM_PULSES 4 +#define MAX_PROGRAM_PULSES 20 +#define NPCM_OTP_ARR_BYTE_SIZE 1024 + +int fuse_prog_image(u32 bank, uintptr_t address); +int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size); +int npcm_otp_select_key(u8 key_index); +bool npcm_otp_is_fuse_array_disabled(u32 arr); +void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size); +void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size); +void npcm_arch_preboot_os(void); + +#endif diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index 0a626fe647a293584dcb909d42fc0829511c96d9..4054dd8edcbc734837013201dbc100aa8d324ba6 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -7,7 +7,6 @@ */ #ifndef _CLOCKS_OMAP4_H_ #define _CLOCKS_OMAP4_H_ -#include /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index a00626e357c960224e39636d75aa62331122431e..b18ef459decc48a48eda45d97937fd48c9babaef 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -8,7 +8,6 @@ */ #ifndef _CLOCKS_OMAP5_H_ #define _CLOCKS_OMAP5_H_ -#include /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per diff --git a/arch/arm/include/asm/arch-pxa/bitfield.h b/arch/arm/include/asm/arch-pxa/bitfield.h deleted file mode 100644 index 104a21c2e47d17f58c6eeedc687dd4ae2367dfe3..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/arch/arm/include/asm/arch-pxa/config.h b/arch/arm/include/asm/arch-pxa/config.h deleted file mode 100644 index 75b0e491ed5bba21423816bf2db550fac43d4f10..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/config.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Andrew Ruder - */ - -#ifndef _ASM_ARM_PXA_CONFIG_ -#define _ASM_ARM_PXA_CONFIG_ - -#include - -/* - * Generic timer support - */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define CONFIG_SYS_TIMER_RATE 3250000 -#elif defined(CONFIG_CPU_PXA25X) -#define CONFIG_SYS_TIMER_RATE 3686400 -#else -#error "Timer frequency unknown - please config PXA CPU type" -#endif - -#define CONFIG_SYS_TIMER_COUNTER OSCR - -#endif /* _ASM_ARM_PXA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h deleted file mode 100644 index 6d0023d7b8650d27f80e2240d613c57c96506b82..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: This file was taken from linux-2.4.19-rmk4-pxa1 - * - * - 2003/01/20 implementation specifics activated - * Robert Schwebel - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -/* - * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. - * PXA300/310/320 all have distinct register mappings in some cases, that's why - * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common - * drivers and compatibility glue with old source then. - */ -#ifndef CONFIG_CPU_MONAHANS -#if defined(CONFIG_CPU_PXA300) || \ - defined(CONFIG_CPU_PXA310) || \ - defined(CONFIG_CPU_PXA320) -#define CONFIG_CPU_MONAHANS -#endif -#endif - -/* - * These are statically mapped PCMCIA IO space for designs using it as a - * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. - * The actual PCMCIA code is mapping required IO region at run time. - */ -#define PCMCIA_IO_0_BASE 0xf6000000 -#define PCMCIA_IO_1_BASE 0xf7000000 - - -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xff000000 -#define UNCACHED_ADDR UNCACHED_PHYS_0 - -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -#include "pxa-regs.h" - -#ifndef __ASSEMBLY__ - -/* - * GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * This must be called *before* the corresponding IRQ is registered. - * Use this instead of directly setting GRER/GFER. - */ -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 - -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h deleted file mode 100644 index b81b42c07c7479b49c05b2085cd6132899faffe4..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ /dev/null @@ -1,2635 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/pxa-regs.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - 2003/01/20: Robert Schwebel */ -#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */ - -#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */ - -#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */ - -#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */ - -#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */ - -#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */ - -#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ -#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#ifdef CONFIG_CPU_MONAHANS -#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) -#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) -#endif - -#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) -#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) -#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) -#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) -#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) -#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) -#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) -#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) -#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) -#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) -#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) -#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) -#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) -#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) -#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) -#else -#define GPLR(x) _GPLR(x) -#define GPDR(x) _GPDR(x) -#define GPSR(x) _GPSR(x) -#define GPCR(x) _GPCR(x) -#define GRER(x) _GRER(x) -#define GFER(x) _GFER(x) -#define GEDR(x) _GEDR(x) -#define GAFR(x) _GAFR(x) -#endif - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -/******************************************************************************/ -/* - * Multi-function Pin Registers: - */ -/* PXA320 */ -#if defined(CONFIG_CPU_PXA320) -#define DF_IO0 0x40e1024c -#define DF_IO1 0x40e10254 -#define DF_IO2 0x40e1025c -#define DF_IO3 0x40e10264 -#define DF_IO4 0x40e1026c -#define DF_IO5 0x40e10274 -#define DF_IO6 0x40e1027c -#define DF_IO7 0x40e10284 -#define DF_IO8 0x40e10250 -#define DF_IO9 0x40e10258 -#define DF_IO10 0x40e10260 -#define DF_IO11 0x40e10268 -#define DF_IO12 0x40e10270 -#define DF_IO13 0x40e10278 -#define DF_IO14 0x40e10280 -#define DF_IO15 0x40e10288 -#define DF_CLE_nOE 0x40e10204 -#define DF_ALE_nWE1 0x40e10208 -#define DF_ALE_nWE2 0x40e1021c -#define DF_SCLK_E 0x40e10210 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define nBE0 0x40e10214 -#define nBE1 0x40e10218 -#define nLUA 0x40e10234 -#define nLLA 0x40e10238 -#define DF_ADDR0 0x40e1023c -#define DF_ADDR1 0x40e10240 -#define DF_ADDR2 0x40e10244 -#define DF_ADDR3 0x40e10248 -#define DF_INT_RnB 0x40e10220 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define DF_nWE 0x40e1022c -#define DF_nRE 0x40e10230 - -#define nXCVREN 0x40e10138 - -#define GPIO0 0x40e10124 -#define GPIO1 0x40e10128 -#define GPIO2 0x40e1012c -#define GPIO3 0x40e10130 -#define GPIO4 0x40e10134 -#define GPIO5 0x40e1028c -#define GPIO6 0x40e10290 -#define GPIO7 0x40e10294 -#define GPIO8 0x40e10298 -#define GPIO9 0x40e1029c -#define GPIO10 0x40e10458 -#define GPIO11 0x40e102a0 -#define GPIO12 0x40e102a4 -#define GPIO13 0x40e102a8 -#define GPIO14 0x40e102ac -#define GPIO15 0x40e102b0 -#define GPIO16 0x40e102b4 -#define GPIO17 0x40e102b8 -#define GPIO18 0x40e102bc -#define GPIO19 0x40e102c0 -#define GPIO20 0x40e102c4 -#define GPIO21 0x40e102c8 -#define GPIO22 0x40e102cc -#define GPIO23 0x40e102d0 -#define GPIO24 0x40e102d4 -#define GPIO25 0x40e102d8 -#define GPIO26 0x40e102dc - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define GPIO30 0x40e1040c -#define GPIO31 0x40e10410 -#define GPIO32 0x40e10414 -#define GPIO33 0x40e10418 -#define GPIO34 0x40e1041c -#define GPIO35 0x40e10420 -#define GPIO36 0x40e10424 -#define GPIO37 0x40e10428 -#define GPIO38 0x40e1042c -#define GPIO39 0x40e10430 -#define GPIO40 0x40e10434 -#define GPIO41 0x40e10438 -#define GPIO42 0x40e1043c -#define GPIO43 0x40e10440 -#define GPIO44 0x40e10444 -#define GPIO45 0x40e10448 -#define GPIO46 0x40e1044c -#define GPIO47 0x40e10450 -#define GPIO48 0x40e10454 -#define GPIO49 0x40e1045c -#define GPIO50 0x40e10460 -#define GPIO51 0x40e10464 -#define GPIO52 0x40e10468 -#define GPIO53 0x40e1046c -#define GPIO54 0x40e10470 -#define GPIO55 0x40e10474 -#define GPIO56 0x40e10478 -#define GPIO57 0x40e1047c -#define GPIO58 0x40e10480 -#define GPIO59 0x40e10484 -#define GPIO60 0x40e10488 -#define GPIO61 0x40e1048c -#define GPIO62 0x40e10490 - -#define GPIO6_2 0x40e10494 -#define GPIO7_2 0x40e10498 -#define GPIO8_2 0x40e1049c -#define GPIO9_2 0x40e104a0 -#define GPIO10_2 0x40e104a4 -#define GPIO11_2 0x40e104a8 -#define GPIO12_2 0x40e104ac -#define GPIO13_2 0x40e104b0 - -#define GPIO63 0x40e104b4 -#define GPIO64 0x40e104b8 -#define GPIO65 0x40e104bc -#define GPIO66 0x40e104c0 -#define GPIO67 0x40e104c4 -#define GPIO68 0x40e104c8 -#define GPIO69 0x40e104cc -#define GPIO70 0x40e104d0 -#define GPIO71 0x40e104d4 -#define GPIO72 0x40e104d8 -#define GPIO73 0x40e104dc - -#define GPIO14_2 0x40e104e0 -#define GPIO15_2 0x40e104e4 -#define GPIO16_2 0x40e104e8 -#define GPIO17_2 0x40e104ec - -#define GPIO74 0x40e104f0 -#define GPIO75 0x40e104f4 -#define GPIO76 0x40e104f8 -#define GPIO77 0x40e104fc -#define GPIO78 0x40e10500 -#define GPIO79 0x40e10504 -#define GPIO80 0x40e10508 -#define GPIO81 0x40e1050c -#define GPIO82 0x40e10510 -#define GPIO83 0x40e10514 -#define GPIO84 0x40e10518 -#define GPIO85 0x40e1051c -#define GPIO86 0x40e10520 -#define GPIO87 0x40e10524 -#define GPIO88 0x40e10528 -#define GPIO89 0x40e1052c -#define GPIO90 0x40e10530 -#define GPIO91 0x40e10534 -#define GPIO92 0x40e10538 -#define GPIO93 0x40e1053c -#define GPIO94 0x40e10540 -#define GPIO95 0x40e10544 -#define GPIO96 0x40e10548 -#define GPIO97 0x40e1054c -#define GPIO98 0x40e10550 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e1067c -#define GPIO3_2 0x40e10680 -#define GPIO4_2 0x40e10684 -#define GPIO5_2 0x40e10688 - -/* PXA300 and PXA310 */ -#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) -#define DF_IO0 0x40e10220 -#define DF_IO1 0x40e10228 -#define DF_IO2 0x40e10230 -#define DF_IO3 0x40e10238 -#define DF_IO4 0x40e10258 -#define DF_IO5 0x40e10260 -#define DF_IO7 0x40e10270 -#define DF_IO6 0x40e10268 -#define DF_IO8 0x40e10224 -#define DF_IO9 0x40e1022c -#define DF_IO10 0x40e10234 -#define DF_IO11 0x40e1023c -#define DF_IO12 0x40e1025c -#define DF_IO13 0x40e10264 -#define DF_IO14 0x40e1026c -#define DF_IO15 0x40e10274 -#define DF_CLE_NOE 0x40e10240 -#define DF_ALE_nWE 0x40e1020c -#define DF_SCLK_E 0x40e10250 -#define nCS0 0x40e100c4 -#define nCS1 0x40e100c0 -#define nBE0 0x40e10204 -#define nBE1 0x40e10208 -#define nLUA 0x40e10244 -#define nLLA 0x40e10254 -#define DF_ADDR0 0x40e10210 -#define DF_ADDR1 0x40e10214 -#define DF_ADDR2 0x40e10218 -#define DF_ADDR3 0x40e1021c -#define DF_INT_RnB 0x40e100c8 -#define DF_nCS0 0x40e10248 -#define DF_nCS1 0x40e10278 -#define DF_nWE 0x40e100cc -#define DF_nRE 0x40e10200 - -#define GPIO0 0x40e100b4 -#define GPIO1 0x40e100b8 -#define GPIO2 0x40e100bc -#define GPIO3 0x40e1027c -#define GPIO4 0x40e10280 - -#define GPIO5 0x40e10284 -#define GPIO6 0x40e10288 -#define GPIO7 0x40e1028c -#define GPIO8 0x40e10290 -#define GPIO9 0x40e10294 -#define GPIO10 0x40e10298 -#define GPIO11 0x40e1029c -#define GPIO12 0x40e102a0 -#define GPIO13 0x40e102a4 -#define GPIO14 0x40e102a8 -#define GPIO15 0x40e102ac -#define GPIO16 0x40e102b0 -#define GPIO17 0x40e102b4 -#define GPIO18 0x40e102b8 -#define GPIO19 0x40e102bc -#define GPIO20 0x40e102c0 -#define GPIO21 0x40e102c4 -#define GPIO22 0x40e102c8 -#define GPIO23 0x40e102cc -#define GPIO24 0x40e102d0 -#define GPIO25 0x40e102d4 -#define GPIO26 0x40e102d8 - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define ULPI_STP 0x40e1040c -#define ULPI_NXT 0x40e10410 -#define ULPI_DIR 0x40e10414 -#define GPIO30 0x40e10418 -#define GPIO31 0x40e1041c -#define GPIO32 0x40e10420 -#define GPIO33 0x40e10424 -#define GPIO34 0x40e10428 -#define GPIO35 0x40e1042c -#define GPIO36 0x40e10430 -#define GPIO37 0x40e10434 -#define GPIO38 0x40e10438 -#define GPIO39 0x40e1043c -#define GPIO40 0x40e10440 -#define GPIO41 0x40e10444 -#define GPIO42 0x40e10448 -#define GPIO43 0x40e1044c -#define GPIO44 0x40e10450 -#define GPIO45 0x40e10454 -#define GPIO46 0x40e10458 -#define GPIO47 0x40e1045c -#define GPIO48 0x40e10460 - -#define GPIO49 0x40e10464 -#define GPIO50 0x40e10468 -#define GPIO51 0x40e1046c -#define GPIO52 0x40e10470 -#define GPIO53 0x40e10474 -#define GPIO54 0x40e10478 -#define GPIO55 0x40e1047c -#define GPIO56 0x40e10480 -#define GPIO57 0x40e10484 -#define GPIO58 0x40e10488 -#define GPIO59 0x40e1048c -#define GPIO60 0x40e10490 -#define GPIO61 0x40e10494 -#define GPIO62 0x40e10498 -#define GPIO63 0x40e1049c -#define GPIO64 0x40e104a0 -#define GPIO65 0x40e104a4 -#define GPIO66 0x40e104a8 -#define GPIO67 0x40e104ac -#define GPIO68 0x40e104b0 -#define GPIO69 0x40e104b4 -#define GPIO70 0x40e104b8 -#define GPIO71 0x40e104bc -#define GPIO72 0x40e104c0 -#define GPIO73 0x40e104c4 -#define GPIO74 0x40e104c8 -#define GPIO75 0x40e104cc -#define GPIO76 0x40e104d0 -#define GPIO77 0x40e104d4 -#define GPIO78 0x40e104d8 -#define GPIO79 0x40e104dc -#define GPIO80 0x40e104e0 -#define GPIO81 0x40e104e4 -#define GPIO82 0x40e104e8 -#define GPIO83 0x40e104ec -#define GPIO84 0x40e104f0 -#define GPIO85 0x40e104f4 -#define GPIO86 0x40e104f8 -#define GPIO87 0x40e104fc -#define GPIO88 0x40e10500 -#define GPIO89 0x40e10504 -#define GPIO90 0x40e10508 -#define GPIO91 0x40e1050c -#define GPIO92 0x40e10510 -#define GPIO93 0x40e10514 -#define GPIO94 0x40e10518 -#define GPIO95 0x40e1051c -#define GPIO96 0x40e10520 -#define GPIO97 0x40e10524 -#define GPIO98 0x40e10528 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e102dc -#define GPIO3_2 0x40e102e0 -#define GPIO4_2 0x40e102e4 -#define GPIO5_2 0x40e102e8 -#define GPIO6_2 0x40e102ec - -#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ -#define GPIO7_2 0x40e1052c -#define GPIO8_2 0x40e10530 -#define GPIO9_2 0x40e10534 -#define GPIO10_2 0x40e10538 -#endif -#endif - -#ifdef CONFIG_CPU_MONAHANS -/* MFPR Bit Definitions, see 4-10, Vol. 1 */ -#define PULL_SEL 0x8000 -#define PULLUP_EN 0x4000 -#define PULLDOWN_EN 0x2000 - -#define DRIVE_FAST_1mA 0x0 -#define DRIVE_FAST_2mA 0x400 -#define DRIVE_FAST_3mA 0x800 -#define DRIVE_FAST_4mA 0xC00 -#define DRIVE_SLOW_6mA 0x1000 -#define DRIVE_FAST_6mA 0x1400 -#define DRIVE_SLOW_10mA 0x1800 -#define DRIVE_FAST_10mA 0x1C00 - -#define SLEEP_SEL 0x200 -#define SLEEP_DATA 0x100 -#define SLEEP_OE_N 0x80 -#define EDGE_CLEAR 0x40 -#define EDGE_FALL_EN 0x20 -#define EDGE_RISE_EN 0x10 - -#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ -#define AF_SEL_1 0x1 /* Alternate function 1 */ -#define AF_SEL_2 0x2 /* Alternate function 2 */ -#define AF_SEL_3 0x3 /* Alternate function 3 */ -#define AF_SEL_4 0x4 /* Alternate function 4 */ -#define AF_SEL_5 0x5 /* Alternate function 5 */ -#define AF_SEL_6 0x6 /* Alternate function 6 */ -#define AF_SEL_7 0x7 /* Alternate function 7 */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO8_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) - -#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) -#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) - -/* - * Power Manager - */ -#ifdef CONFIG_CPU_MONAHANS - -#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */ -#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */ -#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */ -#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */ -#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */ - -#define PMCR 0x40F50000 /* Power Manager Control Register */ -#define PSR 0x40F50004 /* Power Manager S2 Status Register */ -#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */ -#define PCFR 0x40F5000C /* Power Manager General Configuration Register */ -#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */ -#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */ -#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */ -#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */ -#define PCMD(x) (0x40F50110 + x*4) -#define PCMD0 (0x40F50110 + 0 * 4) -#define PCMD1 (0x40F50110 + 1 * 4) -#define PCMD2 (0x40F50110 + 2 * 4) -#define PCMD3 (0x40F50110 + 3 * 4) -#define PCMD4 (0x40F50110 + 4 * 4) -#define PCMD5 (0x40F50110 + 5 * 4) -#define PCMD6 (0x40F50110 + 6 * 4) -#define PCMD7 (0x40F50110 + 7 * 4) -#define PCMD8 (0x40F50110 + 8 * 4) -#define PCMD9 (0x40F50110 + 9 * 4) -#define PCMD10 (0x40F50110 + 10 * 4) -#define PCMD11 (0x40F50110 + 11 * 4) -#define PCMD12 (0x40F50110 + 12 * 4) -#define PCMD13 (0x40F50110 + 13 * 4) -#define PCMD14 (0x40F50110 + 14 * 4) -#define PCMD15 (0x40F50110 + 15 * 4) -#define PCMD16 (0x40F50110 + 16 * 4) -#define PCMD17 (0x40F50110 + 17 * 4) -#define PCMD18 (0x40F50110 + 18 * 4) -#define PCMD19 (0x40F50110 + 19 * 4) -#define PCMD20 (0x40F50110 + 20 * 4) -#define PCMD21 (0x40F50110 + 21 * 4) -#define PCMD22 (0x40F50110 + 22 * 4) -#define PCMD23 (0x40F50110 + 23 * 4) -#define PCMD24 (0x40F50110 + 24 * 4) -#define PCMD25 (0x40F50110 + 25 * 4) -#define PCMD26 (0x40F50110 + 26 * 4) -#define PCMD27 (0x40F50110 + 27 * 4) -#define PCMD28 (0x40F50110 + 28 * 4) -#define PCMD29 (0x40F50110 + 29 * 4) -#define PCMD30 (0x40F50110 + 30 * 4) -#define PCMD31 (0x40F50110 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ - -#define PVCR_FVC (0x1 << 28) -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PVCR_ReadPointer 0x01f00000 -#define PVCR_SlaveAddress (0x7f) - -#else /* ifdef CONFIG_CPU_MONAHANS */ - -#define PMCR 0x40F00000 /* Power Manager Control Register */ -#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */ -#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */ -#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */ -#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR 0x40F0001C /* Power Manager General Configuration Register */ -#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR 0x40F00030 /* Reset Controller Status Register */ - -#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */ -#define PSTR 0x40F00038 /* Power Manager Standby Config Register */ -#define PSNR 0x40F0003C /* Power Manager Sense Config Register */ -#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */ -#define PCMD(x) (0x40F00080 + x*4) -#define PCMD0 (0x40F00080 + 0 * 4) -#define PCMD1 (0x40F00080 + 1 * 4) -#define PCMD2 (0x40F00080 + 2 * 4) -#define PCMD3 (0x40F00080 + 3 * 4) -#define PCMD4 (0x40F00080 + 4 * 4) -#define PCMD5 (0x40F00080 + 5 * 4) -#define PCMD6 (0x40F00080 + 6 * 4) -#define PCMD7 (0x40F00080 + 7 * 4) -#define PCMD8 (0x40F00080 + 8 * 4) -#define PCMD9 (0x40F00080 + 9 * 4) -#define PCMD10 (0x40F00080 + 10 * 4) -#define PCMD11 (0x40F00080 + 11 * 4) -#define PCMD12 (0x40F00080 + 12 * 4) -#define PCMD13 (0x40F00080 + 13 * 4) -#define PCMD14 (0x40F00080 + 14 * 4) -#define PCMD15 (0x40F00080 + 15 * 4) -#define PCMD16 (0x40F00080 + 16 * 4) -#define PCMD17 (0x40F00080 + 17 * 4) -#define PCMD18 (0x40F00080 + 18 * 4) -#define PCMD19 (0x40F00080 + 19 * 4) -#define PCMD20 (0x40F00080 + 20 * 4) -#define PCMD21 (0x40F00080 + 21 * 4) -#define PCMD22 (0x40F00080 + 22 * 4) -#define PCMD23 (0x40F00080 + 23 * 4) -#define PCMD24 (0x40F00080 + 24 * 4) -#define PCMD25 (0x40F00080 + 25 * 4) -#define PCMD26 (0x40F00080 + 26 * 4) -#define PCMD27 (0x40F00080 + 27 * 4) -#define PCMD28 (0x40F00080 + 28 * 4) -#define PCMD29 (0x40F00080 + 29 * 4) -#define PCMD30 (0x40F00080 + 30 * 4) -#define PCMD31 (0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ - /* bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -/* define MACRO for Power Manager General Configuration Register (PCFR) */ -#define PCFR_FVC (0x1 << 10) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * SSP Serial Port Registers - */ -#define SSCR0 0x41000000 /* SSP Control Register 0 */ -#define SSCR1 0x41000004 /* SSP Control Register 1 */ -#define SSSR 0x41000008 /* SSP Status Register */ -#define SSITR 0x4100000C /* SSP Interrupt Test Register */ -#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - -/* - * MultiMediaCard (MMC) controller - */ -#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */ -#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */ -#define MMC_CLKRT 0x41100008 /* MMC clock rate */ -#define MMC_SPI 0x4110000c /* SPI mode control bits */ -#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */ -#define MMC_RESTO 0x41100014 /* Expected response time out */ -#define MMC_RDTO 0x41100018 /* Expected data read time out */ -#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */ -#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */ -#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK 0x41100028 /* Interrupt Mask */ -#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */ -#define MMC_CMD 0x41100030 /* Index of current command */ -#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */ -#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */ -#define MMC_RES 0x4110003c /* Response FIFO (read only) */ -#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */ -#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */ - - -/* - * LCD - */ -#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ -#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */ -#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */ -#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */ -#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 0x44000038 /* LCD Controller Status Register */ -#define LCSR1 0x44000034 /* LCD Controller Status Register */ -#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */ -#define TMEDCR 0x44000044 /* TMED Control Register */ - -#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */ -#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_CPU_PXA27X) -#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ -#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ -#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ -#endif - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) - - -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ - -#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR0_SOF (1 << 1) /* Start of frame */ -#define LCSR0_BER (1 << 2) /* Bus error */ -#define LCSR0_ABC (1 << 3) /* AC Bias count */ -#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR0_OU (1 << 6) /* output FIFO underrun */ -#define LCSR0_QD (1 << 7) /* quick disable */ -#define LCSR0_EOF0 (1 << 8) /* end of frame */ -#define LCSR0_BS (1 << 9) /* branch status */ -#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ - -#define LCSR1_SOF1 (1 << 0) -#define LCSR1_SOF2 (1 << 1) -#define LCSR1_SOF3 (1 << 2) -#define LCSR1_SOF4 (1 << 3) -#define LCSR1_SOF5 (1 << 4) -#define LCSR1_SOF6 (1 << 5) - -#define LCSR1_EOF1 (1 << 8) -#define LCSR1_EOF2 (1 << 9) -#define LCSR1_EOF3 (1 << 10) -#define LCSR1_EOF4 (1 << 11) -#define LCSR1_EOF5 (1 << 12) -#define LCSR1_EOF6 (1 << 13) - -#define LCSR1_BS1 (1 << 16) -#define LCSR1_BS2 (1 << 17) -#define LCSR1_BS3 (1 << 18) -#define LCSR1_BS4 (1 << 19) -#define LCSR1_BS5 (1 << 20) -#define LCSR1_BS6 (1 << 21) - -#define LCSR1_IU2 (1 << 25) -#define LCSR1_IU3 (1 << 26) -#define LCSR1_IU4 (1 << 27) -#define LCSR1_IU5 (1 << 28) -#define LCSR1_IU6 (1 << 29) - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_CPU_PXA27X) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_EOFINT (1 << 21) -#endif - -/* - * Memory controller - */ - -#ifdef CONFIG_CPU_MONAHANS - -/* PXA3xx */ - -/* Static Memory Controller Registers */ -#define MSC0 0x4A000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4A00000C /* Static Memory Control Register 1 */ -#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */ -#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */ -#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */ -#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */ -#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */ -#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */ -#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */ -#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */ - -/* Dynamic Memory Controller Registers */ -#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ -#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ -#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */ -#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */ -#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI 0x48100090 /* EMPI Control Register */ -#define RCOMP 0x48100100 -#define PAD_MA 0x48100110 -#define PAD_MDMSB 0x48100114 -#define PAD_MDLSB 0x48100118 -#define PAD_DMEM 0x4810011c -#define PAD_SDCLK 0x48100120 -#define PAD_SDCS 0x48100124 -#define PAD_SMEM 0x48100128 -#define PAD_SCLK 0x4810012C -#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */ - -/* Some frequently used bits */ -#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ -#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ -#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ -#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ - -#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ -#define MDCNFG_DTC_1 0x100 -#define MDCNFG_DTC_2 0x200 -#define MDCNFG_DTC_3 0x300 - -#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ -#define MDCNFG_DRAC_13 0x20 -#define MDCNFG_DRAC_14 0x40 - -#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ -#define MDCNFG_DCAC_10 0x08 -#define MDCNFG_DCAC_11 0x10 - -#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ -#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ -#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ - - -/* Data Flash Controller Registers */ - -#define NDCR 0x43100000 /* Data Flash Control register */ -#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR 0x43100014 /* Data Controller Status Register */ -#define NDPCR 0x43100018 /* Data Controller Page Count Register */ -#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */ -#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */ -#define NDDB 0x43100040 /* Data Controller Data Buffer */ -#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */ -#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */ -#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */ - -#define NDCR_SPARE_EN (0x1<<31) -#define NDCR_ECC_EN (0x1<<30) -#define NDCR_DMA_EN (0x1<<29) -#define NDCR_ND_RUN (0x1<<28) -#define NDCR_DWIDTH_C (0x1<<27) -#define NDCR_DWIDTH_M (0x1<<26) -#define NDCR_PAGE_SZ (0x3<<24) -#define NDCR_NCSX (0x1<<23) -#define NDCR_ND_STOP (0x1<<22) -/* reserved: - * #define NDCR_ND_MODE (0x3<<21) - * #define NDCR_NAND_MODE 0x0 */ -#define NDCR_CLR_PG_CNT (0x1<<20) -#define NDCR_CLR_ECC (0x1<<19) -#define NDCR_RD_ID_CNT (0x7<<16) -#define NDCR_RA_START (0x1<<15) -#define NDCR_PG_PER_BLK (0x1<<14) -#define NDCR_ND_ARB_EN (0x1<<12) -#define NDCR_RDYM (0x1<<11) -#define NDCR_CS0_PAGEDM (0x1<<10) -#define NDCR_CS1_PAGEDM (0x1<<9) -#define NDCR_CS0_CMDDM (0x1<<8) -#define NDCR_CS1_CMDDM (0x1<<7) -#define NDCR_CS0_BBDM (0x1<<6) -#define NDCR_CS1_BBDM (0x1<<5) -#define NDCR_DBERRM (0x1<<4) -#define NDCR_SBERRM (0x1<<3) -#define NDCR_WRDREQM (0x1<<2) -#define NDCR_RDDREQM (0x1<<1) -#define NDCR_WRCMDREQM (0x1) - -#define NDSR_RDY (0x1<<11) -#define NDSR_CS0_PAGED (0x1<<10) -#define NDSR_CS1_PAGED (0x1<<9) -#define NDSR_CS0_CMDD (0x1<<8) -#define NDSR_CS1_CMDD (0x1<<7) -#define NDSR_CS0_BBD (0x1<<6) -#define NDSR_CS1_BBD (0x1<<5) -#define NDSR_DBERR (0x1<<4) -#define NDSR_SBERR (0x1<<3) -#define NDSR_WRDREQ (0x1<<2) -#define NDSR_RDDREQ (0x1<<1) -#define NDSR_WRCMDREQ (0x1) - -#define NDCB0_AUTO_RS (0x1<<25) -#define NDCB0_CSEL (0x1<<24) -#define NDCB0_CMD_TYPE (0x7<<21) -#define NDCB0_NC (0x1<<20) -#define NDCB0_DBC (0x1<<19) -#define NDCB0_ADDR_CYC (0x7<<16) -#define NDCB0_CMD2 (0xff<<8) -#define NDCB0_CMD1 (0xff) -#define MCMEM(s) MCMEM0 -#define MCATT(s) MCATT0 -#define MCIO(s) MCIO0 -#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ - -/* Maximum values for NAND Interface Timing Registers in DFC clock - * periods */ -#define DFC_MAX_tCH 7 -#define DFC_MAX_tCS 7 -#define DFC_MAX_tWH 7 -#define DFC_MAX_tWP 7 -#define DFC_MAX_tRH 7 -#define DFC_MAX_tRP 15 -#define DFC_MAX_tR 65535 -#define DFC_MAX_tWHR 15 -#define DFC_MAX_tAR 15 - -#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ -#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ - -#else /* CONFIG_CPU_MONAHANS */ - -/* PXA2xx */ - -#define MEMC_BASE 0x48000000 /* Base of Memory Controller */ -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 - -#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ -#define MDCNFG_DE0 0x00000001 -#define MDCNFG_DE1 0x00000002 -#define MDCNFG_DE2 0x00010000 -#define MDCNFG_DE3 0x00020000 -#define MDCNFG_DWID0 0x00000004 - -#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ -#define MSC0 0x48000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4800000C /* Static Memory Control Register 1 */ -#define MSC2 0x48000010 /* Static Memory Control Register 2 */ -#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */ -#define FLYCNFG 0x48000020 -#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ -#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ -#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -#if defined(CONFIG_CPU_PXA27X) - -#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -#endif /* CONFIG_CPU_PXA27X */ - -/* LCD registers */ -#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ -#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ -#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */ -#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */ -#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */ -#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */ -#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */ -#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */ - -#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */ -#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */ -#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */ -#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */ -#define CCR 0x44000090 /* Cursor Control Register */ - -#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ -#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */ - -#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ -#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ - -#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ -#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ - -#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ -#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ - -#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ -#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ -#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ -#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ -#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ -#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ - -#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ -#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ -#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ - -#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ -#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ -#define CCR_CEN (1<<31) /* Enable bit for Cursor */ - -/* Keypad controller */ - -#define KPC 0x41500000 /* Keypad Interface Control register */ -#define KPDK 0x41500008 /* Keypad Interface Direct Key register */ -#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */ -#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */ -#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */ - -#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ -#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ -#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ -#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ -#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ -#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ -#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ -#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ -#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ -#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ -#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ -#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ -#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ -#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ -#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ -#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ -#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ -#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ -#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ - -#define KPDK_DKP (0x1 << 31) -#define KPDK_DK7 (0x1 << 7) -#define KPDK_DK6 (0x1 << 6) -#define KPDK_DK5 (0x1 << 5) -#define KPDK_DK4 (0x1 << 4) -#define KPDK_DK3 (0x1 << 3) -#define KPDK_DK2 (0x1 << 2) -#define KPDK_DK1 (0x1 << 1) -#define KPDK_DK0 (0x1 << 0) - -#define KPREC_OF1 (0x1 << 31) -#define kPREC_UF1 (0x1 << 30) -#define KPREC_OF0 (0x1 << 15) -#define KPREC_UF0 (0x1 << 14) - -#define KPMK_MKP (0x1 << 31) -#define KPAS_SO (0x1 << 31) -#define KPASMKPx_SO (0x1 << 31) - -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR 0x40F00034 -#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ -#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ -#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 0x40A00080 /* */ -#define OSCR4 0x40A00040 /* OS Timer Counter Register */ -#define OMCR4 0x40A000C0 /* */ - -#endif /* CONFIG_CPU_PXA27X */ - -#endif /* _PXA_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h deleted file mode 100644 index 428a848e1573078e9604c08cb34436f0826fbe19..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/pxa.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA common functions - * - * Copyright (C) 2011 Marek Vasut - */ - -#ifndef __PXA_H__ -#define __PXA_H__ - -#define PXA255_A0 0x00000106 -#define PXA250_C0 0x00000105 -#define PXA250_B2 0x00000104 -#define PXA250_B1 0x00000103 -#define PXA250_B0 0x00000102 -#define PXA250_A1 0x00000101 -#define PXA250_A0 0x00000100 -#define PXA210_C0 0x00000125 -#define PXA210_B2 0x00000124 -#define PXA210_B1 0x00000123 -#define PXA210_B0 0x00000122 - -int cpu_is_pxa25x(void); -int cpu_is_pxa27x(void); -uint32_t pxa_get_cpu_revision(void); -void pxa2xx_dram_init(void); - -#endif /* __PXA_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-mmc.h b/arch/arm/include/asm/arch-pxa/regs-mmc.h deleted file mode 100644 index 6d9a736d9c0605c59b530bbebbed853cab5e143e..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/regs-mmc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut - */ - -#ifndef __REGS_MMC_H__ -#define __REGS_MMC_H__ - -#define MMC0_BASE 0x41100000 -#define MMC1_BASE 0x42000000 - -int pxa_mmc_register(int card_index); - -struct pxa_mmc_regs { - uint32_t strpcl; - uint32_t stat; - uint32_t clkrt; - uint32_t spi; - uint32_t cmdat; - uint32_t resto; - uint32_t rdto; - uint32_t blklen; - uint32_t nob; - uint32_t prtbuf; - uint32_t i_mask; - uint32_t i_reg; - uint32_t cmd; - uint32_t argh; - uint32_t argl; - uint32_t res; - uint32_t rxfifo; - uint32_t txfifo; -}; - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (1 << 0) -#define MMC_STRPCL_START_CLK (1 << 1) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (1 << 13) -#define MMC_STAT_PRG_DONE (1 << 12) -#define MMC_STAT_DATA_TRAN_DONE (1 << 11) -#define MMC_STAT_CLK_EN (1 << 8) -#define MMC_STAT_RECV_FIFO_FULL (1 << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) -#define MMC_STAT_RES_CRC_ERROR (1 << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) -#define MMC_STAT_CRC_READ_ERROR (1 << 3) -#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) -#define MMC_STAT_READ_TIME_OUT (1 << 0) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ 0 -#define MMC_CLKRT_10MHZ 1 -#define MMC_CLKRT_5MHZ 2 -#define MMC_CLKRT_2_5MHZ 3 -#define MMC_CLKRT_1_25MHZ 4 -#define MMC_CLKRT_0_625MHZ 5 -#define MMC_CLKRT_0_3125MHZ 6 - -/* MMC_SPI */ -#define MMC_SPI_EN (1 << 0) -#define MMC_SPI_CS_EN (1 << 2) -#define MMC_SPI_CS_ADDRESS (1 << 3) -#define MMC_SPI_CRC_ON (1 << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (1 << 8) -#define MMC_CMDAT_MMC_DMA_EN (1 << 7) -#define MMC_CMDAT_INIT (1 << 6) -#define MMC_CMDAT_BUSY (1 << 5) -#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) -#define MMC_CMDAT_STREAM (1 << 4) -#define MMC_CMDAT_WRITE (1 << 3) -#define MMC_CMDAT_DATA_EN (1 << 2) -#define MMC_CMDAT_R0 0 -#define MMC_CMDAT_R1 1 -#define MMC_CMDAT_R2 2 -#define MMC_CMDAT_R3 3 - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX_MASK 0x7f - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX_MASK 0xffff - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX_MASK 0x3ff - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_MASK_CLK_IS_OFF (1 << 4) -#define MMC_I_MASK_STOP_CMD (1 << 3) -#define MMC_I_MASK_END_CMD_RES (1 << 2) -#define MMC_I_MASK_PRG_DONE (1 << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) -#define MMC_I_MASK_ALL 0x7f - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_REG_CLK_IS_OFF (1 << 4) -#define MMC_I_REG_STOP_CMD (1 << 3) -#define MMC_I_REG_END_CMD_RES (1 << 2) -#define MMC_I_REG_PRG_DONE (1 << 1) -#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX 0x6f - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __REGS_MMC_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h deleted file mode 100644 index bdd0a4757b53902c5bc5d981eab2edcce9466ed9..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/regs-uart.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut - */ - -#ifndef __REGS_UART_H__ -#define __REGS_UART_H__ - -#define FFUART_BASE 0x40100000 -#define BTUART_BASE 0x40200000 -#define STUART_BASE 0x40700000 -#define HWUART_BASE 0x41600000 - -struct pxa_uart_regs { - union { - uint32_t thr; - uint32_t rbr; - uint32_t dll; - }; - union { - uint32_t ier; - uint32_t dlh; - }; - union { - uint32_t fcr; - uint32_t iir; - }; - uint32_t lcr; - uint32_t mcr; - uint32_t lsr; - uint32_t msr; - uint32_t spr; - uint32_t isr; -}; - -#define IER_DMAE (1 << 7) -#define IER_UUE (1 << 6) -#define IER_NRZE (1 << 5) -#define IER_RTIOE (1 << 4) -#define IER_MIE (1 << 3) -#define IER_RLSE (1 << 2) -#define IER_TIE (1 << 1) -#define IER_RAVIE (1 << 0) - -#define IIR_FIFOES1 (1 << 7) -#define IIR_FIFOES0 (1 << 6) -#define IIR_TOD (1 << 3) -#define IIR_IID2 (1 << 2) -#define IIR_IID1 (1 << 1) -#define IIR_IP (1 << 0) - -#define FCR_ITL2 (1 << 7) -#define FCR_ITL1 (1 << 6) -#define FCR_RESETTF (1 << 2) -#define FCR_RESETRF (1 << 1) -#define FCR_TRFIFOE (1 << 0) -#define FCR_ITL_1 0 -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) -#define LCR_SB (1 << 6) -#define LCR_STKYP (1 << 5) -#define LCR_EPS (1 << 4) -#define LCR_PEN (1 << 3) -#define LCR_STB (1 << 2) -#define LCR_WLS1 (1 << 1) -#define LCR_WLS0 (1 << 0) - -#define LSR_FIFOE (1 << 7) -#define LSR_TEMT (1 << 6) -#define LSR_TDRQ (1 << 5) -#define LSR_BI (1 << 4) -#define LSR_FE (1 << 3) -#define LSR_PE (1 << 2) -#define LSR_OE (1 << 1) -#define LSR_DR (1 << 0) - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) -#define MCR_OUT1 (1 << 2) -#define MCR_RTS (1 << 1) -#define MCR_DTR (1 << 0) - -#define MSR_DCD (1 << 7) -#define MSR_RI (1 << 6) -#define MSR_DSR (1 << 5) -#define MSR_CTS (1 << 4) -#define MSR_DDCD (1 << 3) -#define MSR_TERI (1 << 2) -#define MSR_DDSR (1 << 1) -#define MSR_DCTS (1 << 0) - -#endif /* __REGS_UART_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-usb.h b/arch/arm/include/asm/arch-pxa/regs-usb.h deleted file mode 100644 index e46887c9ed457f1908a918c4aa7b7f4257f59578..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-pxa/regs-usb.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA25x UDC definitions - * - * Copyright (C) 2012 Łukasz Dałek - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct pxa25x_udc_regs { - /* UDC Control Register */ - uint32_t udccr; /* 0x000 */ - uint32_t reserved1; - - /* UDC Control Function Register */ - uint32_t udccfr; /* 0x008 */ - uint32_t reserved2; - - /* UDC Endpoint Control/Status Registers */ - uint32_t udccs[16]; /* 0x010 - 0x04c */ - - /* UDC Interrupt Control/Status Registers */ - uint32_t uicr0; /* 0x050 */ - uint32_t uicr1; /* 0x054 */ - uint32_t usir0; /* 0x058 */ - uint32_t usir1; /* 0x05c */ - - /* UDC Frame Number/Byte Count Registers */ - uint32_t ufnrh; /* 0x060 */ - uint32_t ufnrl; /* 0x064 */ - uint32_t ubcr2; /* 0x068 */ - uint32_t ubcr4; /* 0x06c */ - uint32_t ubcr7; /* 0x070 */ - uint32_t ubcr9; /* 0x074 */ - uint32_t ubcr12; /* 0x078 */ - uint32_t ubcr14; /* 0x07c */ - - /* UDC Endpoint Data Registers */ - uint32_t uddr0; /* 0x080 */ - uint32_t reserved3[7]; - uint32_t uddr5; /* 0x0a0 */ - uint32_t reserved4[7]; - uint32_t uddr10; /* 0x0c0 */ - uint32_t reserved5[7]; - uint32_t uddr15; /* 0x0e0 */ - uint32_t reserved6[7]; - uint32_t uddr1; /* 0x100 */ - uint32_t reserved7[31]; - uint32_t uddr2; /* 0x180 */ - uint32_t reserved8[31]; - uint32_t uddr3; /* 0x200 */ - uint32_t reserved9[127]; - uint32_t uddr4; /* 0x400 */ - uint32_t reserved10[127]; - uint32_t uddr6; /* 0x600 */ - uint32_t reserved11[31]; - uint32_t uddr7; /* 0x680 */ - uint32_t reserved12[31]; - uint32_t uddr8; /* 0x700 */ - uint32_t reserved13[127]; - uint32_t uddr9; /* 0x900 */ - uint32_t reserved14[127]; - uint32_t uddr11; /* 0xb00 */ - uint32_t reserved15[31]; - uint32_t uddr12; /* 0xb80 */ - uint32_t reserved16[31]; - uint32_t uddr13; /* 0xc00 */ - uint32_t reserved17[127]; - uint32_t uddr14; /* 0xe00 */ - -}; - -#define PXA25X_UDC_BASE 0x40600000 - -#define UDCCR_UDE (1 << 0) -#define UDCCR_UDA (1 << 1) -#define UDCCR_RSM (1 << 2) -#define UDCCR_RESIR (1 << 3) -#define UDCCR_SUSIR (1 << 4) -#define UDCCR_SRM (1 << 5) -#define UDCCR_RSTIR (1 << 6) -#define UDCCR_REM (1 << 7) - -/* Bulk IN endpoint 1/6/11 */ -#define UDCCS_BI_TSP (1 << 7) -#define UDCCS_BI_FST (1 << 5) -#define UDCCS_BI_SST (1 << 4) -#define UDCCS_BI_TUR (1 << 3) -#define UDCCS_BI_FTF (1 << 2) -#define UDCCS_BI_TPC (1 << 1) -#define UDCCS_BI_TFS (1 << 0) - -/* Bulk OUT endpoint 2/7/12 */ -#define UDCCS_BO_RSP (1 << 7) -#define UDCCS_BO_RNE (1 << 6) -#define UDCCS_BO_FST (1 << 5) -#define UDCCS_BO_SST (1 << 4) -#define UDCCS_BO_DME (1 << 3) -#define UDCCS_BO_RPC (1 << 1) -#define UDCCS_BO_RFS (1 << 0) - -/* Isochronous OUT endpoint 4/9/14 */ -#define UDCCS_IO_RSP (1 << 7) -#define UDCCS_IO_RNE (1 << 6) -#define UDCCS_IO_DME (1 << 3) -#define UDCCS_IO_ROF (1 << 2) -#define UDCCS_IO_RPC (1 << 1) -#define UDCCS_IO_RFS (1 << 0) - -/* Control endpoint 0 */ -#define UDCCS0_OPR (1 << 0) -#define UDCCS0_IPR (1 << 1) -#define UDCCS0_FTF (1 << 2) -#define UDCCS0_DRWF (1 << 3) -#define UDCCS0_SST (1 << 4) -#define UDCCS0_FST (1 << 5) -#define UDCCS0_RNE (1 << 6) -#define UDCCS0_SA (1 << 7) - -#define UICR0_IM0 (1 << 0) - -#define USIR0_IR0 (1 << 0) -#define USIR0_IR1 (1 << 1) -#define USIR0_IR2 (1 << 2) -#define USIR0_IR3 (1 << 3) -#define USIR0_IR4 (1 << 4) -#define USIR0_IR5 (1 << 5) -#define USIR0_IR6 (1 << 6) -#define USIR0_IR7 (1 << 7) - -#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ -#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ -/* - * Intel(R) PXA255 Processor Specification, September 2003 (page 31) - * define new "must be one" bits in UDCCFR (see Table 12-13.) - */ -#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) - -#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ -#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ -#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ -#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ -#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ - -#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-sa1100/bitfield.h b/arch/arm/include/asm/arch-sa1100/bitfield.h deleted file mode 100644 index 104a21c2e47d17f58c6eeedc687dd4ae2367dfe3..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-sa1100/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 14860d89b6b02003edbd46c089ed30f398350499..5870412c439039bc31d3c8b9a1d6834ea42577d8 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -6,12 +6,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #if defined(CONFIG_ARCH_LS1021A) || \ - defined(CONFIG_CPU_PXA27X) || \ - defined(CONFIG_CPU_MONAHANS) || \ - defined(CONFIG_CPU_PXA25X) || \ defined(CONFIG_FSL_LAYERSCAPE) #include #endif diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b0c7599e412b3b894716dcd6e5e426a224baeac5..a4f4961fc877b32b49fde7e40a461910576872c4 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,31 +8,6 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#define CONFIG_FSL_SEC_MON - -#ifdef CONFIG_SPL_BUILD -/* - * Define the key hash for U-Boot here if public/private key pair used to - * sign U-boot are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_SPL_UBOOT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - * else leave it defined as NULL - */ - -#define CONFIG_SPL_UBOOT_KEY_HASH NULL -#endif /* ifdef CONFIG_SPL_BUILD */ - -#define CONFIG_KEY_REVOCATION - -#if defined(CONFIG_FSL_LAYERSCAPE) -/* - * For fsl layerscape based platforms, ESBC image Address in Header - * is 64 bit. - */ -#define CONFIG_ESBC_ADDR_64BIT -#endif - #ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images @@ -49,76 +24,6 @@ #endif -#ifdef CONFIG_ARCH_LS2080A -#define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xa0000000;" \ - "setenv initrd_high 0xcfffffff;" \ - "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -#else -#define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xffffffff;" \ - "setenv initrd_high 0xffffffff;" \ - "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -#endif - -/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from - * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ - defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -/* The address needs to be modified according to NOR, NAND, SD and - * DDR memory map - */ -#ifdef CONFIG_FSL_LSCH3 -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_BS_ADDR_DEVICE 0x20600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000 -#else /* NOR BOOT */ -#define CONFIG_BS_ADDR_DEVICE 0x580600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 -#endif /*ifdef CONFIG_QSPI_BOOT */ -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00004000 -#define CONFIG_BS_ADDR_RAM 0xa0600000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000 -#else -#ifdef CONFIG_SD_BOOT -/* For SD boot address and size are assigned in terms of sector - * offset and no. of sectors respectively. - */ -#define CONFIG_BS_ADDR_DEVICE 0x00003000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200 -#define CONFIG_BS_SIZE 0x00000008 -#define CONFIG_BS_HDR_SIZE 0x00000010 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_ADDR_DEVICE 0x00600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000 -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_BS_ADDR_DEVICE 0x40600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000 -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#else /* Default NOR Boot */ -#define CONFIG_BS_ADDR_DEVICE 0x60600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000 -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#endif -#define CONFIG_BS_ADDR_RAM 0x81000000 -#define CONFIG_BS_HDR_ADDR_RAM 0x81020000 -#endif - -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE -/* BOOTSCRIPT_ADDR is not required */ -#endif - #ifdef CONFIG_FSL_LS_PPA /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. @@ -129,7 +34,6 @@ #define PPA_KEY_HASH NULL #endif /* ifdef CONFIG_FSL_LS_PPA */ -#include #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 264a2e717a7028f1a2a77aa3b66062079420847f..17fdfbcffb7aee5fb1ae89d1724fae0e85ac6643 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -13,6 +13,7 @@ #include #define NUM_SYS_CLKS 7 +#define SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ struct bd_info; diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h index c61374e9f2e49a767ac2d565342712c1e6139d0e..a1f59d9cbae08189913bd86fc7db904ab08b3517 100644 --- a/arch/arm/include/asm/proc-armv/system.h +++ b/arch/arm/include/asm/proc-armv/system.h @@ -163,8 +163,7 @@ #endif /* CONFIG_ARM64 */ -#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \ - defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) /* * On the StrongARM, "swp" is terminally broken since it bypasses the * cache totally. This means that the cache becomes inconsistent, and, diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index b5790bd0bc45712ed5929af1b660e34cc343e182..0ece4b09060a3c94d11324df363f0cb38c4bea9e 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -6,9 +6,8 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ -#if defined(CONFIG_ARCH_OMAP2PLUS) \ - || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ - || defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) || \ + defined(CONFIG_ARCH_K3) || defined(CONFIG_ARCH_OMAP2PLUS) /* Platform-specific defines */ #include diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 612a2d5b698e40cd8a100785e00680a2b85a2603..fe6b4472b9365d5c74fc3dd0585ecb8301b5fe9e 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -9,6 +9,7 @@ #include #include #include +#include /* * This file handles the target-independent stages of the U-Boot @@ -104,7 +105,7 @@ ENTRY(_main) #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else - ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0, =(SYS_INIT_SP_ADDR) #endif bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ mov sp, r0 diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 84c04bd43a2db565154cea2fb79f8f48b11baaba..dcc924dd2f43157734bbbd9ead885409049165f5 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -13,6 +13,7 @@ #include #include #include +#include /* * This file handles the target-independent stages of the U-Boot @@ -81,7 +82,7 @@ ENTRY(_main) #endif add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET #else - ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) + ldr x0, =(SYS_INIT_SP_ADDR) #endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ mov x0, sp diff --git a/arch/arm/lib/vectors_m.S b/arch/arm/lib/vectors_m.S index 7d2d55c7f9facfb3d54f966f866783e457b65a62..8d88cc756fc1a867fa5ece2dc9147737e7112bf0 100644 --- a/arch/arm/lib/vectors_m.S +++ b/arch/arm/lib/vectors_m.S @@ -7,6 +7,7 @@ #include #include #include +#include .type __hard_fault_entry, %function __hard_fault_entry: @@ -35,7 +36,7 @@ __invalid_entry: .section .vectors ENTRY(_start) - .long CONFIG_SYS_INIT_SP_ADDR @ 0 - Reset stack pointer + .long SYS_INIT_SP_ADDR @ 0 - Reset stack pointer .long reset @ 1 - Reset .long __invalid_entry @ 2 - NMI .long __hard_fault_entry @ 3 - HardFault diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 6c49d6aede87830f2a91deff7d9adb336add4033..53c8a15bf9c8400cde3722eb7e5cc36b39756038 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -21,8 +22,37 @@ void board_init_f(ulong dummy) dram_init(); } +/* + * Try to detect the boot mode. Fallback to the default, + * memory mapped SPI XIP booting if detection failed. + */ u32 spl_boot_device(void) { + int rc; + struct udevice *scu_dev; + struct ast2600_scu *scu; + + rc = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev); + if (rc) { + debug("%s: failed to get SCU driver\n", __func__); + goto out; + } + + scu = devfdt_get_addr_ptr(scu_dev); + if (IS_ERR_OR_NULL(scu)) { + debug("%s: failed to get SCU base\n", __func__); + goto out; + } + + /* boot from UART has higher priority */ + if (scu->hwstrap2 & SCU_HWSTRAP2_BOOT_UART) + return BOOT_DEVICE_UART; + + if (scu->hwstrap1 & SCU_HWSTRAP1_BOOT_EMMC) + return BOOT_DEVICE_MMC1; + +out: return BOOT_DEVICE_RAM; } diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds new file mode 100644 index 0000000000000000000000000000000000000000..37f0ccd92201dcfc27c7cfa59ff743adea1a1458 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2022 + * Chia-Wei Wang + */ + +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_SIZE_LIMIT } +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + *(.vectors) + CPUDIR/start.o (.text*) + *(.text*) + *(.glue*) + } > .nor + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } > .nor + + . = ALIGN(4); + .data : { + *(.data*) + } > .nor + + . = ALIGN(4); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } > .nor + + . = ALIGN(4); + .binman_sym_table : { + __binman_sym_start = .; + KEEP(*(SORT(.binman_sym*))); + __binman_sym_end = .; + } > .nor + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } > .nor + + .end : + { + *(.__end) + } > .nor + + _image_binary_end = .; + + .bss : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .bss + + __bss_size = __bss_end - __bss_start; +} + +#if defined(IMAGE_MAX_SIZE) +ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \ + "SPL image too big"); +#endif + +#if defined(CONFIG_SPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \ + "SPL image BSS too big"); +#endif + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b87639f8c07bf89906f89cefc544132d64d1d0c0..11bfd5afe74555d2db0f1361b31267030af5d9da 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -327,6 +327,13 @@ config AT91_EFLASH Enable the driver for the embedded flash used in the Atmel AT91SAM9XE devices. +config EFLASH_PROTSECTORS + int "Number of flash sectors to protect from erasing" + depends on AT91_EFLASH + help + If non-zero, this will be the number of sectors of the flash to disallow + U-Boot to ease, starting from the beginning of flash. + config AT91_GPIO_PULLUP bool "Keep pullups on peripheral pins" depends on CPU_ARM926EJS @@ -370,8 +377,4 @@ source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS - default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7A - endif diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index 23c24936edf0246d5078959985544c66157edf32..043f06a82717d57fd2b9b1caa919e70039864f47 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -120,7 +120,7 @@ unsigned long flash_init(void) if (i%32 == 0) tmp = readl(&eefc->frr); flash_info[0].protect[i] = (tmp >> (i%32)) & 1; -#if defined(CONFIG_EFLASH_PROTSECTORS) +#if CONFIG_VAL(EFLASH_PROTSECTORS) if (i < CONFIG_EFLASH_PROTSECTORS) flash_info[0].protect[i] = 1; #endif @@ -158,7 +158,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) debug("protect sector=%ld prot=%d\n", sector, prot); -#if defined(CONFIG_EFLASH_PROTSECTORS) +#if CONFIG_VAL(EFLASH_PROTSECTORS) if (sector < CONFIG_EFLASH_PROTSECTORS) { if (!prot) { printf("eflash: sector %lu cannot be unprotected\n", diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 74f63552297c068f07fb4d4b1c275f78bc882648..1a8bf94dee0c88dd64e6833f9e2ad650957e0baa 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -29,7 +29,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram + __u_boot_list : { KEEP(*(SORT(__u_boot_list*))) } > .sram . = ALIGN(4); __image_copy_end = .; diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index 950ea55d7c4ef6120da2e8a66bf680da06140f17..6ca725fc4ce0cca04c4dd190ff1b23637f475097 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -36,7 +36,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram + __u_boot_list : { KEEP(*(SORT(__u_boot_list*))) } > .sram . = ALIGN(4); __image_copy_end = .; diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h index c3bd9140dfef83acea50dac87c604a44cfd30c44..b712be8051a8217950994521aa16b3782f89c2b5 100644 --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -74,6 +74,7 @@ struct atmel_pio4_port { #define AT91_PIO_PORTB 0x1 #define AT91_PIO_PORTC 0x2 #define AT91_PIO_PORTD 0x3 +#define AT91_PIO_PORTE 0x4 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config); int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config); diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..2d49380f879b7bf96196eba2fbf3c518be297415 --- /dev/null +++ b/arch/arm/mach-bcmbca/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if ARCH_BCMBCA + +config BCM47622 + bool "Support for Broadcom 47622 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select PL01X_SERIAL + +endif + +source "arch/arm/mach-bcmbca/bcm47622/Kconfig" diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..072d4ea7b5e606f98b6875a2d4c5c4edd448d194 --- /dev/null +++ b/arch/arm/mach-bcmbca/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +obj-$(CONFIG_BCM47622) += bcm47622/ diff --git a/arch/arm/mach-bcmbca/bcm47622/Kconfig b/arch/arm/mach-bcmbca/bcm47622/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..bce30892e35d64eb3e81670ebd7d03af7e61337c --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm47622/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM47622 + +config TARGET_BCM947622 + bool "Broadcom 47622 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm47622" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm47622/Makefile b/arch/arm/mach-bcmbca/bcm47622/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..beb979af7520c5e5eeb5143226976909e76b7179 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm47622/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 6eca8db6d5ff5c65a61c64f8b56b9dde290ad6e9..25c5db49915bc4e98eb8fded9daee1ea20176b4f 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -134,7 +134,4 @@ endif source "board/davinci/da8xxevm/Kconfig" source "board/lego/ev3/Kconfig" -config SPL_LDSCRIPT - default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds" - endif diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f73dbbb507d148e6e35fc9c1441adf8dc3a05565..84102908561e129dc7643d7e95b9c12c3ccc0a20 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -54,11 +54,15 @@ endchoice if ARCH_EXYNOS4 +config EXYNOS4210 + bool + choice prompt "EXYNOS4 board select" config TARGET_SMDKV310 bool "Exynos4210 SMDKV310 board" + select EXYNOS4210 select OF_CONTROL select SUPPORT_SPL @@ -70,6 +74,7 @@ config TARGET_S5PC210_UNIVERSAL config TARGET_ORIGEN bool "Exynos4412 Origen board" + select EXYNOS4210 select SUPPORT_SPL config TARGET_TRATS2 @@ -83,6 +88,15 @@ endif if ARCH_EXYNOS5 +config EXYNOS5250 + bool + +config EXYNOS5420 + bool + +config EXYNOS5_DT + bool + config SPL_GPIO default y @@ -97,6 +111,8 @@ choice config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL config TARGET_ARNDALE @@ -105,36 +121,49 @@ config TARGET_ARNDALE select ARM_ERRATA_774769 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5250 bool "SMDK5250 board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SNOW bool "Snow board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SPRING bool "Spring board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5420 bool "SMDK5420 board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL config TARGET_PEACH_PI bool "Peach Pi board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL config TARGET_PEACH_PIT bool "Peach Pit board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL @@ -189,6 +218,16 @@ endif config SYS_SOC default "exynos" +config EXYNOS_ACE_SHA + bool "Advanced Crypto Engine SHA support" + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && (LIB_HW_RAND || SHA_HW_ACCEL) + default y if ARCH_EXYNOS5 + +config EXYNOS_TMU + bool "Exynos5 thermal management unit support" + depends on ARCH_EXYNOS5 + default y + source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" @@ -201,7 +240,4 @@ source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" -config SPL_LDSCRIPT - default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 - endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index e895c13157f12481d35305ee74f351124440ae93..dd097cf541835da9223a6effa1eb2d66d21c901d 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -10,8 +10,8 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o -obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o +obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o +obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o obj-y += spl_boot.o tzpc.o obj-y += lowlevel_init.o diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c index ecddc7268497f7991565bd440e411aa661b07ac8..58a3c82f681d46fb106790219d7a4ebe56850653 100644 --- a/arch/arm/mach-exynos/dmc_init_exynos4.c +++ b/arch/arm/mach-exynos/dmc_init_exynos4.c @@ -175,7 +175,7 @@ void mem_ctrl_init(int reset) * 0: full_sync */ writel(1, ASYNC_CONFIG); -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + APB_SFR_INTERLEAVE_CONF_OFFSET); diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h index a08d64a8e23e6bbc5d4579a94a42d9690c059a45..fbb45eb897e3ca2adeb424d96773c0a8456fff56 100644 --- a/arch/arm/mach-exynos/exynos4_setup.h +++ b/arch/arm/mach-exynos/exynos4_setup.h @@ -420,7 +420,7 @@ struct mem_timings { #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830 -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ #define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507 #define APB_SFR_ARBRITATION_CONF_VAL 0x00000001 @@ -542,7 +542,7 @@ struct mem_timings { #define CONTROL2_VAL 0x00000000 -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN #define TIMINGREF_VAL 0x000000BB #define TIMINGROW_VAL 0x4046654f #define TIMINGDATA_VAL 0x46400506 diff --git a/arch/arm/mach-exynos/include/mach/pwm_backlight.h b/arch/arm/mach-exynos/include/mach/pwm_backlight.h deleted file mode 100644 index c7d3a91e318396b3698cb0022a48971654ba0fe4..0000000000000000000000000000000000000000 --- a/arch/arm/mach-exynos/include/mach/pwm_backlight.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee - */ - -#ifndef _PWM_BACKLIGHT_H_ -#define _PWM_BACKLIGHT_H_ - -struct pwm_backlight_data { - int pwm_id; - int period; - int max_brightness; - int brightness; -}; - -extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd); - -#endif /* _PWM_BACKLIGHT_H_ */ diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 48f13c76481bac4189860fdbdbb55d4dd311122e..5d0bebac5733e4cd5d3a727859c0c94324b9919f 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -116,6 +116,5 @@ struct exynos5_sysreg { void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); -int exynos_lcd_early_init(const void *blob); #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 2645a8ff492491e381fdf9fdcb204f8efe6546cb..1ff5fcac1b3814b8db6bcb52a13a1380f6a05744 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -49,6 +49,10 @@ enum { }; #ifdef CONFIG_EXYNOS5420 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + /* * Power up secondary CPUs. */ @@ -56,7 +60,7 @@ static void secondary_cpu_start(void) { v7_enable_smp(EXYNOS5420_INFORM_BASE); svc32_mode_en(); - branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE); + branch_bx(EXYNOS_RELOCATE_CODE_BASE); } /* @@ -153,7 +157,7 @@ static void power_down_core(void) static void secondary_cores_configure(void) { /* Clear secondary boot iRAM base */ - writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C)); + writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C)); /* set lowpower flag and address */ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index 59d05e6c01d9db1f89d18cab8216ca8ff6e00b70..40c07209e475a836f4d3800463844381d251401c 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -21,7 +21,7 @@ relocate_wait_code: .ltorg /* * Secondary core waits here until Primary wake it up. - * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE. + * Below code is copied to (CONFIG_IRAM_TOP - 0x1000) * This is a workaround code which is supposed to act as a * substitute/supplement to the iROM code. * diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..afe5f7a29eeec95ed52ab7bca73878a2d611cf56 --- /dev/null +++ b/arch/arm/mach-hpe/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SOC_GXP) += gxp/ diff --git a/arch/arm/mach-hpe/gxp/Kconfig b/arch/arm/mach-hpe/gxp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..2d43133ab06910de8b1cc4c8d995cb7d18ee390c --- /dev/null +++ b/arch/arm/mach-hpe/gxp/Kconfig @@ -0,0 +1,9 @@ +if ARCH_GXP + +config SOC_GXP + bool + select CPU_V7A + +source "board/hpe/gxp/Kconfig" + +endif diff --git a/arch/arm/mach-hpe/gxp/Makefile b/arch/arm/mach-hpe/gxp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f3cc6684b8969508c2aa6e359ec7354dade04275 --- /dev/null +++ b/arch/arm/mach-hpe/gxp/Makefile @@ -0,0 +1 @@ +obj-y += reset.o diff --git a/arch/arm/mach-hpe/gxp/reset.c b/arch/arm/mach-hpe/gxp/reset.c new file mode 100644 index 0000000000000000000000000000000000000000..ce018a35d94d112877a8db67910c89fd22a45f57 --- /dev/null +++ b/arch/arm/mach-hpe/gxp/reset.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GXP driver + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins + * Author: Jean-Marie Verdun + */ + +#include + +#define GXP_CCR 0xc0000000 + +/* empty to satisfy current lowlevel_init, can be removed any time */ +void lowlevel_init(void) +{ +} + +void reset_cpu(ulong ignored) +{ + writel(1, GXP_CCR); + + while (1) + ; /* loop forever till reset */ +} diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 5e1b20a422971b0582268a0f77c7719c61e5b356..2ba7454457ddd01d6047197247d85b546ab72472 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -20,13 +20,13 @@ config MU_BASE_SPL config IMX8QM select IMX8 select SUPPORT_SPL - select SPL_RECOVER_DATA_SECTION + select SPL_RECOVER_DATA_SECTION if SPL bool config IMX8QXP select IMX8 select SUPPORT_SPL - select SPL_RECOVER_DATA_SECTION + select SPL_RECOVER_DATA_SECTION if SPL bool config SYS_SOC @@ -57,11 +57,13 @@ config TARGET_COLIBRI_IMX8X config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT + select FACTORYSET select IMX8QXP config TARGET_GIEDI bool "Support i.MX8QXP Capricorn Giedi board" select BOARD_LATE_INIT + select FACTORYSET select IMX8QXP config TARGET_IMX8QM_MEK diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index a01bf23514990e3bdb2b18d37926975b814c275b..57f693e9a125380fafb27a62c86335e7147267e6 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -16,6 +16,9 @@ config SOC_K3_J721S2 config SOC_K3_AM642 bool "TI's K3 based AM642 SoC Family Support" +config SOC_K3_AM625 + bool "TI's K3 based AM625 SoC Family Support" + endchoice config SYS_SOC @@ -26,6 +29,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE default 0x80000 if SOC_K3_AM6 default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 default 0x1c0000 if SOC_K3_AM642 + default 0x3c000 if SOC_K3_AM625 help Describes the total size of the MCU or OCMC MSRAM present on the SoC in use. This doesn't specify the total size of SPL as @@ -37,6 +41,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE default 0x58000 if SOC_K3_AM6 default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 default 0x180000 if SOC_K3_AM642 + default 0x38000 if SOC_K3_AM625 help Describes the maximum size of the image that ROM can download from any boot media. @@ -61,6 +66,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 + default 0x43c3f290 if SOC_K3_AM625 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -129,6 +135,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW + default 163840 if SOC_K3_AM625 default 278000 help Amount of memory (in bytes) reserved through dynamic allocation at @@ -160,7 +167,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -171,6 +178,7 @@ config K3_DM_FW source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" +source "board/ti/am62x/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index c0a6a9c87d8fac4037a2591ed7e8e15e1db224f2..8459bef93bc8575620197e0878c01ffce03ae790 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o +obj-$(CONFIG_SOC_K3_AM625) += am625_init.o am62x/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_TI_SECURE_DEVICE) += security.o diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c new file mode 100644 index 0000000000000000000000000000000000000000..0d9525992bb09380a4894f1c028879b0af08abce --- /dev/null +++ b/arch/arm/mach-k3/am625_init.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625: SoC specific initialization + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#include +#include +#include +#include +#include "common.h" +#include +#include +#include + +#if defined(CONFIG_SPL_BUILD) + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#if defined(CONFIG_CPU_V7R) + setup_k3_mpu_regions(); +#endif + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + spl_early_init(); + + /* + * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and + * MAIN_UART1 modules and continue regardless of the result of pinctrl. + * Do this without probing the device, but instead by searching the + * device that would request the given sequence number if probed. The + * UARTs will be used by the DM firmware and TIFS firmware images + * respectively and the firmware depend on SPL to initialize the pin + * settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + preloader_console_init(); + +#ifdef CONFIG_K3_EARLY_CONS + /* + * Allow establishing an early console as required for example when + * doing a UART-based boot. Note that this console may not "survive" + * through a SYSFW PM-init step and will need a re-init in some way + * due to changing module clock frequencies. + */ + early_console_init(); +#endif + +#if defined(CONFIG_K3_LOAD_SYSFW) + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM configuration + * callback hook, effectively switching on (or over) the console + * output. + */ + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); +#endif + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); + +#if defined(CONFIG_K3_AM64_DDRSS) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); +#endif +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT) + return MMCSD_MODE_EMMCBOOT; + return MMCSD_MODE_FS; + + case BOOT_DEVICE_MMC2: + return MMCSD_MODE_FS; + + default: + return MMCSD_MODE_RAW; + } +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + + return bootmedia; +} + +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..d6c876df66ddeda3228a8bc35c5874cc9de8aa1e --- /dev/null +++ b/arch/arm/mach-k3/am62x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c new file mode 100644 index 0000000000000000000000000000000000000000..c0881778fe70db7a648fe1a4ec534eee728c4506 --- /dev/null +++ b/arch/arm/mach-k3/am62x/clk-data.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62X specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", + "clk_32k_rc_sel_div_clkout", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv1_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"), + DEV_CLK(13, 20, "board_0_rgmii1_txc_out"), + DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"), + DEV_CLK(13, 23, "board_0_rgmii2_txc_out"), + DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"), + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), + DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), + DEV_CLK(57, 2, "board_0_mmc0_clk_out"), + DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), + DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(95, 2, "wkup_clksel_out0"), + DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"), + DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(107, 0, "wkup_clksel_out0"), + DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"), + DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"), + DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 20, "clkout0_ctrl_out0"), + DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), + DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"), + DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"), + DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"), + DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 158, "wkup_clkout_sel_out0"), + DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"), + DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"), + DEV_CLK(157, 164, "clk_32k_rc_sel_out0"), + DEV_CLK(157, 165, "gluelogic_rcosc_clkout"), + DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 1, "board_0_tck_out"), + DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62x_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 90, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 137, +}; diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c new file mode 100644 index 0000000000000000000000000000000000000000..616d0650b9c09dee3a12d9315397738e8fab2ad4 --- /dev/null +++ b/arch/arm/mach-k3/am62x/dev-data.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62X specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x04000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[1], NULL), + [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]), + [4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]), + [3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]), + [4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]), + [6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]), + [13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]), + [14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]), + [15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(95, &soc_lpsc_list[0]), + PSC_DEV(107, &soc_lpsc_list[0]), + PSC_DEV(170, &soc_lpsc_list[1]), + PSC_DEV(177, &soc_lpsc_list[2]), + PSC_DEV(55, &soc_lpsc_list[3]), + PSC_DEV(178, &soc_lpsc_list[4]), + PSC_DEV(179, &soc_lpsc_list[5]), + PSC_DEV(57, &soc_lpsc_list[6]), + PSC_DEV(58, &soc_lpsc_list[7]), + PSC_DEV(161, &soc_lpsc_list[8]), + PSC_DEV(162, &soc_lpsc_list[9]), + PSC_DEV(75, &soc_lpsc_list[10]), + PSC_DEV(102, &soc_lpsc_list[11]), + PSC_DEV(146, &soc_lpsc_list[11]), + PSC_DEV(13, &soc_lpsc_list[12]), + PSC_DEV(166, &soc_lpsc_list[13]), + PSC_DEV(135, &soc_lpsc_list[14]), + PSC_DEV(136, &soc_lpsc_list[15]), +}; + +const struct ti_k3_pd_platdata am62x_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 5, + .num_lpsc = 16, + .num_devs = 21, +}; diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 86c1a349f1fc6d49d78a641a21f43a08bc44ae53..7992918adcdcb28e017fdf051ecbc4abc9df8c77 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -127,8 +127,8 @@ static int fixup_usb_boot(void) * before the dwc3 bind takes place */ ret = fdt_find_and_setprop((void *)gd->fdt_blob, - "/interconnect@100000/dwc3@4000000/usb@10000", - "dr_mode", "host", 11, 0); + "/bus@100000/dwc3@4000000/usb@10000", + "dr_mode", "host", 5, 0); if (ret) printf("%s: fdt_find_and_setprop() failed:%d\n", __func__, ret); diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 527e664318883b2b3ea2d7792b21ec717bee4402..12cb89335ad3bccc76c7002f7c0439b3656a0690 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -222,7 +222,7 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ -#ifdef CONFIG_SOC_K3_AM642 +#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625)) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) @@ -261,4 +261,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 */ +#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */ diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b4b75f4e6c8671412b41e9be91acdba336c13a71..70f6444e7988cd45a02ae521df576e7eef81b80d 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -516,7 +516,7 @@ void spl_enable_dcache(void) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; - dram_init_banksize(); + dram_init(); /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h new file mode 100644 index 0000000000000000000000000000000000000000..cfabd20cbd79f6a3aac10e91756f8ad1e1003a76 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM62 SoC definitions, structures etc. + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#ifndef __ASM_ARCH_AM62_HARDWARE_H +#define __ASM_ARCH_AM62_HARDWARE_H + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0 + +/* Use Last 2K as Scratch pad */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000 + +#endif /* __ASM_ARCH_AM62_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62_spl.h b/arch/arm/mach-k3/include/mach/am62_spl.h new file mode 100644 index 0000000000000000000000000000000000000000..2c9139d2cc00d6c24195eef520f74a6223c6a479 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62_spl.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#ifndef _ASM_ARCH_AM62_SPL_H_ +#define _ASM_ARCH_AM62_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_RAM 0x00 +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_AM62_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 5c1265ffe94963ff91a6180af996d91d8b7ca334..7c6928d5da1cbde314128330d8541e9c9225e679 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -22,6 +22,10 @@ #include "am64_hardware.h" #endif +#ifdef CONFIG_SOC_K3_AM625 +#include "am62_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID 0x43000014 #define JTAG_ID_VARIANT_SHIFT 28 diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 8a61398529567b2d0ea8472dca8109b0aabb8d65..17996f2938b76d5b0c8be36b14df430b3b84a597 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -21,4 +21,9 @@ #ifdef CONFIG_SOC_K3_AM642 #include "am64_spl.h" #endif + +#ifdef CONFIG_SOC_K3_AM625 +#include "am62_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index f503f15f192ac83b9e1d09d52c2e9c3b3bc843c4..e56ca6d0f5ff91616f532be9197032451f5b1328 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -355,6 +355,17 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) return bootmode; } +u32 spl_spi_boot_bus(void) +{ + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); + u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) | + ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT); + + return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0; +} + u32 spl_boot_device(void) { u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 5e48c36ccd58cf79c7a045699e25d37413e001df..b3beeca9472edf18bcf2d7df8aeb1491704dbfc8 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -324,9 +324,9 @@ static void *k3_sysfw_get_spi_addr(void) struct udevice *dev; fdt_addr_t addr; int ret; + unsigned int sf_bus = spl_spi_boot_bus(); - ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS, - &dev); + ret = uclass_find_device_by_seq(UCLASS_SPI, sf_bus, &dev); if (ret) return NULL; @@ -346,6 +346,25 @@ static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t len) } #endif +#if CONFIG_IS_ENABLED(NOR_SUPPORT) +static void *get_sysfw_hf_addr(void) +{ + struct udevice *dev; + fdt_addr_t addr; + int ret; + + ret = uclass_find_first_device(UCLASS_MTD, &dev); + if (ret) + return NULL; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS); +} +#endif + void k3_sysfw_loader(bool rom_loaded_sysfw, void (*config_pm_pre_callback)(void), void (*config_pm_done_callback)(void)) @@ -413,6 +432,15 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, CONFIG_K3_SYSFW_IMAGE_SIZE_MAX); break; #endif +#if CONFIG_IS_ENABLED(NOR_SUPPORT) + case BOOT_DEVICE_HYPERFLASH: + sysfw_spi_base = get_sysfw_hf_addr(); + if (!sysfw_spi_base) + ret = -ENODEV; + k3_sysfw_spi_copy(sysfw_load_address, sysfw_spi_base, + CONFIG_K3_SYSFW_IMAGE_SIZE_MAX); + break; +#endif #if CONFIG_IS_ENABLED(YMODEM_SUPPORT) case BOOT_DEVICE_UART: #ifdef CONFIG_K3_EARLY_CONS diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c index c4a1908af8d03df3428b040c199b1e2c62f13bb1..6f7f8ab7b40c4a7c11e30e43516e3d59403d9e4e 100644 --- a/arch/arm/mach-keystone/ddr3_spd.c +++ b/arch/arm/mach-keystone/ddr3_spd.c @@ -404,24 +404,11 @@ static void init_ddr3param(struct ddr3_spd_cb *spd_cb, static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params) { int ret; -#if !CONFIG_IS_ENABLED(DM_I2C) - int old_bus; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256); - - i2c_set_bus_num(old_bus); -#else struct udevice *dev; ret = i2c_get_chip_for_busnum(1, 0x53, 1, &dev); if (!ret) ret = dm_i2c_read(dev, 0, (unsigned char *)spd_params, 256); -#endif if (ret) { printf("Cannot read DIMM params\n"); return 1; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ca2da003b65b71d7650e85147567ebd57eae6dd1..98bb10c2dee3dc554eacd8aef568cb5da8ceb735 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -121,6 +121,18 @@ endchoice config SYS_SOC default "kirkwood" +config KIRKWOOD_RGMII_PAD_1V8 + bool "Configures the I/O voltage of the pads connected gigabit interface to 1.8V" + default y + +config KIRKWOOD_EGIGA_INIT + bool "Enable GbePort0/1 for kernel" + default y + +config KIRKWOOD_PCIE_INIT + bool "Enable PCIe Port0 for kernel" + default y + source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 7810cf22d4ea2e268d36434a7cbca8ec33b810a1..90e86ab99b414d815069cdc6b3f074f6fb8ed8bf 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -23,12 +23,6 @@ #endif /* CONFIG_KW88F6281 */ #include -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ - -/* Kirkwood has 2k of Security SRAM, use it for SP */ -#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE #define MV_UART_CONSOLE_BASE KW_UART0_BASE @@ -52,8 +46,6 @@ #define __io /* Data, registers and alternate blocks are at the same offset */ /* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 /* CONFIG_IDE requires some #defines for ATA registers */ /* ATA registers base is at SATA controller base */ #endif /* CONFIG_IDE */ diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 8bd2246325cafd3d6e34f2402c4414e0a671a469..61eeb9c8c186f691aab84ea5aeef471d2eb0fc59 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -65,10 +65,12 @@ KWB_REPLACE += CSK_INDEX KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX) KWB_REPLACE += SEC_BOOT_DEV -KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \ - $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \ - $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \ - ) +ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),) + KWB_CFG_SEC_BOOT_DEV=0x34 +endif +ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),) + KWB_CFG_SEC_BOOT_DEV=0x31 +endif KWB_REPLACE += SEC_FUSE_DUMP KWB_CFG_SEC_FUSE_DUMP = a38x diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index fb4e5af770c78e49c78edba5ff67da6b25742514..4add0d9e1030da3a996a747a44f1ff1f1a1e3089 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -27,9 +27,6 @@ #define CONFIG_SYS_L2_PL310 -/* end of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 - #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE /* Needed for SPI NOR booting in SPL */ diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S index 501c239e9d38baa05579d05e8f7ccf0ad065997b..49891df9ea9e80f05589f1b30a9f3042ca8fea15 100644 --- a/arch/arm/mach-mvebu/lowlevel_spl.S +++ b/arch/arm/mach-mvebu/lowlevel_spl.S @@ -8,19 +8,19 @@ * contains U-Boot SPL, optionally it can also contain additional arguments. * The number of these arguments is in r0, pointer to the argument array in r1. * BootROM expects executable BIN header code to return to address stored in lr. - * Other registers (r2 - r12) must be preserved. We save all registers to - * CONFIG_SPL_BOOTROM_SAVE address. BIN header arguments (passed via r0 and r1) + * Other registers (r2 - r12) must be preserved. We save all registers to the + * address of CONFIG_SPL_STACK + 4. BIN header arguments (passed via r0 and r1) * are currently not used by U-Boot SPL binary. */ ENTRY(save_boot_params) stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */ - ldr r12, =CONFIG_SPL_BOOTROM_SAVE + ldr r12, =(CONFIG_SPL_STACK + 4) str sp, [r12] b save_boot_params_ret ENDPROC(save_boot_params) ENTRY(return_to_bootrom) - ldr r12, =CONFIG_SPL_BOOTROM_SAVE + ldr r12, =(CONFIG_SPL_STACK + 4) ldr sp, [r12] ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */ mov r0, #0x0 /* @ return value: 0x0 NO_ERR */ diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index fa9a1d7ab65e1a0ad042e2e726d61dee86b41205..13c99913c380e230f6c97f1f6608066441b99eec 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -283,7 +283,7 @@ u32 spl_boot_device(void) int board_return_to_bootrom(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { - u32 *regs = *(u32 **)CONFIG_SPL_BOOTROM_SAVE; + u32 *regs = *(u32 **)(CONFIG_SPL_STACK + 4); printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]); return_to_bootrom(); diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e1b9180a3bb3a4b1ff49c5465d3e48d6b35b4cf9..fa41047476739a342064d61333f50bd594520c49 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -169,6 +169,27 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE using hardware memory firewalls. This value must be smaller than the TI_SECURE_EMIF_TOTAL_REGION_SIZE value. +config SYS_AUTOMATIC_SDRAM_DETECTION + bool + +choice + depends on OMAP44XX || OMAP54XX + prompt "Static or dynamic DDR timing calculations" + default SYS_EMIF_PRECALCULATED_TIMING_REGS + help + For the DDR timing information we can either dynamically determine + the timings to use or use pre-determined timings (based on using the + dynamic method). Default to the static timing information. + +config SYS_EMIF_PRECALCULATED_TIMING_REGS + bool "Use precalcualted timing values" + +config SYS_DEFAULT_LPDDR2_TIMINGS + bool "Use default LPDDR2 timing values" + select SYS_AUTOMATIC_SDRAM_DETECTION + +endchoice + source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap4/Kconfig" @@ -190,7 +211,4 @@ source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/phytec/phycore_am335x_r2/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 23865d4c070422e668ddcc3a76dc04cbb54a9a0f..bd6b086552606d569dbb53466e96f17447752418 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -138,6 +138,7 @@ config TARGET_DRACO select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_ETAMIN @@ -146,6 +147,7 @@ config TARGET_ETAMIN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_PCM051 @@ -168,6 +170,7 @@ config TARGET_PXM2 select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_RASTABAN @@ -176,6 +179,7 @@ config TARGET_RASTABAN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_RUT @@ -184,6 +188,7 @@ config TARGET_RUT select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_THUBAN @@ -192,6 +197,7 @@ config TARGET_THUBAN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_PDU001 diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index d7d779819bf35e26fabb64699e1d081c3bd86246..491e7c23dbc688aeaa6f1f67971a0e2fe2dc3722 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -41,7 +41,7 @@ static u32 get_sdr_cs_size(u32 cs) /* TODO: Calculate the size based on EMIF4 configuration */ if (cs == CS0) - size = CONFIG_SYS_CS0_SIZE; + size = 256 * 1024 * 1024; return size; } diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c index 4672dc534c5efbbef5d9ebb4afee2365b0a9b60d..53c39ce1fb6899d2c86992edf129d8e77ec87f0c 100644 --- a/arch/arm/mach-omap2/sata.c +++ b/arch/arm/mach-omap2/sata.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pipe3-phy.h" static struct pipe3_dpll_map dpll_map_sata[] = { diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 82b10f6b2487c213b2b85177ef8777db098919b9..00d91c10136d98f1915e977cae512e226d597932 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -22,6 +22,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -33,7 +34,7 @@ static ulong get_timer_masked(void); * Nothing really to do with interrupts, just starts up a counter. */ -#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) +#define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) #define TIMER_OVERFLOW_VAL 0xffffffff #define TIMER_LOAD_VAL 0 @@ -42,7 +43,7 @@ int timer_init(void) /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, + writel((SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, &timer_base->tclr); return 0; diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds index 88d81f9b98d61cfdf562e077f7666800d71dadaf..1d6e5d45b4689567d3209063d17508c9252cbaf2 100644 --- a/arch/arm/mach-omap2/u-boot-spl.lds +++ b/arch/arm/mach-omap2/u-boot-spl.lds @@ -33,8 +33,8 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } >.sram . = ALIGN(4); diff --git a/arch/arm/mach-orion5x/u-boot-spl.lds b/arch/arm/mach-orion5x/u-boot-spl.lds index a537fe02954bbb9a862a209d74b7d37ed9eee7d4..154bb1206035460a6629271472c02cd80c974bb0 100644 --- a/arch/arm/mach-orion5x/u-boot-spl.lds +++ b/arch/arm/mach-orion5x/u-boot-spl.lds @@ -41,8 +41,8 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .nor . = ALIGN(4); diff --git a/arch/arm/mach-rmobile/lowlevel_init.S b/arch/arm/mach-rmobile/lowlevel_init.S index eb6012a87409bea9c8c4206ad803edea59da6c07..212e95539bc90742d06a9acd6e848d1b96b9f095 100644 --- a/arch/arm/mach-rmobile/lowlevel_init.S +++ b/arch/arm/mach-rmobile/lowlevel_init.S @@ -6,6 +6,7 @@ #include #include +#include ENTRY(lowlevel_init) ldr r0, =MERAM_BASE diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S b/arch/arm/mach-rmobile/lowlevel_init_ca15.S index 967fb027a4331f52373f0f0504c5ea195c7ea56f..a52b761b25d172a832f2d38bda37a6160f0292f4 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S +++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S @@ -8,6 +8,7 @@ #include #include +#include ENTRY(lowlevel_init) #ifndef CONFIG_SPL_BUILD @@ -75,7 +76,7 @@ _enable_actlr_smp: /* R8A7794 only (CA7) */ #endif _exit_init_l2_a15: - ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r3, =(SYS_INIT_SP_ADDR) sub sp, r3, #4 str lr, [sp] diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 4886fe946e3a194eec3e6c7e05f7bdd1b84a54fb..28639c00414ccf0d495798f82149b70d64d15ab0 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -56,9 +56,6 @@ config TPL_LDSCRIPT config TPL_TEXT_BASE default 0xff0e1000 -config TPL_MAX_SIZE - default 10240 - config TPL_STACK default 0xff0e4fff diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 058f848ddc703682f7e9075c16ac9221cced3427..9ad1f54055b3c8f65a4d541d11fd3b664e0188eb 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -26,9 +26,6 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL default y -config TPL_MAX_SIZE - default 28672 - config TPL_STACK default 0x10088000 diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index dd8c7826fc10d6b4dcc48a455286bdddbbb24acd..e8c57843a38fe0d304d3adbc14d5dd1cd23d7c78 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -172,9 +172,6 @@ config SPL_SERIAL config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl.lds" -config TPL_MAX_SIZE - default 32768 - config TPL_STACK default 0xff718000 diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index f6f1e06a83fe9d86ba9202e81ec20274829a50d8..d5cb649ae6baa49698d7f8b877e6bdaf224a6d9d 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -36,9 +36,6 @@ config TPL_LDSCRIPT config TPL_TEXT_BASE default 0xff091000 -config TPL_MAX_SIZE - default 28672 - config TPL_STACK default 0xff098000 diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 104db36737bf77a87b86a8409b3b76462976063f..c3249a7be457d3c27767c43b1398980da89b5c40 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -65,15 +65,9 @@ source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" - config SPL_STACK_R_ADDR default 0x04000000 -config TPL_MAX_SIZE - default 28672 - config TPL_STACK default 0xff8cffff diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index c1f251316cb2f61dbef709af511239dcdd0dc995..b48feeb3466cb50ade0b9c4e1f7596abbdb428fd 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -143,9 +143,6 @@ config SPL_LIBGENERIC_SUPPORT config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" -config TPL_MAX_SIZE - default 188416 - config TPL_STACK default 0xff8effff diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds index 9869972e222042a112bd3a5cede7a6631fa8d8d1..74618eba591b3f565e49116298824c19a6457465 100644 --- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -39,9 +39,9 @@ SECTIONS *(.data*) } - .u_boot_list : { + __u_boot_list : { . = ALIGN(8); - KEEP(*(SORT(.u_boot_list*))); + KEEP(*(SORT(__u_boot_list*))); } .image_copy_end : { diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index f9a583af8d85bffb1ff1620e71fb970140dead9d..d9e264024c8e8b51d0eef685c5d22c3680a824e4 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -9,7 +9,7 @@ choice config TARGET_STIH410_B2260 bool "96Boards STiH410-B2260" help - Support for 96Board STiH410-B2260 based on STMicrolectronics + Support for 96Board STiH410-B2260 based on STMicroelectronics STiH410 soc. This board complies with 96Board Open Platform Specifications. Features: - 1GB DDR diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index e48f98ba29437f0275d3fc4b8ddb5ccb12dd0f14..db47baba6d1ae8377cbe51bafa325d4dd4f950bc 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -33,6 +33,28 @@ config SYS_MALLOC_LEN config ENV_SIZE default 0x2000 +choice + prompt "Select STMicroelectronics STM32MPxxx Soc" + default STM32MP15x + +config STM32MP13x + bool "Support STMicroelectronics STM32MP13x Soc" + select ARM_SMCCC + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select OF_BOARD + select OF_BOARD_SETUP + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + imply CMD_NVEDIT_INFO + help + support of STMicroelectronics SOC STM32MP13x family + STMicroelectronics MPU with core ARMv7 + config STM32MP15x bool "Support STMicroelectronics STM32MP15x Soc" select ARCH_SUPPORT_PSCI @@ -46,6 +68,7 @@ config STM32MP15x select STM32_RCC select STM32_RESET select STM32_SERIAL + select SUPPORT_SPL select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO help @@ -53,92 +76,8 @@ config STM32MP15x STM32MP157, STM32MP153 or STM32MP151 STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 - target all the STMicroelectronics board with SOC STM32MP1 family - -config STM32MP15x_STM32IMAGE - bool "Support STM32 image for generated U-Boot image" - depends on STM32MP15x && TFABOOT - help - Support of STM32 image generation for SOC STM32MP15x - for TF-A boot when FIP container is not used - -choice - prompt "STM32MP15x board select" - optional - -config TARGET_ST_STM32MP15x - bool "STMicroelectronics STM32MP15x boards" - select STM32MP15x - imply BOOTSTAGE - imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE - help - target the STMicroelectronics board with SOC STM32MP15x - managed by board/st/stm32mp1: - Evalulation board (EV1) or Discovery board (DK1 and DK2). - The difference between board are managed with devicetree - -config TARGET_MICROGEA_STM32MP1 - bool "Engicam MicroGEA STM32MP1 SOM" - select STM32MP15x - imply BOOTSTAGE - imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE - help - MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. - - MicroGEA STM32MP1 MicroDev 2.0: - * MicroDev 2.0 is a general purpose miniature carrier board with CAN, - LTE and LVDS panel interfaces. - * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board - for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. - - MicroGEA STM32MP1 MicroDev 2.0 7" OF: - * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS - panel and toucscreen. - * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with - pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" - Open Frame Solution board. - -config TARGET_ICORE_STM32MP1 - bool "Engicam i.Core STM32MP1 SOM" - select STM32MP15x - imply BOOTSTAGE - imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE - help - i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. - - i.Core STM32MP1 EDIMM2.2: - * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. - * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for - creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. - - i.Core STM32MP1 C.TOUCH 2.0 - * C.TOUCH 2.0 is a general purpose Carrier board. - * i.Core STM32MP1 needs to mount on top of this Carrier board - for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. - -config TARGET_DH_STM32MP1_PDK2 - bool "DH STM32MP1 PDK2" - select STM32MP15x - help - Target the DH PDK2 development kit with STM32MP15x SoM. - endchoice -config SYS_TEXT_BASE - default 0xC0100000 - config NR_DRAM_BANKS default 1 @@ -164,7 +103,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 config STM32_ETZPC bool "STM32 Extended TrustZone Protection" - depends on STM32MP15x + depends on STM32MP15x || STM32MP13x default y imply BOOTP_SERVERIP help @@ -187,41 +126,8 @@ config CMD_STM32KEY This command is used to evaluate the secure boot on stm32mp SOC, it is deactivated by default in real products. -config PRE_CON_BUF_ADDR - default 0xC02FF000 - -config PRE_CON_BUF_SZ - default 4096 - -config BOOTSTAGE_STASH_ADDR - default 0xC3000000 - -if BOOTCOUNT_GENERIC -config SYS_BOOTCOUNT_SINGLEWORD - default y - -# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) -config SYS_BOOTCOUNT_ADDR - default 0x5C00A154 -endif - -if DEBUG_UART - -config DEBUG_UART_BOARD_INIT - default y - -# debug on UART4 by default -config DEBUG_UART_BASE - default 0x40010000 - -# clock source is HSI on reset -config DEBUG_UART_CLOCK - default 64000000 -endif +source "arch/arm/mach-stm32mp/Kconfig.13x" +source "arch/arm/mach-stm32mp/Kconfig.15x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" -source "board/dhelectronics/dh_stm32mp1/Kconfig" -source "board/engicam/stm32mp1/Kconfig" -source "board/st/stm32mp1/Kconfig" - endif diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x new file mode 100644 index 0000000000000000000000000000000000000000..5fc000986e11edd88fc2d7daa16cd8acc5b9b28f --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -0,0 +1,57 @@ +if STM32MP13x + +choice + prompt "STM32MP13x board select" + optional + +config TARGET_ST_STM32MP13x + bool "STMicroelectronics STM32MP13x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + target the STMicroelectronics board with SOC STM32MP13x + managed by board/st/stm32mp1. + The difference between board are managed with devicetree + +endchoice + +config SYS_TEXT_BASE + default 0xC0000000 + +config PRE_CON_BUF_ADDR + default 0xC0800000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0xC3000000 + +if BOOTCOUNT_GENERIC +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(31) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A17C +endif + +if DEBUG_UART + +# debug on UART4 by default +config DEBUG_UART_BASE + default 0x40010000 + +# clock source is HSI on reset +config DEBUG_UART_CLOCK + default 48000000 if STM32_FPGA + default 64000000 +endif + +source "board/st/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x new file mode 100644 index 0000000000000000000000000000000000000000..d516270292a3081e630a92f3082df277c8eb3e6d --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -0,0 +1,135 @@ +if STM32MP15x + +config STM32MP15x_STM32IMAGE + bool "Support STM32 image for generated U-Boot image" + depends on TFABOOT + help + Support of STM32 image generation for SOC STM32MP15x + for TF-A boot when FIP container is not used + +choice + prompt "STM32MP15x board select" + optional + +config TARGET_ST_STM32MP15x + bool "STMicroelectronics STM32MP15x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + target the STMicroelectronics board with SOC STM32MP15x + managed by board/st/stm32mp1: + Evalulation board (EV1) or Discovery board (DK1 and DK2). + The difference between board are managed with devicetree + +config TARGET_DH_STM32MP1_PDK2 + bool "DH STM32MP1 PDK2" + help + Target the DH PDK2 development kit with STM32MP15x SoM. + +config TARGET_MICROGEA_STM32MP1 + bool "Engicam MicroGEA STM32MP1 SOM" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. + + MicroGEA STM32MP1 MicroDev 2.0: + * MicroDev 2.0 is a general purpose miniature carrier board with CAN, + LTE and LVDS panel interfaces. + * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board + for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. + + MicroGEA STM32MP1 MicroDev 2.0 7" OF: + * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS + panel and toucscreen. + * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with + pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" + Open Frame Solution board. + +config TARGET_ICORE_STM32MP1 + bool "Engicam i.Core STM32MP1 SOM" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. + + i.Core STM32MP1 EDIMM2.2: + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. + * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for + creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. + + i.Core STM32MP1 C.TOUCH 2.0 + * C.TOUCH 2.0 is a general purpose Carrier board. + * i.Core STM32MP1 needs to mount on top of this Carrier board + for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. + +endchoice + +config STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR" + depends on DM_REGULATOR && DM_PMIC + default y + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR. + +config SPL_STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR in SPL" + depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC + default y + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR in SPL. + +config SYS_TEXT_BASE + default 0xC0100000 + +config PRE_CON_BUF_ADDR + default 0xC02FF000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0xC3000000 + +if BOOTCOUNT_GENERIC +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A154 +endif + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on UART4 by default +config DEBUG_UART_BASE + default 0x40010000 + +# clock source is HSI on reset +config DEBUG_UART_CLOCK + default 64000000 +endif + +source "board/st/stm32mp1/Kconfig" +source "board/dhelectronics/dh_stm32mp1/Kconfig" +source "board/engicam/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 391b47cf13f82d6622240857bb96d8c94aca6081..1db9057e049cb1d2bde697fdd65e8a03b5a53dd7 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -8,6 +8,9 @@ obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o +obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP15x) += stm32mp15x.o + ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o @@ -19,5 +22,5 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_TFABOOT) += boot_params.o endif -obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o +obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 506caa0a31b1916f6f391e2a947fa2db5e546f03..c00130b08b3630e97855753478794e67a9c122d5 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -632,3 +632,20 @@ bool bsec_dbgswenable(void) return false; } + +u32 get_otp(int index, int shift, int mask) +{ + int ret; + struct udevice *dev; + u32 otp = 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(index), + &otp, sizeof(otp)); + + return (otp >> shift) & mask; +} diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 0ad5f307dba2c3d9455263ced6bc6567fa2f97c6..855fc755fe08862d46cbb6d277c958c716d31f07 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -24,67 +23,6 @@ #include #include -/* RCC register */ -#define RCC_TZCR (STM32_RCC_BASE + 0x00) -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_BDCR (STM32_RCC_BASE + 0x0140) -#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) -#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) -#define RCC_BDCR_VSWRST BIT(31) -#define RCC_BDCR_RTCSRC GENMASK(17, 16) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* Security register */ -#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) -#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) - -#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) -#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) -#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) - -#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) - -#define PWR_CR1 (STM32_PWR_BASE + 0x00) -#define PWR_MCUCR (STM32_PWR_BASE + 0x14) -#define PWR_CR1_DBP BIT(8) -#define PWR_MCUCR_SBF BIT(6) - -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -/* GPIOZ registers */ -#define GPIOZ_SECCFGR 0x54004030 - -/* boot interface from Bootrom - * - boot instance = bit 31:16 - * - boot device = bit 15:0 - */ -#define BOOTROM_PARAM_ADDR 0x2FFC0078 -#define BOOTROM_MODE_MASK GENMASK(15, 0) -#define BOOTROM_MODE_SHIFT 0 -#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) -#define BOOTROM_INSTANCE_SHIFT 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) - -/* Package = bit 27:29 of OTP16 - * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm - * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm - * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm - * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm - * - others: Reserved - */ -#define PKG_SHIFT 27 -#define PKG_MASK GENMASK(2, 0) - /* * early TLB into the .data section so that it not get cleared * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) @@ -93,121 +31,6 @@ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); struct lmb lmb; -static void security_init(void) -{ - /* Disable the backup domain write protection */ - /* the protection is enable at each reset by hardware */ - /* And must be disable by software */ - setbits_le32(PWR_CR1, PWR_CR1_DBP); - - while (!(readl(PWR_CR1) & PWR_CR1_DBP)) - ; - - /* If RTC clock isn't enable so this is a cold boot then we need - * to reset the backup domain - */ - if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { - setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); - while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) - ; - clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); - } - - /* allow non secure access in Write/Read for all peripheral */ - writel(GENMASK(25, 0), ETZPC_DECPROT0); - - /* Open SYSRAM for no secure access */ - writel(0x0, ETZPC_TZMA1_SIZE); - - /* enable TZC1 TZC2 clock */ - writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); - - /* Region 0 set to no access by default */ - /* bit 0 / 16 => nsaid0 read/write Enable - * bit 1 / 17 => nsaid1 read/write Enable - * ... - * bit 15 / 31 => nsaid15 read/write Enable - */ - writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); - /* bit 30 / 31 => Secure Global Enable : write/read */ - /* bit 0 / 1 => Region Enable for filter 0/1 */ - writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); - - /* Enable Filter 0 and 1 */ - setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); - - /* RCC trust zone deactivated */ - writel(0x0, RCC_TZCR); - - /* TAMP: deactivate the internal tamper - * Bit 23 ITAMP8E: monotonic counter overflow - * Bit 20 ITAMP5E: RTC calendar overflow - * Bit 19 ITAMP4E: HSE monitoring - * Bit 18 ITAMP3E: LSE monitoring - * Bit 16 ITAMP1E: RTC power domain supply monitoring - */ - writel(0x0, TAMP_CR1); - - /* GPIOZ: deactivate the security */ - writel(BIT(0), RCC_MP_AHB5ENSETR); - writel(0x0, GPIOZ_SECCFGR); -} - -/* - * Debug init - */ -static void dbgmcu_init(void) -{ - /* - * Freeze IWDG2 if Cortex-A7 is in debug mode - * done in TF-A for TRUSTED boot and - * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE - */ - if (bsec_dbgswenable()) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); - } -} - -void spl_board_init(void) -{ - struct udevice *dev; - int ret; - - dbgmcu_init(); - - /* force probe of BSEC driver to shadow the upper OTP */ - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); - if (ret) - log_warning("BSEC probe failed: %d\n", ret); -} - -/* get bootmode from ROM code boot context: saved in TAMP register */ -static void update_bootmode(void) -{ - u32 boot_mode; - u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); - u32 bootrom_device, bootrom_instance; - - /* enable TAMP clock = RTCAPBEN */ - writel(BIT(8), RCC_MP_APB5ENSETR); - - /* read bootrom context */ - bootrom_device = - (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; - bootrom_instance = - (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; - boot_mode = - ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | - ((bootrom_instance << BOOT_INSTANCE_SHIFT) & - BOOT_INSTANCE_MASK); - - /* save the boot mode in TAMP backup register */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, - TAMP_BOOT_MODE_MASK, - boot_mode << TAMP_BOOT_MODE_SHIFT); -} - u32 get_bootmode(void) { /* read bootmode from TAMP backup register */ @@ -229,8 +52,11 @@ void dram_bank_mmu_setup(int bank) enum dcache_option option; if (IS_ENABLED(CONFIG_SPL_BUILD)) { +/* STM32_SYSRAM_BASE exist only when SPL is supported */ +#ifdef CONFIG_SPL start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); +#endif } else if (gd->flags & GD_FLG_RELOC) { /* bd->bi_dram is available only after relocation */ start = bd->bi_dram[bank].start; @@ -277,25 +103,24 @@ static void early_enable_caches(void) */ int arch_cpu_init(void) { - u32 boot_mode; - early_enable_caches(); /* early armv7 timer init: needed for polling */ timer_init(); - if (IS_ENABLED(CONFIG_SPL_BUILD)) { - security_init(); - update_bootmode(); - } -/* reset copro state in SPL, when used, or in U-Boot */ - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { - /* Reset Coprocessor state unless it wakes up from Standby power mode */ - if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { - writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); - writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); - } - } + return 0; +} + +/* weak function for SOC specific initialization */ +__weak void stm32mp_cpu_init(void) +{ +} + +int mach_cpu_init(void) +{ + u32 boot_mode; + + stm32mp_cpu_init(); boot_mode = get_bootmode(); @@ -324,139 +149,6 @@ void enable_caches(void) dcache_enable(); } -static u32 read_idc(void) -{ - /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ - if (bsec_dbgswenable()) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - - return readl(DBGMCU_IDC); - } - - if (CONFIG_IS_ENABLED(STM32MP15x)) - return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ - else - return 0x0; -} - -u32 get_cpu_dev(void) -{ - return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; -} - -u32 get_cpu_rev(void) -{ - return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; -} - -static u32 get_otp(int index, int shift, int mask) -{ - int ret; - struct udevice *dev; - u32 otp = 0; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(stm32mp_bsec), - &dev); - - if (!ret) - ret = misc_read(dev, STM32_BSEC_SHADOW(index), - &otp, sizeof(otp)); - - return (otp >> shift) & mask; -} - -/* Get Device Part Number (RPN) from OTP */ -static u32 get_cpu_rpn(void) -{ - return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); -} - -u32 get_cpu_type(void) -{ - return (get_cpu_dev() << 16) | get_cpu_rpn(); -} - -/* Get Package options from OTP */ -u32 get_cpu_package(void) -{ - return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); -} - -static const char * const soc_type[] = { - "????", - "151C", "151A", "151F", "151D", - "153C", "153A", "153F", "153D", - "157C", "157A", "157F", "157D" -}; - -static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; -static const char * const soc_rev[] = { "?", "A", "B", "Z" }; - -static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, - unsigned int *rev) -{ - u32 cpu_type = get_cpu_type(); - u32 ct = cpu_type & ~(BIT(7) | BIT(0)); - u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); - u32 cp = get_cpu_package(); - - /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ - switch (ct) { - case CPU_STM32MP151Cxx: - *type = cm + 1; - break; - case CPU_STM32MP153Cxx: - *type = cm + 5; - break; - case CPU_STM32MP157Cxx: - *type = cm + 9; - break; - default: - *type = 0; - break; - } - - /* Package */ - switch (cp) { - case PKG_AA_LBGA448: - case PKG_AB_LBGA354: - case PKG_AC_TFBGA361: - case PKG_AD_TFBGA257: - *pkg = cp; - break; - default: - *pkg = 0; - break; - } - - /* Revision */ - switch (get_cpu_rev()) { - case CPU_REV1: - *rev = 1; - break; - case CPU_REV2: - *rev = 2; - break; - case CPU_REV2_1: - *rev = 3; - break; - default: - *rev = 0; - break; - } -} - -void get_soc_name(char name[SOC_NAME_SIZE]) -{ - unsigned int type, pkg, rev; - - get_cpu_string_offsets(&type, &pkg, &rev); - - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); -} - /* used when CONFIG_DISPLAY_CPUINFO is activated */ int print_cpuinfo(void) { @@ -598,16 +290,18 @@ __weak int setup_mac_address(void) { int ret; int i; - u32 otp[2]; + u32 otp[3]; uchar enetaddr[6]; struct udevice *dev; + int nb_eth, nb_otp, index; if (!IS_ENABLED(CONFIG_NET)) return 0; - /* MAC already in environment */ - if (eth_env_get_enetaddr("ethaddr", enetaddr)) - return 0; + nb_eth = get_eth_nb(); + + /* 6 bytes for each MAC addr and 4 bytes for each OTP */ + nb_otp = DIV_ROUND_UP(6 * nb_eth, 4); ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), @@ -615,22 +309,31 @@ __weak int setup_mac_address(void) if (ret) return ret; - ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), - otp, sizeof(otp)); + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp); if (ret < 0) return ret; - for (i = 0; i < 6; i++) - enetaddr[i] = ((uint8_t *)&otp)[i]; + for (index = 0; index < nb_eth; index++) { + /* MAC already in environment */ + if (eth_env_get_enetaddr_by_index("eth", index, enetaddr)) + continue; + + for (i = 0; i < 6; i++) + enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index]; - if (!is_valid_ethaddr(enetaddr)) { - log_err("invalid MAC address in OTP %pM\n", enetaddr); - return -EINVAL; + if (!is_valid_ethaddr(enetaddr)) { + log_err("invalid MAC address %d in OTP %pM\n", + index, enetaddr); + return -EINVAL; + } + log_debug("OTP MAC address %d = %pM\n", index, enetaddr); + ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr); + if (ret) { + log_err("Failed to set mac address %pM from OTP: %d\n", + enetaddr, ret); + return ret; + } } - log_debug("OTP MAC address = %pM\n", enetaddr); - ret = eth_env_set_enetaddr("ethaddr", enetaddr); - if (ret) - log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); return 0; } @@ -662,15 +365,8 @@ static int setup_serial_number(void) return 0; } -static void setup_soc_type_pkg_rev(void) +__weak void stm32mp_misc_init(void) { - unsigned int type, pkg, rev; - - get_cpu_string_offsets(&type, &pkg, &rev); - - env_set("soc_type", soc_type[type]); - env_set("soc_pkg", soc_pkg[pkg]); - env_set("soc_rev", soc_rev[rev]); } int arch_misc_init(void) @@ -678,7 +374,7 @@ int arch_misc_init(void) setup_boot_mode(); setup_mac_address(); setup_serial_number(); - setup_soc_type_pkg_rev(); + stm32mp_misc_init(); return 0; } diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index b1a4b76566395f240cc25cb25af6c70e0d942e07..3b4c05d745162dbc36bac2fd8cc029c5d865b38c 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,13 +28,120 @@ #define ETZPC_RESERVED 0xffffffff -#define STM32_FDCAN_BASE 0x4400e000 -#define STM32_CRYP2_BASE 0x4c005000 -#define STM32_CRYP1_BASE 0x54001000 -#define STM32_GPU_BASE 0x59000000 -#define STM32_DSI_BASE 0x5a000000 +#define STM32MP13_FDCAN_BASE 0x4400F000 +#define STM32MP13_ADC1_BASE 0x48003000 +#define STM32MP13_TSC_BASE 0x5000B000 +#define STM32MP13_CRYP_BASE 0x54002000 +#define STM32MP13_ETH2_BASE 0x5800E000 +#define STM32MP13_DCMIPP_BASE 0x5A000000 +#define STM32MP13_LTDC_BASE 0x5A010000 + +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000 + +static const u32 stm32mp13_ip_addr[] = { + 0x50025000, /* 0 VREFBUF APB3 */ + 0x50021000, /* 1 LPTIM2 APB3 */ + 0x50022000, /* 2 LPTIM3 APB3 */ + STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ + STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ + 0x5A006000, /* 5 USBPHYCTRL APB4 */ + 0x5A003000, /* 6 DDRCTRLPHY APB4 */ + ETZPC_RESERVED, /* 7 Reserved*/ + ETZPC_RESERVED, /* 8 Reserved*/ + ETZPC_RESERVED, /* 9 Reserved*/ + 0x5C006000, /* 10 TZC APB5 */ + 0x58001000, /* 11 MCE APB5 */ + 0x5C000000, /* 12 IWDG1 APB5 */ + 0x5C008000, /* 13 STGENC APB5 */ + ETZPC_RESERVED, /* 14 Reserved*/ + ETZPC_RESERVED, /* 15 Reserved*/ + 0x4C000000, /* 16 USART1 APB6 */ + 0x4C001000, /* 17 USART2 APB6 */ + 0x4C002000, /* 18 SPI4 APB6 */ + 0x4C003000, /* 19 SPI5 APB6 */ + 0x4C004000, /* 20 I2C3 APB6 */ + 0x4C005000, /* 21 I2C4 APB6 */ + 0x4C006000, /* 22 I2C5 APB6 */ + 0x4C007000, /* 23 TIM12 APB6 */ + 0x4C008000, /* 24 TIM13 APB6 */ + 0x4C009000, /* 25 TIM14 APB6 */ + 0x4C00A000, /* 26 TIM15 APB6 */ + 0x4C00B000, /* 27 TIM16 APB6 */ + 0x4C00C000, /* 28 TIM17 APB6 */ + ETZPC_RESERVED, /* 29 Reserved*/ + ETZPC_RESERVED, /* 30 Reserved*/ + ETZPC_RESERVED, /* 31 Reserved*/ + STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ + 0x48004000, /* 33 ADC2 AHB2 */ + 0x49000000, /* 34 OTG AHB2 */ + ETZPC_RESERVED, /* 35 Reserved*/ + ETZPC_RESERVED, /* 36 Reserved*/ + STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ + ETZPC_RESERVED, /* 38 Reserved*/ + ETZPC_RESERVED, /* 39 Reserved*/ + 0x54004000, /* 40 RNG AHB5 */ + 0x54003000, /* 41 HASH AHB5 */ + STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ + 0x54005000, /* 43 SAES AHB5 */ + 0x54006000, /* 44 PKA AHB5 */ + 0x54000000, /* 45 BKPSRAM AHB5 */ + ETZPC_RESERVED, /* 46 Reserved*/ + ETZPC_RESERVED, /* 47 Reserved*/ + 0x5800A000, /* 48 ETH1 AHB6 */ + STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ + 0x58005000, /* 50 SDMMC1 AHB6 */ + 0x58007000, /* 51 SDMMC2 AHB6 */ + ETZPC_RESERVED, /* 52 Reserved*/ + ETZPC_RESERVED, /* 53 Reserved*/ + 0x58002000, /* 54 FMC AHB6 */ + 0x58003000, /* 55 QSPI AHB6 */ + ETZPC_RESERVED, /* 56 Reserved*/ + ETZPC_RESERVED, /* 57 Reserved*/ + ETZPC_RESERVED, /* 58 Reserved*/ + ETZPC_RESERVED, /* 59 Reserved*/ + 0x30000000, /* 60 SRAM1 MLAHB */ + 0x30004000, /* 61 SRAM2 MLAHB */ + 0x30006000, /* 62 SRAM3 MLAHB */ + ETZPC_RESERVED, /* 63 Reserved*/ + ETZPC_RESERVED, /* 64 Reserved*/ + ETZPC_RESERVED, /* 65 Reserved*/ + ETZPC_RESERVED, /* 66 Reserved*/ + ETZPC_RESERVED, /* 67 Reserved*/ + ETZPC_RESERVED, /* 68 Reserved*/ + ETZPC_RESERVED, /* 69 Reserved*/ + ETZPC_RESERVED, /* 70 Reserved*/ + ETZPC_RESERVED, /* 71 Reserved*/ + ETZPC_RESERVED, /* 72 Reserved*/ + ETZPC_RESERVED, /* 73 Reserved*/ + ETZPC_RESERVED, /* 74 Reserved*/ + ETZPC_RESERVED, /* 75 Reserved*/ + ETZPC_RESERVED, /* 76 Reserved*/ + ETZPC_RESERVED, /* 77 Reserved*/ + ETZPC_RESERVED, /* 78 Reserved*/ + ETZPC_RESERVED, /* 79 Reserved*/ + ETZPC_RESERVED, /* 80 Reserved*/ + ETZPC_RESERVED, /* 81 Reserved*/ + ETZPC_RESERVED, /* 82 Reserved*/ + ETZPC_RESERVED, /* 83 Reserved*/ + ETZPC_RESERVED, /* 84 Reserved*/ + ETZPC_RESERVED, /* 85 Reserved*/ + ETZPC_RESERVED, /* 86 Reserved*/ + ETZPC_RESERVED, /* 87 Reserved*/ + ETZPC_RESERVED, /* 88 Reserved*/ + ETZPC_RESERVED, /* 89 Reserved*/ + ETZPC_RESERVED, /* 90 Reserved*/ + ETZPC_RESERVED, /* 91 Reserved*/ + ETZPC_RESERVED, /* 92 Reserved*/ + ETZPC_RESERVED, /* 93 Reserved*/ + ETZPC_RESERVED, /* 94 Reserved*/ + ETZPC_RESERVED, /* 95 Reserved*/ +}; -static const u32 stm32mp1_ip_addr[] = { +static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ 0x5c003000, /* 02 iwdg1 */ @@ -44,7 +151,7 @@ static const u32 stm32mp1_ip_addr[] = { ETZPC_RESERVED, /* 06 reserved */ 0x54003000, /* 07 rng1 */ 0x54002000, /* 08 hash1 */ - STM32_CRYP1_BASE, /* 09 cryp1 */ + STM32MP15_CRYP1_BASE, /* 09 cryp1 */ 0x5a003000, /* 0A ddrctrl */ 0x5a004000, /* 0B ddrphyc */ 0x5c009000, /* 0C i2c6 */ @@ -97,7 +204,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x4400b000, /* 3B sai2 */ 0x4400c000, /* 3C sai3 */ 0x4400d000, /* 3D dfsdm */ - STM32_FDCAN_BASE, /* 3E tt_fdcan */ + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ ETZPC_RESERVED, /* 3F reserved */ 0x50021000, /* 40 lptim2 */ 0x50022000, /* 41 lptim3 */ @@ -110,7 +217,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x48003000, /* 48 adc */ 0x4c002000, /* 49 hash2 */ 0x4c003000, /* 4A rng2 */ - STM32_CRYP2_BASE, /* 4B cryp2 */ + STM32MP15_CRYP2_BASE, /* 4B cryp2 */ ETZPC_RESERVED, /* 4C reserved */ ETZPC_RESERVED, /* 4D reserved */ ETZPC_RESERVED, /* 4E reserved */ @@ -163,8 +270,15 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB]; - array = stm32mp1_ip_addr; - array_size = ARRAY_SIZE(stm32mp1_ip_addr); + if (IS_ENABLED(CONFIG_STM32MP13x)) { + array = stm32mp13_ip_addr; + array_size = ARRAY_SIZE(stm32mp13_ip_addr); + } + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + array = stm32mp15_ip_addr; + array_size = ARRAY_SIZE(stm32mp15_ip_addr); + } for (i = 0; i < ETZPC_DECPROT_NB; i++) decprot[i] = readl(ETZPC_DECPROT(i)); @@ -248,33 +362,46 @@ static void stm32_fdt_disable_optee(void *blob) } } -/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, struct bd_info *bd) +static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) { - int ret = 0; - int soc; - u32 pkg, cpu; - char name[SOC_NAME_SIZE]; - - soc = fdt_path_offset(blob, "/soc"); - /* when absent, nothing to do */ - if (soc == -FDT_ERR_NOTFOUND) - return 0; - if (soc < 0) - return soc; + switch (cpu) { + case CPU_STM32MP131Fxx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Cxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name); + stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name); + fallthrough; + case CPU_STM32MP133Fxx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Cxx: + case CPU_STM32MP133Axx: + stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name); + stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp", + name); + stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name); + break; + default: + break; + } - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { - ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; + switch (cpu) { + case CPU_STM32MP135Dxx: + case CPU_STM32MP135Axx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Axx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name); + break; + default: + break; } +} - /* MPUs Part Numbers and name*/ - cpu = get_cpu_type(); - get_soc_name(name); +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + u32 pkg; switch (cpu) { case CPU_STM32MP151Fxx: @@ -284,19 +411,18 @@ int ft_system_setup(void *blob, struct bd_info *bd) stm32_fdt_fixup_cpu(blob, name); /* after cpu delete we can't trust the soc offsets anymore */ soc = fdt_path_offset(blob, "/soc"); - stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name); - /* fall through */ + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); + fallthrough; case CPU_STM32MP153Fxx: case CPU_STM32MP153Dxx: case CPU_STM32MP153Cxx: case CPU_STM32MP153Axx: - stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name); - stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name); + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); break; default: break; } - switch (cpu) { case CPU_STM32MP157Dxx: case CPU_STM32MP157Axx: @@ -304,24 +430,25 @@ int ft_system_setup(void *blob, struct bd_info *bd) case CPU_STM32MP153Axx: case CPU_STM32MP151Dxx: case CPU_STM32MP151Axx: - stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name); - stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", + name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", + name); break; default: break; } - switch (get_cpu_package()) { - case PKG_AA_LBGA448: + case STM32MP15_PKG_AA_LBGA448: pkg = STM32MP_PKG_AA; break; - case PKG_AB_LBGA354: + case STM32MP15_PKG_AB_LBGA354: pkg = STM32MP_PKG_AB; break; - case PKG_AC_TFBGA361: + case STM32MP15_PKG_AC_TFBGA361: pkg = STM32MP_PKG_AC; break; - case PKG_AD_TFBGA257: + case STM32MP15_PKG_AD_TFBGA257: pkg = STM32MP_PKG_AD; break; default: @@ -334,18 +461,54 @@ int ft_system_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", "st,package", pkg, false); } +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret = 0; + int soc; + u32 cpu; + char name[SOC_NAME_SIZE]; + + soc = fdt_path_offset(blob, "/soc"); + /* when absent, nothing to do */ + if (soc == -FDT_ERR_NOTFOUND) + return 0; + if (soc < 0) + return soc; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob, soc); + if (ret) + return ret; + } + + /* MPUs Part Numbers and name*/ + cpu = get_cpu_type(); + get_soc_name(name); - /* - * TEMP: remove OP-TEE nodes in kernel device tree - * copied from U-Boot device tree by optee_copy_fdt_nodes - * when OP-TEE is not detected (probe failed) - * these OP-TEE nodes are present in -u-boot.dtsi - * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility - * when FIP is not used by TF-A - */ - if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && - !tee_find_device(NULL, NULL, NULL, NULL)) - stm32_fdt_disable_optee(blob); + if (IS_ENABLED(CONFIG_STM32MP13x)) + stm32mp13_fdt_fixup(blob, soc, cpu, name); + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + stm32mp15_fdt_fixup(blob, soc, cpu, name); + + /* + * TEMP: remove OP-TEE nodes in kernel device tree + * copied from U-Boot device tree by optee_copy_fdt_nodes + * when OP-TEE is not detected (probe failed) + * these OP-TEE nodes are present in -u-boot.dtsi + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility + * when FIP is not used by TF-A + */ + if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + } return ret; } diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 47e88fc3dcd5be0bd0fb034d1b98cac0b1bb9008..c70375a723cbcd3728029b752e17893e2af6e6ac 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -17,7 +17,9 @@ #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 +#ifdef CONFIG_STM32MP15x #define STM32_DBGMCU_BASE 0x50081000 +#endif #define STM32_FMC2_BASE 0x58002000 #define STM32_DDRCTRL_BASE 0x5A003000 #define STM32_DDRPHYC_BASE 0x5A004000 @@ -26,8 +28,14 @@ #define STM32_STGEN_BASE 0x5C008000 #define STM32_TAMP_BASE 0x5C00A000 +#ifdef CONFIG_STM32MP15x #define STM32_USART1_BASE 0x5C000000 #define STM32_USART2_BASE 0x4000E000 +#endif +#ifdef CONFIG_STM32MP13x +#define STM32_USART1_BASE 0x4c000000 +#define STM32_USART2_BASE 0x4c001000 +#endif #define STM32_USART3_BASE 0x4000F000 #define STM32_UART4_BASE 0x40010000 #define STM32_UART5_BASE 0x40011000 @@ -39,8 +47,10 @@ #define STM32_SDMMC2_BASE 0x58007000 #define STM32_SDMMC3_BASE 0x48004000 +#ifdef CONFIG_STM32MP15x #define STM32_SYSRAM_BASE 0x2FFC0000 #define STM32_SYSRAM_SIZE SZ_256K +#endif #define STM32_DDR_BASE 0xC0000000 #define STM32_DDR_SIZE SZ_1G @@ -98,6 +108,8 @@ enum boot_device { /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) + +#ifdef CONFIG_STM32MP15x #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) @@ -111,13 +123,18 @@ enum boot_device { #define TAMP_COPRO_STATE_CSTOP 3 #define TAMP_COPRO_STATE_STANDBY 4 #define TAMP_COPRO_STATE_CRASH 5 +#endif + +#ifdef CONFIG_STM32MP13x +#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) +#endif #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) -#define TAMP_BOOT_DEBUG_ON BIT(16) enum forced_boot_mode { BOOT_NORMAL = 0x00, @@ -138,11 +155,19 @@ enum forced_boot_mode { #define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) /* BSEC OTP index */ +#ifdef CONFIG_STM32MP15x #define BSEC_OTP_RPN 1 #define BSEC_OTP_SERIAL 13 #define BSEC_OTP_PKG 16 #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 59 +#endif +#ifdef CONFIG_STM32MP13x +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_SERIAL 13 +#define BSEC_OTP_MAC 57 +#define BSEC_OTP_BOARD 60 +#endif #endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index b91f98eb4515a1486f35781e227de86a6581b45e..4b564e86dc52c12541481a68fcbd5c0362df85f8 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -3,7 +3,7 @@ * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved */ -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */ +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */ #define CPU_STM32MP157Cxx 0x05000000 #define CPU_STM32MP157Axx 0x05000001 #define CPU_STM32MP153Cxx 0x05000024 @@ -17,10 +17,24 @@ #define CPU_STM32MP151Fxx 0x050000AE #define CPU_STM32MP151Dxx 0x050000AF +#define CPU_STM32MP135Cxx 0x05010000 +#define CPU_STM32MP135Axx 0x05010001 +#define CPU_STM32MP133Cxx 0x050100C0 +#define CPU_STM32MP133Axx 0x050100C1 +#define CPU_STM32MP131Cxx 0x050106C8 +#define CPU_STM32MP131Axx 0x050106C9 +#define CPU_STM32MP135Fxx 0x05010800 +#define CPU_STM32MP135Dxx 0x05010801 +#define CPU_STM32MP133Fxx 0x050108C0 +#define CPU_STM32MP133Dxx 0x050108C1 +#define CPU_STM32MP131Fxx 0x05010EC8 +#define CPU_STM32MP131Dxx 0x05010EC9 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 +#define CPU_DEV_STM32MP13 0x501 /* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -36,10 +50,12 @@ u32 get_cpu_rev(void); /* Get Package options from OTP */ u32 get_cpu_package(void); -#define PKG_AA_LBGA448 4 -#define PKG_AB_LBGA354 3 -#define PKG_AC_TFBGA361 2 -#define PKG_AD_TFBGA257 1 +/* package used for STM32MP15x */ +#define STM32MP15_PKG_AA_LBGA448 4 +#define STM32MP15_PKG_AB_LBGA354 3 +#define STM32MP15_PKG_AC_TFBGA361 2 +#define STM32MP15_PKG_AD_TFBGA257 1 +#define STM32MP15_PKG_UNKNOWN 0 /* Get SOC name */ #define SOC_NAME_SIZE 20 @@ -48,7 +64,15 @@ void get_soc_name(char name[SOC_NAME_SIZE]); /* return boot mode */ u32 get_bootmode(void); +int get_eth_nb(void); int setup_mac_address(void); /* board power management : configure vddcore according OPP */ void board_vddcore_init(u32 voltage_mv); + +/* weak function */ +void stm32mp_cpu_init(void); +void stm32mp_misc_init(void); + +/* helper function: read data from OTP */ +u32 get_otp(int index, int shift, int mask); diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 78fa9d7edd29def94471a65ba1bbe401b95734b4..19d9fe04e088d604e58961efae42e08e3a1a9084 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -190,6 +190,7 @@ void board_init_f(ulong dummy) int ret; arch_cpu_init(); + mach_cpu_init(); ret = spl_early_init(); if (ret) { diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp13x.c new file mode 100644 index 0000000000000000000000000000000000000000..bd3f24c349ad53540532e3afcf92147a6c86b43b --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp13x.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include + +/* SYSCFG register */ +#define SYSCFG_IDC_OFFSET 0x380 +#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_IDC_DEV_ID_SHIFT 0 +#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_IDC_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(11, 0) + +static u32 read_idc(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_IDC_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + int nb_eth = 2; + + switch (get_cpu_type()) { + case CPU_STM32MP131Dxx: + fallthrough; + case CPU_STM32MP131Cxx: + fallthrough; + case CPU_STM32MP131Axx: + nb_eth = 1; + break; + default: + nb_eth = 2; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r; + + /* MPUs Part Numbers */ + switch (get_cpu_type()) { + case CPU_STM32MP135Fxx: + cpu_s = "135F"; + break; + case CPU_STM32MP135Dxx: + cpu_s = "135D"; + break; + case CPU_STM32MP135Cxx: + cpu_s = "135C"; + break; + case CPU_STM32MP135Axx: + cpu_s = "135A"; + break; + case CPU_STM32MP133Fxx: + cpu_s = "133F"; + break; + case CPU_STM32MP133Dxx: + cpu_s = "133D"; + break; + case CPU_STM32MP133Cxx: + cpu_s = "133C"; + break; + case CPU_STM32MP133Axx: + cpu_s = "133A"; + break; + case CPU_STM32MP131Fxx: + cpu_s = "131F"; + break; + case CPU_STM32MP131Dxx: + cpu_s = "131D"; + break; + case CPU_STM32MP131Cxx: + cpu_s = "131C"; + break; + case CPU_STM32MP131Axx: + cpu_s = "131A"; + break; + default: + cpu_s = "????"; + break; + } + + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + case CPU_REV1_1: + cpu_r = "Z"; + break; + default: + cpu_r = "?"; + break; + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c new file mode 100644 index 0000000000000000000000000000000000000000..a093e6163e605cd243972a4a0c54a425d94ba9d1 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp15x.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) +#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_MCUCR (STM32_PWR_BASE + 0x14) +#define PWR_CR1_DBP BIT(8) +#define PWR_MCUCR_SBF BIT(6) + +/* GPIOZ registers */ +#define GPIOZ_SECCFGR 0x54004030 + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_PARAM_ADDR 0x2FFC0078 +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines + * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm + * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm + * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm + * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 27 +#define PKG_MASK GENMASK(2, 0) + +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(GENMASK(25, 0), ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable TZC1 TZC2 clock */ + writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); + /* bit 30 / 31 => Secure Global Enable : write/read */ + /* bit 0 / 1 => Region Enable for filter 0/1 */ + writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); + + /* Enable Filter 0 and 1 */ + setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); + + /* GPIOZ: deactivate the security */ + writel(BIT(0), RCC_MP_AHB5ENSETR); + writel(0x0, GPIOZ_SECCFGR); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + security_init(); + update_bootmode(); + } + + /* reset copro state in SPL, when used, or in U-Boot */ + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } + } +} + +static u32 read_idc(void) +{ + /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return readl(DBGMCU_IDC); + } + + return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + return 1; +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +static const char * const soc_type[] = { + "????", + "151C", "151A", "151F", "151D", + "153C", "153A", "153F", "153D", + "157C", "157A", "157F", "157D" +}; + +static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z" }; + +static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, + unsigned int *rev) +{ + u32 cpu_type = get_cpu_type(); + u32 ct = cpu_type & ~(BIT(7) | BIT(0)); + u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); + u32 cp = get_cpu_package(); + + /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ + switch (ct) { + case CPU_STM32MP151Cxx: + *type = cm + 1; + break; + case CPU_STM32MP153Cxx: + *type = cm + 5; + break; + case CPU_STM32MP157Cxx: + *type = cm + 9; + break; + default: + *type = 0; + break; + } + + /* Package */ + switch (cp) { + case STM32MP15_PKG_AA_LBGA448: + case STM32MP15_PKG_AB_LBGA354: + case STM32MP15_PKG_AC_TFBGA361: + case STM32MP15_PKG_AD_TFBGA257: + *pkg = cp; + break; + default: + *pkg = 0; + break; + } + + /* Revision */ + switch (get_cpu_rev()) { + case CPU_REV1: + *rev = 1; + break; + case CPU_REV2: + *rev = 2; + break; + case CPU_REV2_1: + *rev = 3; + break; + default: + *rev = 0; + break; + } +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); +} + +static void setup_soc_type_pkg_rev(void) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + env_set("soc_type", soc_type[type]); + env_set("soc_pkg", soc_pkg[pkg]); + env_set("soc_rev", soc_rev[rev]); +} + +/* weak function called in arch_misc_init */ +void stm32mp_misc_init(void) +{ + setup_soc_type_pkg_rev(); +} diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e712a895340874ceae25fe87b88f46ac0f6d1614..71a7f8dcee06799eba9ef6da82315a70a8dbbe6c 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,9 +1,5 @@ if ARCH_SUNXI -config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 - config IDENT_STRING default " Allwinner Technology" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 5309be9cc2102a634e2072c5c961073344902d48..09ad2d6f5aec290132bc869e6827ee61705e5b97 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -178,6 +178,10 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config TEGRA_GPU + bool "Enable setting up the GPU" + depends on TEGRA124 || TEGRA210 + config CMD_ENTERRCM bool "Enable 'enterrcm' command" default y diff --git a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S index 36db50fd97b565bb1a3684b87be4bff161a8c8c4..6c722d02eda13dbaa557b40c5416c34c514072c9 100644 --- a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S @@ -6,8 +6,9 @@ #include #include +#include ENTRY(lowlevel_init) - ldr sp, = CONFIG_SYS_INIT_SP_ADDR + ldr sp, = SYS_INIT_SP_ADDR b uniphier_cache_disable ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index d116d46812d56630e29d2a81991dfee8d04dfa42..1ba012ca45d6b76398689c49e360f830e27dec93 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -18,7 +18,7 @@ static void _debug_uart_putc(int c) { - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE)) ; @@ -57,7 +57,7 @@ void sg_set_iectrl(unsigned int pin) void _debug_uart_init(void) { #ifdef CONFIG_SPL_BUILD - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); unsigned int divisor; switch (uniphier_get_soc_id()) { diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 7b728ac1101813f4da1dcfe012ab17faa4378152..000af974e867ff3e736bedecfd3e69ce54e10778 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -58,6 +58,10 @@ struct rpu_regs { #define VERSAL_CRP_BASEADDR 0xF1260000 +#define VERSAL_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) + struct crp_regs { u32 reserved0[128]; u32 boot_mode_usr; @@ -82,3 +86,14 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index cf2e727916ba3752155972c32230d01ab4e0a84a..b4c439b4cd6d673ab7489ceebdfecc9cb974bc75 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,8 +1,5 @@ if ARCH_ZYNQ -config SPL_LDSCRIPT - default "arch/arm/mach-zynq/u-boot-spl.lds" - config SPL_FS_FAT default y diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds index 106d2e390ba8b096898e4ac95a29cea454c12ca2..8c18d3f91f4bf84ac2e71e7a9257576cefa9fe2f 100644 --- a/arch/arm/mach-zynq/u-boot-spl.lds +++ b/arch/arm/mach-zynq/u-boot-spl.lds @@ -37,8 +37,8 @@ SECTIONS } > .sram . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .sram . = ALIGN(4); diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index 91c32e89e8fe1d9cbaaa4663cdd4000efd0fd590..a5169fd9150ed9c522d6671a679cae82d3dcf5f2 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -54,8 +54,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 31346d9b2e217ac3a7a1595e076ae5efb6a77d49..b9e0c6c536bef98724e3848bfccb6846ec372cd5 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -79,7 +79,10 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, atfhandoffparams->magic[2] = 'N'; atfhandoffparams->magic[3] = 'X'; + debug("Creating handoff:\n"); + if (bl32_entry) { + debug(" to BL32 at 0x%x EL-1, Secure\n", (u32)bl32_entry); atfhandoffparams->partition[index].entry_point = bl32_entry; atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL1 << FSBL_FLAGS_EL_SHIFT | FSBL_FLAGS_SECURE << FSBL_FLAGS_TZ_SHIFT; @@ -87,6 +90,7 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, } if (bl33_entry) { + debug(" to BL33 at 0x%x EL-2\n", (u32)bl33_entry); atfhandoffparams->partition[index].entry_point = bl33_entry; atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL2 << FSBL_FLAGS_EL_SHIFT; diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 7f6e4310f1f4beee3b91476cab2d80b71b939e8d..76233ef563fb28b170d03186dd707445121b3d90 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -4,6 +4,9 @@ menu "M68000 architecture" config SYS_ARCH default "m68k" +config NEEDS_MANUAL_RELOC + def_bool y + # processor family config MCF520x select OF_CONTROL @@ -53,12 +56,6 @@ config MCF5441x select DM_SERIAL bool -config MCF5227x - select OF_CONTROL - select DM - select DM_SERIAL - bool - # processor type config M5208 bool diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile deleted file mode 100644 index 6a38c4838e99de10c24041036d183f2e15fd6e19..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -# ccflags-y += -DET_DEBUG - -extra-y = start.o -obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c deleted file mode 100644 index a7adf64f0de0a86943db90125089443455035cfa..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/cpu.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - rcm_t *rcm = (rcm_t *) (MMAP_RCM); - udelay(1000); - setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); - - /* we don't return! */ - return 0; -}; - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - ccm_t *ccm = (ccm_t *) MMAP_CCM; - u16 msk; - u16 id = 0; - u8 ver; - - puts("CPU: "); - msk = (in_be16(&ccm->cir) >> 6); - ver = (in_be16(&ccm->cir) & 0x003f); - switch (msk) { - case 0x6c: - id = 52277; - break; - } - - if (id) { - char buf1[32], buf2[32], buf3[32]; - - printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, - ver); - printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n", - strmhz(buf1, gd->cpu_clk), - strmhz(buf2, gd->bus_clk), - strmhz(buf3, gd->arch.flb_clk)); - printf(" INP CLK %s MHz VCO CLK %s MHz\n", - strmhz(buf1, gd->arch.inp_clk), - strmhz(buf2, gd->arch.vco_clk)); - } - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c deleted file mode 100644 index 4ab13b4d8eabcbaca3f6edbdf7f385cf0b79c617..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/cpu_init.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - -void cfspi_port_conf(void) -{ - gpio_t *gpio = (gpio_t *)MMAP_GPIO; - - out_8(&gpio->par_dspi, - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK); -} - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; - -#if !defined(CONFIG_CF_SBF) - scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - pll_t *pll = (pll_t *)MMAP_PLL; - - /* Workaround, must place before fbcs */ - out_be32(&pll->psr, 0x12); - - out_be32(&scm1->mpr, 0x77777777); - out_be32(&scm1->pacra, 0); - out_be32(&scm1->pacrb, 0); - out_be32(&scm1->pacrc, 0); - out_be32(&scm1->pacrd, 0); - out_be32(&scm1->pacre, 0); - out_be32(&scm1->pacrf, 0); - out_be32(&scm1->pacrg, 0); - out_be32(&scm1->pacri, 0); - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); -#endif -#endif /* CONFIG_CF_SBF */ - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ - && defined(CONFIG_SYS_CS4_CTRL)) - out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); - out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); - out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ - && defined(CONFIG_SYS_CS5_CTRL)) - out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); - out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); - out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); -#endif - -#ifdef CONFIG_SYS_I2C_FSL - out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA); -#endif - - icache_enable(); - - cfspi_port_conf(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ -#ifdef CONFIG_MCFRTC - rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - rtcex_t *rtcex = (rtcex_t *)&rtc->extended; - - out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); - out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); -#endif - - return (0); -} - -void uart_port_conf(int port) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (port) { - case 0: - clrbits_be16(&gpio->par_uart, - ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK)); - setbits_be16(&gpio->par_uart, - GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - break; - case 1: - clrbits_be16(&gpio->par_uart, - ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK)); - setbits_be16(&gpio->par_uart, - GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); - break; - case 2: - clrbits_8(&gpio->par_dspi, - ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK)); - out_8(&gpio->par_dspi, - GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); - break; - } -} diff --git a/arch/m68k/cpu/mcf5227x/dspi.c b/arch/m68k/cpu/mcf5227x/dspi.c deleted file mode 100644 index 8fc4da271e85c9a1eeab29195e1a790715c7fe46..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/dspi.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2019 - * Angelo Dureghello - * - * CPU specific dspi routines - */ - -#include -#include -#include - -#ifdef CONFIG_CF_DSPI -void dspi_chip_select(int cs) -{ - struct gpio *gpio = (struct gpio *)MMAP_GPIO; - - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 2: - clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); - setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); - break; - } -} - -void dspi_chip_unselect(int cs) -{ - struct gpio *gpio = (struct gpio *)MMAP_GPIO; - - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 2: - clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); - break; - } -} -#endif /* CONFIG_CF_DSPI */ diff --git a/arch/m68k/cpu/mcf5227x/interrupts.c b/arch/m68k/cpu/mcf5227x/interrupts.c deleted file mode 100644 index 5a6a88cd5713a916852c50ce72033fd3e89ff6c5..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/interrupts.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* CPU specific interrupt routine */ -#include -#include -#include -#include - -int interrupt_init(void) -{ - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - - /* Make sure all interrupts are disabled */ - setbits_be32(&intp->imrh0, 0xffffffff); - setbits_be32(&intp->imrl0, 0xffffffff); - - enable_interrupts(); - return 0; -} - -#if defined(CONFIG_MCFTMR) -void dtimer_intr_setup(void) -{ - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); - clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); -} -#endif diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c deleted file mode 100644 index fa9d5cb7887c3419be1839bb2ef14d6af081e8c3..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/speed.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Low Power Divider specifications - */ -#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ -#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ - -#define CLOCK_PLL_FVCO_MAX 540000000 -#define CLOCK_PLL_FVCO_MIN 300000000 - -#define CLOCK_PLL_FSYS_MAX 266666666 -#define CLOCK_PLL_FSYS_MIN 100000000 -#define MHZ 1000000 - -void clock_enter_limp(int lpdiv) -{ - ccm_t *ccm = (ccm_t *)MMAP_CCM; - int i, j; - - /* Check bounds of divider */ - if (lpdiv < CLOCK_LPD_MIN) - lpdiv = CLOCK_LPD_MIN; - if (lpdiv > CLOCK_LPD_MAX) - lpdiv = CLOCK_LPD_MAX; - - /* Round divider down to nearest power of two */ - for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; - - /* Apply the divider to the system clock */ - clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); - - /* Enable Limp Mode */ - setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); -} - -/* - * brief Exit Limp mode - * warning The PLL should be set and locked prior to exiting Limp mode - */ -void clock_exit_limp(void) -{ - ccm_t *ccm = (ccm_t *)MMAP_CCM; - pll_t *pll = (pll_t *)MMAP_PLL; - - /* Exit Limp mode */ - clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); - - /* Wait for the PLL to lock */ - while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) - ; -} - -/* - * get_clocks() fills in gd->cpu_clock and gd->bus_clk - */ -int get_clocks(void) -{ - - ccm_t *ccm = (ccm_t *)MMAP_CCM; - pll_t *pll = (pll_t *)MMAP_PLL; - int vco, temp, pcrvalue, pfdr; - u8 bootmode; - - pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; - pfdr = pcrvalue >> 24; - - if (pfdr == 0x1E) - bootmode = 0; /* Normal Mode */ - -#ifdef CONFIG_CF_SBF - bootmode = 3; /* Serial Mode */ -#endif - - if (bootmode == 0) { - /* Normal mode */ - vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; - if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { - /* Default value */ - pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); - pcrvalue |= 0x1E << 24; - out_be32(&pll->pcr, pcrvalue); - vco = - ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * - CONFIG_SYS_INPUT_CLKSRC; - } - gd->arch.vco_clk = vco; /* Vco clock */ - } else if (bootmode == 3) { - /* serial mode */ - vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; - gd->arch.vco_clk = vco; /* Vco clock */ - } - - if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { - /* Limp mode */ - } else { - gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ - - temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; - gd->cpu_clk = vco / temp; /* cpu clock */ - - temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; - gd->arch.flb_clk = vco / temp; /* flexbus clock */ - gd->bus_clk = gd->arch.flb_clk; - } - -#ifdef CONFIG_SYS_I2C_FSL - gd->arch.i2c1_clk = gd->bus_clk; -#endif - - return (0); -} diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S deleted file mode 100644 index 632f1b1f38cca466c25b0485e29e4254c68c452f..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5227x/start.S +++ /dev/null @@ -1,491 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - */ - -#include -#include -#include - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -#if defined(CONFIG_CF_SBF) -#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) -#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) -#endif - -.text - -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: -#if defined(CONFIG_CF_SBF) -INITSP: .long 0 /* Initial SP */ -INITPC: .long ASM_DRAMINIT /* Initial PC */ -#else -INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -#endif - -vector02_0F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18_1F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -#if !defined(CONFIG_CF_SBF) -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -#endif - -#if defined(CONFIG_CF_SBF) - /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ -asm_sbf_img_hdr: - .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00020000 /* image length */ - .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */ - -asm_dram_init: - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 /* init Rambar */ - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - /* Must disable global address */ - move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) - move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) - move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) - - /* - * Dram Initialization - * a1, a2, and d0 - */ - move.l #0xFC0A4074, %a1 - move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) - nop - - /* SDRAM Chip 0 and 1 */ - move.l #0xFC0B8110, %a1 - move.l #0xFC0B8114, %a2 - - /* calculate the size */ - move.l #0x13, %d1 - move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 -#ifdef CONFIG_SYS_SDRAM_BASE1 - lsr.l #1, %d2 -#endif - -dramsz_loop: - lsr.l #1, %d2 - add.l #1, %d1 - cmp.l #1, %d2 - bne dramsz_loop - - /* SDRAM Chip 0 and 1 */ - move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) - or.l %d1, (%a1) -#ifdef CONFIG_SYS_SDRAM_BASE1 - move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) - or.l %d1, (%a2) -#endif - nop - - /* dram cfg1 and cfg2 */ - move.l #0xFC0B8008, %a1 - move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) - nop - move.l #0xFC0B800C, %a2 - move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) - nop - - move.l #0xFC0B8000, %a1 /* Mode */ - move.l #0xFC0B8004, %a2 /* Ctrl */ - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) - nop - move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) - nop - - move.l #1000, %d0 -wait1000: - nop - subq.l #1, %d0 - bne wait1000 - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Perform two refresh cycles */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 - nop - move.l %d0, (%a2) - move.l %d0, (%a2) - nop - - move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 - and.l #0x7FFFFFFF, %d0 - or.l #0x10000c00, %d0 - move.l %d0, (%a2) - nop - - /* - * DSPI Initialization - * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h - * a1 - dspi status - * a2 - dtfr - * a3 - drfr - * a4 - Dst addr - */ - - /* Enable pins for DSPI mode - chip-selects are enabled later */ - move.l #0xFC0A4036, %a0 - move.b #0x3F, %d0 - move.b %d0, (%a0) - - /* DSPI CS */ -#ifdef CONFIG_SYS_DSPI_CS0 - move.b (%a0), %d0 - or.l #0xC0, %d0 - move.b %d0, (%a0) -#endif -#ifdef CONFIG_SYS_DSPI_CS2 - move.l #0xFC0A4037, %a0 - move.b (%a0), %d0 - or.l #0x10, %d0 - move.b %d0, (%a0) -#endif - nop - - /* Configure DSPI module */ - move.l #0xFC05C000, %a0 - move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ - - move.l #0xFC05C00C, %a0 - move.l #0x3E000011, (%a0) - - move.l #0xFC05C034, %a2 /* dtfr */ - move.l #0xFC05C03B, %a3 /* drfr */ - - move.l #(ASM_SBF_IMG_HDR + 4), %a1 - move.l (%a1)+, %d5 - move.l (%a1), %a4 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 - - move.l #0xFC05C02C, %a1 /* dspi status */ - - /* Issue commands and address */ - move.l #0x8004000B, %d2 /* Fast Read Cmd */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Address byte 2 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Address byte 1 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Address byte 0 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Dummy Wr and Rd */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - /* Transfer serial boot header to sram */ -asm_dspi_rd_loop1: - move.l #0x80040000, %d2 - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.b %d1, (%a0) /* read, copy to dst */ - - add.l #1, %a0 /* inc dst by 1 */ - sub.l #1, %d4 /* dec cnt by 1 */ - bne asm_dspi_rd_loop1 - - /* Transfer u-boot from serial flash to memory */ -asm_dspi_rd_loop2: - move.l #0x80040000, %d2 - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.b %d1, (%a4) /* read, copy to dst */ - - add.l #1, %a4 /* inc dst by 1 */ - sub.l #1, %d5 /* dec cnt by 1 */ - bne asm_dspi_rd_loop2 - - move.l #0x00040000, %d2 /* Terminate */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - /* jump to memory and execute */ - move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0 - move.l %a0, (%a1) - jmp (%a0) - -asm_dspi_wr_status: - move.l (%a1), %d0 /* status */ - and.l #0x0000F000, %d0 - cmp.l #0x00003000, %d0 - bgt asm_dspi_wr_status - - move.l %d2, (%a2) - rts - -asm_dspi_rd_status: - move.l (%a1), %d0 /* status */ - and.l #0x000000F0, %d0 - lsr.l #4, %d0 - cmp.l #0, %d0 - beq asm_dspi_rd_status - - move.b (%a3), %d1 - rts -#endif /* CONFIG_CF_SBF */ - -.text - . = 0x400 -.globl _start -_start: - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - - /* Set vector base register at the beginning of the Flash */ -#if defined(CONFIG_CF_SBF) - move.l #CONFIG_SYS_TEXT_BASE, %d0 - movec %d0, %VBR -#else - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 -#endif - - /* invalidate and disable cache */ - move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) - - /* put relocation table address to a5 */ - move.l #__got_start, %a5 - - /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp - - /* - * if configured, malloc_f arena will be reserved first, - * then (and always) gd struct space will be reserved - */ - move.l %sp, -(%sp) - bsr board_init_f_alloc_reserve - - /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp - - /* initialize reserved area */ - move.l %d0, -(%sp) - bsr board_init_f_init_reserve - - /* run low-level CPU init code (from flash) */ - bsr cpu_init_f - clr.l %sp@- - - /* run low-level board init code (from flash) */ - move.l #board_init_f, %a1 - jsr (%a1) - - /* board_init_f() does not return */ - -/******************************************************************************/ - -/* - * void relocate_code(addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ -.globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/******************************************************************************/ - -/* exception code */ -.globl _fault -_fault: - bra _fault - -.globl _exc_handler -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - -.globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/******************************************************************************/ - -.align 4 diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile index ba90fc3c34a30e58287abbeb015048a0f6ef0f10..6a38c4838e99de10c24041036d183f2e15fd6e19 100644 --- a/arch/m68k/cpu/mcf5445x/Makefile +++ b/arch/m68k/cpu/mcf5445x/Makefile @@ -6,4 +6,4 @@ # ccflags-y += -DET_DEBUG extra-y = start.o -obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c deleted file mode 100644 index d487468d0bfa64bb669a4ee3b32e22ed1a8a3fa1..0000000000000000000000000000000000000000 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * PCI Configuration space access support - */ -#include -#include -#include -#include -#include - -#if defined(CONFIG_PCI) -/* System RAM mapped over PCI */ -#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) - -#define cfg_read(val, addr, type, op) *val = op((type)(addr)); -#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); - -#define PCI_OP(rw, size, type, op, mask) \ -int pci_##rw##_cfg_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), \ - PCI_FUNC(dev), offset); \ - out_be32(hose->cfg_addr, addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE); \ - return 0; \ -} - -PCI_OP(read, byte, u8 *, in_8, 3) -PCI_OP(read, word, u16 *, in_le16, 2) -PCI_OP(read, dword, u32 *, in_le32, 0) -PCI_OP(write, byte, u8, out_8, 3) -PCI_OP(write, word, u16, out_le16, 2) -PCI_OP(write, dword, u32, out_le32, 0) - -void pci_mcf5445x_init(struct pci_controller *hose) -{ - pci_t *pci = (pci_t *)MMAP_PCI; - pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - u32 barEn = 0; - - out_be32(&pciarb->acr, 0x001f001f); - - /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, - PCIREQ2, PCIGNT2 */ - out_be16(&gpio->par_pci, - GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | - GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 | - GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | - GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0); - - /* Assert reset bit */ - setbits_be32(&pci->gscr, PCI_GSCR_PR); - - setbits_be32(&pci->tcr1, PCI_TCR1_P); - - /* Initiator windows */ - out_be32(&pci->iw0btar, - CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); - out_be32(&pci->iw1btar, - CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); - out_be32(&pci->iw2btar, - CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - - out_be32(&pci->iwcr, - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - - out_be32(&pci->icr, 0); - - /* Enable bus master and mem access */ - out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); - - /* Cache line size and master latency */ - out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8)); - out_be32(&pci->cr2, 0); - -#ifdef CONFIG_SYS_PCI_BAR0 - out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); - out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B0E; -#endif -#ifdef CONFIG_SYS_PCI_BAR1 - out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); - out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B1E; -#endif -#ifdef CONFIG_SYS_PCI_BAR2 - out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2)); - out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B2E; -#endif -#ifdef CONFIG_SYS_PCI_BAR3 - out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3)); - out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B3E; -#endif -#ifdef CONFIG_SYS_PCI_BAR4 - out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4)); - out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B4E; -#endif -#ifdef CONFIG_SYS_PCI_BAR5 - out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5)); - out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B5E; -#endif - - out_be32(&pci->tcr2, barEn); - - /* Deassert reset bit */ - clrbits_be32(&pci->gscr, PCI_GSCR_PR); - udelay(1000); - - /* Enable PCI bus master support */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, - CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 3; - - hose->cfg_addr = &(pci->car); - hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; - - pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, - pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, - pci_write_cfg_dword); - - /* Hose scan */ - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI */ diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds index affb2d93746492d2bf624f43f38e471c1961b2e1..133f79150baa1fb786981872ab4235983c261602 100644 --- a/arch/m68k/cpu/u-boot.lds +++ b/arch/m68k/cpu/u-boot.lds @@ -60,8 +60,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = .; diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index 221eb93d58bc6f67531e8d2c42baa24b410bee60..bad0026648a1477581daa322ba2baae035e24d22 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index d7d1b219704e0d971d68aec649b13cee0c5c4636..ce157a79ccc17c88dcff163b7ddb70ad7d8ae8db 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -4,6 +4,20 @@ menu "MicroBlaze architecture" config SYS_ARCH default "microblaze" +config NEEDS_MANUAL_RELOC + bool "Disable position-independent pre-relocation code" + default y + help + U-Boot expects to be linked to a specific hard-coded address, and to + be loaded to and run from that address. This option lifts that + restriction, thus allowing the code to be loaded to and executed from + almost any 4K aligned address. This logic relies on the relocation + information that is embedded in the binary to support U-Boot + relocating itself to the top-of-RAM later during execution. + +config STATIC_RELA + def_bool y if !NEEDS_MANUAL_RELOC + choice prompt "Target select" optional @@ -25,14 +39,6 @@ config TARGET_MICROBLAZE_GENERIC endchoice -config DCACHE - bool "Enable dcache support" - default y - -config ICACHE - bool "Enable icache support" - default y - source "board/xilinx/Kconfig" source "board/xilinx/microblaze-generic/Kconfig" diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index de5b97e719cc834d2df914b9ac212fef19357ff2..d35b4f6db7a1b33d91f90b6f5673f1205620a826 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -16,3 +16,14 @@ LDFLAGS_FINAL += --gc-sections ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC endif + +ifeq ($(CONFIG_STATIC_RELA),y) +PLATFORM_CPPFLAGS += -fPIC +LDFLAGS_u-boot += -pic +endif + +ifeq ($(CONFIG_SYS_LITTLE_ENDIAN),y) +PLATFORM_ELFFLAGS += -B microblaze $(OBJCOPYFLAGS) -O elf32-microblazeel +else +PLATFORM_ELFFLAGS += -B microblaze $(OBJCOPYFLAGS) -O elf32-microblaze +endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index f7a83d07b6f6f8b6ada5d94b843a6be33b7b7723..1c586a7de023ccaf1985f590f01571b9d72a0068 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,5 +5,7 @@ extra-y = start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o timer.o +obj-y += interrupts.o cache.o exception.o cpuinfo.o +obj-$(CONFIG_STATIC_RELA) += relocate.o +obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index aa832d6be6d40e000b43e1f45b069ec8bb8c8e88..829e6c7ae60577e48c457f96d5483727170a9e53 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -9,6 +9,61 @@ #include #include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void __invalidate_icache(ulong addr, ulong size) +{ + if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) { + for (int i = 0; i < size; + i += gd_cpuinfo()->icache_line_length) { + asm volatile ( + "wic %0, r0;" + "nop;" + : + : "r" (addr + i) + : "memory"); + } + } +} + +void invalidate_icache_all(void) +{ + __invalidate_icache(0, gd_cpuinfo()->icache_size); +} + +static void __flush_dcache(ulong addr, ulong size) +{ + if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { + for (int i = 0; i < size; + i += gd_cpuinfo()->dcache_line_length) { + asm volatile ( + "wdc.flush %0, r0;" + "nop;" + : + : "r" (addr + i) + : "memory"); + } + } +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + if (start >= end) { + debug("Invalid dcache range - start: 0x%08lx end: 0x%08lx\n", + start, end); + return; + } + + __flush_dcache(start, end - start); +} + +void flush_dcache_all(void) +{ + __flush_dcache(0, gd_cpuinfo()->dcache_size); +} int dcache_status(void) { @@ -37,8 +92,8 @@ void icache_enable(void) void icache_disable(void) { - /* we are not generate ICACHE size -> flush whole cache */ - flush_cache(0, 32768); + invalidate_icache_all(); + MSRCLR(0x20); } @@ -49,26 +104,19 @@ void dcache_enable(void) void dcache_disable(void) { -#ifdef XILINX_USE_DCACHE - flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#endif + flush_dcache_all(); + MSRCLR(0x80); } void flush_cache(ulong addr, ulong size) { - int i; - for (i = 0; i < size; i += 4) - asm volatile ( -#ifdef CONFIG_ICACHE - "wic %0, r0;" -#endif - "nop;" -#ifdef CONFIG_DCACHE - "wdc.flush %0, r0;" -#endif - "nop;" - : - : "r" (addr + i) - : "memory"); + __invalidate_icache(addr, size); + __flush_dcache(addr, size); +} + +void flush_cache_all(void) +{ + invalidate_icache_all(); + flush_dcache_all(); } diff --git a/arch/microblaze/cpu/cpuinfo.c b/arch/microblaze/cpu/cpuinfo.c new file mode 100644 index 0000000000000000000000000000000000000000..f021f4e5e2559e1f7ec55d98c87b0705c408c0d4 --- /dev/null +++ b/arch/microblaze/cpu/cpuinfo.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022, Ovidiu Panait + */ +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(CPU_MICROBLAZE) +/* These key value are as per MBV field in PVR0 */ +static const struct microblaze_version_map cpu_ver_lookup[] = { + {"5.00.a", 0x01}, + {"5.00.b", 0x02}, + {"5.00.c", 0x03}, + {"6.00.a", 0x04}, + {"6.00.b", 0x06}, + {"7.00.a", 0x05}, + {"7.00.b", 0x07}, + {"7.10.a", 0x08}, + {"7.10.b", 0x09}, + {"7.10.c", 0x0a}, + {"7.10.d", 0x0b}, + {"7.20.a", 0x0c}, + {"7.20.b", 0x0d}, + {"7.20.c", 0x0e}, + {"7.20.d", 0x0f}, + {"7.30.a", 0x10}, + {"7.30.b", 0x11}, + {"8.00.a", 0x12}, + {"8.00.b", 0x13}, + {"8.10.a", 0x14}, + {"8.20.a", 0x15}, + {"8.20.b", 0x16}, + {"8.30.a", 0x17}, + {"8.40.a", 0x18}, + {"8.40.b", 0x19}, + {"8.50.a", 0x1a}, + {"8.50.b", 0x1c}, + {"8.50.c", 0x1e}, + {"9.0", 0x1b}, + {"9.1", 0x1d}, + {"9.2", 0x1f}, + {"9.3", 0x20}, + {"9.4", 0x21}, + {"9.5", 0x22}, + {"9.6", 0x23}, + {"10.0", 0x24}, + {"11.0", 0x25}, + {NULL, 0}, +}; + +static const struct microblaze_version_map family_string_lookup[] = { + {"virtex2", 0x4}, + {"virtex2pro", 0x5}, + {"spartan3", 0x6}, + {"virtex4", 0x7}, + {"virtex5", 0x8}, + {"spartan3e", 0x9}, + {"spartan3a", 0xa}, + {"spartan3an", 0xb}, + {"spartan3adsp", 0xc}, + {"spartan6", 0xd}, + {"virtex6", 0xe}, + {"virtex7", 0xf}, + /* FIXME There is no key code defined for spartan2 */ + {"spartan2", 0xf0}, + {"kintex7", 0x10}, + {"artix7", 0x11}, + {"zynq7000", 0x12}, + {"UltraScale Virtex", 0x13}, + {"UltraScale Kintex", 0x14}, + {"UltraScale+ Zynq", 0x15}, + {"UltraScale+ Virtex", 0x16}, + {"UltraScale+ Kintex", 0x17}, + {"Spartan7", 0x18}, + {NULL, 0}, +}; + +static const char *lookup_string(u32 code, + const struct microblaze_version_map *entry) +{ + for (; entry->string; ++entry) + if (entry->code == code) + return entry->string; + + return "(unknown)"; +} + +static const u32 lookup_code(const char *string, + const struct microblaze_version_map *entry) +{ + for (; entry->string; ++entry) + if (!strcmp(entry->string, string)) + return entry->code; + + return 0; +} + +const char *microblaze_lookup_fpga_family_string(const u32 code) +{ + return lookup_string(code, family_string_lookup); +} + +const char *microblaze_lookup_cpu_version_string(const u32 code) +{ + return lookup_string(code, cpu_ver_lookup); +} + +const u32 microblaze_lookup_fpga_family_code(const char *string) +{ + return lookup_code(string, family_string_lookup); +} + +const u32 microblaze_lookup_cpu_version_code(const char *string) +{ + return lookup_code(string, cpu_ver_lookup); +} +#endif /* CONFIG_CPU_MICROBLAZE */ + +void microblaze_early_cpuinfo_init(void) +{ + struct microblaze_cpuinfo *ci = gd_cpuinfo(); + + ci->icache_size = CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE; + ci->icache_line_length = 4; + + ci->dcache_size = CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE; + ci->dcache_line_length = 4; +} diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index d3640d3903b81e6d66e69d6af77180a1c44f7c73..9414776afa7fa37b5634dad4b9e4bf690e3f3fe9 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -16,7 +16,7 @@ void _hw_exception_handler (void) /* loading address of exception EAR */ MFS(address, rear); - /* loading excetpion state register ESR */ + /* loading exception state register ESR */ MFS(state, resr); printf("Hardware exception at 0x%x address\n", address); R17(address); diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index fe65f3728fdbfec4d16d371468e007c801ff7d05..ac53208bda679b2b5e53c7b3c1c773b71723f1db 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -8,17 +8,8 @@ */ #include -#include -#include -#include -#include -#include -#include -#include #include -DECLARE_GLOBAL_DATA_PTR; - void enable_interrupts(void) { debug("Enable interrupts for the whole CPU\n"); @@ -34,183 +25,12 @@ int disable_interrupts(void) return (msr & 0x2) != 0; } -static struct irq_action *vecs; -static u32 irq_no; - -/* mapping structure to interrupt controller */ -microblaze_intc_t *intc; - -/* default handler */ -static void def_hdlr(void) -{ - puts("def_hdlr\n"); -} - -static void enable_one_interrupt(int irq) -{ - int mask; - int offset = 1; - - offset <<= irq; - mask = intc->ier; - intc->ier = (mask | offset); - - debug("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask, - intc->ier); - debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -} - -static void disable_one_interrupt(int irq) -{ - int mask; - int offset = 1; - - offset <<= irq; - mask = intc->ier; - intc->ier = (mask & ~offset); - - debug("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask, - intc->ier); - debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -} - -int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg) -{ - struct irq_action *act; - - /* irq out of range */ - if ((irq < 0) || (irq > irq_no)) { - puts("IRQ out of range\n"); - return -1; - } - act = &vecs[irq]; - if (hdlr) { /* enable */ - act->handler = hdlr; - act->arg = arg; - act->count = 0; - enable_one_interrupt(irq); - return 0; - } - - /* Disable */ - act->handler = (interrupt_handler_t *)def_hdlr; - act->arg = (void *)irq; - disable_one_interrupt(irq); - return 1; -} - -/* initialization interrupt controller - hardware */ -static void intc_init(void) -{ - intc->mer = 0; - intc->ier = 0; - intc->iar = 0xFFFFFFFF; - /* XIntc_Start - hw_interrupt enable and all interrupt enable */ - intc->mer = 0x3; - - debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -} - int interrupt_init(void) { - int i; - const void *blob = gd->fdt_blob; - int node = 0; - - debug("INTC: Initialization\n"); - - node = fdt_node_offset_by_compatible(blob, node, - "xlnx,xps-intc-1.00.a"); - if (node != -1) { - fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); - if (base == FDT_ADDR_T_NONE) - return -1; - - debug("INTC: Base addr %lx\n", base); - intc = (microblaze_intc_t *)base; - irq_no = fdtdec_get_int(blob, node, "xlnx,num-intr-inputs", 0); - debug("INTC: IRQ NO %x\n", irq_no); - } else { - return node; - } - - if (irq_no) { - vecs = calloc(1, sizeof(struct irq_action) * irq_no); - if (vecs == NULL) { - puts("Interrupt vector allocation failed\n"); - return -1; - } - - /* initialize irq list */ - for (i = 0; i < irq_no; i++) { - vecs[i].handler = (interrupt_handler_t *)def_hdlr; - vecs[i].arg = (void *)i; - vecs[i].count = 0; - } - /* initialize intc controller */ - intc_init(); - enable_interrupts(); - } else { - puts("Undefined interrupt controller\n"); - } return 0; } void interrupt_handler(void) { - int irqs = intc->ivr; /* find active interrupt */ - int mask = 1; - int value; - struct irq_action *act = vecs + irqs; - - debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -#ifdef DEBUG - R14(value); -#endif - debug("Interrupt handler on %x line, r14 %x\n", irqs, value); - - debug("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n", - (u32)act->handler, act->count, (u32)act->arg); - act->handler(act->arg); - act->count++; - - intc->iar = mask << irqs; - - debug("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr, - intc->ier, intc->iar, intc->mer); -#ifdef DEBUG - R14(value); -#endif - debug("Interrupt handler on %x line, r14 %x\n", irqs, value); -} - -#if defined(CONFIG_CMD_IRQ) -int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]) -{ - int i; - struct irq_action *act = vecs; - - if (irq_no) { - puts("\nInterrupt-Information:\n\n" - "Nr Routine Arg Count\n" - "-----------------------------\n"); - - for (i = 0; i < irq_no; i++) { - if (act->handler != (interrupt_handler_t *)def_hdlr) { - printf("%02d %08x %08x %d\n", i, - (int)act->handler, (int)act->arg, - act->count); - } - act++; - } - puts("\n"); - } else { - puts("Undefined interrupt controller\n"); - } - return 0; + panic("Interrupt occurred\n"); } -#endif diff --git a/arch/microblaze/cpu/pvr.c b/arch/microblaze/cpu/pvr.c new file mode 100644 index 0000000000000000000000000000000000000000..23c0f912d435a04ccd9d8ee4d8795de8dc951372 --- /dev/null +++ b/arch/microblaze/cpu/pvr.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022, Ovidiu Panait + */ +#include +#include +#include + +int microblaze_cpu_has_pvr_full(void) +{ + u32 msr, pvr0; + + MFS(msr, rmsr); + if (!(msr & PVR_MSR_BIT)) + return 0; + + get_pvr(0, pvr0); + debug("%s: pvr0 is 0x%08x\n", __func__, pvr0); + + if (!(pvr0 & PVR0_PVR_FULL_MASK)) + return 0; + + return 1; +} + +void microblaze_get_all_pvrs(u32 pvr[PVR_FULL_COUNT]) +{ + get_pvr(0, pvr[0]); + get_pvr(1, pvr[1]); + get_pvr(2, pvr[2]); + get_pvr(3, pvr[3]); + get_pvr(4, pvr[4]); + get_pvr(5, pvr[5]); + get_pvr(6, pvr[6]); + get_pvr(7, pvr[7]); + get_pvr(8, pvr[8]); + get_pvr(9, pvr[9]); + get_pvr(10, pvr[10]); + get_pvr(11, pvr[11]); + get_pvr(12, pvr[12]); +} diff --git a/arch/microblaze/cpu/relocate.c b/arch/microblaze/cpu/relocate.c new file mode 100644 index 0000000000000000000000000000000000000000..b00d02b1dfcc1b247a464ef0c6fb2e2cf4e5c9ed --- /dev/null +++ b/arch/microblaze/cpu/relocate.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2022 Advanced Micro Devices, Inc + * Michal Simek + */ + +#include +#include + +#define R_MICROBLAZE_NONE 0 +#define R_MICROBLAZE_32 1 +#define R_MICROBLAZE_REL 16 +#define R_MICROBLAZE_GLOB_DAT 18 + +/** + * mb_fix_rela - update relocation to new address + * @reloc_addr: new relocation address + * @verbose: enable version messages + * @rela_start: rela section start + * @rela_end: rela section end + * @dyn_start: dynamic section start + * @origin_addr: address where u-boot starts(doesn't need to be CONFIG_SYS_TEXT_BASE) + */ +void mb_fix_rela(u32 reloc_addr, u32 verbose, u32 rela_start, + u32 rela_end, u32 dyn_start, u32 origin_addr) +{ + u32 num, type, mask, i, reloc_off; + + /* + * Return in case u-boot.elf is used directly. + * Skip it when u-boot.bin is loaded to different address than + * CONFIG_SYS_TEXT_BASE. In this case relocation is necessary to run. + */ + if (reloc_addr == CONFIG_SYS_TEXT_BASE) { + debug_cond(verbose, + "Relocation address is the same - skip relocation\n"); + return; + } + + reloc_off = reloc_addr - origin_addr; + + debug_cond(verbose, "Relocation address:\t0x%08x\n", reloc_addr); + debug_cond(verbose, "Relocation offset:\t0x%08x\n", reloc_off); + debug_cond(verbose, "Origin address:\t0x%08x\n", origin_addr); + debug_cond(verbose, "Rela start:\t0x%08x\n", rela_start); + debug_cond(verbose, "Rela end:\t0x%08x\n", rela_end); + debug_cond(verbose, "Dynsym start:\t0x%08x\n", dyn_start); + + num = (rela_end - rela_start) / sizeof(Elf32_Rela); + + debug_cond(verbose, "Number of entries:\t%u\n", num); + + for (i = 0; i < num; i++) { + Elf32_Rela *rela; + u32 temp; + + rela = (Elf32_Rela *)(rela_start + sizeof(Elf32_Rela) * i); + + mask = 0xffULL; /* would be different on 32-bit */ + type = rela->r_info & mask; + + debug_cond(verbose, "\nRela possition:\t%d/0x%x\n", + i, (u32)rela); + + switch (type) { + case R_MICROBLAZE_REL: + temp = *(u32 *)rela->r_offset; + + debug_cond(verbose, "Type:\tREL\n"); + debug_cond(verbose, "Rela r_offset:\t\t0x%x\n", rela->r_offset); + debug_cond(verbose, "Rela r_info:\t\t0x%x\n", rela->r_info); + debug_cond(verbose, "Rela r_addend:\t\t0x%x\n", rela->r_addend); + debug_cond(verbose, "Value at r_offset:\t0x%x\n", temp); + + rela->r_offset += reloc_off; + rela->r_addend += reloc_off; + + temp = *(u32 *)rela->r_offset; + temp += reloc_off; + *(u32 *)rela->r_offset = temp; + + debug_cond(verbose, "New:Rela r_offset:\t0x%x\n", rela->r_offset); + debug_cond(verbose, "New:Rela r_addend:\t0x%x\n", rela->r_addend); + debug_cond(verbose, "New:Value at r_offset:\t0x%x\n", temp); + break; + case R_MICROBLAZE_32: + case R_MICROBLAZE_GLOB_DAT: + debug_cond(verbose, "Type:\t(32/GLOB) %u\n", type); + debug_cond(verbose, "Rela r_offset:\t\t0x%x\n", rela->r_offset); + debug_cond(verbose, "Rela r_info:\t\t0x%x\n", rela->r_info); + debug_cond(verbose, "Rela r_addend:\t\t0x%x\n", rela->r_addend); + debug_cond(verbose, "Value at r_offset:\t0x%x\n", temp); + + rela->r_offset += reloc_off; + + temp = *(u32 *)rela->r_offset; + temp += reloc_off; + *(u32 *)rela->r_offset = temp; + + debug_cond(verbose, "New:Rela r_offset:\t0x%x\n", rela->r_offset); + debug_cond(verbose, "New:Value at r_offset:\t0x%x\n", temp); + break; + case R_MICROBLAZE_NONE: + debug_cond(verbose, "R_MICROBLAZE_NONE - skip\n"); + break; + default: + debug_cond(verbose, "warning: unsupported relocation type %d at %x\n", + type, rela->r_offset); + } + } +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 645f7cb0389d768a0a29e9968310ba096b245485..a877db305e4ca61cd68a4003fde307e5d1e6b819 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -10,18 +10,64 @@ #include #include +#if defined(CONFIG_STATIC_RELA) +#define SYM_ADDR(reg, reg_add, symbol) \ + mfs r20, rpc; \ + addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \ + lwi reg, r20, symbol@GOT; \ + addk reg, reg reg_add; +#else +#define SYM_ADDR(reg, reg_add, symbol) \ + addi reg, reg_add, symbol +#endif + .text .global _start _start: mts rmsr, r0 /* disable cache */ + mfs r20, rpc + addi r20, r20, -4 - addi r8, r0, _end - mts rslr, r8 + mts rslr, r0 + mts rshr, r20 #if defined(CONFIG_SPL_BUILD) - addi r1, r0, CONFIG_SPL_STACK_ADDR + addi r1, r0, CONFIG_SPL_STACK #else - addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET + add r1, r0, r20 +#if defined(CONFIG_STATIC_RELA) + bri 1f + + /* Force alignment for easier ASM code below */ +#define ALIGNMENT_ADDR 0x20 + .align 4 +uboot_dyn_start: + .word __rel_dyn_start + +uboot_dyn_end: + .word __rel_dyn_end + +uboot_sym_start: + .word __dyn_sym_start +1: + + addi r5, r20, 0 + add r6, r0, r0 + + lwi r7, r20, ALIGNMENT_ADDR + addi r7, r7, -CONFIG_SYS_TEXT_BASE + add r7, r7, r5 + lwi r8, r20, ALIGNMENT_ADDR + 0x4 + addi r8, r8, -CONFIG_SYS_TEXT_BASE + add r8, r8, r5 + lwi r9, r20, ALIGNMENT_ADDR + 0x8 + addi r9, r9, -CONFIG_SYS_TEXT_BASE + add r9, r9, r5 + addi r10, r0, CONFIG_SYS_TEXT_BASE + + brlid r15, mb_fix_rela + nop +#endif #endif addi r1, r1, -4 /* Decrement SP to top of memory */ @@ -29,7 +75,7 @@ _start: /* Call board_init_f_alloc_reserve with the current stack pointer as * parameter. */ add r5, r0, r1 - bralid r15, board_init_f_alloc_reserve + brlid r15, board_init_f_alloc_reserve nop /* board_init_f_alloc_reserve returns a pointer to the allocated area @@ -41,20 +87,25 @@ _start: /* Call board_init_f_init_reserve with the address returned by * board_init_f_alloc_reserve as parameter. */ add r5, r0, r3 - bralid r15, board_init_f_init_reserve + brlid r15, board_init_f_init_reserve nop #if !defined(CONFIG_SPL_BUILD) /* Setup vectors with pre-relocation symbols */ or r5, r0, r0 - bralid r15, __setup_exceptions + brlid r15, __setup_exceptions nop #endif + /* + * Initialize global data cpuinfo with default values (cache + * size, cache line size, etc). + */ + brlid r15, microblaze_early_cpuinfo_init + nop + /* Flush cache before enable cache */ - addik r5, r0, 0 - addik r6, r0, XILINX_DCACHE_BYTE_SIZE - bralid r15, flush_cache + brlid r15, flush_cache_all nop /* enable instruction and data cache */ @@ -64,8 +115,8 @@ _start: clear_bss: /* clear BSS segments */ - addi r5, r0, __bss_start - addi r4, r0, __bss_end + SYM_ADDR(r5, r0, __bss_start) + SYM_ADDR(r4, r0, __bss_end) cmp r6, r5, r4 beqi r6, 3f 2: @@ -75,14 +126,14 @@ clear_bss: bnei r6, 2b 3: /* jumping to board_init */ #ifdef CONFIG_DEBUG_UART - bralid r15, debug_uart_init + brlid r15, debug_uart_init nop #endif #ifndef CONFIG_SPL_BUILD or r5, r0, r0 /* flags - empty */ - brai board_init_f + bri board_init_f #else - brai board_init_r + bri board_init_r #endif 1: bri 1b @@ -141,7 +192,8 @@ __setup_exceptions: swi r2, r4, 0x0 /* reset address - imm opcode */ swi r3, r4, 0x4 /* reset address - brai opcode */ - addik r6, r0, CONFIG_SYS_TEXT_BASE + SYM_ADDR(r6, r0, _start) + /* Intentionally keep reset vector back to origin u-boot location */ sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x2 @@ -154,7 +206,7 @@ __setup_exceptions: swi r2, r4, 0x8 /* user vector exception - imm opcode */ swi r3, r4, 0xC /* user vector exception - brai opcode */ - addik r6, r5, _exception_handler + SYM_ADDR(r6, r5, _exception_handler) sw r6, r1, r0 /* * BIG ENDIAN memory map for user exception @@ -187,7 +239,7 @@ __setup_exceptions: swi r2, r4, 0x10 /* interrupt - imm opcode */ swi r3, r4, 0x14 /* interrupt - brai opcode */ - addik r6, r5, _interrupt_handler + SYM_ADDR(r6, r5, _interrupt_handler) sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x12 @@ -199,7 +251,7 @@ __setup_exceptions: swi r2, r4, 0x20 /* hardware exception - imm opcode */ swi r3, r4, 0x24 /* hardware exception - brai opcode */ - addik r6, r5, _hw_exception_handler + SYM_ADDR(r6, r5, _hw_exception_handler) sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x22 @@ -220,39 +272,6 @@ __setup_exceptions: or r0, r0, r0 .end __setup_exceptions -/* - * Read 16bit little endian - */ - .text - .global in16 - .ent in16 - .align 2 -in16: lhu r3, r0, r5 - bslli r4, r3, 8 - bsrli r3, r3, 8 - andi r4, r4, 0xffff - or r3, r3, r4 - rtsd r15, 8 - sext16 r3, r3 - .end in16 - -/* - * Write 16bit little endian - * first parameter(r5) - address, second(r6) - short value - */ - .text - .global out16 - .ent out16 - .align 2 -out16: bslli r3, r6, 8 - bsrli r6, r6, 8 - andi r3, r3, 0xffff - or r3, r3, r6 - sh r3, r0, r5 - rtsd r15, 8 - or r0, r0, r0 - .end out16 - /* * Relocate u-boot */ @@ -267,31 +286,54 @@ relocate_code: * r7 - reloc_addr */ addi r1, r5, 0 /* Start to use new SP */ + mts rshr, r1 addi r31, r6, 0 /* Start to use new GD */ - add r23, r0, r7 /* Move reloc addr to r23 */ /* Relocate text and data - r12 temp value */ - addi r21, r0, _start - addi r22, r0, _end - 4 /* Include BSS too */ + SYM_ADDR(r21, r0, _start) + SYM_ADDR(r22, r0, _end) /* Include BSS too */ + addi r22, r22, -4 rsub r6, r21, r22 or r5, r0, r0 1: lw r12, r21, r5 /* Load u-boot data */ - sw r12, r23, r5 /* Write zero to loc */ + sw r12, r7, r5 /* Write zero to loc */ cmp r12, r5, r6 /* Check if we have reach the end */ bneid r12, 1b addi r5, r5, 4 /* Increment to next loc - relocate code */ /* R23 points to the base address. */ - add r23, r0, r7 /* Move reloc addr to r23 */ - addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */ - rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */ + rsub r23, r21, r7 /* keep - this is already here gd->reloc_off */ /* Setup vectors with post-relocation symbols */ add r5, r0, r23 /* load gd->reloc_off to r5 */ - bralid r15, __setup_exceptions + brlid r15, __setup_exceptions + nop + +#if defined(CONFIG_STATIC_RELA) + /* reloc_offset is current location */ + SYM_ADDR(r10, r0, _start) + + /* r5 new address where I should copy code */ + add r5, r0, r7 /* Move reloc addr to r5 */ + + /* Verbose message */ + addi r6, r0, 0 + + SYM_ADDR(r7, r0, __rel_dyn_start) + rsub r7, r10, r7 + add r7, r7, r5 + SYM_ADDR(r8, r0, __rel_dyn_end) + rsub r8, r10, r8 + add r8, r8, r5 + SYM_ADDR(r9, r0, __dyn_sym_start) + rsub r9, r10, r9 + add r9, r9, r5 + brlid r15, mb_fix_rela nop + /* end of code which does relocation */ +#else /* Check if GOT exist */ addik r21, r23, _got_start addik r22, r23, _got_end @@ -309,21 +351,15 @@ relocate_code: cmpu r12, r21, r22 /* Check if this cross boundary */ bneid r12, 3b addik r21. r21, 4 - - /* Update pointer to GOT */ - mfs r20, rpc - addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8 - addk r20, r20, r23 +#endif /* Flush caches to ensure consistency */ - addik r5, r0, 0 - addik r6, r0, XILINX_DCACHE_BYTE_SIZE - bralid r15, flush_cache + brlid r15, flush_cache_all nop 2: addi r5, r31, 0 /* gd is initialized in board_r.c */ - addi r6, r0, CONFIG_SYS_TEXT_BASE - addi r12, r23, board_init_r + SYM_ADDR(r6, r0, _start) + SYM_ADDR(r12, r23, board_init_r) bra r12 /* Jump to relocated code */ .end relocate_code diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c deleted file mode 100644 index 647bdcd5ba5295729a5a0d92aacdc13b11332f1d..0000000000000000000000000000000000000000 --- a/arch/microblaze/cpu/timer.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -volatile int timestamp = 0; -microblaze_timer_t *tmr; - -ulong get_timer (ulong base) -{ - if (tmr) - return timestamp - base; - return timestamp++ - base; -} - -void __udelay(unsigned long usec) -{ - u32 i; - - if (tmr) { - i = get_timer(0); - while ((get_timer(0) - i) < (usec / 1000)) - ; - } -} - -#ifndef CONFIG_SPL_BUILD -static void timer_isr(void *arg) -{ - timestamp++; - tmr->control = tmr->control | TIMER_INTERRUPT; -} - -int timer_init (void) -{ - int irq = -1; - u32 preload = 0; - u32 ret = 0; - const void *blob = gd->fdt_blob; - int node = 0; - u32 cell[2]; - - debug("TIMER: Initialization\n"); - - /* Do not init before relocation */ - if (!(gd->flags & GD_FLG_RELOC)) - return 0; - - node = fdt_node_offset_by_compatible(blob, node, - "xlnx,xps-timer-1.00.a"); - if (node != -1) { - fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); - if (base == FDT_ADDR_T_NONE) - return -1; - - debug("TIMER: Base addr %lx\n", base); - tmr = (microblaze_timer_t *)base; - - ret = fdtdec_get_int_array(blob, node, "interrupts", - cell, ARRAY_SIZE(cell)); - if (ret) - return ret; - - irq = cell[0]; - debug("TIMER: IRQ %x\n", irq); - - preload = fdtdec_get_int(blob, node, "clock-frequency", 0); - preload /= CONFIG_SYS_HZ; - } else { - return node; - } - - if (tmr && preload && irq >= 0) { - tmr->loadreg = preload; - tmr->control = TIMER_INTERRUPT | TIMER_RESET; - tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\ - TIMER_RELOAD | TIMER_DOWN_COUNT; - timestamp = 0; - ret = install_interrupt_handler (irq, timer_isr, (void *)tmr); - if (ret) - tmr = NULL; - } - /* No problem if timer is not found/initialized */ - return 0; -} -#else -int timer_init(void) -{ - return 0; -} -#endif - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On Microblaze it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On Microblaze it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 7883a64b158d9504334eea43ae32710dca64eb22..4ac5a21524c5cefb814e21101d2cef2937588278 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -37,8 +37,8 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } __init_end = . ; diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 2b316cc7f5a57f3cfc41fd9b59ac45c64911d5e2..a2c8fb2e21c031cb7f3dc1f4370af7b65afb900f 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -41,11 +41,25 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } __init_end = . ; + . = ALIGN(4); + __rel_dyn_start = .; + .rela.dyn : { + *(.rela.dyn) + } + __rel_dyn_end = .; + + . = ALIGN(4); + __dyn_sym_start = .; + .dynsym : { + *(.dynsym) + } + __dyn_sym_end = .; + .bss ALIGN(0x4): { __bss_start = .; diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h index baee01a0e2814ede877b5fcf468da33e28d1529c..c39b66dd7da633352d6ef0e8fd81d6520814d714 100644 --- a/arch/microblaze/include/asm/cache.h +++ b/arch/microblaze/include/asm/cache.h @@ -18,4 +18,9 @@ #define ARCH_DMA_MINALIGN 16 #endif +/** + * flush_cache_all - flush the entire instruction/data caches + */ +void flush_cache_all(void); + #endif /* __MICROBLAZE_CACHE_H__ */ diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 221eb93d58bc6f67531e8d2c42baa24b410bee60..bad0026648a1477581daa322ba2baae035e24d22 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h new file mode 100644 index 0000000000000000000000000000000000000000..86d2c8a034dc2abd5f96f05690abd5778a7ad6b1 --- /dev/null +++ b/arch/microblaze/include/asm/cpuinfo.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022, Ovidiu Panait + */ + +#ifndef __ASM_MICROBLAZE_CPUINFO_H +#define __ASM_MICROBLAZE_CPUINFO_H + +/** + * struct microblaze_cpuinfo - CPU info for microblaze processor core. + * + * @icache_size: Size of instruction cache memory in bytes. + * @icache_line_length: Instruction cache line length in bytes. + * @dcache_size: Size of data cache memory in bytes. + * @dcache_line_length: Data cache line length in bytes. + * @use_mmu: MMU support flag. + * @cpu_freq: Cpu clock frequency in Hz. + * @addr_size: Address bus width in bits. + * @ver_code: Cpu version code. + * @fpga_code: FPGA family version code. + */ +struct microblaze_cpuinfo { + u32 icache_size; + u32 icache_line_length; + + u32 dcache_size; + u32 dcache_line_length; + +#if CONFIG_IS_ENABLED(CPU_MICROBLAZE) + u32 use_mmu; + u32 cpu_freq; + u32 addr_size; + + u32 ver_code; + u32 fpga_code; +#endif /* CONFIG_CPU_MICROBLAZE */ +}; + +/** + * struct microblaze_version_data - Maps a hex version code to a cpu/fpga name. + */ +struct microblaze_version_map { + const char *string; + const u32 code; +}; + +/** + * microblaze_lookup_cpu_version_code() - Get hex version code for the + * specified cpu name string. + * + * This function searches the cpu_ver_lookup[] array for the hex version code + * associated with a specific CPU name. The version code is returned if a match + * is found, otherwise 0. + * + * @string: cpu name string + * + * Return: >0 if the entry is found, 0 otherwise. + */ +const u32 microblaze_lookup_cpu_version_code(const char *string); + +/** + * microblaze_lookup_fpga_family_code() - Get hex version code for the + * specified fpga family name. + * + * This function searches the family_string_lookup[] array for the hex version + * code associated with a specific fpga family name. The version code is + * returned if a match is found, otherwise 0. + * + * @string: fpga family name string + * + * Return: >0 if the entry is found, 0 otherwise. + */ +const u32 microblaze_lookup_fpga_family_code(const char *string); + +/** + * microblaze_lookup_cpu_version_string() - Get cpu name for the specified cpu + * version code. + * + * This function searches the cpu_ver_lookup[] array for the cpu name string + * associated with a specific version code. The cpu name is returned if a match + * is found, otherwise "(unknown)". + * + * @code: cpu version code + * + * Return: Pointer to the cpu name if the entry is found, otherwise "(unknown)". + */ +const char *microblaze_lookup_cpu_version_string(const u32 code); + +/** + * microblaze_lookup_fpga_family_string() - Get fpga family name for the + * specified version code. + * + * This function searches the family_string_lookup[] array for the fpga family + * name string associated with a specific version code. The fpga family name is + * returned if a match is found, otherwise "(unknown)". + * + * @code: fpga family version code + * + * Return: Pointer to the fpga family name if the entry is found, otherwise + * "(unknown)". + */ +const char *microblaze_lookup_fpga_family_string(const u32 code); + +/** + * microblaze_early_cpuinfo_init() - Initialize cpuinfo with default values. + * + * Initializes the global data cpuinfo structure with default values (cache + * size, cache line size, etc.). It is called very early in the boot process + * (start.S codepath right before the first cache flush call) to ensure that + * cache related operations are properly handled. + */ +void microblaze_early_cpuinfo_init(void); + +#endif /* __ASM_MICROBLAZE_CPUINFO_H */ diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index 05868ac4f54fb5188a82d673184d0af8985f6ba9..93506dec894e0dfb11ad47eec77eb6e3e96c46f9 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -8,12 +8,17 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include + /* Architecture-specific global data */ struct arch_global_data { + struct microblaze_cpuinfo cpuinfo; }; #include #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") +#define gd_cpuinfo() ((struct microblaze_cpuinfo *)&gd->arch.cpuinfo) + #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/microblaze/include/asm/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h deleted file mode 100644 index a7e8715851ead0e7477708c7ca15b762cfc93221..0000000000000000000000000000000000000000 --- a/arch/microblaze/include/asm/microblaze_intc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - */ - -#include - -typedef volatile struct microblaze_intc_t { - int isr; /* interrupt status register */ - int ipr; /* interrupt pending register */ - int ier; /* interrupt enable register */ - int iar; /* interrupt acknowledge register */ - int sie; /* set interrupt enable bits */ - int cie; /* clear interrupt enable bits */ - int ivr; /* interrupt vector register */ - int mer; /* master enable register */ -} microblaze_intc_t; - -struct irq_action { - interrupt_handler_t *handler; /* pointer to interrupt rutine */ - void *arg; - int count; /* number of interrupt */ -}; - -/** - * Register and unregister interrupt handler rutines - * - * @param irq IRQ number - * @param hdlr Interrupt handler rutine - * @param arg Pointer to argument which is passed to int. handler rutine - * Return: 0 if registration pass, 1 if unregistration pass, - * or an error code < 0 otherwise - */ -int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, - void *arg); diff --git a/arch/microblaze/include/asm/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h deleted file mode 100644 index 2ed1651ffcfa552f9e3b753473ca7c4fae5ff27e..0000000000000000000000000000000000000000 --- a/arch/microblaze/include/asm/microblaze_timer.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - */ - -#define TIMER_ENABLE_ALL 0x400 /* ENALL */ -#define TIMER_PWM 0x200 /* PWMA0 */ -#define TIMER_INTERRUPT 0x100 /* T0INT */ -#define TIMER_ENABLE 0x080 /* ENT0 */ -#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ -#define TIMER_RESET 0x020 /* LOAD0 */ -#define TIMER_RELOAD 0x010 /* ARHT0 */ -#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ -#define TIMER_EXT_COMPARE 0x004 /* GENT0 */ -#define TIMER_DOWN_COUNT 0x002 /* UDT0 */ -#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ - -typedef volatile struct microblaze_timer_t { - int control; /* control/statuc register TCSR */ - int loadreg; /* load register TLR */ - int counter; /* timer/counter register */ -} microblaze_timer_t; - -int timer_init(void); diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h new file mode 100644 index 0000000000000000000000000000000000000000..bfe159af7947498488ad0354ea0e71ced034cf68 --- /dev/null +++ b/arch/microblaze/include/asm/pvr.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022, Ovidiu Panait + */ + +#ifndef __ASM_MICROBLAZE_PVR_H +#define __ASM_MICROBLAZE_PVR_H + +#include + +#define PVR_FULL_COUNT 13 /* PVR0 - PVR12 */ + +#define __get_pvr(val, reg) \ + __asm__ __volatile__ ("mfs %0," #reg : "=r" (val) :: "memory") +#define get_pvr(pvrid, val) \ + __get_pvr(val, rpvr ## pvrid) + +#define PVR_MSR_BIT 0x00000400 + +/* PVR0 masks */ +#define PVR0_PVR_FULL_MASK 0x80000000 +#define PVR0_VERSION_MASK 0x0000FF00 + +/* PVR4 masks - ICache configs */ +#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */ +#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */ + +/* PVR5 masks - DCache configs */ +#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */ +#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */ + +/* PVR10 masks - FPGA family */ +#define PVR10_TARGET_FAMILY_MASK 0xFF000000 + +/* PVR11 masks - MMU */ +#define PVR11_USE_MMU 0xC0000000 + +/* PVR access macros */ +#define PVR_VERSION(pvr) \ + ((pvr[0] & PVR0_VERSION_MASK) >> 8) + +#define PVR_ICACHE_LINE_LEN(pvr) \ + ((1 << ((pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) << 2) +#define PVR_ICACHE_BYTE_SIZE(pvr) \ + (1 << ((pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) + +#define PVR_DCACHE_LINE_LEN(pvr) \ + ((1 << ((pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) << 2) +#define PVR_DCACHE_BYTE_SIZE(pvr) \ + (1 << ((pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) + +#define PVR_USE_MMU(pvr) \ + ((pvr[11] & PVR11_USE_MMU) >> 30) + +#define PVR_TARGET_FAMILY(pvr) \ + ((pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) + +/** + * microblaze_cpu_has_pvr_full() - Check for full PVR support + * + * Check MSR register for PVR support and, if applicable, check the PVR0 + * register for full PVR support. + * + * Return: 1 if there is full PVR support, 0 otherwise. + */ +int microblaze_cpu_has_pvr_full(void); + +/** + * microblaze_get_all_pvrs() - Copy PVR0-PVR12 to destination array + * + * @pvr: destination array of size PVR_FULL_COUNT + */ +void microblaze_get_all_pvrs(u32 pvr[PVR_FULL_COUNT]); + +#endif /* __ASM_MICROBLAZE_PVR_H */ diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 12ea32488e69ae7d67493d0ea2e08c96c2a7a25e..af946b864282b582c92f91ccbcf2ba326c8de440 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -57,9 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef XILINX_USE_DCACHE - flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#endif + flush_cache_all(); if (!fake) { /* diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9b62764f4fe684c411f08d7fb7c3a0434c733cf1..2e0793a7a7b8eab92cf28f150e607a3c5f5b0e76 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -180,24 +180,6 @@ source "arch/mips/mach-octeon/Kconfig" if MIPS -choice - prompt "Endianness selection" - help - Some MIPS boards can be configured for either little or big endian - byte order. These modes require different U-Boot images. In general there - is one preferred byteorder for a particular system but some systems are - just as commonly used in the one or the other endianness. - -config SYS_BIG_ENDIAN - bool "Big endian" - depends on SUPPORTS_BIG_ENDIAN - -config SYS_LITTLE_ENDIAN - bool "Little endian" - depends on SUPPORTS_LITTLE_ENDIAN - -endchoice - choice prompt "CPU selection" default CPU_MIPS32_R2 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6502aebd2960f420762874116909a79e77fe3ce7..32c436f2bcb690575a337c151e66db1ae094bd12 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -3,9 +3,7 @@ head-y := arch/mips/cpu/start.o ifeq ($(CONFIG_SPL_BUILD),y) -ifneq ($(CONFIG_SPL_START_S_PATH),) -head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o -endif +head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o endif libs-y += arch/mips/cpu/ diff --git a/arch/mips/config.mk b/arch/mips/config.mk index faf4129ac16c3c18a49444bea3e4744324c79f3d..04f362780580a3859b4671a77bf125e212f583f0 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -65,6 +65,6 @@ PLATFORM_CPPFLAGS += -msoft-float KBUILD_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j __u_boot_list LDFLAGS_STANDALONE += --gc-sections diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 47251a5b92a0cc5ca268181189711c6ac7b379cb..2acc21d5871c301b2a86d43777a85d97b8d75680 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -10,11 +10,7 @@ #include #include #include - -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) -#endif +#include #ifdef CONFIG_32BIT # define STATUS_SET 0 @@ -44,7 +40,7 @@ .macro setup_stack_gd li t0, -16 - PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR + PTR_LI t1, SYS_INIT_SP_ADDR and sp, t1, t0 # force 16 byte alignment PTR_SUBU \ sp, sp, GD_SIZE # reserve space for gd diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds index 28ea4f2a481dea61e513ef5956d5724bb1413c90..194398be8539ed450f695cfd524af29ef09ecbfb 100644 --- a/arch/mips/cpu/u-boot-spl.lds +++ b/arch/mips/cpu/u-boot-spl.lds @@ -29,8 +29,8 @@ SECTIONS #if defined(CONFIG_SPL_DM) || defined(CONFIG_SPL_LOADER_SUPPORT) . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .spl_mem #endif diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 86496737d350a5f74404588e216c915cc393c844..9a4ebcd151564cb740e466ab10bcb8d53d95e20f 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -33,8 +33,8 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h index 221eb93d58bc6f67531e8d2c42baa24b410bee60..bad0026648a1477581daa322ba2baae035e24d22 100644 --- a/arch/mips/include/asm/config.h +++ b/arch/mips/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S index 83cd8fa9b6b5e8c226d2154730fc784f561d41fc..cb369fbc27569c2665dfa92f14b01f302533c479 100644 --- a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S +++ b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S @@ -12,16 +12,11 @@ #include #include #include +#include #include "mt7628.h" -/* Set temporary stack address range */ -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) -#endif - #define CACHE_STACK_SIZE 0x4000 -#define CACHE_STACK_BASE (CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE) +#define CACHE_STACK_BASE (SYS_INIT_SP_ADDR - CACHE_STACK_SIZE) #define DELAY_USEC(us) ((58 * (us)) / 3) @@ -134,7 +129,7 @@ NESTED(lowlevel_init, 0, ra) #if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) /* Set malloc base */ - li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15) + li t0, (SYS_INIT_SP_ADDR + 15) & (~15) PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset #endif diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index cbf54b46103faaf2925e5cba7c98a1e49ff73bce..5b9e27d9406200bfb9a1466720181ad831cb44eb 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -32,8 +32,8 @@ SECTIONS */ . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } /* INIT DATA sections - "Small" data (see the gcc -G option) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index d1b9ae4c3c9228c688d7912fd922b4a83009f99a..9a31604ba3e6d71622e2fb0ba3d0e8f3cf480e6a 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -11,6 +11,11 @@ config E300 config SYS_CPU default "mpc83xx" +config SYS_83XX_DDR_USES_CS0 + bool + help + DDR should be configured using CS0 and CS1 instead of CS2 and CS3. + choice prompt "Target select" optional @@ -19,6 +24,7 @@ config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X select BOARD_EARLY_INIT_F + select SYS_83XX_DDR_USES_CS0 config TARGET_IDS8313 bool "Support ids8313" diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 7c4ef7657e5bf4875a1969e5e38a05fe2aeb5a36..1255f533e343ea24b2f84f23e76c2970efc64693 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -8,10 +8,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif extra-y = start.o diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index e6dcb8a3350735d2c12a991ae1345323998bba6e..33835eeec2a86443815ba2826d696eee42ff2cce 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -138,7 +139,7 @@ void cpu_init_f (volatile immap_t * im) 0; /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + gd = (gd_t *)SYS_INIT_SP_ADDR; /* global data region was cleared in start.S */ @@ -250,19 +251,6 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) - uint32_t temp; - struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - - /* Configure interface. */ - setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); - - /* Wait for clock to stabilize */ - do { - temp = __raw_readl(&ehci->control); - udelay(1000); - } while (!(temp & PHY_CLK_VALID)); -#endif } int cpu_init_r (void) diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 11b1e613fb90da056ea1f3868f12a37b4555a971..d8f6cfe2b4aa821a84f691f487a5036ef0fe2dd1 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -25,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; void cpu_init_f (volatile immap_t * im) { /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + gd = (gd_t *)SYS_INIT_SP_ADDR; /* global data region was cleared in start.S */ diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 0944d19105737ff9444c92f6ed472bd3f057997f..8a351b927c056f2cba1fefe44c1284918981cbd9 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -39,7 +40,7 @@ #endif #if defined(CONFIG_NAND_SPL) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) + (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) #define MINIMAL_SPL #endif @@ -229,8 +230,8 @@ in_flash: /* set up the stack pointer in our newly created * cache-ram; use r3 to keep the new SP for now to * avoid overiding the SP it uselessly */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l + lis r3, SYS_INIT_SP_ADDR@h + ori r3, r3, SYS_INIT_SP_ADDR@l /* r4 = end of GD area */ addi r4, r3, GENERATED_GBL_DATA_SIZE diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index d10f528da4c486787b5fef1018d9114d5245f5f5..1a1e537b2a765dc9b35b38917b726f507beb04fc 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -42,8 +42,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c1b4e94d91914d82b7cbec3448c1c4bd4e057082..b6881bf1ff3928efd88f38f01800e94f69c9edec 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" select ARCH_QEMU_E500 select PHYS_64BIT + select SYS_RAMBOOT imply OF_HAS_PRIOR_STAGE config TARGET_T1024RDB @@ -187,6 +188,7 @@ config ARCH_B4420 select E500MC select E6500 select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -195,7 +197,7 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 @@ -214,6 +216,7 @@ config ARCH_B4860 select E500MC select E6500 select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -222,7 +225,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 @@ -733,7 +736,7 @@ config ARCH_T2080 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -766,7 +769,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007798 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -822,11 +825,8 @@ config FSL_LAW help Use Freescale common code for Local Access Window -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. +config HETROGENOUS_CLUSTERS + bool config MAX_CPUS int "Maximum number of CPUs permitted for MPC85xx" @@ -1121,6 +1121,35 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +if HETROGENOUS_CLUSTERS + +config SYS_MAPLE + def_bool y + +config SYS_CPRI + def_bool y + +config PPC_CLUSTER_START + int + default 0 + +config DSP_CLUSTER_START + int + default 1 + +config SYS_CPRI_CLK + int + default 3 + +config SYS_ULB_CLK + int + default 4 + +config SYS_ETVPE_CLK + int + default 1 +endif + config BACKSIDE_L2_CACHE bool @@ -1185,6 +1214,48 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). +config ENABLE_36BIT_PHYS + bool "Enable 36bit physical address space support" + +config SYS_BOOK3E_HV + bool "Category E.HV is supported" + depends on BOOKE + +config SYS_CPC_REINIT_F + bool + help + The CPC is configured as SRAM at the time of U-Boot entry and is + required to be re-initialized. + +config SYS_FSL_CPC + bool "Corenet Platform Cache support" + +config SYS_CACHE_STASHING + bool "Enable cache stashing" + +config SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up" + depends on MPC85xx + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section. + +config SPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in SPL" + depends on MPC85xx && SPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + +config TPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in TPL" + depends on MPC85xx && TPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + config FSL_VIA bool diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index c32cde04e16a5cd7e973146956962da31474b6bb..f3ee7d34949c16b6c4b8f3b4334dec72fc951cb4 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -9,10 +9,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif extra-y = start.o resetvec.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index a82516a75bdc6c3271817feb52d215b86e83a7bd..ba9736ebef45c6a2ec7f98947c619c168fad8fc6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -344,6 +344,7 @@ __weak unsigned long get_tbclk(void) } +#ifndef CONFIG_WDT #if defined(CONFIG_WATCHDOG) #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) void @@ -372,6 +373,7 @@ watchdog_reset(void) enable_interrupts(); } #endif /* CONFIG_WATCHDOG */ +#endif /* * Initializes on-chip MMC controllers. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 5a0d33b1b3dd7b0d29c2d6494cc7bc2a5c898f41..1bba216371b8e70291aea40f813191307fe3b19a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -94,7 +95,7 @@ void cpu_init_early_f(void *fdt) #endif /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + gd = (gd_t *)SYS_INIT_SP_ADDR; /* gd area was zeroed during startup */ @@ -177,7 +178,7 @@ void cpu_init_early_f(void *fdt) invalidate_tlb(1); #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ - !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ + !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ !defined(CONFIG_NAND_SPL) disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 2b2ad973599592b91ad809b648ad12d17a1377e5..8a6340d800c3f53340feea564adf844b8c543058 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -27,7 +28,7 @@ #define LAW_EN 0x80000000 #if defined(CONFIG_NAND_SPL) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) + (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) #define MINIMAL_SPL #endif @@ -1125,9 +1126,8 @@ switch_as: #else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h - ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start_cont + lis r3,_start_cont@h + ori r3,r3,_start_cont@l mtlr r3 blr #endif @@ -1160,8 +1160,8 @@ _start_cont: bne 1b #if CONFIG_VAL(SYS_MALLOC_F_LEN) - lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l + lis r4,SYS_INIT_SP_ADDR@h + ori r4,r4,SYS_INIT_SP_ADDR@l addi r3,r3,16 /* Pre-relocation malloc area */ stw r3,GD_MALLOC_BASE(r4) @@ -1599,7 +1599,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start_cont + addi r0,r10,in_ram - CONFIG_VAL(SYS_MONITOR_BASE) /* * As IVPR is going to point RAM address, diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 550d45da0efa961ac674d215e92bcc818bfd138a..4f6778c720dbfdac4d493999c13a7a09585bd713 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -44,7 +44,7 @@ __weak void init_tlbs(void) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) + (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 1b4d1e05a4a3027d20f34fbd68283cbce8882e98..62c3c51dea263540b50bd3d431c25815a70f6950 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -9,24 +9,15 @@ #include "config.h" OUTPUT_ARCH(powerpc) -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} -#endif + SECTIONS { + . = IMAGE_TEXT_BASE; + .text : { /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg IMAGE_TEXT_BASE - 0x1000 : - { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(*(.bootpg)) - } :text = 0xffff #endif - . = IMAGE_TEXT_BASE; - .text : { *(.text*) } _etext = .; @@ -50,8 +41,8 @@ SECTIONS _edata = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = .; @@ -75,7 +66,7 @@ SECTIONS #endif /* For nor and nand is needed the SPL with section .resetvec */ -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index e1bbee43bcb4f91547a0351e47cb106b1476aacc..8fba71265557a8e3c60eada66cd955847a7d3c33 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -14,32 +14,22 @@ OUTPUT_ARCH(powerpc) ENTRY(_start) -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - SECTIONS { /* Read-only sections, merged into text segment: */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + .text : { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = CONFIG_SYS_TEXT_BASE; #endif - .text : - { *(.text*) - } :text + } _etext = .; PROVIDE (etext = .); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text + } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -67,8 +57,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = .; @@ -84,16 +74,16 @@ SECTIONS __init_end = .; _end = .; -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) - } :text = 0xffff + } = 0xffff .resetvec RESET_VECTOR_ADDRESS : { KEEP(*(.resetvec)) - } :text = 0xffff + } = 0xffff . = RESET_VECTOR_ADDRESS + 0x4; @@ -115,7 +105,7 @@ SECTIONS *(.sbss*) *(.bss*) *(COMMON) - } :bss + } . = ALIGN(4); __bss_end = . ; diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index bec891d5401c952c814cbf64e5b244d60ca374ca..e3a536d4f8c79f4869a0100373357739c47e4fdb 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -5,10 +5,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif ifdef MINIMAL diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 67f8b1000183c104ba85c1b2684fd9c0ee408e69..871554a7f481b62cd6d9883bf77ae11cdcb13f0e 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -17,10 +17,6 @@ #include #include -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) { diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index cf03f4101906a28a894b7bc9b0bbd4b057e77d29..713ff172bceeb9693f468a43d5d6d18bf571e63f 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -79,7 +79,7 @@ void disable_law(u8 idx) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) + (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; @@ -110,7 +110,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) + (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 1c3f78798eff87d560036e0f9c93d61dd521eb25..ea215ab075fee32d896514f7427114696407aebf 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -13,35 +13,28 @@ compatible = "fsl,p2020-immr", "simple-bus"; bus-frequency = <0x0>; - usb@22000 { - compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; - reg = <0x22000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <28 0x2 0 0>; - phy_type = "ulpi"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; }; - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic"; - device_type = "open-pic"; - big-endian; - single-cpu-affinity; - last-interrupt-source = <255>; + ecm@1000 { + compatible = "fsl,p2020-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2 0 0>; }; - esdhc: sdhc@2e000 { - compatible = "fsl,p2020-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <72 0x2 0 0>; - /* Filled in by U-Boot */ - clock-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,p2020-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <18 2 0 0>; }; +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" + espi0: spi@7000 { compatible = "fsl,mpc8536-espi"; #address-cells = <1>; @@ -51,9 +44,7 @@ fsl,espi-num-chipselects = <4>; }; -/include/ "pq3-i2c-0.dtsi" -/include/ "pq3-i2c-1.dtsi" -/include/ "pq3-duart-0.dtsi" +/include/ "pq3-dma-1.dtsi" /include/ "pq3-gpio-0.dtsi" L2: l2-cache-controller@20000 { @@ -64,6 +55,17 @@ interrupts = <16 2 0 0>; }; +/include/ "pq3-dma-0.dtsi" + + usb@22000 { + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; + phy_type = "ulpi"; + }; + /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" @@ -73,6 +75,29 @@ /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" + + esdhc: sdhc@2e000 { + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + +/include/ "pq3-sec3.1-0.dtsi" +/include/ "pq3-mpic.dtsi" +/include/ "pq3-mpic-timer-B.dtsi" + + global-utilities@e0000 { + compatible = "fsl,p2020-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + pmc: power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + }; }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/pq3-dma-0.dtsi b/arch/powerpc/dts/pq3-dma-0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b5b37ad30e750d2c873266f8b7160e90e93b9004 --- /dev/null +++ b/arch/powerpc/dts/pq3-dma-0.dtsi @@ -0,0 +1,66 @@ +/* + * PQ3 DMA device tree stub [ controller @ offset 0x21000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupts = <20 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <21 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <22 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <23 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-dma-1.dtsi b/arch/powerpc/dts/pq3-dma-1.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..28cb8a55d8074e1f4d12533a33e075589569454c --- /dev/null +++ b/arch/powerpc/dts/pq3-dma-1.dtsi @@ -0,0 +1,66 @@ +/* + * PQ3 DMA device tree stub [ controller @ offset 0xc300 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupts = <76 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <77 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <78 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <79 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-mpic-timer-B.dtsi b/arch/powerpc/dts/pq3-mpic-timer-B.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8734cffae1a130fcf3725fb4d006d99b7a17da55 --- /dev/null +++ b/arch/powerpc/dts/pq3-mpic-timer-B.dtsi @@ -0,0 +1,42 @@ +/* + * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +timer@42100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x42100 0x100 0x42300 4>; + interrupts = <4 0 3 0 + 5 0 3 0 + 6 0 3 0 + 7 0 3 0>; +}; diff --git a/arch/powerpc/dts/pq3-mpic.dtsi b/arch/powerpc/dts/pq3-mpic.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..71c30eb10056962c439d6e7900415d9c27c829fc --- /dev/null +++ b/arch/powerpc/dts/pq3-mpic.dtsi @@ -0,0 +1,79 @@ +/* + * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; +}; + +timer@41100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x41100 0x100 0x41300 4>; + interrupts = <0 0 3 0 + 1 0 3 0 + 2 0 3 0 + 3 0 3 0>; +}; + +message@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + interrupts = < + 0xb0 2 0 0 + 0xb1 2 0 0 + 0xb2 2 0 0 + 0xb3 2 0 0>; +}; + +msi@41600 { + compatible = "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 0 0 + 0xe1 0 0 0 + 0xe2 0 0 0 + 0xe3 0 0 0 + 0xe4 0 0 0 + 0xe5 0 0 0 + 0xe6 0 0 0 + 0xe7 0 0 0>; +}; diff --git a/arch/powerpc/dts/pq3-sec3.1-0.dtsi b/arch/powerpc/dts/pq3-sec3.1-0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8f0a5669bee52fcc88bf4fd861de1db46203c9f5 --- /dev/null +++ b/arch/powerpc/dts/pq3-sec3.1-0.dtsi @@ -0,0 +1,45 @@ +/* + * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +crypto@30000 { + compatible = "fsl,sec3.1", "fsl,sec3.0", + "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 0 0 58 2 0 0>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xbfe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; +}; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 059ffe1fd4f954a1669d00626239674884f66d40..79fe567b5875577c4eba9a9e10d1c93eec4c358e 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,8 +14,6 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #ifndef CONFIG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 47bfcc72444ced4b6e7f0b8353c0d68bf1d70027..a43e6e5e538b3195c3d68f5a98d42c76467293ed 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -18,8 +18,6 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SEC_MON_BE #if defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 @@ -31,35 +29,27 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -68,11 +58,9 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -84,7 +72,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -92,9 +79,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -118,7 +102,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -132,7 +115,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -151,7 +133,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -163,16 +144,13 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 @@ -180,7 +158,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_T4240) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -204,7 +181,6 @@ #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 @@ -219,33 +195,21 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 -#define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ -#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ -#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_MAPLE -#define CONFIG_SYS_CPRI #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 -#define CONFIG_SYS_CPRI_CLK 3 -#define CONFIG_SYS_ULB_CLK 4 -#define CONFIG_SYS_ETVPE_CLK 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_ARCH_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 @@ -255,7 +219,6 @@ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -278,7 +241,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -295,7 +257,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T1024) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -309,7 +270,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 @@ -323,7 +283,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -333,7 +292,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_PCI_VER_3_X #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 @@ -343,7 +301,6 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 @@ -354,10 +311,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_C29X) diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 39fbc04e4744675b6b47ab143a377cea5fad5487..9e2f2d5370d9fb33534c13a26cb2e6f79ba63c3a 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -78,6 +78,7 @@ enum law_trgt_if { enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, + LAW_TRGT_IF_PCIE_1 = 0x02, #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3a1d858ec6456a0afcdd10d0b2a20d7f08ec8d2a..3e707600f28fbff8a6e6d1714dca3931e70fa566 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,28 +10,17 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_TARGET_B4860QDS) || \ - defined(CONFIG_TARGET_B4420QDS) || \ - defined(CONFIG_TARGET_T4240QDS) || \ - defined(CONFIG_TARGET_T2080QDS) || \ +#if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CPC_REINIT_F -#endif -#define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif @@ -47,10 +36,6 @@ #endif #endif -#if defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_KEY_REVOCATION -#endif - #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ defined(CONFIG_ARCH_P5040) || \ @@ -80,55 +65,9 @@ #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 #define CONFIG_SPL_JR0_LIODN_S 454 #define CONFIG_SPL_JR0_LIODN_NS 458 -/* - * Define the key hash for U-Boot here if public/private key pair used to - * sign U-boot are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_SPL_UBOOT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - * else leave it defined as NULL - */ - -#define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ -#define CONFIG_FSL_SEC_MON - #ifndef CONFIG_SPL_BUILD -/* - * fsl_setenv_chain_of_trust() must be called from - * board_late_init() - */ - -/* If Boot Script is not on NOR and is required to be copied on RAM */ -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_HDR_ADDR_RAM 0x00010000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#define CONFIG_BS_ADDR_RAM 0x00012000 -#define CONFIG_BS_ADDR_DEVICE 0x00802000 -#define CONFIG_BS_SIZE 0x00001000 - -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else - -/* The bootscript header address is different for B4860 because the NOR - * mapping is different on B4 due to reduced NOR size. - */ -#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 -#elif defined(CONFIG_FSL_CORENET) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 -#else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 -#endif - -#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ - #include #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index d2443dc90d50ac955924589bf29464dd30ee1c63..6d1ddbcd27b549dd3a5fa30996d8b67daba4b78d 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -666,19 +666,6 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#ifndef CONFIG_ARCH_MPC834X -#ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ -#endif -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 -#endif - #elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ @@ -944,15 +931,6 @@ struct ccsr_gpio { #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) -#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 -#endif -#define CONFIG_SYS_MPC83xx_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_MPC83xx_USB2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) -#endif #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 2e6255f0d6068bc8badb7bac2ce4f2b1d10f59ea..b0aafdcdae10ddf369438883c6ddb2af9f949b2d 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -447,7 +447,7 @@ extern void print_bats(void); (((ts) << 12) & MAS1_TS) |\ (MAS1_TSIZE(tsize))) #define FSL_BOOKE_MAS2(epn, wimge) \ - (((epn) & MAS3_RPN) | (wimge)) + (((epn) & MAS2_EPN) | (wimge)) #define FSL_BOOKE_MAS3(rpn, user, perms) \ (((rpn) & MAS3_RPN) | (user) | (perms)) #define FSL_BOOKE_MAS7(rpn) \ diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 2782740bf5b33608d9be77e49dd2e7e5bb92a54b..066d7f408e08af0b3096ecc92a11a0c2e44fabb9 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -10,10 +10,12 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif obj-y += bdinfo.o diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 3b43066bb4f21c8e67ce1a4e1895d5a4a6b769c5..d365705856dd7b5157433f6d778502b94f5488fd 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -137,7 +137,8 @@ void arch_lmb_reserve(struct lmb *lmb) if (size < bootm_size) { ulong base = bootmap_base + size; - printf("WARNING: adjusting available memory to %lx\n", size); + printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", + size, (unsigned long long)bootm_size); lmb_reserve(lmb, base, bootm_size - size); } diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 76850ec9be2cf45668d9e097f0a1fcfec98d7961..f2ef5564a150f4f0b9b7d25546debec45740a42f 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -94,7 +95,7 @@ call_board_init_f: #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) li t1, CONFIG_SPL_STACK #else - li t1, CONFIG_SYS_INIT_SP_ADDR + li t1, SYS_INIT_SP_ADDR #endif and sp, t1, t0 /* force 16 byte alignment */ diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds index d0495ce2486a9eba507b69be824792be8f8c00b8..993536302a2756d7f221a5f2278a59a09e4fdbfa 100644 --- a/arch/riscv/cpu/u-boot-spl.lds +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -40,8 +40,8 @@ SECTIONS . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .spl_mem . = ALIGN(4); diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index c00d17c73696e09a67e05288026d118bb595f0be..1c937aebee082ded60773250fe6a8a17bf39bf6e 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -44,8 +44,8 @@ SECTIONS . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h index d911007537695cb9a86f98823712f39849df451c..c55c85d4e6cdee8fcb4fe978fada9a4b0c27376a 100644 --- a/arch/riscv/include/asm/config.h +++ b/arch/riscv/include/asm/config.h @@ -7,6 +7,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 5f55c7f28e1d6e8879811641ba6cb724c223059b..852a7c8bf2c2814f8120157d4b409438fbf04e7c 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -17,11 +17,11 @@ config SANDBOX64 config SANDBOX_RAM_SIZE_MB int "RAM size in MiB" - default 128 + default 256 range 64 4095 if !SANDBOX64 range 64 268435456 if SANDBOX64 help - Memory size of the sandbox in MiB. The default value is 128 MiB. + Memory size of the sandbox in MiB. The default value is 256 MiB. The minimum value is 64 MiB. The maximum value is 4095 MiB for the 32bit sandbox. diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 02a3ba0c0e941a5e2d2b3c8d3e20783d181e8727..3e2c7f9ebe55d0bd533e7ff12078440eae84c0a8 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -15,8 +15,19 @@ PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs) PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags) endif +SANITIZERS := +ifdef CONFIG_ASAN +SANITIZERS += -fsanitize=address +endif +ifdef CONFIG_FUZZ +SANITIZERS += -fsanitize=fuzzer +endif +KBUILD_CFLAGS += $(SANITIZERS) + cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \ - $(KBUILD_LDFLAGS:%=-Wl,%)$(LTO_FINAL_LDFLAGS) \ + $(KBUILD_LDFLAGS:%=-Wl,%) \ + $(SANITIZERS) \ + $(LTO_FINAL_LDFLAGS) \ -Wl,--whole-archive \ $(u-boot-main) \ $(u-boot-keep-syms-lto) \ @@ -24,7 +35,9 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \ - $(KBUILD_LDFLAGS:%=-Wl,%) $(LTO_FINAL_LDFLAGS) \ + $(KBUILD_LDFLAGS:%=-Wl,%) \ + $(SANITIZERS) \ + $(LTO_FINAL_LDFLAGS) \ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) \ -Wl,--whole-archive \ $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \ @@ -44,13 +57,13 @@ EFI_TARGET := --target=efi-app-ia32 else ifeq ($(HOST_ARCH),$(HOST_ARCH_AARCH64)) EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_aarch64_efi.lds OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \ - -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \ + -j __u_boot_list -j .rela.dyn -j .got -j .got.plt \ -j .binman_sym_table -j .text_rest \ -j .efi_runtime -j .efi_runtime_rel else ifeq ($(HOST_ARCH),$(HOST_ARCH_ARM)) EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_arm_efi.lds OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \ - -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \ + -j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \ -j .binman_sym_table -j .text_rest \ -j .efi_runtime -j .efi_runtime_rel else ifeq ($(HOST_ARCH),$(HOST_ARCH_RISCV32)) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 7a82798c36de8b968ec844cb6ab1fe0790fadc77..d077948dd7bd902821bf7f868a2f2cd2ecaf0139 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -331,27 +331,27 @@ void *board_fdt_blob_setup(int *ret) err = setup_auto_tree(blob); if (!err) goto done; - printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); + os_printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); *ret = -EINVAL; goto fail; } err = os_get_filesize(fname, &size); if (err < 0) { - printf("Failed to find FDT file '%s'\n", fname); + os_printf("Failed to find FDT file '%s'\n", fname); *ret = err; goto fail; } fd = os_open(fname, OS_O_RDONLY); if (fd < 0) { - printf("Failed to open FDT file '%s'\n", fname); + os_printf("Failed to open FDT file '%s'\n", fname); *ret = -EACCES; goto fail; } if (os_read(fd, blob, size) != size) { os_close(fd); - printf("Failed to read FDT file '%s'\n", fname); + os_printf("Failed to read FDT file '%s'\n", fname); *ret = -EIO; goto fail; } diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 5ea54179176c8e3d22722cbb0d71bcfb8403aa78..f937991139c93913255f69eadcb7585ab6c75d7b 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -8,9 +8,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -26,7 +28,9 @@ #include #include +#include #include +#include #include #include #include @@ -51,6 +55,18 @@ ssize_t os_write(int fd, const void *buf, size_t count) return write(fd, buf, count); } +int os_printf(const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = vfprintf(stdout, fmt, args); + va_end(args); + + return i; +} + off_t os_lseek(int fd, off_t offset, int whence) { if (whence == OS_SEEK_SET) @@ -1001,3 +1017,76 @@ void os_relaunch(char *argv[]) execv(argv[0], argv); os_exit(1); } + + +#ifdef CONFIG_FUZZ +static void *fuzzer_thread(void * ptr) +{ + char cmd[64]; + char *argv[5] = {"./u-boot", "-T", "-c", cmd, NULL}; + const char *fuzz_test; + + /* Find which test to run from an environment variable. */ + fuzz_test = getenv("UBOOT_SB_FUZZ_TEST"); + if (!fuzz_test) + os_abort(); + + snprintf(cmd, sizeof(cmd), "fuzz %s", fuzz_test); + + sandbox_main(4, argv); + os_abort(); + return NULL; +} + +static bool fuzzer_initialized = false; +static pthread_mutex_t fuzzer_mutex = PTHREAD_MUTEX_INITIALIZER; +static pthread_cond_t fuzzer_cond = PTHREAD_COND_INITIALIZER; +static const uint8_t *fuzzer_data; +static size_t fuzzer_size; + +int sandbox_fuzzing_engine_get_input(const uint8_t **data, size_t *size) +{ + if (!fuzzer_initialized) + return -ENOSYS; + + /* Tell the main thread we need new inputs then wait for them. */ + pthread_mutex_lock(&fuzzer_mutex); + pthread_cond_signal(&fuzzer_cond); + pthread_cond_wait(&fuzzer_cond, &fuzzer_mutex); + *data = fuzzer_data; + *size = fuzzer_size; + pthread_mutex_unlock(&fuzzer_mutex); + return 0; +} + +int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) +{ + static pthread_t tid; + + pthread_mutex_lock(&fuzzer_mutex); + + /* Initialize the sandbox on another thread. */ + if (!fuzzer_initialized) { + fuzzer_initialized = true; + if (pthread_create(&tid, NULL, fuzzer_thread, NULL)) + os_abort(); + pthread_cond_wait(&fuzzer_cond, &fuzzer_mutex); + } + + /* Hand over the input. */ + fuzzer_data = data; + fuzzer_size = size; + pthread_cond_signal(&fuzzer_cond); + + /* Wait for the inputs to be finished with. */ + pthread_cond_wait(&fuzzer_cond, &fuzzer_mutex); + pthread_mutex_unlock(&fuzzer_mutex); + + return 0; +} +#else +int main(int argc, char *argv[]) +{ + return sandbox_main(argc, argv); +} +#endif diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 0f5a87309d2a2e42cfd60d40183bf6662dbaf172..90a84e93c794209ee8b25cc0098d6f42ec8b14e5 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -453,7 +453,7 @@ void sandbox_reset(void) os_relaunch(os_argv); } -int main(int argc, char *argv[]) +int sandbox_main(int argc, char *argv[]) { struct sandbox_state *state; void * text_base; diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds index 206e265e74bf0ee451c6ec8182a5d652483dc268..ef885fd0cb00308f127573029223f2a0ec97ad13 100644 --- a/arch/sandbox/cpu/u-boot-spl.lds +++ b/arch/sandbox/cpu/u-boot-spl.lds @@ -9,8 +9,8 @@ SECTIONS { . = ALIGN(32); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } /* Private data for devices with OF_PLATDATA_RT */ @@ -22,9 +22,9 @@ SECTIONS } _u_boot_sandbox_getopt : { - *(.u_boot_sandbox_getopt_start) - KEEP(*(.u_boot_sandbox_getopt)) - *(.u_boot_sandbox_getopt_end) + *(_u_boot_sandbox_getopt_start) + KEEP(*(_u_boot_sandbox_getopt)) + *(_u_boot_sandbox_getopt_end) } } diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index 92e834a8d2bc0028082b65f1319f94f1d6a117c1..ba8dee50c7bd627cc0dc5d2fbf22f87831628fbc 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -9,42 +9,40 @@ SECTIONS { . = ALIGN(32); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } _u_boot_sandbox_getopt : { - *(.u_boot_sandbox_getopt_start) - *(.u_boot_sandbox_getopt) - *(.u_boot_sandbox_getopt_end) + *(_u_boot_sandbox_getopt_start) + *(_u_boot_sandbox_getopt) + *(_u_boot_sandbox_getopt_end) } - .__efi_runtime_start : { - *(.__efi_runtime_start) + efi_runtime_start : { + *(___efi_runtime_start) } - .efi_runtime : { + efi_runtime : { *(efi_runtime_text) *(efi_runtime_data) } - .__efi_runtime_stop : { - *(.__efi_runtime_stop) + efi_runtime_stop : { + *(___efi_runtime_stop) } - .efi_runtime_rel_start : - { - *(.__efi_runtime_rel_start) + efi_runtime_rel_start : { + *(___efi_runtime_rel_start) } - .efi_runtime_rel : { + efi_runtime_rel : { *(.relefi_runtime_text) *(.relefi_runtime_data) } - .efi_runtime_rel_stop : - { - *(.__efi_runtime_rel_stop) + efi_runtime_rel_stop : { + *(___efi_runtime_rel_stop) } .dynsym : diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 18fde1c8c6f071f464c3a96543a4429117514d0b..21f00fcab5ee6ca7747e672174c616246a98a589 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -63,7 +63,6 @@ eth@10002000 { compatible = "sandbox,eth"; reg = <0x10002000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 00]; }; host-fs { diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index ec53106af9dca8cc0d0e941e135d275248e104a7..3eb045708914ad5975080b24cbb82e76d612c0de 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -58,7 +58,6 @@ eth@10002000 { compatible = "sandbox,eth"; reg = <0x0 0x10002000 0x0 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 00]; }; i2c_0: i2c@0 { diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8f93775ff4a312494c3cb50f801453e46cecdd1b..0194b9b30ef8d30e6912f83886734e2f2a101b00 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -28,6 +28,9 @@ ethernet3 = ð_3; ethernet4 = &dsa_eth0; ethernet5 = ð_5; + ethernet6 = "/eth@10004000"; + ethernet7 = &swp_1; + ethernet8 = &phy_eth0; gpio1 = &gpio_a; gpio2 = &gpio_b; gpio3 = &gpio_c; @@ -89,6 +92,10 @@ }; }; + fuzzing-engine { + compatible = "sandbox,fuzzing-engine"; + }; + reboot-mode0 { compatible = "reboot-mode-gpio"; gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>; @@ -524,31 +531,31 @@ eth@10002000 { compatible = "sandbox,eth"; reg = <0x10002000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 00]; }; eth_5: eth@10003000 { compatible = "sandbox,eth"; reg = <0x10003000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 11]; + nvmem-cells = <ð5_addr>; + nvmem-cell-names = "mac-address"; }; eth_3: sbe5 { compatible = "sandbox,eth"; reg = <0x10005000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 33]; + nvmem-cells = <ð3_addr>; + nvmem-cell-names = "mac-address"; }; eth@10004000 { compatible = "sandbox,eth"; reg = <0x10004000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 22]; }; phy_eth0: phy-test-eth { compatible = "sandbox,eth"; reg = <0x10007000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 77]; + mac-address = [ 02 00 11 22 33 49 ]; phy-handle = <ðphy1>; phy-mode = "2500base-x"; }; @@ -556,7 +563,8 @@ dsa_eth0: dsa-test-eth { compatible = "sandbox,eth"; reg = <0x10006000 0x1000>; - fake-host-hwaddr = [00 00 66 44 22 66]; + nvmem-cells = <ð4_addr>; + nvmem-cell-names = "mac-address"; }; dsa-test { @@ -700,6 +708,8 @@ pinctrl-0 = <&pinmux_i2c0_pins>; eeprom@2c { + #address-cells = <1>; + #size-cells = <1>; reg = <0x2c>; compatible = "i2c-eeprom"; sandbox,emul = <&emul_eeprom>; @@ -711,12 +721,22 @@ reg = <10 2>; }; }; + + eth3_addr: mac-address@24 { + reg = <24 6>; + }; }; rtc_0: rtc@43 { + #address-cells = <1>; + #size-cells = <1>; reg = <0x43>; compatible = "sandbox-rtc"; sandbox,emul = <&emul0>; + + eth4_addr: mac-address@40 { + reg = <0x40 6>; + }; }; rtc_1: rtc@61 { @@ -898,7 +918,13 @@ }; misc-test { + #address-cells = <1>; + #size-cells = <1>; compatible = "sandbox,misc_sandbox"; + + eth5_addr: mac-address@10 { + reg = <0x10 6>; + }; }; mmc2 { diff --git a/arch/sandbox/include/asm/fuzzing_engine.h b/arch/sandbox/include/asm/fuzzing_engine.h new file mode 100644 index 0000000000000000000000000000000000000000..cf6396363bb49b9756339186ec540bb22a30d17e --- /dev/null +++ b/arch/sandbox/include/asm/fuzzing_engine.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#ifndef __ASM_FUZZING_ENGINE_H +#define __ASM_FUZZING_ENGINE_H + +/** Function to get fuzzing engine input data. */ +/** + * sandbox_fuzzing_engine_get_input() - get an input from the sandbox fuzzing + * engine + * + * The function will return a pointer to the input data and the size of the + * data pointed to. The pointer will remain valid until the next invocation of + * this function. + * + * @data: output pointer to input data + * @size output size of input data + * Return: 0 if OK, -ve on error + */ +int sandbox_fuzzing_engine_get_input(const uint8_t **data, size_t *size); + +#endif /* __ASM_FUZZING_ENGINE_H */ diff --git a/arch/sandbox/include/asm/getopt.h b/arch/sandbox/include/asm/getopt.h index d2145ad6e2d89a4f14a0cefa6035dfe93e767c1b..df30572d6c9e641b4dbb933092c7b4b87f0e078b 100644 --- a/arch/sandbox/include/asm/getopt.h +++ b/arch/sandbox/include/asm/getopt.h @@ -44,7 +44,7 @@ struct sandbox_cmdline_option { .callback = sandbox_cmdline_cb_##f, \ }; \ /* Ppointer to the struct in a special section for the linker script */ \ - static __used __section(".u_boot_sandbox_getopt") \ + static __used __section("_u_boot_sandbox_getopt") \ struct sandbox_cmdline_option \ *sandbox_cmdline_option_##f##_ptr = \ &sandbox_cmdline_option_##f diff --git a/arch/sandbox/include/asm/main.h b/arch/sandbox/include/asm/main.h new file mode 100644 index 0000000000000000000000000000000000000000..7a2f0d3a8d59c206a2eebf54346745e75cf8a41e --- /dev/null +++ b/arch/sandbox/include/asm/main.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#ifndef __ASM_SANDBOX_MAIN_H +#define __ASM_SANDBOX_MAIN_H + +/** + * sandbox_main() - main entrypoint for sandbox + * + * @argc: the number of arguments passed to the program + * @argv: array of argc+1 pointers, of which the last one is null + */ +int sandbox_main(int argc, char *argv[]); + +#endif /* __ASM_SANDBOX_MAIN_H */ diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h index f4351ae7dbf7ab3c8ba2107857eab5e4699ce711..88837bb35c83ca1f41c40ea04da781e5a5d46146 100644 --- a/arch/sandbox/include/asm/sections.h +++ b/arch/sandbox/include/asm/sections.h @@ -17,7 +17,7 @@ static inline struct sandbox_cmdline_option ** __u_boot_sandbox_option_start(void) { static char start[0] __aligned(4) __attribute__((unused)) - __section(".u_boot_sandbox_getopt_start"); + __section("_u_boot_sandbox_getopt_start"); return (struct sandbox_cmdline_option **)&start; } @@ -26,7 +26,7 @@ static inline struct sandbox_cmdline_option ** __u_boot_sandbox_option_end(void) { static char end[0] __aligned(4) __attribute__((unused)) - __section(".u_boot_sandbox_getopt_end"); + __section("_u_boot_sandbox_getopt_end"); return (struct sandbox_cmdline_option **)&end; } diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index d25dc7c82a03d5e8c2c562de834ce9da05de523c..bf5a585622be1c7ff2d63e58fbf32fa92d4ee6cc 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -6,8 +6,6 @@ #ifndef __asm_spl_h #define __asm_spl_h -#define CONFIG_SPL_BOARD_LOAD_IMAGE - enum { BOOT_DEVICE_BOARD, }; diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c index 2559eeea38beca905fec70f5adb92cd9616b007c..2f2f3fbfdb8681e0d29db7e9a6ae0ef127be49d3 100644 --- a/arch/sandbox/lib/sections.c +++ b/arch/sandbox/lib/sections.c @@ -5,9 +5,9 @@ */ #include -char __efi_runtime_start[0] __section(".__efi_runtime_start"); -char __efi_runtime_stop[0] __section(".__efi_runtime_stop"); +char __efi_runtime_start[0] __section("___efi_runtime_start"); +char __efi_runtime_stop[0] __section("___efi_runtime_stop"); char __efi_runtime_rel_start[0] - __section(".__efi_runtime_rel_start"); + __section("___efi_runtime_rel_start"); char __efi_runtime_rel_stop[0] - __section(".__efi_runtime_rel_stop"); + __section("___efi_runtime_rel_stop"); diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 4cc97737f1c97e0ad6811f633460cbf20bfb80a1..ff80ce78f3e09c9bda3ef889add71493d1c60fd8 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -70,8 +70,8 @@ SECTIONS } >ram PROVIDE (_egot = .); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } >ram PROVIDE (__init_end = .); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7cbfd6c9720877d4045516d327acf8f9e2c7c089..7e86c6a0cd0a31ae5ea0823e758d67bd16dc234e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -945,6 +945,7 @@ config ACPI_GPE config SPL_ACPI_GPE bool "Support ACPI general-purpose events in SPL" + depends on SPL help Enable a driver for ACPI GPEs to allow peripherals to send interrupts via ACPI to the OS. In U-Boot this is only used when U-Boot itself @@ -956,6 +957,7 @@ config SPL_ACPI_GPE config TPL_ACPI_GPE bool "Support ACPI general-purpose events in TPL" + depends on TPL help Enable a driver for ACPI GPEs to allow peripherals to send interrupts via ACPI to the OS. In U-Boot this is only used when U-Boot itself diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c index 5d7d26b140fca3b2811442f709f2a09084b1a68c..9a5502617bf553b3d5878cad4aa72b75f5d63041 100644 --- a/arch/x86/cpu/apollolake/cpu_common.c +++ b/arch/x86/cpu/apollolake/cpu_common.c @@ -72,7 +72,7 @@ static void pch_uart_init(void) } #ifdef CONFIG_DEBUG_UART - apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE); + apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE)); #endif } diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds index 92a30c2a387d25d0361aa53efe814b6cd12bd0ac..53c56043a9ebfaee71a898ba1c8c18fbb012b4bc 100644 --- a/arch/x86/cpu/u-boot-64.lds +++ b/arch/x86/cpu/u-boot-64.lds @@ -12,7 +12,7 @@ ENTRY(_start) SECTIONS { #ifndef CONFIG_CMDLINE - /DISCARD/ : { *(.u_boot_list_2_cmd_*) } + /DISCARD/ : { *(__u_boot_list_2_cmd_*) } #endif #ifdef CONFIG_SYS_TEXT_BASE @@ -41,8 +41,8 @@ SECTIONS . = ALIGN(4); . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index 346f60bdac0b7039e5924c0cd45d1152ec0b5e40..a0a2a06a18cd6d897fdbd9af37c3163933782bce 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -12,7 +12,7 @@ ENTRY(_start) SECTIONS { #ifndef CONFIG_CMDLINE - /DISCARD/ : { *(.u_boot_list_2_cmd_*) } + /DISCARD/ : { *(__u_boot_list_2_cmd_*) } #endif . = IMAGE_TEXT_BASE; /* Location of bootcode in flash */ @@ -25,8 +25,8 @@ SECTIONS . = ALIGN(4); . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index 22fde01e7499e41defbf483437c1b3ca05cb2b1b..7c872098342f61a078545e5c51a45676a4b2afde 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -12,7 +12,7 @@ ENTRY(_start) SECTIONS { #ifndef CONFIG_CMDLINE - /DISCARD/ : { *(.u_boot_list_2_cmd_*) } + /DISCARD/ : { *(__u_boot_list_2_cmd_*) } #endif . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ @@ -39,8 +39,8 @@ SECTIONS . = ALIGN(4); . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index 221eb93d58bc6f67531e8d2c42baa24b410bee60..bad0026648a1477581daa322ba2baae035e24d22 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h index cc6cac08f23b00567ab426af3678886418c83cec..483cf702cbb41dcf1acd641e0260858877e9ab0f 100644 --- a/arch/x86/include/asm/spl.h +++ b/arch/x86/include/asm/spl.h @@ -7,8 +7,6 @@ #ifndef __asm_spl_h #define __asm_spl_h -#define CONFIG_SPL_BOARD_LOAD_IMAGE - enum { BOOT_DEVICE_SPI_MMAP = 10, BOOT_DEVICE_FAST_SPI, diff --git a/arch/x86/lib/elf_ia32_efi.lds b/arch/x86/lib/elf_ia32_efi.lds index aad61e7f817c5481639de520e7f20588107f0c06..6d89c1fbd534c2c42c5b0f0357d3c000b5f97eb3 100644 --- a/arch/x86/lib/elf_ia32_efi.lds +++ b/arch/x86/lib/elf_ia32_efi.lds @@ -51,7 +51,7 @@ SECTIONS /* U-Boot lists and device tree */ . = ALIGN(8); - *(SORT(.u_boot_list*)); + *(SORT(__u_boot_list*)); . = ALIGN(8); *(.dtb*); } @@ -69,7 +69,7 @@ SECTIONS *(.data.rel.local) *(.data.rel.ro) *(.data.rel*) - *(.rel.u_boot_list*) + *(.rel__u_boot_list*) } . = ALIGN(4096); .reloc : /* This is the PECOFF .reloc section! */ diff --git a/arch/x86/lib/elf_x86_64_efi.lds b/arch/x86/lib/elf_x86_64_efi.lds index 75727400aa4bb37a4af570e294d9f496a15a951a..ada024c05c36aeb6ade836702c8b603d3fc41269 100644 --- a/arch/x86/lib/elf_x86_64_efi.lds +++ b/arch/x86/lib/elf_x86_64_efi.lds @@ -50,7 +50,7 @@ SECTIONS /* U-Boot lists and device tree */ . = ALIGN(8); - *(SORT(.u_boot_list*)); + *(SORT(__u_boot_list*)); . = ALIGN(8); *(.dtb*); } @@ -63,7 +63,7 @@ SECTIONS *(.rela.data*) *(.rela.got) *(.rela.stab) - *(.rela.u_boot_list*) + *(.rela__u_boot_list*) } . = ALIGN(4096); diff --git a/arch/xtensa/cpu/u-boot.lds b/arch/xtensa/cpu/u-boot.lds index 493f3fdb99bfc83a4de73e18d462de88c987c232..84ba32c0444403132ca663f3d4a1c644555c8e2f 100644 --- a/arch/xtensa/cpu/u-boot.lds +++ b/arch/xtensa/cpu/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS RELOCATE1(text); RELOCATE1(rodata); RELOCATE1(data); - RELOCATE1(u_boot_list); + RELOCATE_USER1(__u_boot_list); __reloc_table_end = ABSOLUTE(.); } @@ -78,7 +78,7 @@ SECTIONS SECTION_text(XTENSA_SYS_TEXT_ADDR, FOLLOWING(.DoubleExceptionVector.text)) SECTION_rodata(ALIGN(16), FOLLOWING(.text)) SECTION_u_boot_list(ALIGN(16), FOLLOWING(.rodata)) - SECTION_data(ALIGN(16), FOLLOWING(.u_boot_list)) + SECTION_data(ALIGN(16), FOLLOWING(__u_boot_list)) __reloc_end = .; __init_end = .; diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile index fbbdefaf2cf138cab66052b6f6661e29a2211cdd..c22c50ac4e5d7aebac6499a994668fbd48ddf385 100644 --- a/arch/xtensa/dts/Makefile +++ b/arch/xtensa/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb +dtb-$(CONFIG_XTENSA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/xtensa/include/asm/ldscript.h b/arch/xtensa/include/asm/ldscript.h index 08f5d0135ed0ece53fc76fe7a58a968cbca1625e..78a0b230bdaaba24ec9f1ef9dbeee72a1c20e746 100644 --- a/arch/xtensa/include/asm/ldscript.h +++ b/arch/xtensa/include/asm/ldscript.h @@ -41,6 +41,11 @@ LONG(_##_sym_##_##_sec_##_end); \ LONG(LOADADDR(.##_sym_##.##_sec_)); +#define RELOCATE_USER1(_sec_) \ + LONG(_##_sec_##_start); \ + LONG(_##_sec_##_end); \ + LONG(LOADADDR(_sec_)); + #define SECTION_VECTOR(_sym_, _sec_, _vma_, _lma_) \ .##_sym_##.##_sec_ _vma_ : _lma_ \ { \ @@ -100,11 +105,11 @@ } #define SECTION_u_boot_list(_vma_, _lma_) \ - .u_boot_list _vma_ : _lma_ \ + __u_boot_list _vma_ : _lma_ \ { \ - _u_boot_list_start = ABSOLUTE(.); \ - KEEP(*(SORT(.u_boot_list*))); \ - _u_boot_list_end = ABSOLUTE(.); \ + ___u_boot_list_start = ABSOLUTE(.); \ + KEEP(*(SORT(__u_boot_list*))); \ + ___u_boot_list_end = ABSOLUTE(.); \ } #define SECTION_data(_vma_, _lma_) \ diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 91eec35f474f70797234140557e5e4656a6546bc..36b67f0b524c882fd75624db0035933a16f527a9 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ax25-ae350/Kconfig @@ -27,6 +27,10 @@ config SPL_TEXT_BASE config SPL_OPENSBI_LOAD_ADDR default 0x01000000 +config SYS_FDT_BASE + hex + default 0x800f0000 if OF_SEPARATE + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select RISCV_NDS diff --git a/board/advantech/imx8mp_rsb3720a1/Kconfig b/board/advantech/imx8mp_rsb3720a1/Kconfig index 4486ed6d335a0bdfa70d435f23c47b480716c9e7..95cac7c4f09f1d3d1ebdf01096b9c16ccc6a6dbd 100644 --- a/board/advantech/imx8mp_rsb3720a1/Kconfig +++ b/board/advantech/imx8mp_rsb3720a1/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mp_rsb3720" -source "board/freescale/common/Kconfig" - endif diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index f129ebd429bdb6191624e418f29c3bc8d3a9c04e..0a1b2c94161904a9f93e12704e6c771636f86168 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -28,12 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static const iomux_v3_cfg_t wdog_pads[] = { - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { @@ -69,12 +63,6 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images); int board_early_init_f(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - init_uart_clk(2); return 0; diff --git a/board/advantech/imx8qm_rom7720_a1/Kconfig b/board/advantech/imx8qm_rom7720_a1/Kconfig index 8bf3a7d34846981e75e8f08acd3973ebec59051d..c846537f7432a4596a60b69510a16caf44fc5621 100644 --- a/board/advantech/imx8qm_rom7720_a1/Kconfig +++ b/board/advantech/imx8qm_rom7720_a1/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/advantech/imx8qm_rom7720_a1/imximage.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env new file mode 100644 index 0000000000000000000000000000000000000000..585f28ca8587d99aa7c7c79756c34574c638d40b --- /dev/null +++ b/board/armadeus/opos6uldev/opos6uldev.env @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Copyright (C) 2017 Armadeus Systems + */ + +/* Environment is stored in the eMMC boot partition */ + +env_version=100 +consoledev=ttymxc0 +board_name=opos6ul +fdt_addr=0x88000000 +fdt_high=0xffffffff +fdt_name=opos6uldev +initrd_high=0xffffffff +ip_dyn=yes +stdin=serial +stdout=serial +stderr=serial +mmcdev=0 +mmcpart=2 +mmcroot=/dev/mmcblk0p2 ro +mmcrootfstype=ext4 rootwait +kernelimg=opos6ul-linux.bin +splashpos=0,0 +splashimage=CONFIG_SYS_LOAD_ADDR +videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0 +check_env=if test -n ${flash_env_version}; + then env default env_version; + else env set flash_env_version ${env_version}; env save; + fi; + if itest ${flash_env_version} != ${env_version}; then + echo "*** Warning - Environment version + change suggests: run flash_reset_env; reset"; + env default flash_reset_env; + else exit; fi; +flash_reset_env=env default -f -a && saveenv && + echo Environment variables erased! +download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl +flash_uboot_spl= + if mmc dev 0 1; then + setexpr sz ${filesize} / 0x200; + setexpr sz ${sz} + 1; + if mmc write ${loadaddr} 0x2 ${sz}; then + echo Flashing of U-boot SPL succeed; + else echo Flashing of U-boot SPL failed; + fi; + fi; +download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img +flash_uboot_img= + if mmc dev 0 1; then + setexpr sz ${filesize} / 0x200; + setexpr sz ${sz} + 1; + if mmc write ${loadaddr} 0x8a ${sz}; then + echo Flashing of U-boot image succeed; + else echo Flashing of U-boot image failed; + fi; + fi; +update_uboot=run download_uboot_spl flash_uboot_spl + download_uboot_img flash_uboot_img +download_kernel=tftpboot ${loadaddr} ${kernelimg} +flash_kernel= + if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then + echo kernel update succeed; + else echo kernel update failed; + fi; +update_kernel=run download_kernel flash_kernel +download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb +flash_dtb= + if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then + echo dtb update succeed; + else echo dtb update in failed; + fi; +update_dtb=run download_dtb flash_dtb +download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4 +flash_rootfs= + if mmc dev 0 0; then + setexpr nbblocks ${filesize} / 0x200; + setexpr nbblocks ${nbblocks} + 1; + if mmc write ${loadaddr} 0x40800 ${nbblocks}; then + echo Flashing of rootfs image succeed; + else echo Flashing of rootfs image failed; + fi; + fi; +update_rootfs=run download_rootfs flash_rootfs +flash_failsafe= + if mmc dev 0 0; then + setexpr nbblocks ${filesize} / 0x200; + setexpr nbblocks ${nbblocks} + 1; + if mmc write ${loadaddr} 0x800 ${nbblocks}; then + echo Flashing of rootfs image in failsafe partition succeed; + else echo Flashing of rootfs image in failsafe partition failed; + fi; + fi; +update_failsafe=run download_rootfs flash_failsafe +download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4 +flash_userdata= + if mmc dev 0 0; then + setexpr nbblocks ${filesize} / 0x200; + setexpr nbblocks ${nbblocks} + 1; + if mmc write ${loadaddr} 0 ${nbblocks}; then + echo Flashing of user_data image succeed; + else echo Flashing of user_data image failed; + fi; + fi; +update_userdata=run download_userdata flash_userdata; mmc rescan +erase_userdata= + if mmc dev 0 0; then + echo Erasing eMMC User Data partition, no way out...; + mw ${loadaddr} 0 0x200000; + mmc write ${loadaddr} 0 0x1000; + mmc write ${loadaddr} 0x800 0x1000; + mmc write ${loadaddr} 0x40800 0x1000; + mmc write ${loadaddr} 0x440800 0x1000; + fi; + mmc rescan +update_all=run update_rootfs update_uboot +initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs} +addipargs=setenv bootargs ${bootargs} + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off +addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} + rootfstype=${mmcrootfstype} +emmcboot=run initargs; run addmmcargs; + load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && + load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && + bootz ${loadaddr} - ${fdt_addr}; +emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot; +addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw + nfsroot=${serverip}:${rootpath} +nfsboot=run initargs; run addnfsargs addipargs; + nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && + nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && + bootz ${loadaddr} - ${fdt_addr}; diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..709674d4cf7d28da20913208be2f3c0e2e0946b6 --- /dev/null +++ b/board/armltd/corstone1000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CORSTONE1000 + +config SYS_BOARD + default "corstone1000" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "corstone1000" + +endif diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..8c905686de76e4d1948bcbaa84fa6f3201543d38 --- /dev/null +++ b/board/armltd/corstone1000/MAINTAINERS @@ -0,0 +1,7 @@ +CORSTONE1000 BOARD +M: Rui Miguel Silva +M: Vishnu Banavath +S: Maintained +F: board/armltd/corstone1000/ +F: include/configs/corstone1000.h +F: configs/corstone1000_defconfig diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..77a82c28929b4cbbb90061af45acd7ecb55b2189 --- /dev/null +++ b/board/armltd/corstone1000/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Arm Limited +# (C) Copyright 2022 Linaro +# Rui Miguel Silva + +obj-y := corstone1000.o diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c new file mode 100644 index 0000000000000000000000000000000000000000..4f4b96a095c2f163533948f14a0087ff6ffa8f35 --- /dev/null +++ b/board/armltd/corstone1000/corstone1000.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva + */ + +#include +#include +#include +#include +#include +#include + +static struct mm_region corstone1000_mem_map[] = { + { + /* CVM */ + .virt = 0x02000000UL, + .phys = 0x02000000UL, + .size = 0x02000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* QSPI */ + .virt = 0x08000000UL, + .phys = 0x08000000UL, + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Host Peripherals */ + .virt = 0x1A000000UL, + .phys = 0x1A000000UL, + .size = 0x26000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* USB */ + .virt = 0x40200000UL, + .phys = 0x40200000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* ethernet */ + .virt = 0x40100000UL, + .phys = 0x40100000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCVM */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = corstone1000_mem_map; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/armltd/corstone1000/corstone1000.env b/board/armltd/corstone1000/corstone1000.env new file mode 100644 index 0000000000000000000000000000000000000000..b24ff07fc6bd5f4b36484bda16bed520a3197f10 --- /dev/null +++ b/board/armltd/corstone1000/corstone1000.env @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +usb_pgood_delay=250 +boot_bank_flag=0x08002000 +kernel_addr_bank_0=0x083EE000 +kernel_addr_bank_1=0x0936E000 +retrieve_kernel_load_addr= + if itest.l *${boot_bank_flag} == 0; then + setenv kernel_addr $kernel_addr_bank_0; + else + setenv kernel_addr $kernel_addr_bank_1; + fi; +kernel_addr_r=0x88200000 diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index ef82f066070309209db3bfd89bf2c3c6aa6e5bca..50a3830b8573c5fee24366aedf44b83032a34f47 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -168,7 +168,8 @@ Altera_CYC2_Passive_Serial_fns altera_fns = { altera_post_fn }; -Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { +#define FPGA_COUNT 1 +Altera_desc altera_fpga[FPGA_COUNT] = { {Altera_CYC2, passive_serial, 85903, @@ -182,7 +183,7 @@ int astro5373l_altera_load(void) { int i; - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + for (i = 0; i < FPGA_COUNT; i++) { /* * I did not yet manage to get relocation work properly, * so set stuff here instead of static initialisation: @@ -372,7 +373,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_fastwr_config_fn }; -xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc xilinx_fpga[FPGA_COUNT] = { {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, @@ -388,7 +389,7 @@ int astro5373l_xilinx_load(void) fpga_init(); - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + for (i = 0; i < FPGA_COUNT; i++) { /* * I did not yet manage to get relocation work properly, * so set stuff here instead of static initialisation: diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 38f97bce204219cf14c8a001da235f152f82f1fd..a9ea9b558a9e49ce42bf9bb0fa5168b6740f0262 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -74,9 +74,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 0318eeaa94e91739aee0aabbc60795d9ee226509..8a7a960c26b1d6567e17f93be31346515e3143bb 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -234,9 +234,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 3218e14e860ad82a3b8cd8fa56d2a693f9268cf0..c3e1734dda0cbfeaac34efc0baec8fa6b8d6b200 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -192,9 +192,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index fcca8923e38f555eae54157f829cd6708210533c..347197a6067d9cbc6f03f5429d065874258650f3 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -258,9 +258,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index a3fc55bbc34bd6413a6dab6fbf19766ef9633774..018fed9cc2aed6c3368e89144b6f14b2af3c36ed 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -176,9 +176,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index f427ee658bff62c58acbc042747dc3788f9d5099..af59620d0c02f306d414ae8765e3a2281fd55ee8 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -169,9 +169,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index e0abe4aeb08b5d68aa1c09d670afdd625cc93844..8192824c59c3051ff3fe0a0880f9d36be0589ae2 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -105,9 +105,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 00de27781252c399adea9eadabc6e7faf69990b2..d8f32c93b555633bcc8540e45a8b077cf6e43ef8 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -39,9 +39,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 32e5a2bf23af5cb48094e0c2246dfddc4f33533a..7035fab8788c4fdd674b0598a1112fcd9e7d06ae 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -101,9 +101,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index b69f1c8cfaedbe8732a5bd98dd5e2cca963c213e..65d0a7532ea92e601cdd35fdcc5d0182ae58f39b 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -65,10 +65,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif - return 0; } #endif diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 67ada27072deb2033a29afd3abad6060c4909469..c38585c6fe7cdab1445e7de5966e1f4b30d4bfbf 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -58,10 +58,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif - return 0; } #endif diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index da697a7b0fedc41379b436208dfdb5e2f90e6ea2..020777002823a17d281cbf47b7aceabfe3192cf4 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -48,9 +48,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index cca5bd1d8aacf54a1a50085eaf492dac1e9bccf7..16e9183f541430e3d380beee86174495eb1bfc86 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -108,9 +108,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 4bbb05c2fbfdc8942e9443cb1fb669ed66e37611..9e0f9c3b7e3c7afdf74d75b831a4a88b44de0103 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -64,10 +64,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif - return 0; } #endif diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index c25bf42e0af28c05d193af5f6adbd637063dd957..a778f2694df16efa655cc648ee95ab06930f2c63 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -87,9 +87,6 @@ int board_late_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index b6f8dcd91dc06d1240a598ab7e550b3fee24a5cc..132e7fad1ef7f49b87f4776a7c177dc17d2ebc5b 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -140,9 +140,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 2088b48b7ee218ee64b8e7cc6935e10d2f437946..9fb7e6f308de511227d5776171949da1fd8444df 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -102,9 +102,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 46ec1eb324679f53efa58a54c300d8f2af1aa180..ba385333433db54b8e959ab397ebb78d4efc91bc 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -100,9 +100,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index ae18ed05e05a82a8508b073d8a547a134590785b..7d83e76f9ac0a45ea2a77f2bf2bbe5ceb6b3fa38 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -48,9 +48,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#if (IS_ENABLED(CONFIG_DEBUG_UART)) - debug_uart_init(); -#endif return 0; } diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig index 63f064e8cb85ccbc2036e8cf4434e72e755596cb..e5d8aa3ec9cd580e75e797f1c7c51050bfd1dc27 100644 --- a/board/beacon/imx8mm/Kconfig +++ b/board/beacon/imx8mm/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/beacon/imx8mm/imximage-8mm-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12266b22a42fcdc1eb2d6b6d33beeeda2e70a843..a93cc9387842455d77752327a07ab060fff1247f 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -59,31 +59,6 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; -} - static int power_init_board(void) { struct udevice *dev; @@ -124,12 +99,8 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -139,6 +110,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig index fb301397b1ad4ad59f2acd48079682353d332d34..e11286c5c3ac00d4aa4968b64c5b46cb4d202006 100644 --- a/board/beacon/imx8mn/Kconfig +++ b/board/beacon/imx8mn/Kconfig @@ -18,6 +18,4 @@ config IMX8MN_BEACON_2GB_LPDDR config IMX_CONFIG default "board/beacon/imx8mn/imximage-8mn-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index bb51be01c5299780e2c83b266e1d9dc1464072ec..029f71bc9950a2cb2b07b4a325ff9b4aab435d3b 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -68,34 +68,17 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6) static iomux_v3_cfg_t const pwm_pads[] = { IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), }; -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - int board_early_init_f(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - /* Claiming pwm pins prevents LCD flicker during startup*/ imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(1); return 0; @@ -114,14 +97,14 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..63d4252da620c87d7ec8c12034589a456ef6efc1 --- /dev/null +++ b/board/broadcom/bcmbca/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +config SYS_BOARD + default "bcmbca" + +config SYS_VENDOR + default "broadcom" + +if TARGET_BCM947622 + +config SYS_CONFIG_NAME + default "bcm947622" + +endif diff --git a/board/broadcom/bcmbca/Makefile b/board/broadcom/bcmbca/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..8f06c3111b9b36c252b99561df9a09867aadae49 --- /dev/null +++ b/board/broadcom/bcmbca/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd + +obj-y += board.o diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c new file mode 100644 index 0000000000000000000000000000000000000000..4aa1d659d5c7c1ef689769f0bb6a6d2874289c06 --- /dev/null +++ b/board/broadcom/bcmbca/board.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + puts("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/bsh/imx8mn_smm_s2/Kconfig b/board/bsh/imx8mn_smm_s2/Kconfig index f43d058f2188631800a56e7640a6d9ced3965ee5..041a9c78a66d93a4eba3ae3ea175c4ef98c56134 100644 --- a/board/bsh/imx8mn_smm_s2/Kconfig +++ b/board/bsh/imx8mn_smm_s2/Kconfig @@ -22,8 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BSH_SMM_S2_DDR3L_256 -source "board/freescale/common/Kconfig" - endif if TARGET_IMX8MN_BSH_SMM_S2PRO @@ -44,6 +42,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BSH_SMM_S2_DDR3L_512 -source "board/freescale/common/Kconfig" - endif diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds index b00e466d580c28d38f7405c8a82f4b7efeffbfb7..49938804611c9214661ae069423dc89028ee2213 100644 --- a/board/compulab/cm_t335/u-boot.lds +++ b/board/compulab/cm_t335/u-boot.lds @@ -36,8 +36,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 2dc62d6682e041e1f96fbceeaf6262d808fbf5c6..d2d20269ba07ea1df40071dc9ab010c2482f67d3 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -83,31 +83,6 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; -} - static int power_init_board(void) { struct udevice *dev; @@ -149,14 +124,10 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - init_uart_clk(2); timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -166,6 +137,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig index d4a238de99bc03b56eeb1850a15b6498838a6020..a1f2139219b134509a8bd42791ff55dbcea86d35 100644 --- a/board/congatec/common/Kconfig +++ b/board/congatec/common/Kconfig @@ -1,44 +1,3 @@ -if !ARCH_IMX8M && !ARCH_IMX8 - -config CHAIN_OF_TRUST - depends on !FIT_SIGNATURE && SECURE_BOOT - imply CMD_BLOB - imply CMD_HASH if ARM - select FSL_CAAM - select SPL_BOARD_INIT if (ARM && SPL) - select SHA_HW_ACCEL - select SHA_PROG_HW_ACCEL - select ENV_IS_NOWHERE - select CMD_EXT4 if ARM - select CMD_EXT4_WRITE if ARM - bool - default y - -config CMD_ESBC_VALIDATE - bool "Enable the 'esbc_validate' and 'esbc_halt' commands" - default y if CHAIN_OF_TRUST - help - This option enables two commands used for secure booting: - - esbc_validate - validate signature using RSA verification - esbc_halt - put the core in spin loop (Secure Boot Only) - -endif - -config VOL_MONITOR_LTC3882_READ - depends on VID - bool "Enable the LTC3882 voltage monitor read" - help - This option enables LTC3882 voltage monitor read - functionality. It is used by common VID driver. - -config VOL_MONITOR_LTC3882_SET - depends on VID - bool "Enable the LTC3882 voltage monitor set" - help - This option enables LTC3882 voltage monitor set - functionality. It is used by common VID driver. - config USB_TCPC bool "USB Typec port controller simple driver" help diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile index d4ddfbf9716222447402797a5b70946b260e9cb0..2db0fc1ae5c3dbbe22586c95de75dc8b8498cd94 100644 --- a/board/congatec/common/Makefile +++ b/board/congatec/common/Makefile @@ -8,10 +8,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif ifdef MINIMAL # necessary to create built-in.o diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds index 70aef3241c8e448f0f379e29943f8563a8772be3..24b535e724aac8ef990678f535fe497dc4ba22da 100644 --- a/board/cssi/MCR3000/u-boot.lds +++ b/board/cssi/MCR3000/u-boot.lds @@ -59,8 +59,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = .; diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 8f04911306bc4127cea744fefcf73f9056e0630e..7e0f09f3b5b17478a5883c648619e1cc76daff4f 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -11,7 +11,7 @@ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ LENGTH = CONFIG_SPL_MAX_FOOTPRINT } MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + LENGTH = 0x1080000 } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -36,7 +36,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram + __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); } >.sram . = ALIGN(4); .rel.dyn : { diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d407f0bf5921e28fc1ed7114aa51536720f494ed..7a4c08cb7fda00e0b183fd9b8b672573313ec4c9 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -78,11 +77,6 @@ #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - #define KS_CCR 0x08 #define KS_CCR_EEPROM BIT(9) #define KS_BE0 BIT(12) @@ -96,14 +90,15 @@ int setup_mac_address(void) bool skip_eth0 = false; bool skip_eth1 = false; struct udevice *dev; - int off, ret; + int ret; + ofnode node; ret = eth_env_get_enetaddr("ethaddr", enetaddr); if (ret) /* ethaddr is already set */ skip_eth0 = true; - off = fdt_path_offset(gd->fdt_blob, "ethernet1"); - if (off < 0) { + node = ofnode_path("ethernet1"); + if (!ofnode_valid(node)) { /* ethernet1 is not present in the system */ skip_eth1 = true; goto out_set_ethaddr; @@ -116,7 +111,7 @@ int setup_mac_address(void) goto out_set_ethaddr; } - ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll"); + ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll"); if (ret) goto out_set_ethaddr; @@ -127,7 +122,7 @@ int setup_mac_address(void) * MAC address. */ u32 reg, cider, ccr; - reg = fdt_get_base_address(gd->fdt_blob, off); + reg = ofnode_get_addr(node); if (!reg) goto out_set_ethaddr; @@ -149,13 +144,13 @@ out_set_ethaddr: if (skip_eth0 && skip_eth1) return 0; - off = fdt_path_offset(gd->fdt_blob, "eeprom0"); - if (off < 0) { + node = ofnode_path("eeprom0"); + if (!ofnode_valid(node)) { printf("%s: No eeprom0 path offset\n", __func__); - return off; + return -ENOENT; } - ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev); if (ret) { printf("Cannot find EEPROM!\n"); return ret; @@ -191,8 +186,8 @@ int checkboard(void) mode = "basic"; printf("Board: stm32mp1 in %s mode", mode); - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) printf(" (%s)", fdt_compat); puts("\n"); @@ -289,7 +284,7 @@ int board_fit_config_name_match(const char *name) const char *compat; char test[128]; - compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL); + compat = ofnode_get_property(ofnode_root(), "compatible", NULL); snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d", compat, somcode, brdcode); @@ -604,14 +599,13 @@ static void board_init_fmc2(void) #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) ((((n) - 1) & 3) * 2) static int board_get_regulator_buck3_nvm_uv_av96(int *uv) { - const void *fdt = gd->fdt_blob; struct udevice *dev; u8 bucks_vout = 0; const char *prop; int len, ret; /* Check whether this is Avenger96 board. */ - prop = fdt_getprop(fdt, 0, "compatible", &len); + prop = ofnode_get_property(ofnode_root(), "compatible", &len); if (!prop || !len) return -ENODEV; @@ -701,8 +695,8 @@ int board_late_init(void) const void *fdt_compat; int fdt_compat_len; - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) { if (strncmp(fdt_compat, "st,", 3) != 0) env_set("board_name", fdt_compat); diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 2b483dab8e122547266d8e89247a1d50cd7a9cd0..1054837d434d398b9e6054d49f3f385875edb62b 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -273,7 +273,7 @@ void board_debug_uart_init(void) setup_early_clocks(); /* done by pin controller driver if not debugging */ - enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE); + enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE)); } #endif diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 348fcf3bb09997a4b041c81da58280a5fe3a2773..99edaa3b4215925f7879992d6bb5295315657d35 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR; +/* Virtual address range for PCI region maps */ +#define SYS_PCI_MAP_START 0x80000000 +#define SYS_PCI_MAP_END 0xe0000000 + static void *get_fdt_virt(void) { if (gd->flags & GD_FLG_RELOC) @@ -101,7 +105,7 @@ static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr) map_addr += size - 1; map_addr &= ~(size - 1); - if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) + if (map_addr + size >= SYS_PCI_MAP_END) return -1; /* Map virtual memory for range */ @@ -137,7 +141,7 @@ int misc_init_r(void) pci_get_regions(dev, &io, &mem, &pre); /* Start MMIO and PIO range maps above RAM */ - map_addr = CONFIG_SYS_PCI_MAP_START; + map_addr = SYS_PCI_MAP_START; /* Map MMIO range */ ret = pci_map_region(mem->phys_start, mem->size, &map_addr); diff --git a/board/engicam/imx8mm/Kconfig b/board/engicam/imx8mm/Kconfig index 5495b3bf99be44cdbc1e76439350dce7a8851bdb..3b3b93bb2f0a65fd7aebfeec0fcc961d4846de12 100644 --- a/board/engicam/imx8mm/Kconfig +++ b/board/engicam/imx8mm/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index f9be769ec59959457e5d4b45c993fd274aaaa74b..1846134a49255dc5c3fb125ed4980a4dcf6727b8 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -54,19 +54,9 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - int board_early_init_f(void) { - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; + return 0; } void board_init_f(ulong dummy) @@ -81,8 +71,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -92,6 +80,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index 20d8603c78cad2ae671d2953b8e9743cb8d37e0f..0a3e580f5b44759e517fd1cdd940bcd5b7516b3e 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -14,8 +14,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int checkboard(void) { char *mode; @@ -28,8 +26,8 @@ int checkboard(void) mode = "basic"; printf("Board: stm32mp1 in %s mode", mode); - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) printf(" (%s)", fdt_compat); puts("\n"); diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig deleted file mode 100644 index b0e6e43f4fea00ea51bc4f5d0bc768cf28635573..0000000000000000000000000000000000000000 --- a/board/freescale/common/Kconfig +++ /dev/null @@ -1,110 +0,0 @@ -config CHAIN_OF_TRUST - depends on !FIT_SIGNATURE && NXP_ESBC - imply CMD_BLOB - imply CMD_HASH if ARM - select FSL_CAAM - select ARCH_MISC_INIT - select SPL_BOARD_INIT if (ARM && SPL) - select SPL_HASH if (ARM && SPL) - select SHA_HW_ACCEL - select SHA_PROG_HW_ACCEL - select ENV_IS_NOWHERE - select CMD_EXT4 if ARM - select CMD_EXT4_WRITE if ARM - bool - default y - -config CMD_ESBC_VALIDATE - bool "Enable the 'esbc_validate' and 'esbc_halt' commands" - default y if CHAIN_OF_TRUST - help - This option enables two commands used for secure booting: - - esbc_validate - validate signature using RSA verification - esbc_halt - put the core in spin loop (Secure Boot Only) - -config DEEP_SLEEP - bool "Enable SoC deep sleep feature" - default y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A - help - Indicates this SoC supports deep sleep feature. If deep sleep is - supported, core will start to execute uboot when wakes up. - -config FSL_USE_PCA9547_MUX - bool "Enable PCA9547 I2C Mux on Freescale boards" - help - This option enables the PCA9547 I2C mux on Freescale boards. - -config VID - bool "Enable Freescale VID" - depends on I2C || DM_I2C - help - This option enables setting core voltage based on individual - values saved in SoC fuses. - -config SPL_VID - bool "Enable Freescale VID in SPL" - depends on I2C || DM_I2C - help - This option enables setting core voltage based on individual - values saved in SoC fuses, in SPL. - -if VID || SPL_VID - -config VID_FLS_ENV - string "Environment variable for overriding VDD" - help - This option allows for specifying the environment variable - to check to override VDD information. - -config VOL_MONITOR_INA220 - bool "Enable the INA220 voltage monitor read" - help - This option enables INA220 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_IR36021_READ - bool "Enable the IR36021 voltage monitor read" - help - This option enables IR36021 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_IR36021_SET - bool "Enable the IR36021 voltage monitor set" - help - This option enables IR36021 voltage monitor set - functionality. It is used by the common VID driver. - -config VOL_MONITOR_LTC3882_READ - bool "Enable the LTC3882 voltage monitor read" - help - This option enables LTC3882 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_LTC3882_SET - bool "Enable the LTC3882 voltage monitor set" - help - This option enables LTC3882 voltage monitor set - functionality. It is used by the common VID driver. - -config VOL_MONITOR_ISL68233_READ - bool "Enable the ISL68233 voltage monitor read" - help - This option enables ISL68233 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_ISL68233_SET - bool "Enable the ISL68233 voltage monitor set" - help - This option enables ISL68233 voltage monitor set - functionality. It is used by the common VID driver. - -endif - -config FSL_QIXIS - bool "Enable QIXIS support" - -config QIXIS_I2C_ACCESS - bool "Access to QIXIS is over i2c" - depends on FSL_QIXIS - default y diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 4df484935f4c0e0ffff55721671729cfe33142de..4214c6e46e48ecb89ede9b72cbe6b062c05b1677 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -6,10 +6,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif ifdef MINIMAL # necessary to create built-in.o diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 7ffb315bc9352b2644c913323bfc890ffa2f12f5..d31fb821817c388ee70d5b5b0d2e9d5e734bf3fb 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -12,6 +12,7 @@ #include #include #include +#include #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) #include @@ -76,14 +77,14 @@ int fsl_setenv_chain_of_trust(void) /* If Boot mode is Secure, set the environment variables * bootdelay = 0 (To disable Boot Prompt) - * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) + * bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script) */ env_set("bootdelay", "-2"); #ifdef CONFIG_ARM env_set("secureboot", "y"); #else - env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD); + env_set("bootcmd", CHAIN_BOOT_CMD); #endif return 0; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 34875d0b8f2572a527c060d763f88f2742c61473..f1a0b0cfc34ca25e735248c5a88c976afc58a048 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -871,7 +871,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, int ret, i, hash_cmd = 0; u32 srk_hash[8]; - if (arg_hash_str != NULL) { + if (strlen(arg_hash_str) != 0) { const char *cp = arg_hash_str; int i = 0; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 0860bd2312670fe8a71795f4703d16a4b3444d89..af76327e4d2f6806ed3dcc119406d756de94dcee 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -166,4 +166,25 @@ defined(CONFIG_TARGET_LX2160ARDB) #define QIXIS_ESDHC_NO_ADAPTER 0x7 #endif +/* + * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. + */ +static inline u8 qixis_esdhc_detect_quirk(void) +{ + /* + * SDHC1 Card ID: + * Specifies the type of card installed in the SDHC1 adapter slot. + * 000= (reserved) + * 001= eMMC V4.5 adapter is installed. + * 010= SD/MMC 3.3V adapter is installed. + * 011= eMMC V4.4 adapter is installed. + * 100= eMMC V5.0 adapter is installed. + * 101= MMC card/Legacy (3.3V) adapter is installed. + * 110= SDCard V2/V3 adapter installed. + * 111= no adapter is installed. + */ + return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != + QIXIS_ESDHC_NO_ADAPTER); +} + #endif diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig index e92b0d099da7c2f6139e2c21190d4ce1bd00e09c..dbcd1afcbad16014774cacf2330ad44ac6310312 100644 --- a/board/freescale/corenet_ds/Kconfig +++ b/board/freescale/corenet_ds/Kconfig @@ -9,8 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P3041DS" -source "board/freescale/common/Kconfig" - endif if TARGET_P4080DS @@ -24,8 +22,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P4080DS" -source "board/freescale/common/Kconfig" - endif if TARGET_P5040DS @@ -39,6 +35,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P5040DS" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index 3469064562bdfd818596f2f602340ca82a56ba79..9839eaceaf956ea5be3a11aa74ef6f26a0397cd4 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -62,7 +62,6 @@ #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef #define CONFIG_SYS_DDR_TIMING_4 0x00000001 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 0adf87bd42a115079c182fc482a845ba7d895c46..a148a9b998c5bb82546b22a536fc597c5c4dabf7 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -15,6 +15,4 @@ config IMX8MN_LOW_DRIVE_MODE config IMX_CONFIG default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig index 42625fd58889fe69213e9a4ce26b4ffb939921ae..cafa6329a40b77f92cd572b57d69fe1958f4b8a6 100644 --- a/board/freescale/imx8mp_evk/Kconfig +++ b/board/freescale/imx8mp_evk/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig index aed6ab25ce189142519e56f9f3acf5769cafb5a2..5f2413f8dbfcfd196db68a5bc31730508376c139 100644 --- a/board/freescale/imx8qm_mek/Kconfig +++ b/board/freescale/imx8qm_mek/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/freescale/imx8qm_mek/imximage.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig index b9aab3789ee4ad00fc0ff1c80caaff93eb68e6f7..6533b4d9535efb083451431101a919b56c3f17c8 100644 --- a/board/freescale/imx8qxp_mek/Kconfig +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/freescale/imx8qxp_mek/imximage.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig index 1e461ee1da71467e4148c8269718b096bac7c377..4637b969be6dcbcb45411d510742ed19f649fa87 100644 --- a/board/freescale/imx8ulp_evk/Kconfig +++ b/board/freescale/imx8ulp_evk/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8ulp_evk" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index 4ac69d711748acc21ae1c036d40cefe347cad034..75de782afc9c038851cac5c22f8d0b59cfc00cf2 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -89,7 +89,3 @@ config SYS_LS_PFE_ESBC_LENGTH hex "length of PFE Firmware HDR" default 0xc00 endif - -if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY -source "board/freescale/common/Kconfig" -endif diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index 59b1a876655f7198face150d7fe14623201a0c36..991ba6044db8b1013c68060a2b4af6e8ba33ad43 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -77,7 +77,4 @@ config PFE_SGMII_2500_PHY2_ADDR endif - -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index c4acea3ae2db3c7ba93bdf69306b32de42ca8eba..aa15f5a027e891d8aac8ed062c33a58f426a4935 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -63,8 +63,6 @@ config PFE_EMAC2_PHY_ADDR endif -source "board/freescale/common/Kconfig" - endif if TARGET_LS1012A2G5RDB @@ -119,6 +117,4 @@ config PFE_EMAC2_PHY_ADDR endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig index c6b16063a4a620af0321b000b69258837b73065b..4a12c1687fcede1eec51e52be85876fa9bad0eb5 100644 --- a/board/freescale/ls1021aiot/Kconfig +++ b/board/freescale/ls1021aiot/Kconfig @@ -12,6 +12,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021aiot" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig index 60b8472990daf1edaffdd01a83afce789597dc92..119b9550410c2664ab9d959eef8b7e1a040f729f 100644 --- a/board/freescale/ls1021aqds/Kconfig +++ b/board/freescale/ls1021aqds/Kconfig @@ -12,6 +12,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021aqds" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig index d999fa46900265f3db149e132ec46de479264636..aa42a06c663ff55cb762127901108158b778bc60 100644 --- a/board/freescale/ls1021atsn/Kconfig +++ b/board/freescale/ls1021atsn/Kconfig @@ -13,6 +13,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021atsn" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig index a4641cbca09b0ac0f7d572cd4b504d6ebf9ca6c6..bc50b8d96689bb7fb44c3f06058a5df45d6dfd9a 100644 --- a/board/freescale/ls1021atwr/Kconfig +++ b/board/freescale/ls1021atwr/Kconfig @@ -12,6 +12,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021atwr" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig index 40939816ad89a7051196e73ef09d39afd46b5a03..5c27f0f726dd019d3dbff281e1e405f87ecf317b 100644 --- a/board/freescale/ls1028a/Kconfig +++ b/board/freescale/ls1028a/Kconfig @@ -32,8 +32,6 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif if TARGET_LS1028ARDB @@ -58,6 +56,4 @@ config SYS_TEXT_BASE default 0x82000000 if TFABOOT default 0x20100000 -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 71a086ef675b9c0b6c9f3418201c292c24d3f8e6..1a7806fad77bc99f5e80243f38ad787d4198cde8 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019, 2021 NXP + * Copyright 2019-2022 NXP */ #include @@ -328,3 +328,8 @@ int checkboard(void) return 0; } #endif + +void *video_hw_init(void) +{ + return NULL; +} diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig index 182900efb7b28163d5b5bbccc765e4316bd2b229..4be445e8c8f815f6889312efbdaeb114acfe0e16 100644 --- a/board/freescale/ls1043aqds/Kconfig +++ b/board/freescale/ls1043aqds/Kconfig @@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index d66c7804b13e8ce80c8cc5b3df9c54f5b9191ec1..56502f9f9c634cfb5817d0fc7c5d89ffbe814c9d 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -27,6 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig index 6a4c3e92f7ba4475b19405eb7c707b96a98078fc..68329d78caf38d4a31ee9a9b4a46c5b1c8eff1b7 100644 --- a/board/freescale/ls1046afrwy/Kconfig +++ b/board/freescale/ls1046afrwy/Kconfig @@ -13,5 +13,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1046afrwy" -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig index 1616dcc683eb92b43dfd38c5b388aee1c1f42e08..adf325f4efd0d67113354b7204a7cd89b7c22cf9 100644 --- a/board/freescale/ls1046aqds/Kconfig +++ b/board/freescale/ls1046aqds/Kconfig @@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig index 4c31e0e88572a3206f141e8f4ee648669aabcee8..1fb391c991c6c0d9321202244f7093f3808b0a36 100644 --- a/board/freescale/ls1046ardb/Kconfig +++ b/board/freescale/ls1046ardb/Kconfig @@ -27,5 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig index 8bb828e3fd6685b5ae9e3509b034e99945bce292..f1a45236061bf2c72a93258a1f5b4d35a8d89e04 100644 --- a/board/freescale/ls1088a/Kconfig +++ b/board/freescale/ls1088a/Kconfig @@ -26,7 +26,6 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" endif if TARGET_LS1088ARDB @@ -57,5 +56,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig index 6b2b64581d606e2c25a0e2ab43caeac5f6c1f851..1036f33c61fa5817edda34ada87d6e17bc906b98 100644 --- a/board/freescale/ls2080aqds/Kconfig +++ b/board/freescale/ls2080aqds/Kconfig @@ -29,6 +29,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig index 678d58257303066f44d002327a129e4aa6ad5477..c8b0b94596b5bf652eed27cac89eb92063ec8f91 100644 --- a/board/freescale/ls2080ardb/Kconfig +++ b/board/freescale/ls2080ardb/Kconfig @@ -12,8 +12,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls2080ardb" -source "board/freescale/common/Kconfig" - if FSL_LS_PPA config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" @@ -30,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig index 7556f7dd21564712d24f857378fd000b2a4795f2..0e4b4158a7f1f44f073b3f9ab95204a613686775 100644 --- a/board/freescale/lx2160a/Kconfig +++ b/board/freescale/lx2160a/Kconfig @@ -12,7 +12,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2160ardb" -source "board/freescale/common/Kconfig" endif if TARGET_LX2160AQDS @@ -29,7 +28,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2160aqds" -source "board/freescale/common/Kconfig" endif if TARGET_LX2162AQDS @@ -46,5 +44,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2162aqds" -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 49d96d3fa2a97e9625950c119e492af2beea7289..a078643708f79d3f20d3fd8953200dced085d56b 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -356,27 +356,6 @@ int checkboard(void) } #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -/* - * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. - */ -u8 qixis_esdhc_detect_quirk(void) -{ - /* - * SDHC1 Card ID: - * Specifies the type of card installed in the SDHC1 adapter slot. - * 000= (reserved) - * 001= eMMC V4.5 adapter is installed. - * 010= SD/MMC 3.3V adapter is installed. - * 011= eMMC V4.4 adapter is installed. - * 100= eMMC V5.0 adapter is installed. - * 101= MMC card/Legacy (3.3V) adapter is installed. - * 110= SDCard V2/V3 adapter installed. - * 111= no adapter is installed. - */ - return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != - QIXIS_ESDHC_NO_ADAPTER); -} - static void esdhc_adapter_card_ident(void) { u8 card_id, val; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 2a4703579dabbec56ec423be73d0dbd5841fdbf3..85f5f0c034094a89988e32698c526bd15750f7de 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -93,11 +93,6 @@ int testdram(void) #ifdef CONFIG_IDE #include -int ide_preinit(void) -{ - return (0); -} - void ide_set_reset(int idereset) { atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig index 87f3374bf453619e20023d3be1769eee0d45d79b..bd9153bc0d74efd2e514c48440027bf79ed5bb2a 100644 --- a/board/freescale/mpc8548cds/Kconfig +++ b/board/freescale/mpc8548cds/Kconfig @@ -1,5 +1,8 @@ if TARGET_MPC8548CDS +config PCI1 + def_bool y + config SYS_BOARD default "mpc8548cds" diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig index 3adac4af1e3c9bc215666ddd38b936bd41fa4872..159bcc4f54d9208dfc3581f071509090e398b090 100644 --- a/board/freescale/p1010rdb/Kconfig +++ b/board/freescale/p1010rdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P1010RDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index 36b34c70aa8710950b79f8e95807572ac5aca0b0..a00806e6aaed71f81f3d15aa6a2143d7d2e6d8bf 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -5,10 +5,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif ifdef MINIMAL obj-y += spl_minimal.o diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 7eaa2047facb076501e2f91852fd0ddb1450ce31..88695002deb5bdaabcb89731ae4ecc36b03a6126 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -57,24 +57,24 @@ void board_init_f(ulong bootflag) /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); + relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE); } void board_init_r(gd_t *gd, ulong dest_addr) { /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; + gd = (gd_t *)CONFIG_VAL(GD_ADDR); struct bd_info *bd; memset(gd, 0, sizeof(gd_t)); - bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; arch_cpu_init(); get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); + mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR), + CONFIG_VAL(RELOC_MALLOC_SIZE)); gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 04faefe994d0a205e655b7f3f775370345b85ee0..7992666e930785ddab4135f393c1f097a532370e 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -72,8 +72,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) +#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index a7736d8332d4b51592544b998d2a5946be3c27c7..cbdb2507e8385a678ac17fc864f3467a1d2d3716 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -5,10 +5,12 @@ MINIMAL= ifdef CONFIG_SPL_BUILD +ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y endif endif +endif ifdef MINIMAL obj-y += spl_minimal.o diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index be803ddf9c66f2d81f11ea03486c1356680d5d1d..038e6736acecf724c4a1178d2fee1e2fc6e852ed 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -227,7 +227,7 @@ phys_size_t fixed_sdram(void) .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, - .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, + .ddr_data_init = 0xdeadbeef, /* Poison value */ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5f4d713ca5694966a22ec601e1d24e46896e8b7a..6bdfb356eeded9707ad79593067876eac30587ea 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -9,7 +9,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 6665aa4ba94e8c5c6e07820a82e816b46a435b8b..56bc355d2194ca3ab9ead62bb76e95c43ab4cd6d 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,6 +83,12 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00 +void board_reset(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + out_8(&cpld_data->system_rst, 1); +} + void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -154,7 +160,9 @@ int board_early_init_f(void) clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); +#endif board_gpio_init(); board_cpld_init(); @@ -178,7 +186,11 @@ int checkboard(void) int bus_num = CONFIG_SYS_SPD_BUS_NUM; /* FIXME: This should just use the model from the device tree or similar */ - printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", BOARD_NAME, +#ifdef BOARD_NAME + printf("Board: %s ", BOARD_NAME); +#endif + + printf("CPLD: V%d.%d PCBA: V%d.0\n", in_8(&cpld_data->cpld_rev_major) & 0x0F, in_8(&cpld_data->cpld_rev_minor) & 0x0F, in_8(&cpld_data->pcba_rev) & 0x0F); @@ -216,8 +228,11 @@ int checkboard(void) val = (in & io_config) | (out & (~io_config)); puts("rom_loc: "); - if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { + if (0) { +#ifdef __SW_BOOT_SD + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { puts("sd"); +#endif #ifdef __SW_BOOT_SD2 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { puts("sd"); diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec98d85eed424c0d7c59a9f3cae3cd..b60027ebd9ab9c56932d0ee0223704d3bfa9b143 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -63,24 +63,24 @@ void board_init_f(ulong bootflag) /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); + relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE); } void board_init_r(gd_t *gd, ulong dest_addr) { /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; + gd = (gd_t *)CONFIG_VAL(GD_ADDR); struct bd_info *bd; memset(gd, 0, sizeof(gd_t)); - bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; arch_cpu_init(); get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); + mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR), + CONFIG_VAL(RELOC_MALLOC_SIZE)); gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_ENV_SUPPORT diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 5931ec650bd87270feb27d00877ebc5ff127bf92..38843a96cbfb10e83a0eb1d5e819c0798f2ad931 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), #endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE @@ -77,8 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) +#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig index 7e187dde725500ff5ecf725a7dd858d798b5ab2e..78e11214a5b815d15f7e294129cdf000cf879f1b 100644 --- a/board/freescale/p2041rdb/Kconfig +++ b/board/freescale/p2041rdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P2041RDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 5bd2b9950602a114f622a5a1258350dff7c49cfb..2a84e9bdf556b7e6b1b40eb8b79ee722373b8101 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -229,7 +229,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +#if defined(CONFIG_HAS_FSL_DR_USB) fsl_fdt_fixup_dr_usb(blob, bd); #endif diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig index 6deeb248a3006facbd873e66a4e7de4d2ddb80d7..d538386d4344ef6da5349cdab12bca6d067b268d 100644 --- a/board/freescale/t102xrdb/Kconfig +++ b/board/freescale/t102xrdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T102xRDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig index e6e46fa126fbf7df6d1111516a53d7690211b448..e33d3173650ccd9d7bb9803fd63848bcdff10c0a 100644 --- a/board/freescale/t104xrdb/Kconfig +++ b/board/freescale/t104xrdb/Kconfig @@ -11,6 +11,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T104xRDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig index 58a31b65278e55aad5aeda0bc3ece0ee48381a48..c419a59dbb627ac293faa97f6e9a3afcac667091 100644 --- a/board/freescale/t208xqds/Kconfig +++ b/board/freescale/t208xqds/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config SRIO_PCIE_BOOT_SLAVE bool "Boot as a SRIO PCIe slave device" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index d4c061a5eabc48a27c216be4538be8d5b7a19fe2..35d884e6ccbd24b284f2602f0a68ca55eb3731aa 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config T2080RDB_REV_D bool "Support for T2080RDB revisions D and up" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig index 542e574fed142b341b05104785ab1f0f4c115981..d93e4532ac4a4db8bb6619c140dce231d4f81453 100644 --- a/board/freescale/t4rdb/Kconfig +++ b/board/freescale/t4rdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T4240RDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/friendlyarm/Kconfig b/board/friendlyarm/Kconfig index f8f9cfd879a8713eabb6642027912e55eccda519..fa04727a6a2b4c737ab1cee4999d0a21c772a406 100644 --- a/board/friendlyarm/Kconfig +++ b/board/friendlyarm/Kconfig @@ -11,6 +11,7 @@ config S5P4418_ONEWIRE config PWM_NX bool "PWM" + select PWM_S5P help This enables LCD-Backlight control via PWM. endchoice diff --git a/board/gateworks/gw_ventana/gw_ventana.env b/board/gateworks/gw_ventana/gw_ventana.env new file mode 100644 index 0000000000000000000000000000000000000000..9a316c74f21552893e775597572530b5ab19823b --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.env @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Gateworks Corporation + */ + +splashpos=m,m +splashimage=CONFIG_SYS_LOAD_ADDR +usb_pgood_delay=2000 +console=ttymxc1 +bootdevs=usb mmc sata flash +hwconfig=_UNKNOWN_ + +disk=0 +part=1 + +fdt_high=0xffffffff +fdt_addr=0x18000000 +initrd_high=0xffffffff +fixfdt=fdt addr ${fdt_addr} +bootdir=boot +loadfdt= + if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then + echo Loaded DTB from ${bootdir}/${fdt_file}; + run fixfdt; + elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then + echo Loaded DTB from ${bootdir}/${fdt_file1}; + run fixfdt; + elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then + echo Loaded DTB from ${bootdir}/${fdt_file2}; + run fixfdt; + fi + +fs=ext4 +script=6x_bootscript-ventana +loadscript= + if ${fsload} ${loadaddr} ${bootdir}/${script}; then + source ${loadaddr}; + fi + +uimage=uImage +mmc_root=mmcblk0p1 +mmc_boot= + setenv fsload "${fs}load mmc ${disk}:${part}"; + mmc dev ${disk} && mmc rescan && + setenv dtype mmc; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=/dev/${mmc_root} rootfstype=${fs} + rootwait rw ${video} ${extra}; + if run loadfdt; then + bootm ${loadaddr} - ${fdt_addr}; + else + bootm; + fi; + fi + +sata_boot= + setenv fsload "${fs}load sata ${disk}:${part}"; + sata init && + setenv dtype sata; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=/dev/sda1 rootfstype=${fs} + rootwait rw ${video} ${extra}; + if run loadfdt; then + bootm ${loadaddr} - ${fdt_addr}; + else + bootm; + fi; + fi + +usb_boot= + setenv fsload "${fs}load usb ${disk}:${part}"; + usb start && usb dev ${disk} && + setenv dtype usb; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=/dev/sda1 rootfstype=${fs} + rootwait rw ${video} ${extra}; + if run loadfdt; then + bootm ${loadaddr} - ${fdt_addr}; + else + bootm; + fi; + fi + +#ifdef CONFIG_SPI_FLASH +image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin +image_uboot=ventana/u-boot_spi.imx + +spi_koffset=0x90000 +spi_klen=0x200000 + +spi_updateuboot=echo Updating uboot from + ${serverip}:${image_uboot}...; + tftpboot ${loadaddr} ${image_uboot} && + sf probe && sf erase 0 80000 && + sf write ${loadaddr} 400 ${filesize} +spi_update=echo Updating OS from ${serverip}:${image_os} + to ${spi_koffset} ...; + tftp ${loadaddr} ${image_os} && + sf probe && + sf update ${loadaddr} ${spi_koffset} ${filesize} + +flash_boot= + if sf probe && + sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then + setenv bootargs console=${console},${baudrate} + root=/dev/mtdblock3 + rootfstype=squashfs,jffs2 + ${video} ${extra}; + bootm; + fi +#else +image_rootfs=openwrt-imx6-ventana-rootfs.ubi +nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; + tftp ${loadaddr} ${image_rootfs} && + nand erase.part rootfs && + nand write ${loadaddr} rootfs ${filesize} + +flash_boot= + setenv fsload 'ubifsload'; + ubi part rootfs; + if ubi check boot; then + ubifsmount ubi0:boot; + setenv root ubi0:rootfs ubi.mtd=2 + rootfstype=squashfs,ubifs; + setenv bootdir; + elif ubi check rootfs; then + ubifsmount ubi0:rootfs; + setenv root ubi0:rootfs ubi.mtd=2 + rootfstype=ubifs; + fi; + setenv dtype nand; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=${root} ${video} ${extra}; + if run loadfdt; then + ubifsumount; + bootm ${loadaddr} - ${fdt_addr}; + else + ubifsumount; bootm; + fi; + fi +#endif diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 6e6ce015f28a47c5c314053222561c2c5f500a7f..4c0feb4381c9f2e54bd3dd386166c4755ed4386c 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -87,33 +87,6 @@ static void spl_dram_init(int size) ddr_init(dram_timing); } -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -#ifdef CONFIG_IMX8MM -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -#elif CONFIG_IMX8MN -static const iomux_v3_cfg_t wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -#elif CONFIG_IMX8MP -static const iomux_v3_cfg_t wdog_pads[] = { - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -#endif - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - /* * Model specific PMIC adjustments necessary prior to DRAM init * @@ -253,8 +226,6 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ diff --git a/board/hpe/gxp/Kconfig b/board/hpe/gxp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5b154a3f6e560d2faf561c4dc511a9e5bf8db2e7 --- /dev/null +++ b/board/hpe/gxp/Kconfig @@ -0,0 +1,46 @@ +choice + prompt "SoC select" + +config TARGET_GXP + bool "GXP" + select DM + select SOC_GXP + imply CMD_DM + +config TARGET_GXP2 + bool "GXP2" + select DM + select SOC_GXP + select GXP_ECC + imply CMD_DM + +endchoice + +choice + prompt "GXP VROM size" + default GXP_VROM_64MB + optional + +config GXP_VROM_64MB + bool "64MB" + +config GXP_VROM_32MB + bool "32MB" +endchoice + +config GXP_ECC + bool "Enable memory ECC protected" + help + Use half of memory to enable ECC protected + +config SYS_BOARD + default "gxp" + +config SYS_VENDOR + default "hpe" + +config SYS_CONFIG_NAME + default "gxp" + +config SYS_TEXT_BASE + default 0x50000000 diff --git a/board/hpe/gxp/Makefile b/board/hpe/gxp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..775d6bf84976d9821e86874ce1b3afc675f4048c --- /dev/null +++ b/board/hpe/gxp/Makefile @@ -0,0 +1 @@ +obj-y += gxp_board.o diff --git a/board/hpe/gxp/gxp.env b/board/hpe/gxp/gxp.env new file mode 100644 index 0000000000000000000000000000000000000000..4760bf1663a72623482c0d8cdea7e74cd14b22c5 --- /dev/null +++ b/board/hpe/gxp/gxp.env @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +recover_file=openbmc-hpe-recovery-image.mtd +recover_cmd=usb start; mw.b 0xD100000D 0x40; + if fatload usb 0 0x50000000 $recover_file 0x4C0000 0x80000; then + setenv bootargs console=ttyS0,115200 recovery; + setenv force_recovery; + saveenv; + bootm 0x50000000; + else + while itest 0 < 1; do + mw.b 0xd1000005 0xc0; + sleep .1; + mw.b 0xd1000005 0x00; + sleep .1; + done; + fi; + reset; +spiboot=if itest.b *0xD10000B2 == 6; then + run recover_cmd; + fi; + if printenv force_recovery; then + run recover_cmd; + else + bootm 0xfc080000; + run recover_cmd; + fi; diff --git a/board/hpe/gxp/gxp_board.c b/board/hpe/gxp/gxp_board.c new file mode 100644 index 0000000000000000000000000000000000000000..d94d9b8a19e55bd31c31aeee80185d7a6bc170fb --- /dev/null +++ b/board/hpe/gxp/gxp_board.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GXP timer driver + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins + * Author: Jean-Marie Verdun + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ECHI_CMD 0xcefe0010 + +int board_init(void) +{ + writel(0x00080002, ECHI_CMD); + + return 0; +} + +int dram_init(void) +{ + if (IS_ENABLED(CONFIG_TARGET_GXP)) { + if (IS_ENABLED(CONFIG_GXP_ECC)) { + /* 0x0f800000 */ + gd->ram_size = SZ_128M + SZ_64M + SZ_32M + SZ_16M + SZ_8M; + } else { + /* 0x1f000000 */ + gd->ram_size = SZ_256M + SZ_128M + SZ_64M + SZ_32M + SZ_16M; + } + + if (IS_ENABLED(CONFIG_GXP_VROM_64MB)) { + if (IS_ENABLED(CONFIG_GXP_ECC)) { + /* 0x0c000000 */ + gd->ram_size = SZ_128M + SZ_64M; + } else { + /* 0x18000000 */ + gd->ram_size = SZ_256M + SZ_128M; + } + } + + if (IS_ENABLED(CONFIG_GXP_VROM_32MB)) { + if (IS_ENABLED(CONFIG_GXP_ECC)) { + /* 0x0e000000 */ + gd->ram_size = SZ_128M + SZ_64M + SZ_32M; + } else { + /* 0x1c000000 */ + gd->ram_size = SZ_256M + SZ_128M + SZ_64M; + } + } + } + + if (IS_ENABLED(CONFIG_TARGET_GXP2)) { + /* 0x1b200000 */ + gd->ram_size = SZ_256M + SZ_128M + SZ_32M + SZ_16M + SZ_2M; + if (IS_ENABLED(CONFIG_GXP_VROM_64MB)) { + /* 0x14000000 */ + gd->ram_size = SZ_256M + SZ_64M; + } + + if (IS_ENABLED(CONFIG_GXP_VROM_32MB)) { + /* 0x18000000 */ + gd->ram_size = SZ_256M + SZ_128M; + } + } + + return 0; +} + diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 863c07db47d5feb73bc27d0e2440f35adfac90e0..f22faee0ee42d1ed3dc3374bca2b192984033b3b 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -11,6 +11,9 @@ if VENDOR_KM menu "KM Board Setup" +config HUSH_INIT_VAR + def_bool y + config KM_PNVRAM hex "Pseudo RAM" default 0x80000 diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ecc8c786b6b8482a18da1d9ad51229955d2476b2..8a0b1758566358fdd588e27cea8b6aff0a701bec 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -102,8 +102,10 @@ int misc_init_r(void) int last_stage_init(void) { #if defined(CONFIG_TARGET_KMCOGE5NE) - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; + /* + * BFTIC3 on the local bus CS4 + */ + struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000; u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; if (dip_switch != 0) { diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 5a513722c5d5ffa9f5d09ddb0aa3ef47f7257863..09f81351dd4da19cdd97b6d15933c7e689fa5803 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -35,8 +35,6 @@ enum { #define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23) @@ -54,15 +52,6 @@ static iomux_v3_cfg_t const touch_gpio[] = { IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL) }; -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -231,19 +220,6 @@ void spl_board_init(void) printf("Failed to find clock node. Check device tree\n"); } -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; -} - static int power_init_board(void) { struct udevice *dev; @@ -278,12 +254,8 @@ void board_init_f(ulong dummy) init_uart_clk(2); - board_early_init_f(); - timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -293,6 +265,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* PMIC initialization */ diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 41426996ab9f75be4f89b3ecf8e557e1e6987cc1..315d9f99c71d3a93062edfc89bbdc76e8faebe14 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -54,6 +54,9 @@ static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { .ddr_cdr1 = 0x80040000, .ddr_cdr2 = 0x0000bc01, + + /* Erratum A-009942, set optimal CPO value */ + .debug[28] = 0x00700040, }; int fsl_initdram(void) @@ -66,11 +69,17 @@ int fsl_initdram(void) dram_size = 0x80000000; ddr_cfg_regs.cs[1].bnds = 0; ddr_cfg_regs.cs[1].config = 0; - ddr_cfg_regs.cs[1].config_2 = 0; break; case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL; break; + case GPPORCR1_MEM_8GB_CS0_1: + dram_size = 0x200000000ULL; + ddr_cfg_regs.cs[0].bnds = 0x000000ff; + ddr_cfg_regs.cs[0].config = 0x80044403; + ddr_cfg_regs.cs[1].bnds = 0x010001ff; + ddr_cfg_regs.cs[1].config = 0x80044403; + break; case GPPORCR1_MEM_512MB_CS0: dram_size = 0x20000000; fallthrough; /* for now */ @@ -80,7 +89,6 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_2: dram_size = 0x100000000ULL; fallthrough; /* for now */ - case GPPORCR1_MEM_8GB_CS0_1: case GPPORCR1_MEM_8GB_CS0_1_2_3: dram_size = 0x200000000ULL; fallthrough; /* for now */ diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c index 980ffef4cdfdc0d8a8f2a621601f06b80dfcef6a..83492601310152f263a96cd7a1d44145100c5389 100644 --- a/board/lego/ev3/legoev3.c +++ b/board/lego/ev3/legoev3.c @@ -27,6 +27,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -57,6 +58,8 @@ const int lpsc_size = ARRAY_SIZE(lpsc); */ static void setup_serial_number(void) { + struct udevice *idev, *ibus; + int ret; u32 offset; char serial_number[13]; u8 buf[6]; @@ -65,7 +68,15 @@ static void setup_serial_number(void) if (env_get("serial#")) return; - if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) { + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus); + if (ret) + return; + + ret = dm_i2c_probe(ibus, EEPROM_I2C_ADDR, 0, &idev); + if (ret) + return; + + if (dm_i2c_read(idev, EEPROM_REV_OFFSET, buf, 2)) { printf("\nEEPROM revision read failed!\n"); return; } @@ -83,7 +94,7 @@ static void setup_serial_number(void) /* EEPROM rev 3 has Bluetooth address where rev should be */ offset = (eeprom_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_BDADDR_OFFSET; - if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) { + if (dm_i2c_read(idev, offset, buf, 6)) { printf("\nEEPROM serial read failed!\n"); return; } diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index d54145ef995c6587ca1b58068ca62c753f2a6493..d87ab6d4497f8487056169b2eef40825b7676592 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -57,31 +57,6 @@ int board_fit_config_name_match(const char *name) return 0; } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) - -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -90,10 +65,6 @@ void board_init_f(ulong dummy) init_uart_clk(2); - board_early_init_f(); - - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -103,6 +74,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 19c486e551748dd2fbac01e0562c4446700d3b19..faed6fc3b76d7e95b7e24da0815efa0b57a9321b 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -89,31 +89,6 @@ int board_fit_config_name_match(const char *name) return 0; } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_pads[] = { - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -122,8 +97,6 @@ void board_init_f(ulong dummy) init_uart_clk(0); - board_early_init_f(); - ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.env b/board/qualcomm/dragonboard410c/dragonboard410c.env new file mode 100644 index 0000000000000000000000000000000000000000..9d9a575a0c3f7a4739e4fb77a980d742e10510f5 --- /dev/null +++ b/board/qualcomm/dragonboard410c/dragonboard410c.env @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Does what recovery does */ +#define REFLASH(file, partnum) \ +part start mmc 0 partnum start && \ +part size mmc 0 partnum size && \ +tftp $loadaddr file && \ +mmc write $loadaddr $start $size && + +reflash= +mmc dev 0 && +usb start && +dhcp && +tftp $loadaddr dragonboard/rescue/gpt_both0.bin && +mmc write $loadaddr 0 43 && +mmc rescan && +REFLASH(dragonboard/rescue/NON-HLOS.bin, 1) +REFLASH(dragonboard/rescue/sbl1.mbn, 2) +REFLASH(dragonboard/rescue/rpm.mbn, 3) +REFLASH(dragonboard/rescue/tz.mbn, 4) +REFLASH(dragonboard/rescue/hyp.mbn, 5) +REFLASH(dragonboard/rescue/sec.dat, 6) +REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7) +REFLASH(dragonboard/u-boot.img, 8) +usb stop && +echo Reflash completed + +loadaddr=0x81000000 +initrd_high=0xffffffffffffffff +linux_image=Image +kernel_addr_r=0x81000000 +fdtfile=qcom/apq8016-sbc.dtb +fdt_addr_r=0x83000000 +ramdisk_addr_r=0x84000000 +scriptaddr=0x90000000 +pxefile_addr_r=0x90100000 diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds index dcf8256cec38fb7423afb260a88a756207df735f..5251b59fbe768bfaab8f179e0b1007edb88c05e0 100644 --- a/board/qualcomm/dragonboard820c/u-boot.lds +++ b/board/qualcomm/dragonboard820c/u-boot.lds @@ -49,8 +49,8 @@ SECTIONS . = .; . = ALIGN(8); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(8); diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index b43242fd3f40678572b4adca340ff1942862e716..5320c1f2e0adbc0bd9a81acdfb24923111173f1d 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -112,10 +112,10 @@ int checkboard(void) } #endif -#ifdef CONFIG_S5P_PA_SYSRAM +#ifdef CONFIG_SMP_PEN_ADDR void smp_set_core_boot_addr(unsigned long addr, int corenr) { - writel(addr, CONFIG_S5P_PA_SYSRAM); + writel(addr, CONFIG_SMP_PEN_ADDR); /* make sure this write is really executed */ __asm__ volatile ("dsb\n"); diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index 5b32f7feb817ee8ff44d222610016f693477a123..73cd97a1b1de2cb78651b789b6ae0b383522b7bb 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -32,8 +32,8 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } >.sram . = ALIGN(4); diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index d06687620cf400edea4eba04ddb347874dd25fec..24bf355ef6ec3fe543dc06737fa2144f184f92d9 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -403,16 +403,6 @@ int exynos_early_init_f(void) return 0; } -void exynos_reset_lcd(void) -{ - gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); - gpio_direction_output(EXYNOS4_GPIO_Y45, 1); - udelay(10000); - gpio_direction_output(EXYNOS4_GPIO_Y45, 0); - udelay(10000); - gpio_direction_output(EXYNOS4_GPIO_Y45, 1); -} - int lcd_power(void) { #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */ @@ -460,16 +450,3 @@ int mipi_power(void) #endif return 0; } - -#ifdef CONFIG_LCD -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif -#ifdef CONFIG_S6E8AX0 - s6e8ax0_init(); - env_set("lcdinfo", "lcd=s6e8ax0"); -#endif -} -#endif diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index a03dc8738579f066ca622d9ac02e04c215bdfe9f..da7f0dc0229022a610d04d3cb96cd6510fa03ee6 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -302,39 +302,4 @@ int mipi_power(void) return 0; } -void exynos_lcd_power_on(void) -{ -#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */ - struct pmic *p = pmic_get("MAX77686_PMIC"); - - /* LCD_2.2V_EN: GPC0[1] */ - gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en"); - gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP); - gpio_direction_output(EXYNOS4X12_GPIO_C01, 1); - - /* LDO25 VCC_3.1V_LCD */ - pmic_probe(p); - max77686_set_ldo_voltage(p, 25, 3100000); - max77686_set_ldo_mode(p, 25, OPMODE_LPM); -#endif -} - -void exynos_reset_lcd(void) -{ - /* reset lcd */ - gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset"); - gpio_direction_output(EXYNOS4X12_GPIO_F21, 0); - udelay(10); - gpio_set_value(EXYNOS4X12_GPIO_F21, 1); -} - -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif -#ifdef CONFIG_S6E8AX0 - s6e8ax0_init(); -#endif -} #endif /* LCD */ diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 3764b5478b79ab07c03386414459f93f6d565261..1dde2f799b5e31549eefe5b9d3ec97b1ed7b74e4 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -267,98 +267,6 @@ static int init_pmic_lcd(void) return 0; } -void exynos_cfg_lcd_gpio(void) -{ - unsigned int i, f3_end = 4; - - for (i = 0; i < 8; i++) { - /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2)); - gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2)); - gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2)); - /* pull-up/down disable */ - gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE); - gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE); - gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE); - - /* drive strength to max (24bit) */ - gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X); - gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); - gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X); - gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW); - gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X); - gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); - } - - for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) { - /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - gpio_cfg_pin(i, S5P_GPIO_FUNC(2)); - /* pull-up/down disable */ - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - /* drive strength to max (24bit) */ - gpio_set_drv(i, S5P_GPIO_DRV_4X); - gpio_set_rate(i, S5P_GPIO_DRV_SLOW); - } - - /* gpio pad configuration for LCD reset. */ - gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); - gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT); -} - -int mipi_power(void) -{ - return 0; -} - -void exynos_reset_lcd(void) -{ - gpio_set_value(EXYNOS4_GPIO_Y45, 1); - udelay(10000); - gpio_set_value(EXYNOS4_GPIO_Y45, 0); - udelay(10000); - gpio_set_value(EXYNOS4_GPIO_Y45, 1); - udelay(100); -} - -void exynos_lcd_power_on(void) -{ - struct udevice *dev; - int ret; - u8 reg; - - ret = pmic_get("max8998-pmic", &dev); - if (ret) { - puts("Failed to get MAX8998!\n"); - return; - } - - reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3); - reg |= MAX8998_LDO17; - ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg); - if (ret) { - puts("MAX8998 LDO setting error\n"); - return; - } - - reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2); - reg |= MAX8998_LDO7; - ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg); - if (ret) { - puts("MAX8998 LDO setting error\n"); - return; - } -} - -void exynos_cfg_ldo(void) -{ - ld9040_cfg_ldo(); -} - -void exynos_enable_ldo(unsigned int onoff) -{ - ld9040_enable_ldo(onoff); -} - int exynos_init(void) { gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; @@ -390,18 +298,3 @@ int exynos_init(void) return 0; } - -#ifdef CONFIG_LCD -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif - - /* for LD9040. */ - vid->pclk_name = 1; /* MPLL */ - vid->sclk_div = 1; - - env_set("lcdinfo", "lcd=ld9040"); -} -#endif diff --git a/board/sandbox/sandbox.env b/board/sandbox/sandbox.env index b4c04635a48eed53ff4186a34f3779608fef0f59..a2c19702d64ddc7c38af56392ff34a0733496949 100644 --- a/board/sandbox/sandbox.env +++ b/board/sandbox/sandbox.env @@ -6,10 +6,6 @@ stdout=serial,vidconsole stderr=serial,vidconsole ethaddr=02:00:11:22:33:44 -eth2addr=02:00:11:22:33:48 -eth3addr=02:00:11:22:33:45 -eth4addr=02:00:11:22:33:48 -eth5addr=02:00:11:22:33:46 eth6addr=02:00:11:22:33:47 ipaddr=192.0.2.1 diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..131439fcfeac98591fe8c66c02daec327cc3dd59 --- /dev/null +++ b/board/siemens/common/Kconfig @@ -0,0 +1,2 @@ +config FACTORYSET + bool diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 3430a1ed017833bd434748d51df0a0fba88bedec..27aad4eaae3a6643ad76e1b19c2a29dd7fc4698b 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -59,7 +59,8 @@ int checkboard (void) f = get_board_sys_clk(); } else { src = "PCI_CLK"; - f = CONFIG_PCI_CLK_FREQ; + /* PCI is clocked by the external source at 33 MHz */ + f = 33000000; } printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); #else diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 5fb1be2fd3d36c805707b7e2803cb079429273d8..d52dce4f657e125d10bb296fa46dc67674bbe513 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -202,18 +202,4 @@ void stpmic1_init(u32 voltage_mv) STPMIC1_BUCKS_MRST_CR, STPMIC1_MRST_BUCK(STPMIC1_BUCK3), STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); - - /* Check if debug is enabled to program PMIC according to the bit */ - if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) { - log_info("Keep debug unit ON\n"); - - pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR, - STPMIC1_MRST_BUCK_DEBUG, - STPMIC1_MRST_BUCK_DEBUG); - - if (STPMIC1_MRST_LDO_DEBUG) - pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR, - STPMIC1_MRST_LDO_DEBUG, - STPMIC1_MRST_LDO_DEBUG); - } } diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 89e97aec2b6c833e12da24ae12796f75f1afbf24..6ab8f80fa45b6921c523f8c633ddcaa94a3eb8d2 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -11,3 +11,18 @@ config SYS_CONFIG_NAME source "board/st/common/Kconfig" endif + +if TARGET_ST_STM32MP13x + +config SYS_BOARD + default "stm32mp1" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp13_st_common" + +source "board/st/common/Kconfig" + +endif diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index 645119526985d34fc4774760e9372ee19d43c31f..d5a09cdc39fb3d0204016890923242f17849e6a7 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -3,10 +3,14 @@ M: Patrick Delaunay L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained +F: arch/arm/dts/stm32mp13* F: arch/arm/dts/stm32mp15* F: board/st/stm32mp1/ +F: configs/stm32mp13_defconfig F: configs/stm32mp15_defconfig F: configs/stm32mp15_basic_defconfig F: configs/stm32mp15_trusted_defconfig +F: include/configs/stm32mp13_common.h +F: include/configs/stm32mp13_st_common.h F: include/configs/stm32mp15_common.h F: include/configs/stm32mp15_st_common.h diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 07b1a63db7dc263446765697bf9c5e9c2514a9bc..9496890d164194c92787f07c643c0272f589f72b 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -82,11 +82,6 @@ #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - #define USB_LOW_THRESHOLD_UV 200000 #define USB_WARNING_LOW_THRESHOLD_UV 660000 #define USB_START_LOW_THRESHOLD_UV 1230000 @@ -116,8 +111,8 @@ int checkboard(void) mode = "basic"; } - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); log_info("Board: stm32mp1 in %s mode (%s)\n", mode, fdt_compat && fdt_compat_len ? fdt_compat : ""); @@ -554,8 +549,7 @@ static void sysconf_init(void) clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); } -/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ -static int dk2_i2c1_fix(void) +static int board_stm32mp15x_dk2_init(void) { ofnode node; struct gpio_desc hdmi, audio; @@ -564,6 +558,7 @@ static int dk2_i2c1_fix(void) if (!IS_ENABLED(CONFIG_DM_REGULATOR)) return -ENODEV; + /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39"); if (!ofnode_valid(node)) { log_debug("no hdmi-transmitter@39 ?\n"); @@ -611,7 +606,7 @@ error: return ret; } -static bool board_is_dk2(void) +static bool board_is_stm32mp15x_dk2(void) { if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && of_machine_is_compatible("st,stm32mp157c-dk2")) @@ -620,7 +615,7 @@ static bool board_is_dk2(void) return false; } -static bool board_is_ev1(void) +static bool board_is_stm32mp15x_ev1(void) { if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && (of_machine_is_compatible("st,stm32mp157a-ev1") || @@ -644,7 +639,7 @@ U_BOOT_DRIVER(goodix) = { .of_match = goodix_ids, }; -static void board_ev1_init(void) +static void board_stm32mp15x_ev1_init(void) { struct udevice *dev; @@ -657,11 +652,11 @@ int board_init(void) { board_key_check(); - if (board_is_ev1()) - board_ev1_init(); + if (board_is_stm32mp15x_ev1()) + board_stm32mp15x_ev1_init(); - if (board_is_dk2()) - dk2_i2c1_fix(); + if (board_is_stm32mp15x_dk2()) + board_stm32mp15x_dk2_init(); if (IS_ENABLED(CONFIG_DM_REGULATOR)) regulators_enable_boot_on(_DEBUG); @@ -690,8 +685,8 @@ int board_late_init(void) int buf_len; if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) { if (strncmp(fdt_compat, "st,", 3) != 0) { env_set("board_name", fdt_compat); diff --git a/board/synopsys/iot_devkit/u-boot.lds b/board/synopsys/iot_devkit/u-boot.lds index d08316870553fd44a63e68d2573c95090deb6396..e82e4987f6f2978082a93ea606f179f880c1459b 100644 --- a/board/synopsys/iot_devkit/u-boot.lds +++ b/board/synopsys/iot_devkit/u-boot.lds @@ -5,6 +5,7 @@ */ #include +#include MEMORY { ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE @@ -39,8 +40,8 @@ SECTIONS } > ROM . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); /* Mark RAM's LMA */ . = ALIGN(4); diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig index 4abcdb3aaf16b726fe1d3e13f6c3642dd99f9ec8..49d02744a9a03e5469493d37e381e3d0f7ee5b41 100644 --- a/board/sysam/stmark2/Kconfig +++ b/board/sysam/stmark2/Kconfig @@ -3,6 +3,9 @@ if TARGET_STMARK2 config CF_SBF def_bool y +config EXTRA_CLOCK + def_bool y + config SYS_INPUT_CLKSRC hex default 30000000 diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index 03c1d5f73b3dc81445554ec62e2af69fe03e6446..087dee8bb2edd403575f44c10600ab418fe5b9cf 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -72,8 +72,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..87fed44df17f06537a63da1068b24e16183b443f --- /dev/null +++ b/board/ti/am62x/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna + +choice + prompt "TI K3 AM62x based boards" + optional + +config TARGET_AM625_A53_EVM + bool "TI K3 based AM625 EVM running on A53" + select ARM64 + select SOC_K3_AM625 + +config TARGET_AM625_R5_EVM + bool "TI K3 based AM625 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM625 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_AM625_A53_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM625_R5_EVM + +config SYS_BOARD + default "am62x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62x_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..105e741995ed97752aec7a1a1b81f7922401e59d --- /dev/null +++ b/board/ti/am62x/MAINTAINERS @@ -0,0 +1,8 @@ +AM62x BOARD +M: Dave Gerlach +M: Tom Rini +S: Maintained +F: board/ti/am62x/ +F: include/configs/am62x_evm.h +F: configs/am62x_evm_r5_defconfig +F: configs/am62x_evm_a53_defconfig diff --git a/board/ti/am62x/Makefile b/board/ti/am62x/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f4c35edffaddcf2eccbf3f23045db3dce5430fbc --- /dev/null +++ b/board/ti/am62x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ +# Suman Anna +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c new file mode 100644 index 0000000000000000000000000000000000000000..d65ee1d69606d35decfa24a2ed84c1916ff5e9d5 --- /dev/null +++ b/board/ti/am62x/evm.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM62x platforms + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_K3_AM64_DDRSS) +static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); +} +#else +static void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} +#endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ +#if defined(CONFIG_K3_AM64_DDRSS) + fixup_ddr_driver_for_ecc(spl_image); +#else + fixup_memory_node(spl_image); +#endif +} +#endif diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig index d4ec759d7f9718ecfd2fb91731b009a4241ff50f..8036947e3450e3c0babcb46efcfb023984f23125 100644 --- a/board/ti/am64x/Kconfig +++ b/board/ti/am64x/Kconfig @@ -54,9 +54,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am64x_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index 47b41cd6afe422ee4bac7bcad21de7503cc4b3f9..16a7476d9c4bc94f782ab23fbf5d8a54af48ee35 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -53,9 +53,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am65x_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index de92eb0981f941efffb02ffa9a6acfb5757bde1d..ed34991377ee575df2e3a50e363c302dcbdf3a57 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -86,7 +86,7 @@ __weak void gpi2c_init(void) static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, u32 header, u32 size, uint8_t *ep) { - u32 hdr_read; + u32 hdr_read = 0xdeadbeef; int rc; #if CONFIG_IS_ENABLED(DM_I2C) @@ -103,21 +103,25 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, /* * Read the header first then only read the other contents. */ - rc = i2c_set_chip_offset_len(dev, 2); + rc = i2c_set_chip_offset_len(dev, 1); if (rc) return rc; - rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); - if (rc) - return rc; + /* + * Skip checking result here since this could be a valid i2c read fail + * on some boards that use 2 byte addressing. + * We must allow for fall through to check the data if 2 byte + * addressing works + */ + (void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); /* Corrupted data??? */ if (hdr_read != header) { /* * read the eeprom header using i2c again, but use only a - * 1 byte address (some legacy boards need this..) + * 2 byte address (some newer boards need this..) */ - rc = i2c_set_chip_offset_len(dev, 1); + rc = i2c_set_chip_offset_len(dev, 2); if (rc) return rc; @@ -142,19 +146,23 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, /* * Read the header first then only read the other contents. */ - byte = 2; + byte = 1; - rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); - if (rc) - return rc; + /* + * Skip checking result here since this could be a valid i2c read fail + * on some boards that use 2 byte addressing. + * We must allow for fall through to check the data if 2 byte + * addressing works + */ + (void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); /* Corrupted data??? */ if (hdr_read != header) { /* * read the eeprom header using i2c again, but use only a - * 1 byte address (some legacy boards need this..) + * 2 byte address (some newer boards need this..) */ - byte = 1; + byte = 2; rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); if (rc) @@ -434,6 +442,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, struct ti_am6_eeprom_record_board_id board_id; struct ti_am6_eeprom_record record; int rc; + int consecutive_bad_records = 0; /* Initialize with a known bad marker for i2c fails.. */ memset(ep, 0, sizeof(*ep)); @@ -470,7 +479,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, */ eeprom_addr = sizeof(board_id); - while (true) { + while (consecutive_bad_records < 10) { rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header, sizeof(record.header)); if (rc) @@ -506,6 +515,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, pr_err("%s: EEPROM parsing error!\n", __func__); return rc; } + consecutive_bad_records = 0; } else { /* * We may get here in case of larger records which @@ -513,6 +523,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, */ pr_err("%s: Ignoring record id %u\n", __func__, record.header.id); + consecutive_bad_records++; } eeprom_addr += record.header.len; diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 96434b3ba0f4587c12d4cce48a08b1c9679d8cd3..39b5c706a95a045ff6a9cea0da5207be253ac923 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -159,6 +159,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) int misc_init_r(void) { twl4030_power_init(); + twl4030_power_mmc_init(0); #if defined(CONFIG_SMC911X) setup_net_chip(); @@ -247,10 +248,3 @@ static void reset_net_chip(void) gpio_set_value(rst_gpio, 1); } #endif /* CONFIG_SMC911X */ - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif /* CONFIG_MMC */ diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index c28752a658b3d5c9490bdf55e4e50fcd176cfbc9..d19d30d59ef7c8337c797a85fa84c38e0204ea53 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -75,9 +75,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "j721e_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif @@ -108,9 +105,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "j721e_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index e6ff54c065dee39d1d619b420942458b33b6677d..5d090048ceb068c6c6eaba2505bc7361e6d60a4e 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -109,11 +109,12 @@ int board_fit_config_name_match(const char *name) static void __maybe_unused detect_enable_hyperflash(void *blob) { struct gpio_desc desc = {0}; + char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6"; - if (dm_gpio_lookup_name("6", &desc)) + if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc)) return; - if (dm_gpio_request(&desc, "6")) + if (dm_gpio_request(&desc, hypermux_sel_gpio)) return; if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN)) @@ -132,7 +133,8 @@ static void __maybe_unused detect_enable_hyperflash(void *blob) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM) +#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \ + defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM)) void spl_perform_fixups(struct spl_image_info *spl_image) { detect_enable_hyperflash(spl_image->fdt_addr); @@ -380,19 +382,25 @@ void configure_serdes_torrent(void) ret = uclass_get_device_by_driver(UCLASS_PHY, DM_DRIVER_GET(torrent_phy_provider), &dev); - if (ret) + if (ret) { printf("Torrent init failed:%d\n", ret); + return; + } serdes.dev = dev; serdes.id = 0; ret = generic_phy_init(&serdes); - if (ret) - printf("phy_init failed!!\n"); + if (ret) { + printf("phy_init failed!!: %d\n", ret); + return; + } ret = generic_phy_power_on(&serdes); - if (ret) - printf("phy_power_on failed !!\n"); + if (ret) { + printf("phy_power_on failed!!: %d\n", ret); + return; + } } void configure_serdes_sierra(void) @@ -408,21 +416,27 @@ void configure_serdes_sierra(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(sierra_phy_provider), &dev); - if (ret) + if (ret) { printf("Sierra init failed:%d\n", ret); + return; + } count = device_get_child_count(dev); for (i = 0; i < count; i++) { ret = device_get_child(dev, i, &link_dev); - if (ret) - printf("probe of sierra child node %d failed\n", i); + if (ret) { + printf("probe of sierra child node %d failed: %d\n", i, ret); + return; + } if (link_dev->driver->id == UCLASS_PHY) { link.dev = link_dev; link.id = link_count++; ret = generic_phy_power_on(&link); - if (ret) - printf("phy_power_on failed !!\n"); + if (ret) { + printf("phy_power_on failed!!: %d\n", ret); + return; + } } } } @@ -490,6 +504,41 @@ int board_late_init(void) } #endif +static int __maybe_unused detect_SW3_1_state(void) +{ + if (IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) { + struct gpio_desc desc = {0}; + int ret; + char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6"; + + ret = dm_gpio_lookup_name(hypermux_sel_gpio, &desc); + if (ret) { + printf("error getting GPIO lookup name: %d\n", ret); + return ret; + } + + ret = dm_gpio_request(&desc, hypermux_sel_gpio); + if (ret) { + printf("error requesting GPIO: %d\n", ret); + goto err_free_gpio; + } + + ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + if (ret) { + printf("error setting direction flag of GPIO: %d\n", ret); + goto err_free_gpio; + } + + ret = dm_gpio_get_value(&desc); + if (ret < 0) + printf("error getting value of GPIO: %d\n", ret); + +err_free_gpio: + dm_gpio_free(desc.dev, &desc); + return ret; + } +} + void spl_board_init(void) { #if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC) @@ -522,4 +571,18 @@ void spl_board_init(void) printf("ESM PMIC init failed: %d\n", ret); } #endif + if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) && + IS_ENABLED(CONFIG_HBMC_AM654)) { + struct udevice *dev; + int ret; + + ret = detect_SW3_1_state(); + if (ret == 1) { + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(hbmc_am654), + &dev); + if (ret) + debug("Failed to probe hyperflash\n"); + } + } } diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig index 2e115f14171d5aeb8816cf089bd989207a745903..6141798333c0eef244dd99b6aa7f4d8ff30d7515 100644 --- a/board/ti/j721s2/Kconfig +++ b/board/ti/j721s2/Kconfig @@ -55,9 +55,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "j721s2_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 6c8cf4592d1684e2123e34c9e2cb78b634cd6360..9305709a3c0dc12aebdcbde702772d008e41ffc6 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -159,6 +159,42 @@ const char * const toradex_display_adapters[] = { [159] = "Verdin DSI to LVDS Adapter", }; +const u32 toradex_ouis[] = { + [0] = 0x00142dUL, + [1] = 0x8c06cbUL, +}; + +static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr) +{ + int i; + u32 oui = ntohl(eth_addr->oui) >> 8; + u32 nic = ntohl(eth_addr->nic) >> 8; + + for (i = 0; i < ARRAY_SIZE(toradex_ouis); i++) { + if (toradex_ouis[i] == oui) + break; + } + + return (u32)((i << 24) + nic); +} + +void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr) +{ + u8 oui_index = tdx_serial >> 24; + u32 nic = tdx_serial & GENMASK(23, 0); + u32 oui; + + if (oui_index >= ARRAY_SIZE(toradex_ouis)) { + puts("Can't find OUI for this serial#\n"); + oui_index = 0; + } + + oui = toradex_ouis[oui_index]; + + eth_addr->oui = htonl(oui << 8); + eth_addr->nic = htonl(nic << 8); +} + #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) { @@ -331,8 +367,7 @@ int read_tdx_cfg_block(void) memcpy(&tdx_eth_addr, config_block + offset, 6); - /* NIC part of MAC address is serial number */ - tdx_serial = ntohl(tdx_eth_addr.nic) >> 8; + tdx_serial = get_serial_from_mac(&tdx_eth_addr); break; case TAG_HW: memcpy(&tdx_hw_tag, config_block + offset, 8); @@ -354,6 +389,18 @@ out: return ret; } +static int parse_assembly_string(char *string_to_parse, u16 *assembly) +{ + if (string_to_parse[3] >= 'A' && string_to_parse[3] <= 'Z') + *assembly = string_to_parse[3] - 'A'; + else if (string_to_parse[3] == '#') + *assembly = dectoul(&string_to_parse[4], NULL); + else + return -EINVAL; + + return 0; +} + static int get_cfgblock_interactive(void) { char message[CONFIG_SYS_CBSIZE]; @@ -362,6 +409,7 @@ static int get_cfgblock_interactive(void) char wb = 'n'; char mem8g = 'n'; int len = 0; + int ret = 0; /* Unknown module by default */ tdx_hw_tag.prodid = 0; @@ -545,13 +593,18 @@ static int get_cfgblock_interactive(void) } while (len < 4) { - sprintf(message, "Enter the module version (e.g. V1.1B): V"); + sprintf(message, "Enter the module version (e.g. V1.1B or V1.1#26): V"); len = cli_readline(message); } tdx_hw_tag.ver_major = console_buffer[0] - '0'; tdx_hw_tag.ver_minor = console_buffer[2] - '0'; - tdx_hw_tag.ver_assembly = console_buffer[3] - 'A'; + + ret = parse_assembly_string(console_buffer, &tdx_hw_tag.ver_assembly); + if (ret) { + printf("Parsing module version failed\n"); + return ret; + } while (len < 8) { sprintf(message, "Enter module serial number: "); @@ -754,6 +807,7 @@ static int get_cfgblock_carrier_interactive(void) { char message[CONFIG_SYS_CBSIZE]; int len; + int ret = 0; printf("Supported carrier boards:\n"); printf("CARRIER BOARD NAME\t\t [ID]\n"); @@ -767,13 +821,18 @@ static int get_cfgblock_carrier_interactive(void) tdx_car_hw_tag.prodid = dectoul(console_buffer, NULL); do { - sprintf(message, "Enter carrier board version (e.g. V1.1B): V"); + sprintf(message, "Enter carrier board version (e.g. V1.1B or V1.1#26): V"); len = cli_readline(message); } while (len < 4); tdx_car_hw_tag.ver_major = console_buffer[0] - '0'; tdx_car_hw_tag.ver_minor = console_buffer[2] - '0'; - tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A'; + + ret = parse_assembly_string(console_buffer, &tdx_car_hw_tag.ver_assembly); + if (ret) { + printf("Parsing module version failed\n"); + return ret; + } while (len < 8) { sprintf(message, "Enter carrier board serial number: "); @@ -950,8 +1009,7 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, } /* Convert serial number to MAC address (the storage format) */ - tdx_eth_addr.oui = htonl(0x00142dUL << 8); - tdx_eth_addr.nic = htonl(tdx_serial << 8); + get_mac_from_serial(tdx_serial, &tdx_eth_addr); /* Valid Tag */ write_tag(config_block, &offset, TAG_VALID, NULL, 0); diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 43e662e41da250a14bc046a948e7e82df80bdc7f..179069848639d88fbdf6a417d3f865dafc3b4462 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -114,4 +114,6 @@ int read_tdx_cfg_block_carrier(void); int try_migrate_tdx_cfg_block_carrier(void); +void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr); + #endif /* _TDX_CFG_BLOCK_H */ diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 9db4553e0f7bbffa1411d7a75e46b761aad7f26c..3798bf95378e5acd3aff82a29cc700ec1c9fbd6a 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -20,15 +20,17 @@ #include #include "tdx-common.h" -#define TORADEX_OUI 0x00142dUL +#define SERIAL_STR_LEN 8 +#define MODULE_VER_STR_LEN 4 // V1.1 +#define MODULE_REV_STR_LEN 3 // [A-Z] or #[26-99] #ifdef CONFIG_TDX_CFG_BLOCK -static char tdx_serial_str[9]; -static char tdx_board_rev_str[6]; +static char tdx_serial_str[SERIAL_STR_LEN + 1]; +static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA -static char tdx_car_serial_str[9]; -static char tdx_car_rev_str[6]; +static char tdx_car_serial_str[SERIAL_STR_LEN + 1]; +static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; static char *tdx_carrier_board_name; #endif @@ -79,21 +81,37 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif /* CONFIG_SERIAL_TAG */ +static const char *get_board_assembly(u16 ver_assembly) +{ + static char ver_name[MODULE_REV_STR_LEN + 1]; + + if (ver_assembly < 26) { + ver_name[0] = (char)ver_assembly + 'A'; + ver_name[1] = '\0'; + } else { + snprintf(ver_name, sizeof(ver_name), + "#%u", ver_assembly); + } + + return ver_name; +} + int show_board_info(void) { unsigned char ethaddr[6]; if (read_tdx_cfg_block()) { printf("MISSING TORADEX CONFIG BLOCK\n"); - tdx_eth_addr.oui = htonl(TORADEX_OUI << 8); - tdx_eth_addr.nic = htonl(tdx_serial << 8); + get_mac_from_serial(tdx_serial, &tdx_eth_addr); checkboard(); } else { - sprintf(tdx_serial_str, "%08u", tdx_serial); - sprintf(tdx_board_rev_str, "V%1d.%1d%c", - tdx_hw_tag.ver_major, - tdx_hw_tag.ver_minor, - (char)tdx_hw_tag.ver_assembly + 'A'); + snprintf(tdx_serial_str, sizeof(tdx_serial_str), + "%08u", tdx_serial); + snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str), + "V%1d.%1d%s", + tdx_hw_tag.ver_major, + tdx_hw_tag.ver_minor, + get_board_assembly(tdx_hw_tag.ver_assembly)); env_set("serial#", tdx_serial_str); @@ -109,12 +127,13 @@ int show_board_info(void) tdx_carrier_board_name = (char *) toradex_carrier_boards[tdx_car_hw_tag.prodid]; - sprintf(tdx_car_serial_str, "%08u", tdx_car_serial); - sprintf(tdx_car_rev_str, "V%1d.%1d%c", - tdx_car_hw_tag.ver_major, - tdx_car_hw_tag.ver_minor, - (char)tdx_car_hw_tag.ver_assembly + - 'A'); + snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str), + "%08u", tdx_car_serial); + snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str), + "V%1d.%1d%s", + tdx_car_hw_tag.ver_major, + tdx_car_hw_tag.ver_minor, + get_board_assembly(tdx_car_hw_tag.ver_assembly)); env_set("carrier_serial#", tdx_car_serial_str); printf("Carrier: Toradex %s %s, Serial# %s\n", @@ -170,7 +189,7 @@ int ft_common_board_setup(void *blob, struct bd_info *bd) if (tdx_hw_tag.ver_major) { char prod_id[5]; - sprintf(prod_id, "%04u", tdx_hw_tag.prodid); + snprintf(prod_id, sizeof(prod_id), "%04u", tdx_hw_tag.prodid); fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5); fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str, diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig index cfe6fc8c2c780de8891d7c8ed12a219d318a3f20..9a4003aa11b003125d5abc3c0da2de0143290789 100644 --- a/board/variscite/imx8mn_var_som/Kconfig +++ b/board/variscite/imx8mn_var_som/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c index 32703c5f0b3dc04c75e3e8efaaa0678f5d44e66a..41e70505774d7f2f807ff9cbdeae9f58a191f143 100644 --- a/board/variscite/imx8mn_var_som/spl.c +++ b/board/variscite/imx8mn_var_som/spl.c @@ -40,26 +40,8 @@ void spl_board_init(void) puts("Failed to find clock node. Check device tree\n"); } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static const iomux_v3_cfg_t uart_pads[] = { - IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static const iomux_v3_cfg_t wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - int board_early_init_f(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(3); return 0; @@ -78,14 +60,14 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } + preloader_console_init(); + /* DDR initialization */ spl_dram_init(); diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds index 315ba5b99a72a9ce90be3d955bc96b81b66750ac..cb2ee6769753effa73be8db354f13bd55f4bfda6 100644 --- a/board/vscom/baltos/u-boot.lds +++ b/board/vscom/baltos/u-boot.lds @@ -53,8 +53,8 @@ SECTIONS . = .; . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } . = ALIGN(4); diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile index 212028478c0e275089b7a9d1728871e7d15f6aa2..cdc3c9677432ef30452e7f4e241571b1834ac58d 100644 --- a/board/xilinx/common/Makefile +++ b/board/xilinx/common/Makefile @@ -5,6 +5,9 @@ # obj-y += board.o +ifndef CONFIG_ARCH_ZYNQ +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o +endif ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o endif diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 629a6ee036ffd036c6fb77846e32ddfa637063e7..5f2afb9def4eef68441198bfc161c4c6f52dae9d 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -485,31 +485,6 @@ int __maybe_unused board_fit_config_name_match(const char *name) return -1; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_ARCH_ZYNQ) -int print_cpuinfo(void) -{ - struct udevice *soc; - char name[SOC_MAX_STR_SIZE]; - int ret; - - ret = soc_get(&soc); - if (ret) { - printf("CPU: UNKNOWN\n"); - return 0; - } - - ret = soc_get_family(soc, name, SOC_MAX_STR_SIZE); - if (ret) - printf("CPU: %s\n", name); - - ret = soc_get_revision(soc, name, SOC_MAX_STR_SIZE); - if (ret) - printf("Silicon: %s\n", name); - - return 0; -} -#endif - #if CONFIG_IS_ENABLED(DTB_RESELECT) #define MAX_NAME_LENGTH 50 diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c new file mode 100644 index 0000000000000000000000000000000000000000..4a863d00dec8561e0dcc71c55d8011d37d01db5a --- /dev/null +++ b/board/xilinx/common/cpu-info.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2020 Xilinx, Inc. + * Michal Simek + */ + +#include +#include + +int print_cpuinfo(void) +{ + struct udevice *soc; + char name[SOC_MAX_STR_SIZE]; + int ret; + + ret = soc_get(&soc); + if (ret) { + printf("CPU: UNKNOWN\n"); + return 0; + } + + ret = soc_get_family(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("CPU: %s\n", name); + + ret = soc_get_revision(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("Silicon: %s\n", name); + + ret = soc_get_machine(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("Chip: %s\n", name); + + return 0; +} diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index 117b476f3f4133487f87c1748cf1d963bbf5be7d..dd5eacef52a8701761a14cbd42cc38c82fac696a 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -38,6 +38,14 @@ config XILINX_MICROBLAZE0_HW_VER string "Core version number" default "7.10.d" +config XILINX_MICROBLAZE0_FPGA_FAMILY + string "Targeted FPGA family" + default "virtex5" + help + This option contains info about the target FPGA architecture + (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is + implemented on. It corresponds to the C_FAMILY hdl parameter. + config XILINX_MICROBLAZE0_USR_EXCEP bool "MicroBlaze user exception support" default y @@ -63,4 +71,50 @@ config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Memory address location of the exception vector table. It is configurable via the C_BASE_VECTORS hdl parameter. +config XILINX_MICROBLAZE0_USE_WDC + bool "MicroBlaze wdc instruction support" + default y + help + Enable this option if the MicroBlaze processor is configured with + support for the "wdc" (Write to Data Cache) instruction. + +config SPL_XILINX_MICROBLAZE0_USE_WDC + bool + default XILINX_MICROBLAZE0_USE_WDC + +config XILINX_MICROBLAZE0_USE_WIC + bool "MicroBlaze wic instruction support" + default y + help + Enable this option if the MicroBlaze processor is configured with + support for the "wic" (Write to Instruction Cache) instruction. + +config SPL_XILINX_MICROBLAZE0_USE_WIC + bool + default XILINX_MICROBLAZE0_USE_WIC + +config XILINX_MICROBLAZE0_DCACHE_SIZE + int "Default data cache size" + default 32768 + help + This fallback size will be used when no dcache info can be found in + the device tree, or when the data cache is flushed very early in the + boot process, before device tree is available. + +config XILINX_MICROBLAZE0_ICACHE_SIZE + int "Default instruction cache size" + default 32768 + help + This fallback size will be used when no icache info can be found in + the device tree, or when the instruction cache is flushed very early + in the boot process, before device tree is available. + +config XILINX_MICROBLAZE0_PVR + bool "MicroBlaze PVR support" + help + Enables helper functions and macros needed to manipulate PVR + (Processor Version Register) data. Currently, only the microblaze + UCLASS_CPU driver makes use of this feature to retrieve CPU info at + runtime. + endif diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index a88f5bb177e2dd886bb1bfd04d2de113f46dc0f5..81663e0cd0ed14d123c84429dc053b6729ce2645 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -91,6 +91,23 @@ int board_early_init_r(void) return 0; } +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, + char *const argv[]) +{ + int ret = 0; + + if (current_el() > 1) { + smp_kick_all_cpus(); + dcache_disable(); + armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry, + ES_TO_AARCH64); + } else { + printf("FAIL: current EL is not above EL1\n"); + ret = EINVAL; + } + return ret; +} + static u8 versal_get_bootmode(void) { u8 bootmode; diff --git a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c index 40d9279378ba4240fb89cd159cf55c3cc32e9648..5ec327134b70196c7f86311db2c2795f5ec691f3 100644 --- a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c @@ -6,1866 +6,1858 @@ #include #include -static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate); - -static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, - int d_lock_cnt, int d_lfhf, int d_cp, int d_res); - -static unsigned long psu_pll_init_data(void) +static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (pllsel == 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (pllsel == 1) + mask_poll(0xFD4063E4, 0x00000010U); + if (pllsel == 2) + mask_poll(0xFD40A3E4, 0x00000010U); + if (pllsel == 3) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080); + Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); return 1; } -static unsigned long psu_clock_init_data(void) +static int serdes_bist_static_settings(u32 lane_active) { - psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); - psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); - psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); - psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + } - return 1; -} - -static unsigned long psu_ddr_init_data(void) -{ - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + } + if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } return 1; } -static unsigned long psu_mio_init_data(void) +static int serdes_bist_run(u32 lane_active) { - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); + } + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); return 1; } -static unsigned long psu_peripherals_pre_init_data(void) +static int serdes_bist_result(u32 lane_active) { - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; return 1; } -static unsigned long psu_peripherals_init_data(void) +static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol, + u32 lane3_rate, u32 lane2_protocol, + u32 lane2_rate, u32 lane1_protocol, + u32 lane1_rate, u32 lane0_protocol, + u32 lane0_rate, u32 gen2_calib) { - psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - return 1; -} + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); - psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); - psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; + } + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + } - serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0); - psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(pllsel, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, lane1_protocol, + lane1_rate, lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2); - return 1; -} + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8); -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD4023E4, 0x00000010U); + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && + prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && + currbistresult[loop] == 0 && itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + itercount - 1 - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64); - return 1; -} + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue; -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U); + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop]; - return 1; -} + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + } + } + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + } -static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); + } + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); + } + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); + } + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } return 1; } -static unsigned long psu_ddr_phybringup_data(void) +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - unsigned int regval = 0; - - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); - int cur_PLLCR0; - - cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL0PLLCR0; - - cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL1PLLCR0; - - cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL2PLLCR0; - - cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL3PLLCR0; - - cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL4PLLCR0; - - cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SLBPLLCR0; - - cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; - Xil_Out32(0xFD080068, 0x02120000); - Xil_Out32(0xFD081404, 0x02120000); - Xil_Out32(0xFD081444, 0x02120000); - Xil_Out32(0xFD081484, 0x02120000); - Xil_Out32(0xFD0814C4, 0x02120000); - Xil_Out32(0xFD081504, 0x02120000); - Xil_Out32(0xFD0817C4, 0x02120000); - int cur_div2; - - cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; - int cur_fbdiv; - - cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; - dpll_prog(1, 49, 63, 625, 3, 3, 2); - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset; - while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_retry--; + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - Xil_Out32(0xFD0800C0U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD070010U, 0x80000018U); - Xil_Out32(0xFD0701B0U, 0x00000005U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); - - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000331U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000B36U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0; - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000C56U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000E19U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); + } + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0; - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00001616U); - Xil_Out32(0xFD070010U, 0x80000018U); - Xil_Out32(0xFD070010U, 0x80000010U); - Xil_Out32(0xFD0701B0U, 0x00000005U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); - prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); - prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); - prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); - prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); - prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0); - Xil_Out32(0xFD080068, cur_PLLCR0); - Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); - Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); - Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); - Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); - Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); - Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0; - dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); - for (int tp = 0; tp < 2000; tp++) - regval = Xil_In32(0xFD070018); + serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0); - prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); - prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); + } + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0); - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - for (int tp = 0; tp < 2000; tp++) - regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); + } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); + } - prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); - prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); - prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); - prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); - prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); - for (int tp = 0; tp < 2000; tp++) - regval = Xil_In32(0xFD070018); + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); + } + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + } - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0014FE01); + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } + } - regval = Xil_In32(0xFD080030); - while (regval != 0x8000007E) - regval = Xil_In32(0xFD080030); + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37); - Xil_Out32(0xFD080200U, 0x000091C7U); - regval = Xil_In32(0xFD080030); - while (regval != 0x80008FFF) - regval = Xil_In32(0xFD080030); + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37); - Xil_Out32(0xFD080200U, 0x800091C7U); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); - prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); - prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); - prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); - Xil_Out32(0xFD070180U, 0x02160010U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); - for (int tp = 0; tp < 4000; tp++) - regval = Xil_In32(0xFD070018); + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37); - prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); - prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); - prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); - prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); - prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); - prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); - prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); - prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); - prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); - prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); - prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37); return 1; } -static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res) { - Xil_Out32(0xFD410098, 0x00000000); - Xil_Out32(0xFD401010, 0x00000040); - Xil_Out32(0xFD405010, 0x00000040); - Xil_Out32(0xFD409010, 0x00000040); - Xil_Out32(0xFD40D010, 0x00000040); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - Xil_Out32(0xFD410098, 0x00000004); - mask_delay(50); - if (lane0_rate == 1) - Xil_Out32(0xFD410098, 0x0000000E); - Xil_Out32(0xFD410098, 0x00000006); - if (lane0_rate == 1) { - Xil_Out32(0xFD40000C, 0x00000004); - Xil_Out32(0xFD40400C, 0x00000004); - Xil_Out32(0xFD40800C, 0x00000004); - Xil_Out32(0xFD40C00C, 0x00000004); - Xil_Out32(0xFD410098, 0x00000007); - mask_delay(400); - Xil_Out32(0xFD40000C, 0x0000000C); - Xil_Out32(0xFD40400C, 0x0000000C); - Xil_Out32(0xFD40800C, 0x0000000C); - Xil_Out32(0xFD40C00C, 0x0000000C); - mask_delay(15); - Xil_Out32(0xFD410098, 0x0000000F); - mask_delay(100); - } - if (pllsel == 0) - mask_poll(0xFD4023E4, 0x00000010U); - if (pllsel == 1) - mask_poll(0xFD4063E4, 0x00000010U); - if (pllsel == 2) - mask_poll(0xFD40A3E4, 0x00000010U); - if (pllsel == 3) - mask_poll(0xFD40E3E4, 0x00000010U); - mask_delay(50); - Xil_Out32(0xFD401010, 0x000000C0); - Xil_Out32(0xFD405010, 0x000000C0); - Xil_Out32(0xFD409010, 0x000000C0); - Xil_Out32(0xFD40D010, 0x000000C0); - Xil_Out32(0xFD401010, 0x00000080); - Xil_Out32(0xFD405010, 0x00000080); - Xil_Out32(0xFD409010, 0x00000080); - Xil_Out32(0xFD40D010, 0x00000080); + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; - Xil_Out32(0xFD402084, 0x000000C0); - Xil_Out32(0xFD406084, 0x000000C0); - Xil_Out32(0xFD40A084, 0x000000C0); - Xil_Out32(0xFD40E084, 0x000000C0); - mask_delay(50); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - mask_delay(50); - Xil_Out32(0xFD401010, 0x00000000); - Xil_Out32(0xFD405010, 0x00000000); - Xil_Out32(0xFD409010, 0x00000000); - Xil_Out32(0xFD40D010, 0x00000000); - Xil_Out32(0xFD402084, 0x00000000); - Xil_Out32(0xFD406084, 0x00000000); - Xil_Out32(0xFD40A084, 0x00000000); - Xil_Out32(0xFD40E084, 0x00000000); - mask_delay(500); - return 1; -} + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); + pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); -static int serdes_bist_static_settings(u32 lane_active) -{ - if (lane_active == 0) { - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - Xil_Out32(0xFD403068, 0x1); - Xil_Out32(0xFD40306C, 0x1); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403008, 0x0); - Xil_Out32(0xFD40300C, 0xF4); - Xil_Out32(0xFD403010, 0x0); - Xil_Out32(0xFD403014, 0x0); - Xil_Out32(0xFD403018, 0x00); - Xil_Out32(0xFD40301C, 0xFB); - Xil_Out32(0xFD403020, 0xFF); - Xil_Out32(0xFD403024, 0x0); - Xil_Out32(0xFD403028, 0x00); - Xil_Out32(0xFD40302C, 0x00); - Xil_Out32(0xFD403030, 0x4A); - Xil_Out32(0xFD403034, 0x4A); - Xil_Out32(0xFD403038, 0x4A); - Xil_Out32(0xFD40303C, 0x4A); - Xil_Out32(0xFD403040, 0x0); - Xil_Out32(0xFD403044, 0x14); - Xil_Out32(0xFD403048, 0x02); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - } - if (lane_active == 1) { - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - Xil_Out32(0xFD407068, 0x1); - Xil_Out32(0xFD40706C, 0x1); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407008, 0x0); - Xil_Out32(0xFD40700C, 0xF4); - Xil_Out32(0xFD407010, 0x0); - Xil_Out32(0xFD407014, 0x0); - Xil_Out32(0xFD407018, 0x00); - Xil_Out32(0xFD40701C, 0xFB); - Xil_Out32(0xFD407020, 0xFF); - Xil_Out32(0xFD407024, 0x0); - Xil_Out32(0xFD407028, 0x00); - Xil_Out32(0xFD40702C, 0x00); - Xil_Out32(0xFD407030, 0x4A); - Xil_Out32(0xFD407034, 0x4A); - Xil_Out32(0xFD407038, 0x4A); - Xil_Out32(0xFD40703C, 0x4A); - Xil_Out32(0xFD407040, 0x0); - Xil_Out32(0xFD407044, 0x14); - Xil_Out32(0xFD407048, 0x02); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - } + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); - if (lane_active == 2) { - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40B068, 0x1); - Xil_Out32(0xFD40B06C, 0x1); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B008, 0x0); - Xil_Out32(0xFD40B00C, 0xF4); - Xil_Out32(0xFD40B010, 0x0); - Xil_Out32(0xFD40B014, 0x0); - Xil_Out32(0xFD40B018, 0x00); - Xil_Out32(0xFD40B01C, 0xFB); - Xil_Out32(0xFD40B020, 0xFF); - Xil_Out32(0xFD40B024, 0x0); - Xil_Out32(0xFD40B028, 0x00); - Xil_Out32(0xFD40B02C, 0x00); - Xil_Out32(0xFD40B030, 0x4A); - Xil_Out32(0xFD40B034, 0x4A); - Xil_Out32(0xFD40B038, 0x4A); - Xil_Out32(0xFD40B03C, 0x4A); - Xil_Out32(0xFD40B040, 0x0); - Xil_Out32(0xFD40B044, 0x14); - Xil_Out32(0xFD40B048, 0x02); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - } + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); + pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); + pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); + pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); + pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_status_regval = 0x00000000; + while ((pll_status_regval & 0x00000002U) != 0x00000002U) + pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); - if (lane_active == 3) { - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40F068, 0x1); - Xil_Out32(0xFD40F06C, 0x1); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F008, 0x0); - Xil_Out32(0xFD40F00C, 0xF4); - Xil_Out32(0xFD40F010, 0x0); - Xil_Out32(0xFD40F014, 0x0); - Xil_Out32(0xFD40F018, 0x00); - Xil_Out32(0xFD40F01C, 0xFB); - Xil_Out32(0xFD40F020, 0xFF); - Xil_Out32(0xFD40F024, 0x0); - Xil_Out32(0xFD40F028, 0x00); - Xil_Out32(0xFD40F02C, 0x00); - Xil_Out32(0xFD40F030, 0x4A); - Xil_Out32(0xFD40F034, 0x4A); - Xil_Out32(0xFD40F038, 0x4A); - Xil_Out32(0xFD40F03C, 0x4A); - Xil_Out32(0xFD40F040, 0x0); - Xil_Out32(0xFD40F044, 0x14); - Xil_Out32(0xFD40F048, 0x02); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - } return 1; } -static int serdes_bist_run(u32 lane_active) +static unsigned long psu_clock_init_data(void) { - if (lane_active == 0) { - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); - } - if (lane_active == 1) { - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); - } - if (lane_active == 2) { - psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); - } - if (lane_active == 3) { - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); - } - mask_delay(100); + psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); + psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + return 1; } -static int serdes_bist_result(u32 lane_active) +static unsigned long psu_ddr_init_data(void) { - u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - if (lane_active == 0) { - pkt_cnt_l0 = Xil_In32(0xFD40304C); - pkt_cnt_h0 = Xil_In32(0xFD403050); - err_cnt_l0 = Xil_In32(0xFD403054); - err_cnt_h0 = Xil_In32(0xFD403058); - } - if (lane_active == 1) { - pkt_cnt_l0 = Xil_In32(0xFD40704C); - pkt_cnt_h0 = Xil_In32(0xFD407050); - err_cnt_l0 = Xil_In32(0xFD407054); - err_cnt_h0 = Xil_In32(0xFD407058); - } - if (lane_active == 2) { - pkt_cnt_l0 = Xil_In32(0xFD40B04C); - pkt_cnt_h0 = Xil_In32(0xFD40B050); - err_cnt_l0 = Xil_In32(0xFD40B054); - err_cnt_h0 = Xil_In32(0xFD40B058); - } - if (lane_active == 3) { - pkt_cnt_l0 = Xil_In32(0xFD40F04C); - pkt_cnt_h0 = Xil_In32(0xFD40F050); - err_cnt_l0 = Xil_In32(0xFD40F054); - err_cnt_h0 = Xil_In32(0xFD40F058); - } - if (lane_active == 0) - Xil_Out32(0xFD403004, 0x0); - if (lane_active == 1) - Xil_Out32(0xFD407004, 0x0); - if (lane_active == 2) - Xil_Out32(0xFD40B004, 0x0); - if (lane_active == 3) - Xil_Out32(0xFD40F004, 0x0); - if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || - (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) - return 0; return 1; } -static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol, - u32 lane3_rate, u32 lane2_protocol, - u32 lane2_rate, u32 lane1_protocol, - u32 lane1_rate, u32 lane0_protocol, - u32 lane0_rate, u32 gen2_calib) +static unsigned long psu_ddr_qos_init_data(void) { - u64 tempbistresult; - u32 currbistresult[4]; - u32 prevbistresult[4]; - u32 itercount = 0; - u32 ill12_val[4], ill1_val[4]; - u32 loop = 0; - u32 iterresult[8]; - u32 meancount[4]; - u32 bistpasscount[4]; - u32 meancountalt[4]; - u32 meancountalt_bistpasscount[4]; - u32 lane0_active; - u32 lane1_active; - u32 lane2_active; - u32 lane3_active; - - lane0_active = (lane0_protocol == 1); - lane1_active = (lane1_protocol == 1); - lane2_active = (lane2_protocol == 1); - lane3_active = (lane3_protocol == 1); - for (loop = 0; loop <= 3; loop++) { - iterresult[loop] = 0; - iterresult[loop + 4] = 0; - meancountalt[loop] = 0; - meancountalt_bistpasscount[loop] = 0; - meancount[loop] = 0; - prevbistresult[loop] = 0; - bistpasscount[loop] = 0; - } - itercount = 0; - if (lane0_active) - serdes_bist_static_settings(0); - if (lane1_active) - serdes_bist_static_settings(1); - if (lane2_active) - serdes_bist_static_settings(2); - if (lane3_active) - serdes_bist_static_settings(3); - do { - if (gen2_calib != 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x04 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane1_active == 1) - ill1_val[1] = ((0x04 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane2_active == 1) - ill1_val[2] = ((0x04 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane3_active == 1) - ill1_val[3] = ((0x04 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, - ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x104 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane1_active == 1) - ill1_val[1] = ((0x104 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane2_active == 1) - ill1_val[2] = ((0x104 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane3_active == 1) - ill1_val[3] = ((0x104 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, - ill12_val[3]); - } + return 1; +} - if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); - if (lane0_active == 1) - currbistresult[0] = 0; - if (lane1_active == 1) - currbistresult[1] = 0; - if (lane2_active == 1) - currbistresult[2] = 0; - if (lane3_active == 1) - currbistresult[3] = 0; - serdes_rst_seq(pllsel, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, lane1_protocol, - lane1_rate, lane0_protocol, lane0_rate); - if (lane3_active == 1) - serdes_bist_run(3); - if (lane2_active == 1) - serdes_bist_run(2); - if (lane1_active == 1) - serdes_bist_run(1); - if (lane0_active == 1) - serdes_bist_run(0); - tempbistresult = 0; - if (lane3_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(3); - tempbistresult = tempbistresult << 1; - if (lane2_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(2); - tempbistresult = tempbistresult << 1; - if (lane1_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(1); - tempbistresult = tempbistresult << 1; - if (lane0_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(0); - Xil_Out32(0xFD410098, 0x0); - Xil_Out32(0xFD410098, 0x2); +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - if (itercount < 32) { - iterresult[0] = - ((iterresult[0] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[1] = - ((iterresult[1] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[2] = - ((iterresult[2] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[3] = - ((iterresult[3] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } else { - iterresult[4] = - ((iterresult[4] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[5] = - ((iterresult[5] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[6] = - ((iterresult[6] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[7] = - ((iterresult[7] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } - currbistresult[0] = - currbistresult[0] | ((tempbistresult & 0x1) == 1); - currbistresult[1] = - currbistresult[1] | ((tempbistresult & 0x2) == 0x2); - currbistresult[2] = - currbistresult[2] | ((tempbistresult & 0x4) == 0x4); - currbistresult[3] = - currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + return 1; +} - for (loop = 0; loop <= 3; loop++) { - if (currbistresult[loop] == 1 && - prevbistresult[loop] == 1) - bistpasscount[loop] = bistpasscount[loop] + 1; - if (bistpasscount[loop] < 4 && - currbistresult[loop] == 0 && itercount > 2) { - if (meancountalt_bistpasscount[loop] < - bistpasscount[loop]) { - meancountalt_bistpasscount[loop] = - bistpasscount[loop]; - meancountalt[loop] = - ((itercount - 1) - - ((bistpasscount[loop] + 1) / 2)); - } - bistpasscount[loop] = 0; - } - if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && - (currbistresult[loop] == 0 || itercount == 63) && - prevbistresult[loop] == 1) - meancount[loop] = - itercount - 1 - - ((bistpasscount[loop] + 1) / 2); - prevbistresult[loop] = currbistresult[loop]; - } - } while (++itercount < 64); +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); - for (loop = 0; loop <= 3; loop++) { - if (lane0_active == 0 && loop == 0) - continue; - if (lane1_active == 0 && loop == 1) - continue; - if (lane2_active == 0 && loop == 2) - continue; - if (lane3_active == 0 && loop == 3) - continue; + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + return 1; +} - if (meancount[loop] == 0) - meancount[loop] = meancountalt[loop]; +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - if (gen2_calib != 1) { - ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x04 + meancount[loop] * 8) >= - 0x100) ? 0x10 : 0x00; - } - if (gen2_calib == 1) { - ill1_val[loop] = - ((0x104 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x104 + meancount[loop] * 8) >= - 0x200) ? 0x02 : 0x01; - } - } - if (gen2_calib != 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); - } + serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0); + psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4023E4, 0x00000010U); - Xil_Out32(0xFD410098, 0); - if (lane0_active == 1) { - Xil_Out32(0xFD403004, 0); - Xil_Out32(0xFD403008, 0); - Xil_Out32(0xFD40300C, 0); - Xil_Out32(0xFD403010, 0); - Xil_Out32(0xFD403014, 0); - Xil_Out32(0xFD403018, 0); - Xil_Out32(0xFD40301C, 0); - Xil_Out32(0xFD403020, 0); - Xil_Out32(0xFD403024, 0); - Xil_Out32(0xFD403028, 0); - Xil_Out32(0xFD40302C, 0); - Xil_Out32(0xFD403030, 0); - Xil_Out32(0xFD403034, 0); - Xil_Out32(0xFD403038, 0); - Xil_Out32(0xFD40303C, 0); - Xil_Out32(0xFD403040, 0); - Xil_Out32(0xFD403044, 0); - Xil_Out32(0xFD403048, 0); - Xil_Out32(0xFD40304C, 0); - Xil_Out32(0xFD403050, 0); - Xil_Out32(0xFD403054, 0); - Xil_Out32(0xFD403058, 0); - Xil_Out32(0xFD403068, 1); - Xil_Out32(0xFD40306C, 0); - Xil_Out32(0xFD4010AC, 0); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); - } - if (lane1_active == 1) { - Xil_Out32(0xFD407004, 0); - Xil_Out32(0xFD407008, 0); - Xil_Out32(0xFD40700C, 0); - Xil_Out32(0xFD407010, 0); - Xil_Out32(0xFD407014, 0); - Xil_Out32(0xFD407018, 0); - Xil_Out32(0xFD40701C, 0); - Xil_Out32(0xFD407020, 0); - Xil_Out32(0xFD407024, 0); - Xil_Out32(0xFD407028, 0); - Xil_Out32(0xFD40702C, 0); - Xil_Out32(0xFD407030, 0); - Xil_Out32(0xFD407034, 0); - Xil_Out32(0xFD407038, 0); - Xil_Out32(0xFD40703C, 0); - Xil_Out32(0xFD407040, 0); - Xil_Out32(0xFD407044, 0); - Xil_Out32(0xFD407048, 0); - Xil_Out32(0xFD40704C, 0); - Xil_Out32(0xFD407050, 0); - Xil_Out32(0xFD407054, 0); - Xil_Out32(0xFD407058, 0); - Xil_Out32(0xFD407068, 1); - Xil_Out32(0xFD40706C, 0); - Xil_Out32(0xFD4050AC, 0); - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); - } - if (lane2_active == 1) { - Xil_Out32(0xFD40B004, 0); - Xil_Out32(0xFD40B008, 0); - Xil_Out32(0xFD40B00C, 0); - Xil_Out32(0xFD40B010, 0); - Xil_Out32(0xFD40B014, 0); - Xil_Out32(0xFD40B018, 0); - Xil_Out32(0xFD40B01C, 0); - Xil_Out32(0xFD40B020, 0); - Xil_Out32(0xFD40B024, 0); - Xil_Out32(0xFD40B028, 0); - Xil_Out32(0xFD40B02C, 0); - Xil_Out32(0xFD40B030, 0); - Xil_Out32(0xFD40B034, 0); - Xil_Out32(0xFD40B038, 0); - Xil_Out32(0xFD40B03C, 0); - Xil_Out32(0xFD40B040, 0); - Xil_Out32(0xFD40B044, 0); - Xil_Out32(0xFD40B048, 0); - Xil_Out32(0xFD40B04C, 0); - Xil_Out32(0xFD40B050, 0); - Xil_Out32(0xFD40B054, 0); - Xil_Out32(0xFD40B058, 0); - Xil_Out32(0xFD40B068, 1); - Xil_Out32(0xFD40B06C, 0); - Xil_Out32(0xFD4090AC, 0); - psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); - } - if (lane3_active == 1) { - Xil_Out32(0xFD40F004, 0); - Xil_Out32(0xFD40F008, 0); - Xil_Out32(0xFD40F00C, 0); - Xil_Out32(0xFD40F010, 0); - Xil_Out32(0xFD40F014, 0); - Xil_Out32(0xFD40F018, 0); - Xil_Out32(0xFD40F01C, 0); - Xil_Out32(0xFD40F020, 0); - Xil_Out32(0xFD40F024, 0); - Xil_Out32(0xFD40F028, 0); - Xil_Out32(0xFD40F02C, 0); - Xil_Out32(0xFD40F030, 0); - Xil_Out32(0xFD40F034, 0); - Xil_Out32(0xFD40F038, 0); - Xil_Out32(0xFD40F03C, 0); - Xil_Out32(0xFD40F040, 0); - Xil_Out32(0xFD40F044, 0); - Xil_Out32(0xFD40F048, 0); - Xil_Out32(0xFD40F04C, 0); - Xil_Out32(0xFD40F050, 0); - Xil_Out32(0xFD40F054, 0); - Xil_Out32(0xFD40F058, 0); - Xil_Out32(0xFD40F068, 1); - Xil_Out32(0xFD40F06C, 0); - Xil_Out32(0xFD40D0AC, 0); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); - } return 1; } -static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static unsigned long psu_resetin_init_data(void) { - unsigned int rdata = 0; - unsigned int sata_gen2 = 1; - unsigned int temp_ill12 = 0; - unsigned int temp_PLL_REF_SEL_OFFSET; - unsigned int temp_TM_IQ_ILL1; - unsigned int temp_TM_E_ILL1; - unsigned int temp_tx_dig_tm_61; - unsigned int temp_tm_dig_6; - unsigned int temp_pll_fbdiv_frac_3_msb_offset; + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U); - if (lane0_protocol == 2 || lane0_protocol == 1) { - Xil_Out32(0xFD401910, 0xF3); - Xil_Out32(0xFD40193C, 0xF3); - Xil_Out32(0xFD401914, 0xF3); - Xil_Out32(0xFD401940, 0xF3); - } - if (lane1_protocol == 2 || lane1_protocol == 1) { - Xil_Out32(0xFD405910, 0xF3); - Xil_Out32(0xFD40593C, 0xF3); - Xil_Out32(0xFD405914, 0xF3); - Xil_Out32(0xFD405940, 0xF3); - } - if (lane2_protocol == 2 || lane2_protocol == 1) { - Xil_Out32(0xFD409910, 0xF3); - Xil_Out32(0xFD40993C, 0xF3); - Xil_Out32(0xFD409914, 0xF3); - Xil_Out32(0xFD409940, 0xF3); - } - if (lane3_protocol == 2 || lane3_protocol == 1) { - Xil_Out32(0xFD40D910, 0xF3); - Xil_Out32(0xFD40D93C, 0xF3); - Xil_Out32(0xFD40D914, 0xF3); - Xil_Out32(0xFD40D940, 0xF3); - } + return 1; +} - if (sata_gen2 == 1) { - if (lane0_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); - Xil_Out32(0xFD402360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); - temp_TM_E_ILL1 = Xil_In32(0xFD401924); - Xil_Out32(0xFD4018F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); - temp_tm_dig_6 = Xil_In32(0xFD40106C); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD401990) & 0xF0; +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); - serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0); + return 1; +} - Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40106C, temp_tm_dig_6); - Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); - Xil_Out32(0xFD401990, temp_ill12); - Xil_Out32(0xFD401924, temp_TM_E_ILL1); - } - if (lane1_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); - Xil_Out32(0xFD406360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); - psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); - temp_TM_E_ILL1 = Xil_In32(0xFD405924); - Xil_Out32(0xFD4058F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); - temp_tm_dig_6 = Xil_In32(0xFD40506C); - psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD405990) & 0xF0; +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; - serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + int cur_PLLCR0; - Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40506C, temp_tm_dig_6); - Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); - Xil_Out32(0xFD405990, temp_ill12); - Xil_Out32(0xFD405924, temp_TM_E_ILL1); - } - if (lane2_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); - Xil_Out32(0xFD40A360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); - psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); - temp_TM_E_ILL1 = Xil_In32(0xFD409924); - Xil_Out32(0xFD4098F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); - temp_tm_dig_6 = Xil_In32(0xFD40906C); - psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD409990) & 0xF0; + cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL0PLLCR0; - serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0); + cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL1PLLCR0; - Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40906C, temp_tm_dig_6); - Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); - Xil_Out32(0xFD409990, temp_ill12); - Xil_Out32(0xFD409924, temp_TM_E_ILL1); - } - if (lane3_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); - Xil_Out32(0xFD40E360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); - temp_TM_E_ILL1 = Xil_In32(0xFD40D924); - Xil_Out32(0xFD40D8F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); - temp_tm_dig_6 = Xil_In32(0xFD40D06C); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL2PLLCR0; - serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0); + cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL3PLLCR0; - Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40D06C, temp_tm_dig_6); - Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); - Xil_Out32(0xFD40D990, temp_ill12); - Xil_Out32(0xFD40D924, temp_TM_E_ILL1); - } - rdata = Xil_In32(0xFD410098); - rdata = (rdata & 0xDF); - Xil_Out32(0xFD410098, rdata); - } + cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL4PLLCR0; - if (lane0_protocol == 2 && lane0_rate == 3) { - psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); - } - if (lane1_protocol == 2 && lane1_rate == 3) { - psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); - } - if (lane2_protocol == 2 && lane2_rate == 3) { - psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); - } - if (lane3_protocol == 2 && lane3_rate == 3) { - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); - } + cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SLBPLLCR0; - if (lane0_protocol == 1) { - if (lane0_rate == 0) { - serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - } else { - serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate, - 1); - } + cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; + Xil_Out32(0xFD080068, 0x02120000); + Xil_Out32(0xFD081404, 0x02120000); + Xil_Out32(0xFD081444, 0x02120000); + Xil_Out32(0xFD081484, 0x02120000); + Xil_Out32(0xFD0814C4, 0x02120000); + Xil_Out32(0xFD081504, 0x02120000); + Xil_Out32(0xFD0817C4, 0x02120000); + int cur_div2; + + cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; + int cur_fbdiv; + + cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; + dpll_prog(1, 49, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_retry--; } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; - if (lane0_protocol == 3) - Xil_Out32(0xFD401914, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401940, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401990, 0x20); - if (lane0_protocol == 3) - Xil_Out32(0xFD401924, 0x37); + Xil_Out32(0xFD080004U, 0x00040063U); + Xil_Out32(0xFD0800C0U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - if (lane1_protocol == 3) - Xil_Out32(0xFD405914, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405940, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405990, 0x20); - if (lane1_protocol == 3) - Xil_Out32(0xFD405924, 0x37); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); - if (lane2_protocol == 3) - Xil_Out32(0xFD409914, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409940, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409990, 0x20); - if (lane2_protocol == 3) - Xil_Out32(0xFD409924, 0x37); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000331U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D914, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D940, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D990, 0x20); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D924, 0x37); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000B36U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); - return 1; -} + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000C56U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); -static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, - int d_lock_cnt, int d_lfhf, int d_cp, int d_res) -{ - unsigned int pll_ctrl_regval; - unsigned int pll_status_regval; + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000E19U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); - pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00001616U); + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD070010U, 0x80000010U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); - pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + Xil_Out32(0xFD080068, cur_PLLCR0); + Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); + Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); + Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); + Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); + Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); + Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); - pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); - pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); + prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); - pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); - pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); - pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); - pll_ctrl_regval = pll_ctrl_regval | (1 << 3); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0014FE01); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); - pll_ctrl_regval = pll_ctrl_regval | (1 << 0); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + regval = Xil_In32(0xFD080030); + while (regval != 0x8000007E) + regval = Xil_In32(0xFD080030); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); - pll_ctrl_regval = pll_ctrl_regval | (0 << 0); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + Xil_Out32(0xFD080200U, 0x000091C7U); + regval = Xil_In32(0xFD080030); + while (regval != 0x80008FFF) + regval = Xil_In32(0xFD080030); - pll_status_regval = 0x00000000; - while ((pll_status_regval & 0x00000002U) != 0x00000002U) - pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + Xil_Out32(0xFD080200U, 0x800091C7U); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD070180U, 0x02160010U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + for (int tp = 0; tp < 4000; tp++) + regval = Xil_In32(0xFD070018); - pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); - pll_ctrl_regval = pll_ctrl_regval | (0 << 3); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); + prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); + prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); + prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); + prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); + prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); + prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); + prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); + prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + + return 1; } static int serdes_enb_coarse_saturation(void) diff --git a/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c index 2adcad04d86de161feb548b81605ffe0b79c45d8..f98ad8af82e0f8854299be77a911b91515e71856 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c @@ -6,1692 +6,1687 @@ #include #include -static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate); - -static unsigned long psu_pll_init_data(void) +static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (lane0_protocol != 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (lane1_protocol != 0) + mask_poll(0xFD4063E4, 0x00000010U); + if (lane2_protocol != 0) + mask_poll(0xFD40A3E4, 0x00000010U); + if (lane3_protocol != 0) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080); + Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); return 1; } -static unsigned long psu_clock_init_data(void) +static int serdes_bist_static_settings(u32 lane_active) { - psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); - psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); - psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + } + + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + } + if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } return 1; } -static unsigned long psu_ddr_init_data(void) +static int serdes_bist_run(u32 lane_active) { - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_mio_init_data(void) -{ - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_peripherals_pre_init_data(void) -{ - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); - - return 1; -} - -static unsigned long psu_peripherals_init_data(void) -{ - psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); - - mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - return 1; -} - -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); - psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); - psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); - psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); - psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); - psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); - psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); - psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); - psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); - psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); - psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); - psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); - psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); - psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - - serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); - psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); - psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); - psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); - psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); - psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); - - return 1; -} - -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); - psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); - psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); - psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); - psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD40A3E4, 0x00000010U); - mask_poll(0xFD40E3E4, 0x00000010U); - psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); - psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); - psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); - psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); - - return 1; -} - -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); - - return 1; -} - -static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); - psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U); - - return 1; -} - -static unsigned long psu_ddr_phybringup_data(void) -{ - unsigned int regval = 0; - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - int cur_R006_tREFPRD; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); - - while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) - >> 16; - pll_retry--; + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD0701B0U, 0x00000001U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); - regval = Xil_In32(0xFD080030); - while (regval != 0x80000FFF) - regval = Xil_In32(0xFD080030); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - Xil_Out32(0xFD080200U, 0x100091C7U); - - cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - - Xil_Out32(0xFD080004, 0x00060001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80004001) != 0x80004001) - regval = Xil_In32(0xFD080030); - - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); - - Xil_Out32(0xFD080200U, 0x800091C7U); - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - Xil_Out32(0xFD080004, 0x0000C001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80000C01) != 0x80000C01) - regval = Xil_In32(0xFD080030); + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); + return 1; +} - Xil_Out32(0xFD070180U, 0x01000040U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; return 1; } -static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate, + u32 gen2_calib) { - Xil_Out32(0xFD410098, 0x00000000); - Xil_Out32(0xFD401010, 0x00000040); - Xil_Out32(0xFD405010, 0x00000040); - Xil_Out32(0xFD409010, 0x00000040); - Xil_Out32(0xFD40D010, 0x00000040); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - Xil_Out32(0xFD410098, 0x00000004); - mask_delay(50); - if (lane0_rate == 1) - Xil_Out32(0xFD410098, 0x0000000E); - Xil_Out32(0xFD410098, 0x00000006); - if (lane0_rate == 1) { - Xil_Out32(0xFD40000C, 0x00000004); - Xil_Out32(0xFD40400C, 0x00000004); - Xil_Out32(0xFD40800C, 0x00000004); - Xil_Out32(0xFD40C00C, 0x00000004); - Xil_Out32(0xFD410098, 0x00000007); - mask_delay(400); - Xil_Out32(0xFD40000C, 0x0000000C); - Xil_Out32(0xFD40400C, 0x0000000C); - Xil_Out32(0xFD40800C, 0x0000000C); - Xil_Out32(0xFD40C00C, 0x0000000C); - mask_delay(15); - Xil_Out32(0xFD410098, 0x0000000F); - mask_delay(100); + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; } - if (lane0_protocol != 0) - mask_poll(0xFD4023E4, 0x00000010U); - if (lane1_protocol != 0) - mask_poll(0xFD4063E4, 0x00000010U); - if (lane2_protocol != 0) - mask_poll(0xFD40A3E4, 0x00000010U); - if (lane3_protocol != 0) - mask_poll(0xFD40E3E4, 0x00000010U); - mask_delay(50); - Xil_Out32(0xFD401010, 0x000000C0); - Xil_Out32(0xFD405010, 0x000000C0); - Xil_Out32(0xFD409010, 0x000000C0); - Xil_Out32(0xFD40D010, 0x000000C0); - Xil_Out32(0xFD401010, 0x00000080); - Xil_Out32(0xFD405010, 0x00000080); - Xil_Out32(0xFD409010, 0x00000080); - Xil_Out32(0xFD40D010, 0x00000080); + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + } + + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, + lane2_rate, lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2); - Xil_Out32(0xFD402084, 0x000000C0); - Xil_Out32(0xFD406084, 0x000000C0); - Xil_Out32(0xFD40A084, 0x000000C0); - Xil_Out32(0xFD40E084, 0x000000C0); - mask_delay(50); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - mask_delay(50); - Xil_Out32(0xFD401010, 0x00000000); - Xil_Out32(0xFD405010, 0x00000000); - Xil_Out32(0xFD409010, 0x00000000); - Xil_Out32(0xFD40D010, 0x00000000); - Xil_Out32(0xFD402084, 0x00000000); - Xil_Out32(0xFD406084, 0x00000000); - Xil_Out32(0xFD40A084, 0x00000000); - Xil_Out32(0xFD40E084, 0x00000000); - mask_delay(500); - return 1; -} + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8); -static int serdes_bist_static_settings(u32 lane_active) -{ - if (lane_active == 0) { - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - Xil_Out32(0xFD403068, 0x1); - Xil_Out32(0xFD40306C, 0x1); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403008, 0x0); - Xil_Out32(0xFD40300C, 0xF4); - Xil_Out32(0xFD403010, 0x0); - Xil_Out32(0xFD403014, 0x0); - Xil_Out32(0xFD403018, 0x00); - Xil_Out32(0xFD40301C, 0xFB); - Xil_Out32(0xFD403020, 0xFF); - Xil_Out32(0xFD403024, 0x0); - Xil_Out32(0xFD403028, 0x00); - Xil_Out32(0xFD40302C, 0x00); - Xil_Out32(0xFD403030, 0x4A); - Xil_Out32(0xFD403034, 0x4A); - Xil_Out32(0xFD403038, 0x4A); - Xil_Out32(0xFD40303C, 0x4A); - Xil_Out32(0xFD403040, 0x0); - Xil_Out32(0xFD403044, 0x14); - Xil_Out32(0xFD403048, 0x02); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - } - if (lane_active == 1) { - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - Xil_Out32(0xFD407068, 0x1); - Xil_Out32(0xFD40706C, 0x1); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407008, 0x0); - Xil_Out32(0xFD40700C, 0xF4); - Xil_Out32(0xFD407010, 0x0); - Xil_Out32(0xFD407014, 0x0); - Xil_Out32(0xFD407018, 0x00); - Xil_Out32(0xFD40701C, 0xFB); - Xil_Out32(0xFD407020, 0xFF); - Xil_Out32(0xFD407024, 0x0); - Xil_Out32(0xFD407028, 0x00); - Xil_Out32(0xFD40702C, 0x00); - Xil_Out32(0xFD407030, 0x4A); - Xil_Out32(0xFD407034, 0x4A); - Xil_Out32(0xFD407038, 0x4A); - Xil_Out32(0xFD40703C, 0x4A); - Xil_Out32(0xFD407040, 0x0); - Xil_Out32(0xFD407044, 0x14); - Xil_Out32(0xFD407048, 0x02); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && + currbistresult[loop] == 0 && itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + (itercount - 1) - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64); - if (lane_active == 2) { - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40B068, 0x1); - Xil_Out32(0xFD40B06C, 0x1); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B008, 0x0); - Xil_Out32(0xFD40B00C, 0xF4); - Xil_Out32(0xFD40B010, 0x0); - Xil_Out32(0xFD40B014, 0x0); - Xil_Out32(0xFD40B018, 0x00); - Xil_Out32(0xFD40B01C, 0xFB); - Xil_Out32(0xFD40B020, 0xFF); - Xil_Out32(0xFD40B024, 0x0); - Xil_Out32(0xFD40B028, 0x00); - Xil_Out32(0xFD40B02C, 0x00); - Xil_Out32(0xFD40B030, 0x4A); - Xil_Out32(0xFD40B034, 0x4A); - Xil_Out32(0xFD40B038, 0x4A); - Xil_Out32(0xFD40B03C, 0x4A); - Xil_Out32(0xFD40B040, 0x0); - Xil_Out32(0xFD40B044, 0x14); - Xil_Out32(0xFD40B048, 0x02); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue; - if (lane_active == 3) { - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40F068, 0x1); - Xil_Out32(0xFD40F06C, 0x1); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F008, 0x0); - Xil_Out32(0xFD40F00C, 0xF4); - Xil_Out32(0xFD40F010, 0x0); - Xil_Out32(0xFD40F014, 0x0); - Xil_Out32(0xFD40F018, 0x00); - Xil_Out32(0xFD40F01C, 0xFB); - Xil_Out32(0xFD40F020, 0xFF); - Xil_Out32(0xFD40F024, 0x0); - Xil_Out32(0xFD40F028, 0x00); - Xil_Out32(0xFD40F02C, 0x00); - Xil_Out32(0xFD40F030, 0x4A); - Xil_Out32(0xFD40F034, 0x4A); - Xil_Out32(0xFD40F038, 0x4A); - Xil_Out32(0xFD40F03C, 0x4A); - Xil_Out32(0xFD40F040, 0x0); - Xil_Out32(0xFD40F044, 0x14); - Xil_Out32(0xFD40F048, 0x02); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - } - return 1; -} + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop]; -static int serdes_bist_run(u32 lane_active) -{ - if (lane_active == 0) { - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); - } - if (lane_active == 1) { - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); - } - if (lane_active == 2) { - psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + } } - if (lane_active == 3) { - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); } - mask_delay(100); - return 1; -} -static int serdes_bist_result(u32 lane_active) -{ - u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); - if (lane_active == 0) { - pkt_cnt_l0 = Xil_In32(0xFD40304C); - pkt_cnt_h0 = Xil_In32(0xFD403050); - err_cnt_l0 = Xil_In32(0xFD403054); - err_cnt_h0 = Xil_In32(0xFD403058); - } - if (lane_active == 1) { - pkt_cnt_l0 = Xil_In32(0xFD40704C); - pkt_cnt_h0 = Xil_In32(0xFD407050); - err_cnt_l0 = Xil_In32(0xFD407054); - err_cnt_h0 = Xil_In32(0xFD407058); - } - if (lane_active == 2) { - pkt_cnt_l0 = Xil_In32(0xFD40B04C); - pkt_cnt_h0 = Xil_In32(0xFD40B050); - err_cnt_l0 = Xil_In32(0xFD40B054); - err_cnt_h0 = Xil_In32(0xFD40B058); + Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); } - if (lane_active == 3) { - pkt_cnt_l0 = Xil_In32(0xFD40F04C); - pkt_cnt_h0 = Xil_In32(0xFD40F050); - err_cnt_l0 = Xil_In32(0xFD40F054); - err_cnt_h0 = Xil_In32(0xFD40F058); + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); } - if (lane_active == 0) - Xil_Out32(0xFD403004, 0x0); - if (lane_active == 1) - Xil_Out32(0xFD407004, 0x0); - if (lane_active == 2) - Xil_Out32(0xFD40B004, 0x0); - if (lane_active == 3) - Xil_Out32(0xFD40F004, 0x0); - if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || - (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) - return 0; - return 1; -} - -static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate, - u32 gen2_calib) -{ - u64 tempbistresult; - u32 currbistresult[4]; - u32 prevbistresult[4]; - u32 itercount = 0; - u32 ill12_val[4], ill1_val[4]; - u32 loop = 0; - u32 iterresult[8]; - u32 meancount[4]; - u32 bistpasscount[4]; - u32 meancountalt[4]; - u32 meancountalt_bistpasscount[4]; - u32 lane0_active; - u32 lane1_active; - u32 lane2_active; - u32 lane3_active; - - lane0_active = (lane0_protocol == 1); - lane1_active = (lane1_protocol == 1); - lane2_active = (lane2_protocol == 1); - lane3_active = (lane3_protocol == 1); - for (loop = 0; loop <= 3; loop++) { - iterresult[loop] = 0; - iterresult[loop + 4] = 0; - meancountalt[loop] = 0; - meancountalt_bistpasscount[loop] = 0; - meancount[loop] = 0; - prevbistresult[loop] = 0; - bistpasscount[loop] = 0; + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); } - itercount = 0; - if (lane0_active) - serdes_bist_static_settings(0); - if (lane1_active) - serdes_bist_static_settings(1); - if (lane2_active) - serdes_bist_static_settings(2); - if (lane3_active) - serdes_bist_static_settings(3); - do { - if (gen2_calib != 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x04 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane1_active == 1) - ill1_val[1] = ((0x04 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane2_active == 1) - ill1_val[2] = ((0x04 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane3_active == 1) - ill1_val[3] = ((0x04 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } + return 1; +} - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, - ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x104 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane1_active == 1) - ill1_val[1] = ((0x104 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane2_active == 1) - ill1_val[2] = ((0x104 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane3_active == 1) - ill1_val[3] = ((0x104 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset; - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, - ill12_val[3]); - } + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); + } - if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); - if (lane0_active == 1) - currbistresult[0] = 0; - if (lane1_active == 1) - currbistresult[1] = 0; - if (lane2_active == 1) - currbistresult[2] = 0; - if (lane3_active == 1) - currbistresult[3] = 0; - serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, - lane2_rate, lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate); - if (lane3_active == 1) - serdes_bist_run(3); - if (lane2_active == 1) - serdes_bist_run(2); - if (lane1_active == 1) - serdes_bist_run(1); - if (lane0_active == 1) - serdes_bist_run(0); - tempbistresult = 0; - if (lane3_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(3); - tempbistresult = tempbistresult << 1; - if (lane2_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(2); - tempbistresult = tempbistresult << 1; - if (lane1_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(1); - tempbistresult = tempbistresult << 1; - if (lane0_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(0); - Xil_Out32(0xFD410098, 0x0); - Xil_Out32(0xFD410098, 0x2); + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0; - if (itercount < 32) { - iterresult[0] = - ((iterresult[0] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[1] = - ((iterresult[1] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[2] = - ((iterresult[2] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[3] = - ((iterresult[3] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } else { - iterresult[4] = - ((iterresult[4] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[5] = - ((iterresult[5] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[6] = - ((iterresult[6] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[7] = - ((iterresult[7] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } - currbistresult[0] = - currbistresult[0] | ((tempbistresult & 0x1) == 1); - currbistresult[1] = - currbistresult[1] | ((tempbistresult & 0x2) == 0x2); - currbistresult[2] = - currbistresult[2] | ((tempbistresult & 0x4) == 0x4); - currbistresult[3] = - currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0); - for (loop = 0; loop <= 3; loop++) { - if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) - bistpasscount[loop] = bistpasscount[loop] + 1; - if (bistpasscount[loop] < 4 && - currbistresult[loop] == 0 && itercount > 2) { - if (meancountalt_bistpasscount[loop] < - bistpasscount[loop]) { - meancountalt_bistpasscount[loop] = - bistpasscount[loop]; - meancountalt[loop] = - ((itercount - 1) - - ((bistpasscount[loop] + 1) / 2)); - } - bistpasscount[loop] = 0; - } - if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && - (currbistresult[loop] == 0 || itercount == 63) && - prevbistresult[loop] == 1) - meancount[loop] = - (itercount - 1) - - ((bistpasscount[loop] + 1) / 2); - prevbistresult[loop] = currbistresult[loop]; + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); } - } while (++itercount < 64); + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0; - for (loop = 0; loop <= 3; loop++) { - if (lane0_active == 0 && loop == 0) - continue; - if (lane1_active == 0 && loop == 1) - continue; - if (lane2_active == 0 && loop == 2) - continue; - if (lane3_active == 0 && loop == 3) - continue; + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0); - if (meancount[loop] == 0) - meancount[loop] = meancountalt[loop]; + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0; - if (gen2_calib != 1) { - ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x04 + meancount[loop] * 8) >= - 0x100) ? 0x10 : 0x00; - Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); } - if (gen2_calib == 1) { - ill1_val[loop] = - ((0x104 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x104 + meancount[loop] * 8) >= - 0x200) ? 0x02 : 0x01; - Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); } - if (gen2_calib != 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); } - if (gen2_calib == 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + } + + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } } - if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37); + + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37); + + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37); + + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37); + + return 1; +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - Xil_Out32(0xFD410098, 0); - if (lane0_active == 1) { - Xil_Out32(0xFD403004, 0); - Xil_Out32(0xFD403008, 0); - Xil_Out32(0xFD40300C, 0); - Xil_Out32(0xFD403010, 0); - Xil_Out32(0xFD403014, 0); - Xil_Out32(0xFD403018, 0); - Xil_Out32(0xFD40301C, 0); - Xil_Out32(0xFD403020, 0); - Xil_Out32(0xFD403024, 0); - Xil_Out32(0xFD403028, 0); - Xil_Out32(0xFD40302C, 0); - Xil_Out32(0xFD403030, 0); - Xil_Out32(0xFD403034, 0); - Xil_Out32(0xFD403038, 0); - Xil_Out32(0xFD40303C, 0); - Xil_Out32(0xFD403040, 0); - Xil_Out32(0xFD403044, 0); - Xil_Out32(0xFD403048, 0); - Xil_Out32(0xFD40304C, 0); - Xil_Out32(0xFD403050, 0); - Xil_Out32(0xFD403054, 0); - Xil_Out32(0xFD403058, 0); - Xil_Out32(0xFD403068, 1); - Xil_Out32(0xFD40306C, 0); - Xil_Out32(0xFD4010AC, 0); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); - } - if (lane1_active == 1) { - Xil_Out32(0xFD407004, 0); - Xil_Out32(0xFD407008, 0); - Xil_Out32(0xFD40700C, 0); - Xil_Out32(0xFD407010, 0); - Xil_Out32(0xFD407014, 0); - Xil_Out32(0xFD407018, 0); - Xil_Out32(0xFD40701C, 0); - Xil_Out32(0xFD407020, 0); - Xil_Out32(0xFD407024, 0); - Xil_Out32(0xFD407028, 0); - Xil_Out32(0xFD40702C, 0); - Xil_Out32(0xFD407030, 0); - Xil_Out32(0xFD407034, 0); - Xil_Out32(0xFD407038, 0); - Xil_Out32(0xFD40703C, 0); - Xil_Out32(0xFD407040, 0); - Xil_Out32(0xFD407044, 0); - Xil_Out32(0xFD407048, 0); - Xil_Out32(0xFD40704C, 0); - Xil_Out32(0xFD407050, 0); - Xil_Out32(0xFD407054, 0); - Xil_Out32(0xFD407058, 0); - Xil_Out32(0xFD407068, 1); - Xil_Out32(0xFD40706C, 0); - Xil_Out32(0xFD4050AC, 0); - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); - } - if (lane2_active == 1) { - Xil_Out32(0xFD40B004, 0); - Xil_Out32(0xFD40B008, 0); - Xil_Out32(0xFD40B00C, 0); - Xil_Out32(0xFD40B010, 0); - Xil_Out32(0xFD40B014, 0); - Xil_Out32(0xFD40B018, 0); - Xil_Out32(0xFD40B01C, 0); - Xil_Out32(0xFD40B020, 0); - Xil_Out32(0xFD40B024, 0); - Xil_Out32(0xFD40B028, 0); - Xil_Out32(0xFD40B02C, 0); - Xil_Out32(0xFD40B030, 0); - Xil_Out32(0xFD40B034, 0); - Xil_Out32(0xFD40B038, 0); - Xil_Out32(0xFD40B03C, 0); - Xil_Out32(0xFD40B040, 0); - Xil_Out32(0xFD40B044, 0); - Xil_Out32(0xFD40B048, 0); - Xil_Out32(0xFD40B04C, 0); - Xil_Out32(0xFD40B050, 0); - Xil_Out32(0xFD40B054, 0); - Xil_Out32(0xFD40B058, 0); - Xil_Out32(0xFD40B068, 1); - Xil_Out32(0xFD40B06C, 0); - Xil_Out32(0xFD4090AC, 0); - psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); - } - if (lane3_active == 1) { - Xil_Out32(0xFD40F004, 0); - Xil_Out32(0xFD40F008, 0); - Xil_Out32(0xFD40F00C, 0); - Xil_Out32(0xFD40F010, 0); - Xil_Out32(0xFD40F014, 0); - Xil_Out32(0xFD40F018, 0); - Xil_Out32(0xFD40F01C, 0); - Xil_Out32(0xFD40F020, 0); - Xil_Out32(0xFD40F024, 0); - Xil_Out32(0xFD40F028, 0); - Xil_Out32(0xFD40F02C, 0); - Xil_Out32(0xFD40F030, 0); - Xil_Out32(0xFD40F034, 0); - Xil_Out32(0xFD40F038, 0); - Xil_Out32(0xFD40F03C, 0); - Xil_Out32(0xFD40F040, 0); - Xil_Out32(0xFD40F044, 0); - Xil_Out32(0xFD40F048, 0); - Xil_Out32(0xFD40F04C, 0); - Xil_Out32(0xFD40F050, 0); - Xil_Out32(0xFD40F054, 0); - Xil_Out32(0xFD40F058, 0); - Xil_Out32(0xFD40F068, 1); - Xil_Out32(0xFD40F06C, 0); - Xil_Out32(0xFD40D0AC, 0); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); - } return 1; } -static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static unsigned long psu_peripherals_pre_init_data(void) { - unsigned int rdata = 0; - unsigned int sata_gen2 = 1; - unsigned int temp_ill12 = 0; - unsigned int temp_PLL_REF_SEL_OFFSET; - unsigned int temp_TM_IQ_ILL1; - unsigned int temp_TM_E_ILL1; - unsigned int temp_tx_dig_tm_61; - unsigned int temp_tm_dig_6; - unsigned int temp_pll_fbdiv_frac_3_msb_offset; + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); - if (lane0_protocol == 2 || lane0_protocol == 1) { - Xil_Out32(0xFD401910, 0xF3); - Xil_Out32(0xFD40193C, 0xF3); - Xil_Out32(0xFD401914, 0xF3); - Xil_Out32(0xFD401940, 0xF3); - } - if (lane1_protocol == 2 || lane1_protocol == 1) { - Xil_Out32(0xFD405910, 0xF3); - Xil_Out32(0xFD40593C, 0xF3); - Xil_Out32(0xFD405914, 0xF3); - Xil_Out32(0xFD405940, 0xF3); - } - if (lane2_protocol == 2 || lane2_protocol == 1) { - Xil_Out32(0xFD409910, 0xF3); - Xil_Out32(0xFD40993C, 0xF3); - Xil_Out32(0xFD409914, 0xF3); - Xil_Out32(0xFD409940, 0xF3); - } - if (lane3_protocol == 2 || lane3_protocol == 1) { - Xil_Out32(0xFD40D910, 0xF3); - Xil_Out32(0xFD40D93C, 0xF3); - Xil_Out32(0xFD40D914, 0xF3); - Xil_Out32(0xFD40D940, 0xF3); - } + return 1; +} - if (sata_gen2 == 1) { - if (lane0_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); - Xil_Out32(0xFD402360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); - temp_TM_E_ILL1 = Xil_In32(0xFD401924); - Xil_Out32(0xFD4018F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); - temp_tm_dig_6 = Xil_In32(0xFD40106C); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD401990) & 0xF0; +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); - serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0); + return 1; +} - Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40106C, temp_tm_dig_6); - Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); - Xil_Out32(0xFD401990, temp_ill12); - Xil_Out32(0xFD401924, temp_TM_E_ILL1); - } - if (lane1_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); - Xil_Out32(0xFD406360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); - psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); - temp_TM_E_ILL1 = Xil_In32(0xFD405924); - Xil_Out32(0xFD4058F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); - temp_tm_dig_6 = Xil_In32(0xFD40506C); - psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD405990) & 0xF0; +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); - serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0); + return 1; +} - Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40506C, temp_tm_dig_6); - Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); - Xil_Out32(0xFD405990, temp_ill12); - Xil_Out32(0xFD405924, temp_TM_E_ILL1); - } - if (lane2_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); - Xil_Out32(0xFD40A360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); - psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); - temp_TM_E_ILL1 = Xil_In32(0xFD409924); - Xil_Out32(0xFD4098F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); - temp_tm_dig_6 = Xil_In32(0xFD40906C); - psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD409990) & 0xF0; +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U); - serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + return 1; +} - Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40906C, temp_tm_dig_6); - Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); - Xil_Out32(0xFD409990, temp_ill12); - Xil_Out32(0xFD409924, temp_TM_E_ILL1); - } - if (lane3_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); - Xil_Out32(0xFD40E360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); - temp_TM_E_ILL1 = Xil_In32(0xFD40D924); - Xil_Out32(0xFD40D8F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); - temp_tm_dig_6 = Xil_In32(0xFD40D06C); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + int cur_R006_tREFPRD; - serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); - Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40D06C, temp_tm_dig_6); - Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); - Xil_Out32(0xFD40D990, temp_ill12); - Xil_Out32(0xFD40D924, temp_TM_E_ILL1); - } - rdata = Xil_In32(0xFD410098); - rdata = (rdata & 0xDF); - Xil_Out32(0xFD410098, rdata); + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; - if (lane0_protocol == 2 && lane0_rate == 3) { - psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); - } - if (lane1_protocol == 2 && lane1_rate == 3) { - psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); - } - if (lane2_protocol == 2 && lane2_rate == 3) { - psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); - } - if (lane3_protocol == 2 && lane3_rate == 3) { - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); - } + Xil_Out32(0xFD080004U, 0x00040063U); - if (lane0_protocol == 1) { - if (lane0_rate == 0) { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - } else { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate, - 1); - } - } + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - if (lane0_protocol == 3) - Xil_Out32(0xFD401914, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401940, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401990, 0x20); - if (lane0_protocol == 3) - Xil_Out32(0xFD401924, 0x37); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; - if (lane1_protocol == 3) - Xil_Out32(0xFD405914, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405940, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405990, 0x20); - if (lane1_protocol == 3) - Xil_Out32(0xFD405924, 0x37); + Xil_Out32(0xFD080200U, 0x100091C7U); - if (lane2_protocol == 3) - Xil_Out32(0xFD409914, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409940, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409990, 0x20); - if (lane2_protocol == 3) - Xil_Out32(0xFD409924, 0x37); + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D914, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D940, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D990, 0x20); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D924, 0x37); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); return 1; } diff --git a/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c index bd316872eb338691cc1d79161ad3f6591bba0771..5d47cd1abc0875c19b6e2d41b978458653fcb6e7 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c @@ -6,1692 +6,1687 @@ #include #include -static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate); - -static unsigned long psu_pll_init_data(void) +static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (lane0_protocol != 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (lane1_protocol != 0) + mask_poll(0xFD4063E4, 0x00000010U); + if (lane2_protocol != 0) + mask_poll(0xFD40A3E4, 0x00000010U); + if (lane3_protocol != 0) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080); + Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); return 1; } -static unsigned long psu_clock_init_data(void) +static int serdes_bist_static_settings(u32 lane_active) { - psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); - psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); - psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + } + + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + } + if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } return 1; } -static unsigned long psu_ddr_init_data(void) +static int serdes_bist_run(u32 lane_active) { - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_mio_init_data(void) -{ - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_peripherals_pre_init_data(void) -{ - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); - - return 1; -} - -static unsigned long psu_peripherals_init_data(void) -{ - psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); - - mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - return 1; -} - -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); - psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); - psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); - psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); - psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); - psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); - psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); - psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); - psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); - psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); - psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); - psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); - psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); - psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - - serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); - psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); - psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); - psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); - psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); - psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); - - return 1; -} - -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); - psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); - psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); - psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); - psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD40A3E4, 0x00000010U); - mask_poll(0xFD40E3E4, 0x00000010U); - psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); - psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); - psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); - psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); - - return 1; -} - -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); - - return 1; -} - -static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); - psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U); - - return 1; -} - -static unsigned long psu_ddr_phybringup_data(void) -{ - unsigned int regval = 0; - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - int cur_R006_tREFPRD; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); - - while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) - >> 16; - pll_retry--; + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD0701B0U, 0x00000001U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); - regval = Xil_In32(0xFD080030); - while (regval != 0x80000FFF) - regval = Xil_In32(0xFD080030); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - Xil_Out32(0xFD080200U, 0x100091C7U); - - cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - - Xil_Out32(0xFD080004, 0x00060001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80004001) != 0x80004001) - regval = Xil_In32(0xFD080030); - - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); - - Xil_Out32(0xFD080200U, 0x800091C7U); - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - Xil_Out32(0xFD080004, 0x0000C001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80000C01) != 0x80000C01) - regval = Xil_In32(0xFD080030); + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); + return 1; +} - Xil_Out32(0xFD070180U, 0x01000040U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; return 1; } -static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate, + u32 gen2_calib) { - Xil_Out32(0xFD410098, 0x00000000); - Xil_Out32(0xFD401010, 0x00000040); - Xil_Out32(0xFD405010, 0x00000040); - Xil_Out32(0xFD409010, 0x00000040); - Xil_Out32(0xFD40D010, 0x00000040); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - Xil_Out32(0xFD410098, 0x00000004); - mask_delay(50); - if (lane0_rate == 1) - Xil_Out32(0xFD410098, 0x0000000E); - Xil_Out32(0xFD410098, 0x00000006); - if (lane0_rate == 1) { - Xil_Out32(0xFD40000C, 0x00000004); - Xil_Out32(0xFD40400C, 0x00000004); - Xil_Out32(0xFD40800C, 0x00000004); - Xil_Out32(0xFD40C00C, 0x00000004); - Xil_Out32(0xFD410098, 0x00000007); - mask_delay(400); - Xil_Out32(0xFD40000C, 0x0000000C); - Xil_Out32(0xFD40400C, 0x0000000C); - Xil_Out32(0xFD40800C, 0x0000000C); - Xil_Out32(0xFD40C00C, 0x0000000C); - mask_delay(15); - Xil_Out32(0xFD410098, 0x0000000F); - mask_delay(100); + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; } - if (lane0_protocol != 0) - mask_poll(0xFD4023E4, 0x00000010U); - if (lane1_protocol != 0) - mask_poll(0xFD4063E4, 0x00000010U); - if (lane2_protocol != 0) - mask_poll(0xFD40A3E4, 0x00000010U); - if (lane3_protocol != 0) - mask_poll(0xFD40E3E4, 0x00000010U); - mask_delay(50); - Xil_Out32(0xFD401010, 0x000000C0); - Xil_Out32(0xFD405010, 0x000000C0); - Xil_Out32(0xFD409010, 0x000000C0); - Xil_Out32(0xFD40D010, 0x000000C0); - Xil_Out32(0xFD401010, 0x00000080); - Xil_Out32(0xFD405010, 0x00000080); - Xil_Out32(0xFD409010, 0x00000080); - Xil_Out32(0xFD40D010, 0x00000080); + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + } + + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, + lane2_rate, lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2); - Xil_Out32(0xFD402084, 0x000000C0); - Xil_Out32(0xFD406084, 0x000000C0); - Xil_Out32(0xFD40A084, 0x000000C0); - Xil_Out32(0xFD40E084, 0x000000C0); - mask_delay(50); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - mask_delay(50); - Xil_Out32(0xFD401010, 0x00000000); - Xil_Out32(0xFD405010, 0x00000000); - Xil_Out32(0xFD409010, 0x00000000); - Xil_Out32(0xFD40D010, 0x00000000); - Xil_Out32(0xFD402084, 0x00000000); - Xil_Out32(0xFD406084, 0x00000000); - Xil_Out32(0xFD40A084, 0x00000000); - Xil_Out32(0xFD40E084, 0x00000000); - mask_delay(500); - return 1; -} + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8); -static int serdes_bist_static_settings(u32 lane_active) -{ - if (lane_active == 0) { - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - Xil_Out32(0xFD403068, 0x1); - Xil_Out32(0xFD40306C, 0x1); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403008, 0x0); - Xil_Out32(0xFD40300C, 0xF4); - Xil_Out32(0xFD403010, 0x0); - Xil_Out32(0xFD403014, 0x0); - Xil_Out32(0xFD403018, 0x00); - Xil_Out32(0xFD40301C, 0xFB); - Xil_Out32(0xFD403020, 0xFF); - Xil_Out32(0xFD403024, 0x0); - Xil_Out32(0xFD403028, 0x00); - Xil_Out32(0xFD40302C, 0x00); - Xil_Out32(0xFD403030, 0x4A); - Xil_Out32(0xFD403034, 0x4A); - Xil_Out32(0xFD403038, 0x4A); - Xil_Out32(0xFD40303C, 0x4A); - Xil_Out32(0xFD403040, 0x0); - Xil_Out32(0xFD403044, 0x14); - Xil_Out32(0xFD403048, 0x02); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - } - if (lane_active == 1) { - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - Xil_Out32(0xFD407068, 0x1); - Xil_Out32(0xFD40706C, 0x1); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407008, 0x0); - Xil_Out32(0xFD40700C, 0xF4); - Xil_Out32(0xFD407010, 0x0); - Xil_Out32(0xFD407014, 0x0); - Xil_Out32(0xFD407018, 0x00); - Xil_Out32(0xFD40701C, 0xFB); - Xil_Out32(0xFD407020, 0xFF); - Xil_Out32(0xFD407024, 0x0); - Xil_Out32(0xFD407028, 0x00); - Xil_Out32(0xFD40702C, 0x00); - Xil_Out32(0xFD407030, 0x4A); - Xil_Out32(0xFD407034, 0x4A); - Xil_Out32(0xFD407038, 0x4A); - Xil_Out32(0xFD40703C, 0x4A); - Xil_Out32(0xFD407040, 0x0); - Xil_Out32(0xFD407044, 0x14); - Xil_Out32(0xFD407048, 0x02); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && currbistresult[loop] == 0 && + itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + (itercount - 1) - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64); - if (lane_active == 2) { - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40B068, 0x1); - Xil_Out32(0xFD40B06C, 0x1); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B008, 0x0); - Xil_Out32(0xFD40B00C, 0xF4); - Xil_Out32(0xFD40B010, 0x0); - Xil_Out32(0xFD40B014, 0x0); - Xil_Out32(0xFD40B018, 0x00); - Xil_Out32(0xFD40B01C, 0xFB); - Xil_Out32(0xFD40B020, 0xFF); - Xil_Out32(0xFD40B024, 0x0); - Xil_Out32(0xFD40B028, 0x00); - Xil_Out32(0xFD40B02C, 0x00); - Xil_Out32(0xFD40B030, 0x4A); - Xil_Out32(0xFD40B034, 0x4A); - Xil_Out32(0xFD40B038, 0x4A); - Xil_Out32(0xFD40B03C, 0x4A); - Xil_Out32(0xFD40B040, 0x0); - Xil_Out32(0xFD40B044, 0x14); - Xil_Out32(0xFD40B048, 0x02); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue; - if (lane_active == 3) { - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40F068, 0x1); - Xil_Out32(0xFD40F06C, 0x1); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F008, 0x0); - Xil_Out32(0xFD40F00C, 0xF4); - Xil_Out32(0xFD40F010, 0x0); - Xil_Out32(0xFD40F014, 0x0); - Xil_Out32(0xFD40F018, 0x00); - Xil_Out32(0xFD40F01C, 0xFB); - Xil_Out32(0xFD40F020, 0xFF); - Xil_Out32(0xFD40F024, 0x0); - Xil_Out32(0xFD40F028, 0x00); - Xil_Out32(0xFD40F02C, 0x00); - Xil_Out32(0xFD40F030, 0x4A); - Xil_Out32(0xFD40F034, 0x4A); - Xil_Out32(0xFD40F038, 0x4A); - Xil_Out32(0xFD40F03C, 0x4A); - Xil_Out32(0xFD40F040, 0x0); - Xil_Out32(0xFD40F044, 0x14); - Xil_Out32(0xFD40F048, 0x02); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - } - return 1; -} + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop]; -static int serdes_bist_run(u32 lane_active) -{ - if (lane_active == 0) { - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); - } - if (lane_active == 1) { - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); - } - if (lane_active == 2) { - psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + } } - if (lane_active == 3) { - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); } - mask_delay(100); - return 1; -} -static int serdes_bist_result(u32 lane_active) -{ - u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); - if (lane_active == 0) { - pkt_cnt_l0 = Xil_In32(0xFD40304C); - pkt_cnt_h0 = Xil_In32(0xFD403050); - err_cnt_l0 = Xil_In32(0xFD403054); - err_cnt_h0 = Xil_In32(0xFD403058); - } - if (lane_active == 1) { - pkt_cnt_l0 = Xil_In32(0xFD40704C); - pkt_cnt_h0 = Xil_In32(0xFD407050); - err_cnt_l0 = Xil_In32(0xFD407054); - err_cnt_h0 = Xil_In32(0xFD407058); - } - if (lane_active == 2) { - pkt_cnt_l0 = Xil_In32(0xFD40B04C); - pkt_cnt_h0 = Xil_In32(0xFD40B050); - err_cnt_l0 = Xil_In32(0xFD40B054); - err_cnt_h0 = Xil_In32(0xFD40B058); + Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); } - if (lane_active == 3) { - pkt_cnt_l0 = Xil_In32(0xFD40F04C); - pkt_cnt_h0 = Xil_In32(0xFD40F050); - err_cnt_l0 = Xil_In32(0xFD40F054); - err_cnt_h0 = Xil_In32(0xFD40F058); + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); } - if (lane_active == 0) - Xil_Out32(0xFD403004, 0x0); - if (lane_active == 1) - Xil_Out32(0xFD407004, 0x0); - if (lane_active == 2) - Xil_Out32(0xFD40B004, 0x0); - if (lane_active == 3) - Xil_Out32(0xFD40F004, 0x0); - if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || - (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) - return 0; - return 1; -} - -static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate, - u32 gen2_calib) -{ - u64 tempbistresult; - u32 currbistresult[4]; - u32 prevbistresult[4]; - u32 itercount = 0; - u32 ill12_val[4], ill1_val[4]; - u32 loop = 0; - u32 iterresult[8]; - u32 meancount[4]; - u32 bistpasscount[4]; - u32 meancountalt[4]; - u32 meancountalt_bistpasscount[4]; - u32 lane0_active; - u32 lane1_active; - u32 lane2_active; - u32 lane3_active; - - lane0_active = (lane0_protocol == 1); - lane1_active = (lane1_protocol == 1); - lane2_active = (lane2_protocol == 1); - lane3_active = (lane3_protocol == 1); - for (loop = 0; loop <= 3; loop++) { - iterresult[loop] = 0; - iterresult[loop + 4] = 0; - meancountalt[loop] = 0; - meancountalt_bistpasscount[loop] = 0; - meancount[loop] = 0; - prevbistresult[loop] = 0; - bistpasscount[loop] = 0; + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); } - itercount = 0; - if (lane0_active) - serdes_bist_static_settings(0); - if (lane1_active) - serdes_bist_static_settings(1); - if (lane2_active) - serdes_bist_static_settings(2); - if (lane3_active) - serdes_bist_static_settings(3); - do { - if (gen2_calib != 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x04 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane1_active == 1) - ill1_val[1] = ((0x04 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane2_active == 1) - ill1_val[2] = ((0x04 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane3_active == 1) - ill1_val[3] = ((0x04 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } + return 1; +} - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, - ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x104 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane1_active == 1) - ill1_val[1] = ((0x104 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane2_active == 1) - ill1_val[2] = ((0x104 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane3_active == 1) - ill1_val[3] = ((0x104 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset; - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, - ill12_val[3]); - } + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); + } - if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); - if (lane0_active == 1) - currbistresult[0] = 0; - if (lane1_active == 1) - currbistresult[1] = 0; - if (lane2_active == 1) - currbistresult[2] = 0; - if (lane3_active == 1) - currbistresult[3] = 0; - serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, - lane2_rate, lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate); - if (lane3_active == 1) - serdes_bist_run(3); - if (lane2_active == 1) - serdes_bist_run(2); - if (lane1_active == 1) - serdes_bist_run(1); - if (lane0_active == 1) - serdes_bist_run(0); - tempbistresult = 0; - if (lane3_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(3); - tempbistresult = tempbistresult << 1; - if (lane2_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(2); - tempbistresult = tempbistresult << 1; - if (lane1_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(1); - tempbistresult = tempbistresult << 1; - if (lane0_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(0); - Xil_Out32(0xFD410098, 0x0); - Xil_Out32(0xFD410098, 0x2); + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0; - if (itercount < 32) { - iterresult[0] = - ((iterresult[0] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[1] = - ((iterresult[1] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[2] = - ((iterresult[2] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[3] = - ((iterresult[3] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } else { - iterresult[4] = - ((iterresult[4] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[5] = - ((iterresult[5] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[6] = - ((iterresult[6] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[7] = - ((iterresult[7] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } - currbistresult[0] = - currbistresult[0] | ((tempbistresult & 0x1) == 1); - currbistresult[1] = - currbistresult[1] | ((tempbistresult & 0x2) == 0x2); - currbistresult[2] = - currbistresult[2] | ((tempbistresult & 0x4) == 0x4); - currbistresult[3] = - currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0); - for (loop = 0; loop <= 3; loop++) { - if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) - bistpasscount[loop] = bistpasscount[loop] + 1; - if (bistpasscount[loop] < 4 && currbistresult[loop] == 0 && - itercount > 2) { - if (meancountalt_bistpasscount[loop] < - bistpasscount[loop]) { - meancountalt_bistpasscount[loop] = - bistpasscount[loop]; - meancountalt[loop] = - ((itercount - 1) - - ((bistpasscount[loop] + 1) / 2)); - } - bistpasscount[loop] = 0; - } - if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && - (currbistresult[loop] == 0 || itercount == 63) && - prevbistresult[loop] == 1) - meancount[loop] = - (itercount - 1) - - ((bistpasscount[loop] + 1) / 2); - prevbistresult[loop] = currbistresult[loop]; + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); } - } while (++itercount < 64); + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0; - for (loop = 0; loop <= 3; loop++) { - if (lane0_active == 0 && loop == 0) - continue; - if (lane1_active == 0 && loop == 1) - continue; - if (lane2_active == 0 && loop == 2) - continue; - if (lane3_active == 0 && loop == 3) - continue; + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0); - if (meancount[loop] == 0) - meancount[loop] = meancountalt[loop]; + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0; - if (gen2_calib != 1) { - ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x04 + meancount[loop] * 8) >= - 0x100) ? 0x10 : 0x00; - Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); } - if (gen2_calib == 1) { - ill1_val[loop] = - ((0x104 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x104 + meancount[loop] * 8) >= - 0x200) ? 0x02 : 0x01; - Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); } - if (gen2_calib != 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); } - if (gen2_calib == 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + } + + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } } - if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37); + + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37); + + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37); + + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37); + + return 1; +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - Xil_Out32(0xFD410098, 0); - if (lane0_active == 1) { - Xil_Out32(0xFD403004, 0); - Xil_Out32(0xFD403008, 0); - Xil_Out32(0xFD40300C, 0); - Xil_Out32(0xFD403010, 0); - Xil_Out32(0xFD403014, 0); - Xil_Out32(0xFD403018, 0); - Xil_Out32(0xFD40301C, 0); - Xil_Out32(0xFD403020, 0); - Xil_Out32(0xFD403024, 0); - Xil_Out32(0xFD403028, 0); - Xil_Out32(0xFD40302C, 0); - Xil_Out32(0xFD403030, 0); - Xil_Out32(0xFD403034, 0); - Xil_Out32(0xFD403038, 0); - Xil_Out32(0xFD40303C, 0); - Xil_Out32(0xFD403040, 0); - Xil_Out32(0xFD403044, 0); - Xil_Out32(0xFD403048, 0); - Xil_Out32(0xFD40304C, 0); - Xil_Out32(0xFD403050, 0); - Xil_Out32(0xFD403054, 0); - Xil_Out32(0xFD403058, 0); - Xil_Out32(0xFD403068, 1); - Xil_Out32(0xFD40306C, 0); - Xil_Out32(0xFD4010AC, 0); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); - } - if (lane1_active == 1) { - Xil_Out32(0xFD407004, 0); - Xil_Out32(0xFD407008, 0); - Xil_Out32(0xFD40700C, 0); - Xil_Out32(0xFD407010, 0); - Xil_Out32(0xFD407014, 0); - Xil_Out32(0xFD407018, 0); - Xil_Out32(0xFD40701C, 0); - Xil_Out32(0xFD407020, 0); - Xil_Out32(0xFD407024, 0); - Xil_Out32(0xFD407028, 0); - Xil_Out32(0xFD40702C, 0); - Xil_Out32(0xFD407030, 0); - Xil_Out32(0xFD407034, 0); - Xil_Out32(0xFD407038, 0); - Xil_Out32(0xFD40703C, 0); - Xil_Out32(0xFD407040, 0); - Xil_Out32(0xFD407044, 0); - Xil_Out32(0xFD407048, 0); - Xil_Out32(0xFD40704C, 0); - Xil_Out32(0xFD407050, 0); - Xil_Out32(0xFD407054, 0); - Xil_Out32(0xFD407058, 0); - Xil_Out32(0xFD407068, 1); - Xil_Out32(0xFD40706C, 0); - Xil_Out32(0xFD4050AC, 0); - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); - } - if (lane2_active == 1) { - Xil_Out32(0xFD40B004, 0); - Xil_Out32(0xFD40B008, 0); - Xil_Out32(0xFD40B00C, 0); - Xil_Out32(0xFD40B010, 0); - Xil_Out32(0xFD40B014, 0); - Xil_Out32(0xFD40B018, 0); - Xil_Out32(0xFD40B01C, 0); - Xil_Out32(0xFD40B020, 0); - Xil_Out32(0xFD40B024, 0); - Xil_Out32(0xFD40B028, 0); - Xil_Out32(0xFD40B02C, 0); - Xil_Out32(0xFD40B030, 0); - Xil_Out32(0xFD40B034, 0); - Xil_Out32(0xFD40B038, 0); - Xil_Out32(0xFD40B03C, 0); - Xil_Out32(0xFD40B040, 0); - Xil_Out32(0xFD40B044, 0); - Xil_Out32(0xFD40B048, 0); - Xil_Out32(0xFD40B04C, 0); - Xil_Out32(0xFD40B050, 0); - Xil_Out32(0xFD40B054, 0); - Xil_Out32(0xFD40B058, 0); - Xil_Out32(0xFD40B068, 1); - Xil_Out32(0xFD40B06C, 0); - Xil_Out32(0xFD4090AC, 0); - psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); - } - if (lane3_active == 1) { - Xil_Out32(0xFD40F004, 0); - Xil_Out32(0xFD40F008, 0); - Xil_Out32(0xFD40F00C, 0); - Xil_Out32(0xFD40F010, 0); - Xil_Out32(0xFD40F014, 0); - Xil_Out32(0xFD40F018, 0); - Xil_Out32(0xFD40F01C, 0); - Xil_Out32(0xFD40F020, 0); - Xil_Out32(0xFD40F024, 0); - Xil_Out32(0xFD40F028, 0); - Xil_Out32(0xFD40F02C, 0); - Xil_Out32(0xFD40F030, 0); - Xil_Out32(0xFD40F034, 0); - Xil_Out32(0xFD40F038, 0); - Xil_Out32(0xFD40F03C, 0); - Xil_Out32(0xFD40F040, 0); - Xil_Out32(0xFD40F044, 0); - Xil_Out32(0xFD40F048, 0); - Xil_Out32(0xFD40F04C, 0); - Xil_Out32(0xFD40F050, 0); - Xil_Out32(0xFD40F054, 0); - Xil_Out32(0xFD40F058, 0); - Xil_Out32(0xFD40F068, 1); - Xil_Out32(0xFD40F06C, 0); - Xil_Out32(0xFD40D0AC, 0); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); - } return 1; } -static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static unsigned long psu_peripherals_pre_init_data(void) { - unsigned int rdata = 0; - unsigned int sata_gen2 = 1; - unsigned int temp_ill12 = 0; - unsigned int temp_PLL_REF_SEL_OFFSET; - unsigned int temp_TM_IQ_ILL1; - unsigned int temp_TM_E_ILL1; - unsigned int temp_tx_dig_tm_61; - unsigned int temp_tm_dig_6; - unsigned int temp_pll_fbdiv_frac_3_msb_offset; + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); - if (lane0_protocol == 2 || lane0_protocol == 1) { - Xil_Out32(0xFD401910, 0xF3); - Xil_Out32(0xFD40193C, 0xF3); - Xil_Out32(0xFD401914, 0xF3); - Xil_Out32(0xFD401940, 0xF3); - } - if (lane1_protocol == 2 || lane1_protocol == 1) { - Xil_Out32(0xFD405910, 0xF3); - Xil_Out32(0xFD40593C, 0xF3); - Xil_Out32(0xFD405914, 0xF3); - Xil_Out32(0xFD405940, 0xF3); - } - if (lane2_protocol == 2 || lane2_protocol == 1) { - Xil_Out32(0xFD409910, 0xF3); - Xil_Out32(0xFD40993C, 0xF3); - Xil_Out32(0xFD409914, 0xF3); - Xil_Out32(0xFD409940, 0xF3); - } - if (lane3_protocol == 2 || lane3_protocol == 1) { - Xil_Out32(0xFD40D910, 0xF3); - Xil_Out32(0xFD40D93C, 0xF3); - Xil_Out32(0xFD40D914, 0xF3); - Xil_Out32(0xFD40D940, 0xF3); - } + return 1; +} - if (sata_gen2 == 1) { - if (lane0_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); - Xil_Out32(0xFD402360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); - temp_TM_E_ILL1 = Xil_In32(0xFD401924); - Xil_Out32(0xFD4018F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); - temp_tm_dig_6 = Xil_In32(0xFD40106C); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD401990) & 0xF0; +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); - serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0); + return 1; +} - Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40106C, temp_tm_dig_6); - Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); - Xil_Out32(0xFD401990, temp_ill12); - Xil_Out32(0xFD401924, temp_TM_E_ILL1); - } - if (lane1_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); - Xil_Out32(0xFD406360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); - psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); - temp_TM_E_ILL1 = Xil_In32(0xFD405924); - Xil_Out32(0xFD4058F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); - temp_tm_dig_6 = Xil_In32(0xFD40506C); - psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD405990) & 0xF0; +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); - serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0); + return 1; +} - Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40506C, temp_tm_dig_6); - Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); - Xil_Out32(0xFD405990, temp_ill12); - Xil_Out32(0xFD405924, temp_TM_E_ILL1); - } - if (lane2_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); - Xil_Out32(0xFD40A360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); - psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); - temp_TM_E_ILL1 = Xil_In32(0xFD409924); - Xil_Out32(0xFD4098F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); - temp_tm_dig_6 = Xil_In32(0xFD40906C); - psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD409990) & 0xF0; +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U); - serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + return 1; +} - Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40906C, temp_tm_dig_6); - Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); - Xil_Out32(0xFD409990, temp_ill12); - Xil_Out32(0xFD409924, temp_TM_E_ILL1); - } - if (lane3_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); - Xil_Out32(0xFD40E360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); - temp_TM_E_ILL1 = Xil_In32(0xFD40D924); - Xil_Out32(0xFD40D8F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); - temp_tm_dig_6 = Xil_In32(0xFD40D06C); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + int cur_R006_tREFPRD; - serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); - Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40D06C, temp_tm_dig_6); - Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); - Xil_Out32(0xFD40D990, temp_ill12); - Xil_Out32(0xFD40D924, temp_TM_E_ILL1); - } - rdata = Xil_In32(0xFD410098); - rdata = (rdata & 0xDF); - Xil_Out32(0xFD410098, rdata); + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; - if (lane0_protocol == 2 && lane0_rate == 3) { - psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); - } - if (lane1_protocol == 2 && lane1_rate == 3) { - psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); - } - if (lane2_protocol == 2 && lane2_rate == 3) { - psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); - } - if (lane3_protocol == 2 && lane3_rate == 3) { - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); - } + Xil_Out32(0xFD080004U, 0x00040063U); - if (lane0_protocol == 1) { - if (lane0_rate == 0) { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - } else { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate, - 1); - } - } + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - if (lane0_protocol == 3) - Xil_Out32(0xFD401914, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401940, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401990, 0x20); - if (lane0_protocol == 3) - Xil_Out32(0xFD401924, 0x37); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; - if (lane1_protocol == 3) - Xil_Out32(0xFD405914, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405940, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405990, 0x20); - if (lane1_protocol == 3) - Xil_Out32(0xFD405924, 0x37); + Xil_Out32(0xFD080200U, 0x100091C7U); - if (lane2_protocol == 3) - Xil_Out32(0xFD409914, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409940, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409990, 0x20); - if (lane2_protocol == 3) - Xil_Out32(0xFD409924, 0x37); + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D914, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D940, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D990, 0x20); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D924, 0x37); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); return 1; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index e311aa772ccedace7edb5146bb760814999e2f0c..106c3953e1fca68149267b0d760ccf2b3a04e652 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -44,278 +45,10 @@ #include "pm_cfg_obj.h" -#define ZYNQMP_VERSION_SIZE 7 -#define EFUSE_VCU_DIS_MASK 0x100 -#define EFUSE_VCU_DIS_SHIFT 8 -#define EFUSE_GPU_DIS_MASK 0x20 -#define EFUSE_GPU_DIS_SHIFT 5 -#define IDCODE2_PL_INIT_MASK 0x200 -#define IDCODE2_PL_INIT_SHIFT 9 - DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; - -enum { - ZYNQMP_VARIANT_EG = BIT(0U), - ZYNQMP_VARIANT_EV = BIT(1U), - ZYNQMP_VARIANT_CG = BIT(2U), - ZYNQMP_VARIANT_DR = BIT(3U), -}; - -static const struct { - u32 id; - u8 device; - u8 variants; -} zynqmp_devices[] = { - { - .id = 0x04688093, - .device = 1, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04711093, - .device = 2, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04710093, - .device = 3, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04721093, - .device = 4, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | - ZYNQMP_VARIANT_EV, - }, - { - .id = 0x04720093, - .device = 5, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | - ZYNQMP_VARIANT_EV, - }, - { - .id = 0x04739093, - .device = 6, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04730093, - .device = 7, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | - ZYNQMP_VARIANT_EV, - }, - { - .id = 0x04738093, - .device = 9, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04740093, - .device = 11, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04750093, - .device = 15, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04759093, - .device = 17, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04758093, - .device = 19, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x047E1093, - .device = 21, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E3093, - .device = 23, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E5093, - .device = 25, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E4093, - .device = 27, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E0093, - .device = 28, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E2093, - .device = 29, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E6093, - .device = 39, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FD093, - .device = 43, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047F8093, - .device = 46, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FF093, - .device = 47, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FB093, - .device = 48, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FE093, - .device = 49, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x046d0093, - .device = 67, - .variants = ZYNQMP_VARIANT_DR, - }, -}; - -static const struct { - u32 id; - char *name; -} zynqmp_svd_devices[] = { - { - .id = 0x04714093, - .name = "xck24" - }, - { - .id = 0x04724093, - .name = "xck26", - }, -}; - -static char *zynqmp_detect_svd_name(u32 idcode) -{ - u32 i; - - for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) { - if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF)) - return zynqmp_svd_devices[i].name; - } - - return "unknown"; -} - -static char *zynqmp_get_silicon_idcode_name(void) -{ - u32 i; - u32 idcode, idcode2; - char name[ZYNQMP_VERSION_SIZE]; - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload); - if (ret) { - debug("%s: Getting chipid failed\n", __func__); - return "unknown"; - } - - /* - * Firmware returns: - * payload[0][31:0] = status of the operation - * payload[1]] = IDCODE - * payload[2][19:0] = Version - * payload[2][28:20] = EXTENDED_IDCODE - * payload[2][29] = PL_INIT - */ - - idcode = ret_payload[1]; - idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT; - debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode, - idcode2); - - for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { - if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF)) - break; - } - - if (i >= ARRAY_SIZE(zynqmp_devices)) - return zynqmp_detect_svd_name(idcode); - - /* Add device prefix to the name */ - ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d", - zynqmp_devices[i].device); - if (ret < 0) - return "unknown"; - - if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) { - /* Devices with EV variant might be EG/CG/EV family */ - if (idcode2 & IDCODE2_PL_INIT_MASK) { - u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >> - EFUSE_VCU_DIS_SHIFT) << 1 | - ((idcode2 & EFUSE_GPU_DIS_MASK) >> - EFUSE_GPU_DIS_SHIFT); - - /* - * Get family name based on extended idcode values as - * determined on UG1087, EXTENDED_IDCODE register - * description - */ - switch (family) { - case 0x00: - strncat(name, "ev", 2); - break; - case 0x10: - strncat(name, "eg", 2); - break; - case 0x11: - strncat(name, "cg", 2); - break; - default: - /* Do not append family name*/ - break; - } - } else { - /* - * When PL powered down the VCU Disable efuse cannot be - * read. So, ignore the bit and just findout if it is CG - * or EG/EV variant. - */ - strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : - "e", 2); - } - } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) { - /* Devices with CG variant might be EG or CG family */ - strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2); - } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) { - strncat(name, "eg", 2); - } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) { - strncat(name, "dr", 2); - } else { - debug("Variant not identified\n"); - } - - return strdup(name); -} #endif int __maybe_unused psu_uboot_init(void) @@ -406,6 +139,11 @@ static void print_secure_boot(void) int board_init(void) { +#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) + struct udevice *soc; + char name[SOC_MAX_STR_SIZE]; + int ret; +#endif #if defined(CONFIG_ZYNQMP_FIRMWARE) struct udevice *dev; @@ -432,10 +170,15 @@ int board_init(void) printf("EL Level:\tEL%d\n", current_el()); #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) - zynqmppl.name = zynqmp_get_silicon_idcode_name(); - printf("Chip ID:\t%s\n", zynqmppl.name); - fpga_init(); - fpga_add(fpga_xilinx, &zynqmppl); + ret = soc_get(&soc); + if (!ret) { + ret = soc_get_machine(soc, name, sizeof(name)); + if (ret >= 0) { + zynqmppl.name = strdup(name); + fpga_init(); + fpga_add(fpga_xilinx, &zynqmppl); + } + } #endif /* display secure boot information */ @@ -924,6 +667,7 @@ void set_dfu_alt_info(char *interface, char *devstr) bootseq, multiboot, bootseq, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq); break; +#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: snprintf(buf, DFU_ALT_BUF_LEN, @@ -932,6 +676,7 @@ void set_dfu_alt_info(char *interface, char *devstr) multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, CONFIG_SYS_SPI_U_BOOT_OFFS); break; +#endif default: return; } diff --git a/boot/Kconfig b/boot/Kconfig index 08451c65a56b9c6882f71faa47ebf74259653b23..17438b566d5c574a351b3360dc471dcaed48b3ad 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -555,8 +555,12 @@ config CHROMEOS_VBOOT distinguishing between booting Chrome OS in a basic way (developer mode) and a full boot. +config SYS_RAMBOOT + bool + config RAMBOOT_PBL bool "Freescale PBL(pre-boot loader) image format support" + select SYS_RAMBOOT if PPC help Some SoCs use PBL to load RCW and/or pre-initialization instructions. For more details refer to doc/README.pblimage @@ -575,6 +579,19 @@ config SPIFLASH endchoice +config FSL_FIXED_MMC_LOCATION + bool "PBL MMC is at a fixed location" + depends on SDCARD && !RAMBOOT_PBL + +config ESDHC_HC_BLK_ADDR + def_bool y + depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_BSC9132 || ARCH_P1010) + help + In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and + code length of these soc specify the memory address in block address + format. Block length is fixed to 512 bytes as per the SD High + Capacity specification. + config SYS_FSL_PBL_PBI string "PBI(pre-boot instructions) commands for the PBL image" depends on RAMBOOT_PBL @@ -589,6 +606,14 @@ config SYS_FSL_PBL_RCW Enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details. +config SYS_BOOT_RAMDISK_HIGH + depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ + depends on !(NIOS2 || SANDBOX || SH || XTENSA) + def_bool y + help + Enable initrd_high functionality. If defined then the initrd_high + feature is enabled and the boot* ramdisk subcommand is enabled. + endmenu # Boot images menu "Boot timing" @@ -613,7 +638,7 @@ config BOOTSTAGE config SPL_BOOTSTAGE bool "Boot timing and reported in SPL" - depends on BOOTSTAGE + depends on BOOTSTAGE && SPL help Enable recording of boot time in SPL. To make this visible to U-Boot proper, enable BOOTSTAGE_STASH as well. This will stash the timing @@ -622,7 +647,7 @@ config SPL_BOOTSTAGE config TPL_BOOTSTAGE bool "Boot timing and reported in TPL" - depends on BOOTSTAGE + depends on BOOTSTAGE && TPL help Enable recording of boot time in SPL. To make this visible to U-Boot proper, enable BOOTSTAGE_STASH as well. This will stash the timing diff --git a/boot/bootm.c b/boot/bootm.c index 714406ab668de8d6f6215591ed84f1645eb0de71..86dbfbcfed5b758063870dd28a3d39a03473df27 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -33,11 +33,6 @@ #include #include -#ifndef CONFIG_SYS_BOOTM_LEN -/* use 8MByte as default max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN 0x800000 -#endif - #define MAX_CMDLINE_SIZE SZ_4K #define IH_INITRD_ARCH IH_ARCH_DEFAULT @@ -369,10 +364,12 @@ static int bootm_find_other(struct cmd_tbl *cmdtp, int flag, int argc, * * @comp_type: Compression type being used (IH_COMP_...) * @uncomp_size: Number of bytes uncompressed + * @buf_size: Number of bytes the decompresion buffer was * @ret: errno error code received from compression library * Return: Appropriate BOOTM_ERR_ error code */ -static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret) +static int handle_decomp_error(int comp_type, size_t uncomp_size, + size_t buf_size, int ret) { const char *name = genimg_get_comp_name(comp_type); @@ -380,7 +377,7 @@ static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret) if (ret == -ENOSYS) return BOOTM_ERR_UNIMPLEMENTED; - if (uncomp_size >= CONFIG_SYS_BOOTM_LEN) + if (uncomp_size >= buf_size) printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n"); else printf("%s: uncompress error %d\n", name, ret); @@ -420,7 +417,8 @@ static int bootm_load_os(bootm_headers_t *images, int boot_progress) load_buf, image_buf, image_len, CONFIG_SYS_BOOTM_LEN, &load_end); if (err) { - err = handle_decomp_error(os.comp, load_end - load, err); + err = handle_decomp_error(os.comp, load_end - load, + CONFIG_SYS_BOOTM_LEN, err); bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } @@ -498,7 +496,8 @@ ulong bootm_disable_interrupts(void) } #define CONSOLE_ARG "console=" -#define CONSOLE_ARG_SIZE sizeof(CONSOLE_ARG) +#define NULL_CONSOLE (CONSOLE_ARG "ttynull") +#define CONSOLE_ARG_SIZE sizeof(NULL_CONSOLE) /** * fixup_silent_linux() - Handle silencing the linux boot if required @@ -550,21 +549,22 @@ static int fixup_silent_linux(char *buf, int maxlen) char *end = strchr(start, ' '); int start_bytes; - start_bytes = start - cmdline + CONSOLE_ARG_SIZE - 1; + start_bytes = start - cmdline; strncpy(buf, cmdline, start_bytes); + strncpy(buf + start_bytes, NULL_CONSOLE, CONSOLE_ARG_SIZE); if (end) - strcpy(buf + start_bytes, end); + strcpy(buf + start_bytes + CONSOLE_ARG_SIZE - 1, end); else - buf[start_bytes] = '\0'; + buf[start_bytes + CONSOLE_ARG_SIZE] = '\0'; } else { - sprintf(buf, "%s %s", cmdline, CONSOLE_ARG); + sprintf(buf, "%s %s", cmdline, NULL_CONSOLE); } if (buf + strlen(buf) >= cmdline) return -ENOSPC; } else { - if (maxlen < sizeof(CONSOLE_ARG)) + if (maxlen < CONSOLE_ARG_SIZE) return -ENOSPC; - strcpy(buf, CONSOLE_ARG); + strcpy(buf, NULL_CONSOLE); } debug("after silent fix-up: %s\n", buf); @@ -1004,7 +1004,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type, ulong data, len; bootm_headers_t images; int noffset; - ulong load_end; + ulong load_end, buf_size; uint8_t image_type; uint8_t imape_comp; void *load_buf; @@ -1030,14 +1030,14 @@ static int bootm_host_load_image(const void *fit, int req_image_type, } /* Allow the image to expand by a factor of 4, should be safe */ - load_buf = malloc((1 << 20) + len * 4); + buf_size = (1 << 20) + len * 4; + load_buf = malloc(buf_size); ret = image_decomp(imape_comp, 0, data, image_type, load_buf, - (void *)data, len, CONFIG_SYS_BOOTM_LEN, - &load_end); + (void *)data, len, buf_size, &load_end); free(load_buf); if (ret) { - ret = handle_decomp_error(imape_comp, load_end - 0, ret); + ret = handle_decomp_error(imape_comp, load_end - 0, buf_size, ret); if (ret != BOOTM_ERR_UNIMPLEMENTED) return ret; } diff --git a/boot/image-board.c b/boot/image-board.c index 0d2e0fc9692e8f09b0f2a720a65c0878a1926b2a..cfc1c658e3a612d3de26a1df1cb51a962c988d16 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -21,10 +21,6 @@ #include #include -#ifndef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE 512 -#endif - DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) @@ -827,6 +823,7 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, return 0; } +#ifdef CONFIG_SYS_BOOT_GET_CMDLINE /** * boot_get_cmdline - allocate and initialize kernel cmdline * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -900,6 +897,7 @@ int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd) return 0; } +#endif int image_setup_linux(bootm_headers_t *images) { diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c index 78d89069a98d6d96fdd2fa89b43de8fb24386757..5ab9ae18746021feb47225f75fa2afbe68530751 100644 --- a/boot/image-pre-load.c +++ b/boot/image-pre-load.c @@ -23,11 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; #define IMAGE_PRE_LOAD_PROP_PUBLIC_KEY "public-key" #define IMAGE_PRE_LOAD_PROP_MANDATORY "mandatory" -#ifndef CONFIG_SYS_BOOTM_LEN -/* use 8MByte as default max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN 0x800000 -#endif - /* * Information in the device-tree about the signature in the header */ diff --git a/cmd/Kconfig b/cmd/Kconfig index 09193b61b95f4b07818081f9c7addee12d3e5773..d5f842136cff6a606a199fbe234aab4f2aa623f6 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -71,6 +71,23 @@ config SYS_PROMPT_HUSH_PS2 printed when the command interpreter needs more input to complete a command. Usually "> ". +config SYS_MAXARGS + int "Maximum number arguments accepted by commands" + default 16 + +config SYS_CBSIZE + int "Console input buffer size" + default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \ + RCAR_GEN3 || TARGET_SOCFPGA_SOC64 + default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \ + FSL_LSCH3 || X86 + default 256 if M68K || PPC + default 1024 + +config SYS_PBSIZE + int "Buffer size for console output" + default 1044 + config SYS_XTRACE bool "Command execution tracer" depends on CMDLINE @@ -318,6 +335,16 @@ config BOOTM_VXWORKS help Support booting VxWorks images via the bootm command. +config SYS_BOOTM_LEN + hex "Maximum size of a decompresed OS image" + depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ + default 0x4000000 if PPC || ARM64 + default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 + default 0x800000 + help + This is the maximum size of the buffer that is used to decompress the OS + image in to, if passing a compressed image to bootm/booti/bootz. + config CMD_BOOTEFI bool "bootefi" depends on EFI_LOADER @@ -1143,6 +1170,11 @@ config CMD_LOADB help Load a binary file over serial line. +config CMD_LOADM + bool "loadm" + help + Load a binary over memory mapped. + config CMD_LOADS bool "loads" default y @@ -1276,6 +1308,10 @@ config CMD_ONENAND and erasing blocks. It allso provides a way to show and change bad blocks, and test the device. +config USE_ONENAND_BOARD_INIT + bool "Call onenand_board_init() in the onenand command" + depends on CMD_ONENAND + config CMD_OSD bool "osd" help @@ -1715,6 +1751,15 @@ config NFS_TIMEOUT "ERROR: Cannot umount" in nfs command, try longer timeout such as 10000. +config SYS_DISABLE_AUTOLOAD + bool "Disable automatically loading files over the network" + depends on CMD_BOOTP || CMD_DHCP || CMD_NFS || CMD_RARP + help + Typically, commands such as "dhcp" will attempt to automatically + load a file from the network, once the initial network configuration + is complete. Enable this option to disable this behavior and instead + require files to be loaded over the network by subsequent commands. + config CMD_MII bool "mii" imply CMD_MDIO @@ -2552,6 +2597,7 @@ config CMD_UBIFS depends on CMD_UBI default y if CMD_UBI select LZO + select GZIP help UBIFS is a file system for flash devices which works on top of UBI. diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 827fcd97dfd840932b13dc48f1017dee1996c33d..37ce659fa123f4b2db90216181f9d090f1fe85cb 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -34,6 +34,18 @@ static struct efi_device_path *bootefi_device_path; static void *image_addr; static size_t image_size; +/** + * efi_get_image_parameters() - return image parameters + * + * @img_addr: address of loaded image in memory + * @img_size: size of loaded image + */ +void efi_get_image_parameters(void **img_addr, size_t *img_size) +{ + *img_addr = image_addr; + *img_size = image_size; +} + /** * efi_clear_bootdev() - clear boot device */ diff --git a/cmd/cpu.c b/cmd/cpu.c index 67dbb044b53113229e448320cf0d53adabe21d3f..2ca4d05ae8adacf4a43cac10c93182c2a5796ee2 100644 --- a/cmd/cpu.c +++ b/cmd/cpu.c @@ -82,36 +82,13 @@ static int do_cpu_detail(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } -static struct cmd_tbl cmd_cpu_sub[] = { - U_BOOT_CMD_MKENT(list, 2, 1, do_cpu_list, "", ""), - U_BOOT_CMD_MKENT(detail, 4, 0, do_cpu_detail, "", ""), -}; - -/* - * Process a cpu sub-command - */ -static int do_cpu(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct cmd_tbl *c = NULL; - - /* Strip off leading 'cpu' command argument */ - argc--; - argv++; - - if (argc) - c = find_cmd_tbl(argv[0], cmd_cpu_sub, - ARRAY_SIZE(cmd_cpu_sub)); - - if (c) - return c->cmd(cmdtp, flag, argc, argv); - else - return CMD_RET_USAGE; -} - -U_BOOT_CMD( - cpu, 2, 1, do_cpu, - "display information about CPUs", +#if CONFIG_IS_ENABLED(SYS_LONGHELP) +static char cpu_help_text[] = "list - list available CPUs\n" "cpu detail - show CPU detail" -); + ; +#endif + +U_BOOT_CMD_WITH_SUBCMDS(cpu, "display information about CPUs", cpu_help_text, + U_BOOT_SUBCMD_MKENT(list, 1, 1, do_cpu_list), + U_BOOT_SUBCMD_MKENT(detail, 1, 0, do_cpu_detail)); diff --git a/cmd/dm.c b/cmd/dm.c index 1dd19fe45b5490c9ef58dec2c11d72609a5c3ebe..eb40f0865fe0776bcad9d3bb55793de94223865c 100644 --- a/cmd/dm.c +++ b/cmd/dm.c @@ -8,26 +8,13 @@ #include #include -#include -#include -#include -#include -#include #include #include -static int do_dm_dump_all(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - dm_dump_all(); - - return 0; -} - -static int do_dm_dump_uclass(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +static int do_dm_dump_driver_compat(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) { - dm_dump_uclass(); + dm_dump_driver_compat(); return 0; } @@ -48,71 +35,68 @@ static int do_dm_dump_drivers(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } -static int do_dm_dump_driver_compat(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) +#if CONFIG_IS_ENABLED(DM_STATS) +static int do_dm_dump_mem(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { - dm_dump_driver_compat(); + struct dm_stats mem; + + dm_get_mem(&mem); + dm_dump_mem(&mem); return 0; } +#endif /* DM_STATS */ -static int do_dm_dump_static_driver_info(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) +static int do_dm_dump_static_driver_info(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) { dm_dump_static_driver_info(); return 0; } -static struct cmd_tbl test_commands[] = { - U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""), - U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""), - U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""), - U_BOOT_CMD_MKENT(drivers, 1, 1, do_dm_dump_drivers, "", ""), - U_BOOT_CMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat, "", ""), - U_BOOT_CMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info, "", ""), -}; - -static __maybe_unused void dm_reloc(void) +static int do_dm_dump_tree(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { - static int relocated; + dm_dump_tree(); - if (!relocated) { - fixup_cmdtable(test_commands, ARRAY_SIZE(test_commands)); - relocated = 1; - } + return 0; } -static int do_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int do_dm_dump_uclass(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { - struct cmd_tbl *test_cmd; - int ret; - -#ifdef CONFIG_NEEDS_MANUAL_RELOC - dm_reloc(); -#endif - - if (argc < 2) - return CMD_RET_USAGE; - test_cmd = find_cmd_tbl(argv[1], test_commands, - ARRAY_SIZE(test_commands)); - argc -= 2; - argv += 2; - if (!test_cmd || argc > test_cmd->maxargs) - return CMD_RET_USAGE; - - ret = test_cmd->cmd(test_cmd, flag, argc, argv); + dm_dump_uclass(); - return cmd_process_error(test_cmd, ret); + return 0; } -U_BOOT_CMD( - dm, 3, 1, do_dm, - "Driver model low level access", - "tree Dump driver model tree ('*' = activated)\n" - "dm uclass Dump list of instances for each uclass\n" +#if CONFIG_IS_ENABLED(DM_STATS) +#define DM_MEM_HELP "dm mem Provide a summary of memory usage\n" +#define DM_MEM U_BOOT_SUBCMD_MKENT(mem, 1, 1, do_dm_dump_mem), +#else +#define DM_MEM_HELP +#define DM_MEM +#endif + +#if CONFIG_IS_ENABLED(SYS_LONGHELP) +static char dm_help_text[] = + "compat Dump list of drivers with compatibility strings\n" "dm devres Dump list of device resources for each device\n" "dm drivers Dump list of drivers with uclass and instances\n" - "dm compat Dump list of drivers with compatibility strings\n" - "dm static Dump list of drivers with static platform data" -); + DM_MEM_HELP + "dm static Dump list of drivers with static platform data\n" + "dn tree Dump tree of driver model devices ('*' = activated)\n" + "dm uclass Dump list of instances for each uclass" + ; +#endif + +U_BOOT_CMD_WITH_SUBCMDS(dm, "Driver model low level access", dm_help_text, + U_BOOT_SUBCMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat), + U_BOOT_SUBCMD_MKENT(devres, 1, 1, do_dm_dump_devres), + U_BOOT_SUBCMD_MKENT(drivers, 1, 1, do_dm_dump_drivers), + DM_MEM + U_BOOT_SUBCMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info), + U_BOOT_SUBCMD_MKENT(tree, 1, 1, do_dm_dump_tree), + U_BOOT_SUBCMD_MKENT(uclass, 1, 1, do_dm_dump_uclass)); diff --git a/cmd/load.c b/cmd/load.c index 7e4a552d90efc29e5ae61578ca51e0036145bf65..1224a7f85bb37b52126aed10098cb9adec87e920 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -1063,6 +1063,44 @@ static ulong load_serial_ymodem(ulong offset, int mode) #endif +#if defined(CONFIG_CMD_LOADM) +static int do_load_memory_bin(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr, dest, size; + void *src, *dst; + + if (argc != 4) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + dest = simple_strtoul(argv[2], NULL, 16); + + size = simple_strtoul(argv[3], NULL, 16); + + if (!size) { + printf("loadm: can not load zero bytes\n"); + return 1; + } + + src = map_sysmem(addr, size); + dst = map_sysmem(dest, size); + + memcpy(dst, src, size); + + unmap_sysmem(src); + unmap_sysmem(dst); + + if (IS_ENABLED(CONFIG_CMD_BOOTEFI)) + efi_set_bootdev("Mem", "", "", map_sysmem(dest, 0), size); + + printf("loaded bin to memory: size: %lu\n", size); + + return 0; +} +#endif + /* -------------------------------------------------------------------- */ #if defined(CONFIG_CMD_LOADS) @@ -1137,3 +1175,13 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LOADB */ + +#if defined(CONFIG_CMD_LOADM) +U_BOOT_CMD( + loadm, 4, 0, do_load_memory_bin, + "load binary blob from source address to destination address", + "[src_addr] [dst_addr] [size]\n" + " - load a binary blob from one memory location to other" + " from src_addr to dst_addr by size bytes" +); +#endif /* CONFIG_CMD_LOADM */ diff --git a/cmd/misc.c b/cmd/misc.c index bcd8d960ee06141447ccd2ed9291dabf2cb64f08..ec32b41ed1e96f01bcc27b1d3d2a6226d8966bed 100644 --- a/cmd/misc.c +++ b/cmd/misc.c @@ -44,7 +44,6 @@ static int do_misc_list(struct cmd_tbl *cmdtp, int flag, static int do_misc_op(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], enum misc_op op) { - int (*misc_op)(struct udevice *, int, void *, int); struct udevice *dev; int offset; void *buf; @@ -62,11 +61,10 @@ static int do_misc_op(struct cmd_tbl *cmdtp, int flag, size = hextoul(argv[3], NULL); if (op == MISC_OP_READ) - misc_op = misc_read; + ret = misc_read(dev, offset, buf, size); else - misc_op = misc_write; + ret = misc_write(dev, offset, buf, size); - ret = misc_op(dev, offset, buf, size); if (ret < 0) { if (ret == -ENOSYS) { printf("The device does not support %s\n", diff --git a/cmd/qfw.c b/cmd/qfw.c index d58615040c64dc110fd5aac1dcfe46846668d136..ccbc967ca9f698b37a98c8557ba09c2199d2296f 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -25,15 +25,17 @@ static int qemu_fwcfg_cmd_setup_kernel(void *load_addr, void *initrd_addr) qfw_read_entry(qfw_dev, FW_CFG_SETUP_SIZE, 4, &setup_size); qfw_read_entry(qfw_dev, FW_CFG_KERNEL_SIZE, 4, &kernel_size); - if (setup_size == 0 || kernel_size == 0) { + if (kernel_size == 0) { printf("warning: no kernel available\n"); return -1; } data_addr = load_addr; - qfw_read_entry(qfw_dev, FW_CFG_SETUP_DATA, - le32_to_cpu(setup_size), data_addr); - data_addr += le32_to_cpu(setup_size); + if (setup_size != 0) { + qfw_read_entry(qfw_dev, FW_CFG_SETUP_DATA, + le32_to_cpu(setup_size), data_addr); + data_addr += le32_to_cpu(setup_size); + } qfw_read_entry(qfw_dev, FW_CFG_KERNEL_DATA, le32_to_cpu(kernel_size), data_addr); diff --git a/common/Kconfig b/common/Kconfig index a96842a5c11dd7bd2b432e14c7eee99c2a4ab69c..e7914ca750a3eb601a5d060aa31ad0c93ac07c24 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -83,14 +83,17 @@ config LOGLEVEL config SPL_LOGLEVEL int + depends on SPL default LOGLEVEL config TPL_LOGLEVEL int + depends on TPL default LOGLEVEL config VPL_LOGLEVEL int "loglevel for VPL" + depends on VPL default LOGLEVEL help All Messages with a loglevel smaller than the console loglevel will @@ -271,15 +274,6 @@ config LOG if LOG -config VPL_LOG - bool "Enable logging support in VPL" - depends on LOG - help - This enables support for logging of status and debug messages. These - can be displayed on the console, recorded in a memory buffer, or - discarded if not needed. Logging supports various categories and - levels of severity. - config LOG_MAX_LEVEL int "Maximum log level to record" default 6 @@ -365,7 +359,7 @@ config LOG_SYSLOG config SPL_LOG bool "Enable logging support in SPL" - depends on LOG + depends on LOG && SPL help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or @@ -408,7 +402,7 @@ endif config TPL_LOG bool "Enable logging support in TPL" - depends on LOG + depends on LOG && TPL help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or @@ -451,7 +445,7 @@ endif config VPL_LOG bool "Enable logging support in VPL" - depends on LOG + depends on LOG && VPL help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or @@ -659,6 +653,18 @@ config MISC_INIT_R help Enabling this option calls 'misc_init_r' function +config SYS_MALLOC_BOOTPARAMS + bool "Malloc a buffer to use for bootparams" + help + In some cases rather than using a known location to store the + bi_boot_params portion of gd we need to allocate it from our malloc pool. + +config SYS_BOOTPARAMS_LEN + hex "Size of the bootparam buffer to malloc in bytes" + depends on SYS_MALLOC_BOOTPARAMS + default 0x20000 if MIPS || RCAR_GEN3 + default 0x10000 + config ID_EEPROM bool "Enable I2C connected system identifier EEPROM" help diff --git a/common/Makefile b/common/Makefile index 75c24e32492766d933b784d17ed7c974359215c4..2ed8672c3ac1bd3a34c8c7ddfe78b5f1fd40c088 100644 --- a/common/Makefile +++ b/common/Makefile @@ -23,10 +23,9 @@ obj-$(CONFIG_MII) += miiphyutil.o obj-$(CONFIG_CMD_MII) += miiphyutil.o obj-$(CONFIG_PHYLIB) += miiphyutil.o -ifdef CONFIG_USB -obj-y += usb.o usb_hub.o +obj-$(CONFIG_USB_HOST) += usb.o usb_hub.o +obj-$(CONFIG_USB_GADGET) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o -endif # others obj-$(CONFIG_CONSOLE_MUX) += iomux.o @@ -57,13 +56,9 @@ endif obj-$(CONFIG_SPL_NET) += miiphyutil.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o -ifdef CONFIG_SPL_USB_HOST -obj-y += usb.o -obj-y += usb_hub.o +obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o -else -obj-$(CONFIG_USB_MUSB_HOST) += usb.o -endif +obj-$(CONFIG_SPL_MUSB_NEW) += usb.o endif # CONFIG_SPL_BUILD #others diff --git a/common/board_f.c b/common/board_f.c index 51d2f3c365e9dfcb3fca62e6e3212e39e3df2aad..5c86faeb217bedbceeaec993e0b5d0d0b4d456e5 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -400,13 +400,9 @@ static int reserve_video(void) ((unsigned long)gd->relocaddr - addr) >> 10, addr); gd->relocaddr = addr; #elif defined(CONFIG_LCD) -# ifdef CONFIG_FB_ADDR - gd->fb_base = CONFIG_FB_ADDR; -# else /* reserve memory for LCD display (always full pages) */ gd->relocaddr = lcd_setmem(gd->relocaddr); gd->fb_base = gd->relocaddr; -# endif /* CONFIG_FB_ADDR */ #endif return 0; @@ -684,6 +680,8 @@ static int setup_reloc(void) #ifdef CONFIG_SYS_TEXT_BASE #ifdef ARM gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; +#elif defined(CONFIG_MICROBLAZE) + gd->reloc_off = gd->relocaddr - (u32)_start; #elif defined(CONFIG_M68K) /* * On all ColdFire arch cpu, monitor code starts always diff --git a/common/board_r.c b/common/board_r.c index 6f4aca2077d667927d873de8479aa218ab74e9e9..ed29069d2de6d2638e855e5908700c7a84dd8408 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -457,7 +457,7 @@ static int initr_env(void) return 0; } -#ifdef CONFIG_SYS_BOOTPARAMS_LEN +#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS static int initr_malloc_bootparams(void) { gd->bd->bi_boot_params = (ulong)malloc(CONFIG_SYS_BOOTPARAMS_LEN); @@ -469,18 +469,6 @@ static int initr_malloc_bootparams(void) } #endif -#ifdef CONFIG_CMD_NET -static int initr_ethaddr(void) -{ - struct bd_info *bd = gd->bd; - - /* kept around for legacy kernels only ... ignore the next section */ - eth_env_get_enetaddr("ethaddr", bd->bi_enetaddr); - - return 0; -} -#endif /* CONFIG_CMD_NET */ - #if defined(CONFIG_LED_STATUS) static int initr_status_led(void) { @@ -612,6 +600,9 @@ static init_fnc_t init_sequence_r[] = { */ #endif initr_reloc_global_data, +#if CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC) && CONFIG_IS_ENABLED(EVENT) + event_manual_reloc, +#endif #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) initr_unlock_ram_in_cache, #endif @@ -713,7 +704,7 @@ static init_fnc_t init_sequence_r[] = { initr_pvblock, #endif initr_env, -#ifdef CONFIG_SYS_BOOTPARAMS_LEN +#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS initr_malloc_bootparams, #endif INIT_FUNC_WATCHDOG_RESET @@ -756,9 +747,6 @@ static init_fnc_t init_sequence_r[] = { initr_status_led, #endif /* PPC has a udelay(20) here dating from 2002. Why? */ -#ifdef CONFIG_CMD_NET - initr_ethaddr, -#endif #if defined(CONFIG_GPIO_HOG) gpio_hog_probe_all, #endif diff --git a/common/event.c b/common/event.c index 9d67a060a021f73763a3dbc75b9c44602446ba75..af1ed4121d8a86cb01a4f678f4381b8c6ecc9d70 100644 --- a/common/event.c +++ b/common/event.c @@ -17,6 +17,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -148,6 +149,20 @@ void event_show_spy_list(void) } } +#if CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC) +int event_manual_reloc(void) +{ + struct evspy_info *spy, *end; + + spy = ll_entry_start(struct evspy_info, evspy_info); + end = ll_entry_end(struct evspy_info, evspy_info); + for (; spy < end; spy++) + MANUAL_RELOC(spy->func); + + return 0; +} +#endif + #if CONFIG_IS_ENABLED(EVENT_DYNAMIC) static void spy_free(struct event_spy *spy) { @@ -159,8 +174,6 @@ int event_register(const char *id, enum event_t type, event_handler_t func, void struct event_state *state = gd_event_state(); struct event_spy *spy; - if (!CONFIG_IS_ENABLED(EVENT_DYNAMIC)) - return -ENOSYS; spy = malloc(sizeof(*spy)); if (!spy) return log_msg_ret("alloc", -ENOMEM); diff --git a/common/init/board_init.c b/common/init/board_init.c index eab5ee139536afee605c77506f3748f70b422d22..6a550261778d54e0f329ec8ad04540f171994fb4 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,8 +78,10 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ +#ifndef CONFIG_MALLOC_F_ADDR #if CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); +#endif #endif /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */ top = rounddown(top-sizeof(struct global_data), 16); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 50ff113cab21c60ea84e7dbb399ebf50a6ad6496..931619c366f3307464ccd75a6b07c8ecda9278e1 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1,5 +1,3 @@ -menu "SPL / TPL / VPL" - config SUPPORT_SPL bool @@ -13,15 +11,16 @@ config SPL_DFU_NO_RESET bool config SPL - bool + bool "Enable SPL" depends on SUPPORT_SPL - prompt "Enable SPL" help If you want to build SPL as well as the normal image, say Y. +menu "SPL configuration options" + depends on SPL + config SPL_FRAMEWORK bool "Support SPL based upon the common SPL framework" - depends on SPL default y help Enable the SPL framework under common/spl/. This framework @@ -39,7 +38,6 @@ config SPL_FRAMEWORK_BOARD_INIT_F config SPL_SIZE_LIMIT hex "Maximum size of SPL image" - depends on SPL default 0x11000 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB default 0x0 @@ -75,6 +73,90 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK of SRAM available for SPL when the stack required before reolcation uses this SRAM, too. +config SPL_MAX_SIZE + hex "Maximum size of the SPL image, excluding BSS" + default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB + default 0x1b000 if AM33XX && !TI_SECURE_DEVICE + default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB + default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000 + default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616 + default 0x7000 if RCAR_GEN3 + default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 + default 0x10000 if ASPEED_AST2600 + default 0x0 + help + Maximum size of the SPL image (text, data, rodata, and linker lists + sections), BSS excluded. When defined, the linker checks that the + actual size does not exceed it. + +config SPL_PAD_TO + hex "Offset to which the SPL should be padded before appending the SPL payload" + default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB + default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB) + default 0x10000 if ARCH_KEYSTONE + default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616 + default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE + default SPL_MAX_SIZE + help + Image offset to which the SPL should be padded before appending the + SPL payload. By default, this is defined as CONFIG_SPL_MAX_SIZE, or 0 if + CONFIG_SPL_MAX_SIZE is undefined. CONFIG_SPL_PAD_TO must be either + 0, meaning to append the SPL payload without any padding, or >= + CONFIG_SPL_MAX_SIZE. + +config SPL_HAS_BSS_LINKER_SECTION + depends on SPL_FRAMEWORK + bool "Use a specific address for the BSS via the linker script" + default y if ARCH_SUNXI || ARCH_MX6 || ARCH_OMAP2PLUS || MIPS || RISCV + +config SPL_BSS_START_ADDR + hex "Link address for the BSS within the SPL binary" + depends on SPL_HAS_BSS_LINKER_SECTION + default 0x88200000 if (ARCH_MX6 && (MX6SX || MX6SL || MX6UL || MX6ULL)) || ARCH_MX7 + default 0x18200000 if ARCH_MX6 && !(MX6SX || MX6SL || MX6UL || MX6ULL) + default 0x80a00000 if ARCH_OMAP2PLUS + default 0x81f80000 if ARCH_SUNXI && MACH_SUNIV + default 0x4ff80000 if ARCH_SUNXI && !(MACH_SUN9I || MACH_SUNIV) + default 0x2ff80000 if ARCH_SUNXI && MACH_SUN9I + +choice + prompt "Enforce SPL BSS limit" + depends on !PPC + default SPL_BSS_LIMIT + help + In some platforms we only want to enforce a limit on the size of the + BSS in memory. On other platforms we need to enforce a limit on the + whole of the memory allocation as we're strictly limited to a small + typically non-DRAM location. Finally, other platforms do not enforce + a memory limit within SPL. + +config SPL_NO_BSS_LIMIT + bool "Do not enforce a build time limit on the size of the BSS" + +config SPL_BSS_LIMIT + bool "Enforce a limit on the size of the BSS only" + +config SPL_FOOTPRINT_LIMIT + bool "Enforce a limit on the whole of memory allocated to SPL, BSS included" + +endchoice + +config SPL_BSS_MAX_SIZE + hex "Maximum size in memory allocated to the SPL BSS" + depends on SPL_BSS_LIMIT + default 0x100000 if ARCH_MX6 || RISCV + default 0x80000 if ARCH_OMAP2PLUS || ARCH_SUNXI + help + When non-zero, the linker checks that the actual memory used by SPL + from __bss_start to __bss_end does not exceed it. + +config SPL_MAX_FOOTPRINT + hex "Maximum size in memory allocated to the SPL, BSS included" + depends on SPL_FOOTPRINT_LIMIT + help + When non-zero, the linker checks that the actual memory used by SPL + from _start to __bss_end does not exceed it. + config SPL_SYS_STACK_F_CHECK_BYTE hex default 0xaa @@ -109,40 +191,31 @@ config SPL_BINMAN_SYMBOLS depends on SPL_FRAMEWORK && BINMAN default y help - This enables use of symbols in SPL which refer to U-Boot, enabling SPL - to obtain the location of U-Boot simply by calling spl_get_image_pos() - and spl_get_image_size(). - - For this to work, you must have a U-Boot image in the binman image, so - binman can update SPL with the location of it. + This enables use of symbols in SPL which refer to other entries in + the same binman image as the SPL. These can be declared with the + binman_sym_declare(type, entry, prop) macro and accessed by the + binman_sym(type, entry, prop) macro defined in binman_sym.h. -menu "PowerPC and LayerScape SPL Boot options" + See tools/binman/binman.rst for a detailed explanation. -config SPL_NAND_BOOT - bool "Load SPL from NAND flash" - depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK) - -config SPL_MMC_BOOT - bool "Load SPL from SD Card / eMMC" - depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK) - -config SPL_SPI_BOOT - bool "Load SPL from SPI flash" - depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK) - -config SPL_FSL_PBL - bool "Create SPL in Freescale PBI format" - depends on (PPC || ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && \ - SUPPORT_SPL +config SPL_BINMAN_UBOOT_SYMBOLS + bool "Declare binman symbols for U-Boot phases in SPL" + depends on SPL_BINMAN_SYMBOLS + default n if ARCH_IMX8M + default y help - Create boot binary having SPL binary in PBI format concatenated with - u-boot binary. + This enables use of symbols in SPL which refer to U-Boot phases, + enabling SPL to obtain the location and size of its next phase simply + by calling spl_get_image_pos() and spl_get_image_size(). -endmenu + For this to work, you must have all U-Boot phases in the same binman + image, so binman can update SPL with the locations of everything. + +source "common/spl/Kconfig.nxp" config HANDOFF bool "Pass hand-off information from SPL to U-Boot proper" - depends on SPL && BLOBLIST + depends on BLOBLIST help It is useful to be able to pass information from SPL to U-Boot proper to preserve state that is known in SPL and is needed in U-Boot. @@ -150,8 +223,6 @@ config HANDOFF in boot. It is available in gd->handoff. The state state is set up in SPL (or TPL if that is being used). -if SPL - config SPL_HANDOFF bool "Pass hand-off information from SPL to U-Boot proper" depends on HANDOFF && SPL_BLOBLIST @@ -164,6 +235,18 @@ config SPL_HANDOFF config SPL_LDSCRIPT string "Linker script for the SPL stage" + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if ARCH_SUNXI && !MACH_SUNIV && !ARM64 + default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK + default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if ARCH_AT91 && CPU_ARM926EJS + default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if ARCH_AT91 && CPU_V7A + default "arch/arm/mach-omap2/u-boot-spl.lds" if ARCH_MX6 || ARCH_OMAP2PLUS || (ARCH_K3 && !ARM64) + default "arch/arm/mach-zynq/u-boot-spl.lds" if ARCH_ZYNQ + default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 + default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds" if ARCH_DAVINCI default "arch/\$(ARCH)/cpu/u-boot-spl.lds" help The SPL stage will usually require a different linker-script @@ -189,13 +272,6 @@ config SPL_BOARD_INIT spl_board_init() from board_init_r(). This function should be provided by the board. -config VPL_BOARD_INIT - bool "Call board-specific initialization in VPL" - help - If this option is enabled, U-Boot will call the function - spl_board_init() from board_init_r(). This function should be - provided by the board. - config SPL_BOOTROM_SUPPORT bool "Support returning to the BOOTROM" help @@ -246,23 +322,33 @@ config SPL_LEGACY_IMAGE_CRC_CHECK are correct, without further integrity checks. config SPL_SYS_MALLOC_SIMPLE - bool - prompt "Only use malloc_simple functions in the SPL" + bool "Only use malloc_simple functions in the SPL" help Say Y here to only use the *_simple malloc functions from malloc_simple.c, rather then using the versions from dlmalloc.c; this will make the SPL binary smaller at the cost of more heap usage as the *_simple malloc functions do not re-use free-ed mem. -config TPL_SYS_MALLOC_SIMPLE - bool - prompt "Only use malloc_simple functions in the TPL" - depends on TPL +config SPL_SHARES_INIT_SP_ADDR + bool "SPL and U-Boot use the same initial stack pointer location" + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + default n if ARCH_SUNXI || ARCH_MX6 || ARCH_MX7 + default y help - Say Y here to only use the *_simple malloc functions from - malloc_simple.c, rather then using the versions from dlmalloc.c; - this will make the TPL binary smaller at the cost of more heap - usage as the *_simple malloc functions do not re-use free-ed mem. + In many cases, we can use the same initial stack pointer address for + both SPL and U-Boot itself. If you need to specify a different address + however, say N here and then set a different value in CONFIG_SPL_STACK. + +config SPL_STACK + hex "Initial stack pointer location" + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + depends on !SPL_SHARES_INIT_SP_ADDR + default 0x946bb8 if ARCH_MX7 + default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB + default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB + help + Address of the start of the stack SPL will use before SDRAM is + initialized. config SPL_STACK_R bool "Enable SDRAM location for SPL stack" @@ -301,6 +387,23 @@ config SPL_SEPARATE_BSS location is used. Normally we put the device tree at the end of BSS but with this option enabled, it goes at _image_binary_end. +config SYS_SPL_MALLOC + bool "Enable malloc pool in SPL" + depends on SPL_FRAMEWORK + +config HAS_CUSTOM_SPL_MALLOC_START + bool "For the SPL malloc pool, define a custom starting address" + depends on SYS_SPL_MALLOC + +config CUSTOM_SYS_SPL_MALLOC_ADDR + hex "SPL malloc addr" + depends on HAS_CUSTOM_SPL_MALLOC_START + +config SYS_SPL_MALLOC_SIZE + hex "Size of the SPL malloc pool" + depends on SYS_SPL_MALLOC + default 0x100000 + config SPL_READ_ONLY bool depends on SPL_OF_PLATDATA @@ -314,16 +417,6 @@ config SPL_READ_ONLY writeable memory) of anything it wants to modify, such as device-private data. -config TPL_SEPARATE_BSS - bool "BSS section is in a different memory region from text" - default y if SPL_SEPARATE_BSS - help - Some platforms need a large BSS region in TPL and can provide this - because RAM is already set up. In this case BSS can be moved to RAM. - This option should then be enabled so that the correct device tree - location is used. Normally we put the device tree at the end of BSS - but with this option enabled, it goes at _image_binary_end. - config SPL_BANNER_PRINT bool "Enable output of the SPL banner 'U-Boot SPL ...'" default y @@ -332,15 +425,6 @@ config SPL_BANNER_PRINT info. Disabling this option could be useful to reduce SPL boot time (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). -config TPL_BANNER_PRINT - bool "Enable output of the TPL banner 'U-Boot TPL ...'" - depends on TPL - default y - help - If this option is enabled, TPL will print the banner with version - info. Disabling this option could be useful to reduce TPL boot time - (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). - config SPL_EARLY_BSS depends on ARM && !ARM64 bool "Allows initializing BSS early before entering board_init_f" @@ -591,6 +675,31 @@ config SPL_FS_FAT filesystem from within SPL. Support for the underlying block device (e.g. MMC or USB) must be enabled separately. +config SPL_FS_LOAD_PAYLOAD_NAME + string "File to load for U-Boot from the filesystem" + depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS + default "tispl.bin" if SYS_K3_SPL_ATF + default "u-boot.itb" if SPL_LOAD_FIT + default "u-boot.img" + help + Filename to read to load U-Boot when reading from filesystem. + +config SPL_FS_LOAD_KERNEL_NAME + string "File to load for the OS kernel from the filesystem" + depends on (SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS) && SPL_OS_BOOT + default "uImage" + help + Filename to read to load for the OS kernel when reading from the + filesystem. + +config SPL_FS_LOAD_ARGS_NAME + string "File to load for the OS kernel argument parameters from the filesystem" + depends on (SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS) && SPL_OS_BOOT + default "args" + help + Filename to read to load for the OS kernel argument parameters from + the filesystem. + config SPL_FAT_WRITE bool "Support write for FAT filesystems" help @@ -667,6 +776,7 @@ config SPL_LIBGENERIC_SUPPORT config SPL_DM_MAILBOX bool "Support Mailbox" + depends on SPL_DM help Enable support for Mailbox within SPL. This enable the inter processor communication protocols tobe used within SPL. Enable @@ -749,13 +859,23 @@ config SPL_NAND_SUPPORT This enables the drivers in drivers/mtd/nand/raw as part of an SPL build. +config SPL_NAND_RAW_ONLY + bool "Support to boot only raw u-boot.bin images" + depends on SPL_NAND_SUPPORT + help + Use this only if you need to save space. + config SPL_NAND_DRIVERS bool "Use standard NAND driver" help SPL uses normal NAND drivers, not minimal drivers. config SPL_NAND_ECC - bool "Include standard software ECC in the SPL" + bool "Include standard ECC in SPL" + +config SPL_NAND_SOFTECC + bool "Use software ECC in SPL" + depends on SPL_NAND_ECC config SPL_NAND_SIMPLE bool "Support simple NAND drivers in SPL" @@ -781,19 +901,9 @@ config SPL_UBI Enable support for loading payloads from UBI. See README.ubispl for more info. -if SPL_DM -config SPL_DM_SPI - bool "Support SPI DM drivers in SPL" - help - Enable support for SPI DM drivers in SPL. - -config SPL_DM_SPI_FLASH - bool "Support SPI DM FLASH drivers in SPL" - help - Enable support for SPI DM flash drivers in SPL. +menu "UBI configuration for SPL" + depends on SPL_UBI -endif -if SPL_UBI config SPL_UBI_LOAD_BY_VOLNAME bool "Support loading volumes by name" help @@ -803,58 +913,49 @@ config SPL_UBI_LOAD_BY_VOLNAME config SPL_UBI_MAX_VOL_LEBS int "Maximum number of LEBs per volume" - depends on SPL_UBI help The maximum number of logical eraseblocks which a static volume to load can contain. Used for sizing the scan data structure. config SPL_UBI_MAX_PEB_SIZE int "Maximum PEB size" - depends on SPL_UBI help The maximum physical erase block size. config SPL_UBI_MAX_PEBS int "Maximum number of PEBs" - depends on SPL_UBI help The maximum physical erase block size. If not overridden by board code, this value will be used as the actual number of PEBs. config SPL_UBI_PEB_OFFSET int "Offset to first UBI PEB" - depends on SPL_UBI help The offset in number of PEBs from the start of flash to the first PEB part of the UBI image. config SPL_UBI_VID_OFFSET int "Offset to VID header" - depends on SPL_UBI config SPL_UBI_LEB_START int "Offset to LEB in PEB" - depends on SPL_UBI help The offset in bytes to the LEB within a PEB. config SPL_UBI_INFO_ADDR hex "Address to place UBI scan info" - depends on SPL_UBI help Address for ubispl to place the scan info. Read README.ubispl to determine the required size config SPL_UBI_VOL_IDS int "Maximum volume id" - depends on SPL_UBI help The maximum volume id which can be loaded. Used for sizing the scan data structure. config SPL_UBI_LOAD_MONITOR_ID int "id of U-Boot volume" - depends on SPL_UBI help The UBI volume id from which to load U-Boot @@ -866,13 +967,13 @@ config SPL_UBI_LOAD_MONITOR_VOLNAME config SPL_UBI_LOAD_KERNEL_ID int "id of kernel volume" - depends on SPL_OS_BOOT && SPL_UBI + depends on SPL_OS_BOOT help The UBI volume id from which to load the kernel config SPL_UBI_LOAD_ARGS_ID int "id of kernel args volume" - depends on SPL_OS_BOOT && SPL_UBI + depends on SPL_OS_BOOT help The UBI volume id from which to load the device tree @@ -882,7 +983,19 @@ config UBI_SPL_SILENCE_MSG Disable messages from UBI SPL. This leaves warnings and errors enabled. -endif # if SPL_UBI +endmenu + +config SPL_DM_SPI + bool "Support SPI DM drivers in SPL" + depends on SPL_DM + help + Enable support for SPI DM drivers in SPL. + +config SPL_DM_SPI_FLASH + bool "Support SPI DM FLASH drivers in SPL" + depends on SPL_DM + help + Enable support for SPI DM flash drivers in SPL. config SPL_NET bool "Support networking" @@ -893,19 +1006,19 @@ config SPL_NET the network stack uses a number of environment variables. See also SPL_ETH. -if SPL_NET config SPL_NET_VCI_STRING string "BOOTP Vendor Class Identifier string sent by SPL" + depends on SPL_NET help As defined by RFC 2132 the vendor class identifier field can be sent by the client to identify the vendor type and configuration of a client. This is often used in practice to allow for the DHCP server to specify different files to load depending on if the ROM, SPL or U-Boot itself makes the request -endif # if SPL_NET config SPL_NO_CPU_SUPPORT - bool "Drop CPU code in SPL" + def_bool y + depends on (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK help This is specific to the ARM926EJ-S CPU. It disables the standard start.S start-up code, presumably so that a replacement can be @@ -922,7 +1035,6 @@ config SPL_NOR_SUPPORT config SPL_XIP_SUPPORT bool "Support XIP" - depends on SPL help Enable support for execute in place of U-Boot or kernel image. There is no need to copy image from flash to ram if flash supports execute @@ -944,16 +1056,25 @@ config SPL_OS_BOOT Enable booting directly to an OS from SPL. for more info read doc/README.falcon -if SPL_OS_BOOT +config SYS_SPL_ARGS_ADDR + hex "Address in memory to load 'args' file for Falcon Mode to" + depends on SPL_OS_BOOT + default 0x88000000 if ARCH_OMAP2PLUS + help + Address in memory where the 'args' file, typically a device tree + will be loaded in to memory. + +config SYS_NAND_SPL_KERNEL_OFFS + hex "Address in memory to load the OS file for Falcon mode to" + depends on SPL_OS_BOOT && SPL_NAND_SUPPORT + config SYS_OS_BASE hex "addr, where OS is found" - depends on SPL_NOR_SUPPORT + depends on SPL_OS_BOOT && SPL_NOR_SUPPORT help Specify the address, where the OS image is found, which gets booted. -endif # SPL_OS_BOOT - config SPL_FALCON_BOOT_MMCSD bool "Enable Falcon boot from MMC or SD media" depends on SPL_OS_BOOT && SPL_MMC @@ -970,6 +1091,20 @@ config SYS_MMCSD_RAW_MODE_KERNEL_SECTOR Note that the Falcon mode image can also be a FIT, if FIT support is enabled. +config SYS_MMCSD_RAW_MODE_ARGS_SECTOR + hex "Falcon mode: Sector to load 'args' from MMC" + depends on SPL_FALCON_BOOT_MMCSD + help + When Falcon mode is used with an MMC or SD media, SPL needs to know + where to look for the OS 'args', typically a device tree. The + contents are expected to begin at the raw MMC specified in this config. + Note that if using a FIT image, this and the next option can be set to + 0x0. + +config SYS_MMCSD_RAW_MODE_ARGS_SECTORS + hex "Falcon mode: Number of sectors to load for 'args' from MMC" + depends on SPL_FALCON_BOOT_MMCSD && SYS_MMCSD_RAW_MODE_ARGS_SECTOR != 0x0 + config SPL_PAYLOAD string "SPL payload" default "tpl/u-boot-with-tpl.bin" if TPL @@ -1007,7 +1142,7 @@ config SPL_POST_MEM_SUPPORT config SPL_DM_RESET bool "Support reset drivers" - depends on SPL + depends on SPL_DM help Enable support for reset control in SPL. That can be useful in SPL to handle IP reset in driver, as in U-Boot, @@ -1196,6 +1331,13 @@ config SPL_USB_STORAGE config options. This enables loading from USB using a configured device. +config SYS_USB_FAT_BOOT_PARTITION + int "Partition on USB to use to load U-Boot from" + depends on SPL_USB_STORAGE + default 1 + help + Partition on the USB storage device to load U-Boot from + config SPL_USB_GADGET bool "Suppport USB Gadget drivers" help @@ -1310,6 +1452,7 @@ config SPL_ATF_NO_PLATFORM_PARAM config SPL_AM33XX_ENABLE_RTC32K_OSC bool "Enable the RTC32K OSC on AM33xx based platforms" + depends on AM33XX default y if AM33XX help Enable access to the AM33xx RTC and select the external 32kHz clock @@ -1339,519 +1482,15 @@ config SPL_OPENSBI_LOAD_ADDR help Load address of the OpenSBI binary. -config TPL - bool - depends on SUPPORT_TPL - prompt "Enable TPL" - help - If you want to build TPL as well as the normal image and SPL, say Y. - -if TPL - -config TPL_SIZE_LIMIT - hex "Maximum size of TPL image" - depends on TPL - default 0x0 - help - Specifies the maximum length of the U-Boot TPL image. - If this value is zero, it is ignored. - -config TPL_BINMAN_SYMBOLS - bool "Declare binman symbols in TPL" - depends on SPL_FRAMEWORK && BINMAN - default y - help - This enables use of symbols in TPL which refer to U-Boot, enabling TPL - to obtain the location of U-Boot simply by calling spl_get_image_pos() - and spl_get_image_size(). - - For this to work, you must have a U-Boot image in the binman image, so - binman can update TPL with the location of it. - -config TPL_FRAMEWORK - bool "Support TPL based upon the common SPL framework" - default y if SPL_FRAMEWORK - help - Enable the SPL framework under common/spl/ for TPL builds. - This framework supports MMC, NAND and YMODEM and other methods - loading of U-Boot's SPL stage. If unsure, say Y. - -config TPL_HANDOFF - bool "Pass hand-off information from TPL to SPL and U-Boot proper" - depends on HANDOFF && TPL_BLOBLIST - default y - help - This option enables TPL to write handoff information. This can be - used to pass information like the size of SDRAM from TPL to U-Boot - proper. The information is also available to SPL if it is useful - there. - -config TPL_BOARD_INIT - bool "Call board-specific initialization in TPL" - help - If this option is enabled, U-Boot will call the function - spl_board_init() from board_init_r(). This function should be - provided by the board. - -config TPL_BOOTCOUNT_LIMIT - bool "Support bootcount in TPL" - depends on TPL_ENV_SUPPORT - help - If this option is enabled, the TPL will support bootcount. - For example, it may be useful to choose the device to boot. - -config TPL_LDSCRIPT - string "Linker script for the TPL stage" - depends on TPL - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 - default "arch/\$(ARCH)/cpu/u-boot-spl.lds" - help - The TPL stage will usually require a different linker-script - (as it runs from a different memory region) than the regular - U-Boot stage. Set this to the path of the linker-script to - be used for TPL. - - May be left empty to trigger the Makefile infrastructure to - fall back to the linker-script used for the SPL stage. - -config TPL_NEEDS_SEPARATE_STACK - bool "TPL needs a separate initial stack-pointer" - depends on TPL - help - Enable, if the TPL stage should not inherit its initial - stack-pointer from the settings for the SPL stage. - -config TPL_POWER - bool "Support power drivers" - help - Enable support for power control in TPL. This includes support - for PMICs (Power-management Integrated Circuits) and some of the - features provided by PMICs. In particular, voltage regulators can - be used to enable/disable power and vary its voltage. That can be - useful in TPL to turn on boot peripherals and adjust CPU voltage - so that the clock speed can be increased. This enables the drivers - in drivers/power, drivers/power/pmic and drivers/power/regulator - as part of an TPL build. - -config TPL_TEXT_BASE - hex "Base address for the .text section of the TPL stage" - default 0 - help - The base address for the .text section of the TPL stage. - -config TPL_MAX_SIZE - int "Maximum size (in bytes) for the TPL stage" - default 0 - depends on TPL - help - The maximum size (in bytes) of the TPL stage. - -config TPL_STACK - hex "Address of the initial stack-pointer for the TPL stage" - depends on TPL_NEEDS_SEPARATE_STACK - help - The address of the initial stack-pointer for the TPL stage. - Usually this will be the (aligned) top-of-stack. - -config TPL_READ_ONLY - bool - depends on TPL_OF_PLATDATA - select TPL_OF_PLATDATA_NO_BIND - select TPL_OF_PLATDATA_RT - help - Some platforms (e.g. x86 Apollo Lake) load SPL into a read-only - section of memory. This means that of-platdata must make a copy (in - writeable memory) of anything it wants to modify, such as - device-private data. - -config TPL_BOOTROM_SUPPORT - bool "Support returning to the BOOTROM (from TPL)" - help - Some platforms (e.g. the Rockchip RK3368) provide support in their - ROM for loading the next boot-stage after performing basic setup - from the TPL stage. - - Enable this option, to return to the BOOTROM through the - BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the - boot device list, if not implemented for a given board) - -config TPL_CRC32 - bool "Support CRC32 in TPL" - default y if TPL_ENV_SUPPORT || TPL_BLOBLIST - help - Enable this to support CRC32 in uImages or FIT images within SPL. - This is a 32-bit checksum value that can be used to verify images. - For FIT images, this is the least secure type of checksum, suitable - for detected accidental image corruption. For secure applications you - should consider SHA1 or SHA256. - -config TPL_DRIVERS_MISC - bool "Support misc drivers in TPL" - help - Enable miscellaneous drivers in TPL. These drivers perform various - tasks that don't fall nicely into other categories, Enable this - option to build the drivers in drivers/misc as part of an TPL - build, for those that support building in TPL (not all drivers do). - -config TPL_ENV_SUPPORT - bool "Support an environment" - help - Enable environment support in TPL. See SPL_ENV_SUPPORT for details. - -config TPL_GPIO - bool "Support GPIO in TPL" - help - Enable support for GPIOs (General-purpose Input/Output) in TPL. - GPIOs allow U-Boot to read the state of an input line (high or - low) and set the state of an output line. This can be used to - drive LEDs, control power to various system parts and read user - input. GPIOs can be useful in TPL to enable a 'sign-of-life' LED, - for example. Enable this option to build the drivers in - drivers/gpio as part of an TPL build. - -config TPL_I2C - bool "Support I2C" - help - Enable support for the I2C bus in TPL. See SPL_I2C for - details. - -config TPL_LIBCOMMON_SUPPORT - bool "Support common libraries" - help - Enable support for common U-Boot libraries within TPL. See - SPL_LIBCOMMON_SUPPORT for details. - -config TPL_LIBGENERIC_SUPPORT - bool "Support generic libraries" - help - Enable support for generic U-Boot libraries within TPL. See - SPL_LIBGENERIC_SUPPORT for details. - -config TPL_MPC8XXX_INIT_DDR - bool "Support MPC8XXX DDR init" - help - Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See - SPL_MPC8XXX_INIT_DDR for details. - -config TPL_MMC - bool "Support MMC" - depends on MMC - help - Enable support for MMC within TPL. See SPL_MMC for details. - -config TPL_NAND_SUPPORT - bool "Support NAND flash" - help - Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details. - -config TPL_PCI - bool "Support PCI drivers" - help - Enable support for PCI in TPL. For platforms that need PCI to boot, - or must perform some init using PCI in SPL, this provides the - necessary driver support. This enables the drivers in drivers/pci - as part of a TPL build. - -config TPL_PCH - bool "Support PCH drivers" - help - Enable support for PCH (Platform Controller Hub) devices in TPL. - These are used to set up GPIOs and the SPI peripheral early in - boot. This enables the drivers in drivers/pch as part of a TPL - build. - -config TPL_RAM_SUPPORT - bool "Support booting from RAM" - help - Enable booting of an image in RAM. The image can be preloaded or - it can be loaded by TPL directly into RAM (e.g. using USB). - -config TPL_RAM_DEVICE - bool "Support booting from preloaded image in RAM" - depends on TPL_RAM_SUPPORT - help - Enable booting of an image already loaded in RAM. The image has to - be already in memory when TPL takes over, e.g. loaded by the boot - ROM. - -config TPL_RTC - bool "Support RTC drivers" - help - Enable RTC (Real-time Clock) support in TPL. This includes support - for reading and setting the time. Some RTC devices also have some - non-volatile (battery-backed) memory which is accessible if - needed. This enables the drivers in drivers/rtc as part of an TPL - build. - -config TPL_SERIAL - bool "Support serial" - select TPL_PRINTF - select TPL_STRTO - help - Enable support for serial in TPL. See SPL_SERIAL for - details. - -config TPL_SPI_FLASH_SUPPORT - bool "Support SPI flash drivers" - help - Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT - for details. - -config TPL_SPI_FLASH_TINY - bool "Enable low footprint TPL SPI Flash support" - depends on TPL_SPI_FLASH_SUPPORT && !SPI_FLASH_BAR - default y if SPI_FLASH - help - Enable lightweight TPL SPI Flash support that supports just reading - data/images from flash. No support to write/erase flash. Enable - this if you have TPL size limitations and don't need full-fledged - SPI flash support. - -config TPL_SPI_LOAD - bool "Support loading from SPI flash" - depends on TPL_SPI_FLASH_SUPPORT - help - Enable support for loading next stage, U-Boot or otherwise, from - SPI NOR in U-Boot TPL. - -config TPL_SPI - bool "Support SPI drivers" - help - Enable support for using SPI in TPL. See SPL_SPI for - details. - -config TPL_DM_SPI - bool "Support SPI DM drivers in TPL" - help - Enable support for SPI DM drivers in TPL. - -config TPL_DM_SPI_FLASH - bool "Support SPI DM FLASH drivers in TPL" - help - Enable support for SPI DM flash drivers in TPL. - -config TPL_YMODEM_SUPPORT - bool "Support loading using Ymodem" - depends on TPL_SERIAL - help - While loading from serial is slow it can be a useful backup when - there is no other option. The Ymodem protocol provides a reliable - means of transmitting U-Boot over a serial line for using in TPL, - with a checksum to ensure correctness. - -endif # TPL - -config VPL - bool - depends on SUPPORT_SPL - prompt "Enable VPL" - help - If you want to build VPL as well as the normal image, TPL and SPL, - say Y. - -if VPL - -config VPL_BANNER_PRINT - bool "Enable output of the VPL banner 'U-Boot VPL ...'" - depends on VPL - default y - help - If this option is enabled, VPL will print the banner with version - info. Disabling this option could be useful to reduce VPL boot time - (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). - -config VPL_BOARD_INIT - bool "Call board-specific initialization in VPL" - help - If this option is enabled, U-Boot will call the function - spl_board_init() from board_init_r(). This function should be - provided by the board. - -config VPL_CACHE - depends on CACHE - bool "Support cache drivers in VPL" +config SPL_TARGET + string "Addtional build targets for 'make'" + default "spl/u-boot-spl.srec" if RCAR_GEN2 + default "spl/u-boot-spl.scif" if RCAR_GEN3 + default "" help - Enable support for cache drivers in VPL. + On some platforms we need to have 'make' run additional build target + rules. If required on your platform, enter it here, otherwise leave blank. -config VPL_CRC32 - bool "Support CRC32 in VPL" - default y if VPL_ENV_SUPPORT || VPL_BLOBLIST - help - Enable this to support CRC32 in uImages or FIT images within VPL. - This is a 32-bit checksum value that can be used to verify images. - For FIT images, this is the least secure type of checksum, suitable - for detected accidental image corruption. For secure applications you - should consider SHA1 or SHA256. - -config VPL_DM_SPI - bool "Support SPI DM drivers in VPL" - help - Enable support for SPI DM drivers in VPL. - -config VPL_DM_SPI_FLASH - bool "Support SPI DM FLASH drivers in VPL" - help - Enable support for SPI DM flash drivers in VPL. - -config VPL_FRAMEWORK - bool "Support VPL based upon the common SPL framework" - default y - help - Enable the SPL framework under common/spl/ for VPL builds. - This framework supports MMC, NAND and YMODEM and other methods - loading of U-Boot's next stage. If unsure, say Y. - -config VPL_HANDOFF - bool "Pass hand-off information from VPL to SPL" - depends on HANDOFF && VPL_BLOBLIST - default y - help - This option enables VPL to write handoff information. This can be - used to pass information like the size of SDRAM from VPL to SPL. Also - VPL can receive information from TPL in the same place if that is - enabled. - -config VPL_LIBCOMMON_SUPPORT - bool "Support common libraries" - default y if SPL_LIBCOMMON_SUPPORT - help - Enable support for common U-Boot libraries within VPL. See - SPL_LIBCOMMON_SUPPORT for details. - -config VPL_LIBGENERIC_SUPPORT - bool "Support generic libraries" - default y if SPL_LIBGENERIC_SUPPORT - help - Enable support for generic U-Boot libraries within VPL. These - libraries include generic code to deal with device tree, hashing, - printf(), compression and the like. This option is enabled on many - boards. Enable this option to build the code in lib/ as part of a - VPL build. - -config VPL_DRIVERS_MISC - bool "Support misc drivers" - default y if TPL_DRIVERS_MISC - help - Enable miscellaneous drivers in VPL. These drivers perform various - tasks that don't fall nicely into other categories, Enable this - option to build the drivers in drivers/misc as part of a VPL - build, for those that support building in VPL (not all drivers do). - -config VPL_ENV_SUPPORT - bool "Support an environment" - help - Enable environment support in VPL. The U-Boot environment provides - a number of settings (essentially name/value pairs) which can - control many aspects of U-Boot's operation. Enabling this option will - make env_get() and env_set() available in VSPL. - -config VPL_GPIO - bool "Support GPIO in VPL" - default y if SPL_GPIO - help - Enable support for GPIOs (General-purpose Input/Output) in VPL. - GPIOs allow U-Boot to read the state of an input line (high or - low) and set the state of an output line. This can be used to - drive LEDs, control power to various system parts and read user - input. GPIOs can be useful in VPL to enable a 'sign-of-life' LED, - for example. Enable this option to build the drivers in - drivers/gpio as part of a VPL build. - -config VPL_HANDOFF - bool "Pass hand-off information from VPL to SPL and U-Boot proper" - depends on HANDOFF && VPL_BLOBLIST - default y - help - This option enables VPL to write handoff information. This can be - used to pass information like the size of SDRAM from VPL to U-Boot - proper. The information is also available to VPL if it is useful - there. - -config VPL_HASH - bool "Support hashing drivers in VPL" - depends on VPL - select SHA1 - select SHA256 - help - Enable hashing drivers in VPL. These drivers can be used to - accelerate secure boot processing in secure applications. Enable - this option to build system-specific drivers for hash acceleration - as part of a VPL build. - -config VPL_I2C_SUPPORT - bool "Support I2C in VPL" - default y if SPL_I2C_SUPPORT - help - Enable support for the I2C bus in VPL. Vee SPL_I2C_SUPPORT for - details. - -config VPL_PCH_SUPPORT - bool "Support PCH drivers" - default y if TPL_PCH_SUPPORT - help - Enable support for PCH (Platform Controller Hub) devices in VPL. - These are used to set up GPIOs and the SPI peripheral early in - boot. This enables the drivers in drivers/pch as part of a VPL - build. - -config VPL_PCI - bool "Support PCI drivers" - default y if SPL_PCI - help - Enable support for PCI in VPL. For platforms that need PCI to boot, - or must perform some init using PCI in VPL, this provides the - necessary driver support. This enables the drivers in drivers/pci - as part of a VPL build. - -config VPL_RTC - bool "Support RTC drivers" - help - Enable RTC (Real-time Clock) support in VPL. This includes support - for reading and setting the time. Some RTC devices also have some - non-volatile (battery-backed) memory which is accessible if - needed. This enables the drivers in drivers/rtc as part of a VPL - build. - -config VPL_SERIAL - bool "Support serial" - default y if TPL_SERIAL - select VPL_PRINTF - select VPL_STRTO - help - Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for - details. - -config VPL_SIZE_LIMIT - hex "Maximum size of VPL image" - depends on VPL - default 0x0 - help - Specifies the maximum length of the U-Boot VPL image. - If this value is zero, it is ignored. - -config VPL_SPI - bool "Support SPI drivers" - help - Enable support for using SPI in VPL. See SPL_SPI_SUPPORT for - details. - -config VPL_SPI_FLASH_SUPPORT - bool "Support SPI flash drivers" - help - Enable support for using SPI flash in VPL, and loading U-Boot from - SPI flash. SPI flash (Serial Peripheral Bus flash) is named after - the SPI bus that is used to connect it to a system. It is a simple - but fast bidirectional 4-wire bus (clock, chip select and two data - lines). This enables the drivers in drivers/mtd/spi as part of a - VPL build. This normally requires VPL_SPI_SUPPORT. - -config VPL_TEXT_BASE - hex "VPL Text Base" - default 0x0 - help - The address in memory that VPL will be running from. - -endif # VPL config SPL_AT91_MCK_BYPASS bool "Use external clock signal as a source of main clock for AT91 platforms" @@ -1863,6 +1502,21 @@ config SPL_AT91_MCK_BYPASS The external source has to provide a stable clock on the XIN pin. If this option is disabled, the SoC expects a crystal oscillator that needs driving on both XIN and XOUT lines. - -endif # SPL endmenu + +config TPL + depends on SUPPORT_TPL + bool "Enable TPL" + help + If you want to build TPL as well as the normal image and SPL, say Y. + +source "common/spl/Kconfig.tpl" + +config VPL + depends on SUPPORT_SPL + bool "Enable VPL" + help + If you want to build VPL as well as the normal image, TPL and SPL, + say Y. + +source "common/spl/Kconfig.vpl" diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp new file mode 100644 index 0000000000000000000000000000000000000000..8da85539afd1741c9a6b9602562807cf86f713b6 --- /dev/null +++ b/common/spl/Kconfig.nxp @@ -0,0 +1,124 @@ +menu "PowerPC and LayerScape SPL Boot options" + depends on (PPC && SUPPORT_SPL && !SPL_FRAMEWORK) || \ + ((ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && SUPPORT_SPL) + +config SPL_NAND_BOOT + bool "Load SPL from NAND flash" + depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK) + +config SPL_MMC_BOOT + bool "Load SPL from SD Card / eMMC" + depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK) + +config SPL_SPI_BOOT + bool "Load SPL from SPI flash" + depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK) + +config SPL_FSL_PBL + bool "Create SPL in Freescale PBI format" + depends on (PPC || ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && \ + SUPPORT_SPL + help + Create boot binary having SPL binary in PBI format concatenated with + u-boot binary. + +config SPL_SYS_CCSR_DO_NOT_RELOCATE + bool "Ensures that CCSR is not relocated" + depends on PPC + help + If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a + value that ensures that CCSR is not relocated. + +config TPL_SYS_CCSR_DO_NOT_RELOCATE + def_bool y + depends on SPL_SYS_CCSR_DO_NOT_RELOCATE + +menu "PowerPC SPL / TPL specific options" + depends on PPC && (SPL && !SPL_FRAMEWORK) + +config SPL_INIT_MINIMAL + bool "Arch init code will be built for a very small image" + +config SPL_FLUSH_IMAGE + bool "Clean dcache and invalidate icache after loading the image" + +config SPL_SKIP_RELOCATE + bool "Skip relocating SPL" + +config SPL_GD_ADDR + hex "Address to use for global data (gd) in SPL" + depends on !SPL_INIT_MINIMAL + +config SPL_RELOC_TEXT_BASE + hex "Address to relocate SPL to" + default SPL_TEXT_BASE + help + If unspecified, this is equal to CONFIG_SPL_TEXT_BASE (i.e. no + relocation is done). + +config SPL_RELOC_STACK + hex "Address of the start of the stack SPL will use after relocation." + help + If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting + address of the malloc pool used in SPL. When this option is set the full + malloc is used in SPL and it is set up by spl_init() and before that, the + simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined. + +config SPL_RELOC_MALLOC + bool "SPL has malloc pool after relocation" + +config SPL_RELOC_MALLOC_ADDR + hex "Address of malloc pool in SPL" + depends on SPL_RELOC_MALLOC + +config SPL_RELOC_MALLOC_SIZE + hex "Size of malloc pool in SPL" + depends on SPL_RELOC_MALLOC + +config TPL_GD_ADDR + hex "Address to use for global data (gd) in TPL" + depends on TPL + +config TPL_RELOC_TEXT_BASE + hex "Address to relocate TPL to" + depends on TPL + default TPL_TEXT_BASE + help + If unspecified, this is equal to CONFIG_TPL_TEXT_BASE (i.e. no + relocation is done). + +config TPL_RELOC_STACK + hex "Address of the start of the stack TPL will use after relocation." + depends on TPL + help + If unspecified, this is equal to CONFIG_SYS_TPL_MALLOC_START. Starting + address of the malloc pool used in TPL. When this option is set the full + malloc is used in TPL and it is set up by spl_init() and before that, the + simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined. + +config TPL_RELOC_MALLOC + bool "TPL has malloc pool after relocation" + depends on TPL + +config TPL_RELOC_MALLOC_ADDR + hex "Address of malloc pool in TPL" + depends on TPL_RELOC_MALLOC + +config TPL_RELOC_MALLOC_SIZE + hex "Size of malloc pool in TPL" + depends on TPL_RELOC_MALLOC + +config TPL_PAD_TO + hex "Offset to which the TPL should be padded before appending the TPL payload" + depends on TPL && !TPL_FRAMEWORK + default TPL_MAX_SIZE + help + Image offset to which the TPL should be padded before appending the + TPL payload. By default, this is defined as CONFIG_TPL_MAX_SIZE, or 0 if + CONFIG_TPL_MAX_SIZE is undefined. CONFIG_TPL_PAD_TO must be either + 0, meaning to append the TPL payload without any padding, or >= + CONFIG_TPL_MAX_SIZE. +endmenu + +endmenu + diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl new file mode 100644 index 0000000000000000000000000000000000000000..e314b793a2e94714705cdc7e0e3bde60edcbc7e8 --- /dev/null +++ b/common/spl/Kconfig.tpl @@ -0,0 +1,335 @@ +menu "TPL configuration options" + depends on TPL + +config TPL_SIZE_LIMIT + hex "Maximum size of TPL image" + default 0x0 + help + Specifies the maximum length of the U-Boot TPL image. + If this value is zero, it is ignored. + +config TPL_BINMAN_SYMBOLS + bool "Support binman symbols in TPL" + depends on TPL_FRAMEWORK && BINMAN + default y + help + This enables use of symbols in TPL which refer to other entries in + the same binman image as the TPL. These can be declared with the + binman_sym_declare(type, entry, prop) macro and accessed by the + binman_sym(type, entry, prop) macro defined in binman_sym.h. + + See tools/binman/binman.rst for a detailed explanation. + +config TPL_BINMAN_UBOOT_SYMBOLS + bool "Declare binman symbols for U-Boot phases in TPL" + depends on TPL_BINMAN_SYMBOLS + default n if ARCH_IMX8M + default y + help + This enables use of symbols in TPL which refer to U-Boot phases, + enabling TPL to obtain the location and size of its next phase simply + by calling spl_get_image_pos() and spl_get_image_size(). + + For this to work, you must have all U-Boot phases in the same binman + image, so binman can update TPL with the locations of everything. + +config TPL_FRAMEWORK + bool "Support TPL based upon the common SPL framework" + default y if SPL_FRAMEWORK + help + Enable the SPL framework under common/spl/ for TPL builds. + This framework supports MMC, NAND and YMODEM and other methods + loading of U-Boot's SPL stage. If unsure, say Y. + +config TPL_BANNER_PRINT + bool "Enable output of the TPL banner 'U-Boot TPL ...'" + default y + help + If this option is enabled, TPL will print the banner with version + info. Disabling this option could be useful to reduce TPL boot time + (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). + +config TPL_HANDOFF + bool "Pass hand-off information from TPL to SPL and U-Boot proper" + depends on HANDOFF && TPL_BLOBLIST + default y + help + This option enables TPL to write handoff information. This can be + used to pass information like the size of SDRAM from TPL to U-Boot + proper. The information is also available to SPL if it is useful + there. + +config TPL_BOARD_INIT + bool "Call board-specific initialization in TPL" + help + If this option is enabled, U-Boot will call the function + spl_board_init() from board_init_r(). This function should be + provided by the board. + +config TPL_BOOTCOUNT_LIMIT + bool "Support bootcount in TPL" + depends on TPL_ENV_SUPPORT + help + If this option is enabled, the TPL will support bootcount. + For example, it may be useful to choose the device to boot. + +config TPL_SYS_MALLOC_SIMPLE + bool + prompt "Only use malloc_simple functions in the TPL" + help + Say Y here to only use the *_simple malloc functions from + malloc_simple.c, rather then using the versions from dlmalloc.c; + this will make the TPL binary smaller at the cost of more heap + usage as the *_simple malloc functions do not re-use free-ed mem. + +config TPL_SEPARATE_BSS + bool "BSS section is in a different memory region from text" + default y if SPL_SEPARATE_BSS + help + Some platforms need a large BSS region in TPL and can provide this + because RAM is already set up. In this case BSS can be moved to RAM. + This option should then be enabled so that the correct device tree + location is used. Normally we put the device tree at the end of BSS + but with this option enabled, it goes at _image_binary_end. + +config TPL_LDSCRIPT + string "Linker script for the TPL stage" + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + default "arch/\$(ARCH)/cpu/u-boot-spl.lds" + help + The TPL stage will usually require a different linker-script + (as it runs from a different memory region) than the regular + U-Boot stage. Set this to the path of the linker-script to + be used for TPL. + + May be left empty to trigger the Makefile infrastructure to + fall back to the linker-script used for the SPL stage. + +config TPL_NEEDS_SEPARATE_STACK + bool "TPL needs a separate initial stack-pointer" + help + Enable, if the TPL stage should not inherit its initial + stack-pointer from the settings for the SPL stage. + +config TPL_POWER + bool "Support power drivers" + help + Enable support for power control in TPL. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in TPL to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of an TPL build. + +config TPL_TEXT_BASE + hex "Base address for the .text section of the TPL stage" + default 0 + help + The base address for the .text section of the TPL stage. + +config TPL_MAX_SIZE + hex "Maximum size (in bytes) for the TPL stage" + default 0x2e000 if ROCKCHIP_RK3399 + default 0x8000 if ROCKCHIP_RK3288 + default 0x7000 if ROCKCHIP_RK322X || ROCKCHIP_RK3328 || ROCKCHIP_RK3368 + default 0x2800 if ROCKCHIP_PX30 + default 0x0 + help + The maximum size (in bytes) of the TPL stage. + +config TPL_STACK + hex "Address of the initial stack-pointer for the TPL stage" + depends on TPL_NEEDS_SEPARATE_STACK + help + The address of the initial stack-pointer for the TPL stage. + Usually this will be the (aligned) top-of-stack. + +config TPL_READ_ONLY + bool + depends on TPL_OF_PLATDATA + select TPL_OF_PLATDATA_NO_BIND + select TPL_OF_PLATDATA_RT + help + Some platforms (e.g. x86 Apollo Lake) load SPL into a read-only + section of memory. This means that of-platdata must make a copy (in + writeable memory) of anything it wants to modify, such as + device-private data. + +config TPL_BOOTROM_SUPPORT + bool "Support returning to the BOOTROM (from TPL)" + help + Some platforms (e.g. the Rockchip RK3368) provide support in their + ROM for loading the next boot-stage after performing basic setup + from the TPL stage. + + Enable this option, to return to the BOOTROM through the + BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the + boot device list, if not implemented for a given board) + +config TPL_CRC32 + bool "Support CRC32 in TPL" + default y if TPL_ENV_SUPPORT || TPL_BLOBLIST + help + Enable this to support CRC32 in uImages or FIT images within SPL. + This is a 32-bit checksum value that can be used to verify images. + For FIT images, this is the least secure type of checksum, suitable + for detected accidental image corruption. For secure applications you + should consider SHA1 or SHA256. + +config TPL_DRIVERS_MISC + bool "Support misc drivers in TPL" + help + Enable miscellaneous drivers in TPL. These drivers perform various + tasks that don't fall nicely into other categories, Enable this + option to build the drivers in drivers/misc as part of an TPL + build, for those that support building in TPL (not all drivers do). + +config TPL_ENV_SUPPORT + bool "Support an environment" + help + Enable environment support in TPL. See SPL_ENV_SUPPORT for details. + +config TPL_GPIO + bool "Support GPIO in TPL" + help + Enable support for GPIOs (General-purpose Input/Output) in TPL. + GPIOs allow U-Boot to read the state of an input line (high or + low) and set the state of an output line. This can be used to + drive LEDs, control power to various system parts and read user + input. GPIOs can be useful in TPL to enable a 'sign-of-life' LED, + for example. Enable this option to build the drivers in + drivers/gpio as part of an TPL build. + +config TPL_I2C + bool "Support I2C" + help + Enable support for the I2C bus in TPL. See SPL_I2C for + details. + +config TPL_LIBCOMMON_SUPPORT + bool "Support common libraries" + help + Enable support for common U-Boot libraries within TPL. See + SPL_LIBCOMMON_SUPPORT for details. + +config TPL_LIBGENERIC_SUPPORT + bool "Support generic libraries" + help + Enable support for generic U-Boot libraries within TPL. See + SPL_LIBGENERIC_SUPPORT for details. + +config TPL_MPC8XXX_INIT_DDR + bool "Support MPC8XXX DDR init" + help + Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See + SPL_MPC8XXX_INIT_DDR for details. + +config TPL_MMC + bool "Support MMC" + depends on MMC + help + Enable support for MMC within TPL. See SPL_MMC for details. + +config TPL_NAND_SUPPORT + bool "Support NAND flash" + help + Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details. + +config TPL_PCI + bool "Support PCI drivers" + help + Enable support for PCI in TPL. For platforms that need PCI to boot, + or must perform some init using PCI in SPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of a TPL build. + +config TPL_PCH + bool "Support PCH drivers" + help + Enable support for PCH (Platform Controller Hub) devices in TPL. + These are used to set up GPIOs and the SPI peripheral early in + boot. This enables the drivers in drivers/pch as part of a TPL + build. + +config TPL_RAM_SUPPORT + bool "Support booting from RAM" + help + Enable booting of an image in RAM. The image can be preloaded or + it can be loaded by TPL directly into RAM (e.g. using USB). + +config TPL_RAM_DEVICE + bool "Support booting from preloaded image in RAM" + depends on TPL_RAM_SUPPORT + help + Enable booting of an image already loaded in RAM. The image has to + be already in memory when TPL takes over, e.g. loaded by the boot + ROM. + +config TPL_RTC + bool "Support RTC drivers" + help + Enable RTC (Real-time Clock) support in TPL. This includes support + for reading and setting the time. Some RTC devices also have some + non-volatile (battery-backed) memory which is accessible if + needed. This enables the drivers in drivers/rtc as part of an TPL + build. + +config TPL_SERIAL + bool "Support serial" + select TPL_PRINTF + select TPL_STRTO + help + Enable support for serial in TPL. See SPL_SERIAL for + details. + +config TPL_SPI_FLASH_SUPPORT + bool "Support SPI flash drivers" + help + Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT + for details. + +config TPL_SPI_FLASH_TINY + bool "Enable low footprint TPL SPI Flash support" + depends on TPL_SPI_FLASH_SUPPORT && !SPI_FLASH_BAR + default y if SPI_FLASH + help + Enable lightweight TPL SPI Flash support that supports just reading + data/images from flash. No support to write/erase flash. Enable + this if you have TPL size limitations and don't need full-fledged + SPI flash support. + +config TPL_SPI_LOAD + bool "Support loading from SPI flash" + depends on TPL_SPI_FLASH_SUPPORT + help + Enable support for loading next stage, U-Boot or otherwise, from + SPI NOR in U-Boot TPL. + +config TPL_SPI + bool "Support SPI drivers" + help + Enable support for using SPI in TPL. See SPL_SPI for + details. + +config TPL_DM_SPI + bool "Support SPI DM drivers in TPL" + help + Enable support for SPI DM drivers in TPL. + +config TPL_DM_SPI_FLASH + bool "Support SPI DM FLASH drivers in TPL" + help + Enable support for SPI DM flash drivers in TPL. + +config TPL_YMODEM_SUPPORT + bool "Support loading using Ymodem" + depends on TPL_SERIAL + help + While loading from serial is slow it can be a useful backup when + there is no other option. The Ymodem protocol provides a reliable + means of transmitting U-Boot over a serial line for using in TPL, + with a checksum to ensure correctness. + +endmenu diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl new file mode 100644 index 0000000000000000000000000000000000000000..ba4b2e4f99e9c1aaedac1bf2c3f33f05f4d9e248 --- /dev/null +++ b/common/spl/Kconfig.vpl @@ -0,0 +1,226 @@ +menu "VPL options" + depends on VPL + +config VPL_BANNER_PRINT + bool "Enable output of the VPL banner 'U-Boot VPL ...'" + default y + help + If this option is enabled, VPL will print the banner with version + info. Disabling this option could be useful to reduce VPL boot time + (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). + +config VPL_BOARD_INIT + bool "Call board-specific initialization in VPL" + help + If this option is enabled, U-Boot will call the function + spl_board_init() from board_init_r(). This function should be + provided by the board. + +config VPL_CACHE + depends on CACHE + bool "Support cache drivers in VPL" + help + Enable support for cache drivers in VPL. + +config VPL_CRC32 + bool "Support CRC32 in VPL" + default y if VPL_ENV_SUPPORT || VPL_BLOBLIST + help + Enable this to support CRC32 in uImages or FIT images within VPL. + This is a 32-bit checksum value that can be used to verify images. + For FIT images, this is the least secure type of checksum, suitable + for detected accidental image corruption. For secure applications you + should consider SHA1 or SHA256. + +config VPL_DM_SPI + bool "Support SPI DM drivers in VPL" + help + Enable support for SPI DM drivers in VPL. + +config VPL_DM_SPI_FLASH + bool "Support SPI DM FLASH drivers in VPL" + help + Enable support for SPI DM flash drivers in VPL. + +config VPL_FRAMEWORK + bool "Support VPL based upon the common SPL framework" + default y + help + Enable the SPL framework under common/spl/ for VPL builds. + This framework supports MMC, NAND and YMODEM and other methods + loading of U-Boot's next stage. If unsure, say Y. + +config VPL_HANDOFF + bool "Pass hand-off information from VPL to SPL" + depends on HANDOFF && VPL_BLOBLIST + default y + help + This option enables VPL to write handoff information. This can be + used to pass information like the size of SDRAM from VPL to SPL. Also + VPL can receive information from TPL in the same place if that is + enabled. + +config VPL_LIBCOMMON_SUPPORT + bool "Support common libraries" + default y if SPL_LIBCOMMON_SUPPORT + help + Enable support for common U-Boot libraries within VPL. See + SPL_LIBCOMMON_SUPPORT for details. + +config VPL_LIBGENERIC_SUPPORT + bool "Support generic libraries" + default y if SPL_LIBGENERIC_SUPPORT + help + Enable support for generic U-Boot libraries within VPL. These + libraries include generic code to deal with device tree, hashing, + printf(), compression and the like. This option is enabled on many + boards. Enable this option to build the code in lib/ as part of a + VPL build. + +config VPL_DRIVERS_MISC + bool "Support misc drivers" + default y if TPL_DRIVERS_MISC + help + Enable miscellaneous drivers in VPL. These drivers perform various + tasks that don't fall nicely into other categories, Enable this + option to build the drivers in drivers/misc as part of a VPL + build, for those that support building in VPL (not all drivers do). + +config VPL_ENV_SUPPORT + bool "Support an environment" + help + Enable environment support in VPL. The U-Boot environment provides + a number of settings (essentially name/value pairs) which can + control many aspects of U-Boot's operation. Enabling this option will + make env_get() and env_set() available in VSPL. + +config VPL_GPIO + bool "Support GPIO in VPL" + default y if SPL_GPIO + help + Enable support for GPIOs (General-purpose Input/Output) in VPL. + GPIOs allow U-Boot to read the state of an input line (high or + low) and set the state of an output line. This can be used to + drive LEDs, control power to various system parts and read user + input. GPIOs can be useful in VPL to enable a 'sign-of-life' LED, + for example. Enable this option to build the drivers in + drivers/gpio as part of a VPL build. + +config VPL_HANDOFF + bool "Pass hand-off information from VPL to SPL and U-Boot proper" + depends on HANDOFF && VPL_BLOBLIST + default y + help + This option enables VPL to write handoff information. This can be + used to pass information like the size of SDRAM from VPL to U-Boot + proper. The information is also available to VPL if it is useful + there. + +config VPL_HASH + bool "Support hashing drivers in VPL" + select SHA1 + select SHA256 + help + Enable hashing drivers in VPL. These drivers can be used to + accelerate secure boot processing in secure applications. Enable + this option to build system-specific drivers for hash acceleration + as part of a VPL build. + +config VPL_I2C_SUPPORT + bool "Support I2C in VPL" + default y if SPL_I2C_SUPPORT + help + Enable support for the I2C bus in VPL. Vee SPL_I2C_SUPPORT for + details. + +config VPL_PCH_SUPPORT + bool "Support PCH drivers" + default y if TPL_PCH_SUPPORT + help + Enable support for PCH (Platform Controller Hub) devices in VPL. + These are used to set up GPIOs and the SPI peripheral early in + boot. This enables the drivers in drivers/pch as part of a VPL + build. + +config VPL_PCI + bool "Support PCI drivers" + default y if SPL_PCI + help + Enable support for PCI in VPL. For platforms that need PCI to boot, + or must perform some init using PCI in VPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of a VPL build. + +config VPL_RTC + bool "Support RTC drivers" + help + Enable RTC (Real-time Clock) support in VPL. This includes support + for reading and setting the time. Some RTC devices also have some + non-volatile (battery-backed) memory which is accessible if + needed. This enables the drivers in drivers/rtc as part of a VPL + build. + +config VPL_SERIAL + bool "Support serial" + default y if TPL_SERIAL + select VPL_PRINTF + select VPL_STRTO + help + Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for + details. + +config VPL_SIZE_LIMIT + hex "Maximum size of VPL image" + default 0x0 + help + Specifies the maximum length of the U-Boot VPL image. + If this value is zero, it is ignored. + +config VPL_SPI + bool "Support SPI drivers" + help + Enable support for using SPI in VPL. See SPL_SPI_SUPPORT for + details. + +config VPL_SPI_FLASH_SUPPORT + bool "Support SPI flash drivers" + help + Enable support for using SPI flash in VPL, and loading U-Boot from + SPI flash. SPI flash (Serial Peripheral Bus flash) is named after + the SPI bus that is used to connect it to a system. It is a simple + but fast bidirectional 4-wire bus (clock, chip select and two data + lines). This enables the drivers in drivers/mtd/spi as part of a + VPL build. This normally requires VPL_SPI_SUPPORT. + +config VPL_TEXT_BASE + hex "VPL Text Base" + default 0x0 + help + The address in memory that VPL will be running from. + +config VPL_BINMAN_SYMBOLS + bool "Declare binman symbols in VPL" + depends on VPL_FRAMEWORK && BINMAN + default y + help + This enables use of symbols in VPL which refer to other entries in + the same binman image as the VPL. These can be declared with the + binman_sym_declare(type, entry, prop) macro and accessed by the + binman_sym(type, entry, prop) macro defined in binman_sym.h. + + See tools/binman/binman.rst for a detailed explanation. + +config VPL_BINMAN_UBOOT_SYMBOLS + bool "Declare binman symbols for U-Boot phases in VPL" + depends on VPL_BINMAN_SYMBOLS + default n if ARCH_IMX8M + default y + help + This enables use of symbols in VPL which refer to U-Boot phases, + enabling VPL to obtain the location and size of its next phase simply + by calling spl_get_image_pos() and spl_get_image_size(). + + For this to work, you must have all U-Boot phases in the same binman + image, so binman can update VPL with the locations of everything. + +endmenu diff --git a/common/spl/spl.c b/common/spl/spl.c index c8c463f80bd377127ef6366df5d2f6787a69258f..29e0898f03de15b1dd01c675fd24c3fad00ed0eb 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -33,12 +34,14 @@ #include #include #include +#include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; +DECLARE_BINMAN_MAGIC_SYM; #ifndef CONFIG_SYS_UBOOT_START #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE @@ -50,11 +53,10 @@ DECLARE_GLOBAL_DATA_PTR; u32 *boot_params_ptr = NULL; -#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) +#if CONFIG_IS_ENABLED(BINMAN_UBOOT_SYMBOLS) /* See spl.h for information about this */ binman_sym_declare(ulong, u_boot_any, image_pos); binman_sym_declare(ulong, u_boot_any, size); -#endif #ifdef CONFIG_TPL binman_sym_declare(ulong, u_boot_spl, image_pos); @@ -66,6 +68,8 @@ binman_sym_declare(ulong, u_boot_vpl, image_pos); binman_sym_declare(ulong, u_boot_vpl, size); #endif +#endif /* BINMAN_UBOOT_SYMBOLS */ + /* Define board data structure */ static struct bd_info bdata __attribute__ ((section(".data"))); @@ -148,9 +152,11 @@ void spl_fixup_fdt(void *fdt_blob) #endif } -#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) ulong spl_get_image_pos(void) { + if (!CONFIG_IS_ENABLED(BINMAN_UBOOT_SYMBOLS)) + return BINMAN_SYM_MISSING; + #ifdef CONFIG_VPL if (spl_next_phase() == PHASE_VPL) return binman_sym(ulong, u_boot_vpl, image_pos); @@ -162,6 +168,9 @@ ulong spl_get_image_pos(void) ulong spl_get_image_size(void) { + if (!CONFIG_IS_ENABLED(BINMAN_UBOOT_SYMBOLS)) + return BINMAN_SYM_MISSING; + #ifdef CONFIG_VPL if (spl_next_phase() == PHASE_VPL) return binman_sym(ulong, u_boot_vpl, size); @@ -170,7 +179,6 @@ ulong spl_get_image_size(void) binman_sym(ulong, u_boot_spl, size) : binman_sym(ulong, u_boot_any, size); } -#endif /* BINMAN_SYMBOLS */ ulong spl_get_image_text_base(void) { @@ -221,7 +229,7 @@ __weak struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) void spl_set_header_raw_uboot(struct spl_image_info *spl_image) { - ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos); + ulong u_boot_pos = spl_get_image_pos(); spl_image->size = CONFIG_SYS_MONITOR_LEN; @@ -728,9 +736,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_set_bd(); -#if defined(CONFIG_SYS_SPL_MALLOC_START) - mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, - CONFIG_SYS_SPL_MALLOC_SIZE); +#if defined(CONFIG_SYS_SPL_MALLOC) + mem_malloc_init(SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); gd->flags |= GD_FLG_FULL_MALLOC_INIT; #endif if (!(gd->flags & GD_FLG_SPL_INIT)) { @@ -780,6 +787,14 @@ void board_init_r(gd_t *dummy1, ulong dummy2) bootcount_inc(); + /* Dump driver model states to aid analysis */ + if (CONFIG_IS_ENABLED(DM_STATS)) { + struct dm_stats mem; + + dm_get_mem(&mem); + dm_dump_mem(&mem); + } + memset(&spl_image, '\0', sizeof(spl_image)); #ifdef CONFIG_SYS_SPL_ARGS_ADDR spl_image.arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR; diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 6116a68371a952d46e7298d6ff7b430e559ed489..f66147477e77bf25d5bd4f81239a57152efe3514 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -229,7 +229,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image, { int ret; -#if defined(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR) +#if CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR) unsigned long count; count = blk_dread(mmc_get_blk_desc(mmc), diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 067a2d42bbf8e171b1f0cf90b7d62d0d784030f9..7986e930d28b6343306cfd3a97e5d1df1b849f17 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -74,8 +74,8 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, (void *)(CONFIG_SYS_OS_BASE + sizeof(struct image_header)), spl_image->size); -#ifdef CONFIG_SYS_FDT_BASE - spl_image->arg = (void *)CONFIG_SYS_FDT_BASE; +#ifdef CONFIG_SYS_SPL_ARGS_ADDR + spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR; #endif return 0; diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 8296459257186108e20af60dd2373d0a6e882d1b..d64710878cf25620f7c6350673e0e56c70dc8c5d 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -70,7 +70,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image, load.read = spl_ram_load_read; spl_load_simple_fit(spl_image, &load, 0, header); } else { - ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos); + ulong u_boot_pos = spl_get_image_pos(); debug("Legacy image\n"); /* diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 1f3a144cdfbf472629884f06765a2fd48a4fffec..1351d78612a5142803fc6d12c184e903a9055c99 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -21,10 +21,6 @@ #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 #endif -#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR /* Dummy value to make the compiler happy */ #define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100 @@ -73,21 +69,11 @@ static int spl_sata_load_image(struct spl_image_info *spl_image, int err = 0; struct blk_desc *stor_dev; -#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI) - err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE); -#endif - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: sata init failed: err - %d\n", err); -#endif - return err; - } else { - /* try to recognize storage devices immediately */ - scsi_scan(false); - stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0); - if (!stor_dev) - return -ENODEV; - } + /* try to recognize storage devices immediately */ + scsi_scan(false); + stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0); + if (!stor_dev) + return -ENODEV; #if CONFIG_IS_ENABLED(OS_BOOT) if (spl_start_uboot() || diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index cf3f7ef4c0d50a40348447767373d44e24f41393..3eef2f8d683ce37e95d81f1b02e5eab257b3a26b 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -71,6 +71,16 @@ unsigned int __weak spl_spi_get_uboot_offs(struct spi_flash *flash) return CONFIG_SYS_SPI_U_BOOT_OFFS; } +u32 __weak spl_spi_boot_bus(void) +{ + return CONFIG_SF_DEFAULT_BUS; +} + +u32 __weak spl_spi_boot_cs(void) +{ + return CONFIG_SF_DEFAULT_CS; +} + /* * The main entry for SPI booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -83,15 +93,15 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, unsigned int payload_offs; struct spi_flash *flash; struct image_header *header; + unsigned int sf_bus = spl_spi_boot_bus(); + unsigned int sf_cs = spl_spi_boot_cs(); /* * Load U-Boot image from SPI flash into RAM * In DM mode: defaults speed and mode will be * taken from DT when available */ - - flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, - CONFIG_SF_DEFAULT_CS, + flash = spi_flash_probe(sf_bus, sf_cs, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); if (!flash) { diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c index 33863fe7d454ae6a6b1a51d829340d1287de0bc3..e9a40b0ec7976d20dc113ba8f76300b0b3c57338 100644 --- a/common/spl/spl_xip.c +++ b/common/spl/spl_xip.c @@ -14,7 +14,7 @@ static int spl_xip(struct spl_image_info *spl_image, { #if CONFIG_IS_ENABLED(OS_BOOT) if (!spl_start_uboot()) { - spl_image->arg = (void *)CONFIG_SYS_FDT_BASE; + spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR; spl_image->name = "Linux"; spl_image->os = IH_OS_LINUX; spl_image->load_addr = CONFIG_SYS_LOAD_ADDR; diff --git a/common/usb.c b/common/usb.c index aad13fd9c5574343ea69dc95e50a7a42ea081574..6fcf1e8428e95524979331d58d7ad3c718cea27a 100644 --- a/common/usb.c +++ b/common/usb.c @@ -49,10 +49,6 @@ char usb_started; /* flag for the started/stopped USB status */ static struct usb_device usb_dev[USB_MAX_DEVICE]; static int dev_index; -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /*************************************************************************** * Init USB Device */ diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index 72f8ce91019c9c0a8bb7a96231a4963dbd116b10..6c56cdc3286d27c128f4e3bcf2a43bb680eb147e 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_BASE=0xCFF80000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 0a69871ec567b1cba16990fdcbad1482ab769ad7..f266c0e5e41d69247090baab376df977aea59d8d 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_BASE=0xD7F80000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_XIMG is not set @@ -37,6 +39,7 @@ CONFIG_ALTERA_SYSID=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 90f12308bab919004c39b174dbd6525edb014bc5..26a921279b5b2b17e0d58db5c547d4a22bc6ed3d 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -11,8 +11,11 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 99f5785751781bed19eb130cf96753449f26fe98..7e9b92ee5ee4234a4b7f0fae0bbc79d4c9b4b7b7 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,7 +9,9 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index f9d17b19500f14ec1e346e893f65f8c2b3e964dd..625a331e44565fdfefc86cbc7179e6c71e784fe4 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,6 +13,8 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 8c9043559bdb23ab1ecb8714f0859a779e69e0f0..5e0396c150fa45b3926cc19822d7b2754a8e2f6b 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_DFU_RAM=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 918fc64e0e067d01fe5aa096d0987011db6c81ac..b5802818ec3efe6812566b66c0933c58e17e6ffa 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -13,10 +13,13 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 903e3fdbcc875c0936ebeea7ccc73f28cec81598..de4f6311f2d4c2ec5b97affbf0f661e3f6141d64 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,10 +11,13 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index c06050610de8a1eb74b624bacad9f35437a19465..ebb3a02b824ad7e003db3e6e4351251c048e9f48 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -9,8 +9,11 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index cf3fc682e447bc79b6a9503f8cff8cc09b4af7ff..c8802435b412fb52101d0a00b980edb429245dc0 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -11,8 +11,11 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 81c27432cdca18801ee8ed60824ff06b27478a00..f44964124564249acfbb841e7a433e86ac3959e6 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,8 +12,11 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 075d999e1c9fb64d6962d167d524aea0f79fdcf3..67b47f51f1b7b211b801714da5ff241d9231d039 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -12,8 +12,11 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 829e7bbcd33ba0c43a7d5faa3ae69fd4da812f03..e02d67da5e711bf03b8bba79d659e452b679f90b 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -13,8 +13,11 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 5b96ddc68ba47d458b239c58e9e42c7b407dd3c7..317a1e695d8badb02d0b0082210c1339fbd6819e 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -12,8 +12,11 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 351a454339be195029f59682ee8825aca6bbae96..c9eec1f88790acb7db4a6cb6646cdcc12a577025 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -16,5 +16,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 9a18af8c6e1129eae2c29bedbabe69c3b431b766..8cd38f7905bb43dda7b26a3e62c6bcc3790da3a2 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 7bf3dfcd8a5ef9f1f14fe5f63aae312c205f812a..68707ed3e951a0cb4522cf8b9fb64957564ef3d3 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 7d81f12f766df64a1b308dcaa995dcde80b47c2f..703df186b27f7f76707c03d4ceaa5411346322c9 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,7 +8,9 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 4c7154b04c499e584507b505326078a3bdf64407..a8d236eaf9d99c95bb9cf96d70a9c6c8a7ee40c5 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,7 +6,9 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index a66aef0755ad285e481a52d9a1ae69dc4b68917a..be5be9ae2fbd9978c2d892cbf63aabf694929bb6 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -12,8 +12,11 @@ CONFIG_USB2_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 7f59fc9b3d3e507b85890bacc2265b9a70b1d753..053ba1376525a0d67ce5b2061a22fa6695654529 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,9 +9,12 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index bad38a66568ee62a45abeb1279215057143defe0..6a07f26c02c46e450134477151b87c7e7a29e093 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -10,6 +10,8 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index e075635aaddf20194881586001238f1ec951ead2..36f9bf8b32e33ccf7b0e5971ac76319d8c3147d9 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,9 +11,12 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index cd9bdbfd36f77a2b3e92794b4125528ee5faffd5..40d2c5b668afeb49069ae3fdfb020206c5afdf05 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -7,7 +7,9 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y CONFIG_CHIP_DIP_SCAN=y +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 29179601907ad4ef4b5e70f8c83454309b3e8a00..90168010bb8e84078b9553c3797a6c32bac50fec 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -5,7 +5,9 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0" diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 1cd39d498f238205020d34b4e37766176d1a6f00..49be3fc4a2d2156cf6b003412aabe9470e50645e 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 02b3e69584f1857d07eb09eeefd8ae5195f39dc0..b59d1786e6efda588de38c7075dfe4875e291bd8 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 270bd7d351a92b05e18d96008a4397d8a9ef7f42..24b55bfa8cc9a292a8c482ab79887f4e28b77cd0 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -15,6 +15,8 @@ CONFIG_VIDEO_LCD_BL_EN="PM1" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index b06a3ae4238d97ec53da6ba1ff66345839865a66..315c52f3448d383b41493dd39be580858d6f5698 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -8,8 +8,11 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 04ed79afb6d546ec0cb0f1ee93dedc33cc8fb338..928299e8a513085e55ba9842c7f3dbc0b1610ffe 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -12,5 +12,7 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y +CONFIG_SPL_STACK=0x18000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 93a7932b76a83fa4f33a7f5c0953e14f393bbe41..49eb01869533b00629e32b9e57c6bb90e1bb0319 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -8,8 +8,11 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index a4f7b872ff02cb49b57e9bb200d4c66373d848f7..62668df01ecbefa51816a7e14b74fc5324f95f06 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -13,10 +13,13 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 13f958977be2c49babad182b1821ecd9b4584d5a..8119b8b9cf6b387cb771f2efa117840b4c111484 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -16,6 +16,8 @@ CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index a9bbe8bcffac8b853c3d8f3a2a707f3e3ca81abf..0187b896f873b05c8151d86c5a6198f41563b32d 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -16,7 +16,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index fc1f26b7a998636e608b858efeb5af5b81ee50f0..6570b97ca4c6ee91b30aa6ae888adcc345866e5c 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 24e8b5be1b5b035f5f429f01c1735d1bcd967d01..3afe4c56ae4db3a213b8181388c6c027a85ac393 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -9,6 +9,8 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 482e0fb7a83d7ecc5f40571cf3f62c0fbf312221..8bf7d1efba61df6919d5b961b2ec5171fb0e5107 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 58184422147871cf4068ff2135eba5f5dd309ec1..1a161555842df8eac54d67e119437a3dbdb61ab7 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -8,8 +8,11 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 6dd7b7ae7024a6123f86b5a789f66df51ad40134..3627e4dd3afa0b8fa8fd550b291bc3c4f106eb10 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -10,8 +10,11 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 9815348badd113a96374af03756c7a385c61cca1..2e0b0b71e140704bd815c5e0f8f2e3eb03d5f762 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -5,4 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 # CONFIG_NETDEVICES is not set diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 25cea8437394bf646eef103a71117880b9d95dd1..41ed46a7b5a12883da87865de76c1dd29efc5e7d 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -10,8 +10,11 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index de88dd0a3031081ff705b0008ebba1074d5f112a..44a3901e22debed98b06c8931f6eff5fc2e8fc4b 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -8,8 +8,11 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 49dcfa098ee2a5724c469c01874f219458d464c8..279641551b30eb92762ab209376d985b63c70ae0 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,7 +6,9 @@ CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index bd2f31722111012b6338563e2b47a26b6874a7b5..858fc5bbfd2eaddbf8774b0b3893e8a207970ea0 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -11,9 +11,12 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y @@ -32,6 +35,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index e3b0146d84169364d503abe266cee6c209990942..c7fd5a07a7c5e5d84f893cb349e0ae557cc52d70 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -12,8 +12,11 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0xFFC00400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -39,6 +42,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index d026400745b62d67ee83730f2c9f43d08a5ff104..a14bf427ad0a871579148b84d0ebbe26b0b5cf14 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -11,9 +11,12 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -39,6 +42,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index 9a360b0eae2fa9ed1ba0330fe0256bed721018ae..f99375b535ed460994beb815d880361a919242a2 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -13,7 +13,9 @@ CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_DEVICE_NULLDEV=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_LOOPW=y CONFIG_CMD_MX_CYCLIC=y @@ -23,6 +25,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MCFUART=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 6f69acaee160063cbec036703681b27757947fb0..3ed703a7a79349b42d616ec99aed8c786d2438ec 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -11,8 +11,11 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0xFF800400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index ed48264ed9ca6fc1a4dff305fa024d300dedf859..e3f736bf6308b71fc6a9a81d60fa960392c7e6f0 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -11,9 +11,11 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set @@ -52,6 +54,7 @@ CONFIG_SYS_BR7_PRELIM=0x701 CONFIG_SYS_OR7_PRELIM=0xFFC0007C CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 2f517984b6304af25cfef4c0f43276e234bb877b..fe6ffca43c9f4116bbbce45322a06fc80669ec20 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -13,9 +13,12 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="bootm ffe40000" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 850d027f0014814d340fe0da145d0532eaab2ea9..42940e1000a4c05954dbae2882aa6a6293787d99 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -11,9 +11,11 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set @@ -28,6 +30,7 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 005a3bcf08c8017673fa477365234533f421cdb8..28d51eaa9deb71400449ca1e03635648339e5b11 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -13,9 +13,12 @@ CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y @@ -34,11 +37,13 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 83a3bb07aeb6790d3ca6902c9b61c95d097d7f6f..c59359b820c7f53f7d5cd1f23ac6837e41c435df 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -11,9 +11,12 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set @@ -34,10 +37,12 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 728f2b18e668167c903c2cb5d1202fc12006d990..ae4add504b1c3150ab333a00213a17f9147ff7ab 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -11,9 +11,12 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -35,11 +38,13 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index f61e344a51807819672a9622d9ec956f44d46929..aead0f45bd30adde4d12dfa53d60cc436823f0e5 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -11,9 +11,12 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -35,11 +38,13 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index f99a830b546a112b567e9e735d182bd664dda4df..6adba431ef0964768c4366cc7a1e81973c0db8c0 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -31,8 +31,10 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="S3K> " +CONFIG_SYS_PBSIZE=278 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_LOADB is not set diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 3ed962d7cd94e50a39b579c3cf84c3d26109c341..4e678bdf051fe666079d8800e67f2bd8fc9043f4 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,7 +5,9 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 4a9db732f92e303fd173e6ca9c6342648583720d..efdddf7c2b3d5f1298d7ef785c8b01ad2b86aa92 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -153,6 +153,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 6933699771fbab606a79b57ef83a4fd220cec793..6fa89aad36a78293568f428269ca62cfd763ac33 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -10,6 +10,8 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_PCIE1=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -20,6 +22,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath # CONFIG_MISC_INIT_R is not set CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index ee9c14880c6eab6c38c7fbf9a43938a39f568d4c..82776497a592103968bcdac1e2669529ed267cde 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -10,6 +10,8 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_PCIE1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y @@ -19,6 +21,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath # CONFIG_MISC_INIT_R is not set CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 97f641d71cdfe9f166f59bcc7d037edc27cac66e..c21ed57dc37561f33e454a98bc8825a9f5b79d9a 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -10,7 +10,9 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y +CONFIG_PCIE1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y @@ -20,6 +22,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath # CONFIG_MISC_INIT_R is not set CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 071169fd298908af268a379350ef64d395654545..7a4b224bf2a1e01df28db375282b32fd0ba2af0c 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,7 +10,9 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index e77b0072923e6c7f7a9a32bee02e794e37938862..bb820fd0a39f067631c0f49bfb70a0611364c5b8 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -13,6 +13,8 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB_MUSB_HOST=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 61d978319751156e28c7d143c7f30fd35946c577..1584778dc744ab3428aed583d81f018c6efe082e 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -5,7 +5,10 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index c6bfe381db8a581a305fbd73e3e94b74b26a8d82..8ee6791408a096bf5ce36a414e5d4d4becd808c8 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -8,6 +8,8 @@ CONFIG_INITIAL_USB_SCAN_DELAY=2000 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index d3a01275cf51892618c1aea7d772fb039803ff4b..eb3e79880058e498be1245b374172567c12342ad 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -8,8 +8,11 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 2b9bca13d08e07ddde84dbfdfa44c59847e9cad2..48dad606b884930f9a9627ac26049fc021876a9c 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 77cb464c9326ac5cc83f567873917452553a8022..ce962395a253ba21349baff3ec8c08efcef0f209 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,7 +9,9 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index f2ee3b1c0cf0817130f165e8b25426dbd28f1cc2..2e6d5dd460495ca10b67a9e85d734ef00032141d 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -9,8 +9,11 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index be6dd417545c23bbc24a9889b996ed250f28e0e7..b84a2aebe206c3add05787d9e19e2c79fddf0d4d 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index c5d1f40df39892ab92c83a6b10c70e15a0541266..3709a11ec03691b4eac10944a1ff9507e1e636c7 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -12,5 +12,7 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y +CONFIG_SPL_STACK=0x18000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index e8bc14857663150c4ab3b9c62de12188480b5745..76b6b7d2bce7191f741b726c4bfe898d00eced9c 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,7 +6,9 @@ CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index b66023418aec43cb6defb2b182d55ca5d30143e5..5b1a1d40614ad4c57b4ba7423b276f4a8ea5f704 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,6 +9,8 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y # CONFIG_MMC is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index d69bc7af93b7ac6a50f7ee5980652042ff6a17b3..ba976f8f5f3cc7457d291b78304bbe9e3206daa3 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -12,8 +12,11 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 508cace424c97493fb7fa725bf48128576742e88..720e9e5df4c6ae3e1c2614f106f8206d96c35df0 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -14,8 +14,11 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b44264f41d6f3ab3213b0345c9f10c45cfced9b7..7a50cd7f90d00efdb5a0026079dbc4d92b9a98b9 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,12 +14,17 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -28,15 +32,30 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x2000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 +CONFIG_SPL_RELOC_STACK=0xd003fff0 +CONFIG_TPL_GD_ADDR=0xd002c000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_TPL_RELOC_STACK=0xd0030000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -52,16 +71,21 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index bd5d7b652b4bd80aeb66c2dc0de6a3f5d46a0066..5030afd098e78737b45994193325c24937232725 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -9,11 +8,16 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -21,6 +25,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -41,10 +46,15 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 516198b9634702f98def0e7c4bcff3ea10fdc783..dd04cff4a448b08a0d7b4d82f068034a826d4d38 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -1,24 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -26,11 +31,22 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -52,10 +68,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index a545cffe4d9269b34230fe3ee50f44bb7a8820a3..46613cce3b59206a632fd62ce7dc7a450c3188a7 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -16,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -29,11 +33,22 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -55,10 +70,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 9cb7f55ecf4ee9a88b77c8d7359317d34e89fde6..49acfd2d38e5b445bb3816686b252ed6903c01db 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,11 +14,16 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -27,15 +31,30 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x2000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 +CONFIG_SPL_RELOC_STACK=0xd003fff0 +CONFIG_TPL_GD_ADDR=0xd002c000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_TPL_RELOC_STACK=0xd0030000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -51,16 +70,21 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 510035739fdeef75a8d362e4fa9ca7a41130b7e1..89fccd6fc324c96331bf366b51bfa6e2d4965890 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -9,10 +8,15 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -20,6 +24,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -40,10 +45,15 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 160f4a0dfdeb38c79a06d9203b6ee9f227b9eb9e..a2786616c8de3d4649adc907fae3c01d121caf57 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -1,23 +1,28 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -25,11 +30,22 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -51,10 +67,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index cf61ca3b9228204009286ff336b7aac5fb05c01e..17daecd2ece9d3064f8804deed45f330dd4da82d 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -16,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -28,11 +32,22 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -54,10 +69,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 67659cfc90698067e08751a4def3c57465daefd0..6b73bf43413ef9bd19113cf66a8a5fb5dfe1a37b 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,12 +14,17 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -29,15 +33,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x2000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 +CONFIG_SPL_RELOC_STACK=0xd003fff0 +CONFIG_TPL_GD_ADDR=0xd002c000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_TPL_RELOC_STACK=0xd0030000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -53,16 +72,21 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 228db54c22ce6c4dd548a48ff11930bb839bd2c2..7a5e057a2c22c20cb14879d1d26e9f2461030f40 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -9,11 +8,16 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -22,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -42,10 +47,15 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 2774a5c5c448241ee7b285612cab4ec6ccaaaa52..ef85d48719c88fbba1a9da16df0e0eb16a7d8f80 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -1,24 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -27,11 +32,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -53,10 +69,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 240aa3a4c2e8a7e4eebc0e9b0e16504d1d150ff4..bda32ccbf342ff4e3c7853dc8759bea3aa7c6842 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -16,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -30,11 +34,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -56,10 +71,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 18215d8f358a2aac00f0d8fdc79f79f903859634..50667e56f6afbf3d969de21be67ee359694ac50a 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,11 +14,16 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -28,15 +32,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x2000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 +CONFIG_SPL_RELOC_STACK=0xd003fff0 +CONFIG_TPL_GD_ADDR=0xd002c000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_TPL_RELOC_STACK=0xd0030000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -52,16 +71,21 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 21ef7a0d76f0c6324a544eb8ab51f84c6541904a..c13369efe7087519d082fea5b8d12d5455970d81 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -9,10 +8,15 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -21,6 +25,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -41,10 +46,15 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 4ad9633bf6035ad47753af26c555d8873b5cdcfc..691d6e33dac4d6060e434c2189c4ec0073974c99 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -1,23 +1,28 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -26,11 +31,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -52,10 +68,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 9b05f4846823ee9b7cbd1856d3261a9da7c01521..a630e961ee2424e074d26a3c8a80d958fb0a1863 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -16,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -29,11 +33,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x18000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xd0018000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 +CONFIG_SPL_RELOC_STACK=0xd001c000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -55,10 +70,14 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 56b984e5ae685becc791cc3f770f931a8bd6a47a..8288e858ed022ba0241bc98213c1608726cc3b7a 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,13 +14,18 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -29,15 +33,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x1000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000 +CONFIG_SPL_RELOC_STACK=0xf8fbfff0 +CONFIG_TPL_GD_ADDR=0xf8fac000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 +CONFIG_TPL_RELOC_STACK=0xf8fb0000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -52,14 +71,18 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 @@ -72,6 +95,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y @@ -119,5 +143,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 4407a02a7d9713353bce7e42d4c35cae2850ead0..b581cb109b169cb7bf450e9b74cc13db65cc2fce 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -1,26 +1,31 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -28,12 +33,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -54,8 +69,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -65,6 +83,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -106,5 +125,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index ee0fdd6657d125931b8ab17346d74ba3de5736e2..e8543c6461a15bb09dac4da16d96307a0391738c 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -16,13 +15,18 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -31,12 +35,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -57,8 +71,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -68,6 +85,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -109,5 +127,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index bbfc4a5bcff98ce7970586654153b66a5f50000a..2b9fcb034c9cf4c54b8f9a7af4e529f06fde5ef1 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -10,12 +9,17 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -24,6 +28,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -43,8 +48,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -54,6 +62,8 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -95,5 +105,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 00d847d50af220ce2d7f95b23f31cf6a50193447..fdb163f49c2ac8bd9bba1222ffd59e116a0e8c6c 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,12 +14,17 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -28,15 +32,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x1000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000 +CONFIG_SPL_RELOC_STACK=0xf8fbfff0 +CONFIG_TPL_GD_ADDR=0xf8fac000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 +CONFIG_TPL_RELOC_STACK=0xf8fb0000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -51,14 +70,18 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 @@ -71,6 +94,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y @@ -118,4 +142,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index feb00ea91615453544f1663b6fc233065923ce15..7489ad3459f427d588bb35dfed49ae5d13565ba0 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -1,25 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -27,12 +32,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -53,8 +68,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -64,6 +82,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -105,4 +124,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index f18f4b2ce150023ee035413f1383d934de6a150f..728592f6c3c81c9e0f9acc998ff1caea56af7a60 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -16,12 +15,17 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -30,12 +34,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -56,8 +70,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -67,6 +84,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -108,4 +126,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index aec0d47acb7c1d298d3b9b1df90e2209398b1c4d..ada7e2d59a746b251d7d73a2484e2e2dc203489b 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -10,11 +9,16 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -23,6 +27,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -42,8 +47,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -53,6 +61,8 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -94,4 +104,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 0d713624d48899542a2ecf4f1e3f8d5c8073c787..08392863371ff55738e5c003c4f3e1a424a4bfe2 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,12 +14,17 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -28,15 +32,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x1000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000 +CONFIG_SPL_RELOC_STACK=0xf8fbfff0 +CONFIG_TPL_GD_ADDR=0xf8fac000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 +CONFIG_TPL_RELOC_STACK=0xf8fb0000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -54,14 +73,18 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x60000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8796 @@ -74,6 +97,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index b50dfcbc392c039a1898950e144eb24f65473c6f..ddd9e335e6425d17783ae64b8089da3f479ec2c0 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -1,25 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -27,12 +32,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -56,8 +71,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -67,6 +85,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 6649f5b2feaf41cd80a59158d294e4066d18843e..88365bff62b9dcf6f327cbcc229e8577e1680010 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -16,12 +15,17 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -30,12 +34,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x1b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -59,8 +73,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -70,6 +87,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index cbbdb0fb113a762592f97c5dd9456854f8c67f76..ef31e0970ace27fbb1ef86d9acee27f1c7fe8621 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -10,11 +9,16 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -23,6 +27,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -45,8 +50,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -56,6 +64,8 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index e167468ed385de53468371fb7b6fb4df1eba4ad8..99f1d26446e039f8fdc1a4d1ce8231918078719d 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,13 +14,18 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -29,15 +33,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x1000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000 +CONFIG_SPL_RELOC_STACK=0xf8fffff0 +CONFIG_TPL_GD_ADDR=0xf8fac000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 +CONFIG_TPL_RELOC_STACK=0xf8fb0000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -56,14 +75,18 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb) CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 @@ -76,6 +99,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 1e15552edc701e10ed16320cbecb76f19f26f048..856a78fdd13762134ccec5367271658bedf0e78c 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -1,26 +1,31 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -28,12 +33,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -58,8 +73,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -69,6 +87,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index cf0ae5da3cfa1afd9dc599d0e1878be785650b19..b03c17c7e7b84102e8fa765f7d1ae133e0457191 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -16,13 +15,18 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -31,12 +35,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -61,8 +75,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -72,6 +89,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index bd189b965b00005ec9b2342408f3e0265eb6d21f..c1a5ef9d30c5fa20b509549b8fb3af4f3e1f5d27 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -10,12 +9,17 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -24,6 +28,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -47,8 +52,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -58,6 +66,8 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 29d90c91400ee0d7c0512ac986b792b7a1507872..2558596b161aca17330543c530df5fb66bae13e0 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -15,12 +14,17 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -28,15 +32,30 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x1000 CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_INIT_MINIMAL=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000 +CONFIG_SPL_RELOC_STACK=0xf8fffff0 +CONFIG_TPL_GD_ADDR=0xf8fac000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 +CONFIG_TPL_RELOC_STACK=0xf8fb0000 +CONFIG_TPL_RELOC_MALLOC=y +CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 +CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_TPL=y +CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -55,14 +74,18 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb), CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 @@ -75,6 +98,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 540999bef21d5062760a8a6859602ff987c52093..29cc14700aebe83277ba431fb44bb88506e11d46 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -1,25 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -27,12 +32,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -57,8 +72,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -68,6 +86,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 0881e35476ac800fbaafae02b2978fdf68228ae7..3ee43f8da61783ac78a49a03afa604315be89b83 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -16,12 +15,17 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -30,12 +34,22 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_GD_ADDR=0xf8f9c000 +CONFIG_SPL_RELOC_STACK=0xf8f9d000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -60,8 +74,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -71,6 +88,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index eba11d340acbd1535a72580a4bade3436900bdb7..7af0244078ac22857c0110e033c3d22f7553a0e8 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -1,5 +1,4 @@ CONFIG_PPC=y -CONFIG_SYS_IMMR=0xFFE00000 CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x2000 @@ -10,11 +9,16 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -23,6 +27,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_MISC_INIT_R is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -46,8 +51,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -57,6 +65,8 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xFFA00801 CONFIG_SYS_OR3_PRELIM=0xFFF009F7 +CONFIG_COMMON_INIT_DDR=y +CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 9717f50834ad2fb87d5e4e86642582d984fe9e9d..30bf78be1e6ea169ffe239061b0fcf3d75071ba2 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +31,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -45,6 +53,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -90,6 +99,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 50065c4a96727a867753a2a5b426aaa363eccc9f..d5ad60981a2a418335aded57af9b1e7384e79f7e 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +31,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -45,6 +53,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -85,6 +94,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 25f32c03c149ed63fe578ff88f93b31dbc6d865d..97b01b498bf1ecb34f6ef1a147517a1fba3d708a 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -8,6 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +33,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -47,6 +55,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -87,6 +96,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 29e94fcd094cb8f48fbbc35b4a8b92c03423e65b..c1eb08053299c766b59242e7862f23d280d95629 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -8,6 +8,13 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -42,6 +50,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -82,6 +91,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 638b409b9635889db3a6b3292a6115ad662dd897..1df522a7449a35a4a8a855bc6aa346f9cf773f68 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -7,6 +7,14 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +32,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -43,8 +52,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -93,6 +104,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index e05ea44d2c2afc56ff786a6f3c3c5f8569b20dd9..2380cfc7710c95de9fc492c601ab5f90290745b2 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -7,6 +7,14 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +32,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -43,8 +52,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -88,6 +99,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 9bfde175420fd3e5e3c8b205ae0063031ca8803c..8a2464df91dd824191d5f245b84e0e540796c6c9 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -8,6 +8,14 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +34,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -45,8 +54,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -90,6 +101,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index d62a200871abee54b9240ce04c38dec8ca495a8b..0abf6e1631dafc8ed3bf4a5d79b878de023a5d4f 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -8,6 +8,14 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,6 +30,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -40,8 +49,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -85,6 +96,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 63f8e6aa9d49d3c94b96bfba067e3192819a53f2..66769e03c77d5c4eaf04b1ec4fb42a07f93d481a 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +31,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -43,7 +51,9 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -86,6 +96,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 56da9d80b73f5c1cab4d2407dd5f61d0b4589ac2..8b5b81448a5dff24c7c5bf79703dbd0991004f0a 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -8,6 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +33,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -45,7 +53,9 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -88,6 +98,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index ec5d2f9ac6c3adc46ec62a50661e33705dfc30e2..a0b12d049ef3ff338e05260e14fa02edf81ea9fb 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -8,6 +8,13 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -40,7 +48,9 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -83,6 +93,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 2ac298a43141332848839a8624dfbfc41521fd94..f48b0f92f72d8e0253aa150a7727b4b5bc118820 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +31,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -44,8 +52,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -94,6 +104,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index a1ddca57750cc01371d2eaea079ec1c3f495ad00..bf7287417e9674791e7fee88d29e19fa77944f08 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +31,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -43,8 +51,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -88,6 +98,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 32fec67e949ed5fbe8caedee25357b24d7f70410..c3a5f630a9741a6a427f16c40342a1abc8a10038 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -8,6 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +33,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -45,8 +53,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -90,6 +100,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 48bd2b6f1bf1f50a18456e1b8217e50379f37dc9..9dac9e94c64b978a440cb6c95d17e35f32093a02 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -8,6 +8,13 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -40,8 +48,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -85,6 +95,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index ef427490ff91f457d643a64e75e85d96134893cc..f186f247eb63ff08f03ca415e7f38af1fd66027a 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -13,6 +13,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw" CONFIG_IDENT_STRING="\nSBx81LIFKW" CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y @@ -20,6 +22,8 @@ CONFIG_SILENT_U_BOOT_ONLY=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 687e064fa8fc2da6498df3d34363f08eb425484f..9d579091a82f86517aa9112dd8f6847f62ba2d71 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -13,6 +13,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat" CONFIG_IDENT_STRING="\nSBx81LIFXCAT" CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y @@ -20,6 +22,8 @@ CONFIG_SILENT_U_BOOT_ONLY=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 238b0073e7946eb1c561dde43ee6cf5d0a175aea..2d33331f3d3d51819cdf38193aea7fbb9129a3f4 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -10,6 +10,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 4eb5300b04685ed2d5f48eee1e09048e22937461..fcee14b5462bfce1018fbe6120a9de0710f617ea 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -13,6 +13,8 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index aba95270eb2f446cea73aee82b356ca3f399510a..c080a247105ec09662f47e2a9add3bdfecd4a8d6 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index d27f495f48f0e08c685b48fc5e8cc5eb64f19f50..32ec5deca7d896275b9bd4010ef2e361c7b0b578 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -17,6 +17,8 @@ CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_AXP_DCDC5_VOLT=1200 diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index bb62ae9a7a992fb888225f7c00c6fa96c64f6285..749bf1cff9dbdf2c0cc487c8e40c671312c19f49 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -12,3 +12,5 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x18000 +CONFIG_SYS_PBSIZE=1024 diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index c86c5c153096cba2999731a287ef6af6ffc3dacc..de2b09c18fe95277084501ff9bac4d35947af615 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -12,6 +12,15 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -32,13 +41,24 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -111,6 +131,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index a820d2969e35d2e57166487d4dc2a88e46ba27ed..3a3cff873b2dde9b3a673ac4856f2bf2cc32fd38 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -13,6 +13,14 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -33,12 +41,23 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -106,6 +125,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 2708e9f0911f5eff8e9bcde9710d0ab902b31f0b..9499f585f1a669a547b1a633b78eb562225b20b7 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,6 +15,14 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -36,12 +44,23 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -109,6 +128,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 3359c59958eaf046fb2674d5820b1ce6361deedb..da28ef143f8426fb6cab35c08942a38525cfa1f4 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -8,6 +8,13 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -25,6 +32,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -92,6 +100,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 978c6c0bb65dd60a64ba07046ac0985598a2cc07..e51e363cfdd7a12eec2aa98ed8ac442ed409d6c4 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -11,6 +11,16 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -28,13 +38,24 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -109,6 +130,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 3cb72f03d6b049d3fbc7e58a79fead1c45238721..e86f0fa99a66e5a106607ae6bc8f5728cb14caa0 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -12,6 +12,15 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -29,12 +38,23 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -104,6 +124,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 662c93691d1d4b1317c69a05a85fe0fbd4aec98e..c8d8857ccbc9ef5f350fa8c9a70f0ddbfa864c6c 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -14,6 +14,15 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -32,12 +41,23 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -107,6 +127,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 23f116fb7ccf9ffb4c8c1ab1a36e058f9fee3983..1f3d6f6985fd5f83acfc98d3614808199c2bd302 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -7,6 +7,14 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -21,6 +29,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -90,6 +99,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index f5fc3e19b581be0c52e69e06d021d5075fa817e1..f9475619603caf68359273ac6d518471db635f30 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -1,11 +1,26 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -13,11 +28,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -33,13 +43,24 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -61,6 +82,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -114,6 +136,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index d440ab69a685e59d56d3b71b1bb52205ecba26a6..d83d365423767292868c2475f75388db78b737bf 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -1,11 +1,26 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -13,12 +28,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -34,12 +43,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -61,6 +81,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -109,6 +130,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 0464557c7726a8b741961f70f61aba59806a5a9a..a18ea5651665ec78208d508ac6a7bde2d62366b6 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -1,8 +1,20 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="t2080qds" +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_NXP_ESBC=y +CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000 +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -10,9 +22,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_SYS_MALLOC_F is not set CONFIG_MP=y CONFIG_FIT=y @@ -25,6 +34,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr" CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -46,6 +56,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 @@ -93,9 +104,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index f3ae31bf2224ea87236ce944e1d9161d65a8bd85..160e697159fb5a69bac38c56ab9f66af67c5d49e 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -7,13 +7,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -21,6 +14,22 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -37,12 +46,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -64,6 +84,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -112,6 +133,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 81623471926dd2286c62af2a20b0df32323e6517..16563ea8afce0a6464f3571f6e8ee483bd89f400 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -2,6 +2,19 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" +CONFIG_ENV_ADDR=0xFFE20000 +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SRIO_PCIE_BOOT_SLAVE=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -9,11 +22,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_SRIO_PCIE_BOOT_SLAVE=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +34,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y @@ -44,6 +53,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -86,6 +96,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 51184a08d7c4e6789bf16783fd0554198487b17f..e7775dac0b808916ad26c8c75845336c63790b76 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -3,6 +3,18 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" +CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -10,10 +22,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +34,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y @@ -47,6 +56,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -95,6 +105,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 1c73bfb3d01ca5af8cfbf3a4196adcd8f7389cc0..472e5779af644aa1e1b31c5c1d4deb6d03aab09d 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -1,20 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -31,13 +41,24 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -63,6 +84,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -117,6 +139,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index f6668720cf3ad0a48ec6e411643cdc7872196e48..6882baf164afcd1f937930f8e9b022505dc0d13c 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -1,21 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -32,12 +41,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -63,6 +83,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -112,6 +133,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 2578b0eabb884c68694c0723c716fa4d6081396c..5b1824ddb9bdea29194e70cb72a6c99924ea379e 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -7,10 +7,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -18,6 +14,19 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -35,12 +44,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -66,6 +86,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -115,6 +136,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 3d3dc7c8a43fca5e753a9495a5928cf6b911cb7e..6c6835eee316c11b4edf0b3bf5e3e261dc1b5c56 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -3,14 +3,22 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -24,6 +32,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -49,6 +58,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -97,6 +107,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index e9d78e92c95aaf03b29d61cd3fa28707d6209abd..a34c7caec7eada2bf0a3a5e47aa3e1814cabeb27 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -1,21 +1,31 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -32,13 +42,24 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -64,6 +85,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -119,6 +141,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 9951efbb3d5018f22c784284f327d9b5e6410526..0f503a889cc1dc8dd4042f5076f696cfe893d320 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -1,22 +1,31 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -33,12 +42,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -64,6 +84,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -114,6 +135,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 59f67d88a02496abc9ab22b6785ad54b64052d83..d5845febd8d8af285b224e05a62134e3534aae47 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -7,10 +7,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -18,7 +14,20 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -36,12 +45,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -67,6 +87,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -117,6 +138,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 0c954e51386dc5916c87f7a438593026a79ff123..e599c4e640e80f263bd9ce9d1c30e983a752b57c 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -3,15 +3,23 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -25,6 +33,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y @@ -50,6 +59,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -99,6 +109,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 43354c0af2b7f37f7dea5ef829ca223001e2706c..bd467ac7cfb5cb0217f3c3660887ae48072611de 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -1,21 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -30,12 +39,23 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MAX_SIZE=0x28000 +CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y +CONFIG_SPL_FLUSH_IMAGE=y +CONFIG_SPL_SKIP_RELOCATE=y +CONFIG_SPL_GD_ADDR=0xfffc8000 +CONFIG_SPL_RELOC_STACK=0xfffd8000 +CONFIG_SPL_RELOC_MALLOC=y +CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000 +CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -55,6 +75,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 @@ -99,6 +120,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 40bcbfe98b5deea35c0077a49fdd66d84a808631..5b7849ea6ba867cc3e5d0884559c08a6973d439c 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -3,14 +3,22 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,6 +30,7 @@ CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudra CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -41,6 +50,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 @@ -85,6 +95,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index b021b0a8865cb9a03ab44bb9a07ad134431b27c7..4e6652db18f6ac460eb9ae4fa7511198d7248707 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,7 +20,9 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 101ce57aa44dcbe4efcdcae55f3ab395a76c5a74..f63d18c327fab938db303a3fbaa2dd7de805e45e 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,7 +13,9 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 83b82133b96bc8b69fb83a4835dc41a50dba84d5..c9d22534d5c10113a94ddb911c095aa2c246fd92 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -12,8 +12,11 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index e0687bf887dbd444c63e7eaf0711a37b5439e05e..ab919c0795a8d173b149cbd3c419b418128df774 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,7 +7,9 @@ CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index f1ceb8b552758ac3055ef508d1d0a7789f604e8a..1117e147cc17d072bb20298a46dc3c63cb854540 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,7 +19,9 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index 6701ecce2fefc85d0f895afe6781340fcbbf80bb..ef30aee82815ebe407ee05a115cb38cfda7f4bb4 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -16,5 +16,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig index 536e23e1df975a9342e198fd2097d7cd2a4a781e..9c0427236b932f0c9b93c3cdd5c7b1c009747ed4 100644 --- a/configs/a3y17lte_defconfig +++ b/configs/a3y17lte_defconfig @@ -10,6 +10,8 @@ CONFIG_TARGET_A3Y17LTE=y CONFIG_NR_DRAM_BANKS=8 CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte" CONFIG_SYS_LOAD_ADDR=0x40001000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200e50 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;" @@ -17,6 +19,8 @@ CONFIG_SAVE_PREV_BL_FDT_ADDR=y CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig index c6f452a85587b4ad31213ace8ce4cc2d61dbfcda..ea0773e7a264243868718dade7d8b21c006fbc2b 100644 --- a/configs/a5y17lte_defconfig +++ b/configs/a5y17lte_defconfig @@ -10,6 +10,8 @@ CONFIG_TARGET_A5Y17LTE=y CONFIG_NR_DRAM_BANKS=12 CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte" CONFIG_SYS_LOAD_ADDR=0x40001000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200e50 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;" @@ -17,6 +19,8 @@ CONFIG_SAVE_PREV_BL_FDT_ADDR=y CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index 8ec9eb3e9c2d8c6c8abeec5817bc30888dffca58..afa0c24b688a2849ba89ebd9e1bb45731dae7a15 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -6,6 +6,9 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 16cef18beefef136a635dd8df348356d56198813..ccb5abc98452e35233eeda6839e6f8ad895fa700 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -6,6 +6,9 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig index 28e9c097d199afb2c8331ee3a3a4b4e10a0a1ae3..952c72b760d2554aee72442026e6c467a50ab2d9 100644 --- a/configs/a7y17lte_defconfig +++ b/configs/a7y17lte_defconfig @@ -10,6 +10,8 @@ CONFIG_TARGET_A7Y17LTE=y CONFIG_NR_DRAM_BANKS=12 CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte" CONFIG_SYS_LOAD_ADDR=0x40001000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200e50 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;" @@ -17,6 +19,8 @@ CONFIG_SAVE_PREV_BL_FDT_ADDR=y CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 8284feb773a199ea75ee2ec80f8c1cb0af377cf7..b7ea28b1786a428dab9504da7a662d34c9090ae4 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -7,11 +7,15 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_AX25_AE350=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -28,7 +32,9 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index babe02145471a9c481ba215134f863caf0695e24..fd89ea14e9cb049608e27f5034592fe9d212fc68 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -10,12 +10,18 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_AX25_AE350=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -31,6 +37,8 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e21136d5351d1ab800591f9bb763fb6d189cb3e4..2a0c1abf6e54121b7a1f4ab4b7881fa2a2ccd44c 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -12,12 +12,18 @@ CONFIG_TARGET_AX25_AE350=y CONFIG_RISCV_SMODE=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -33,6 +39,8 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index d76118630beca0f42b93e94a8ed04a2c419301d2..e85921bcb3ab10cb8eb2d2a74a0f45599e5312c9 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -8,11 +8,15 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_AX25_AE350=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -29,7 +33,9 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 860a45f7fbfcb1aaef89a43f63b13397f5315ca0..cab5a387e5a924f0d2e7772b11ffae34192879f7 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -8,11 +8,15 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -29,7 +33,9 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 09207bfba7de8c4f9891d7ac7e07a3f34c6b9ce9..a5cc75718229cd7acc2fdfaa157c3d8b663dd34f 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -11,12 +11,18 @@ CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -32,6 +38,8 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 6f641d7e437eb63724ffde42a366fd97342b63a1..dbe5db278fd29772f068e7dcf6f8c9b47caca2eb 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -13,12 +13,18 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -34,6 +40,8 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 3375cb69e645cc7e104b2f63c6ca05d4955c3dfa..c9dc1d10f821f0519e5645fd70753f2c3d1341e2 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -9,11 +9,15 @@ CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y @@ -30,7 +34,9 @@ CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 6ab4fe7a818c7b1aa7268b067e3ae30c4e9401be..4e73e6af7d74865026a56cb1fc8473b18f4b12a7 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 5ad078ffaa93832b2e44fca07b7a954024bf9d91..bbb987c5edd65ce981e2a6a81d785a09592ac357 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -12,11 +12,15 @@ CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y @@ -26,6 +30,8 @@ CONFIG_SPL_NAND_BASE=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index dc4693d40bfd9a165deecf382180a3ee493aa373..9fe5ac4a1618c6d918fdfb2fcb90d858fe035a4e 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -10,6 +10,8 @@ CONFIG_CLOCK_SYNTHESIZER=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -20,6 +22,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_MUSB_NEW=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NET=y @@ -27,8 +31,12 @@ CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -47,6 +55,7 @@ CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 30577a6fce42c2f29c7744b8cbc005c7256733d3..b5801094e8c48195aff80e7fba90ab8cec4ec739 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -10,6 +10,8 @@ CONFIG_AM335X_USB0_PERIPHERAL=y CONFIG_AM335X_USB1=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -18,9 +20,12 @@ CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_boot CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_ETH=y # CONFIG_SPL_FS_EXT4 is not set +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MUSB_NEW=y CONFIG_SPL_NAND_DRIVERS=y @@ -29,10 +34,15 @@ CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x200000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00080000 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -54,6 +64,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_CLK_TI_CTRL=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index f1b9d6c3ad8b84e48ab5caf2c9451f34880d32cd..1f28d50a1b3edd3ad2b22750319455ec99518fd5 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -19,13 +21,18 @@ CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_boot CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_FS_EXT4 is not set +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -47,6 +54,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_DFU_TFTP=y @@ -70,7 +78,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 -# CONFIG_SPL_NAND_AM33XX_BCH is not set CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 7925e100bc22e408cb202c72d9fb74737ff213ee..56da3720d9613efce17ce724f91a9a52ac067422 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x81000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0 CONFIG_TIMESTAMP=y CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y @@ -30,6 +32,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y @@ -43,6 +47,8 @@ CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL" CONFIG_SPL_POWER=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -54,6 +60,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index c1ad2a59ec979d64cb25062468289eecfa36d3fb..bb03e487f874f5615faa525fc3db067c563124c6 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -9,6 +9,8 @@ CONFIG_AM33XX=y CONFIG_CLOCK_SYNTHESIZER=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -17,15 +19,21 @@ CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_boot CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0xb0b0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_FS_EXT4 is not set +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y # CONFIG_SPL_YMODEM_SUPPORT is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -44,6 +52,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_DFU_MMC=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 48e72f8227635862db27bc177be00d53a66696e0..ac451026b09a3cf809e11d373ad383b98fb93c4d 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -20,6 +22,9 @@ CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_boot CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x9ab0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_FS_EXT4 is not set @@ -28,6 +33,8 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -46,6 +53,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_DFU_MMC=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 04566142ef53ef694f4cf025c16492f0e46ed785..6da31d9e7f981b01b6a385a2f9e7b5e53d5c5e1b 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -14,9 +14,13 @@ CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt;run mmcboot;run nandboot;run netboot;" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y @@ -36,11 +40,15 @@ CONFIG_SPL_UBI_LOAD_MONITOR_ID=0 CONFIG_SPL_UBI_LOAD_KERNEL_ID=3 CONFIG_SPL_UBI_LOAD_ARGS_ID=4 CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index f6aa825ee43d9a99c63658338910aff56977a25c..9757057b85e72095cc49038d01b62e38f7b64b4e 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -16,17 +16,22 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_LOCALVERSION="-EETS-1.0.0" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=1 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run eval_boot_device;part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;setenv bootargs console=${console} vt.global_cursor_default=0 root=PARTUUID=${root_fs_partuuid} rootfstype=ext4 rootwait rootdelay=1;fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};bootz ${loadaddr} - ${fdtaddr}" CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMINFO=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 65cdc2acf566250771d24d914e6df241815e2219..070674651ffda9fbe35dae3f5d4a021f567e00cc 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_AUTOBOOT_KEYED=y @@ -30,17 +32,24 @@ CONFIG_BOOTCOMMAND="if mmc dev 1; mmc rescan; then run emmc_setup; else echo ERR CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index a59ebf4a4ed5879116fdaf4526eee5f0693a4467..595e7301cf9e721ef610eb2b6d975b032dd3e9d9 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SHC_ICT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_AUTOBOOT_KEYED=y @@ -28,17 +30,24 @@ CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 3c291cfe6d626525cc64aede421752f83a27c393..d5cd182acb8314c20da6fda9f9340a098154018d 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SHC_NETBOOT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_AUTOBOOT_KEYED=y @@ -31,6 +33,8 @@ CONFIG_BOOTCOMMAND="run fusecmd; if run netboot; then echo Booting from network; CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y @@ -38,11 +42,16 @@ CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 8c4f14d764e16e20c9e9934669b3994bf41dba45..e9e89f627e20c9b94127f39a12b33da5a2da1318 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SHC_SDBOOT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_AUTOBOOT_KEYED=y @@ -31,17 +33,24 @@ CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 41017de2f9c3afb69d6a9a2c641e101a5f328c74..f2385e3d703a64410107a8fc0d9f25d39e769ac2 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -15,12 +15,16 @@ CONFIG_ENV_OFFSET_REDUND=0x20000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y @@ -34,9 +38,13 @@ CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y @@ -61,6 +69,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 904fc5302be644c46f2f6e4a2d018d5954593ba6..19e01dc41ae295b4ad244e7cc0040aa72c768697 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -14,9 +14,14 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2500 CONFIG_SPL=y CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_BOOTDELAY=10 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi" +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set @@ -26,10 +31,16 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x84000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x2a0000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 # CONFIG_SPL_POWER is not set CONFIG_SYS_PROMPT="AM3517_EVM # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0xaa0000 diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 7a736b6fe1a341c18506d9beda6652a5884d6ed2..35b1cdb401666319fe9125f6b6d8ddfe698805db 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -10,12 +10,18 @@ CONFIG_AM43XX=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x439e0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_ETH=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -23,11 +29,15 @@ CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x300000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 2a36dc580e98e9ba20c3aba8d5349cf32156b969..18be57a2fe993ceda3ff2fadac2afa16094bb33f 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -12,11 +12,14 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm" CONFIG_AM43XX=y CONFIG_ENV_OFFSET_REDUND=0x120000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_QSPI_BOOT=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y @@ -51,8 +54,6 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPL_POWER_LEGACY=y -CONFIG_SPL_POWER_I2C=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 30e44cb65e3fd4c1d1046c9b8655cf3819a5e221..ff5fbc6676ae522d470e0454e0764cc363cce46e 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -10,18 +10,28 @@ CONFIG_AM43XX=y CONFIG_SPL_RTC_DDR_SUPPORT=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x439e0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x300000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index e844106243d28964d1b65850f44b8b0ac2216662..0a4b9a99ceeb31669f65b80efa5cd5ba75b1c0bf 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -9,21 +9,31 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_AM43XX=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x37690 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x300000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 1517b707048645f8be0d73dafabea1fad7a2e2ea..c401d5619a98f021805bed154f9ab72e7fe5a305 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -16,13 +16,19 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x36100 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_ETH=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -33,6 +39,7 @@ CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 4223f00156c81578fc6fa1472ac8232c9f8aa35b..249e6702dd76708cd50284d01885bdcf4a87425a 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -15,6 +15,8 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y @@ -26,16 +28,24 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y +CONFIG_SPL_MAX_SIZE=0x7bc00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_CMD_SPL=y @@ -98,6 +108,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 529636d335484493b819cce6ee0fe8c81b8338d2..aa0b466d95486b5b22419e3aa1a8fcf952a468d0 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y @@ -29,12 +31,18 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y +CONFIG_SPL_MAX_SIZE=0x7a8b0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -90,6 +98,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 3149bd1719f3c69c2419a954da5a81cceb93550f..1c37b635406a322a044fa7b0e49c92b46a21508c 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -32,8 +34,12 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y +CONFIG_SPL_MAX_SIZE=0x74eb0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_RAM_SUPPORT=y @@ -42,6 +48,8 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -99,6 +107,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PALMAS_POWER=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2c0bd4d2e10cc5392b75136559664c34604cc25e --- /dev/null +++ b/configs/am62x_evm_a53_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_AM625_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x800000 +CONFIG_CMD_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..deafb92fc1422a80e2195d8779721494b79083da --- /dev/null +++ b/configs/am62x_evm_r5_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_AM625_R5_EVM=y +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c37800 +CONFIG_SPL_BSS_MAX_SIZE=0x5000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index be702285d5dc84e02c4ea30efb27cd69eee9bdb8..0f547526fe625f7da7c500c405a2194c9262e44f 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -25,19 +25,28 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x180000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y @@ -53,6 +62,8 @@ CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 158c43e2bce56443012581185afc9d4bee193020..7226af760e3ed3ffe0f373bfd6b6ea607c19408d 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y @@ -31,11 +33,19 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x180000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x7019b800 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -60,6 +70,7 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 9f41b397c346796a5e86cd344856dd5db37464fe..65e41e5b6afb93f802f76832c4477dad044e89e0 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 @@ -33,12 +35,19 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y @@ -55,6 +64,7 @@ CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y @@ -170,4 +180,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index a8f9a85deae3bc49b68e9812d25fb65f45ef1ff8..5232b979709d1a9a285c690978d768eaea904076 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -31,9 +33,17 @@ CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -52,7 +62,9 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 57cd0f35a56f27c3bdeb434165769f69a429f3d2..7507128c11e90a30089d1a4596de2f527d385fea 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -16,15 +16,30 @@ CONFIG_SPL_TEXT_BASE=0x41c00000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x7ec00 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y @@ -39,7 +54,9 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index e6147d1be36dc002d97afe6d1ae3d96e0ef9d407..e7e222647322c7f832199bbbafae46289cd789ba 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -16,14 +16,29 @@ CONFIG_SPL_TEXT_BASE=0x41c00000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x7ec00 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y @@ -39,7 +54,9 @@ CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 05063d30c84a584bfebd71707065cf48bc1e03c7..3ce290467ab454b5a7d5193d7587ed7f479b5992 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -33,11 +35,18 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit" CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y @@ -49,6 +58,7 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig index e52941e396609bed28f9470c1f32dacb47fb6589..6e63f0e880787ef747f209828e729d144ff9ed7f 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am65x_hs_evm_r5_defconfig @@ -23,13 +23,23 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c7effc +CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -48,7 +58,9 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index ae44b66d10929fb8819d732e29f9ea3497ac859d..72f97cee4de5e9edea16a5c0dfb358c039b505ef 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -7,6 +7,9 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index 00620d4579f97ec8371bff9421fd02eeccd4e86e..ad549c02c1528794176983094e5f9c1598a2487f 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -15,9 +15,11 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="bootm ffc20000" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="amcore $ " +CONFIG_SYS_PBSIZE=282 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_IMLS=y # CONFIG_CMD_XIMG is not set diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index 13120f370e25201477b8a0d027a59c3fc3b4b819..e522a3f4c018650e5d4c8ec588ba590c9b447f3c 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -5,14 +5,16 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="ap121" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xb8020000 CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ARCH_ATH79=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_END=0x83f00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xbd007fff CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" @@ -20,7 +22,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f650000" CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SYS_PROMPT="ap121 # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 2f1a9f3cc124fd959e32e8fa37dba2ad4021bd4d..4bdcea30602691875c6ef2494ae436f3d794620d 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -6,15 +6,17 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="ap143" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xb8020000 CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP143=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_END=0x83f00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xbd001fff CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" @@ -22,7 +24,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f680000" CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SYS_PROMPT="ap143 # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig index ded583f398d450054d0195eed9a5369625e1c748..adcc6c54a8f8e9021d715c5fa4911b1d718a5d0a 100644 --- a/configs/ap152_defconfig +++ b/configs/ap152_defconfig @@ -6,15 +6,17 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="ap152" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xb8020000 CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP152=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_END=0x83f00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xbd001fff CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" @@ -22,7 +24,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe;mtdparts default;bootm 0x9f060000" CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SYS_PROMPT="ap152 # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index beb20f6e1c0178f14f96c6e5a59e747fcc6e13a1..b1e6dda8546b2b84dc0bd0e7603f67b0ecfbbc7e 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -21,6 +23,9 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index e098b1171ee21b980e30d1e0cbcfe9a182e5bed0..39ee46dbec7306a9bd8abe779663aee62308ef08 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_APALIS_TK1=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -21,7 +22,18 @@ CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Apalis TK1 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -47,6 +59,7 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y CONFIG_E1000=y +CONFIG_E1000_NO_NVM=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_DM_PMIC=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index ea4ad276e7f2eebf6df1d0a46270e722bfa5954f..f9721796dbf9fa17385bd44c28fca6bd6ebb2573 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -36,12 +36,16 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_PROMPT="Apalis iMX6 # " +CONFIG_SYS_MAXARGS=48 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1055 # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -75,6 +79,7 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y @@ -100,6 +105,7 @@ CONFIG_DM_SCSI=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 86d48eb6d92c0a2732133f6f119a25c50d98288e..f5d958646fa7792194f74b2a8a2a0f9858f6a134 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -17,7 +17,18 @@ CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Apalis T30 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -39,6 +50,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_E1000=y +CONFIG_E1000_NO_NVM=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 886fc4a6febdf5e348f70081f69d4878ff26d6af..4ba09334d4221e0aec6b8e60a28fd48f2d387fdc 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -6,6 +6,9 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_NET is not set CONFIG_APPLE_SPI_KEYB=y # CONFIG_MMC is not set diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index b3bc406aa6c55ebae5423704577bd69542b5b977..26bcb00ff5373511de9c2aad34eaa060b089b473 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set @@ -49,6 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red),-(ubi-nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 30177fa46b1a20eb69fc79e508dc26ae6ef3da3e..682903082cba74a0c328a305f984a5c6abdf1bd9 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set @@ -49,6 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red),-(ubi-nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index 4d3b3a3c51e265c13451ae45965201a6b04e9a38..6a67c60dd425eeccfb0a09f60cf2701e72a29ade 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -15,10 +15,14 @@ CONFIG_TARGET_ARMADILLO_800EVA=y CONFIG_SYS_CLK_FREQ=50000000 CONFIG_SYS_LOAD_ADDR=0x44000000 CONFIG_ENV_ADDR=0x40000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe8083000 CONFIG_SYS_MONITOR_BASE=0x00000000 CONFIG_BOOTDELAY=3 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index c7fc2454b3230b12ca4200f3a29a5b12e2a3567d..5beba58776664da62c74702503eed313d1a8ce7c 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -17,13 +17,18 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" for ARNDALE" CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3800 CONFIG_SYS_PROMPT="ARNDALE # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 1eea56b5ef29630418576ecb8ed0537cf8bf2cb3..3a44c7e8ec9d68400431e3356aebe148d85d4da8 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -16,9 +16,11 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&run alteraload&&bootm 0x80000;update;reset" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="URMEL > " +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_IMLS=y CONFIG_CMD_FPGA_LOADMK=y CONFIG_CMD_I2C=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index a2e1272c35845ffc71f7e0053e3cc05c4019e780..62b467ea30970e22ab44468a7ffb25b3180f333c 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 204f7e3173ce845f8fa28117698726f0d43fc642..a5ccce1eae256379d05f45868f134ba97d14bfdb 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 547f11ce6a0d12b2c15069fbe58d6fe40b42e312..d3706d158b7d386a4e62d6b32a0d2e3eba3e0c85 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -10,9 +10,9 @@ CONFIG_AT91SAM9260EK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -24,6 +24,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -61,3 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index dc6b40c04e9a2222587d77c1f2ea499e274847bb..d479d76c79ec23a68e55388ccd95e4d4f9a15ed6 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -26,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -63,4 +65,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 5d7a7f170932e988ffba53bc53018f16a63f5de7..96c44e9a16286a60594b645b85451a729ebd5b35 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -26,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -63,4 +65,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index ee250d7e4aec7130daa592b05d8c3657166d976d..16de5195119122e07634be7da5e084b17d15d2fc 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -9,9 +9,9 @@ CONFIG_AT91SAM9261EK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -25,6 +25,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -61,4 +63,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index d0d5b1a572f65a873806e271629048d8ef17fe81..e73ff8861bed8a60aabd7bfccc0eb3975fe6fd2a 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -27,6 +27,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -66,4 +68,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index d0d5b1a572f65a873806e271629048d8ef17fe81..e73ff8861bed8a60aabd7bfccc0eb3975fe6fd2a 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -27,6 +27,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -66,4 +68,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 1807e3cb97a1ed8282cc77b605cb655e13660d55..184431640e66750c8dc19429cf9c800df2bb93e9 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -9,9 +9,9 @@ CONFIG_ATMEL_LEGACY=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -26,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -64,4 +66,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 585e10b891b9b8ff288fe5857fcf7cc3320cbc4f..7b975813928c11e6db84516cbd3ef80e2ef63ceb 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -11,9 +11,9 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_ADDR=0x107E0000 CONFIG_DEBUG_UART=y @@ -24,6 +24,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -66,4 +68,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 19b3d9da88a5c5cd509b19b069478263f4db2047..2c354f3b5b513216ff06ed996adf1a66f92f03a2 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_ADDR=0x107E0000 CONFIG_DEBUG_UART=y @@ -25,6 +25,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -67,4 +69,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 18433376c71befebc6e9655b8e0c964498f3fa9e..ee4de9b67d67e3a5505ab20a5c4d97fb41b3747d 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -26,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -60,3 +62,6 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index edf84fd0b5156489cc97cdfb2bd80a4a5ae35e46..4a47ad128655045db4896dbbde5ca3e28cd39adc 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -26,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -60,3 +62,6 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 390516c76841a8bacd5172c36f9528c093df0534..0e3d0b13140ccb5afca12dea48c4227c4bf48749 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -9,9 +9,9 @@ CONFIG_AT91SAM9G10=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -25,6 +25,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -58,3 +60,6 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 34b0b830e54415188e00ecb36e1fec4f6969bbe0..add019c10afd788dc69f87bf467f4795525c202f 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x2000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_SD_BOOT=y @@ -26,6 +26,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x22000000 uImage; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -64,3 +66,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 0eb118e93f408a103d37156c90a23e66905e67ea..72a21c3da94d95f3001e587908964d474332a5a8 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -11,9 +11,9 @@ CONFIG_AT91SAM9G20EK_2MMC=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 596c9bf6ed4228790f6ba9e2331b286f748b9e76..03b029cee8d9fb10b341f5fb3357af825067d7ae 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 281894d91fa35fe732dd5d2cdff378a2d50e6ddb..1ae1b28feefdaa32263ed51bdf6b3a7fa6de6c5f 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index d7a57db08b880f3fe9b76937e03b8b2f5ad43a14..77ad4b9fda2d60ca5d79a41996a71615014168eb 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -10,9 +10,9 @@ CONFIG_AT91SAM9260EK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -24,6 +24,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -61,3 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 03e6d3a9bd5306ae6d11bed9033dbd151ae48816..18693919507cc9b30b73159c2cbae736b5aae3d3 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -9,11 +9,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00 CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -25,6 +27,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index f1c8574685aafe73fdcb8b6bb751e7a9a05a3662..46938e5362bb7c06a8a8caa6fc9c35393a97cf74 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -8,12 +8,14 @@ CONFIG_ATMEL_LEGACY=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -25,6 +27,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 9cb1ea28f3df9110e424ed3a9986c26f487ea57a..95f62e84e43a8eff68b574364f3f74f4e24ef631 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -7,11 +7,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00 CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -20,6 +22,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index d73d80b5af842b1502b338149612b738f0bb4c85..5ffa29448226dbb0999034b0d32807578c8ab628 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -6,12 +6,14 @@ CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -20,6 +22,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -44,9 +48,7 @@ CONFIG_AT91_GPIO=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 9c984a941fefb8411894fa35641894896303bf01..a85afbcc9ee96250f0bb5a9594a836e511f98b92 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -9,11 +9,13 @@ CONFIG_ENV_OFFSET=0x5000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00 CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -22,6 +24,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index fad75acbebe974cf13d8d25c2e7b263efde24dd4..20093a8098644069ca32d61242c112464321b36d 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -26,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index fb683a722ce7b0195dfbbf78187985e8c4882a50..ea790941e3e408ea7449fddecbf5da5f4b5bfbe5 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -10,9 +10,9 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_SD_BOOT=y @@ -25,6 +25,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index e42a999dcc208f5f3c679a29093fd556e6f45c3b..18c630ed34e6a399d320c20fa2c9d8350f877785 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -9,9 +9,9 @@ CONFIG_ATMEL_LEGACY=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -25,6 +25,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 2fe34776b66ea0652aa8c48c744da2bd09b622ef..da37fb507a9150db5bd7b60dd2fc2f15ff6e9402 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -11,11 +11,13 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -27,6 +29,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -51,9 +55,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 6bca1c6d38e14fc11eac29cc4942ca8179184915..eee25d25b75ad077e8b11a840c8ada46defd2bcf 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -9,11 +9,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -24,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 327fa336a85cd96f6dcda7291c5404bf9529149e..9d581734f946e930a747eaa1d02313b1bc5602c5 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -8,12 +8,14 @@ CONFIG_ATMEL_LEGACY=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -26,6 +28,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -50,9 +54,7 @@ CONFIG_AT91_GPIO=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 50b3fc9b51573e00fc1363720484915faf89f595..f4917297961c882eed64d8ba59b0f37470e0c0be 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -11,11 +11,13 @@ CONFIG_ENV_OFFSET=0x5000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -28,6 +30,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index a2e1272c35845ffc71f7e0053e3cc05c4019e780..62b467ea30970e22ab44468a7ffb25b3180f333c 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 204f7e3173ce845f8fa28117698726f0d43fc642..a5ccce1eae256379d05f45868f134ba97d14bfdb 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -13,9 +13,9 @@ CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 @@ -25,6 +25,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:1; sf read 0x22000000 0x84000 0x294000; bootm 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -63,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 547f11ce6a0d12b2c15069fbe58d6fe40b42e312..d3706d158b7d386a4e62d6b32a0d2e3eba3e0c85 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -10,9 +10,9 @@ CONFIG_AT91SAM9260EK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y @@ -24,6 +24,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -61,3 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index f27d92ab7852bb8ceb7c97275e8e420b60e406a2..0574ee95e421809259ae439c03f65cc1d488edd4 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -6,8 +6,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_ZYNQ_MAC_IN_EEPROM=y @@ -18,6 +16,8 @@ CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,7 +26,23 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 +CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub" +CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin" CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x8000000 +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 89b9f9faea717c3a9bea46db698be10d35bb52cf..a5f60bd8d0c47aa9655e3469b3658da2d9e257f2 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -7,7 +7,6 @@ CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_TARGET_TAURUS=y @@ -17,6 +16,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" @@ -35,16 +35,31 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flash_self" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x3e00 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3e00 +CONFIG_SPL_BSS_MAX_SIZE=0x600 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x304000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x460000 CONFIG_SPL_CRC32=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_SOFTECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 0f3e06263d304623c4d6ff4b56dbba1c76b9af49..c744b38cc48bc52f94ddc044936588fab6e1615a 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -10,6 +10,8 @@ CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=750000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" @@ -17,6 +19,9 @@ CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=278 +CONFIG_SYS_BOOTM_LEN=0x8000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index d86fb9c8d3c11a53c37eb8c7063fd049a9e3a29e..29affdc5e96477ae5136a7e172de1f947d8c0aaa 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -10,6 +10,8 @@ CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" @@ -17,6 +19,9 @@ CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=278 +CONFIG_SYS_BOOTM_LEN=0x8000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y @@ -58,5 +63,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index b89dd8ea62b4608cdc35d268223665858b0b4731..66c444fc750734f2581f5c4875114de6193ea22f 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,7 +9,9 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig index 798564e1730cbdd402a723304c719303535af0ea..b54272c2b38d3f383410f8b0bea6354f9c3a142e 100644 --- a/configs/bananapi-m5_defconfig +++ b/configs/bananapi-m5_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING="bpi-m5" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 2f0c22f62fa8c807d9be406b082a349c73df1838..290e9c17e2118cd75580f5eaa859a0f40f5a3933 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -9,9 +9,12 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index a35fcdb64e8ddae7d02d81ba5be21579b4cee3e1..e6b8f0f8a3f846ce864b11269fa7154bdf41a8a5 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -9,8 +9,11 @@ CONFIG_USB1_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index 26ced59fb02b49a2439c7bd0ed3ee8e2f0f8a10e..d0981f6481af19280cb3092627f55a47fda7d54f 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index fb6c945919a059f62068513cbad864d4a5d03c3e..a68742e9d6a771bb5593a905e4820476f54d8704 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index ac3f8f5ab8bc923a4addbbdb698b99fa62394c52..6a3594c0938d87b45214300878bec4afe99073cc 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -6,3 +6,5 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 5463b046fdb2021c71f6e777378800ab18fb0ce7..36aa80a09baa7dfbdee4ecf036f6d72e10cd75e4 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -7,6 +7,9 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 667240bff1ca8af4ee7ea042eca4cb870d8141af..d1a467dfe79e298126d2dcdf63f83c6e1d9ab224 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -54,6 +55,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y CONFIG_SPI=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 401a2d7414cace498f6047a95b57852d0d6da732..c44e6ba4ffcc8277d67736b8f09cd999ec3da600 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -19,6 +19,10 @@ CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsavea CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=536 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index b30d4bba0243c4d1ab46be8962e6a365ebcce740..bab2c76efb73b4683aecc97985024e52160b4bd9 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -20,6 +20,10 @@ CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsavea CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=536 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..c61fbe1848e66865ec73578f5c6ac84778f3a94b --- /dev/null +++ b/configs/bcm947622_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCMBCA=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BCM47622=y +CONFIG_TARGET_BCM947622=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="bcm947622" +CONFIG_IDENT_STRING=" Broadcom BCM47622" +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_CLK=y diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 642faf511f5aa6d33c2951952454be9272f1a8ac..424eca7946b8069586dba7f51de2a1398d9e8b19 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -12,6 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="bcm963158" CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_TARGET_BCM963158=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x11000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_RSASSA_PSS=y @@ -20,6 +22,10 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/bcm96753ref_ram_defconfig b/configs/bcm96753ref_ram_defconfig index 9a72c75000bd7d03aa85bc392dc7cdcd647e535f..59ac1cdf7e1e4a4c84a2e2be89bf4276a7adde5c 100644 --- a/configs/bcm96753ref_ram_defconfig +++ b/configs/bcm96753ref_ram_defconfig @@ -13,6 +13,8 @@ CONFIG_ARMV7_LPAE=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_TARGET_BCM96753REF=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_CIPHER=y @@ -23,6 +25,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/bcm968360bg_ram_defconfig b/configs/bcm968360bg_ram_defconfig index cde18125633bca4bc991cf312ed7ec5a2f18d300..7f9093c6f6d3e2125985b2f1545401bc301dcfba 100644 --- a/configs/bcm968360bg_ram_defconfig +++ b/configs/bcm968360bg_ram_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg" CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_TARGET_BCM968360BG=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x11000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -18,6 +20,10 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index b6181a2e10e9bdf40c890b1473b5ec57eeadd976..0475535e9910dfa1f73812b57bda27b1ffefd5f5 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -16,8 +16,12 @@ CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="bcm968380gerg # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=545 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index d1a17c758fc8b98885f2ea6e8e85428830151eee..a8c7ffa748758be9cb3a22040bde4363b8f343e6 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_TARGET_BCM968580XREF=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x11000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -18,6 +20,10 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 9267bf361890e21748ee9ea9c5fdea4a75c84f10..9181b9e47743fcac0d46735b664684cca8874a5a 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ns3-board" CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_SIGNATURE_MAX_SIZE=0x20000000 @@ -24,7 +26,10 @@ CONFIG_SILENT_U_BOOT_ONLY=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1049 # CONFIG_SYS_XTRACE is not set +CONFIG_SYS_BOOTM_LEN=0x1800000 CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_MMC=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 8aa8438467bd3d04434c623ba38718e90048a294..dbaa7ac3198e66fbce62d701deea56235fe6d77a 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -14,7 +14,17 @@ CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra30 (Beaver) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig index 841a482602f5cd985f0dd5179946cb1bcc250de8..2a7fddd7eb58677aae2e66d1ca68f492c7ff7ed8 100644 --- a/configs/beelink-gsking-x_defconfig +++ b/configs/beelink-gsking-x_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" beelink" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index f0500411c704d2f35dcfaef8cf5b90590b5e8491..862445375dd8a9c08936e34259c5ed77c4263336 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" beelink" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig index 86c1d3f67346390ab66efbcee179ff8ec127c1fa..f9300a21acb91428126c556cb66148ca38646481 100644 --- a/configs/beelink-gtkingpro_defconfig +++ b/configs/beelink-gtkingpro_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" beelink" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index 42925eabcb0a483a5db1489e2d4d55387fb6c437..2c440e44f5dcd7bcc4cb6b4a30401ab9432ab2f8 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -8,6 +8,9 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x118000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index 6206d90900311bc753f8999e7ae1bf738490c377..4065e64d523f97da8fffd3fde6440e5cf9cdcfd9 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -6,5 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=567 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 721deb37ea23823ee9b8ecd718a6691ca1599012..b0d2105db6e45c962a3201a11fb6957ac9f22ac0 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y @@ -27,10 +26,21 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="antminer> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=2075 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_DM is not set # CONFIG_CMD_FLASH is not set @@ -46,6 +56,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 324a80e4af15b50c9811f4530f07181999d4e1e5..0f8955dbbf183c203842c505aa234f9fb2cd3fa6 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -30,6 +30,8 @@ CONFIG_BOOTCOMMAND="run set_gpio122; run set_gpio96; sf probe; run manage_userda CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_CMD_ELF is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -39,6 +41,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 1ab40d617ab2e4dcb522f967277ac1d0cd4d1f7e..42f3dc4b6f4790b6fd481750fbc537c284901ee9 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -16,9 +16,13 @@ CONFIG_R8A7792=y CONFIG_TARGET_BLANCHE=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0x40000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -53,6 +57,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index b27ce773ede6a15ebab53ddbb087f8e19d53a8ef..2be57d2d1ed9e6271b956554f7418df70efe9284 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -19,6 +19,9 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 985e8bdb051e90d94498b42ae8c23853fab1ab82..524564355f444157980d8731b3df6b99bedbaf18 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -8,18 +8,21 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index bedac025402dfbeabe67065f0e18025bb9720d55..7bb4e692d6b7c4a33a0f8fb2b78553937d934a9b 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -20,6 +20,9 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index b90a58c502f9ca75434f8538095895897e3cb24f..8ae2f235b1a7de5e3b602870efcb50ab293fa649 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -8,19 +8,22 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R6=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index bca4a0412ccc610dca633eb445f304a11ce63cff..4a41e6b5cc64ac13bad37e8a6fc8161677f54fc2 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -20,6 +20,9 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index 681c05321aeb7004349cb0763f6cfc9f19e6338d..0670ffabbbb2c13f9acc232dcbb78c43273e5cb5 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -8,19 +8,22 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R2=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index 0aabb22b2fc015ff1e15ea4ca225b78e40bf212a..bf7f709524b93fa93e4c8afbaa87086bda23f06f 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -20,6 +20,9 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index f1e0175db7bd7133ca39de64f3a1caf510c15b88..e1d46d30606af0d534576fdb18572491b306dcda 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -8,19 +8,22 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R6=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index f1e7f81c40150e08df0ee5d6fba0f0e116d26be0..f088e0bdc099a1d84a9f67ffa6fd85ee52d449d6 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x50000 CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -32,13 +34,19 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -54,6 +62,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index d75090a245cecd09a6c0b3af52240364883bd5d7..7f961ae473cba0f57ae45173d9a62cfe8fa0b22d 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -14,6 +14,8 @@ CONFIG_TARGET_BRPPT1=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -29,6 +31,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y @@ -38,7 +42,11 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -54,6 +62,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 33780488e6205ceccafb5e36415142db712699f6..5d6dfbd5c449db6d783936590d0cbcaff6ce2597 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -20,6 +20,8 @@ CONFIG_ENV_OFFSET_REDUND=0x30000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -36,6 +38,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set @@ -46,7 +50,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -63,6 +71,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index ab767ab737ef07973d4ceea26a3a39e2b5ae13b2..e2c36e13add8439f76a7c76a54ed4702aaf88083 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y # CONFIG_SPL_SYS_THUMB_BUILD is not set CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_MX6=y -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SYS_MALLOC_F_LEN=0x1000 @@ -10,6 +9,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -32,12 +32,15 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run b_default" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_SPL_MALLOC=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set @@ -54,6 +57,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index 1eef3bde06071db728dd559325c1a70a502871cb..0a906ca95517f0cee2b1a1d57927ead65ace792a 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -20,6 +20,8 @@ CONFIG_ENV_OFFSET_REDUND=0x30000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -35,6 +37,8 @@ CONFIG_BOARD_TYPES=y CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set @@ -44,11 +48,15 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -65,6 +73,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index c1acbe0259e9b081ea1c443606417383d73e4371..c38393410f3d13e1bb7728eb3927ec2b64c77d3c 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x50000 CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -31,11 +33,16 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set @@ -56,6 +63,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index a21b245c845ed0348e4014fedf05bf75d05aeb55..8dc928a9274ed618c80e411960b75ba618e231d1 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -8,12 +8,17 @@ CONFIG_MACH_S900=y CONFIG_IDENT_STRING="\nBubblegum-96" CONFIG_SYS_LOAD_ADDR=0x7ffc0 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1107ff00 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyOWL5,115200n8" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_CACHE=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index a2126eeadff1332983ef23da274d08abd9b60fb5..bf8504fd72528076a2c43f4ba54d8b0d66709c23 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -13,7 +13,17 @@ CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 197d462ce061fb035e3bfef37535290a6dda66cd..35f8d9c7817792a14ff87c6a475e363ae2bbfa1b 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -10,12 +10,23 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_TEGRA_GPU=y CONFIG_ARMV7_PSCI_0_1=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2086 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index c53fa742751aac9da45b6b7232d8d6142c8e1881..5dea71980ba047fbd926a6342e681c49ff497ac7 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y @@ -26,15 +28,28 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x13e000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x3000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_CLK=y CONFIG_CMD_DM=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 38302ddc2f282c91520a3ace29030178f34749d5..9c3d26a36e13c7a2ff9a91aa9d0355325c95f1b6 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y @@ -44,6 +45,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y CONFIG_SPI=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 1b03d836944e0d6ab3ab59ecfec7e48a61316b7e..05569061429942af347f654bae664353b6d4661c 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -16,18 +16,23 @@ CONFIG_ENV_OFFSET_REDUND=0x22000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0 CONFIG_TIMESTAMP=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run mmcboot; run nandboot; run netboot" CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -49,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MISC=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 81662915d2489c218e749cbef3f4f32a4211cb38..dad3b36b99374842441d94dfcee3a84536944169 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -18,18 +18,25 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 1b2db5d0a8fb1bca60edae204d206eeba1692f32..938bc28a1d278533d8297e1ae02404229b5f656f 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +28,15 @@ CONFIG_MISC_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff8effff CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y @@ -93,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 82692542078dd2d9a0d252a6b80600b69312c1a3..60c50e75be6522777ba32b6cf9ace6f7706dead0 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -9,9 +9,9 @@ CONFIG_SPL_TEXT_BASE=0xfef10000 CONFIG_TPL_TEXT_BASE=0xffff8000 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000 CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000 -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xde000000 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_CORAL=y CONFIG_DEBUG_UART=y @@ -41,16 +41,18 @@ CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x30000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_CPU=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_PCI=y CONFIG_SPL_POWER=y # CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_TPL_POWER=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_PMC=y CONFIG_CMD_GPIO=y @@ -85,6 +87,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index d3d9f8fc0ba02786c03d0e52b2524ffda954da9a..35d546e631596d9e4537adeab19717571737d550 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" CONFIG_SILENT_CONSOLE=y @@ -24,13 +26,18 @@ CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index ad6cbca198b8ccbe8fd6bdb2580fe600e0b35e5d..6f88002f968c9d2f120055c45520a9c3bf1fffc1 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -19,6 +19,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -27,8 +29,15 @@ CONFIG_MISC_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff8effff CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y @@ -94,6 +103,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index b29c5ccd7a4d2a9816ac95b699c39ecae72618d8..b645cba907090db7fc82eb750ac8d33787f66636 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -7,9 +7,9 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_SPL_TEXT_BASE=0xfffd0000 -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_X86_RUN_64BIT=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_LINK64=y @@ -32,6 +32,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y @@ -42,6 +43,7 @@ CONFIG_SPL_PCI=y CONFIG_SPL_PCH=y CONFIG_SPL_RTC=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y @@ -68,6 +70,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 9186621f8d0c8200e27ed270a535453bc6119f41..fa3641e42f53447ad24356d133a42ba00c0bafe6 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -6,9 +6,9 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_DEBUG_UART=y @@ -28,6 +28,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y @@ -59,6 +60,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 63899f37aaa7cb17cfabfafbf395e0f1314931a7..60fc528a8ce70182c87b3fd4862addcce72fd2f3 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -18,19 +18,26 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 93f1d403fa2aaa7eb670b6091d5b8e15061bfb44..56a0d6c8a8eedd563692d0e92552395874338852 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -6,9 +6,9 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_SAMUS=y CONFIG_DEBUG_UART=y @@ -28,6 +28,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -61,6 +62,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 3687118239507a8ab12cf8c521666b70eaf60311..1e1091fa7eed1539bb3d60fb1af81047ce68df26 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -9,9 +9,9 @@ CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" CONFIG_SPL_TEXT_BASE=0xffe70000 CONFIG_TPL_TEXT_BASE=0xfffd8000 -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y CONFIG_DEBUG_UART=y @@ -35,6 +35,7 @@ CONFIG_MISC_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0xff7c0000 CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y @@ -46,6 +47,7 @@ CONFIG_TPL_PCH=y CONFIG_TPL_DM_SPI=y CONFIG_TPL_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -78,6 +80,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 9343263be5ecd6515d956cd2560b5c059e2622cc..e6f03faa87e8a9177466c7823b1881f690390210 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -18,19 +18,26 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 363b5f39f019e87a246b48d7bf0c97afd25eedad..870843ada580dbbf8b8305d4e8d17bf201e8fbd7 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -24,6 +24,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y CONFIG_CMD_SPI=y @@ -52,6 +53,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_RTL8169=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 867b9bba7e0e76697f5e18722f7a8c1f9a153f42..07848a5933ebe136efa44f7b5dcc886b6663cd49 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -22,11 +22,19 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x2e00 +CONFIG_SPL_BSS_START_ADDR=0xf4004000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xf4008000 # CONFIG_SPL_BANNER_PRINT is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c CONFIG_SPL_MMC_TINY=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DM=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 7c708257b4862de7cec92e0aaf0c747ba52ca683..bf670dbae68954f43fbb08edb15ebdb5cc68abbe 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -25,12 +25,18 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="echo SD boot attempt ...; run sdbootscript; run sdboot; echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; echo USB boot attempt ...; run usbbootscript; " CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CL-SOM-iMX7 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=543 CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set @@ -46,6 +52,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 9f744d0caf96e391af516547e7de251b60721570..1ee0c6637573e26ffd58d7598873d7b852075f30 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -19,12 +19,22 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x22fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_TLV_EEPROM=y CONFIG_SPL_CMD_TLV_EEPROM=y # CONFIG_CMD_FLASH is not set @@ -40,6 +50,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_MIN_ENTRIES=128 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index a82cbafb798bed0c9f99ab82412b442811e7fcd5..baafe3c58c6e25313227437d10fe139c81beba62 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -23,6 +25,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -44,6 +48,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index cfa328157488869a1a687666d915f5ae8cbaa55c..9bf78788e49732367130d63a5844bbc62ab32e60 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -30,12 +30,15 @@ CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="usb start;sf probe" CONFIG_MISC_INIT_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="CM-FX6 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=538 # CONFIG_CMD_XIMG is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y @@ -53,6 +56,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y @@ -72,6 +76,7 @@ CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set +CONFIG_LBA48=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 0b4912bba3dcf0dc826fefa65b15b884b145cb52..f1b4b622cbd56b95e3e54e00357c47756d564327 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -14,9 +14,13 @@ CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y @@ -27,6 +31,8 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_SYS_PROMPT="CM-T335 # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1051 CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y @@ -40,6 +46,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 7a0cd52d737d6cd5af06bed97732bf5b30d97754..c0dc70312a2e835b413dc5ab8e7791cbdae537f3 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -22,11 +22,16 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_BOOTCOMMAND="mmc dev 0; if mmc rescan; then if run loadbootscript; then run bootscript; fi; fi; mmc dev 1; if mmc rescan; then run emmcboot; fi;" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x37690 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y @@ -40,6 +45,8 @@ CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SYS_PROMPT="CM-T43 # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y @@ -55,6 +62,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index eacfc661433900ea7c7da51d1d7072a79434f2e0..42f6087d83c911022122134b1c27978e7e3ae7d9 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -11,9 +11,11 @@ CONFIG_MCFTMR=y CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="COBRA > " +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_IMLS=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index eb4b6a79eaa0ca61f39c57d660584f44de583a09..bfbbf34ae5cd1e87798d5988dfa39d7d9ec941a1 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -21,6 +21,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=547 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_CMD_ELF is not set diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index d0825472b2f783353232a81f26a7a97b29f946d2..a4225d862b4484a51bd8ae6df6af018dbae10927 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=547 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_CMD_ELF is not set @@ -53,6 +55,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 0c9d6b64c1b6a28ea487447af919e929c4b585f7..964d5bebc123b749071b639626fd6b0018e88f81 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -20,6 +22,9 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 4f38d5cb4839a4bc6b5cdaee53228f73bc005fc2..0bdd088b1e7e580c62a373715ed302502037d225 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -35,12 +35,16 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_PROMPT="Colibri iMX6 # " +CONFIG_SYS_MAXARGS=48 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1056 # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -98,6 +102,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 973afc1a2b4bbf15587b8b56f360ad7842b4c722..15dae6b3db947138412c428a4367b66d6aa02d2a 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -25,6 +25,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="Colibri iMX7 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=544 # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set @@ -54,6 +56,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 01b1cb8b55205e4a5848020454d4f4bbefeb5d21..361077ee84e7ceb232f3902ccea42349ef7d864b 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -24,6 +24,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="Colibri iMX7 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=544 # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 00f45dc115fd4b02e06d6cca15b98fe27d0b27c1..92d9dfed30fa203186083beaca5832a130c465fb 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -16,7 +16,18 @@ CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Colibri T20 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1055 # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index abbc0662baee8d975fec1ea7effacd6dac709b95..a9fe05246d6ee554809b5cfc7ff8ed133794dafd 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -17,7 +17,18 @@ CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Colibri T30 # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1055 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index c5f4322923b76937210da3fbbba0bfcd14237598..9dbe6280dd74ce4e527e3b01d72fa0153dca6404 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -29,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Colibri VFxx # " +CONFIG_SYS_PBSIZE=1056 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set CONFIG_CMD_BOOTZ=y @@ -61,6 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index 5d3636e34e8ccdd704bfccf070baf05d25173b1a..f17083310a27b23592e1d59617554687199dd912 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 CONFIG_USB_MUSB_HOST=y diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index b2eb24d2e8081c56f9f3b3fa52e4eab465f9b2e5..36eab571eafe76648685b22971d8a350232ffbed 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -17,8 +17,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AR-5315un # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -68,3 +72,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index bebb4b299813e67b3554f7e1a58cb31f0f9f2ced..68969c041386aaffe27849eba2e621c77cd6e164 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -17,8 +17,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AR-5387un # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -69,3 +73,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index a2011b9663e8fa41ef895c8eb57f3b479b3297d3..cb2caf454350b0adbb7828fc7b852c3ffcf57b76 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -17,8 +17,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CT-5361 # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=539 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -63,4 +67,6 @@ CONFIG_BCM6345_SERIAL=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y CONFIG_WDT_BCM6345=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 8d5646167f75572898f0b89d44fc9b64b9ee7d4d..138d3c84bac7c1a8eb30b63f06c38c41004127ea 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -17,8 +17,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="VR-3032u # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=540 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -68,3 +72,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index a8004d8af8eee6d57c815cb674ce452ec22fefc7..b7174ff5ee34850fa85ea7a87249a31ff904c275 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -17,8 +17,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="WAP-5813n # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -65,3 +69,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 1c5efec707fd2c1eca792a7daead25362f0156e0..8b6957da1629426222f45b0d1ac8236a8d54c49b 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -61,6 +62,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 5aba0e2f7f7790fa0be6769d5b675b9210f1bc94..286abe2f8297dcb1fc75b970ff493e8787378738 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -57,6 +58,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index c366db40e6fa17d1fe24b29ccdc28ba4a8019598..2fc7ba475a3e8e2bbb259d742d1c889a0b153464 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -22,6 +22,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -32,10 +34,17 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_LAST_STAGE_INIT=y +CONFIG_SPL_MAX_SIZE=0x27fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40028000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x40031000 CONFIG_SPL_I2C=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_ELF is not set # CONFIG_CMD_GO is not set CONFIG_CMD_GPIO=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 3427848748680e05cf06cf02844c04ad3aed5af9..a42fc3974aa17d91a36455a3fbbf3bf8899646a4 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -20,7 +20,9 @@ CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y @@ -56,6 +58,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y CONFIG_SOUND_I8254=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index b09f3f03601ab2b7ed4deac89ad1f4b00af20bee..fcd48148f126e08ce7a2a60bdcc62aa2bc2690a5 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y @@ -51,6 +52,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y CONFIG_SOUND_I8254=y diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..ba5cf0308f3ab2394a54287386f0e1a9dc76f7e2 --- /dev/null +++ b/configs/corstone1000_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_TARGET_CORSTONE1000=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3" +CONFIG_IDENT_STRING=" corstone1000 aarch64 " +CONFIG_SYS_LOAD_ADDR=0x82100000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" +CONFIG_BOOTCOMMAND="run retrieve_kernel_load_addr; echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" +CONFIG_CONSOLE_RECORD=y +CONFIG_LOGLEVEL=7 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="corstone1000# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +# CONFIG_CMD_CONSOLE is not set +CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x800000 +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_LOADM=y +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_OF_CONTROL=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_SMC911X=y +CONFIG_PHY=y +CONFIG_RAM=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_ERRNO_STR=y diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig index 6514f0753e4688733dd212cebbbe191cbbd60838..1471deb0a9877016cc09b3a5c2be2ca3bafbd19b 100644 --- a/configs/cortina_presidio-asic-base_defconfig +++ b/configs/cortina_presidio-asic-base_defconfig @@ -11,6 +11,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" CONFIG_IDENT_STRING="Presidio-SoC" CONFIG_SYS_LOAD_ADDR=0x10000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_REMAKE_ELF=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SHOW_BOOT_PROGRESS=y @@ -20,6 +22,10 @@ CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0" CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="G3#" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0xc00000 CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/cortina_presidio-asic-emmc_defconfig b/configs/cortina_presidio-asic-emmc_defconfig index b8a1c96c8347cb5d0030400c931a6c6178128f7f..456f26ced3c2a17edc6f6a48ed401391d9e7e587 100644 --- a/configs/cortina_presidio-asic-emmc_defconfig +++ b/configs/cortina_presidio-asic-emmc_defconfig @@ -11,6 +11,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" CONFIG_IDENT_STRING="Presidio-SoC" CONFIG_SYS_LOAD_ADDR=0x10000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_REMAKE_ELF=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SHOW_BOOT_PROGRESS=y @@ -18,6 +20,10 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="G3#" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0xc00000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_WDT=y diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig index 944fed6ca0378db27d74166919bd35cd228f88c3..be3e6a9bd193a11e69852761b6aa30d916b14833 100644 --- a/configs/cortina_presidio-asic-pnand_defconfig +++ b/configs/cortina_presidio-asic-pnand_defconfig @@ -11,6 +11,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" CONFIG_IDENT_STRING="Presidio-SoC" CONFIG_SYS_LOAD_ADDR=0x10000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_REMAKE_ELF=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SHOW_BOOT_PROGRESS=y @@ -20,6 +22,10 @@ CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0" CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="G3#" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0xc00000 CONFIG_CMD_MTD=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index c0ae60f7e3393dca24f5c9d388e47fa768c69afc..859c9a3104088b0eee1ee73461eee07232cfa274 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -22,6 +22,8 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SYS_LOAD_ADDR=0x70000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70007f00 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -30,13 +32,24 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x3000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3000 +CONFIG_SPL_BSS_MAX_SIZE=0x800 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_SOFTECC=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 9226c780d9a620ac3ca0b24a1f9c43123fd3dbcf..7ee0cb746e40c91f56262a4643ab1a99c223a757 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y @@ -47,6 +48,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 590fee97942db69499b521a05c0ce312c2b33697..fdd0d2badb070eb5c2cad8638f1e9b465f3de544 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -52,6 +53,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y CONFIG_SOUND=y diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig index 2ebba329475cb7d8025c659a656a7407f4c7c1a6..1b46ab4bf97200e4c90180f4b3a654dee68d8ef9 100644 --- a/configs/crs305-1g-4s-bit_defconfig +++ b/configs/crs305-1g-4s-bit_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s-bit" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y @@ -21,7 +23,9 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index 54f5268beafa9fcfd49d63a518ac5569f19c3b8a..a7a3ffe4812db3b1dcc99be4c8ce2dc7fef26bb3 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y @@ -21,7 +23,9 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig index fd31efdd223a6f670c264875b1ab279e89c853b0..70f71de6ae0973e5f1d3ace4371a64654fe6684b 100644 --- a/configs/crs326-24g-2s-bit_defconfig +++ b/configs/crs326-24g-2s-bit_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s-bit" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y @@ -21,7 +23,9 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig index 8c12c595775a5f4438dce0cf5d2c7a9661b553d8..5991b62923af6569f9ec92d8f7dd2590fe5b3bd0 100644 --- a/configs/crs326-24g-2s_defconfig +++ b/configs/crs326-24g-2s_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y @@ -21,7 +23,9 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig index 2334d1e88ca4ea586873ceebb5219776eea2a7b3..434e9fb90f39fc968d07a15639b0eb22eb7f9ee2 100644 --- a/configs/crs328-4c-20s-4s-bit_defconfig +++ b/configs/crs328-4c-20s-4s-bit_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s-bit" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y @@ -21,7 +23,9 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig index 09c3b7c2934db3153811dc6f13f4e5980f5dee78..8e08cceaac4aff604a9b0921e9bdc457da05a5f4 100644 --- a/configs/crs328-4c-20s-4s_defconfig +++ b/configs/crs328-4c-20s-4s_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y @@ -21,7 +23,9 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig index 677bff64b90d50ceeeedd6f8a46a1f65cec38bda..7437d4b4b9d5d7d254977b927bd2a043a4f2e8d2 100644 --- a/configs/cubieboard7_defconfig +++ b/configs/cubieboard7_defconfig @@ -7,12 +7,17 @@ CONFIG_MACH_S700=y CONFIG_IDENT_STRING="\ncubieboard7" CONFIG_SYS_LOAD_ADDR=0x7ffc0 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1107ff00 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyOWL3,115200n8" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_MMC=y CONFIG_MMC_OWL=y CONFIG_PHY_REALTEK=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 897c00e523c5092b9255eee546d6ee5984526849..bbafd57727959e04626c3081ac46c346948e81ed 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -14,6 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net" CONFIG_IDENT_STRING=" D2 v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -27,6 +29,8 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="d2v2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1047 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y @@ -34,6 +38,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -50,6 +55,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index bfc8488e0e8c29920ff55eeb8c71b651312bca81..d7348298587f27dfef2a0331a7a040acce3c95b0 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_LTO=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0000f20 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -33,13 +35,25 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0000000 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x8001ff00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0f70000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x110000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CRC32_VERIFY=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_DM=y @@ -96,6 +110,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index b1d84f1594ea08acc55762ed7ea6087041f4bc5d..8f6b8b9702f41fd1c4a559c890ed67a22afcf8ae 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -16,6 +16,8 @@ CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_ENV_ADDR=0x60100000 CONFIG_LTO=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8001ff00 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -29,6 +31,7 @@ CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 # CONFIG_CMD_BOOTZ is not set CONFIG_CMD_IMLS=y CONFIG_CRC32_VERIFY=y @@ -85,6 +88,7 @@ CONFIG_DAVINCI_SPI=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 0f5e135f1bfc0a02bdddb4e8ff87c90b97171285..95b41ef32b1480e2cdc8343152e41952a31595cb 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_LTO=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0000f20 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -30,7 +32,18 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0000000 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x8001ff00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0f70000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x110000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -39,6 +52,7 @@ CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CRC32_VERIFY=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_DM=y @@ -99,6 +113,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 03f938455edad3b5ecb5da0ab7cf5680fb106c31..64d788f663213114350843f94308a767d48c4848 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -14,7 +14,17 @@ CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2086 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 8ebc78111435caa29eb3cbe2edf81e746457dec8..c08203e030accb3773b0efd6d6ebfd52bb56c3d1 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -17,13 +17,23 @@ CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x1ffd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index be4ee7913513242618d3b1e06287e86c9f4227a8..fd2d5ee2ca95fe71c4f90069e079f2f8a21b73ae 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 @@ -24,7 +26,15 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x22fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=96 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 55ebb57c692e606a30e3f7072290ddf78144d7dd..7d039d664a107ec0e3d9ca1fc886425095bae259 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -18,12 +18,22 @@ CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x22fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 2c1d3b464d857de91a20dfc13d5e768761e5bb6f..49c616852b244cb9844d4cf9b8b336337a894860 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -17,13 +17,23 @@ CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x1bfd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y @@ -51,6 +61,7 @@ CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 58fcf96c76047f25504b0eb8493af37b5776acb0..995835a96b32fb2d21300d690e4f1a53b3a9b08e 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -12,11 +12,14 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BUILD_TARGET="u-boot.kwb" CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_MAXARGS=96 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y # CONFIG_CMD_FLASH is not set diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index 425fff6c70a63972af5896144deaeaee61e721a2..ae1179a116019eb86a5032e093d2c3490929a9b0 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -22,6 +22,8 @@ CONFIG_IDENT_STRING=" ##v01.06" CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y @@ -34,16 +36,30 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x13e000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x3000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2073 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 71e80e8048535f116e6f4077f6c918db39e7aa6d..eae073d76ea6d6e6a0c4aa13d8e4559b42872fed 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80008000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" @@ -23,11 +25,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="dhcp; tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; setenv bootargs ${bootargs} ${nfsargs} ${userargs}; bootm ${loadaddr} - ${dtbaddr}" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfff8 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_SOFTECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_CMD_IMLS=y CONFIG_CMD_GPIO=y @@ -35,6 +43,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y @@ -77,4 +86,7 @@ CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="lpc32xx-ohci" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 +CONFIG_USB_OHCI_LPC32XX=y CONFIG_OF_LIBFDT=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index be780949ec37c0f29487d510a60da79e1f45140a..ac3079447868b37303a6c6f384c45159379fcf57 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -2,25 +2,42 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="omap3-devkit8000" CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_DEVKIT8000=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_BOOTCOMMAND="run autoboot" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 +CONFIG_SPL_BSS_START_ADDR=0x80000500 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 +# CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x80000100 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x8 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=8 +CONFIG_SYS_MAXARGS=64 # CONFIG_CMD_IMI is not set CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x680000 -CONFIG_CMD_SPL_WRITE_SIZE=0x400 +CONFIG_CMD_SPL_NAND_OFS=0x280000 +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -38,14 +55,21 @@ CONFIG_JFFS2_PART_SIZE=0xF980000 CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)" +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=20 CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DM_I2C=y CONFIG_TWL4030_LED=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -58,7 +82,6 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_DM_ETH=y CONFIG_DRIVER_DM9000=y -CONFIG_CONS_INDEX=3 CONFIG_JFFS2_NAND=y -CONFIG_OF_LIBFDT=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 0dfb7bbe02579ea81b923c0c9c66ffb8f44a9cfb..35e2c1a326fe25dcfe00b9823d8d65c1b8f4f63f 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -27,6 +27,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -55,6 +56,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_NUVOTON_NCT6102D=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 558619fc31033db44b0f5abf334f720dde7127f8..051816f719fef65019dfe4605085a5e69f4518d8 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -35,8 +35,11 @@ CONFIG_SPL_FIT=y CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y CONFIG_CMD_DFU=y @@ -64,7 +67,9 @@ CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index e1067b66eec2117f0e3c83c04ca304b3625535fa..a3917eaf1794a0cc617ffc644b17b84fe936847b 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/display5_defconfig b/configs/display5_defconfig index fa271b24028af866b1b0936e63d2213249921248..f586596ee9215d85ae186257fb139780c1b6630d 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -37,18 +37,25 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="if run check_em_pad; then run recovery;else if test ${BOOT_FROM} = FACTORY; then run factory_nfs;else run boot_mmc;fi;fi" CONFIG_MISC_INIT_R=y CONFIG_SPL_BOOTCOUNT_LIMIT=y +CONFIG_SYS_SPL_MALLOC=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SAVEENV=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x100 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="display5 > " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2076 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set CONFIG_CMD_SPL=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 45b6b96449184bd2bf2e97ee25d30653804dc0bb..e2f35a9790c0ead4f687b97e7cb5a98a8bcb1460 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -34,12 +34,16 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="echo SDP Display5 recovery" CONFIG_MISC_INIT_R=y +CONFIG_SYS_SPL_MALLOC=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x100 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_USB_HOST=y @@ -47,6 +51,9 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="display5 factory > " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2084 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set CONFIG_CMD_SPL=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 96088a177a8d7389410329731e83eb5b81a116df..242cc36fcef069bf909bf6400ef39c23559fb97f 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -12,6 +12,8 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325" CONFIG_IDENT_STRING="\nD-Link DNS-325" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -21,12 +23,14 @@ CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -47,6 +51,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index a740da9fc0d890febf678d53b7a9bcf3f2566a46..6f99cdd44b05f5f31207aa9f2e8d864ddc8a889d 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar" CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -21,6 +23,8 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="DockStar> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1051 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_USB=y @@ -32,6 +36,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index e972d3b11704dfaafb8e936c1adba78aef2e5316..bd3ce11b79ff22b7850004fe5a59eefcaa7a6226 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -26,20 +28,28 @@ CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot request CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x7bc00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x200000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -120,6 +130,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 3c9293d8b08c81e4b2a91ad533045f6b47ebe125..63b8f2b6fe7741a00fae90b9c2bc0d6dc706d460 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -19,6 +19,8 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -29,8 +31,12 @@ CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot request CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x7a8b0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -41,6 +47,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -117,6 +124,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 5560a1ba184f96dfa722168b8f8cb9d65995a66b..cd4b8bbce0a98f7671bda4bec4dac33bc18d9e3c 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -31,8 +33,12 @@ CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot request CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0x74eb0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_RAM_SUPPORT=y @@ -41,6 +47,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -106,6 +113,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 264a51b07392dd416835bd3aa10d2a85b4f1a2bf..c137fc72e0f202bcc9df0f5fad545405983fb875 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -34,6 +36,10 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -46,6 +52,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -71,6 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index dc136f98612114cc9bc7eb8091cf9bad28d90114..2bf759d843752fa426aff33bba367235367c4807 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -10,6 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_REMAKE_ELF=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -19,6 +21,9 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="dragonboard410c => " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=548 # CONFIG_CMD_IMI is not set CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index 3bd22aa34f0b85ff6a526c48dbfcfef2b53c9733..2ede13fed1b6b46c9fabc62a414a6b15d41ef467 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -10,6 +10,8 @@ CONFIG_TARGET_DRAGONBOARD820C=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyMSM0,115200n8" # CONFIG_USE_BOOTCOMMAND is not set @@ -17,6 +19,9 @@ CONFIG_BOOTARGS="console=ttyMSM0,115200n8" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="dragonboard820c => " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=548 CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPIO=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 5f9073d2e62870224cf9ef847b32d1d9aac469b9..d6b55636ba5bf21e8695f5e65c792da33c9f97c4 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -14,6 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug" CONFIG_IDENT_STRING="\nMarvell-DreamPlug" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x100000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -21,6 +23,7 @@ CONFIG_BOOTCOMMAND="setenv ethact ethernet-controller@72000; ${x_bootcmd_etherne CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_SATA=y @@ -47,6 +50,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 07d5dce51be5b86917a13b6bafa36d84e10dab94..529d7569476ef822a22ea4019475d302cc86a8cb 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -18,12 +18,15 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x3D0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv ethact egiga0; ${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y @@ -45,6 +48,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 81a767cc0ea8212a3b92bb4d9a32bc0f579f544c..7af7bb4e980e1fab9753edf6660efb3de563d6f9 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -23,6 +23,8 @@ CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1" @@ -31,7 +33,15 @@ CONFIG_BOOTCOMMAND="sf probe; sf read ${loadaddr} 0xd0000 0x2d0000; sf read ${ra # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1bfd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 60910c3ce3542bd3a767631d69a267f6ea2aaa46..c737cdb4d99c7fb013f4abf851494ebfa5c85d38 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/durian_defconfig b/configs/durian_defconfig index 8ce80f9d903096ab512e3b91642c16e0fb3a44b6..27c8e260d92e50c0d98c6bd1244115a30f3a47b9 100644 --- a/configs/durian_defconfig +++ b/configs/durian_defconfig @@ -12,12 +12,17 @@ CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_SYS_PCI_64BIT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x87f00000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="durian#" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=280 +CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set CONFIG_CMD_PCI=y diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig index 51a440f29eb2abbf7e3c78153da9346b6117eaa7..d56a838763074c9c09298d0c47fb2d96dbddfdc8 100644 --- a/configs/ea-lpc3250devkitv2_defconfig +++ b/configs/ea-lpc3250devkitv2_defconfig @@ -11,6 +11,8 @@ CONFIG_TARGET_EA_LPC3250DEVKITV2=y CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250" CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20 CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=1048575 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -18,6 +20,8 @@ CONFIG_BOARD_SIZE_LIMIT=1048575 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="EA-LPC3250v2=> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=288 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_OF_CONTROL=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index dc649f213fae731a49ab59aa19133725e7f0a9ff..4cf03abc61e4a85822a9c836b4d2c69d22b789d7 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFF040000 CONFIG_TARGET_EB_CPU5282=y CONFIG_MCFTMR=y +CONFIG_SYS_BARGSIZE=1024 CONFIG_SYS_MONITOR_BASE=0xFF000400 CONFIG_BOOTDELAY=5 CONFIG_BOOT_RETRY=y @@ -16,8 +17,11 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="printenv" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="\nEB+CPU5282> " +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1054 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -41,6 +45,7 @@ CONFIG_LED_STATUS_BOOT=0 CONFIG_LED_STATUS_CMD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 2f2692340f2c2fb2741b1f94488b99191b785537..1178515846933c351084f7d0ccb7651a8ff2c0c5 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFF040000 CONFIG_TARGET_EB_CPU5282=y CONFIG_MCFTMR=y +CONFIG_SYS_BARGSIZE=1024 CONFIG_SYS_MONITOR_BASE=0xF0000418 CONFIG_BOOTDELAY=5 CONFIG_BOOT_RETRY=y @@ -16,7 +17,9 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="printenv" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_CBSIZE=1024 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -40,6 +43,7 @@ CONFIG_LED_STATUS_BOOT=0 CONFIG_LED_STATUS_CMD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index a9479e54a960123340841467940dcb61a0c23b42..dbca94525ed4e7a3834b5ff5fe75b86f34a2f520 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -14,6 +14,9 @@ CONFIG_SYS_MONITOR_BASE=0x01101000 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=128 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_CPU=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index 4987e0946592a354b9516163242cd77dacbf4e6b..6b7cdbe4b119991bf33c005125eec1e92a3cbf3b 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -1,12 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_ORION5X=y -CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_SPL_TEXT_BASE=0xffff0000 @@ -16,15 +16,28 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" EDMiniV2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0xFFF84000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf40 CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0xfff0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x1ffff CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x20000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x40000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1ffff CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="EDMiniV2> " +CONFIG_SYS_PBSIZE=1051 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y @@ -43,6 +56,7 @@ CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x4000 +CONFIG_LBA48=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index 7a723c136c2b2bbb7c0ecd339dc8136bf2429478..4ae74dbd2e389e44a47330796dbe3044e6b1150d 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTM is not set CONFIG_CMD_PART=y # CONFIG_CMD_NET is not set diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index 98f91d811642d9f0067a4ee9dcc05c575d0bc851..3f1e80120c6a563972d81efb0c421b2e7a6276d5 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTM is not set CONFIG_CMD_PART=y # CONFIG_CMD_NET is not set diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index ceadd8290d06289bb0bec003c1af8d05535eabc7..83f532d6e5438e7b21362efe62e3b69142b40e61 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y @@ -48,6 +49,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set # CONFIG_GZIP is not set CONFIG_EFI=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index b5d1cf12435294da302d6759d4a21e5f57c4e97f..28aaff69e97843633414716bcbe060d92f0d1758 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y @@ -48,6 +49,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set # CONFIG_GZIP is not set CONFIG_EFI=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 113b7c8cfe0623ccc8b1417eff891d08552963c1..263fe3b7c8d18dcf1eb09c2fad04916e4f91d709 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -8,11 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1" CONFIG_ROCKCHIP_RV1108=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_TARGET_ELGIN_RV1108=y -# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -53,6 +55,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_PRODUCT_NUM=0x110a diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index a3b43dffc63c6c0cac1a1f4bedea907584fce336..73121f2f4eb28148ef724d955d21bf613349f5cc 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -8,4 +8,7 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig index 17ca315a4ac0447a3166a1952b9c4f889eca0ffa..4c2cc3489256c312b6a0b68859898c2ad54ab990 100644 --- a/configs/emsdp_defconfig +++ b/configs/emsdp_defconfig @@ -9,10 +9,14 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="emsdp" CONFIG_SYS_CLK_FREQ=40000000 CONFIG_SYS_LOAD_ADDR=0x10000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10100000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="emsdp# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=280 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MMC=y diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index 533757ba5b489b2784e2fd397e1c0c8d4534e3ec..34e5b4e743f2043d355a5dcb5cdce4aaa252da85 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420" CONFIG_IDENT_STRING=" for ESPRESSO7420" CONFIG_SYS_LOAD_ADDR=0x43e00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2158000 # CONFIG_AUTOBOOT is not set CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y @@ -17,6 +19,8 @@ CONFIG_CONSOLE_MUX=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="ESPRESSO7420 # " +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 34b9fff5ded2e6f124144a73ab5b00660b1cd8eb..f0b10f0292392e142be0404eb90c50409b3722b0 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -35,6 +37,10 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -47,6 +53,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -72,6 +80,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x200000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 18faa1a7fb35af514cac69d7b45cae3d98e371e3..796b71793a7f090891a11e59414715f744ece4f9 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x27000000 CONFIG_SYS_MALLOC_LEN=0x121000 CONFIG_TARGET_ETHERNUT5=y CONFIG_AT91_EFLASH=y +CONFIG_EFLASH_PROTSECTORS=1 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x21000 CONFIG_ENV_OFFSET=0x3DE000 @@ -22,6 +23,8 @@ CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0xc6000 0x294000; bootm 0x2 CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y @@ -35,6 +38,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_RARP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y diff --git a/configs/ev-imx280-nano-x-mb_defconfig b/configs/ev-imx280-nano-x-mb_defconfig index 770f05f966d9667a298cb3a5e0154da63f70921a..20ac5ddb332ca55b9687b2c024cc51bf10f4c261 100644 --- a/configs/ev-imx280-nano-x-mb_defconfig +++ b/configs/ev-imx280-nano-x-mb_defconfig @@ -8,6 +8,8 @@ CONFIG_DM_GPIO=y CONFIG_EV_IMX280_NANO_X_MB=y CONFIG_IMX_MODULE_FUSE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 2371cc2742cf16b596f197e0e5769d75e23c99b3..e7d93ec48bf0fb05b7b4b7a61d400b4e45b8c0b2 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -18,6 +18,9 @@ CONFIG_PRE_CONSOLE_BUFFER=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -33,6 +36,7 @@ CONFIG_CLK=y CONFIG_ASPEED_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y CONFIG_PHY_REALTEK=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index f84b723bbba3687aba988d8559522ece9363e6ae..d07d3c41fef66108ada4085465bd3158f6357b4a 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_POSITION_INDEPENDENT=y CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_ARCH_ASPEED=y CONFIG_SYS_TEXT_BASE=0x80000000 @@ -10,6 +11,7 @@ CONFIG_TARGET_EVB_AST2600=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds" CONFIG_ENV_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" @@ -19,6 +21,8 @@ CONFIG_SPL_SIZE_LIMIT=0x10000 CONFIG_SPL=y # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -32,14 +36,29 @@ CONFIG_BOOTCOMMAND="run bootspi" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x83000000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_CRC32=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -47,6 +66,11 @@ CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_DOS_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -57,12 +81,10 @@ CONFIG_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_DM_HASH=y -CONFIG_HASH_ASPEED=y -CONFIG_ASPEED_ACRY=y CONFIG_ASPEED_GPIO=y CONFIG_DM_I2C=y -CONFIG_MISC=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y CONFIG_PHY_REALTEK=y @@ -83,4 +105,3 @@ CONFIG_WDT=y CONFIG_SHA384=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 36eaf4e6b954f7b2d2f465ca64672fa2d105f758..abd563270814fd1d8fdaf30b74d86f209cac722c 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -18,6 +18,8 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -28,12 +30,20 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_TPL_MAX_SIZE=0x20000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 1e2b0f03087cffaa575f213c80342371bab51ae8..fc46154dfda5ae358bb38226c7f0b5ac09bfbcc6 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -32,13 +34,21 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x20000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x188000 CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index dcc70cb0bc7f960b662e004d5cfc1fefffe1a980..7bc535e68cfb073f46b7c1963a3dcfff067a9a1d 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -17,12 +17,16 @@ CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK_R=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index d232d78d6e571fea64824d5d9621e15c3240fe59..6526933274a247b602911dcc8e9339a412c6f5ea 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -7,15 +7,18 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb" CONFIG_ROCKCHIP_RK3128=y -# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0x60800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_FIT=y CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -49,6 +52,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 8eda765fb373b797cd3656482b6d4aa32040450b..ebf13c31c5bfa9a6348c28ecc6c4834a051ee7c1 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -18,6 +18,8 @@ CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x61800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -26,10 +28,15 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_OPTEE_IMAGE=y +CONFIG_TPL_MAX_SIZE=0x100000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 14a1d4cf332233a38b679ad06864bfc9035acbe6..a2b88169c67d665fbb658d50f21df473a23a225a 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -15,6 +15,8 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,9 +26,14 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_OPTEE_IMAGE=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index b4ce8a1a3962a9b25798273631000e398c327e68..eb17b3d5e1f47ae7a28bde99b9515e8b6d240873 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -16,12 +16,21 @@ CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 7e0c4c50a617f83cea739ee32c742140d9a4cab5..c81437300c740d9c5f3cb9700bb1cdc362f3e927 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -25,12 +27,20 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -89,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index a9afb63fdd9b41ae2de595fd9340d77d4705c14c..e3b7137c8f1f065f06c52d2e85bace5328e6d76d 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index 1d61c151943622deed09e3ac58fcee8656b30af7..135f48ced0488e4ff43c62a5cdb77c49f6ff16be 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -18,13 +18,22 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index fcdef1d35492cf2c70a6e2ed21ae644186829af3..65b76c6b36d401d37477b8fdb8296378507bf88b 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -5,11 +5,13 @@ CONFIG_SYS_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" CONFIG_ROCKCHIP_RV1108=y -# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_BOOTCOMMAND="sf probe;sf read 0x62000000 0x140800 0x500000;dcache off;go 0x62000000" CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -47,6 +49,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_PRODUCT_NUM=0x110a diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 1ee3cb225bf15d1cc1869d6301307cce9aeec810..b2c530d338054d49b5b3f5012bc723cce8f06803 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,8 +13,17 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff8effff CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_CMD_BOOTZ=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 01858a65b4cc5d8b2291e5204dd9c5cec5dce640..e7e405fc5028cce642812f0cf3fbd889b5e8ddaa 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -19,6 +19,8 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -29,12 +31,20 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_TPL_MAX_SIZE=0x20000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index c0dbd8470a783d19330566dbcff6d852bada0c07..b3198bfa38081415d237cc09d76677643c00550d 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -15,13 +15,20 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 3803e42f380a0f671957533024825b28be724ab7..036769c066a2d3515cbe00e730b4c4d20f9139dd 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -12,10 +12,19 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 599eeb96b4f26f265f13cc923db75e917618d37f..7cdb6c56755b3ea3472004328fa427a7ab54c167 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -17,6 +17,8 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 58c8bb9040b9ceb6e8183d3d482a9aa94d3376b1..5ae13d5a1e2bb9ad5f9eca057c1795d906d59515 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -48,6 +49,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index dd61b834a92711132c09ea4ff5f974786594818e..eb7af8db36dae74296a8c3a5b814c87ef22a040a 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -18,11 +18,13 @@ CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003f00 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=0 @@ -32,12 +34,24 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0x7000 +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x308000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMINFO=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 314ab9fddfd0d953056198ed9e52ffa3eb7a0d6b..b9ee281be9f9ded952f6a4c989d0deff298e1fd1 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -36,9 +36,16 @@ CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_LICENSE=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index f2f0257071c293a8de46a47b7f8716551cb10958..a81aa00f2dba481b22816f8296713a41ee1e3b35 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -112,6 +112,7 @@ CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y CONFIG_CMD_IOLOOP=y CONFIG_SYS_MEMTEST_START=0x00001000 CONFIG_SYS_MEMTEST_END=0x07e00000 +CONFIG_SYS_BARGSIZE=1024 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -130,7 +131,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=1024 CONFIG_CMD_CPU=y +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_BINOP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index a1cf676f3f576e5333502d7d751da93f8490574b..c282990aa4584224fd4a15ee93b078f99583d067 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -37,12 +37,15 @@ CONFIG_LOG_MAX_LEVEL=8 CONFIG_LOG_DEFAULT_LEVEL=4 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -120,6 +123,7 @@ CONFIG_POWEROFF_GPIO=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 8cfe772f4ed63305c935a69607dd132c0f5b093b..c33287812663b2868adbb5662b3c32bf914a9c21 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -23,6 +23,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set @@ -72,6 +74,8 @@ CONFIG_CMD_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 8287600e0ba3011a6b5e4b5a476783f3b85233c1..2ef8b41c779407d4219aa5db2179039bd779a15b 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFF690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index 4fbf7ebdcd95632cacf891d64ecb129a97b0ca38..016282080bed47edf544096c86c3f56e793aba5e 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -22,6 +22,8 @@ CONFIG_IDENT_STRING=" ##v01.07" CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y @@ -34,16 +36,30 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x13e000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x3000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2073 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 3d5fd830ebea43499ce33250e4cf081c755ca18e..1ef4d6c881e2273468b71660740c167bced042b2 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet" CONFIG_IDENT_STRING="\nSeagate GoFlex Home" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -21,6 +23,8 @@ CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="GoFlexHome> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1053 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y @@ -47,6 +51,7 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index a81dacdcaba5ff8070155c1338fed31cdadc6103..350c4ec3f0ec9d1f5b3fa0eb39f5a1e22b8367bf 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index fb5b90f32b42d163b1be3f24b749a84ebd7db4a7..f706ee3dfbec477d54bcf00b75afd086babb1653 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -13,12 +13,16 @@ CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot" CONFIG_RZA1=y CONFIG_SYS_CLK_FREQ=66666666 CONFIG_SYS_LOAD_ADDR=0x20400000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 # CONFIG_CMD_ELF is not set CONFIG_CMD_GPIO=y CONFIG_CMD_USB=y diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index 1a5fe06bbe114490e47772b5f547addaa7362e22..c81f0f6c5eb9a06ee7b20970c3c3e60f9d493b6b 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index e353b64e5171e975a3c6aa27888a9add6df0a7b0..01546de8fda3f0871f5c84c2ec1ed24a332bc299 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -18,6 +18,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 89d78cfc175ce9fc786ae7e98c0338124c7dcba9..c5cbce52a9b77f43b8bf62235135791a942f6152 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -12,6 +12,8 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus" CONFIG_IDENT_STRING="\nMarvell-GuruPlug" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=917504 @@ -22,6 +24,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y @@ -51,6 +54,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 28a73fb304ba18aaad1de864c1d98ec0f57e7df5..0516176e6d070a68068b9c95834f4700a91ac405 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -41,16 +41,23 @@ CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x100 CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=539 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set @@ -90,6 +97,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -107,6 +115,7 @@ CONFIG_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 9deb080ca231deac589f5d4be1470d277fbf4430..63c87f17a5c6a1a14c81b909a38dd72e356e0946 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -41,16 +41,23 @@ CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x100 CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=539 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set @@ -90,6 +97,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -111,6 +119,7 @@ CONFIG_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 8ef794c21e45afece3634c9167ce7d62425d856a..9d6819f19d30b220a999e5dd244da898ef91a6c0 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -41,17 +41,25 @@ CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x1200000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x100 CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=539 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL_NAND_OFS=0x1100000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_UNZIP=y @@ -92,6 +100,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -116,6 +125,7 @@ CONFIG_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..4408c6ce370108b02d651574e365ac653bc2305f --- /dev/null +++ b/configs/gxp_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_GXP=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_GXP_VROM_64MB=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x60000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DEFAULT_DEVICE_TREE="hpe-bmc-dl360gen10" +CONFIG_ENV_OFFSET_REDUND=0x70000 +CONFIG_SYS_LOAD_ADDR=0x40100000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=5 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlyprintk console=ttyS2,115200 user_debug=31" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run spiboot" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="gxp# " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MISC=y +CONFIG_CMD_FAT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NETCONSOLE=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=3 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_POWER is not set +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_GXP_SPI=y +CONFIG_TIMER=y +CONFIG_GXP_TIMER=y +CONFIG_SHA512=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 29f965200e1aae95f785a13e723f9d8d7a3ee556..8af0b3c3332448b9c8f63950e96396ad52457841 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -11,6 +11,8 @@ CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 9763b21a34b411d731d765d8c98a9956fcac9dbf..647b4674891e059ca6c820b0ee35d715fdc18ee2 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -12,7 +12,17 @@ CONFIG_TARGET_HARMONY=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2085 # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 4dc9e3bc58dda4310ef484894377e1a07ed33178..4642eb1ccb2505f2a90308f5faed0b3fa9cc91f4 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -19,12 +19,22 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x22fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_TLV_EEPROM=y CONFIG_SPL_CMD_TLV_EEPROM=y # CONFIG_CMD_FLASH is not set @@ -41,6 +51,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_MIN_ENTRIES=128 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 746f127f0f4c81700ca7ef156ea62ea8408d65f2..4fc7356010223dc5744434d41f515b29c8b76126 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0xFFF88000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_AUTOBOOT_KEYED=y @@ -29,6 +31,7 @@ CONFIG_MISC_INIT_R=y # CONFIG_CMD_SETEXPR is not set CONFIG_ENV_IS_IN_NVRAM=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_BOOTCOUNT_LIMIT=y # CONFIG_MMC is not set CONFIG_CALXEDA_XGMAC=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 3e1077389c224ce33df1d70ffb35209894d5a05b..8bf14e09d47fd3d85b116d1710deefd7438992c3 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -20,7 +20,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig index 627daa1fb83b201add50f3b26494f830ea2b72c8..0e7f264a2e32d6a5ef2b952ddfcdfc7117846329 100644 --- a/configs/hikey960_defconfig +++ b/configs/hikey960_defconfig @@ -9,6 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960" CONFIG_IDENT_STRING="\nHikey960" CONFIG_SYS_LOAD_ADDR=0x80000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fff0 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw" @@ -17,6 +19,8 @@ CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=283 CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPT=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 6f33bba1eb6edcfba15225591071c47c8a0e1b50..84242e8784811b15b5295973f868da6a964a897c 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -9,6 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey" CONFIG_IDENT_STRING="hikey" CONFIG_SYS_LOAD_ADDR=0x80000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fff0 CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -17,6 +19,9 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index b043982e360808eb29bee41d7545b718f75e9560..8e673545a966e27def181c6a64f38639d07a882f 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=500000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_BOARD_EARLY_INIT_F=y @@ -19,6 +21,9 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="hsdk-4xd# " +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2075 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ENV_FLAGS=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -64,6 +69,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index ce8f72d69343598a3c119f82b66f378157855d59..3bd6f9314ccb8a773c5e169ed0f5171541a1bab3 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=500000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_BOARD_EARLY_INIT_F=y @@ -18,6 +20,9 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="hsdk# " +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2071 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ENV_FLAGS=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -63,6 +68,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index fcded41eac58df760b90dcdf144b0c93d407b7d5..2b5a58714102eb341e644ab5ec292ace35c17b5f 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -17,8 +17,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="HG556a # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=538 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -65,3 +69,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 257dd89af45b45b53205e94eb6a10d813338f8f3..29cea180201c6e2e2c86782f90b3e2f1b348ea50 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -7,7 +7,9 @@ CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 436e3a8c209f88d42347cfc7f4488f8cd7907f08..8b6936497fd568f7ef065c66432834fa2a3fceb9 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 6978f8b0aabd439a47d4b9e5ae8dbc5abe78801c..a05876a18f3f0e58e5c640c538dbc25cff192fed 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 2c8ecb51de05f7bc1372beec5c40b1611f144e6b..3a9f30877b03e7a984f18470e06e2b8a830a75ab 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,7 +13,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 9a90252dbd7a056aee9adce3b70b00990e9df1dd..664745c9f135b722376112841f761739bf31dc76 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -17,6 +17,8 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=5 diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 61c5649f0960eaf37bf9140febbd59425fac5d56..6ed3d68cd9c6bc8a5f61ddd486d4278701930e28 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -12,6 +12,8 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0" CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -20,6 +22,8 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1051 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y @@ -33,6 +37,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y @@ -49,6 +54,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index de766b226bb5c524d0e6673305ee19b0b7691046..afe5b28e66b97bbf7847a24e9a881caec43f989d 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -19,7 +19,9 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_UNZIP=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 193160f8087d782c255067bf90d63c0627c2cd62..7adf76d77799ddaface46d0ed6de677f815d2e2a 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect" CONFIG_IDENT_STRING=" Iomega iConnect" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -22,6 +24,8 @@ CONFIG_USE_PREBOOT=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="iConnect> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1051 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y @@ -33,6 +37,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 7415b1158c6ae8da61a1a80eb23b0bb686cdce64..74dfc6680420e882c15d601f1716c0fd30003a8c 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -119,6 +119,7 @@ CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_BARGSIZE=1024 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y @@ -140,6 +141,8 @@ CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_ENV_FLAGS=y CONFIG_CMD_I2C=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index f0d6ac56b6a80e149250f10cca9cb95ab25ec8bd..17c97ac27f7969c1fc3f7d895256c8bb85f85c66 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -9,13 +9,18 @@ CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_IGEP00X0=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -36,12 +41,18 @@ CONFIG_SPL_UBI_LOAD_KERNEL_ID=3 CONFIG_SPL_UBI_LOAD_ARGS_ID=4 CONFIG_SPL_ONENAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x84000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_ONENAND=y +CONFIG_USE_ONENAND_BOARD_INIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig index cc79f99330a5ceb0709f30c093be841c34188cac..51c7e500dc2ff897d472c09b8c6ecee3471f7876 100644 --- a/configs/imgtec_xilfpga_defconfig +++ b/configs/imgtec_xilfpga_defconfig @@ -10,6 +10,8 @@ CONFIG_MIPS_CACHE_SETUP=y CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x87fff000 CONFIG_TIMESTAMP=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,6 +19,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="MIPSfpga # " +CONFIG_SYS_PBSIZE=1052 # CONFIG_CMD_SAVEENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_DHCP=y diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 63d6101bb893996b448ef42a427d19400055885b..1537e8361f68f205cfcb27f252e59adaebfe4b94 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -32,9 +32,12 @@ CONFIG_BOOTCOMMAND="run ${bootpri} ; run ${bootsec}" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run prebootcmd" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x20000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y @@ -42,12 +45,16 @@ CONFIG_SPL_DMA=y CONFIG_SPL_MMC_TINY=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x44000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x40 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index 97c7db04e12927472ea0e636a7dfa4004c9c47d9..ad478c469bc1599f90ddaf02f668816c642be8b6 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -24,6 +24,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run prebootcmd" CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -32,8 +33,8 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y CONFIG_SPL_DMA=y CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 0d7f89301446030063ffb25004b28c9fd3d56bf7..71e3d39597d18fc5b35df63dc7692752be6f6698 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -24,11 +24,14 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index f869539c0cea4fff5fc2b8d2f55dfe5c94192ab7..067498d80e3279c856e63d4b57cd608bbd42fe18 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -17,9 +17,15 @@ CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x13000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y @@ -57,6 +63,7 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 4b75e5794e99bd35c51e822d67ddcc1b24db3af9..a2501ebc1a1e7212596674cd0400b7ff9dc599eb 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -34,6 +34,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run mmc_mmc_fit" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa # CONFIG_SPL_CRC32 is not set # CONFIG_SPL_CRYPTO is not set diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 67c5640cc1eb3ca9347cf92b8dca2d2be64039b3..bf5f620ad8829927f3d82f9652a2ad122c08c794 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -25,11 +25,14 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 560733e6b2135bec48ed36c0869e6a842a7e7052..1510d10dc5271c0cc5dd61cc417739add137158a 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -27,18 +27,26 @@ CONFIG_BOOTCOMMAND="run autoboot" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x500000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x800 CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="i.MX6 Logic # " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=543 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x1500000 CONFIG_CMD_SPL_WRITE_SIZE=0x00100000 diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 4f7cc6c6aadf45bd29254bd79ba78b1252fc37f9..bddc4ff98ef67eba9089c52be2ca72024caec966 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -33,12 +33,18 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl-mipi> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=546 CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 96f4603a260ef5d86aa355b1ae7946e6bf000528..f8194a002a19aaffb38f5789e709d609ffc21cad 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -36,12 +36,18 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 67c5640cc1eb3ca9347cf92b8dca2d2be64039b3..bf5f620ad8829927f3d82f9652a2ad122c08c794 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -25,11 +25,14 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 7a0f932936dc781af1da06c2192fdab5d2afea93..cb2b0df98b76de0b8bdc681b0db5318993edf0d8 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -30,12 +30,18 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl-rqs> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=545 CONFIG_CMD_SPL=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 4b606f6986712dfd1374cd4baeb2ec3a91a9822e..9e46b1137fc8472238fa975e958941a6c663ea1b 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -28,9 +28,12 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=538 CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index b3b13db5c4a1f35d410a4274a92732a6e6ef0fc1..ac56f204cdbd4b5b0f5902e158cf2aeaf4247296 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -25,11 +25,14 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=538 CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 4fff94b957e5b7620a8a11b076837f910ff21ab7..7dadf80cd5ac5ccaa6b7e8ef875459284dbea343 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -28,9 +28,12 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=541 CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 726a387acde615e584b0c73a73ee0e83034d9f9e..a5828ead1bd7903b8dff8501e0a1c30d802ee79a 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -25,11 +25,14 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run $modeboot" +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=541 CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig index c22c4d570d405e9c2e023c13735697a882902364..830e4029e504af411cf8d8c9be46085871d2c3ac 100644 --- a/configs/imx7_cm_defconfig +++ b/configs/imx7_cm_defconfig @@ -24,10 +24,16 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run boot${boot-mode}" CONFIG_DEFAULT_FDT_FILE="ask" # CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 8b3d1b3ef1a114acb8861061fc377d019a851794..2a209bcfe47174e5f3675a7e6d31591d526805af 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -23,13 +23,27 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y @@ -108,6 +122,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_ABX80X=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index b418e86248f91c66d29e595307939536029f1120..07084988139455e69614588be634ef9424b1031e 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -25,13 +25,27 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y @@ -111,6 +125,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_ABX80X=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 535ff6dcba5ef9378cc65be152d25fc18fb2caec..7040d782ef6410a4c02b0caed34fba829f2a8eae 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -23,11 +23,25 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set @@ -72,9 +86,7 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 101d5a00bc77800d3ddf64ea428f750151de5660..0488ec223f0d0e7c9c13a40dd6ee50b15db98473 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -23,11 +23,25 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set @@ -72,9 +86,7 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index a4164951de09878445a622e9b2b1b6fa3d8e7c92..ec672f8764e7f96f0be143d495a7b55d1cbc5ed2 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -34,13 +34,26 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="Verdin iMX8MM # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 9cd8ac972858602e7e591e31ca50e49f6adeaf3a..1a0672879e58b9277a915aeab0755751401c7e8f 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -25,7 +25,17 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;" CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -33,6 +43,10 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set @@ -110,9 +124,7 @@ CONFIG_SPL_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 99a1f8622003a103f361d76dae354036004e9848..30c1eac4476ce15e2455ce22a543fb1371e8103c 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -41,9 +41,19 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -54,10 +64,14 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ec3206bd640303e6363678040018d777635583bb..00af724bbaa734a60036147a70039eb6391841bd 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -23,13 +23,26 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 0165a4e5df08a5a0aecd44f658094ba89d37ca0b..49b36e0c8f4848ae9dd97cc976622b32773f4a43 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -31,12 +31,25 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CRC32_VERIFY=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 145f96d491d8d5f9eda54b27756fc63cdbf3544d..bd177887689c37d30111db8a40153a9fbb6af147 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -32,15 +32,29 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y @@ -114,7 +128,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 9052e68e967da1e4e8253bd72b6c278132e593be..738d308f45b36c847d1b2f56aca79b32855fea05 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -31,8 +31,18 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -40,7 +50,11 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y @@ -118,7 +132,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index f8c75a2b237ea9e322986c0d6e17df264ea91c3b..79995591f28dabd59a48485d900735b366ff84ba 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -26,8 +26,18 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_DMA=y @@ -37,6 +47,10 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2067 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 52661ec1689ddc533c6f8e253fe7c33947a57573..74d033eb40350121a161ed9616548e0a77b51d11 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -27,14 +27,28 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2067 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index bc1cfa4bbd5263c2d71478f53ad7be8353078843..e53e00845edb5f403bba6d2f7cdd1ec8fa7d3034 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -25,13 +25,27 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index e62e17cf3b8ca9c32e852b9782b3bdb41717b9e9..7c1e48dcccea2c299e8af573d7e9c6615be4eaef 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -26,17 +26,31 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 5ec82f2a9269061b74c69882b36c2d981e0d83dc..927b449e03f97cee4c24a9ebb8e071118535a6f7 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -27,14 +27,28 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2067 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -83,6 +97,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 63a654973710acb111710b5428d45fddd71860d8..935de023161a06cf883c9393ed6b8eef1392988e 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -32,12 +32,26 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CRC32_VERIFY=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 2764152a91908e697d1486081a1fb8df946f80a6..f3b69070698bfa8a3e54166242c350c0b4c31a57 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -45,8 +45,18 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x96fc00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -54,10 +64,14 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index c3ffed85998cdf50f7f93190bdb2a196f4f13fc4..dcee933a1be024ae83b6e911c05b4eb7892cabca 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -28,15 +28,29 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 323a7eacdcab9679a3b1db700df7c94b726176e8..9f067fc6336eafd03c2f7aa0b8704148f751100c 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -34,15 +34,29 @@ CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 3feb6396d5f6587d6fd0bf36a4377fdce93fa3e7..2271f2a14e5ecc8fad1e1e7eff012b9b4c5c0ba2 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -34,15 +34,29 @@ CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 6758cd251e6003bd18d1bfc6d45f7eb6113f079e..7fdde41b6da58e9219733fb7b3949c8e11aa5e51 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -32,12 +32,26 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CRC32_VERIFY=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 8e024604378eac7db85fbfe7a0e11ecd1c5b216e..6f59f29dac07b769ade3fb1da0875ea645672cea 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -27,11 +27,24 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 9f54a280d9b0fe9ca24ac7a885b23d31b6c8ad86..4747bff6274ba47f7e227c698dcb8004d26cc27d 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -29,13 +29,25 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 1cf58937fe52afdd5740359a0fb0d149c298337c..1187dcf51ce25d9edcc0709fe022729d6eafc56d 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -30,13 +30,25 @@ CONFIG_SD_BOOT=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x2b000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 2e42872f843d75c20d0c805ccc9dec035bd0eff3..89e289a3b9e7521abfe2020d22f97b7d85cce98e 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL=y CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y @@ -28,13 +30,25 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x13e000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x3000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index d9997cfa82809f6ca3459fdf5ad4919f482b4b6c..5e32568ef198890e333bdf3a9dc32d9760ea5139 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y @@ -25,10 +27,16 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 43f42f7a58affc630ecae5b8a47d134f66d61062..f250425e26a68f7974cba322b3b3c1e2a0fceeda 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL=y CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y @@ -28,14 +30,28 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x13e000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x120000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x3000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index f47c8016611354adb12a7a3d45220851636c8866..d885206a472ac8e26e324fb464ec2df8792716a1 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -27,11 +27,24 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x22048000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x22050000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x22040000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x8000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index 3c490bf6b23ef5f995c8a2bd81b2abfb73e785f0..6cf12d5ef4599caa2318a6192c10faf183304c3f 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -18,15 +18,20 @@ CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x20209000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20240000 CONFIG_SD_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 # CONFIG_SPL_CRC32 is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 7193e93755221d2265b75e0b86a5c9f263b998f7..9e756386e9b1ebf6bdb937f086c2dcfdd76feb4d 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -20,16 +20,21 @@ CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x20209000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20280000 CONFIG_SD_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 # CONFIG_SPL_CRC32 is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index f81120b119755427b462d02a134f853e314e2cba..dae6b23a936e91f9823474699ba0813b9a084057 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 3ade9fea824659db4bc45fbe43c77c03b309365c..0382a4a054113220d96b8468080b89e77f574782 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index d5d2dc32c9356882be65c779675c85412cd282be..f3e374c2e345ce3c5fffa3c65684c02fce3ee893 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,7 +13,9 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index bd6c45bd661adff7bfb2a2d88109fb02c5ece10a..c392fc2bb8713f0debdbfe925233e4fe90584aaf 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 4485f9302364e1e303156a708297d49fdbb71084..81a1c9940fd830c2ae58fe541c363f2d827c6aa7 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,7 +13,9 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 1769256b7d1ed8c27726049f16585f8a9b43fcd1..a4a828c70a3a2949ad0333f0afe0917bf3f5b83b 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -15,6 +15,8 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 2b41fc1ba1961fbd6ff0193e07f9a589fca743db..7b1e8dee16df486df5db4e471e036bb847c7e01a 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -14,6 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2" CONFIG_IDENT_STRING=" IS v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -27,6 +29,8 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1046 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y @@ -34,6 +38,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -50,6 +55,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index c33ef94d2c98728f9f23f9c63e4369d77b74f039..5f4ec5ff8f0e3f7af2b46743421032a4bb3bd308 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -7,6 +7,8 @@ CONFIG_CM720T=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_LOAD_ADDR=0x7fc0 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" CONFIG_USE_BOOTCOMMAND=y @@ -17,6 +19,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-AP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index a3e6b8d8e8e553d9791f6cc2553e2701e33eb81f..fb86b7cf2996e27787cdb7575e854dbe7e655532 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -7,6 +7,8 @@ CONFIG_CM920T=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_LOAD_ADDR=0x7fc0 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" CONFIG_USE_BOOTCOMMAND=y @@ -17,6 +19,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-AP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index af0d73b4f874400981cd4b0fc53dfbf507c5f65f..6bf08cd13aefd3a3a52883efb3a19822e8ae3c03 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -7,6 +7,8 @@ CONFIG_CM926EJ_S=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_LOAD_ADDR=0x7fc0 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" CONFIG_USE_BOOTCOMMAND=y @@ -17,6 +19,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-AP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 52846913b69d87f3da2204bab79e46fdfd067ffc..97c44f3695544d01306c48f0b5daf56ea0c0b9c2 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -7,6 +7,8 @@ CONFIG_CM946ES=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_SYS_LOAD_ADDR=0x7fc0 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" CONFIG_USE_BOOTCOMMAND=y @@ -17,6 +19,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-AP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index 8bafa694db445677b8ac214b64c746273668a484..89cfa9b9a6f7e5493afc03cba819eb9ce55baf40 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" @@ -21,6 +23,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-CP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 59bee63e6138629eabbb8a9f8975ebc888ead45c..d895ba4629204d538ef0493466da619a36371aeb 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" @@ -21,6 +23,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-CP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index e4c91956651fcc6511a2d28935817b8d9cf8adae..9cf449cb4c8186254e32784bfcc5a10fc5af37a7 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" @@ -21,6 +23,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-CP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index d228c8ad554a57192c1566ccfafda52db58aa1d1..bcbcde2112858baef25499616ba0a005c1cf82b2 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" @@ -21,6 +23,8 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Integrator-CP # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=289 CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 175ec70915d18e32c84a60ab04db44dfaabeb3b4..b50b5d0938208fe21ae5715007db640e65b8825d 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -22,6 +22,8 @@ CONFIG_ENV_OFFSET_REDUND=0x6a0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80100000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -31,9 +33,15 @@ CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_SPL_SHOW_BOOT_PROGRESS=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DM_MAILBOX=y @@ -45,6 +53,8 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SYS_PROMPT="IOT2050> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig index b22050daa371d24c893e6cf50c833405b8507fe3..0894562140031fc656762e4e9e6c403c7da4912a 100644 --- a/configs/iot_devkit_defconfig +++ b/configs/iot_devkit_defconfig @@ -12,8 +12,12 @@ CONFIG_DEFAULT_DEVICE_TREE="iot_devkit" CONFIG_SYS_CLK_FREQ=16000000 CONFIG_SYS_LOAD_ADDR=0x30000000 CONFIG_LOCALVERSION="-iotdk-1.0" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80008000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_PROMPT="IoTDK# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=280 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 3eba698447601031ab397839fcd34e94d3e3db59..828425960458d6cc4b673122c5587dd248ff24fb 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 @@ -32,13 +34,20 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" CONFIG_LOGLEVEL=7 +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y @@ -55,6 +64,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 0f4b006b80b5dfd6e8ef1c8e3434429d604dfee1..9ac6ef1678629105ee52308b06aed0bd09e0b61e 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 @@ -28,9 +30,17 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc +CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -55,6 +65,8 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 931abf5e5976c418ec9ba2c029d34da8956e838a..1b57b5e316674ce3ec7737a3c7890518719ec85c 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -23,22 +23,34 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" CONFIG_LOGLEVEL=7 +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y @@ -50,6 +62,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -90,6 +103,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 6553212de85b03c5bd46a746b5b0f5038b065a39..5e25ed620fa97803edfdab785773e55351fec81a 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -21,16 +21,27 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc +CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -39,7 +50,9 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y @@ -53,6 +66,8 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y @@ -61,6 +76,7 @@ CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y @@ -73,6 +89,8 @@ CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y @@ -101,6 +119,13 @@ CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index 7c826e8d31f637527f629f849b2e84deeb914965..a1c8a374aea5ebc8174703dfb83f2e28e0d255ac 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -10,6 +11,7 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_A72_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 @@ -24,19 +26,31 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" CONFIG_LOGLEVEL=7 +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y # CONFIG_SPL_SPI_FLASH_TINY is not set @@ -44,6 +58,7 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -80,6 +95,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index 11b6e1e5606b736c7355515d24ebe073d8e645fb..add8da02056c7cfdc88add138100d4ebcff638c7 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -23,14 +23,24 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc +CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y @@ -48,6 +58,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 0023f73d9e8f990b3219787c381bbaa03cff7b59..14dfb6946f6995d93139c16a539a41c5c0948246 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 @@ -32,13 +34,20 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" CONFIG_LOGLEVEL=7 +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y @@ -56,6 +65,7 @@ CONFIG_SPL_THERMAL=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 4147b4e26c7b0eed11de11e1c88c6f167d627ca8..98d69a18b95f93d5bf28fe656a96970c74ff52cb 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 @@ -32,11 +34,19 @@ CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41c76000 +CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 @@ -62,6 +72,8 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 0ff666b2ee5c0e5b3e54d0d7ebd08297073414ee..5fce5836c9c5b5b5a80c79316bef11d7629c240a 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -8,7 +8,9 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig index 63c5329398f1bdeffd201ad56a893cef6b8f9f71..342e7e0d79fbc73fd9028025ada09db3e448fed9 100644 --- a/configs/jethub_j100_defconfig +++ b/configs/jethub_j100_defconfig @@ -13,10 +13,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" jethubj100" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_EEPROM=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index 8746ed9c80fdcc844dd2e2c30b87060d7ce84df6..1a6a697c1bacb5e2f68da6f2a51c325baac69136 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -13,11 +13,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" jethubj80" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_EEPROM=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 425b123ba1d0e3854d26f8820f1586f87e5bbce9..515fa23b249cec723535d6f5db5eebda309f38cd 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -10,11 +10,22 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_JETSON_TK1=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2089 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 17b83d3b34354ea4663377f0276a11c44e997a34..58c8c13b15a4243c8aad31ef1fb416659af1d08c 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -22,11 +22,21 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0xfff8 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc10fff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xc1223f4 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x8000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -35,6 +45,8 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SPL_TARGET="u-boot-spi.gph" +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index a4efc4f85cc3a8ba8f24977b187e986981e47954..1845bec5178b2fd15eb2f4c455042e83dedc5743 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -15,11 +15,14 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index db21695da52142f400ef69380cca77a8b1c8f639..b96d1fc7c1a2bf0c7295f3115cb5b66e6bfb665e 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -21,11 +21,21 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_mon_${boot} run_mon; run set_name_pmmc get_pmmc_${boot} run_pmmc; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0xfff8 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0afff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xc0c23f4 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x8000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -33,6 +43,8 @@ CONFIG_SPL_NAND_BASE=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SPL_TARGET="u-boot-spi.gph" +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index f74af6de3ff84d937b853e4c43c95db7ed69c457..ef92bef10c7a8a5ae8dcce5cc4b4991da57d1653 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -14,11 +14,14 @@ CONFIG_TARGET_K2G_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 754fed7c3ccae1b7c2c38804adf96ca064eea639..cfe5978e550b56177281f43ca7a6da3eef43ff2a 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -22,11 +22,21 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc1fff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0xfff8 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc20fff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xc2223f4 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x8000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -35,6 +45,8 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SPL_TARGET="u-boot-spi.gph" +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 8f659cdfc8257ec445a63c081523a6bfb6ca500d..5caf3db2fe51019b8b4dcfaab76059d532873381 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -15,11 +15,14 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc1fff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 4f13da8da4e57e883763a0edb658952f27b1da86..47d5bd14ac561eed30d99e673c2170d028ca1835 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -22,11 +22,21 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0xfff8 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc10fff8 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xc1223f4 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x8000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -35,6 +45,8 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SPL_TARGET="u-boot-spi.gph" +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index d863e40fd1a1f956238557c39ec698220963db53..5c44ca922c4d0a3a85edcf3fd6535c63644e5dd5 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -14,6 +14,8 @@ CONFIG_TARGET_K2L_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10 CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y @@ -21,6 +23,7 @@ CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index cddf5228b6086d317621b3c8b04d156300ade4b2..9a0171e4a8a4e15a5643d3192b22fb4b4f19aca2 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -12,13 +12,23 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " +CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -55,6 +65,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index bd52c015fa4da48c4392e4239d0147a339770d27..27f119931fb40f377537a5c7a93e2de8f86f973d 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -12,13 +12,23 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " +CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -54,6 +64,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 21bf9487a86372b4d1fcf1459fd009be465332e9..de2b625120aa1398bb60dc2bbaed9d61757d33f0 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -12,13 +12,23 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " +CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -55,6 +65,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 8345e47bddbc50ffb50fc9c04b58ce45284b62c0..bee5abe4cdbb4cbc93ef1f15109e44e3a260c89d 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -11,11 +11,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index df97c519fecfb05b038f52b4df1afc3bac365068..d025e444bddf99b33a6b5e5772dab9cbb5499215 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -13,12 +13,15 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index 299150cf207126029e748d9c1a8522c8c8a99163..825f687fdd8b445c6bfc051d4c21d79736d10510 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -13,11 +13,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_AVB_VERIFY=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index 75ccfba2aeaf9b7dda54fc6f12e8afb486c801e8..68ab1546bf0ee9f8f5f639257f47d2ff2b250bb1 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 615f2d9b6c07bf38a8e6c9bada2cee478d92d5cc..fc766ee476c229a17d10c69a91338a1c2b5045c4 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -13,12 +13,15 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3l" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_AVB_VERIFY=y CONFIG_ANDROID_AB=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index ad4eb281f159d9b14f87f9244c56c3762fc237b2..372aa7d91cf6e13fdc5fdba985a87d1bc75b0108 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -13,11 +13,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3l" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_AVB_VERIFY=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index 2e1eabca6524028ee4f2babfbc0d543998bdd8cc..df7e01d1f983570f18dd955ff1334a2417f2fb03 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3l" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index e450d27244aae4247de71f602d933b7862d5d27e..9444fe8258d4db71b3ca7682cae8653afd2d14db 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -11,11 +11,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index ce872c14908c1c890082a974851bf1cf92efad5a..054038fdd043021d91f4216201e5da2a1fff2be2 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_TARGET_KM_KIRKWOOD=y +# CONFIG_KIRKWOOD_PCIE_INIT is not set CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" @@ -15,6 +16,8 @@ CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_KM_KIRKWOOD_128M16=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " @@ -22,10 +25,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index 26be327e226f514075949d95c1f5081a6b3c191d..ac2deeb27c20faa4b8c3af63d059d707934a6bf4 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_TARGET_KM_KIRKWOOD=y +# CONFIG_KIRKWOOD_PCIE_INIT is not set CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" @@ -15,6 +16,8 @@ CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_KM_KIRKWOOD=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " @@ -22,10 +25,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index 493b16d4cda79266c14d1ab94e3682422451213b..80746791fe3a366201b8d2291171e3699555c9fe 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -16,6 +16,8 @@ CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_KM_FPGA_CONFIG=y CONFIG_KM_KIRKWOOD_PCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " @@ -23,10 +25,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index e90c23879010f6233769c4116a490691bda00fb9..a0c92441cea018834b2c282f74c878a0a7a576df 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -10,6 +10,12 @@ CONFIG_ENV_ADDR=0xebf20000 CONFIG_MPC85xx=y CONFIG_TARGET_KMCENT2=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_PCIE1=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_IVM_BUS=2 CONFIG_MP=y @@ -23,6 +29,9 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -49,6 +58,7 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="fm1-mac5" CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 00c98483b303c46c155eae088e2fc3cfe9f77263..34ab31565ca43f9a48dbf176eef7ea5287ca76a8 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -168,6 +168,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -197,6 +201,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 1cb21c243b52647af3c38aebc080a83fbea325bd..5766f49d774acd4a1e16ad0a3bdd1f79375b782a 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_256M8_1.cfg" CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_TARGET_KM_KIRKWOOD=y +# CONFIG_KIRKWOOD_PCIE_INIT is not set CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -18,6 +19,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_KM_ENV_IS_IN_SPI_NOR=y CONFIG_KM_PIGGY4_88E6352=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " @@ -25,10 +28,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index ae29991c492d7a8e8f06c4a270ca1b6d252e6eee..98f23dbbf17512ce23cca1e06cf8c27a7b3647a7 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -138,6 +138,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -166,6 +170,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index b3855915b86d1559365af31bcc949a75690bc538..a309acae7dc379460f8f937afe63c4c1a42cc96a 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -19,6 +19,8 @@ CONFIG_KM_FPGA_CONFIG=y CONFIG_KM_ENV_IS_IN_SPI_NOR=y CONFIG_KM_PIGGY4_88E6352=y CONFIG_KM_NUSA=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " @@ -26,10 +28,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 45bc3eb3b4d57913b911d358bb55d442e9c5b802..6a6f20890a76e79b16b557dafa3f07be54b6fba7 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -151,6 +151,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 08d217986d74b296dcfca5ba538c59b768b3308c..d251eba0d04b24c7947b352f6c21c2fd6d14a7c7 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -131,6 +131,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -157,6 +161,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig index 25ae6a4b2ca6567af479435cd566cb1a781a05f9..de44deb1ad1c0a09ee49bcb07279b0881cc30873 100644 --- a/configs/kmsuse2_defconfig +++ b/configs/kmsuse2_defconfig @@ -20,6 +20,8 @@ CONFIG_KM_FPGA_FORCE_CONFIG=y CONFIG_KM_FPGA_NO_RESET=y CONFIG_KM_ENV_IS_IN_SPI_NOR=y CONFIG_KM_SUSE2=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " @@ -27,10 +29,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index a752672ead196821015bbdc7c22846c698146941..7c0ebefa69826c34687dcf81479064d6a3f8561b 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -130,6 +130,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -158,6 +162,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index a0cca5b9f280e1d5a356b1f2a80dcc526339ecbc..5bb3d9c1160ac8dcc384846d2675bc96efe2907a 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -151,6 +151,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index c3a88f692672daa5873dbbd239b2ef19acf2a2c1..467b44c3e6b018f9c939be54bfe97073b4f8d3d4 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 11e4e956c8e77aee939743e2199643ddb3bfd9d0..f9cebf9e9c96befa695d654f86cb8263c761f631 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -28,9 +28,12 @@ CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -89,6 +92,7 @@ CONFIG_FSL_QSPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index f453ace625549e5ca5eb063dcec6836bf8f6ba5e..344f627bf5f7dc5001b91e52da6a70a1e0fc51f5 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -27,7 +27,17 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOARD_TYPES=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x91fff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 # CONFIG_SPL_FIT_IMAGE_TINY is not set @@ -36,6 +46,8 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_ATF=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_LZMADEC is not set CONFIG_CMD_CLK=y @@ -103,7 +115,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y -CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 07a07bd53f979a1ac81bbe77e127e937c9854060..49671e8fb47f0303b5d46a9e441eaeae5e34ea59 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -30,12 +30,25 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index dc8c28f8cca89bd3b132aa8774de070fa14015cc..aaca8966c8f9df54870be5f6af1601cdf546d2c3 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -25,6 +25,8 @@ CONFIG_ARMV8_PSCI_RELOCATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0 CONFIG_MP=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y @@ -35,10 +37,20 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 3ec33477208782e7df93e866d8d802db55968e54..6f60aa96f12e11f61d9a20993a19fd50e26a6289 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -22,6 +22,7 @@ CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 9c9aac369d6bac58b4237e43e7ca5bf2208092b6..8c5010d6052378b547a3b05ad74bf09b01f4caf0 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -27,8 +27,11 @@ CONFIG_AUTOBOOT_STOP_STR="." # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_ELF is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 0111f30e14d7c1c056b58200a1bffaef8d999e0c..4f17de826c84d0d1ac4a723f36f531c6f500ce11 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -19,12 +19,16 @@ CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK_R=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig index 45881b5dd1c1741fa332b490f9730cdc94da34a4..9a944cad39c26b6f6d36a4a201830fca861ff96b 100644 --- a/configs/kzm9g_defconfig +++ b/configs/kzm9g_defconfig @@ -18,6 +18,8 @@ CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200" # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="KZM-A9-GT# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y @@ -34,6 +36,7 @@ CONFIG_SYS_I2C_SH=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_CFI=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x10000000 diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 503c7e05dfbe5bf9a112501b854b6edc56ce82bc..c9ec38d711ffcf4ccb971801e8ead9b4f65da6b1 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 2fa8d563ebe2db8288892453bdf92565b05bd45a..1e708ed3f90670f8981ce515954397b7a0e898f6 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -12,8 +12,17 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 1d35e75a1bac04ef84d9cf75491bfe1c54bc4413..36e3d70692385504926153dd08c2949f56a3ce78 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -9,6 +9,8 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3" CONFIG_SYS_LOAD_ADDR=0xc0700000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80010000 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y @@ -44,7 +46,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_NET is not set CONFIG_DM=y # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index 1e51b7a6537900de005c6b1a5cf20a39c2659331..cce1b36758e756c8bb15468119f7a1c55f955d52 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -14,12 +14,15 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-ac" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 5506f386f2ee09be8f2abed763a464e555ea3e3b..d1e925039e695e85fdcb539cf785678ef9d5f565 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index a3fb6bbbda29c3fb06f0bfddc8cc2672855493b7..ba27e65d9aab0cb704f16a7ab2a2153e661f01ed 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -13,12 +13,15 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc-v2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index 8ee69ca5ec818f962e7e16d53e7e2ffcf8934446..99a099d0a52ef3869932c18f2495a1af499eeb43 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -14,11 +14,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-s905d-pc" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index 224a3fb02fc207641e856442164be343acef25d9..e65db0778c2b5c7b64857cf8a2f4c1d3e0741db8 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -13,11 +13,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-s912-pc" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index 8725fe64cdcfd028a158fb3ef75171ff220fe562..ca995568024dc5a0fb2522cb836ae21b208e6ba6 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -6,6 +6,8 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 5275fdc36da3673cf05d5992b355796941291213..7ca312c8fbcdeb6d1e4fcacb120903fd3d78ed69 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -6,6 +6,8 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 96274019499a5cb1508d45751718e3a09d5cc763..13ff7582124446955972b794a52e58b1e5226e98 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -6,6 +6,9 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index cb7ffb4d7daa5d329aa78982cdb370c95b78ca60..75280ee1e3b2ecfa09cadc7e89c67506e01f2d79 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index c3aa4b10617f445da3a8f61d68041625d01d69cd..f42747e9466c0646a8c0a972fa76bd7031054461 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 9fd1dcc9958fa5bf18ad2343d7e352f917e5ad3d..0252763c77624971daf6016b9c1c0a17a2851a3e 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -10,3 +10,6 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 +# CONFIG_SYSRESET is not set diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 52e5524726fa2bdba245fb12d47cde5d4e2dd5bc..a129679e9d45a4014a8ea492265892bc79ace9d9 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -28,9 +28,16 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_LICENSE=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 426913816bf37ac38cd54bb5191fcd8e0d7a2196..294ff4238fcb9dd91b68c4ad99d6d864ba27fad5 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -19,6 +19,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -30,14 +32,22 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-lion-haikou.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x20000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x188000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y CONFIG_TPL=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index bf700dffb7f12ea22c0276cf3d7451ca576a9c23..24e71bb48d88108fa177db947245cbfc023a04b6 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -24,8 +24,11 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index cb9ad24b1226d34b4c0305bff6212a97e87dec79..da72b39a494df722e4c7d8843d3424e6bef3c86c 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -12,9 +12,12 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -26,6 +29,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 8763e0d7b04a0db6a3c9953c9d3cf956d1e993cd..8219d70e42040bda89668729c449b832fa322536 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -14,6 +14,7 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -26,6 +27,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index fa3486cfbb791a7d5338bb537843ff00bd0db29f..c679b2b9836b7cf10cabe715a35067a32c5ebbac 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -11,9 +11,12 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -25,6 +28,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd;run qspi_bootcmd" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index a56a27bfc2910d5f91f48b768ff1fc91f7bf9638..b580a59df4244977964d9dcc51559655c136d90c 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -25,6 +26,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index e25d964124c42de698b7f67fe7f8a91910de6bc4..1f12a3b95ac0100c8d9890c093f4ca7709704044 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -5,14 +5,18 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_FSL_LS_PPA=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -24,6 +28,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -43,6 +49,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index e0ae291872ca84fdffd23e1cb530380d517721e6..dfa525f31d9cf94ab7c23d2b30e1aa96a4ab2b45 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -12,9 +12,13 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_FSL_LS_PPA=y CONFIG_ENV_ADDR=0x401D0000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -26,6 +30,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 56ddeaaf4d631fee6829a4ea3235a942cc975b82..50855d545628550101d2b58b8469f6397860dfaa 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -6,12 +6,14 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -24,6 +26,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -43,6 +47,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 4d718cd44ea43be66c106ebcbd57b8eba1231ff9..2bdebe2da49ccfce403d6709b4dca89871d36e12 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -25,6 +27,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index eedb895c6b36cf84fb5f9407cb44be192e5bf609..0f6c2ac37dce40f888176823c20193fd5a4d96a6 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -9,13 +9,17 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -29,6 +33,8 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index fa847f3844fff398911c84a5d702a3a98bb57044..fcc7914b56563ff9da83c9fa0417c1f7f5006c40 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -6,13 +6,15 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_QIXIS=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -28,6 +30,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -50,6 +54,7 @@ CONFIG_DM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 295d27173ea266d91820797fbc7a47e10e1b1ad5..98e48f2fbaa23771362882c4c4a71c7fd9b4d83e 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -10,11 +10,13 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_QIXIS=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -30,6 +32,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index eccaf131604a4019f5f7f9c52d697fe2bde88456..6147d4b0bcee6f93589a745d362ac081b782580c 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -5,15 +5,19 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -25,6 +29,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -46,6 +52,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index d9293d3e243486821c789769d0416ced587e7a0f..f9b0e6edacd9f4821775fefb196031661fdcd42f 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -13,9 +13,13 @@ CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_ENV_ADDR=0x40300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -27,6 +31,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 8397c49989678d996a49f4af7dae53d09cbc01bc..a603bd9acc5be31f34a1ce6878dc4902986f4b7e 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -6,13 +6,15 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -26,6 +28,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -46,6 +50,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 82ccb856c3ad5fa0111ee176d306cf842b5d2c54..5a86992f0999f03cdcedcab818022c3ed2efcac9 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -14,6 +14,8 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -26,6 +28,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 0e869a2295ec8b2bc131d96f65365025c1c7a13d..d731936d5299b8bc7be2e3207411d61b625e01b0 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -12,9 +12,12 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" -# CONFIG_DEEP_SLEEP is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_QSPI_BOOT=y @@ -22,6 +25,8 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 030480bdbf8da56a9e39a78a666c8ddfd946b803..c71ab78186940500c1d4659741a25c3b6339d9cb 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -14,12 +14,15 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -# CONFIG_DEEP_SLEEP is not set CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_RAMBOOT_PBL=y @@ -31,13 +34,25 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82080000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 70501cb3f0979a72211e3e45a3e440e8e4c62d06..92fa4f000ed3f442301d6eaaadbd353e925d5df8 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -32,7 +35,10 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 1948abc74ac344ff26544ffacb70951551307c9c..fcbaf9b685e02904dacb5ac69575f99cfa2cd07a 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -32,7 +35,10 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 7bb420513786e27ffe1eaa1d6e3312719e816b1f..19a21f4a04757d6076f0c0dd05a39929ac9f6aa5 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -16,14 +16,17 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -41,7 +44,17 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y @@ -50,7 +63,10 @@ CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -83,6 +99,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 6b6cf1fcddeaf1eed9531cce2a0502ea77defc5e..727475f622645323585c4755b77f3ef9cf571560 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -6,17 +6,20 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff # CONFIG_SYS_MALLOC_F is not set @@ -31,7 +34,10 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -60,6 +66,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y @@ -93,4 +100,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index d5b85db931a59813ee9bb028df5d2677da1a682e..82c6a1bdc3bc28d691ffde1869eea930dc452653 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -32,7 +35,10 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -63,6 +69,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 6f18270c7efa32f1e81f82c4f4be2a2b89acdb2e..438a8ecf0ae64565f3c61473edf50f813dfea8fe 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -32,7 +35,10 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -63,6 +69,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index d677ff72288d70455a861fab0b980b8ae2475024..750a5a501e5f2908ca38e01ff6d3a9bea89974b4 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -13,10 +13,13 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -31,7 +34,10 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -60,6 +66,7 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 61809aae70e6310db5b4e919c3269898dd5d73bf..cbb7c55944f946cdce62be4f19b429341823d740 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -16,15 +16,18 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -40,7 +43,17 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x820c0000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y @@ -48,7 +61,10 @@ CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -81,6 +97,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 66f930aa61de489f11a8ee4c4850d7a115ed0f07..71eff4582f93a7d670b8238310daafc183746427 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -16,14 +16,17 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -39,7 +42,17 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x820c0000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y @@ -47,7 +60,10 @@ CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -77,6 +93,7 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 0b42b195f9a3519468d224c01228ae4e8f207322..4ee30728663e62e6769ce628d12a45f1f3bce290 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -14,6 +14,9 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -24,6 +27,9 @@ CONFIG_SILENT_CONSOLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index e6fdec2974c06172bdb9219f99430b507170e20e..aad997833111c5d975e230107b199ba181b87314 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -33,13 +36,26 @@ CONFIG_SILENT_CONSOLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82100000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 628e1d475e5a6dd9bfee0ab7e24a7b444287b9a2..b86a60fd32643dfe3041f037c236b806d6e4cf31 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -14,6 +13,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -30,6 +33,9 @@ CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -77,4 +83,3 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index c4df3338d7d5e5e0bab169d5c699a6ed59634e82..0410249b316b974e04799a52adfca3a4e606a819 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -31,6 +34,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index aa6b619d34b98fb8bb50b995129e26ca1a66685c..82e3b39a522e73c51996b1c28c58c19d21441feb 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -31,6 +34,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 1edc123181f774f8254eb1f33160f274fb789954..9343203eacfd62069120218691b75dc47ef44a7a 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -15,6 +15,9 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -32,6 +35,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 7824b24fb0df72a0cdf833be1e4b3ec235b292d6..d247d114f393e6c68b32981385a1b718e3caae88 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -21,6 +20,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -40,13 +43,26 @@ CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82104000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 8bab45bcffe369d758f538dbec43ed714a47c922..855657ca37a09dc97b9db44d957a7f2e1af8b554 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -41,13 +44,26 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82100000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index a0f05d513daad506d81d9b40086e85661b5597e7..a225f1a37bf756b7e45540b2599425d6f0213dc9 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -42,13 +45,26 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x1c000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x82100000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 2e4db036a4482568ec7aaaa6621203faf4429d62..752dca28dfb2e7f84c48fe66a56990a039ac96be 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -8,14 +8,14 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -29,6 +29,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y @@ -93,6 +95,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_VIDEO=y CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_RSA=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 556f77e222509aa82502f12a2cbbb74a7824ba37..bb0e76df9bb1d98db22497edba647fd2a63e59a0 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -12,12 +12,12 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -31,6 +31,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y @@ -99,6 +101,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_VIDEO=y CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 2adb28c89d1398ef95ad12061ffeaeba6bea9cdc..7025f114479a9137cc7e1e8c5fb140f8e1e29381 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -11,12 +11,12 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -30,6 +30,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 20cb844b01ff668fec8b02f5836e4cf5539fdb36..31773689a75a157a2bf341c85661b3b869569133 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -8,14 +8,14 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -28,6 +28,8 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y @@ -87,6 +89,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_VIDEO=y CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_RSA=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index fdfdf39c619405ac0cadf63b0f1df343e5d230db..c953706216b904ecfe3a65bcb15e660b978335b9 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -12,12 +12,12 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -30,6 +30,8 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_ID_EEPROM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y @@ -97,6 +99,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_VIDEO=y CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 49ed96365e90a8940daa1ecd996d71b534da0ef2..364a34751fcf4624cfb395ae9af3ae6c2b2f4b8c 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -19,12 +26,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index bd5c5f7fea6858678c51a9ce7aca8c0085a392da..7b083b32fba13c45eb8a5d4fb670fdd8d13ee9b0 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -19,12 +26,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index aba4a1e98a0220cd2260c002d89e42448fa65666..7446f01272e0eaab2d54a8c80e221a0f207c28a7 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -15,6 +15,15 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -22,14 +31,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -45,7 +51,17 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y @@ -53,6 +69,8 @@ CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 9c1886b6ffbdf75ce66d81c19fb6bcc5bf9ee7e6..6dd797c652b9bbafdd37bb14b09bdbaaff039f4f 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -19,12 +26,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 1c7b27e3d7ed67f15525655e4325ff4a33575752..30cc15a12f3d5ed68cfda4161ccb32a349dee2b9 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -13,18 +13,24 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x40300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x40300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -37,6 +43,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 699ac5b1050d2744a33f38101e11c5468e5b3df5..53f19a376ee8425cb0422ffb727fcf573a55f65b 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -15,6 +15,16 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -22,15 +32,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -46,13 +52,23 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x17000 +CONFIG_SPL_PAD_TO=0x1d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001e000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 78ff90d19e0a056118a77073829f9265643699c4..447a51513fe3be73e08f72816c2054fbb1d8ef29 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -15,21 +15,27 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" +CONFIG_VOL_MONITOR_INA220=y +CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -46,13 +52,23 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x17000 +CONFIG_SPL_PAD_TO=0x1d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001e000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 6f920ef8a88561349b2fb2d4f3e48f10a0bc6277..1ebe893b43d41b179ac7a3261c65d37ce3c3b154 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -6,22 +6,26 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -35,6 +39,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -62,6 +68,7 @@ CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -100,5 +107,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 031b5d8e753307997a4a3e30898574871d9164f8..d04d1d918b72eddc1d06953cc40089a667ca10fe 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -14,16 +14,20 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x60500000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x60500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -38,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 65c336984e77feb64507be5df147ea1e083a9638..787c8f96bd56a1a25177a0f4ef25df95dbcf99bb 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -13,7 +12,14 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -23,6 +29,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y @@ -41,10 +49,12 @@ CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -81,6 +91,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index c617716c53c4ac0d5f6381161128bffbce6f5391..341fb0f926983713d80bab504620bbe73dfbf7ca 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -14,7 +14,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y CONFIG_ENV_ADDR=0x60300000 +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -25,6 +31,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y @@ -45,6 +53,7 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 750cc548998a476e184351b43ba9107d4e6c0daf..305734d748228db6f0429afeee96ad384a485558 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 @@ -15,7 +14,14 @@ CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -29,13 +35,25 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y @@ -59,6 +77,7 @@ CONFIG_SPL_DM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 78195de5ff196af6e817aca3ac0cbbcbc620cf5a..56cdef82216da60e73641ccdda96581f4fdb7395 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -19,7 +19,13 @@ CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -34,8 +40,18 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1a000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001d000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y @@ -43,6 +59,8 @@ CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 69d8d43c93de194956c6d4ab4136db9f12cde6f2..bf2805db9e94f7719662377ed57eaa7183aefa06 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 @@ -16,7 +15,14 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -30,12 +36,22 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x17000 +CONFIG_SPL_PAD_TO=0x1d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001e000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -61,6 +77,7 @@ CONFIG_SPL_DM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index b05731df925bed5a31be1077d4f259728ef40b7b..f1370b5104b6db41b1387cb27c82177f3f3a2082 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -20,7 +20,13 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -35,13 +41,23 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x17000 +CONFIG_SPL_PAD_TO=0x1d000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001e000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index b08ba4f5c63ae9d4b7547d98694f9036f3990d50..12ccb78b9210e312a300b2703bd5ad935c15965c 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -15,6 +14,11 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -24,6 +28,8 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y @@ -42,10 +48,12 @@ CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -81,6 +89,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 90623a7df99fbef615577e094b01b76064f97391..db5229487216cfd091d25fc54f31faadc8949d65 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -17,6 +17,10 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x60500000 +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -27,6 +31,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y @@ -49,6 +55,7 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index fddb02e556ab2afb8e7686d08ecc7474429570a9..1be7002a18596f3d1fdf942f98aed1fa76a79484 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -6,14 +6,18 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" -CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -22,6 +26,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -43,6 +49,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 23ceb185f497b19dc05faa443faece82c8ce321b..f41434c7419b36757f38cbc1f03021fb99549863 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -10,12 +10,16 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" -CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x40500000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -26,6 +30,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 902c14c7354f6202cd28352952e98db03621ee32..fdeedca476787e64d8166f89f6d12726bc840f8b 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -5,13 +5,19 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -19,11 +25,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -34,6 +40,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -60,6 +68,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index f9616ef82dd9c1ad0b99d75a1b329fa49f682a76..a66099c815dd4535dedffd6cc908e250bdb4c82c 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -19,12 +26,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index d1538829d1dcb3128490ab6727b127a45f390372..835159deefbb2bfe5c3c65b73f8a6404a3625b9a 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -19,12 +26,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index b804ac410926f7cbcbdaf89479d27414886ccca9..2a70d660ed66f37ed6470f65fe55b66151324175 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -15,6 +15,15 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -22,14 +31,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -45,8 +51,16 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run nand_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x17000 +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1001f000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y @@ -54,6 +68,8 @@ CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index cb8a7a219bae8fe6ce9e83a7abb1538c217ad083..049cf1e56f981e02adecc78a657cf1bb82075165 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -13,18 +13,24 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x40300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x40300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -37,6 +43,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 48e58f6c103b2f001f8cdd90a0d518f5ae73835d..11554a831d5a0977cf08986b10c053952cb14cf8 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -15,6 +15,16 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -22,15 +32,11 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -46,14 +52,24 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_PAD_TO=0x21000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10020000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index bc548848245620f5171878b7482a70796638115f..68aae882a8078d2f2e119ef56c43782dd99e67b6 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -15,21 +15,27 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" +CONFIG_VOL_MONITOR_INA220=y +CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -46,14 +52,24 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_PAD_TO=0x21000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10020000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index e96cda3cef6eff7d638e77c1ad51e6d957c1b23f..7fd24122f041cb3014e99ff0d416b6f6d7fdc4c3 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -6,22 +6,26 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -35,6 +39,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -62,6 +68,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 633399afc7bc8b1c84d84f7ad564761795dad291..52d3d302d94266db83cefef7f6a952eca1f2dc5a 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -14,16 +14,20 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x60500000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x60500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -38,6 +42,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 2c6772d28f67e7036ef1149b102bf51495d8f6ec..3314198446694142efc3901dff4fceaffcf95e21 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -21,7 +21,13 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,14 +42,24 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_PAD_TO=0x21000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10020000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index b7ace80367ba448010aa1744c1a1b5556f03ae2c..2ea72cc2a8ad5100b588c85fe002225c60c9d31f 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -15,7 +14,14 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -29,6 +35,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -53,6 +61,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 78acce163bfc0e809122ccd231379061d8d9c7de..c6b537f3b8ddaac611d5520bb469314546e798ec 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -17,7 +17,13 @@ CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_ENV_ADDR=0x40300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -32,6 +38,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 9d43c35439b883e7b68f56375b3db4648bae9330..57cebf5f8b43d725a16c87eb836729f8bd0f47bf 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -23,7 +23,13 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -40,14 +46,26 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10020000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x90000000 CONFIG_SYS_OS_BASE=0x40980000 CONFIG_SPL_WATCHDOG=y +CONFIG_SPL_TARGET="spl/u-boot-spl.pbl" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_SPL=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index af30b022c80f10fc7c2c9c8b1171ca2e4913663f..6960aa9d3ffdcb0e146826dbf66ee7791db79d78 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -20,7 +19,14 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -34,13 +40,23 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_PAD_TO=0x21000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10020000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -68,6 +84,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 40e343c2997f57c87acfb5955ca750872ccbb39d..9ca4315c83c7f3492bdc79d99655205c8d4d40c8 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -21,7 +21,13 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -36,14 +42,24 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="run distro_bootcmd;run sd_bootcmd; env exists secureboot && esbc_halt;" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_PAD_TO=0x21000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8f000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10020000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 369b80a18df7056506a737bfac1fdada6450ccc3..e192ef48b131a5fb1369a21fef5e86b32da8deb8 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -17,6 +16,11 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -26,6 +30,8 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -49,6 +55,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index f126cb7036e3c20f09160d80d02564a60d633be8..6e5f29a708dd7d5a59e3e3ce601e42c1446aebd4 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -19,6 +19,10 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x40500000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -29,6 +33,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index d1a6dc5ac451f90fc81c94ad916f1d7d72934b99..64d87ae9b4f3cf7cb6261a082cb5b3821b537987 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -8,18 +8,19 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x80300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x80300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -35,6 +36,8 @@ CONFIG_BOOTCOMMAND="fsl_mc lazyapply dpl 0x580d00000 && cp.b $kernel_start $kern CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -67,6 +70,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 130af4a7fbf1a889f5ac6c2ee30605ceb3bf5168..3af10a0e0627bb01d5c21d25bf9bc941f34b287a 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -5,22 +5,23 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -34,6 +35,8 @@ CONFIG_BOOTCOMMAND="sf probe 0:0;sf read 0x80001000 0xd00000 0x100000; fsl_mc la # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -61,6 +64,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index eb3e51343e8ed3ac594413962948452576283078..55a5389272a4d15fdfd948b7adb88badcfd49e25 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -9,20 +9,21 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_ENV_ADDR=0x20300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ENV_ADDR=0x20300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -36,6 +37,8 @@ CONFIG_BOOTCOMMAND="sf probe 0:0;sf read 0x80001000 0xd00000 0x100000; fsl_mc la # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -64,6 +67,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 9725bbe3014c6a84b27c3552675acb9019061217..d3b068483968c242d97ada4e45c78039d57ccfed 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -11,6 +11,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,14 +24,10 @@ CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -39,12 +41,22 @@ CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply d # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -78,6 +90,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 0c7a465f3bf7dc6133a83c6e65780b2f829d87a5..fa1f71d77c1f111d97e412fc319f632fb4750d57 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -11,6 +11,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,15 +24,11 @@ CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -40,11 +42,21 @@ CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply d # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -74,6 +86,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index fcd4757ab2e5a529c1169bd75458c0cffe4e1e53..af5ecadec9d376b871af795cbf4076a34892786b 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -11,18 +11,17 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x20500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -38,6 +37,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -77,6 +78,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 4373a7bb84f2f7b5cc8c8878e782173d6a296eef..b4cae480e17549b4684609fc225eb1c6a6850547 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -5,22 +5,23 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -35,6 +36,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 7d6340997f5939b46d664a2baf4cec8839832c9e..452ee839b87b42127ab19d928544a4501a202d8c 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -9,20 +9,21 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_ENV_ADDR=0x20300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ENV_ADDR=0x20300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -37,6 +38,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 279e756f0f248c85fb02fe351adb2962ecae6e7d..e36512e62d5502d3137199a93c0b0988ee6292db 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -7,10 +7,15 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,14 +23,11 @@ CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -40,11 +42,21 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index cb390573a25bba5acba60749ef52a4cc88492d11..2f81a1343c171eccbb1a6a90f4c26731a1fffad6 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -11,6 +11,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,15 +24,11 @@ CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -41,11 +43,21 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 42094a6b140e8c312e8adda77f911e5a43fc6eb3..b5f556dc2035ef0d7d94a51cffca8a5f75c1f537 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -7,20 +7,19 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -36,6 +35,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -99,6 +100,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 364fe1882eeb1c711a073f91ea43ebf9c7ed5a40..3af7828887cdd605e4071638a2d41783fd661960 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -11,18 +11,17 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x20500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -38,6 +37,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index ff0550db53f038b302505d4465a41da2688ec85a..91cb2df6ee1a01ab48e1b53d8df828088713d199 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -6,13 +6,15 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -25,6 +27,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load" CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y @@ -55,6 +59,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 97eebb727485d25185e9600ba4ab255ce05204f4..8aef83af820fb7044238ed44b5646fcc279c55bc 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -8,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_FSL_LS_PPA=y CONFIG_ENV_ADDR=0x80300000 CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -26,6 +28,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load" CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y @@ -58,6 +62,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index e7b2cc4c80207ddcc0870b97535da858994e807b..1d841af6b0c6f8197a0a0cd141856b4162e6486f 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -12,12 +12,14 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT=y @@ -31,10 +33,21 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load" CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -70,6 +83,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index faa8f713b31cb082a796c6c8edf885738ee6a1dd..302de323988890bb74c7f3acaa682569de5d82db 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -10,9 +10,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT=y @@ -26,6 +28,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_BOOTCOMMAND="fsl_mc apply dpl 0x580d00000 && cp.b $kernel_start $kernel_load $kernel_size && bootm $kernel_load" CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -60,6 +64,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 843c1e72ac73d9b6b5b1c9c536835476ecab5f84..e97284222dcd820d3290803a4688b724b8515685 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -12,14 +12,16 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -32,11 +34,21 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_BOOTCOMMAND="mmc read 0x80200000 0x6800 0x800; fsl_mc apply dpl 0x80200000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load" CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y @@ -66,6 +78,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 0a36c795c817add12ea45945ebf230b56c3a739a..4fab4fb3b1508915389bb88597e442c7996a2cc8 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -6,8 +6,10 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -15,8 +17,8 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -30,6 +32,8 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 1001618f6352640a62667a614c09f5c59e2b7d78..c3327cd0b7cc8f8ff9c421e797930735cf1f7075 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -8,6 +8,9 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x80300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -15,9 +18,8 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x80300000 -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -31,6 +33,8 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 505cdc19a3a8352c20c8f3f3d8340b11b3366b5f..6c7b49b71c2cf9f0a310cb8202418e3ca6da6777 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -12,6 +12,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -19,10 +23,8 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT=y @@ -37,10 +39,21 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="env exists mcinitcmd && env exists secureboot && esbc_validate 0x5806C0000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x580d00000;run distro_bootcmd;run nor_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SPL_MAX_SIZE=0x16000 +CONFIG_SPL_PAD_TO=0x80000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x18009ff0 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index dee04065025c3c079f348b54c6b61a9c3bae8a98..fb7faa46d2cb14e24be3b8d2d4bb6343f331ff56 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -9,15 +9,17 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -32,6 +34,8 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index cd535babb54e02d7e6a45eb1eeb9f305d3c8797c..dc0f6f886bdf645c65cf340b907936929ad82784 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -11,13 +11,13 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x580500000 CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -29,6 +29,8 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y @@ -71,6 +73,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 540d8e0f041b531eb835d47f419e0b05edbfe52c..b86f8164f0b85a5a42fc94195747bcace6462391 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -6,17 +6,19 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -29,6 +31,8 @@ CONFIG_BOOTDELAY=10 CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index df0244a8e5cb43a260e0a1271a62e5173e1dabfc..9e08552fb375d41006eb580344da6def57eac24f 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -10,15 +10,17 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_ENV_ADDR=0x20300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ENV_ADDR=0x20300000 -CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -33,6 +35,8 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 2740f0c698e356463f90e0e664f76f5e725ccd75..8d970cce429d3d3f7a56055ac8a2a6c95fc14fff 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -8,9 +8,13 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -18,10 +22,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -33,6 +33,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y @@ -101,6 +103,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 004c557923aae47ebdcdd7daa835cf0b79ee0092..d70d3cbf90b35b4e900e0dbe1973d9bf3d9b5b4e 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -12,6 +12,11 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x580500000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -19,11 +24,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x580500000 -CONFIG_AHCI=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -35,6 +35,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 181fb3e3458ebc4d6833257acbda9e61d1caf5f1..0da058302c3496fe7ecc022e8490a63852668b7e 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2" CONFIG_IDENT_STRING=" LS-CHLv2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_API=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 @@ -26,6 +28,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y @@ -41,6 +44,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 8c92ba2d2d218e33648d973f441af4bff6bc66e2..d847255d5ecfb7cebf9ef70ec400a17fe9ce7b33 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -16,6 +16,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl" CONFIG_IDENT_STRING=" LS-XHL" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_API=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 @@ -27,6 +29,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y @@ -42,6 +45,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index f00d21fcc1e36fe920b164cf3becc13db2689249..b2bc71afa8ef60c56feca83bb35cbdb86f9c9885 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -8,21 +8,20 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y -CONFIG_OF_BOARD_FIXUP=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -34,6 +33,8 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -67,6 +68,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y @@ -103,7 +105,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 32ea3cb387d0fedbf5f6e2b2f80febc424621b2f..32e47c326e8f2166a210fabc2c7d8e68075167e5 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -12,19 +12,18 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -37,6 +36,8 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -74,6 +75,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y @@ -110,6 +112,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index cd19663829c6bc0ca35307a3d43d4e089607656f..a758a4dca2296f652ec207b644180330bef63f47 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -8,22 +8,21 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_EMC2305=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_NXP_ESBC=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -34,6 +33,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -94,7 +95,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index ee63ccdf4607d7a31e825d10f4530f1226a95ee1..e6e794006cf63c293a0c1a5df91dcc8a56327dea 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -12,13 +12,6 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_EMC2305=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -26,6 +19,12 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -37,6 +36,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -105,6 +106,7 @@ CONFIG_OPTEE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index ce106fb018f2c4043047612167180369f187965b..bbdcb895d8e4fb614a27bc9faf46acca5e6a4eb1 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -12,13 +12,6 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_EMC2305=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -26,6 +19,12 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -37,6 +36,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y @@ -105,5 +106,6 @@ CONFIG_OPTEE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 0d8ac1c9b47c7c8333ede288dd5d55714f513f2e..bb81e56fed81811677901ffdbd4b0ca93ab3de41 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -8,21 +8,20 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y -CONFIG_OF_BOARD_FIXUP=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -35,6 +34,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 @@ -107,6 +108,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index a13abd29a7634254636d78e28fee9a870a56d974..216ac800742007fc3383d2251b6adbfa448979de 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -12,19 +12,18 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -38,6 +37,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 114bc6ee728dd7502d68fe45e5c724888e4f9f78..b7a4238e92eac6899b42e2634adcb7354427c1a5 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -12,19 +12,18 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_SIGNATURE=y @@ -39,6 +38,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 90d3e59e57d8189fcd0ad2d955fd3c47369c43a7..2ce0ab91819e55672befeead21f03ad93fa64ce1 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -31,9 +31,16 @@ CONFIG_BOOTCOMMAND="run mmc_mmc" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run try_bootscript" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x70004000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-nand-spl.imx" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y @@ -61,6 +68,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ub CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 88d3cbea8e95cc66dadd73375e25261fff797966..e55b4a491455cfee25621ea3b0a8f642b73f051b 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -12,8 +12,12 @@ CONFIG_CPU_MIPS64_R2=y # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -35,5 +39,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index d4f043ebf29509df2e4386a62dda777027dc3a95..6c6492d3febcc9fdf02dee06608c1285b1eb7c3e 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -9,13 +9,17 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff81000000 CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000 CONFIG_TARGET_MALTA=y CONFIG_BUILD_TARGET="u-boot-swap.bin" -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R2=y +CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=283 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -37,5 +41,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 2002425f378a52ed2f3ce94be40be95aaf393b50..3aff68b0188f5ecfec335575ccd52c73acab05cb 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -11,8 +11,12 @@ CONFIG_TARGET_MALTA=y # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -34,5 +38,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 2c6f99e96bf2cf4a0b75942b09b6577f14c7fecf..e268fb63743f36182a1a86ca36d2054595f8d801 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -13,8 +13,12 @@ CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=283 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -36,5 +40,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index f3e83668465d2f447ad6738e54fff2390b1d4232..c7212ebcd3b97e03426180942439230831326053 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -20,6 +20,8 @@ CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index c325dd7cb2723d4e64a696bb97493d2b93feb4ec..35005fcc354277c1371cf7bb7a56e990162e6815 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -17,12 +17,22 @@ CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x1bfd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 44c97c15a3ff1c12e30a2aee10d534ef81c54153..80b59cbb053b5c7545062e92a6d9ec20b8ce0f09 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -24,11 +24,15 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x18000000 CONFIG_SYS_OS_BASE=0x8180000 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NOR_OFS=0x09600000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -58,6 +62,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 4c719337eeaa8f1a9a28f75ebd94a812f5d78336..6984256a1c2d5c0b35c1fc723fb313170a74b608 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -25,8 +25,11 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NOR_OFS=0x09600000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -56,6 +59,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index d1eedc6aa88c6eac7201b00f9f98e965a1b54edc..dd402f286bac663239994f880b7bb0e510ae1637 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -13,7 +13,17 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2089 # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/meerkat96_defconfig b/configs/meerkat96_defconfig index 930c998b7e70219b8419a224885c3140a1533b15..4fdcdafac2051f2a7e8f1932803cfa41b069121c 100644 --- a/configs/meerkat96_defconfig +++ b/configs/meerkat96_defconfig @@ -15,6 +15,8 @@ CONFIG_IMX_BOOTAUX=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index e636a3199ae57d0d0a9776942e058388c828d0aa..315c4841825847efd7ea95550e899837c5bc8c4f 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -18,6 +18,8 @@ CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_LOADS is not set diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index c549fa232fad6bff22728c307769584ea22e301a..9246f095254411b05ff6d1c6b9e553a8e0374f63 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -17,6 +17,8 @@ CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_LOADS is not set diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 3142b469c26b95c70b76df188be971d4f8232aae..ad61859b897eedeaa5d5993cb721bdc44709f379 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -14,6 +14,7 @@ CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1 CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=-1 @@ -24,12 +25,21 @@ CONFIG_PREBOOT="echo U-BOOT for ${hostname};setenv preboot;echo" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0xffb00 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x100000 CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x2a000000 CONFIG_SYS_OS_BASE=0x2c060000 CONFIG_SYS_PROMPT="U-Boot-mONStR> " +CONFIG_SYS_MAXARGS=15 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y @@ -76,6 +86,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 6cae07a1d1a4817f92bc735b0288dae09560858a..cf093532b1920d3cab1e2b23e6bb7330cb9f92bf 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -8,10 +8,15 @@ CONFIG_TARGET_MICROCHIP_ICICLE=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index c051e00a6ab7d72007974c7fa544171d7da20d65..2e9edc6c4ee639d97e1c2394bd0dabce78d75728 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -32,6 +32,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -60,6 +61,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y CONFIG_SPI=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index c5af739fa4886559f36c7e737f07927982fce3cb..34465f99a52fe7b9a8dc5e4e51d86aa9c988b159 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -15,13 +15,20 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 0e4cdc4467015e56215e29e184be9935e3fda953..11e3dfcf4babe8a93275f7a0774f1ecb7d15a964 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -9,6 +9,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 21f7a6e535d2091d4731e8cb404143852475ad69..3ce7e5f1d68ab93e922c8e3f168528a4c017076c 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,7 +7,9 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 416565e5af2bc655d29028927c54c127da1cee0b..0fd8d3adbd21e60450ee977daa85394fdda2b2d6 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 965a9cd5c4b09658ffe15c846f0a5803c5836381..942911bddbaffd99b8852c7704d6062fbac8841c 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,7 +4,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 20bca75adfc49905c0b296ae31edca37420fb561..7df44fb81f11c5e6ed86f2cc030d1ca6739fee07 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0x60000000 CONFIG_ROCKCHIP_RK3066=y # CONFIG_ROCKCHIP_STIMER is not set CONFIG_TPL_TEXT_BASE=0x10080C04 -CONFIG_TPL_MAX_SIZE=32764 CONFIG_TPL_STACK=0x1008FFFF CONFIG_TARGET_MK808=y CONFIG_SPL_STACK_R_ADDR=0x70000000 @@ -26,18 +25,28 @@ CONFIG_SPL_FS_FAT=y CONFIG_SYS_LOAD_ADDR=0x70800800 CONFIG_SPL_PAYLOAD="u-boot.bin" CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000 CONFIG_SD_BOOT=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x32000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x1008ffff CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FS_EXT4=y CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2 CONFIG_TPL_NEEDS_SEPARATE_STACK=y +CONFIG_TPL_MAX_SIZE=0x7ffc +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 1b77a08a93cd6f97dc375569adf1a41020da964c..b2e1a8e8261021afd2fc62bb65c6defb4fd43a30 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -6,17 +6,17 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x70100000 CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_JR2=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fc00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -26,8 +26,11 @@ CONFIG_BOARD_TYPES=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="jr2 # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=279 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 502c8ef61c51e278ab19869d19abb6902f8dd95e..8eebe7b314db61a901b717f83665c42ff1e7eb8b 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -6,19 +6,19 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x70100000 CONFIG_DEBUG_UART_CLOCK=208333333 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_LUTON=y CONFIG_DDRTYPE_MT47H128M8HQ=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x87c00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,8 +28,11 @@ CONFIG_BOARD_TYPES=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="luton # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index f3f8eb3847334a3eb96e865437c0530f91770de5..6ba931162650569b3667076986b38038bd4a4ca9 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -6,16 +6,16 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x70100000 CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fc00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -25,8 +25,11 @@ CONFIG_BOARD_TYPES=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="ocelot # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index 9bc94ebbb876b529ae5586680d0fc72a1b6b2c61..1b9096682f0910ef69d03f9497d134cd1a159780 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -11,9 +11,9 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_SERVAL=y CONFIG_DDRTYPE_H5TQ1G63BFA=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x87c00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -23,8 +23,11 @@ CONFIG_BOARD_TYPES=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="serval # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index f861b4713d849e92791f1c9dc06b3e9b6f63ac1e..ca358e666a19f1cca6d9293d8b85be90fd3ba0ac 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -10,9 +10,9 @@ CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_SERVALT=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fc00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,8 +22,11 @@ CONFIG_BOARD_TYPES=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="servalt # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=283 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig index af1282c99044f4557048cb4a1cd48f64027ebf8b..8c64bb740a305cf2e166ee0704009d86e55e7f8a 100644 --- a/configs/mt7620_mt7530_rfb_defconfig +++ b/configs/mt7620_mt7530_rfb_defconfig @@ -23,8 +23,13 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig index ac7a56ef1eada0e2e401efd4e1019052fd2b5a80..2aa6eb7e2697fc53fbf72cb9d4a6e0aa16bb5b1a 100644 --- a/configs/mt7620_rfb_defconfig +++ b/configs/mt7620_rfb_defconfig @@ -22,8 +22,13 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 90e8d774ce6b312367a0ea29e83209264a0bda90..c2df7172296eb526f86d847900f10f1310e1b4f1 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -14,6 +14,8 @@ CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" CONFIG_LOGLEVEL=7 CONFIG_LOG=y CONFIG_SYS_PROMPT="MT7622> " +CONFIG_SYS_MAXARGS=8 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index 8b21afb06d822be3194aa19356c7e78480cc6ec9..c8ac1997ca5804807c175c88494b8cf4e6a83d79 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -10,6 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc" CONFIG_TARGET_MT7623=y CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 @@ -17,6 +19,9 @@ CONFIG_DEFAULT_FDT_FILE="mt7623a-unielec-u7623-02-emmc.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_MAXARGS=8 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 677e192bcb425f40015e5d5c1cce870a81d1f27e..4e8905b68f7925e25e67ec25fef253deca025017 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -10,6 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" CONFIG_TARGET_MT7623=y CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 @@ -17,6 +19,9 @@ CONFIG_DEFAULT_FDT_FILE="mt7623n-bananapi-bpi-r2.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_MAXARGS=8 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig index 5862295871b153e9b929c9968db5704235e219ce..14fc8b05e3cfa3ea29a768a5dd36fb860369a202 100644 --- a/configs/mt7628_rfb_defconfig +++ b/configs/mt7628_rfb_defconfig @@ -22,8 +22,13 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 4d47b47be493c9f8a930cb63938ea26a36db73f0..a74c3edbf8e6919a7d704bc0a83bff6cd1c4a2e5 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -15,6 +15,8 @@ CONFIG_SPL_STACK_R_ADDR=0x40800000 CONFIG_SYS_LOAD_ADDR=0x42007f1c CONFIG_SPL_PAYLOAD="u-boot-lzma.img" CONFIG_BUILD_TARGET="u-boot-mtk.bin" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41fffef0 CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,12 +24,20 @@ CONFIG_BOOTDELAY=3 CONFIG_DEFAULT_FDT_FILE="mt7629-rfb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x106000 CONFIG_SPL_STACK_R=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_MAXARGS=8 +CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/mt8183_pumpkin_defconfig b/configs/mt8183_pumpkin_defconfig index ea7ab5c8096d2bf0ee8e7dfa8404334aa36a4028..ab2a9c7efa12a349eb598a10fbc3e8962a1bcb1e 100644 --- a/configs/mt8183_pumpkin_defconfig +++ b/configs/mt8183_pumpkin_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="mt8183-pumpkin" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index 7e711b1b469f8383102939763b3919d6c6077b17..4e7b8fbdd35eb1e0dac21157c399d49db73df97a 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -15,6 +15,8 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" CONFIG_SYS_PROMPT="MT8512> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index 52c12609b152fa2630cde26659b5991252e77c7a..0425ffd0f97671353bc63b71289852e6ec9b83d9 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -22,6 +22,8 @@ CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index a994cd3a2da921e66ded7f5068f66b893663d380..8a2ddabcda7fd44b1b10c3b330d9e606674c15b7 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -15,6 +15,8 @@ CONFIG_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="MT8518> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y CONFIG_EFI_PARTITION=y diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index e4a786c011ce550a07724a337acf4a0a94af8bf8..bcffaefb9b1963b18418c881bf0bd908cd14a9be 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -22,6 +24,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Marvell>> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y @@ -43,6 +48,8 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index ff891150d2442a1782378d24e395af8698b8ced5..437d438f8ff651e95425653390dfcda7ab0d9c68 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -23,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y @@ -44,6 +47,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y # CONFIG_MVEBU_GPIO is not set diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index ddbce1b52c43fd6e93c8783e3611cfc693b1ed47..2eee745ed67a4a07da0d59773806c08003eb3f09 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -22,6 +24,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -40,6 +44,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 64f3f2f3432bcb9cd00f295907a902f421f2c4ab..99d46c1a2a80a2da316dcce894f0b17f0eb2c61d 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -24,6 +26,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Marvell>> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y @@ -44,6 +49,8 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 8d7d57ff1bc6fc7fbd3443f5d739ab65e7544971..dd1f91215065fc2e3f53deb2f8eb9dbe68db225a 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y @@ -26,6 +28,7 @@ CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y @@ -55,6 +58,8 @@ CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_PCI=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index e8095d4cedf02849dc4a84b64d6521fa3314e179..8164beb1413200e4280c2db9256b7512dd5a9a05 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -23,6 +25,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -44,6 +48,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index 1c773458dce94868b8e4b9bac5c2f37fcd5d2c76..25ae690fe600a5f51605a6e3fb727073a06f1ec4 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n" @@ -27,6 +29,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -47,6 +51,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index ff656c5efd1cd09c99030d60b753ab47bb0cae4c..9ff772434b738949d34feb28a6b6350c655df839 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -21,8 +21,9 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_CPU_SUPPORT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 41c5b37d0af2d0a7a2b85178e4434441311b054b..56122873c4f2e3621bc00c06b4436e1fc1cae63c 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -22,8 +22,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_CPU_SUPPORT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index af9ff1941870e37797f019c9c73ec3198f996d6c..b9c85d616079574d535127dd702225cc42871a71 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -19,8 +19,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_CPU_SUPPORT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 3a9c7ff54175163568ba690fec38bd7da08e2cd6..bdfad9fec6224f59ed0eb8e827b9519aed2d5e47 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -23,8 +23,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_CPU_SUPPORT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index 7ffdb817e194a9b6bbd328833ab060aab63ef537..136c1d60699b039d339435fca7f209d84dee3047 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -20,8 +20,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_CPU_SUPPORT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -42,6 +43,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5 CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 1bac5851435916350d7a24f2da88e6dadba16133..ab8c34c8b1647839cca6baf1f98b2ed644ba3e41 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -18,8 +18,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_CPU_SUPPORT=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index e3b6c64c087a144cd4998a585d4cb090d51a727d..8bd32003812d8196abdf72a0ff7c227b9a323474 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -18,6 +18,8 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index f79595db6886a58d6bf54c7c178a9e2295378e61..8d5c76f69e4932eac12467bab8800e67687fdef9 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x70010000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 7cf959beec7cce556c8bee937df772a75b7dd9b8..bede23dccc0b03efa6871eb71ed69392cde6690f 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_MMC=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index e4eddef15ab69c2475db132ba2a84237d201766d..c92e89c612b8370d0e7cb9538bcf8306da63ab06 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -22,6 +22,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=48 +CONFIG_SYS_CBSIZE=1024 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 46634a1727787a6c96b653671fc7ad0d88f64513..1f15287369e3399847c8dde6752e0c5f18c2e2b8 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -27,9 +27,13 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set @@ -52,6 +56,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index b2185172bb6814e639b476321058e3c19900f4d3..021e8a6151eef00ebc82f7a28b8d5e5b3011c5b2 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -15,9 +15,11 @@ CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SPL_USB_HOST=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=528 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 472758ac889465a86ef7053e7f9f89a71d9889d2..fa2c280a8d405216ad18460e2ca2182fd9052e5b 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -25,6 +25,8 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y # CONFIG_CMD_FLASH is not set @@ -52,6 +54,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 053026daa31dbd06b465edbe0f9481c924bd2d8f..d9d429b4f9627bce7e494097995ee4daec75635d 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -33,14 +33,18 @@ CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loa CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -99,6 +103,7 @@ CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 674384c8785af9cbedbd6323865ab75f8ad735c0..ea0c764674624060f1a0907404487577ef4a3ac9 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -32,12 +32,15 @@ CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loa CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -94,6 +97,8 @@ CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 79057f7f4c14cebbd86f48a25d07e8a9a153a775..34f9b06deefb0692a9de73761b59e7854b52d3b4 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -15,6 +15,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 2f9026287fc6d1278ce4286fd1036488a57c293c..5e54fd3eac4229e939328020fc41af28e8b7ad8b 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -17,6 +17,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 5a43a5501ceaa033c26a1d553471cf04b7c8d410..c05c33d0df88797696b2d4979ea5f42b29291a35 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -25,10 +25,14 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index b949b5e30c082968cb952af25897aaa7ffae07e0..ec6843e57431edb9f5f65e8d4fb4be0cfa14cfc7 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -17,6 +17,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 3fea1b17faae4fad909b2a89819768d569b203ee..bd44298cb2971916f9a6292bd696e2ce151017b2 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -18,6 +18,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 30194a8cde48e5a5b8e5b70ac0b0810b665310f8..d32ea1ea3cac7847774d92da4a4afccd795de344 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -14,6 +14,8 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index b5b0b374f2e54e9eeb01fe753b1f4d7a38e20e90..1985ff96dec34684231a20e6aefafd304a616afd 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -58,6 +60,8 @@ CONFIG_DM_ETH=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 1e1e799eb384880291ad56556dcfd166b1ef118b..784a5d97f086e1f5dee51e2df762afde09e01063 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -27,13 +27,17 @@ CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc resc # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -89,6 +93,7 @@ CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 4b90fcad261f74940fb705b1b56948b6a6316867..de77e4fed6df57ef4ed38944bb7c2346eaf28a61 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -27,10 +27,14 @@ CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc resc # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index ec526b6e4f81c3217bd48bbd28d758149182c4ee..c48fd4adae0bdd61db9eed3d7794ce737626b5df 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index ec2a537581dc655ddd337385b1e38d56cec9d355..a9b7eb4aaff20e02ebbb633caa7ceefc9b3fd4b4 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -17,6 +17,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 0a7002d936e948cc5da027b9767069f257ac45e0..a3afd12d2cbc5aff0d269f2acaa4a5ede72f4bc3 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index d8c5dbcc93a8ed791128a6781f223efafbb713e6..0de958b621b9136ed24d2840c77eb2b8ddbacfb5 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 7aa35791089db5a79ace5027a4fe81cb8d3c397c..c52f45a97493cccdf5838b76ddb8f5036dede325 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig index b9154a9e3c6d0d6eb4a55d14d7da31f3256385e7..2b55fbd3b29a8b15c9f8febb5ff4060310c72c70 100644 --- a/configs/mx7ulp_com_defconfig +++ b/configs/mx7ulp_com_defconfig @@ -17,7 +17,10 @@ CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi" CONFIG_DEFAULT_FDT_FILE="imx7ulp-com" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 12c89b5be962e1130a9a24f787841884ba92b69b..95cd22a59d8f2e4cc3f8ac9a3873c0bb7485b12a 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -17,7 +17,11 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=256 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index cec1a878714c26b83d72977dc8ffda97c9bb3a5c..45cdd74f09abf799a4825dcf7c272dd950b804f6 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -16,6 +16,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=256 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index 4f99042b51a374034457c57dd0f624789c85ac2a..f748b4dd66bad69e04f7543e877c6a11f210b608 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -19,11 +19,14 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 31de4bd1a9467ebb1b73f0fc0005fa1f179095a9..15ab46e5e12f3df6df56c3e8ae4142c3084afc6e 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index f7d8f788c69b71bfab4fe4417ae51ec7f80d1873..dafbf16cb821b61cc2a8d964e495a513804374e4 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -10,10 +10,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" nanopi-k2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 7c8eff869b6338948daf95b5e528410fba200c35..93dafb8642296f63be21a12d545c4ab69b1043e9 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index d500ebe58dc499b2de9ed36fa5e6fdb1eb72c751..b5d9f4184d6c8ef9f26816882381a82ede74c7ae 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 16e39035e5e5f0b0a4866c6214cdd9e3ac0a6b63..c4b51adb6e1f556f9bdc5998c57f529b4987c148 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 753ba92d0ed1674ae8a704c5e2737e780f925c14..2bc066887fa5aefce21e1c89d0159951b105332a 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index ed6b80302162494601486ddf92087319c5373fa3..eabbd47f268a2ebd2f164c6bfa3bc0ce40d5f71f 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -26,13 +28,21 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -93,6 +103,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 46ba07f4d5558e2200b50ec8819277bfb7c505c0..917fd3fd8eb8046797593cf8a0b5af9d74153cb4 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 70fc257eebd9c7f9924ad833767288f4d007c15f..226ccaa12ffe852205f864c2b853e194fa879d79 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -5,6 +5,9 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index dc2dbd62900350c3c04bb45d08b810acf79b762c..47a6b7804e379ca830aea2d040f766a95b7e66e2 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -5,5 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 37b7817d869ca89f42d25a1bcd497a36746acc2c..c71d721f743a15bf4f5d875de0be8e2e26cf72fd 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -8,6 +8,8 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 95dd56aa04c791562b63258b2d9748d22e7f4054..6fedf056ff72043d359b202c5e43e1bf5a76f223 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 806d95c1cc753f1bdd596a6e524c138c5d933ce5..b83b6a3499dd3cdfde280b96b9e693368dfe62eb 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -7,5 +7,7 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index c0255196384f0bd0c78b3ecaf6bcc8b6e3c090d6..f8377535e97dd70b39c8ac751dbbb02f8e3bdcf8 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 924ff38f17cacf9be50b9a0520633df489251df6..3f834b756dfd759e61678b41ce0af461fabaa7f2 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -9,6 +9,9 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig index 27cf172d72af1180fb4cef03529fa7c09cc4339b..a0cf8ff0442fd4364f7d07abd391fceabf8b60ca 100644 --- a/configs/nanopi_r1s_h5_defconfig +++ b/configs/nanopi_r1s_h5_defconfig @@ -9,6 +9,9 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 924061da99f6b2412acb4e072e19d0555fcfd9a1..cc971f9b19a034c3a13b5aded601dd2191ce7ffa 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -12,6 +12,8 @@ CONFIG_ENV_OFFSET=0xA0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220" CONFIG_IDENT_STRING="\nNAS 220" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -20,12 +22,15 @@ CONFIG_USE_PREBOOT=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nas220> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -33,6 +38,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y @@ -48,6 +55,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 522d8adfa7b4e3aafec03b3879b780f6bd40cee4..248ce90519eb08f81acb3cd95a1658eeff33cfeb 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big" CONFIG_IDENT_STRING=" 2Big v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,6 +30,8 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="2big2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y @@ -35,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -51,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index b126bd382edfcd9d4033b24bf7ab66ef1319e4aa..4336116f5770786999b64bc1f4ba4bf6a33e189f 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -15,8 +15,12 @@ CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CG3100D # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=539 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index d04e73f847ce9ad05a3f6270976b63ffccc70b2f..73de5ed15b15ce8731b22aaafd03f16836ca1bbb 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -18,8 +18,12 @@ CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="DGND3700v2 # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=542 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -64,3 +68,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 153ae76a10b4d188a91c0b7e0c42eb54fac61b12..eea86eb0b73657133285cb09f7be277ba1507d8c 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite" CONFIG_IDENT_STRING=" NS v2 Lite" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,6 +30,8 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1046 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y @@ -35,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -51,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index b5d77fa5918c2a1f5dfb4af0957260103666b07c..cb06fe2ae3cf57cd1ede2a0961ba4fc0083db570 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max" CONFIG_IDENT_STRING=" NS Max v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,6 +30,8 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1046 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y @@ -35,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -51,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index ac92f42911d8577a1be346946843a1a313267ac5..3a461469106ff57b648581a45fbab118ad4fe227 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini" CONFIG_IDENT_STRING=" NS v2 Mini" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,12 +30,15 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1046 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -50,6 +55,8 @@ CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 CONFIG_BLK=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 00c19f55c95b4ef3b57220061e083c8e4351469d..d39b6a479e9490a3530fd766474324d95a3d41a9 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2" CONFIG_IDENT_STRING=" NS v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,6 +30,8 @@ CONFIG_MISC_INIT_R=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1046 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y @@ -35,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -51,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 3a0d95c37310f0866e9e7d07eec32b0a2d17d7bf..2d653d4d0d339c222b7f3847d5c1d6cdfdfc0e5c 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index f8c1cb11de93fc82abf33d1c360cfec13d639998..282fea4508d1b234cc4867941a67eba2a211a4be 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 02b168c2d45d84bd126e61eaf1d55d7116307d86..ec75ead6e20c207ca2af0c71a48b8f7a5dc4a1ef 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y @@ -60,6 +62,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 1286ce5d8c54bb584d5339f67e9332f87c2edc8a..1b999ecc9c176eb5d6fbdaa3a25dc1e05305b61c 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y @@ -60,6 +62,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index cec00603cad3b0542a6eb07c34ff1377224b864b..60edd7d6e321d0b1070d55ae5e457b38fc48f50f 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index d6d7bac57827600c0f61e521e2c28f138acd7fcb..7d1da4cf6b1a8e80ba25a42f8e5cbf6e62a169f1 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 309cf28269c149687d6df4e61bfc892744d490ff..6c3a95cd069c533ec9c5ac5e4508e9bc3b6fab7e 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -28,6 +28,8 @@ CONFIG_PREBOOT="run preboot" # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Nokia RX-51 # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=287 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set diff --git a/configs/novena_defconfig b/configs/novena_defconfig index db33d1153bc278497e528bf15b42f376a45b663a..d4ab93850c4a1a9fddf8cd596a80ef17e808cca8 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -31,9 +31,13 @@ CONFIG_BOOTARGS="console=ttymxc1,115200 " CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_BUS=2 @@ -59,6 +63,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -70,6 +75,8 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index ff015e36a5a058670fdd2281711612aea07bc631..2b39ae74b3150c12c68d2e106079032671998f47 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -14,6 +14,8 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s" CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000" @@ -21,6 +23,8 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="NSA310s> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -35,6 +39,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y @@ -48,6 +53,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/nsim_700_defconfig b/configs/nsim_700_defconfig index 4dcb948f49871e1f39c22ca4250af64a05887555..60809400d26397c9b9e58b1bc961b155d79f68dc 100644 --- a/configs/nsim_700_defconfig +++ b/configs/nsim_700_defconfig @@ -10,10 +10,15 @@ CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="nsim# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/nsim_700be_defconfig b/configs/nsim_700be_defconfig index cf62da15f2b7e067176ff95f116fca2c7be5b555..e021cc94cca6101e9f06d4bf7d3251390fd6cfe4 100644 --- a/configs/nsim_700be_defconfig +++ b/configs/nsim_700be_defconfig @@ -11,10 +11,15 @@ CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="nsim# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/nsim_hs38_defconfig b/configs/nsim_hs38_defconfig index d85d00e00af638128d6df05f72bbd11f6d8f3f20..3c3d1812a791e418cf065e748815e44ab06c54f9 100644 --- a/configs/nsim_hs38_defconfig +++ b/configs/nsim_hs38_defconfig @@ -11,11 +11,16 @@ CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="nsim# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_DM=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/nsim_hs38be_defconfig b/configs/nsim_hs38be_defconfig index 7d16c2ed6e5ece7791d8160c25babc398f6f374f..9e1a14845df3c31995e888cf4a4fc3050a7c3e3b 100644 --- a/configs/nsim_hs38be_defconfig +++ b/configs/nsim_hs38be_defconfig @@ -12,10 +12,15 @@ CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="nsim# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index f82bace9e750e9d8fe878b2adcbee1642aa8c527..a48920cc99da2d9d1b9d6f6b9db8942b1538231f 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0x70006000 CONFIG_DEBUG_UART_CLOCK=408000000 CONFIG_TEGRA124=y CONFIG_TARGET_NYAN_BIG=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x82408000 CONFIG_DEBUG_UART=y CONFIG_FIT=y @@ -23,7 +24,17 @@ CONFIG_SPL_BOOTSTAGE=y CONFIG_BOOTSTAGE_STASH=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0xef8100 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2087 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/o4-imx6ull-nano_defconfig b/configs/o4-imx6ull-nano_defconfig index 27a82b11630423089844135cf720f4ba7c015bb6..b634a82eaa7f343e5f72eca1d3305e41b1c4e2bd 100644 --- a/configs/o4-imx6ull-nano_defconfig +++ b/configs/o4-imx6ull-nano_defconfig @@ -8,6 +8,8 @@ CONFIG_DM_GPIO=y CONFIG_MT41K256M16HA_125E=y CONFIG_IMX_MODULE_FUSE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 7ce63ba665d63f265fabcd5566ba8ce841936d88..1cd8e9f2b680c4cee3455b9b6da108545b166618 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -10,6 +10,9 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index f70f0d214cf98bc044a4c8947634ffba0c1b63c7..0a18b94295a6df4f77ab1ddf27eccebc206ae120 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -18,6 +18,9 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index 3ab5838f03e56db14f118726ef559ca693f1078e..95e98c1161db105deb60fae7300fdbac4bb694f3 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -25,6 +25,9 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -43,6 +46,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_TFTP_TSIZE=y CONFIG_SATA=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y # CONFIG_INPUT is not set CONFIG_MISC=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 46a28e1b2061523ac88e00482de366a03c55f677..d4f9f565aef884c7c7560e8891cb0d58f605d149 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_LOAD_ADDR=0x4000000 CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x04000000 CONFIG_SYS_MEMTEST_END=0x040f0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40ffff0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y @@ -33,6 +35,9 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -55,6 +60,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CDP=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 9d8cc4b7be42a69e9ce70065e8d4ba6ec2fc87ea..aeb9f8a8b6de3aa421dde1e70c445589a9719193 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -16,6 +16,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x4000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40ffff0 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y @@ -33,6 +35,9 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -56,6 +61,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CDP=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index d14e121b6ed223867b4345c3836d6bdf212a609c..6fe96f47553d8d516da98fbdb4371d61d2464e63 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -18,6 +18,8 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x2800000 CONFIG_SYS_MEMTEST_END=0x28f0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x28ffff0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y @@ -33,6 +35,9 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus= CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -78,6 +83,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index f1d482afb62531a1edbe25ec1ccd44db760bfc11..5ba4fc1cad861c0814e4bccc5d14a534a2f7b761 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -16,6 +16,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x2800000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x28ffff0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y @@ -31,6 +33,9 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus= CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -75,6 +80,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index f9b0c79eff7abd630909becac01faa98e9fabf6e..079d86961c2beb654ac40588d9d616b9ea448bfa 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -10,10 +10,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig index f3ea892b5eb298ffb92ebcc0dc3e120ce8b23642..12312dbb2a8ed00c6724aacdd58d7f2485d77257 100644 --- a/configs/odroid-c4_defconfig +++ b/configs/odroid-c4_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c4/hc4" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 8ff71fd28cda5a7c4a2a53a596197f166ba425a7..599ff0b89bcf055bacbf2034660c621d14d27333 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -21,6 +21,8 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -32,14 +34,22 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_TPL_MAX_SIZE=0x20000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig index 4be838314a86b2b470f4a6c2dd4e15f329e7f963..05d818018870bb293fcc8926d7c710cd4ee83cf4 100644 --- a/configs/odroid-hc4_defconfig +++ b/configs/odroid-hc4_defconfig @@ -13,10 +13,13 @@ CONFIG_IDENT_STRING=" odroid-hc4" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index b19f98585cffe705b07df4a4ccfc6f5dd796ccc7..aa05ee6a5db7c633e70a6f1914daf433cd36b464 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -12,10 +12,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-n2/n2-plus" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index a4c9c79b81ddc1408215eeb998105d2e3c94aa46..929a52140d5d19dff85eb79c526137bd81043882 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS5=y +# CONFIG_EXYNOS_TMU is not set CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x310000 @@ -14,6 +15,8 @@ CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2" CONFIG_SYS_MEM_TOP_HIDE=0x01600000 CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x42e00000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y @@ -25,6 +28,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="ODROID-XU3 # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index f2a8cd41912488027aee0c80f79ae21d153039b1..9f4543c1ba844606acd1c16cc703d4ba607b8f8e 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_ODROID=y +CONFIG_EXYNOS_ACE_SHA=y CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x140000 @@ -15,6 +16,8 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" CONFIG_SYS_MEM_TOP_HIDE=0x00100000 CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43dfff10 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -27,6 +30,7 @@ CONFIG_BOARD_TYPES=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="Odroid # " +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_XIMG is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y @@ -68,6 +72,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_LIB_HW_RAND=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index d6ca3c2bda0ff9583743156330fef8a0335b321a..787c26eaa4779a43b9af1b330629bebfa0c67826 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -14,13 +14,18 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set @@ -30,9 +35,15 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x84000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SYS_PROMPT="OMAP Logic # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 @@ -40,6 +51,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 34b3af8ba688af22b9e0bb51bd3c0d3115c40a80..ab5dfad28fccbacbb510acbe34a6c10524109f76 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -14,6 +14,8 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_SYS_MONITOR_BASE=0x10000000 CONFIG_BOOTCOMMAND="run autoboot" @@ -21,7 +23,10 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set @@ -31,16 +36,23 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x84000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 # CONFIG_SPL_POWER is not set CONFIG_SYS_PROMPT="OMAP Logic # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y @@ -60,6 +72,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 4767c0bdc67cd38edf09f5924a8292266da4ae08..5479380786403886c78811ed32dfddd4c80edbe9 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -10,11 +10,16 @@ CONFIG_TARGET_OMAP3_BEAGLE=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -22,6 +27,8 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SYS_PROMPT="BeagleBoard # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1055 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x280000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index d451e201c72573c79666037ff99a167b9a528439..aa7a55e6a1c47af9c967a39063a0eadfd14fe5a7 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -10,11 +10,16 @@ CONFIG_TARGET_OMAP3_EVM=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run envboot; run distro_bootcmd" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then setenv boot mmc; setenv addr_fit 0x8b000000; run update_to_fit; run mmcboot; fi; run envboot; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -22,6 +27,8 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SYS_PROMPT="OMAP3_EVM # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1053 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x280000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -48,7 +55,10 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -56,8 +66,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_GPIO_HOG=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 2397ba534195176e094c9c3b9a710ad4b6afa440..ce777cae88b379077a6868ffb8a0049edeb6f4f4 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -14,12 +14,17 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set @@ -29,9 +34,15 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x84000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SYS_PROMPT="OMAP Logic # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 @@ -39,6 +50,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 721516d9e531f44101ebf67838d23a26d544a5c3..8c5bc19f10bfd9635309886fb9e3555303c8146b 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -14,6 +14,8 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_SYS_MONITOR_BASE=0x10000000 CONFIG_BOOTCOMMAND="run autoboot" @@ -21,7 +23,10 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set @@ -31,16 +36,23 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x84000000 +CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 # CONFIG_SPL_POWER is not set CONFIG_SYS_PROMPT="OMAP Logic # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1054 # CONFIG_CMD_IMI is not set CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y @@ -61,6 +73,7 @@ CONFIG_MMC_OMAP36XX_PINS=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 03e1a6b70dd3bd4f671923859a574386c98615cb..bd6c2ce4caca83ff58159fd57f666635bde572f0 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -7,16 +7,24 @@ CONFIG_OMAP44XX=y CONFIG_TARGET_OMAP4_PANDA=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030df00 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="omap4-panda.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xbc00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GPIO=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 9dae340f643bd74421a36356c49a279632a646e4..62eb75d1f9ae9060406b6c829d3134b0fdb8ef3f 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -11,12 +11,18 @@ CONFIG_TARGET_OMAP4_SDP4430=y CONFIG_CMD_BAT=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030df00 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="omap4-sdp.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0xbc00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SPL_I2C is not set # CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 4c66a4cb39729df1734a0a83834ebe1ef908772a..912dd91259c1051f3389140945cd17ce80a52381 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -11,13 +11,21 @@ CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00 CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; " CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_MAX_SIZE=0x1dc00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y @@ -46,6 +54,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_ETH=y +CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_CONS_INDEX=3 diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 799dc4075713f9952b02705cb33b17705bfd47d0..28f4f95c95bd2e532d8cdac769ffc4624645d879 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -22,6 +22,8 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0xc0700000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0000f20 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -31,7 +33,18 @@ CONFIG_LOGLEVEL=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xc0000000 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x8001ff00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0f70000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x110000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -92,6 +105,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig index 1700f4a2a5b500967da5f54bedb997818270ac6f..98d6818e1be48dc24dd1878fee86fd1ae96ad698 100644 --- a/configs/openpiton_riscv64_defconfig +++ b/configs/openpiton_riscv64_defconfig @@ -11,18 +11,23 @@ CONFIG_RISCV_SMODE=y CONFIG_OF_BOARD_FIXUP=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82000000 # CONFIG_EXPERT is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " CONFIG_SYS_PROMPT="openpiton$ " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=284 # CONFIG_CMD_CPU is not set CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -69,8 +74,6 @@ CONFIG_RAM=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_FS_SQUASHFS=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_MD5=y diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index 8a7e3ccf3dff931e352c755ac8abc84c2eba1017..8ae265f902b7bb9d71033bc31d779d6004b7394c 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -15,24 +15,35 @@ CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82000000 # CONFIG_EXPERT is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x82000000 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x83fffe80 +CONFIG_SYS_SPL_MALLOC=y # CONFIG_SPL_BANNER_PRINT is not set CONFIG_SPL_CPU=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="boot/fw_payload.bin" CONFIG_SPL_RTC=y CONFIG_SYS_PROMPT="openpiton$ " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=284 # CONFIG_CMD_CPU is not set CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -80,7 +91,6 @@ CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_FS_SQUASHFS=y CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_MD5=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 4ae5d1fa5dd788d7632de364514ed73dbfa00edc..ba5d3a6bfc32b7c54c61e4fafcfbfa1c2274c75a 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base" CONFIG_IDENT_STRING="\nOpenRD-Base" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 @@ -23,6 +25,7 @@ CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y @@ -53,6 +56,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 3e6eb170ff830c9addcf9236e3ca8d11ecb2a043..0ee6ce3a65e11849dc99652ff5f82f1497570fc2 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -14,6 +14,8 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client" CONFIG_IDENT_STRING="\nOpenRD-Client" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 @@ -24,6 +26,7 @@ CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y @@ -54,6 +57,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index d7a02dd2d8a0ea7bc47af1f1c6e070a26529a6ee..f7e8a3ee4e7d618061f8d234c15a7a138ea457e3 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -14,6 +14,8 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate" CONFIG_IDENT_STRING="\nOpenRD-Ultimate" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 @@ -24,6 +26,7 @@ CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y @@ -54,6 +57,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 5f5caceb8d4525f74c0f6c0b1fee0952c2bd7717..b76e272e2552e4ba5d7aa28e195024d5db0ec590 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -31,11 +31,14 @@ CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="BIOS> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=535 CONFIG_CMD_CONFIG=y CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y @@ -52,6 +55,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 461300fd10606d628ee4595e40d54a776f001e23..e9626fb09a63b4a4e35cd54ae1e1ecb04bcd35bb 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -12,9 +12,18 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 7aaa5190b3a319381eb1bddf4ace47f4492e2ce3..e18b8610847ce715658a9e9d79f614251bf38df7 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -7,7 +7,9 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index ebecf49ebdaa82b5f1638f72024888b315a1d408..dbca66d14292413e3b1bef3bbc967c7f13a83766 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -8,6 +8,9 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x118000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_PHY_SUN50I_USB3=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 75c97d6b897cdca3fbecadfd0858dba53e0fd037..14c88062812211d9bdc477c3380780348b2f1b9c 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -7,5 +7,8 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x118000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 96bbd1bab6fe96d76dd8d04b99c106be3146c98b..c7174170dbf26977d678d70f4d11990671c16d37 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -5,5 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 1064b4a39de659c455018b2c24e15d0b1349fb62..112ff5e5b6ac571b89a081103abfb52748b8be20 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -5,6 +5,8 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 55a8b003fb5b4b1c89df9a40a92c93687e42e937..a4336332fc753dd51f24156f3884cd8ef070fe93 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -7,5 +7,8 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x118000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 777af8c60ea7035d3cc09c071ff5a0a482b6c9e7..d0cad2a74615735dbf454a863ef265de2ba58319 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -8,7 +8,10 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 905ff7b1271dbce80e2c5d65017b975e8820a8bf..28107ad5f7a231efd57a722351a4625847c8f08f 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -5,7 +5,9 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index f845138153dba42f0f017da0590055ef0f3175a1..30638679bc6e160f01c3415c16e2374a8eb61601 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -6,7 +6,9 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 138a6a72b8ce0d9c871dafe1f865791554ab60ba..85b25ddd1677b0fb3e3425ab95df9ebea0d69684 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -7,7 +7,9 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 76de72aa2287daab3148b75c4e4ea3b9d0a5026a..dff0a2fd6e9823c5e7568108528d7a1561ecec17 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -9,7 +9,9 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 95a82e20f3ec0af3f09180f272329d236ce7185b..690a5f195b63d59622f717353b0691bf21f64fab 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index 4496aa4a45c7360266a955d5112a2f08cc404cad..e15069c048e85738d39d1e557cac99153b013129 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 3b78ad7e52d4fc2aafc4ba4adc8653a4700ff714..7a9ca8e88a80bee692721e872279160dbc9669cc 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,6 +7,9 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 54faf6aba2cf8511e2d54fb6fee8e58613830e42..cad7a7bb064fe8918dd9bafbca933b2d88f47fcd 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -10,7 +10,11 @@ CONFIG_MACH_SUN50I_H616=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_MAX_SIZE=0xbfa0 +CONFIG_SPL_STACK=0x58000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 2dc69d2994a111ff8144c5f7b9d3df8f1eb1eaa9..b5ff84aaf67c3e24d7209f5c7e21c0deee794141 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 9583d24c8d620160663883bb454d816d34c5f945..02f70ccf0c0944a540dd872d256bbacd61964f51 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -9,6 +9,9 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig index 55a251374a1ed72baa249811f7105b911aabbb99..b2d4f3f8e07d1f87c787c941588949c2c13c555c 100644 --- a/configs/orangepi_zero_plus2_h3_defconfig +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index f3ecf35eee1df7b1cb7393b8f330e2ad9d301083..15520955f5efa4658baaa7e348a17f578069e2ac 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 05d955696b2224ae80506a8919d277c7a2163830..9a429a8704a0f26f5422182114426e52b9632ec5 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -18,11 +18,16 @@ CONFIG_IDENT_STRING=" for ORIGEN" CONFIG_SYS_MEM_TOP_HIDE=0x100000 CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000 CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3800 CONFIG_SYS_PROMPT="ORIGEN # " +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_XIMG is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y @@ -49,5 +54,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/p200_defconfig b/configs/p200_defconfig index 4ba0028f73ac444a1b9d53e4c22e27063e3e697d..5fdcc1216f03f19efc2d3317b57adad26a4809a4 100644 --- a/configs/p200_defconfig +++ b/configs/p200_defconfig @@ -10,10 +10,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p200" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/p201_defconfig b/configs/p201_defconfig index 6de83263bdff364f5413e70c334a37cbc4e3ec21..a87c16a60c0bcb870b74b39ee0a52242f2ec1486 100644 --- a/configs/p201_defconfig +++ b/configs/p201_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p201" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 8506601a47b5459d564e5cf8a97e718a4e8f3b9b..ebcb194767e7ef3481668ab7512c50ff01c7645c 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -11,11 +11,14 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p212" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index b335d851bfc0c270b686feb9cd201cef34038677..3852f7ba07f7ad660cc995d3c89eb6127b05335f 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -8,11 +8,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" CONFIG_TEGRA210=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2089 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 5977325973ef4c9e9f928378796f6eef6d66ba17..bf5872203b3d75305cba6433917cbd7013630ed0 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -10,12 +10,16 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180" CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2089 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index d3f169ae2418bd3223bcc9d809350735a35f3120..5f57b1c0198965133157991b477a43f4685eb1b8 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -9,11 +9,15 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" CONFIG_TEGRA210=y CONFIG_TARGET_P2571=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2571) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 47be8a1c2863553829f4266bb55eb79c3e1e74b9..ed23937fed50a6680d3b8227ec9b97746acea170 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -14,6 +14,9 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2093 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 94866cd7693cfe28bdcf40a09d79fe16835ffbd3..15e07a129429fe30c35fc2cb31d0331e5112563e 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -14,6 +14,9 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2093 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index ec813dd7a5b8c345add2905401383bf4169e17df..36a001b83b660f4360054858f659d14cecdb0d1e 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -11,12 +11,16 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" CONFIG_TEGRA210=y CONFIG_TARGET_P3450_0000=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2089 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index d56c4504b6a84e532ad4856b3244962d4ae475e8..14e9b455feb71d08c7912e573c49c94144c4eed1 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -11,6 +11,8 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index f11b57dde7587fc558d841af7b6872cb41c7fd06..0aa8a7673a319c2628ef85a5e4f97bcf9bddf1d1 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -12,7 +12,17 @@ CONFIG_TARGET_PAZ00=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2087 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 264bff86fb97f18552818f2cc08d9907fec43363..41f1dc22c88ab93982e42673c660df3d24b1638a 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -22,6 +22,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run bootcmd_nand" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -29,6 +31,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 8b6a8b35700519131f9b176c3434debeab9706c4..132942bf554cf160b343b97c9381eb86fa0f8dc9 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -30,14 +30,18 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmcboot;run nandboot" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x31400 CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 7c45872052a4250d3ec3f8364862787c9988fbbb..d6662e18ab7b9b46e1aa0da1f5e229245b27a7d7 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -18,11 +18,16 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" for Peach-Pi" CONFIG_SYS_LOAD_ADDR=0x23e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2073800 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x7800 CONFIG_SYS_PROMPT="Peach-Pi # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -79,6 +84,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_LCD=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 9e1fdd4e6a2457730d3744e0c94e8c3e9309e6b5..07740571c7572b1e7e526e59137a410e7ced2500 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -17,11 +17,16 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" for Peach-Pit" CONFIG_SYS_LOAD_ADDR=0x23e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2073800 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x7800 CONFIG_SYS_PROMPT="Peach-Pit # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -78,6 +83,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_LCD=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 844a39fd38842039c43ce7a696fde24f83fc972b..bc58a631bed3007df127edbc9ddef39fc226ffe5 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_CLK_FREQ=66666666 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -41,6 +43,10 @@ CONFIG_SILENT_CONSOLE=y CONFIG_EVENT=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -65,6 +71,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index bea61f70f619c2c6e695b768ff3b7f3a05398e2a..5d70160bd3b95ac2641b083f9febee4b3a1c8a1f 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -39,6 +41,10 @@ CONFIG_SILENT_CONSOLE=y CONFIG_EVENT=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -63,6 +69,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 8161088178208e0fd1a39b58647b227fe8bbb359..a604d3248f2cab11b7fa1e959094f4fae7e17f41 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_CLK_FREQ=66666666 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -41,6 +43,10 @@ CONFIG_SILENT_CONSOLE=y CONFIG_EVENT=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -65,6 +71,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 0a36ab9839bbf54e5f3247eeea521e9552436e97..dfd6d627e1c1b24d6f4bbc284d78030b27d1f6d6 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -39,6 +41,10 @@ CONFIG_SILENT_CONSOLE=y CONFIG_EVENT=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -63,6 +69,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 1344a2350a2ea06ea048c381b431ee218addad00..27342294f79715ceeacee10c1583354772942fc2 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -15,6 +15,8 @@ CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y @@ -22,6 +24,8 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -29,6 +33,7 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 45ded518a93d17f4df3ae12fdd082e7dbf7d1662..95905b4ba4c577bb2623bf8c61677f6878dfd835 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -15,6 +15,8 @@ CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y @@ -22,6 +24,8 @@ CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y @@ -29,6 +33,7 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index ba5833f706000cfc9b530d3983dcf73d2ce2c7e4..0316d45caebbc92d0dcd39e78a0aa3808dfb4fa6 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -26,7 +26,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -35,6 +45,9 @@ CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set @@ -107,6 +120,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 86d0f4df7f6a5d5daac220fdfdadba051f802b46..2c53a5ff8c6effb11b3e5cd55c9c8c3b20759ca5 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -27,9 +27,19 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -37,6 +47,9 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set @@ -98,6 +111,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 6444649222133fa696e321491da370113d57baad..519a705a40edd8c04192b1d84716684fd9c4542e 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -15,14 +15,21 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 0a05c4b22f2a52b45867fc19538a6613a51b5e61..b9d2a976636c6c9c132d9f21b1be90a4d57eddd7 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -18,8 +18,11 @@ CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index a672b16f2370bc388c674ad0ed618b4779b94d59..f172b065bfcfaeb005df984c1b410bfbf14acbef 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -18,8 +18,11 @@ CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmc_mmc_fit" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 8c5934cc9169709f69278bcfacd1dc17126f7a31..a912ea638ff68e44ec30204ab064f6b010609050 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -12,10 +12,15 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x88080000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007ffff CONFIG_TIMESTAMP=y CONFIG_BOOTDELAY=5 CONFIG_BOOTCOMMAND="run distro_bootcmd || run legacy_bootcmd" +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SYS_BOOTPARAMS_LEN=0x1000 CONFIG_SYS_PROMPT="dask # " +CONFIG_SYS_PBSIZE=1048 # CONFIG_CMD_SAVEENV is not set CONFIG_LOOPW=y CONFIG_CMD_MEMINFO=y diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index 8e1c25def99ec6d2c1b61264cbf4b73d32ebfcbc..cb9c6b8fece9f20d54ab1ad445206938a90f292e 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -25,9 +25,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y @@ -69,6 +72,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 90b607b90dffda7900a911eab9753d9b9bc48bd3..3adba803dd4312368526a9409b3977c3fafbbcd4 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -25,10 +25,16 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set @@ -81,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 28414666851b40f995d3ca1db0aebc106ab5c983..0a2f10d0f159602d9a7f36c10b67a18ebf1634c7 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -26,9 +26,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y @@ -72,6 +75,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 1342d8501171efed74a83d615a22902353a0f24d..cbfe346820f5039a7d400ba376ed89b1d3b310cc 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -25,10 +25,16 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set @@ -81,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 5330556734d8dc83b8d2c166d846c09b070c2304..086b3ee3ab25a5d09203c4ada88eb35b37dce703 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -27,12 +27,16 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTCOMMAND="run default_boot" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index c198a660ea33e331fd6ef433fd303b69a6ceec8d..e8f6c434b66ea471f41cc468d06a6bce301a59ff 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -26,9 +26,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -75,6 +78,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 09117e9a4ea8ea11b0f2e7f087ea887b205974a7..a9d21eb02c8da04efd33f059cee0ff457d133c47 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -26,11 +26,17 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y @@ -78,6 +84,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 6473aaaede4cd52c31dea575046aabb63053978b..6a2f87a8bb170d479bc5a8e9ec7b82ec7802a163 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -25,10 +25,16 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set @@ -81,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 91aca29e8301b1171ee9d6e98874a5ffa14d337e..6d4bebd6dcf24f41335ddb2f35c2113dce0646ce 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -30,14 +30,26 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 90b607b90dffda7900a911eab9753d9b9bc48bd3..3adba803dd4312368526a9409b3977c3fafbbcd4 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -25,10 +25,16 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set @@ -81,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 31f37dab26fdedf43e07df7b8fd23e9c7008057c..a184393abd22c0b0e5e7b39ed70b6d8ae38da5ad 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -26,9 +26,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y @@ -72,6 +75,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 812aa24b0910beeab6f986d9d53f328b29086d52..79aa398e1e81f67a90311da72b0d827d15ba90be 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -25,10 +25,16 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" +CONFIG_SPL_MAX_SIZE=0xe000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set @@ -81,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 7e7c2d79104ab139a4d6324f94f4398a70399f93..3f9ea1e329f1a06a8386d4db9fb33363603a8e73 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,6 +10,9 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index f42f4e5923abd79b5ebabed09916bd96e49f8957..62608f93bdb55622633c2208f99770de589c5e4e 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -6,6 +6,9 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 09a4275f0e79223902d0ad325318cb9a377ccadd..2f511c80517364eac79b219f9195570c2ff8d002 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -11,6 +11,9 @@ CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x118000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index aaa52c6ea7032b51eb895808215bcdf088328f26..602bcb78cb26cd664e7ed49fdff5f79baeeef44d 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -15,12 +15,21 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y @@ -81,6 +90,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 26918dd387533b17bd30f9b048e8ba694c944c9f..982f68143b9db7ebda1f3a01c4a943efa7c10d51 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -8,6 +8,9 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 28e347b4d952307c0a21af3ac6d8c15e1366a787..531cf0f83b625f9205ad24cae448725d816dd1d0 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -8,7 +8,9 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 9d39204a439a0fcde0e772e8507723ed67f02eda..905b47d29e6af9a59ce3fb0477c24b836e892c75 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -10,6 +10,9 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig index 0cc24146b3942d660605284080105c22caff9401..e20d20a2fd5e3ffe7839a461a842b282e74c8337 100644 --- a/configs/pinetab_defconfig +++ b/configs/pinetab_defconfig @@ -8,3 +8,6 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index 3a179fa5ae5ef49285a318b9441b5dfbdcb7314c..ad1853f05e21c7c8b3bfff79b00533166f01966b 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -14,7 +14,17 @@ CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (Plutux) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index 8b14e0daf3abdde043f82db858fbfb49d12c3e62..6922380b0093ac1fd9c101a977a2d52e50d285cb 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -11,6 +11,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_ADDR=0x10040000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003f00 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 " @@ -22,6 +24,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="pm9261> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -57,6 +61,9 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_LCD=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 78f2ae9a4bee1ccadb94a0234900bc22b560f633..2b4a844d804b5a0ee527aac40d42d992969d9eeb 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -11,6 +11,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_ADDR=0x10040000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003f00 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock4 rootfstype=jffs2 fbcon=rotate:3 " @@ -21,6 +23,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="u-boot-pm9263> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=288 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -61,6 +65,9 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_LCD=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 1b4dbdeafac56b7c832f9be96be8a6c2933f76bc..cd2d51aba8fedf3b7d5a3d30af3b7eb777b4e885 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -24,6 +26,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 2d807f1a9c1173b905f79e3326221a06f1a62011..e1a2517eb6377c86d440933db1960fa0dc23af6a 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02" CONFIG_IDENT_STRING="\nPogo E02" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -20,6 +22,8 @@ CONFIG_BOOTCOMMAND="setenv bootargs $(bootargs_console); run bootcmd_usb; bootm CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="PogoE02> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1050 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_USB=y @@ -31,6 +35,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index ca27bbba67a4ae12f940720c807e111f98320049..c62c88f1b5ac3b83af7978906302642d37cd28fb 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4" CONFIG_IDENT_STRING="\nPogoplug V4" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_BOOTSTAGE=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=10 @@ -22,6 +24,8 @@ CONFIG_USE_PREBOOT=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Pogo_V4> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set @@ -60,6 +64,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MVEBU_MMC=y diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 17fffeb1e26abebbe9180f9977afe820a3e84c86..74ffaf1d01178e5e7425c6365093d3f65a1951e7 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index e542b71113258a6c4d16a4b4e3a91dac305a7611..10057ade9a5ae7e9da64aedde474a9d7b4fcbe37 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 94bb34a3a75b93f912ecce9180eddc8c7b8dd7a3..16f6215148c8a4d34777b87820dc0ae2084f892c 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -13,9 +13,14 @@ CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb" CONFIG_TARGET_POLEG=y CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_ENV_ADDR=0x80100000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7f10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" CONFIG_SYS_PROMPT="U-Boot>" +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=280 CONFIG_CMD_GPIO=y CONFIG_CMD_SPI=y CONFIG_CMD_CACHE=y diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig index 5dcd1e57761aa5ef779ae2b48023598a6c5fc1b7..515624fd42e97928266cd59ea3ecd70b31f6f2d3 100644 --- a/configs/pomelo_defconfig +++ b/configs/pomelo_defconfig @@ -8,12 +8,17 @@ CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_SYS_PCI_64BIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2981a000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="pomelo#" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=280 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig index 5d2639f71bdf181c3c1973d945858b6bc646a003..85ff6bd07cb8ffd47911bd5cb149091f2e01a67d 100644 --- a/configs/poplar_defconfig +++ b/configs/poplar_defconfig @@ -10,8 +10,13 @@ CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar" CONFIG_IDENT_STRING="poplar" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200000 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="poplar# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=537 CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_ISO_PARTITION is not set diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index cb463a9b69aade6c332d71b624c63916c06794af..7b024437c2ba9112d2a5b613a455c1ea633f8b5c 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -15,14 +15,21 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 05f85d33b64b499da05ac0fbec59dcd200011aa9..568ec18049d9b125bdd4e6e931ab122e46846671 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index a62c9f8fa37f7603238b3196775b675ba708441e..523de63fc27a3bff6f67bf08632dc5f3bf09d2fc 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,7 +14,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 7ce2dc07192d1a434a1eae8562925a8276e03c2d..f902f144f28a72fa69a2013fc2d9aa0ec7d0c329 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -17,10 +17,19 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xff8e0000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff8effff CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 213d01fe7a8cbf8cebd4d092e82633462869ae85..7a526b8c07fa0cf653b6b7fed1cb11e9cbe95ace 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -19,6 +19,8 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -29,12 +31,20 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_TPL_MAX_SIZE=0x20000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 875d7aa7de337c0520d9f067fa365dc312411f61..c836c7cb957ac0ec6fc9b253bcedbccef3e9bde3 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -19,6 +19,8 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -29,12 +31,20 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_TPL_MAX_SIZE=0x20000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 4e2fa8cf7dc87009b5ed2cc742ae66693bed9a10..33529900b000bdb3d0aba89f37578c9c8cfd827f 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -19,6 +19,8 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -29,12 +31,20 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_TPL_MAX_SIZE=0x20000 # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index c2051615cbbc3d93626554b485cfaed81012afa9..8dfd51e25b8517368bb3048b3ac929bdc42dc149 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -22,6 +22,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -34,6 +36,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -45,6 +51,8 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index f269b8a588950f3619819277e2aef20707d23f29..83981d3ac7498d28abf6e1c14cdcd9c37bcbc573 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,7 +15,9 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index dda1a0c51f6e96725e038641b7fe15ef4120c5f7..11d208a34a050e315b6390c7e06726ee4c06c0b7 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 7925677d30e26f73040927542f4d633c1d4318a1..c848e62d73c92c90547fd5f0ca85c43d3bc3ad7f 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index f3335f9d233e0b219f52f9c03255ce27a7bcd754..ee5654185b169fceb020a3f51fd3c1cf8082dc60 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -16,6 +16,8 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index eac2cc2854dbe62bae91fdfc70ae8ba08379940b..034f7e6935b8919367084d02d343a06f53ace3a3 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -1,21 +1,24 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xf01000 +CONFIG_SYS_TEXT_BASE=0xf00000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500" CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_QEMU_PPCE500=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_MONITOR_BASE=0x00F01000 +CONFIG_SYS_MONITOR_BASE=0x00F00000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_REGINFO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y @@ -38,6 +41,7 @@ CONFIG_DM=y CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_BLK=y CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_LBA48=y CONFIG_CHIP_SELECTS_PER_CTRL=0 CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 91b5c9a3b8021df5f16c6e15467bf148182c4a0f..9634d7f77f1102dac6b9009352994174a3807848 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -6,9 +6,14 @@ CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 5a135f8624cdd2b755bc41aeb0ef15939fb4aa0f..1c5a0617aa8d71d9e43502ea5ab1e8ca0b57c929 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -7,9 +7,14 @@ CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 410aecf2162654de69b56a5d22edd514d55cea81..2421c9a371943d80340e41eed72f73fb0b71a9b9 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -9,10 +9,18 @@ CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y # CONFIG_OF_BOARD_FIXUP is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index f7b9de10875fb43e57438d15cc9bc88b77b6e217..d5eae95c80fd03d03918fd9d363069059302b4ca 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -7,9 +7,14 @@ CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 4d83570c455df8ea7979d357c0548085f250015c..2861d07f97e7f9bbb0c158c820904c1ca39d0c2c 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -8,11 +8,16 @@ CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index e19273e79cdb05525c92ee96b8fdb2e5d1200236..1ecfa27ce29a0040a7ae528417f84d9d7ab78fe3 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -9,10 +9,18 @@ CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index cc8393e6b98e0577c85d86e994966e329db33cfb..b81e60658fd841fc56164ad42c141c383f9d25c4 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y @@ -38,6 +39,7 @@ CONFIG_SPL_NET=y CONFIG_SPL_PCI=y CONFIG_SPL_PCH=y CONFIG_SPL_RTC=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y @@ -63,6 +65,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 6010b61d2df7b8539e7e70c8c6e3f14958f9659b..c65b5868cd2954c931c57b7172783cb85fc6b194 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y @@ -45,6 +46,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPI=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 8d5c5751961910f03d090a0b5c9cdcc164e00846..f7c93ba2af543dd9be98a0307ba914202e281f06 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -8,11 +8,14 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64" CONFIG_DEBUG_UART_BASE=0x9000000 CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40200000 CONFIG_ENV_ADDR=0x4000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -22,6 +25,8 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_PCI_INIT_R=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 3b019e4bbe9957e964ed4e835fec5f2ed483b549..50945472315ac659ec631a1186e563ae045c880e 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -15,6 +15,8 @@ CONFIG_ENV_ADDR=0x4000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -24,6 +26,9 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_PCI_INIT_R=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 40617089ee79975849f2a52f856a52f3814d4523..2beda3a2fe0a61a7e90c09a61dc1c3c8490260f9 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -17,6 +17,8 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum" CONFIG_DISPLAY_BOARDINFO=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_IDE=y @@ -50,6 +52,7 @@ CONFIG_PCNET=y CONFIG_RTL8139=y CONFIG_TULIP=y CONFIG_PCI=y +CONFIG_SH7751_PCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SERIAL_RX_BUFFER=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 8875a09b2c98c5ded62c62a7f5173bd7d101c584..f5adbd3686cbbf55092c7e72eeece9338516db08 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,7 +6,9 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 7b050d824573740dc78ef8e924f6cc2adb912688..9ca3ddf27b79994ae96529e49cedd3108fa8e100 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -21,7 +21,15 @@ CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77970-eagle.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index c3b6e99ae77b4acab0496fd731a63a000b046c0d..ef59b9c778529504860f15028e031bb630b9cc39 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -22,7 +22,15 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77980-condor.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index fba03a760fc91174dcd13df4c7202e5e0e133411..e667d23d7eea61824a207bac5d8e0d135b7197eb 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -22,8 +22,16 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77990-ebisu.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_UPDATE_TFTP=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y @@ -69,6 +77,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 008254715e2f0dbf6ffc6d067f8c99be962d0dec..afccf86461df40974c5e71d0957b30a42d3e0a10 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -21,8 +21,16 @@ CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77995-draak.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_UPDATE_TFTP=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y @@ -63,6 +71,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index f76b1132a8e75600e79df0398c5dfb65feff15e4..72c31ac3a1948c1ef618f87df8a6c837d0583f2d 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -24,7 +24,15 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a779a0-falcon.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig index 5e845600b46819976f75f228cb5299eb343d36f3..95f7f42911153f4cb767f6a84386d65e80e30ae2 100644 --- a/configs/radxa-zero_defconfig +++ b/configs/radxa-zero_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" radxa-zero" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 4bdaae0bc6384ddb9afa122345d6b806d4f55719..373bca678ddac68407d0b37f9ab1ae8e3c9c1fbb 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -34,6 +36,10 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -46,6 +52,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -71,6 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 6ef62ab4cbba2bae912bc976d614b05a38ea4917..d423ad7b82615f484e1a9434bc904baf71a1c70a 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -21,8 +21,16 @@ CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-salvator-x.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_UPDATE_TFTP=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe633f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y @@ -72,6 +80,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index a7ef4f1c0eec2a51b233af4895a66b86cfd3ae24..341abe4f6dda44d46b9110a63cbc551986d904b1 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -21,8 +21,16 @@ CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77950-ulcb.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_UPDATE_TFTP=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe633f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y @@ -71,6 +79,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index bdfe51cef81fed257f6cb1236fd01abb348863c2..a2ef6187f827fd2807aeee5facf9826c1cecf107 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -28,10 +28,14 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" +CONFIG_SPL_FS_LOAD_ARGS_NAME="imx6dl-riotboard.dtb" CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_FALCON_BOOT_MMCSD=y -CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x0 +CONFIG_SYS_SPL_ARGS_ADDR=0x13000000 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 0ae45ca8a197010f76e20e4232f2382c5d2a4267..325b7cb182b00be1999c43a93c8e8415d7c8ac64 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -16,12 +16,21 @@ CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 5fc4dd7794347700e2e1a2446afbfbea1d268d2a..43b90c7879b7a8f5d046452779fbe8eb6497578a 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -26,13 +28,21 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -98,6 +108,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index fd857ed0ffd3236b2920aa510b3185e289255afb..f537a605e1aa0e775ad0cda985577676c65fa00b 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -17,10 +17,19 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 4684fa6e7471821f9eff965c073bb164330db47b..a502e549fb390e2f77c694afc4adec100c2010fc 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -17,10 +17,19 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 80d1e63b59c80475a48b47df8e11fa65ef9128c2..cf2e9fbde389cf143a1692ae3565c0cffc12881d 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -12,11 +12,20 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index bda4b70dbf9bddef1fe5e52c6769a104f9199978..fd5b25d77b40ee6cc30c74c750565166e1f6acba 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -12,11 +12,20 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 36038d9053093bb1bd2577d3921573739b714907..7d95e171f7f4d6245a22008b90c977f3e2e9b660 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -18,6 +18,8 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -27,14 +29,22 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_TPL_DRIVERS_MISC=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -99,6 +109,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 7151da4c19104c580da4a3642124564640f9dfa4..e63a77a25376909d4fd134ced227095c542a20bf 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -13,12 +13,21 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 6d13e351ee6e5dc8af6415df111476824d9b0799..87b050f5dc84deaae3f46cd52168d5c50842b542 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -16,12 +16,19 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index e8d183cd9b6f02e0d6029880da7d311b4a610f16..dcececdc315c878654ec645242e5ba0cf6a5aec3 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -15,14 +15,21 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index ea61fe738f2fc6a3e2a98d0543e3d8acd39fd698..bc333a5e2a6a1c89a355a32730328bf135e687f4 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y @@ -26,13 +28,21 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_TPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_TPL_MAX_SIZE=0x40000 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -96,6 +106,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index be0e1c7d186531ee6f131b3a92cb5cf2bbaf1af4..bb5b2143691dee4ff9f45c9be0770963b970fc33 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -11,15 +11,25 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_SYS_PROMPT="rock960 => " +CONFIG_SYS_PBSIZE=1052 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -64,6 +74,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 4aa4608f9042ef58e9c1fb64fe8417d30029e3bb..e99272ef2268a380f9593b7435a5d0800e410ad4 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -18,10 +18,17 @@ CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x7800 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x10087fff CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_RANDOM_UUID=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index b0c3527fab0bd7eb42956940edb8970273f5f1ca..72a5b78d792f540a5be73c8d183aaab49e92ab62 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -15,11 +15,20 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y @@ -80,6 +89,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 2e4a0df39bd31b720dfa5b1b32681dd1f8efb750..504f475b0345ab5dfaa9adede59343da8e6f09ab 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff00 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -16,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 7b78e84ba327c43cf822704ca56a870427edd96a..9e5d97a226904b31a53d570cb4e5475e02e2c29f 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff00 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -17,6 +19,7 @@ CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index c1d5538810112c39f229299839acb6cbf9a9da6b..1fc95365dfb847f003c0ce598a04dd64e113e336 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff00 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -16,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index f935e678780e817efcbdc2557af31462766f9634..a1f9ba78aaa2754472d4a7629734a93807c92a65 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -8,6 +8,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe40 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -15,6 +17,7 @@ CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 9e4e168ef045f294c1496bcbe1ee28e8b77bf03b..770d496dc6bae42a1b1c38721926dc9bff711517 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -8,6 +8,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe40 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -15,6 +17,7 @@ CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index a699591ceec80fff22d1a234d893263aebdf2eb4..aed6e5254742f703440bd5a7e061f3a4f044deb3 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -6,6 +6,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffee0 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" @@ -14,6 +16,7 @@ CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index eae03bf023caea222b098d41581006e4cd0d7b88..6637505697346b453aaeeba0ce276aed9eb573ff 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -6,6 +6,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe30 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" @@ -14,6 +16,7 @@ CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 933e142206534c60b3d8b67e19a9daade318375b..16f64eb54082085d428b8286010a488317475bc5 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -6,6 +6,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe30 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" @@ -14,6 +16,7 @@ CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 0fe4ec4cf40d5fcc756dcac6c17c527e2e9e5f19..00745c2a1ea376587bdd0b11d8bcfd986c04748d 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -9,6 +9,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff00 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -16,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index b1fde88303fc5677f8aaad56c68bfbdc81aea67d..1b91d8b5ab8da33b5a2da07e947e43233097b878 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -22,6 +22,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -34,6 +36,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -45,6 +51,8 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_ASKENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 6c8a94a06bceb57482bdb14ffa88929dd1db1dd2..1451a40dd9331aae13a7b3879d7097b618ed73a2 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -19,7 +19,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig index 1cebca67793ff92d5f46c7dd6ab0f98d6f0c12fe..ee855aa4b49ef0d95a5cbcde27d5b8d0f1696edc 100644 --- a/configs/s400_defconfig +++ b/configs/s400_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" s400" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index 4d571acd870574410cade6f17371c75b3e0254d6..e6e2d3eedbee367b68c0a2e42d3c4d0b2680f3fc 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -18,6 +18,8 @@ CONFIG_ROOT_PART=2 CONFIG_SYS_LOAD_ADDR=0x71080000 CONFIG_SYS_MEMTEST_START=0x71000000 CONFIG_SYS_MEMTEST_END=0xb0000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x74c00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SUPPORT_RAW_INITRD=y @@ -27,6 +29,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nanopi2# " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_RTEMS is not set diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 5c39c1d6bbe553fc2e1077e633afa840ade21556..05335d2c2b6071bef5ca82d0e38ad2af4522b0db 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -11,6 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" CONFIG_TARGET_S5P_GONI=y CONFIG_SYS_LOAD_ADDR=0x34000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x33000000 # CONFIG_AUTOBOOT is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}" @@ -21,6 +23,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="Goni # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=384 # CONFIG_CMD_XIMG is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y @@ -28,6 +32,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_ONENAND=y +CONFIG_USE_ONENAND_BOARD_INIT=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -46,6 +51,7 @@ CONFIG_DM_I2C_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y +CONFIG_SAMSUNG_ONENAND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX8998=y CONFIG_USB=y @@ -54,5 +60,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index e7bd1ae047e59df6ff4c602ecc630adc72b14202..cab0ac8e845ba78d857d2b54937e423d69c4391f 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -15,6 +15,8 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210" CONFIG_SYS_MEM_TOP_HIDE=0x100000 CONFIG_SYS_LOAD_ADDR=0x44800000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x447fff10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="Please use defined boot" CONFIG_BOOTCOMMAND="run mmcboot" @@ -22,6 +24,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="Universal # " +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_XIMG is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y @@ -46,6 +49,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y +CONFIG_SAMSUNG_ONENAND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX8998=y CONFIG_SOFT_SPI=y @@ -55,5 +59,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index c06ff632b4051cd454c489eb299ff9fc1785f2f0..875ae210de408c42633340f64e5673b4427dc4e7 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -16,8 +16,12 @@ CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="F@ST1704 # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=540 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/sam9x60_curiosity_mmc_defconfig b/configs/sam9x60_curiosity_mmc_defconfig index dd884bf8aa6477f31f0af02975c9352f747e1257..5a58d8486ff008ce378c086361f2d24a1d8b7c4d 100644 --- a/configs/sam9x60_curiosity_mmc_defconfig +++ b/configs/sam9x60_curiosity_mmc_defconfig @@ -10,11 +10,13 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -27,6 +29,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index bc0164c38e4f75e7cb3221ae238fcd7964377c4d..c50aa6b5c5940175df0861d5ae73ca44e18644db 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -10,11 +10,13 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -27,6 +29,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y @@ -35,6 +39,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y @@ -67,6 +72,13 @@ CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=8 CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y @@ -75,6 +87,9 @@ CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_AT91=y CONFIG_TIMER=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index 5c34f089e67a8b7e0b12785355e6d2e993558247..d8d2383fede2e8f11f73d02e2404054b2cd2cedf 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -9,12 +9,14 @@ CONFIG_ATMEL_LEGACY=y CONFIG_NR_DRAM_BANKS=8 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -27,6 +29,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y @@ -36,6 +40,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y @@ -68,6 +73,14 @@ CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=8 CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y @@ -76,6 +89,9 @@ CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_AT91=y CONFIG_TIMER=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index 1a64b2948f5ad594e10a8b8779854bbd36dbb234..fc4108cdc4721aba07d9e5fb8bd462f94110433c 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -10,12 +10,14 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -28,6 +30,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 CONFIG_CMD_BOOTZ=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig index 4977189716fecbd1d3cf863545629e7dee0e56f4..df5be2357ec7460c530b8fd383c1c6d3a1b352a8 100644 --- a/configs/sama5d27_giantboard_defconfig +++ b/configs/sama5d27_giantboard_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -36,7 +38,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0 0x22000000 at91-sama5d27_giantboard.dtb; fatload mmc 0 0x23000000 zImage; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 3e8c7b5d11220400c9cf575177b54cac3b4890d6..d15bd6b0804147cd5a645ef5b7dd9ccea1588a33 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -15,14 +15,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -32,7 +34,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 1 0x22000000 at91-sama5d27_som1_ek.dtb; fatload mmc 1 0x23000000 zImage; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 4a9a1f9bdf607c225c3f43853867ec00bbf79a03..c8a1271bef0036f10708e06679fda9c287cdc6a4 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -33,7 +35,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0 0x22000000 at91-sama5d27_som1_ek.dtb; fatload mmc 0 0x23000000 zImage; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index a20272fe427a7299f42873526eff62bf542cf909..f10973c9d6d04caaaab6ed08247c483f2f9ded61 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -31,7 +33,17 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 05a2e412a6d8c693bb6fcc9ed3e66e0ac5cb9bc2..fae4f77387c6e406f840d9bc3f9a6bfc021e8acd 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -14,14 +14,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -32,10 +34,20 @@ CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_ # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 691b0c21fc00b421f5da3f14cfdfb990308ff8ec..5dac554b9ce409d0ca33e90512a11e2346a0b0bb 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -14,14 +14,16 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_SPI_BOOT=y @@ -32,6 +34,14 @@ CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x220 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DM_SPI_FLASH=y @@ -39,6 +49,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index bb70c10e25612bb55b0b246f1bb7b6c7be0de922..86a49a1acfd1cec33f59be547c67219499cd96c2 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -14,14 +14,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -31,12 +33,22 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_DM=y @@ -44,6 +56,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_PING=y @@ -71,6 +84,15 @@ CONFIG_SYS_I2C_AT91=y CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SF_DEFAULT_SPEED=66000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -79,6 +101,9 @@ CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_AT91=y diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig index 715691844f60fe02555555ecf8177500678ccc57..27bd05f960129cae15ddd9420134e36ff30d896a 100644 --- a/configs/sama5d2_icp_qspiflash_defconfig +++ b/configs/sama5d2_icp_qspiflash_defconfig @@ -6,9 +6,9 @@ CONFIG_TARGET_SAMA5D2_ICP=y CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x20000000 @@ -16,6 +16,8 @@ CONFIG_SYS_MEMTEST_END=0x40000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_SYS_BOOT_GET_CMDLINE=y CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y @@ -27,6 +29,8 @@ CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; fatload mmc CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CONFIG=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 542d667d7e27b91fec30669b399f70c5dd9d694d..d7c85445db3358d39cb954f0c1bda3e6393ab444 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -8,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -25,6 +27,8 @@ CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index e1887e14b19a98d03c919caf3ba059f784210b2b..9f72648283bdb6b2e6dcf105a1ec04ad9923fda4 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -7,13 +7,15 @@ CONFIG_TARGET_SAMA5D2_PTC_EK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -25,6 +27,8 @@ CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index 081f5f9d9c6ad958c006245b2bf2c10f965bb6f1..0c8a90d62ddf604109f57069614f2cdc5b00001f 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -15,14 +15,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -31,7 +33,17 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwai CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x22000000 at91-sama5d2_xplained.dtb; fatload mmc 0:1 0x23000000 zImage; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 255fb0fa7d5d858ef88794222659ec33d9e50377..e6722e2133e65b7c825028532635163e0b6c229d 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -33,7 +35,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x22000000 at91-sama5d2_xplained.dtb; fatload mmc 1:1 0x23000000 zImage; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 5bd4d69332caf3c5ba2e56a2262da112060ba8ca..b7e93d1846c81de87f3feab88d26dc6236525e07 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y @@ -34,7 +36,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 1:0; sf read 0x22000000 0x180000 0x80000; sf read 0x23000000 0x200000 0x600000; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index b1c27e98518a16c549cba59922f387b28bdb0b2b..2ebe8d96499b4197922f3be88dc8999f41e297ec 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -18,14 +18,16 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -35,10 +37,20 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; ext4load mmc 0:1 0x23000000 /boot/zImage; bootz 0x23000000 - 0x22000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 256ab76b0766205a05d661451663c452becec190..e5794f37013a3870b1de027426a2bf0bfabbb5d6 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -8,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -25,6 +27,8 @@ CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_ CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index d89b539ccf5f6283593d3f522bccc23669f5650a..2fd58b07bd1edaf143e19ebf62d14f2fae213e16 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -7,13 +7,15 @@ CONFIG_TARGET_SAMA5D3XEK=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -25,6 +27,8 @@ CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set @@ -49,11 +53,9 @@ CONFIG_AT91_GPIO=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 9fbed91b845e160c9a21766ac2b1c52911bb5f41..8541deeb2c853ba4274d01f1e696eb3c2e706c22 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -10,12 +10,14 @@ CONFIG_ENV_OFFSET=0x6000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -27,6 +29,8 @@ CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x220 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index b9b938bab772d11dc8df2b699a55d02a2b9a676d..486e2190b2b332344669204dd698fecfe328ee78 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -32,7 +34,17 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwai CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x318000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set @@ -92,6 +104,9 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_SPL_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y +CONFIG_USB_ATMEL_CLK_SEL_UPLL=y CONFIG_USB_STORAGE=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index d8dd849dc0dea2a30b143b3d956ec502f4521bcc..184ff5ff724891a2ffd4ca8f12bdac6c61a6f45e 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -14,13 +14,15 @@ CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -29,10 +31,20 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x318000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set @@ -95,6 +107,9 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_SPL_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y +CONFIG_USB_ATMEL_CLK_SEL_UPLL=y CONFIG_USB_STORAGE=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 2dbf9abf4cdf276b55d8a9b9f4cb6cfdceaa9d29..40a8c028c2dc7256a4fc4a5f31650c4bce083e7d 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -34,7 +36,17 @@ CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_ # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x318000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_IMLS=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 27ab84c3a3744d8941234de75c87610ba549e0c3..772511543dbf0cdf885256ed4d5d3f6bb640e5a4 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -14,13 +14,15 @@ CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -31,10 +33,20 @@ CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x318000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_IMLS=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 6a4230207debc03b538b665311f906245a985404..4e85807432e5d9a13cf36b7c085df54522ea24f8 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -18,14 +18,16 @@ CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -34,10 +36,20 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x318000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index c217d6d439b6fd7e39589f9bbceeb5c771a05982..84c53ce65301b038714ed0390a7e20b494864d0c 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -33,7 +35,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_name}.dtb; fi; fatload mmc 0:1 0x21000000 ${dtb_name}; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 5c62a7f6aeeaa9381a2ca0cbc877723fd07c74d0..6481be4bb969a12e67c2f9d1b2649b75542634e1 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -14,13 +14,15 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -30,10 +32,20 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0x200000 0x600000;bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 60bd2eb8f1ba55f64faf6674b46e93c652fa1995..131982d1dffa2e0e6e4a51eff310ed8c61f3a8ae 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -18,14 +18,16 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -35,10 +37,20 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index c36175c8cec00aae344a507687981868015f4176..e1c0582054f9f210048e33ffe2949b9d146ff41d 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -16,14 +16,16 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -34,7 +36,17 @@ CONFIG_BOOTCOMMAND="if test ! -n ${dtb_name}; then setenv dtb_name at91-${board_ # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 7c544017cfec72d6616146c1fb9d596ca6ab50db..8e934ff44bbc21dd0e4b418449be3adf1e3181c5 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -14,13 +14,15 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -31,10 +33,20 @@ CONFIG_BOOTCOMMAND="nand read 0x21000000 0x180000 0x80000;nand read 0x22000000 0 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 0b86976df9eb4b48db2eade9bc1d387d428c6703..c3fbaccc11187cb7e6c5394dec8feb5d543e52b4 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -18,14 +18,16 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -34,10 +36,20 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x21000000 0x60000 0xc000; sf read 0x22000000 0x6c000 0x394000; bootz 0x22000000 - 0x21000000" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_MAX_SIZE=0x18000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x218000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index 42d96f7c022e2e9abb296eb319f0341556b937d8..860362e158977711d3e649516687fa29a4e9a677 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -7,14 +7,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60014ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y @@ -23,7 +25,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMTEST=y @@ -76,4 +81,3 @@ CONFIG_TIMER=y CONFIG_MCHP_PIT64B_TIMER=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER_HII is not set -CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index e03a6ba9af4d52042beee60977c560b3ab3f41fa..bc2852f0916ff1b8028e60d4b2634bc280f19c3b 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -7,14 +7,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek" -CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60014ef0 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y @@ -23,7 +25,10 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMTEST=y @@ -76,4 +81,3 @@ CONFIG_TIMER=y CONFIG_MCHP_PIT64B_TIMER=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER_HII is not set -CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index d7f22b39ae512703f10a57f13c64c51f09484670..6553568e768431564d6772b75474ccc0f3d4f7cc 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_LOADM=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y @@ -133,7 +134,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y @@ -144,6 +144,7 @@ CONFIG_LED_GPIO=y CONFIG_DM_MAILBOX=y CONFIG_SANDBOX_MBOX=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y @@ -151,7 +152,6 @@ CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y CONFIG_P2SB=y CONFIG_PWRSEQ=y -CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y CONFIG_MMC_SANDBOX=y CONFIG_MTD=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index c509a924e6b3e0afd4b4c93bf1ad1d52f00b8ecc..572cf8edd8b0a63d3b2fff148c0dbe5eb6c7f95f 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -67,6 +67,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_LOADM=y CONFIG_CMD_LSBLK=y CONFIG_CMD_MUX=y CONFIG_CMD_OSD=y @@ -177,7 +178,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y @@ -188,6 +188,7 @@ CONFIG_LED_GPIO=y CONFIG_DM_MAILBOX=y CONFIG_SANDBOX_MBOX=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y @@ -195,7 +196,6 @@ CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y CONFIG_P2SB=y CONFIG_PWRSEQ=y -CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y CONFIG_MMC_PCI=y CONFIG_MMC_SANDBOX=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 80a4be47eba40605a0b4175231c2c53e35b499d2..a71ce77c4031a57a359cbe2fbaedf164942610de 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -106,7 +106,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y @@ -117,6 +116,7 @@ CONFIG_LED_GPIO=y CONFIG_DM_MAILBOX=y CONFIG_SANDBOX_MBOX=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y @@ -124,7 +124,6 @@ CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y CONFIG_P2SB=y CONFIG_PWRSEQ=y -CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y CONFIG_MMC_SANDBOX=y CONFIG_SPI_FLASH_SANDBOX=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index c9430da0f09e533be0125a8e857acd1b5883f551..9ee70c29c1a53c55fc75fa6c71985419697b47bf 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -29,6 +29,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y @@ -143,6 +144,7 @@ CONFIG_LED_GPIO=y CONFIG_DM_MAILBOX=y CONFIG_SANDBOX_MBOX=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 13a76e89ea52a62da64e6bcd2dbb1134224269e6..ec2d26d4436b7e5767ef2f0dbdff246d35ef17a2 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -29,6 +29,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y @@ -144,6 +145,8 @@ CONFIG_LED_GPIO=y CONFIG_DM_MAILBOX=y CONFIG_SANDBOX_MBOX=y CONFIG_MISC=y +CONFIG_NVMEM=y +CONFIG_SPL_NVMEM=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y @@ -152,6 +155,7 @@ CONFIG_CROS_EC_SPI=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_SANDBOX=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index e4ec16b3c922c4d4ebbf7b010b06a44d7aae2478..0d946b4ad779078934131b866f8b14220d8c72fc 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -33,13 +33,14 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_RTC=y CONFIG_TPL=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index f3d3b0a498021debb77c92ef1ecb8ad440ddb5a0..f9864febcb0ec69fb47b4e7185cdb09b716f438c 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -12,7 +12,17 @@ CONFIG_TARGET_SEABOARD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2086 # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index 4cf79c5b7ee6e0cf4805dde31b148ff6715f9596..e12a7d850606a3bd6604d8c327a0e5bd9ad65ca6 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -20,11 +20,14 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index e9f5781248fe430d9cf975e320fc8a820022705e..79a215fe9e8df687f13c46b464d7427814645eaf 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -16,6 +16,8 @@ CONFIG_IDENT_STRING=" sei510" # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y @@ -24,6 +26,7 @@ CONFIG_PREBOOT="run load_logo" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_AVB_VERIFY=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 93b9008383deaece92a9395f1852b8a34fad5eb6..a5b28c2774547f86e5449ed06763d7c4abc33777 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -16,6 +16,8 @@ CONFIG_IDENT_STRING=" sei610" # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y @@ -24,6 +26,7 @@ CONFIG_PREBOOT="run load_logo" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_AVB_VERIFY=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 8ff982bd78af4f21efed2e61d2c6ff847f5ff8b3..df008b797f869af3aaf2b74c951d965e7317544a 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -18,8 +18,12 @@ CONFIG_MIPS_BOOT_FDT=y CONFIG_REMAKE_ELF=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="NB4-SER # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=539 CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_BOOTD is not set @@ -67,3 +71,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 80f599d3a395cf5219f3c9e3d00dffefc2ecd7ec..06dacef8a7daae5f73788f754aac0c4294306142 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1b0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 0477cd79e3e5887c8fa65341ef8dc6f01b53479e..fa1e7bd2c0cb57559ffcea29db0ca8f3130d7276 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 @@ -22,6 +24,7 @@ CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_boota CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -50,6 +53,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_MVEBU_MMC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index fe2227e596b4c6e8ea959443be40656141696266..99faabaa2ff29577292d9e43f9eb6517f75271a1 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -14,6 +14,8 @@ CONFIG_TARGET_SIFIVE_UNLEASHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_USE_PREBOOT=y @@ -22,9 +24,17 @@ CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x85000000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x81cfe70 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 5d070843bc05ca199d046d7fdec4c2bde3abb6a3..c390af26897fb53c582649430cbc774075559dec 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -17,6 +17,8 @@ CONFIG_TARGET_SIFIVE_UNMATCHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_USE_PREBOOT=y @@ -26,9 +28,17 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ID_EEPROM=y +CONFIG_SPL_MAX_SIZE=0x100000 +CONFIG_SPL_BSS_START_ADDR=0x85000000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x81cfe60 +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 099a200539feaae4194c47e011882f7db9f2e9c0..24fcfae4ef2a7515045148963d3026edc009d1a1 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -23,7 +23,15 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774c0-ek874.dtb; booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6304000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 9ae358d97a78024d5be39c772d109fea846aa349..ac827ff2027ae1eafd21ca95ef3ce89278267e32 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 7d1722c88335c9cae518239773067dc1d406ceee..731665723a135bf130ab2dad779adcae6c9cde15 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -6,11 +6,15 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff CONFIG_STACK_SIZE=0x100000 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run k210_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" # CONFIG_NET is not set diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig index 0008f5cfa7efc1bc4f869f66c4329ead73833a0f..ab2b3532e6b845a2bb8d448182a53f4a85145774 100644 --- a/configs/sipeed_maix_smode_defconfig +++ b/configs/sipeed_maix_smode_defconfig @@ -8,10 +8,14 @@ CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff CONFIG_STACK_SIZE=0x100000 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run k210_bootcmd" CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" # CONFIG_NET is not set diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index 5988777fb90280cfbb8663dc02c7bf1bbb7cc240..b6b9f88c00bbaa7dc9a32b3d054d811f458faf04 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_BOOTP_BOOTFILESIZE=y @@ -27,6 +28,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set CONFIG_CONSOLE_SCROLL_LINES=5 # CONFIG_GZIP is not set diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 3cf30ddd766fe5cbf2f07de69bb9a290cd63b1d7..84337e49e6c9625f1f425ab3a018a66c3c67fa54 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -32,12 +32,26 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x1000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x301000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x460000 CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_SOFTECC=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=537 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y # CONFIG_CMD_LOADS is not set @@ -55,6 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 @@ -77,6 +92,8 @@ CONFIG_MACB=y CONFIG_RMII=y CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 31332af41d463ee30dcf5469e3b65e8f824f2057..cbbf13526c19d1d442c208aa8c6d93c3dd8edef0 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -20,12 +20,17 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" for SMDK5250" CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3800 CONFIG_SYS_PROMPT="SMDK5250 # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 7f2e42a3a52eb70511edabb098702cca1f4ac369..7cf2cd5b566db39a2acaa254e4f591bf2bc79fc4 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -18,12 +18,17 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" for SMDK5420" CONFIG_SYS_LOAD_ADDR=0x23e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2073800 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x7800 CONFIG_SYS_PROMPT="SMDK5420 # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 2fe065e9fc5cb7aa4cceb7da9d2f51dd0b06f851..ae5983e807ef8187800bf2c2ca1e32d16a7d61f8 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -12,6 +12,8 @@ CONFIG_IDENT_STRING=" for SMDKC100" CONFIG_SYS_CLK_FREQ=12000000 CONFIG_SYS_LOAD_ADDR=0x30000000 CONFIG_ENV_ADDR=0x40000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2f000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)" @@ -20,8 +22,11 @@ CONFIG_BOOTCOMMAND="run ubifsboot" CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="SMDKC100 # " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=384 # CONFIG_CMD_FLASH is not set CONFIG_CMD_ONENAND=y +CONFIG_USE_ONENAND_BOARD_INIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y @@ -32,5 +37,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_ONENAND=y # CONFIG_MMC is not set CONFIG_MTD=y +CONFIG_SAMSUNG_ONENAND=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x98800300 diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 55528cc5f8e3ed5cef2ca502a78debcf531271b6..17fc2c41e958b05af321e149996e085d36dee2dd 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -15,9 +15,14 @@ CONFIG_SPL=y CONFIG_IDENT_STRING=" for SMDKC210/V310" CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000 CONFIG_BOOTCOMMAND="fatload mmc 0 40007000 uImage; bootm 40007000" # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3800 CONFIG_SYS_PROMPT="SMDKV310 # " +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_XIMG is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index d5d1791d48f7441bda5bfd3113b1220f8253f701..25a75d1aa5ac18d8679c52416266d295c6cfa143 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -20,6 +20,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; " CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 4c93ba4e0576460f6dac0552fd63b21515763cb5..9fb55dc9af3651f676fcb626363326ea423d9461 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -20,6 +20,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 ip=any" CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Snapper> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 34f563c3ddf922a78ea3887d4852888c6acc1845..aa765c417793d35c65e42777937b778d64cf543f 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -19,6 +19,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 ip=any" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 6d63d30d52257ca343f48e3860126584671c393f..e2725f4a22f2bd9c90e86e9edf5221e818b803f4 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -9,14 +9,25 @@ CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_SNIPER=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SPL_MAX_SIZE=0xec00 +CONFIG_SPL_BSS_START_ADDR=0x80000000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4020fffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2 # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SYS_PROMPT="sniper # " +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=538 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index e7cf8d872227d225a772a4d2b2def9087639c23d..8d1b28dcf8c56a9c2868d0339f1cb853f65e8cc1 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -23,11 +23,16 @@ CONFIG_IDENT_STRING=" for snow" CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3800 CONFIG_SYS_PROMPT="snow # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -89,6 +94,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index f1ae3c3349df03dea53c910427884fc976130c75..bdfe764d9e41e4002e040d5598107b43ef3869be 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -14,6 +14,8 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_SYS_LOAD_ADDR=0x02000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -25,14 +27,28 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2082 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index bfbbd9bfdde84b5767e216a521122d04e1d707e6..e2d869610cf5798e6c18c82948a3e5b0fca2d872 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -16,17 +16,33 @@ CONFIG_SPL_FS_FAT=y CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x3fe00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000 CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2082 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index d29b51729ddbd50195bca41874837b59285bb7e1..6f15b3e9622a5271744519cdf0abae6809056838 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -15,6 +15,8 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_SYS_LOAD_ADDR=0x02000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -26,14 +28,28 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2082 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 1be9a2df083072c3fdb17ae0e225f432da7574f3..c98c106851fc36c955c517cd906f0c94884c90e4 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -11,6 +11,8 @@ CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y CONFIG_IDENT_STRING="socfpga_arria10" CONFIG_SPL_FS_FAT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000 CONFIG_FIT=y CONFIG_TIMESTAMP=y CONFIG_SPL_FIT=y @@ -24,8 +26,17 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe2b000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xffe2b000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x15000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FPGA=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index dafeafff3e732de4006bd1870c58f0e2054417cb..24c21090b1961ee9c191f38e6eaf20725eb8667a 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,8 +20,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index b09672d8a2f28707880a24d886e4871087e5f81b..d010b54240dd5b77a6a24cb7ce7434b46dbd3568 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,8 +20,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index a8ef2e934add2a4af2ed605636d69ce00bc027ef..a1574b6a5d7c5de25d0e5cf24c3a4c6006e31ee2 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -7,6 +7,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y CONFIG_USE_BOOTARGS=y @@ -21,9 +23,14 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 2e5bd80d2efbc2e771f12a2f339f350e1f8cfea0..ec7355d2cc432f16540230f5f6d40710b0e5c599 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,9 +20,14 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 95b4ef638ecfbb44181730af8090111a16aa455e..b62f029962878114dae40833bb63037ea6d84b08 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,8 +20,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index 91bd49840d8dc619f3029fc131fc3bfd78ce2f80..b8bc9da4d0e4fae80c0a813e3484baa99e47154d 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_standard" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_TERASIC_DE10_STANDARD=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,8 +20,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 75e16be42a9c5622f78c54a581bd1f467a71d482..749ec540b4fdc7225cdfa7c9884fbff5306e77e1 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,8 +20,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 53e9a7296cf9e0160500cdc860dadea995f04fc7..958adfe25a43893fb63cfc23997424d8258e4264 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_TARGET_SOCFPGA_IS1=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y CONFIG_USE_BOOTARGS=y @@ -21,8 +23,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffff8 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set @@ -45,6 +52,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=500 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 07ca4bf954b9b92a5908f60265ffd08f3dc4970f..18e125f5bdf9c1574d5dad7f14acf43fd75fabd9 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y CONFIG_USE_BOOTARGS=y @@ -19,8 +21,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 50b3319561e69f674e04113b5c9a5ecaa43719ee..37c843631881196a28b0ee2fbc11d1c829553ed5 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -13,6 +13,8 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" CONFIG_SPL_FS_FAT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -24,14 +26,28 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_N5X # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2079 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 8cdf65dbee16ac63bc7bbb6fd907c6e895d20cad..5f415b7ad4f9481501047a21459c0a5644495b0e 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -13,17 +13,33 @@ CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" CONFIG_SPL_FS_FAT=y # CONFIG_PSCI_RESET is not set +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000 CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_N5X # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2079 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 04942e4fd9d0889820843d6111035c9f9d5df987..a57d54a7f271971cae43a999f40412b8010f86ee 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -14,6 +14,8 @@ CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" CONFIG_SPL_FS_FAT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -25,14 +27,28 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_N5X # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2079 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 641d205093a9a9271fc48776d291203b98b62505..83e24402a887b3a7c2452bc9c9ef9f2a1b0dfc6f 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -16,6 +16,8 @@ CONFIG_ENV_OFFSET_REDUND=0x120000 CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_BOOT_RETRY=y CONFIG_BOOT_RETRY_TIME=45 @@ -31,11 +33,18 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index e245288b92a4c9b52ba61096697abafca4bdd52f..2a02f1dbfaa6021bf2f2255ab6b5bbf6563fa29a 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -18,8 +20,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 7044186469157324b1665fbe58ef2b67d971ea18..3d0c48d76623a1d10cad25963bb5778afe244639 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb" @@ -17,8 +19,13 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index b0be03395389bdbc252d8337010f66636f133e23..def2ee8dbc14b91a08d9cc59281b302c390c70da 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -13,6 +13,8 @@ CONFIG_ENV_OFFSET_REDUND=0xF0000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x40000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -25,8 +27,13 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffff8 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y @@ -49,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 6d2f4736c607e299b1e2ff6d5e51361a371b7876..6be4210c7d6ea87245a12156eabb37bfa0372edb 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -14,6 +14,8 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_SYS_LOAD_ADDR=0x02000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -25,13 +27,27 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2085 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 8e16c2bfbb33218934a34d624badea75e608b9c5..07e9f20a41a218c93a52a5f09cbcd3a568adfe22 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -18,16 +18,32 @@ CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_OPTIMIZE_INLINING=y CONFIG_SPL_OPTIMIZE_INLINING=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000 CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3ff00000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x3fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 +CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2085 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 331975ad30971d4178332290ccec765de26c2612..d0c87416efd076ffecec8a4bc5f3ba0f29f44de2 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y CONFIG_ENV_OFFSET_REDUND=0x110000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 CONFIG_FIT=y CONFIG_TIMESTAMP=y CONFIG_BOOTDELAY=5 @@ -25,9 +27,15 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CLOCKS=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x0 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMDLINE_PS_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 2abb81c53b49e2b2a88d43e0becc8275efd7bb21..60a38abc8e3a670f7318d913180281957e7072ba 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_ADDR=0xFFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y +CONFIG_ENABLE_36BIT_PHYS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -21,11 +22,13 @@ CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_REGINFO=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y @@ -94,4 +97,6 @@ CONFIG_USB=y # CONFIG_USB_EHCI_HCD is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_PCI=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y CONFIG_USB_STORAGE=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index fb630bddc79f4491eb0e28e613136a1f02c2e489..d912ac70bc186262da374987598680e08124d7b8 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y @@ -55,6 +56,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y CONFIG_SPI=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 33b1791213570d9b235be18c148c8b04af07b7e6..b99266fec74a225b021599b3dc250104127932bd 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run setfdtfile; run checkbootdev; run loadfdt;if run loadbootscript; then run bootscript; else if run loadimage; then run setbootargs; bootz ${loadaddr} - ${fdt_addr}; fi; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index fbbef7a9f9ad4a9fb2b8917992ca40e343547261..55116f72d0d3ff8e7cada2d9323b9ac720400054 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -11,6 +11,9 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 8f4a8a1e5d0b2cbdc06ddec9404ece04ca22afcc..366790b4efe49f2e0433276399de2323a6e1c2dd 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -23,11 +23,16 @@ CONFIG_IDENT_STRING=" for spring" CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2050000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y # CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3800 CONFIG_SYS_PROMPT="spring # " +CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -90,6 +95,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_LCD=y diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig index 608d001b6df5873352f42b15a4899f9a95a97bf2..2d07767b61bbf04b08d1fb1e9c1c61dadd00d48c 100644 --- a/configs/starqltechn_defconfig +++ b/configs/starqltechn_defconfig @@ -14,6 +14,9 @@ CONFIG_SAVE_PREV_BL_FDT_ADDR=y CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_BMP=y # CONFIG_NET is not set diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig index f49f970bec71b9790d6ef6f17e44ccdeeb1d18bc..7fc0a39872c9c63c2c3e157693691fc38eb64fa5 100644 --- a/configs/stemmy_defconfig +++ b/configs/stemmy_defconfig @@ -10,13 +10,18 @@ CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy" CONFIG_SYS_LOAD_ADDR=0x100000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run fastbootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CONFIG=y CONFIG_CMD_LICENSE=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 642c199c5cb91889d67b236645a0e195868cdd9b..c9be056cf6249fbb262e81a7daf8a55b061e5158 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -10,12 +10,16 @@ CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260" CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260" CONFIG_SYS_LOAD_ADDR=0x40000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7bdfff10 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait mem=992M@0x40000000 vmalloc=256m" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="stih410-b2260 => " +CONFIG_SYS_PBSIZE=1058 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -55,6 +59,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index b2820149a32d8bf4a2578d7495009299b4c547fd..64610658c7bda953cfbbe4b0b584ad1eaeecd29e 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -10,6 +10,8 @@ CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -19,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y @@ -45,6 +48,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPI=y diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 6ec0b3cf599ded1fa9cdcdb954c0334145b618d4..753a4b80cbbc12d29656e4b474f2fa24ca07b3cf 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -26,12 +28,16 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_XIP_SUPPORT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000 CONFIG_SPL_DM_RESET=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y @@ -63,6 +69,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index c48052ab13a1c251493e0f2a2f5371e2479e0c78..fde427ae692f04c02cfc1797cceb7fd267c81138 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -12,6 +12,8 @@ CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_SYS_LOAD_ADDR=0x90400000 CONFIG_ENV_ADDR=0x8040000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" @@ -20,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIMER=y diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index 2217584a3c762dbcd9c981cb4650060179736650..e2c41b0844e8140cb12fdda9c0262d14ec8e6c5f 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -10,10 +10,13 @@ CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_EVALUATION=y CONFIG_SYS_LOAD_ADDR=0x400000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000 CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_IMLS=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 8af71302b2503818d30f66680c42e252a38f1c51..c7dbc69fa889479f66207a14875e0481358a2b63 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -10,10 +10,13 @@ CONFIG_STM32F4=y CONFIG_TARGET_STM32F469_DISCOVERY=y CONFIG_SYS_LOAD_ADDR=0x400000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000 CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_IMLS=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 64d7d18a69a39305ec08dff73b91adb9ced6cc57..e3f80ab8e2069ea605e936f5c28408e4e787cb6a 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -10,6 +10,8 @@ CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -19,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y @@ -45,6 +48,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPI=y diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index c417a4ff75b9f811e300c3e4cca43fdf2571e8e8..927d28dd9733b99d5507a17ff0a6293107373626 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -26,12 +28,16 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_XIP_SUPPORT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000 CONFIG_SPL_DM_RESET=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y @@ -63,6 +69,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 89fac36e707829ec740bf2f3eeac59e317ae73eb..b7e9ee92a7e1ba44643188a1b18f87816c0e7619 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -10,6 +10,8 @@ CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -18,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y @@ -44,6 +47,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPI=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 92c8490a840b8844994a9aabc2eef84abe21932f..bae28b4ec132efb4a234725e31f5065ded96e1dd 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -18,6 +18,8 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -25,12 +27,16 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_XIP_SUPPORT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000 CONFIG_SPL_DM_RESET=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y @@ -62,6 +68,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index 43e9228759273c18698fbec2e747b6b5f2a23e8f..2b1d1b4e26c5740e1c5e09d0f87e38a566251353 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -10,6 +10,8 @@ CONFIG_STM32H7=y CONFIG_TARGET_STM32H743_DISCO=y CONFIG_SYS_LOAD_ADDR=0xd0400000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -17,6 +19,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index d7c1c79bb352458dd4b39da4e6e81fc1f465dc0d..eb848dab6d5b40edfdc0520e516ec0ff5edcdd2a 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -10,6 +10,8 @@ CONFIG_STM32H7=y CONFIG_TARGET_STM32H743_EVAL=y CONFIG_SYS_LOAD_ADDR=0xd0400000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" @@ -17,6 +19,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig index 7a2709d52fbc8c13143e91b17d32e9e7bc48c469..8ba91d343603e86ec6453000c440b65ec12aaad9 100644 --- a/configs/stm32h750-art-pi_defconfig +++ b/configs/stm32h750-art-pi_defconfig @@ -10,6 +10,8 @@ CONFIG_STM32H7=y CONFIG_TARGET_STM32H750_ART_PI=y CONFIG_SYS_LOAD_ADDR=0xc1800000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y @@ -23,6 +25,8 @@ CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..f5b62628833ecf4652339d752bc3cb80479dd058 --- /dev/null +++ b/configs/stm32mp13_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x180000 +CONFIG_ENV_OFFSET=0x900000 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk" +CONFIG_STM32MP13x=y +CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_TARGET_ST_STM32MP13x=y +CONFIG_ENV_OFFSET_REDUND=0x940000 +# CONFIG_ARMV7_NONSEC is not set +CONFIG_SYS_LOAD_ADDR=0xc2000000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000 +CONFIG_FIT=y +CONFIG_BOOTDELAY=1 +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_CLK_SCMI=y +CONFIG_STM32_SDMMC2=y +CONFIG_DM_ETH=y +CONFIG_PINCONF=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_SCMI=y +CONFIG_RESET_SCMI=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_SYSRESET_PSCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_ERRNO_STR=y +# CONFIG_LMB_USE_MAX_REGIONS is not set +CONFIG_LMB_MEMORY_REGIONS=2 +CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index 7bf24cf01781061b1afdf30166ee457030340b4a..c70329cd4a69042ebe1f643d57c00f5cb6825a86 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -13,14 +13,26 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -32,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index a2f4b7e6d97e6b1b70a455eefdf58f56be3d8033..838fd89eb993d73daecc89439d58dea99f2a36e5 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -13,14 +13,26 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -32,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index 65bb1c675553b0583d874ee4dfd2d641d34c717f..d503c1a36fe7b1fba64fce096d3e49f7c656c717 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -13,14 +13,26 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -32,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 39f7d9643b17de2a3dbc24a858f9cec7dd97a810..c2792aaad3010ce5b8f4379445a0ea066340cf02 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -13,14 +13,26 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -32,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 1b1c255b981d1910477603011342170de39e2216..416d92bf1bb65701e5fbe3cbc25b1253fb997956 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -8,11 +8,11 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SPL_MMC=y CONFIG_SPL=y -CONFIG_TARGET_ST_STM32MP15x=y CONFIG_CMD_STM32KEY=y -CONFIG_CMD_STM32PROG=y -CONFIG_ENV_OFFSET_REDUND=0x2C0000 CONFIG_TYPEC_STUSB160X=y +CONFIG_TARGET_ST_STM32MP15x=y +CONFIG_ENV_OFFSET_REDUND=0x2C0000 +CONFIG_CMD_STM32PROG=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set @@ -20,11 +20,21 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SPL_LOG=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y @@ -36,6 +46,8 @@ CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -53,6 +65,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 02b37e14eaee07ffdb6c1a166c61e30132920a6a..3452403c61dbbc796f4c0f59aaa0fff6efa0c1d7 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -5,22 +5,25 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_ENV_OFFSET=0x480000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" -CONFIG_TARGET_ST_STM32MP15x=y CONFIG_DDR_CACHEABLE_SIZE=0x10000000 CONFIG_CMD_STM32KEY=y -CONFIG_CMD_STM32PROG=y -CONFIG_ENV_OFFSET_REDUND=0x4C0000 CONFIG_TYPEC_STUSB160X=y +CONFIG_TARGET_ST_STM32MP15x=y +CONFIG_ENV_OFFSET_REDUND=0x4C0000 +CONFIG_CMD_STM32PROG=y # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -38,6 +41,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index ca3873c7e6c38d0188df7898993875bc1f895f4e..4f478c13120c9db8a87997b393a1c78c2a484e62 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 @@ -25,7 +27,15 @@ CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_CONSOLE_MUX=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y @@ -39,7 +49,10 @@ CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y +CONFIG_SPL_TARGET="u-boot.itb" CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_EEPROM=y @@ -60,6 +73,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -72,6 +86,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k( # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_OF_LIVE=y CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx" CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 66a09ef18b72433ba3e0fade8f7ddc90e72b10e4..01fbb05123a9bdac7950d8ce5016ad5743e2373f 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -14,6 +14,8 @@ CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 @@ -23,7 +25,15 @@ CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_CONSOLE_MUX=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x30000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xc0300000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1d00000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y @@ -37,7 +47,10 @@ CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y +CONFIG_SPL_TARGET="u-boot.itb" CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_EEPROM=y @@ -58,6 +71,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -70,6 +84,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k( # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index df31c0fbb103cd432bc94d84442b9388e134ee49..e14668042fa2d3a5e16f6c2f6858239f91c0b137 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -5,23 +5,26 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_ENV_OFFSET=0x280000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" -CONFIG_STM32MP15x_STM32IMAGE=y -CONFIG_TARGET_ST_STM32MP15x=y CONFIG_DDR_CACHEABLE_SIZE=0x10000000 CONFIG_CMD_STM32KEY=y -CONFIG_CMD_STM32PROG=y -CONFIG_ENV_OFFSET_REDUND=0x2C0000 CONFIG_TYPEC_STUSB160X=y +CONFIG_STM32MP15x_STM32IMAGE=y +CONFIG_TARGET_ST_STM32MP15x=y +CONFIG_ENV_OFFSET_REDUND=0x2C0000 +CONFIG_CMD_STM32PROG=y # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -39,6 +42,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 75369d2a0e188e8c6aa6b81bfe14cd6e2203c998..dfec23e75187e4ec56f60dbd384db99ef028812d 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="stmark2" CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_TARGET_STMARK2=y CONFIG_MCFTMR=y +CONFIG_SYS_BARGSIZE=256 CONFIG_TIMESTAMP=y CONFIG_SYS_MONITOR_BASE=0x47E00400 CONFIG_USE_BOOTARGS=y @@ -15,9 +16,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit= CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe 0:1 50000000; sf read ${loadaddr} 0x100000 ${kern_size}; bootm ${loadaddr}" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set CONFIG_SYS_PROMPT="stmark2 $ " +CONFIG_SYS_PBSIZE=283 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_EXPORTENV is not set diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 35c99aaed37bc536dfdffb7abd5ada4775b7539f..4f0cda9c897a7f20087c14af28355490ceaaf492 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -26,16 +26,24 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_SPL_MAX_SIZE=0x4000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xe6340000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=256 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 27d1f40f3c1bbfabf7261c7c44ca2b8474a87f6b..2c143068b79ee8cd9da5e56f2cb1bcf736b5617c 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTCOMMAND="go 0x40040000" CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="STV0991> " +CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_MEMTEST=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set @@ -36,6 +37,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_PHY_RESET_DELAY=10000 CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y CONFIG_CADENCE_QSPI=y CONFIG_HAS_CQSPI_REF_CLK=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index a3b1d76d8bb11871128bafedd039a2c76b760471..59315cdb05d5139e6922ffb057438279ca605415 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -9,6 +9,8 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 3fee7c2e50c0d159a233d5a5237d3fc4a6ec4847..b77c4e7a3cb0b23160f1ac8132ee81ddc2ce1043 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,7 +11,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index add6041e2707aa20c2f819f872587e6eeb1c3ce7..9ddc80fe17df323255116f28145bcdfc5d88a620 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -11,9 +11,13 @@ CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_TARGET_DEVELOPERBOX=y CONFIG_AHCI=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe0000000 CONFIG_FIT=y CONFIG_BOOTSTAGE_STASH_SIZE=4096 CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=128 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 9d2edd2eceb6c7a45d60262ea7498d70928735bb..51f629488b951420d5363954e71baea46fd264da 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -9,8 +9,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 -CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_MAC_IN_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_SYS_LOAD_ADDR=0x0 @@ -25,10 +23,21 @@ CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 +CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_FALCON_BOOT_MMCSD=y -CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x0 +CONFIG_SYS_SPL_ARGS_ADDR=0x10000000 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=2071 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig index 0390347415cd41d76b0f244eaf403fd0c64a4cb5..84dbf106d495d74a715dfb9b7cb8db41d8b5d981 100644 --- a/configs/tanix_tx6_defconfig +++ b/configs/tanix_tx6_defconfig @@ -8,3 +8,6 @@ CONFIG_DRAM_CLK=648 CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x118000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index e6bef6c974eed3409e9da241aae8db702d57bb82..3d61c7b57b59ba5d79650b71b25624889d869ae5 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -8,7 +8,6 @@ CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_TARGET_TAURUS=y @@ -19,6 +18,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" @@ -39,16 +39,31 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x3e00 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x3e00 +CONFIG_SPL_BSS_MAX_SIZE=0x600 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x304000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20ba0000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x460000 CONFIG_SPL_CRC32=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_SOFTECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_SYS_XTRACE is not set # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y @@ -95,6 +110,8 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_ATMEL_USART=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 7b843a71f096ea197490a4015837f4de7fff7251..aebaa6ad1476929757ebec9fcc7b20c079713cc1 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -7,10 +7,15 @@ CONFIG_ENV_SIZE=0x800 CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" CONFIG_SYS_CLK_FREQ=500000000 CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f30 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="[tb100]:~# " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=284 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 9f7642f25ca0d520df9dbaa459c7cfd2f766e8f6..892d7c60d283932760ad2d435cb35ae0b7ddb101 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -28,6 +28,8 @@ CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Matrix U-Boot> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=544 # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set @@ -69,6 +71,8 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -79,6 +83,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y # CONFIG_PCI_PNP is not set +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_RTC=y diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index b3c2e69d6cdb2ed826f9c58ad89e587c642049b8..3dd9252a7423564b58f64dce15e33d7f8cee5e38 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -13,6 +13,8 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index ea568d4bf700cc0375ed54b1e736aba8980d6033..191b2c08509d7d998b37dc7b1f266dbf50129b2e 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -14,7 +14,17 @@ CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index ec6ecbce6fb17b82fe0bcbbb52fc02f695612cc1..9fed0eaed1357d181a075ab9b354d5c7f246d6d5 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -13,7 +13,17 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (TEC) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2081 # CONFIG_CMD_IMI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index 96bca8344dfd03d59b4b311de15ec3165aa5dcbb..4bbee30b064220070f4e2993986bf6c159504d8b 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -27,6 +27,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_ID_EEPROM is not set CONFIG_PCI_INIT_R=y CONFIG_RESET_PHY_R=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index e7de85eb506c6041818152d5c01a8921818e452d..6f202dc8a4344e42d9fea12cffeb02b451a9b25b 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -9,6 +9,9 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" +CONFIG_SPL_STACK=0x54000 +CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 25758b434f57c9eacc1f7e31db8241bf62295a96..afb1957ddd233aa6fd05fe345da54f95aff9d269 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -27,6 +27,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -57,6 +58,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 73241aeed09f6892c372f2dfc303a15f8f2ccadd..113c0dae2e6880b2acd7cc5eea14c4d2a85147a8 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -56,6 +57,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 9dd2d4f387d563c2d52be8d89e5d39ca0ed34271..95ff9d763ff0d93d8a8491276666b79515a77966 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -54,6 +55,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_NUVOTON_NCT6102D=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 9e8523d94145bb66b7afd9ae768a9eecf013ab14..d47413c0a911dad4bdef0b8a79a54e1830bf9789 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -19,6 +19,8 @@ CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_MEM_TOP_HIDE=0x80000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_BOOTDELAY=3 @@ -27,8 +29,16 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x1bfd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40020000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_I2C=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -57,9 +67,11 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_STRATIX_V=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 8cf0100aef7d5af42df2be09c7649c8f41aee03f..6115e9e3edcac22edb87839e656476c5f62b50d5 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -34,6 +36,10 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80208000 CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -46,6 +52,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -71,6 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 5e818864d2cd66b2434add94626cebae79eafdc8..71fbf2122cdd7704ee5e1afe44c0bfbfb2f54ad7 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core" CONFIG_SYS_LOAD_ADDR=0x500000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x57fff0 CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y @@ -21,6 +23,10 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000 debug ma CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="ThunderX_88XX> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_EDITENV is not set diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index d328ea12226002131d653330b9ecbbebdd4e5602..54c1d80e5105411a7202b4639a02860b7581948f 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -20,6 +20,8 @@ CONFIG_SYS_CLK_FREQ=27000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk" @@ -27,12 +29,16 @@ CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_MISC_INIT_R is not set +CONFIG_SPL_MAX_SIZE=0xfff1b400 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y +CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 5c2366098b7b1f21baa4087ec6fd00cda51f753b..839b93284f8c38a35b5d8bf0aba825b068ed121e 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -16,15 +16,22 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 4b6ae64988af07ba55010c3da8abaecca948715b..886c6a933a7c1d2374bccf91fa42a76519aef387 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -11,20 +11,27 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s" CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x800000 -CONFIG_SPL_SIZE_LIMIT=0x4B000 +CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index eecc3dcb935867c5a0b1c43eb6624909c588ff5d..faa0c4b10e28f689fcaa54e0e66b21e06f0c15bf 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -10,7 +10,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" CONFIG_SYS_LOAD_ADDR=0x0 @@ -25,10 +24,21 @@ CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot" CONFIG_USE_PREBOOT=y CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=2077 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 7188a03edcb4c2128dc908879a81d8676b606f96..97b3f237dc39ce4c294b252c6cb1fdca515dcfe2 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -10,7 +10,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" CONFIG_SYS_LOAD_ADDR=0x0 @@ -25,10 +24,21 @@ CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot" CONFIG_USE_PREBOOT=y CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=2077 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 83f38effd5f7e882e0894b933d2d0920eaab2f2d..4c76e8d18055ac4a50075ae645159dcf5cbd3d7a 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -10,7 +10,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" CONFIG_SYS_LOAD_ADDR=0x0 @@ -25,10 +24,21 @@ CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot" CONFIG_USE_PREBOOT=y CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=2077 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index 826afaa66cb34cb10ec29a8ed4a5c9c0c5cfbc25..2cb17f5040bf536f528fc51d9c8518da22a272c4 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_REMAKE_ELF=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y @@ -22,6 +24,9 @@ CONFIG_AVB_VERIFY=y CONFIG_AVB_BUF_ADDR=0x90000000 CONFIG_AVB_BUF_SIZE=0x10000000 CONFIG_SYS_PROMPT="TOTAL_COMPUTE# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -46,6 +51,7 @@ CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index c8f97be7eba48334f581655cbbcd618438f51479..40dc2c158ef62cf9d684c21d4f53e37f1da4e074 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -8,6 +8,8 @@ CONFIG_ARCH_ATH79=y CONFIG_BOARD_TPLINK_WDR4300=y CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_END=0x83f00000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xbd007fff CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" @@ -15,7 +17,9 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index 81c30c6fc67791b84af0159a535f0ffe635554f5..a02ee9278524e6beb1c6b1a64fbcaf1a41df720c 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 25f231cc1de78b7051eb2bedbae6b10e1d4d1ee3..8f7e0ac1019fd9deed599acbf4811194db02ff82 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -19,6 +19,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index b838858c415c443e3f8655a14e04dba2d847b0dd..48822f388c8f6940793e5805313c9553163fb63a 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index a3bca139412cb4dc17bc98174f460a811405dbdb..ed774262aecf19ab1ccbb82d632e25ebd0d16fd9 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -19,6 +19,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index b41ace3d41d19064f2572864d1dbf052702fd50b..9400c6481211af1c1458336a68a0e286df9453a6 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index b9a3facdb1b79897d0eb1dccb9632646dea24c2a..ddbf9a757e6e372e2f638139a0ec52c678d0a2d7 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -19,6 +19,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 6c43a02cb0ca23e6fb8de5c1d2210e2583e07929..b48ed9c4242d5318c241beca2e82d20f9d029902 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -8,12 +8,15 @@ CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_TRATS2=y +CONFIG_EXYNOS_ACE_SHA=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" CONFIG_SYS_MEM_TOP_HIDE=0x100000 CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43dfff10 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +27,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="Trats2 # " +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_XIMG is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y @@ -58,6 +62,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_LIB_HW_RAND=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 5990dc12263a843cd11022b498584b52a50e8bdc..3e0fdfe83483910ce42719a93cd7cca9fe2caece 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -8,12 +8,15 @@ CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_TRATS=y +CONFIG_EXYNOS_ACE_SHA=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" CONFIG_SYS_MEM_TOP_HIDE=0x100000 CONFIG_SYS_LOAD_ADDR=0x44800000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x447fff10 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y @@ -23,6 +26,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="Trats # " +CONFIG_SYS_PBSIZE=1024 # CONFIG_CMD_XIMG is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y @@ -55,6 +59,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_LIB_HW_RAND=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index b28349dc1c8e4d6d25c8eb1f7a9f54055a405fd7..134605d8793a73a061bc4d7711e1410eec085e1d 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -14,7 +14,17 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2087 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 11f8b5b10516286a76ffbe40499a4a2c9098e884..0d1c99c62c5032285e5c07e8ad04e6ec5cee86e8 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -131,6 +131,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -157,6 +161,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index c1bd1de4a91ceef8af5e57049d4ca8c5b41db9d8..1df47fe3c9ca5a70d500c92e1af8ee99e26fd2f2 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -16,6 +16,8 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -28,6 +30,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index da94ca74ac911c3cacd8691fc3729f670b0285d8..4085fac2329e51f8567b68942f17aa019a2c5471 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -27,6 +27,8 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -36,9 +38,16 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x22fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SYS_MAXARGS=32 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index c253664062193e6893731f18a09fc89b735f25bc..3fe731fd188a1003bd36f1b57be316c77840fdb8 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -153,6 +153,10 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/u200_defconfig b/configs/u200_defconfig index 609f282c65a7ce3a1b3d9b19fbbfdf4c3abbf1ab..0260a3823fa03d8437fd324a4d9002c9ae0dd7d7 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" u200" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index f7cd1a0589bc13467b6ef106ec4fc66da7f9cbb3..2b2dc16646219c6e9bf4c94ec7ad580e54149241 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="uDPU>> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=1048 # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -50,6 +54,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y @@ -96,4 +102,3 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_LZO=y -CONFIG_SPL_LZO=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index ab2b2ee67550b56113ccc9139a114ded8738063b..a1d2d7f2e475c3000649ced6ee7976ec8ba2a8d7 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -22,9 +22,13 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set @@ -40,6 +44,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 2daf5f81bbf2904001bf0fb52516e42acd1d3bd4..e5ba2f3d090203711598d4a8332eb0a3e0593cfe 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -22,9 +22,13 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 03e4f1fb036086205556acece5035a52567dfff1..5de9a6883432614b2b13472f77941f9065affbe7 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -10,15 +10,24 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x100000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_CMD_CONFIG=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_XIMG is not set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index b69b2b265706575b3ba4de610536f43b6f8a9e24..b6b5ca58c2725f303f13f75af64327002f841036 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -10,15 +10,24 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x100000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_CMD_CONFIG=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_XIMG is not set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index db986cf13b84a940e66e9784326006c5bfc896cb..eccfb0dbb167cf12cffed906d45061ec2d36ab41 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -16,6 +16,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 CONFIG_CMD_CONFIG=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_XIMG is not set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index 65f6a5e97146a5f12e7324b5667b5db189dbb816..b6846503ef4da83345ad1d09eca93e2c07cfa591 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -20,6 +20,8 @@ CONFIG_BOOTCOMMAND="nboot 21000000 0" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 6141a5cfd015b05df60ab9da4283fd5640b84dc6..c01ca017064c9edf9280a54d4508a48d9238b31c 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MEMTEST_START=0x70000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run distro_bootcmd; setenv bootargs console=${console} ${bootargs_default}; ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; bootz ${kernel_addr_r} - ${fdt_addr_r}" +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_I2C=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 187402a61bdee4b730c16ea8c77eeaeebd2b2ba7..0f9cc8d82d3b7da83e6684d476b9feb52202d209 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -18,8 +18,11 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmc_mmc_fit" +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -55,6 +58,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Variscite" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index aa47fbca5ba86376fd8c065daa682c4dc7ae28c9..db455f4d97634f993c9d9a487c32a70c5b960e03 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -10,11 +10,22 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_VENICE2=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra124 (Venice2) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2086 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 1c8857e44cbbcab5a6c61e8e07c831096b881648..87e4d10b292e02f1000ad2ee7b6eb59a648bfbf9 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -12,7 +12,17 @@ CONFIG_TARGET_VENTANA=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x90000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2085 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 46d4dd7210612a3b4fa11324c2de3b69531fbd51..34afdc57911ed009e9a3320be6ca3ae0d62ce5f6 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -32,13 +32,26 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="Verdin iMX8MM # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 4b7cf74f6cdcac50e0af7f83827b2ca49877d31e..52d281e831887cd1c413b043829dd7448b83025c 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -40,15 +40,28 @@ CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="Verdin iMX8MP # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 967bc560936f35602733458f193087579067e438..792bcf1eb5d44f33f687ee94e16068968bf77812 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -7,6 +7,8 @@ CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_TARGET_VEXPRESS64_JUNO=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y @@ -14,6 +16,9 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="VExpress64# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_MEMTEST=y CONFIG_CMD_ARMFLASH=y CONFIG_CMD_PCI=y @@ -23,9 +28,11 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y +CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_PCI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 1a4cbc1cdd064e284844dfa3799928f32306adbc..0ae8ae10a3106eca9fbfe9b467f5851d488e8ca4 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -14,6 +14,9 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="VExpress64# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 CONFIG_CMD_ABOOTIMG=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_ARMFLASH=y @@ -22,6 +25,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y +CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig index a1c5d88717013bdc07b30d37e780ce4c9c8f40fa..2cc28d6c6a32f7e86d0011048dd6263eaad14a15 100644 --- a/configs/vexpress_aemv8r_defconfig +++ b/configs/vexpress_aemv8r_defconfig @@ -11,5 +11,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x9c090000 rootfstype=ext4 root=/dev/vda2 rw rootwait" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="VExpress64# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 # CONFIG_MMC is not set CONFIG_VIRTIO_MMIO=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index e221e8207e462677e1e6305d0853962df6396644..f2084890edeca86d948bb952c0199f1370da4ddf 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -11,11 +11,15 @@ CONFIG_DEFAULT_DEVICE_TREE="vexpress-v2p-ca9" CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_ENV_ADDR=0x47F80000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60000f10 CONFIG_SYS_MONITOR_BASE=0x40000000 CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index b3c66dfc6181c4188b8b288879216aa57548d95d..0a3374cd545bf7d016b66fdeb87694b9a2679379 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -25,6 +25,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 9cbd62e3c8d08e210093f267298b56d033e57126..288169c7ee3faaa0f92b359ef52587e7dbac8ba6 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -25,6 +25,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y @@ -43,6 +45,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_VYBRID_GPIO=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index e1e1f953826ceaed9fe96c70b45474ac84cf058e..390712a8df67b2d8b9952ff6db175ea3e3b48e18 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -12,6 +12,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="at91-vinco" CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000f00 CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,8 @@ CONFIG_BOOTCOMMAND="mmc dev 0 0;mmc read ${loadaddr} ${k_offset} ${k_blksize};mm CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="vinco => " +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_GPT=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 57fd3376bbcc09f276c1130918f2b0ecb0d884ab..8d87857ba0a4c58e67a929bbe7690e9ace08e8f1 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -31,13 +31,17 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -80,6 +84,8 @@ CONFIG_DM_ETH=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y @@ -89,6 +95,7 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index 867655457441c7540420af102e4ed4a16d0301b9..b362d549a21d4618b3441cf301f9df51447ef59f 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -30,9 +30,16 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_LOGLEVEL=8 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_MAX_SIZE=0x10000 +CONFIG_SPL_BSS_START_ADDR=0x80010000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_LICENSE=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index ecba1a76c3895469da6ca717e442cf3b6374d3be..516e2cc32b8c57094970a8a12d29265d89c1b5bb 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -16,15 +16,25 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0xffe5000 CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x8800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x8000 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 569b5873ffc8f804d36dd5447decc78290a68ea8..8b0533ce585c01604ee6c23c37d863d2ffac68cf 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -33,10 +33,14 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -55,6 +59,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 100f1c93627813616e1420053a73efaa60ce4c59..a50a1c8bc77018c9294d1ac8a8892412310ad3b0 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -19,6 +19,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi" # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index b72332c778a46b41363299ad9075fe12052c0f2a..40f9e502e92f5c96a85d75576041a782fc102b73 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -23,6 +23,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then run do_bootscript_hab;if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi" # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set diff --git a/configs/warp_defconfig b/configs/warp_defconfig index a3bc5b68528cd25db945910b02092916e883e56f..4c9f7051fefc773d9091d1a050b3a5dd68dd95e1 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -16,6 +16,8 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index 07268c14a046f7e25e45365beb7076015953d811..c8fe005e6040a9cfb337d5785116283c12a3d465 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -11,10 +11,13 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" wetek-core2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_REMAKE_ELF=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 4c5008fedef3211a463bcfba6224f9cf5ff2dc04..7eb23907ebcdd6e27245249cb695d01e2aa8581f 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -20,14 +20,20 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x120000 CONFIG_SYS_LOAD_ADDR=0x80008000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007ff20 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS2,115200n8" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_PAD_TO=0x20000 +CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfff8 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 860cb220713922c626a045a129406c35d2590571..c52c9bdb066b1fee0cb914a81f5d080fd2fd117b 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -19,6 +19,8 @@ CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_ENV_ADDR=0x100000 CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SILENT_CONSOLE=y @@ -26,8 +28,17 @@ CONFIG_SILENT_U_BOOT_ONLY=y CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x22fd0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x40023000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x4002c000 CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index 11fca0907de18597f34b230f430baaa21ee69d5e..31fb4fde40e20cdeb4a6a9dd5da3603dbc55fb1b 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -11,8 +11,11 @@ CONFIG_SYS_LOAD_ADDR=0x40000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=10 CONFIG_SYS_PROMPT="xenguest# " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1051 # CONFIG_CMD_BDI is not set # CONFIG_CMD_BOOTD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_IMI is not set diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 00d08f49f61634d30c9086575318183baa45f1bb..e555c0ccfac2e40da671581e6384bfa6dec2a4e3 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set @@ -29,6 +31,9 @@ CONFIG_CLOCKS=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Versal> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 9d2f97576bbd7185b2db0f8d5ec0a01b10dc22d2..60d2263c5846f65432c57a5a49e2c73f7439c669 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -11,6 +11,8 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set @@ -25,6 +27,9 @@ CONFIG_CLOCKS=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Versal> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 7efb9287561a395d1e18dfd803491ae156d57131..6bbaf3ce33973264db530ecfd5dc60a86907c2d1 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -11,6 +11,8 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set @@ -25,6 +27,9 @@ CONFIG_CLOCKS=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Versal> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 38747ffd02cb39321e18561a6dc999b54b0af13d..7f0bcb2eaa98434b532aa3f32a6dd463b9234271 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 -CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt" CONFIG_CMD_FRU=y CONFIG_DEFINE_TCM_OCM_MMAP=y @@ -22,6 +21,9 @@ CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="Versal> " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMTEST=y @@ -44,6 +46,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_PARTITION_TYPE_GUID=y @@ -92,6 +95,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_AXIMRMAC=y @@ -102,6 +106,8 @@ CONFIG_XILINX_UARTLITE=y CONFIG_SOC_XILINX_VERSAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1f3e6a42a1465c1d173e4c683016eaf0c88ac0ee..b3834b4952ff986a6b0896dcf98bc3159f824aae 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -28,12 +28,26 @@ CONFIG_LEGACY_IMAGE_FORMAT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_PREBOOT=y CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x100000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x10000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_PBSIZE=2071 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y @@ -58,6 +72,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y @@ -111,6 +126,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_REALTEK=y CONFIG_PHY_XILINX=y +CONFIG_DM_ETH_PHY=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_ARM_DCC=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index f2eaec2f91b9f14857d9705d545ac118ec7df1f1..5963dd90f7268417ec0cc3344a91542ecb5de1d4 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -12,6 +12,8 @@ CONFIG_ZYNQMP_PSU_INIT_ENABLED=y CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set @@ -21,6 +23,9 @@ CONFIG_CLOCKS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index b405277156694532fe23c59e4a9d1c4315622793..a248cbf3a37b0b1de231900c8b2a1096ac692765 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL=y CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y @@ -22,8 +24,21 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 5fa1337d761c4ce92bfa65d87b6b2eb8b9b39ac6..df0365ba77f86cdcb3d05c0445b00a9455336890 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL=y CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y @@ -22,8 +24,21 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 90e28203b3f4573c87ab28229ce5acc3b3d1931d..a2405f24ef77631295818801d95d767cdf05d50e 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -10,6 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y @@ -22,6 +24,9 @@ CONFIG_CLOCKS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 1a63ec9195fed04081ffdd7835d2ded96be98c74..e6ebc12ed7d2c6aa444b61c5084c84d99206541d 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -10,6 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y @@ -22,6 +24,9 @@ CONFIG_CLOCKS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index bdda942db6db31915c3e784050610e5a01269b4a..82510f190477d861f14afe207946943b4f7b7d23 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -14,6 +14,8 @@ CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set @@ -21,9 +23,22 @@ CONFIG_REMAKE_ELF=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1049 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index 3dcfa43af59bc129ca4f7f9067041d0642f1a1ef..1784792ce49cf86d84823ecc5d37de847634eee2 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -15,6 +15,10 @@ CONFIG_DEBUG_UART=y CONFIG_BOOTSTAGE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="ZynqMP r5> " +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=284 +CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 35894076c52f908d34e08bee108c0ddf6336e3eb..89622d18f8e2ca88a06850551b53c743508e9a16 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -31,15 +31,31 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run scsi_init;usb start" CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffffc CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 +CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub" +CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin" CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_SPL_ARGS_ADDR=0x8000000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_NVEDIT_EFI=y @@ -79,6 +95,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y @@ -160,6 +177,7 @@ CONFIG_PHY_TI_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y CONFIG_DM_REGULATOR=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 5de17c6c8c67cc598cbe6576566ff10faaec161c..eab40fc0d133e9b93529041cd1e6886a5f144346 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -15,8 +15,10 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press to stop\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_MISC_INIT_R=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y @@ -36,6 +38,7 @@ CONFIG_DM=y # CONFIG_DM_SEQ_ALIAS is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHYLIB=y diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig index 11f3715e6dccd7eb4eafe41acd3a04947f71c387..7d45440c0cc5a23b7c52674adc42d5cc90f48246 100644 --- a/configs/zeropi_defconfig +++ b/configs/zeropi_defconfig @@ -8,6 +8,8 @@ CONFIG_MACPWR="PD6" # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_PBSIZE=1024 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index b2c5924c2564d75f8ff5c28e280cec039cb1c134..b69c8b92a488ccc44671b8fd741e00a387f24792 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -21,10 +21,23 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1047 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 280627e4ca4b1c8c6943db0d89ad2446f1e5ffea..ecdbf8182e68c79e4c7d4e223670610499d1d40f 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -21,10 +21,23 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1047 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 9d4e49e8f3c7b42f3c6ef8f4257f3ef1b6f0e62c..49dd5ad6069224cdf8601659219402cb39b7682e 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -28,12 +28,25 @@ CONFIG_USE_PREBOOT=y # CONFIG_ARCH_EARLY_INIT_R is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x2000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1047 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 65b0896c7fd29603a69e3e1f6c1b82997d205491..a7da4bcb836eec125b1c92325458f88764a8f8df 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,18 +11,6 @@ Configuration options CONFIG_USB_OHCI_NEW: enable the new OHCI driver - CONFIG_SYS_USB_OHCI_BOARD_INIT: call the board dependant hooks: - - - extern int board_usb_init(void); - - extern int usb_board_stop(void); - - extern int usb_cpu_init_fail(void); - - CONFIG_SYS_USB_OHCI_CPU_INIT: call the cpu dependant hooks: - - - extern int usb_cpu_init(void); - - extern int usb_cpu_stop(void); - - extern int usb_cpu_init_fail(void); - CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers @@ -43,21 +31,3 @@ config option needs to be defined. - -PCI Controllers ----------------- - -You'll need to define - - CONFIG_PCI_OHCI - -If you have several USB PCI controllers, define - - CONFIG_PCI_OHCI_DEVNO: number of the OHCI device in PCI list - -If undefined, the first instance found in PCI space will be used. - -PCI Controllers need to do byte swapping on register accesses, so they -should to define: - - CONFIG_SYS_OHCI_SWAP_REG_ACCESS diff --git a/doc/api/index.rst b/doc/api/index.rst index 72fea981b724e2bbde2320727a9431c063fbba03..a9338cfef9f15211dd97dfb351ab48bbb3abae99 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -14,6 +14,7 @@ U-Boot API documentation linker_lists lmb logging + nvmem pinctrl rng sandbox diff --git a/doc/api/linker_lists.rst b/doc/api/linker_lists.rst index 7063fdc83144e1c90f9939a3c44422fd9dcb1910..3cd447f187dfeb21f9a657d222d5aeb95ccdda9d 100644 --- a/doc/api/linker_lists.rst +++ b/doc/api/linker_lists.rst @@ -13,7 +13,7 @@ then the corresponding input section name is :: - .u_boot_list_ + 2_ + @_list + _2_ + @_entry + __u_boot_list_ + 2_ + @_list + _2_ + @_entry and the C variable name is @@ -23,7 +23,7 @@ and the C variable name is This ensures uniqueness for both input section and C variable name. -Note that the names differ only in the first character, "." for the +Note that the names differ only in the characters, "__" for the section and "_" for the variable, so that the linker cannot confuse section and symbol names. From now on, both names will be referred to as @@ -63,11 +63,11 @@ iterated at least once. :: - .u_boot_list_2_array_1 - .u_boot_list_2_array_2_first - .u_boot_list_2_array_2_second - .u_boot_list_2_array_2_third - .u_boot_list_2_array_3 + __u_boot_list_2_array_1 + __u_boot_list_2_array_2_first + __u_boot_list_2_array_2_second + __u_boot_list_2_array_2_third + __u_boot_list_2_array_3 If lists must be divided into sublists (e.g. for iterating only on part of a list), one can simply give the list a name of the form @@ -129,17 +129,17 @@ the compiler cannot update the alignment of the linker_list item. In the first case, an 8-byte 'fill' region is added:: - .u_boot_list_2_driver_2_testbus_drv + __u_boot_list_2_driver_2_testbus_drv 0x0000000000270018 0x80 test/built-in.o 0x0000000000270018 _u_boot_list_2_driver_2_testbus_drv - .u_boot_list_2_driver_2_testfdt1_drv + __u_boot_list_2_driver_2_testfdt1_drv 0x0000000000270098 0x80 test/built-in.o 0x0000000000270098 _u_boot_list_2_driver_2_testfdt1_drv *fill* 0x0000000000270118 0x8 - .u_boot_list_2_driver_2_testfdt_drv + __u_boot_list_2_driver_2_testfdt_drv 0x0000000000270120 0x80 test/built-in.o 0x0000000000270120 _u_boot_list_2_driver_2_testfdt_drv - .u_boot_list_2_driver_2_testprobe_drv + __u_boot_list_2_driver_2_testprobe_drv 0x00000000002701a0 0x80 test/built-in.o 0x00000000002701a0 _u_boot_list_2_driver_2_testprobe_drv diff --git a/doc/api/nvmem.rst b/doc/api/nvmem.rst new file mode 100644 index 0000000000000000000000000000000000000000..d923784652476419ea5eca1b2c1fab627c4d1b26 --- /dev/null +++ b/doc/api/nvmem.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NVMEM API +========= + +.. kernel-doc:: include/nvmem.h + :doc: Design + +.. kernel-doc:: include/nvmem.h + :internal: diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 0c5d3a90f04ee8e353ab8783d722d6732cf40e76..00f9b454421f765edbde625870c409c050fd960f 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -1,41 +1,31 @@ .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause .. sectionauthor:: Patrick Delaunay -STM32MP15x boards +STM32MP1xx boards ================= -This is a quick instruction for setup STM32MP15x boards. +This is a quick instruction for setup STMicroelectronics STM32MP1xx boards. -Futher information can be found in STMicrolectronics STM32 WIKI_. +Further information can be found in STMicroelectronics STM32 WIKI_. Supported devices ----------------- -U-Boot supports STMP32MP15x SoCs: +U-Boot supports all the STMicroelectronics MPU with the associated boards - - STM32MP157 - - STM32MP153 - - STM32MP151 + - STMP32MP15x SoCs: -The STM32MP15x is a Cortex-A MPU aimed at various applications. + - STM32MP157 + - STM32MP153 + - STM32MP151 -It features: - - - Dual core Cortex-A7 application core (Single on STM32MP151) - - 2D/3D image composition with GPU (only on STM32MP157) - - Standard memories interface support - - Standard connectivity, widely inherited from the STM32 MCU family - - Comprehensive security support + - STMP32MP13x SoCs: -Each line comes with a security option (cryptography & secure boot) and -a Cortex-A frequency option: - - - A : Cortex-A7 @ 650 MHz - - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - - D : Cortex-A7 @ 800 MHz - - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz + - STM32MP135 + - STM32MP133 + - STM32MP131 -Everything is supported in Linux but U-Boot is limited to: +Everything is supported in Linux but U-Boot is limited to the boot device: 1. UART 2. SD card/MMC controller (SDMMC) @@ -49,7 +39,35 @@ And the necessary drivers 1. I2C 2. STPMIC1 (PMIC and regulator) 3. Clock, Reset, Sysreset - 4. Fuse + 4. Fuse (BSEC) + 5. OP-TEE + 6. ETH + 7. USB host + 8. WATCHDOG + 9. RNG + 10. RTC + +STM32MP15x +`````````` + +The STM32MP15x is a Cortex-A7 MPU aimed at various applications. + +It features: + + - Dual core Cortex-A7 application core (Single on STM32MP151) + - 2D/3D image composition with GPU (only on STM32MP157) + - Standard memories interface support + - Standard connectivity, widely inherited from the STM32 MCU family + - Comprehensive security support + - Cortex M4 coprocessor + +Each line comes with a security option (cryptography & secure boot) and +a Cortex-A frequency option: + + - A : Cortex-A7 @ 650 MHz + - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz + - D : Cortex-A7 @ 800 MHz + - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz Currently the following boards are supported: @@ -59,6 +77,16 @@ Currently the following boards are supported: + stm32mp157c-ev1.dts + stm32mp15xx-dhcor-avenger96.dts +STM32MP13x +`````````` + +The STM32MP13x is a single Cortex-A7 MPU aimed at various applications. + +Currently the following boards are supported: + + + stm32mp135f-dk.dts + + Boot Sequences -------------- @@ -71,12 +99,22 @@ Boot Sequences + +------------------------+-------------------------+--------------+ | | embedded RAM | DDR | +----------+------------------------+-------------------------+--------------+ +| TrustZone| secure monitor | ++----------+------------------------+-------------------------+--------------+ + +The trusted boot chain is recommended with: + +- FSBL = **TF-A BL2** +- Secure monitor = **OP-TEE** +- SSBL = **U-Boot** + +It is the only supported boot chain for STM32MP13x family. The **Trusted** boot chain with TF-A_ ````````````````````````````````````` defconfig_file : - + **stm32mp15_defconfig** (for TF-A_ with FIP support) + + **stm32mp15_defconfig** and **stm32mp13_defconfig** (for TF-A_ with FIP support) + **stm32mp15_trusted_defconfig** (for TF-A_ without FIP support) +-------------+--------------------------+------------+-------+ @@ -98,8 +136,8 @@ TF-A_ (BL2) initialize the DDR and loads the next stage binaries from a FIP file the secure monitor to access to secure resources. + HW_CONFIG: The hardware configuration file = the U-Boot device tree -The **Basic** boot chain with SPL -````````````````````````````````` +The **Basic** boot chain with SPL (for STM32MP15x) +`````````````````````````````````````````````````` defconfig_file : + **stm32mp15_basic_defconfig** @@ -117,16 +155,19 @@ SPL has limited security initialization. U-Boot is running in secure mode and provide a secure monitor to the kernel with only PSCI support (Power State Coordination Interface defined by ARM). -All the STM32MP15x boards supported by U-Boot use the same generic board -stm32mp1 which support all the bootable devices. +.. warning:: This alternate **basic** boot chain with SPL is not supported/promoted by STMicroelectronics to make product. + +Device Tree +----------- -Each board is configured only with the associated device tree. +All the STM32MP15x and STM32MP13x boards supported by U-Boot use the same generic board +stm32mp1 which supports all the bootable devices. -Device Tree Selection ---------------------- +Each STMicroelectronics board is only configured with the associated device tree. -You need to select the appropriate device tree for your board, -the supported device trees for STM32MP15x are: +STM32MP15x device Tree Selection +```````````````````````````````` +The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig) are: + ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1) @@ -148,6 +189,15 @@ the supported device trees for STM32MP15x are: + stm32mp15xx-dhcor-avenger96 +STM32MP13x device Tree Selection +```````````````````````````````` +The supported device trees for STM32MP13x (stm32mp13_defconfig) are: + ++ dk: Discovery board + + + stm32mp135f-dk + + Build Procedure --------------- @@ -170,6 +220,7 @@ Build Procedure for example: use one output directory for each configuration:: + # export KBUILD_OUTPUT=stm32mp13 # export KBUILD_OUTPUT=stm32mp15 # export KBUILD_OUTPUT=stm32mp15_trusted # export KBUILD_OUTPUT=stm32mp15_basic @@ -184,9 +235,10 @@ Build Procedure with : - - For **trusted** boot mode : **stm32mp15_defconfig** or - stm32mp15_trusted_defconfig - - For basic boot mode: stm32mp15_basic_defconfig + - For **trusted** boot mode : + - For STM32MP13x: **stm32mp13_defconfig** + - For STM32MP15x: **stm32mp15_defconfig** or stm32mp15_trusted_defconfig + - For STM32MP15x basic boot mode: stm32mp15_basic_defconfig 5. Configure the device-tree and build the U-Boot image:: @@ -194,37 +246,42 @@ Build Procedure Examples: - a) trusted boot with FIP on ev1:: + a) trusted boot with FIP on STM32MP15x ev1:: # export KBUILD_OUTPUT=stm32mp15 # make stm32mp15_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all - b) trusted boot without FIP on dk2:: + b) trusted boot on STM32MP13x discovery board:: - # export KBUILD_OUTPUT=stm32mp15_trusted - # make stm32mp15_trusted_defconfig - # make DEVICE_TREE=stm32mp157c-dk2 all + # export KBUILD_OUTPUT=stm32mp13 + # make stm32mp13_defconfig + # make DEVICE_TREE=stm32mp135f-dk all - c) basic boot on ev1:: + DEVICE_TEE selection is optional as stm32mp135f-dk is the default board of the defconfig:: + + # make stm32mp13_defconfig + # make all + + c) basic boot on STM32MP15x ev1:: # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all - d) basic boot on ed1:: + d) basic boot on STM32MP15x ed1:: # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ed1 all - e) basic boot on dk1:: + e) basic boot on STM32MP15x dk1:: # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157a-dk1 all - f) basic boot on avenger96:: + f) basic boot on STM32MP15x avenger96:: # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig @@ -235,6 +292,7 @@ Build Procedure So in the output directory (selected by KBUILD_OUTPUT), you can found the needed U-Boot files: + - stm32mp13_defconfig = **u-boot-nodtb.bin** and **u-boot.dtb** - stm32mp15_defconfig = **u-boot-nodtb.bin** and **u-boot.dtb** - stm32mp15_trusted_defconfig = u-boot.stm32 @@ -325,9 +383,9 @@ the boot pin values = BOOT0, BOOT1, BOOT2 | SPI-NAND | 1 | 1 | 1 | +-------------+---------+---------+---------+ -- on the **daugther board ed1 = MB1263** with the switch SW1 -- on **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable) -- on board **DK1/DK2** with the switch SW1 = BOOT0, BOOT2 +- on the STM32MP15x **daughter board ed1 = MB1263** with the switch SW1 +- on STM32MP15x **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable) +- on board STM32MP15x **DK1/DK2** with the switch SW1 = BOOT0, BOOT2 with only 2 pins available (BOOT1 is forced to 0 and NOR not supported), the possible value becomes: @@ -355,7 +413,7 @@ The communication between HOST and board is based on Prepare an SD card ------------------ -The minimal requirements for STMP32MP15x boot up to U-Boot are: +The minimal requirements for STMP32MP15x and STM32MP13x boot up to U-Boot are: - GPT partitioning (with gdisk or with sgdisk) - 2 fsbl partitions, named "fsbl1" and "fsbl2", size at least 256KiB @@ -511,14 +569,25 @@ MAC Address Please read doc/README.enetaddr for the implementation guidelines for mac id usage. Basically, environment has precedence over board specific storage. -For STMicroelectonics board, it is retrieved in STM32MP15x OTP : +For STMicroelectronics board, it is retrieved in: + + - STM32MP15x OTP: - - OTP_57[31:0] = MAC_ADDR[31:0] - - OTP_58[15:0] = MAC_ADDR[47:32] + - OTP_57[31:0] = MAC_ADDR[31:0] + - OTP_58[15:0] = MAC_ADDR[47:32] -To program a MAC address on virgin OTP words above, you can use the fuse command + - STM32MP13x OTP: + + - OTP_57[31:0] = MAC_ADDR0[31:0] + - OTP_58[15:0] = MAC_ADDR0[47:32] + - OTP_58[31:16] = MAC_ADDR1[15:0] + - OTP_59[31:0] = MAC_ADDR1[47:16] + +To program a MAC address on virgin STM32MP15x OTP words above, you can use the fuse command on bank 0 to access to internal OTP and lock them: +In the next example we are using the 2 OTPs used on STM32MP15x. + Prerequisite: check if a MAC address isn't yet programmed in OTP 1) check OTP: their value must be equal to 0:: @@ -571,8 +640,8 @@ Example to set mac address "12:34:56:78:9a:bc" OTP are protected. It is already done for the board provided by STMicroelectronics. -Coprocessor firmware --------------------- +Coprocessor firmware on STM32MP15x +---------------------------------- U-Boot can boot the coprocessor before the kernel (coprocessor early boot). @@ -678,7 +747,7 @@ All the supported device are exported for dfu-util tool:: You can update the boot device: -- SD card (mmc0) :: +- SD card (mmc0):: $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1.stm32 $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1.stm32 diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst new file mode 100644 index 0000000000000000000000000000000000000000..4e68c2018a50bb1cfea91259c6142ea8668638dd --- /dev/null +++ b/doc/board/ti/am62x_sk.rst @@ -0,0 +1,231 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Vignesh Raghavendra + +Texas Instruments AM62 Platforms +================================ + +Introduction: +------------- +The AM62 SoC family is the follow on AM335x built on the K3 Multicore +SoC architecture platform, providing ultra-low-power modes, dual +display, multi-sensor edge compute, security and other BOM-saving +integrations. The AM62 SoC targets a broad market to enable +applications such as Industrial HMI, PLC/CNC/Robot control, Medical +Equipment, Building Automation, Appliances and more. + +Some highlights of this SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. + Pin-to-pin compatible options for single and quad core are available. +* Cortex-M4F for general-purpose or safety usage. +* Dual display support, providing 24-bit RBG parallel interface and + OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display + resolution. +* Selectable GPU support, up to 8GFLOPS, providing better user experience + in 3D graphic display case and Android. +* PRU(Programmable Realtime Unit) support for customized programmable + interfaces/IOs. +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. +* Dedicated Centralized System Controller for Security, Power, and + Resource Management. +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +More details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiv7 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + +------------------------------------------------------------------------+ + | TIFS | Main R5 | A53 | + +------------------------------------------------------------------------+ + | +--------+ | | | + | | Reset | | | | + | +--------+ | | | + | : | | | + | +--------+ | +-----------+ | | + | | *ROM* |----------|-->| Reset rls | | | + | +--------+ | +-----------+ | | + | | | | : | | + | | ROM | | : | | + | |services| | : | | + | | | | +-------------+ | | + | | | | | *R5 ROM* | | | + | | | | +-------------+ | | + | | |<---------|---|Load and auth| | | + | | | | | tiboot3.bin | | | + | +--------+ | +-------------+ | | + | | |<---------|---| Load sysfw | | | + | | | | | part to TIFS| | | + | | | | | core | | | + | | | | +-------------+ | | + | | | | : | | + | | | | : | | + | | | | : | | + | | | | +-------------+ | | + | | | | | *R5 SPL* | | | + | | | | +-------------+ | | + | | | | | DDR | | | + | | | | | config | | | + | | | | +-------------+ | | + | | | | | Load | | | + | | | | | tispl.bin | | | + | | | | +-------------+ | | + | | | | | Load R5 | | | + | | | | | firmware | | | + | | | | +-------------+ | | + | | |<---------|---| Start A53 | | | + | | | | | and jump to | | | + | | | | | DM fw image | | | + | | | | +-------------+ | | + | | | | | +-----------+ | + | | |----------|-----------------------|---->| Reset rls | | + | | | | | +-----------+ | + | | TIFS | | | : | + | |Services| | | +-----------+ | + | | |<---------|-----------------------|---->|*ATF/OPTEE*| | + | | | | | +-----------+ | + | | | | | : | + | | | | | +-----------+ | + | | |<---------|-----------------------|---->| *A53 SPL* | | + | | | | | +-----------+ | + | | | | | | Load | | + | | | | | | u-boot.img| | + | | | | | +-----------+ | + | | | | | : | + | | | | | +-----------+ | + | | |<---------|-----------------------|---->| *U-Boot* | | + | | | | | +-----------+ | + | | | | | | prompt | | + | | |----------|-----------------------|-----+-----------+-----| + | +--------+ | | | + | | | | + +------------------------------------------------------------------------+ + +- Here TIFS acts as master and provides all the critical services. R5/A53 + requests TIFS to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git + Branch: master + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +5. TI Linux Firmware: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +Build procedure: +---------------- +1. ATF: + +.. code-block:: text + + $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=lite SPD=opteed + +2. OPTEE: + +.. code-block:: text + + $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- CROSS_COMPILE64=aarch64-none-linux-gnu- + +3. U-Boot: + +* 3.1 R5: + +.. code-block:: text + + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am62x_evm_r5_defconfig O=/tmp/r5 + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5 + $ cd + $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=/ti-sysfw/ti-fs-firmware-am62x-gp.bin + +Use the tiboot3.bin generated from last command + +* 3.2 A53: + +.. code-block:: text + + $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig O=/tmp/a53 + $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=/build/k3/lite/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53 + +Target Images +-------------- +Copy the below images to an SD card and boot: + - tiboot3.bin from step 3.1 + - tispl.bin, u-boot.img from 3.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: text + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | |TIFS with board cfg| | + | | | | + | +-------------------+ | + | | | | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: text + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A53 ATF | | + | +-------------------+ | + | | | | + | | A53 OPTEE | | + | +-------------------+ | + | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | + | | A53 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ diff --git a/doc/board/ti/index.rst b/doc/board/ti/index.rst index 014a097178ab98295548fa960042b1a327b687ea..250d9242e82bbe8fbcf7f131e8d83a8a89136054 100644 --- a/doc/board/ti/index.rst +++ b/doc/board/ti/index.rst @@ -8,3 +8,4 @@ Texas Instruments am335x_evm j721e_evm + am62x_sk diff --git a/doc/develop/bloblist.rst b/doc/develop/bloblist.rst index 572aa65d764cdada2e4a92cc6543243807f8bd1d..81643c7674b4644c4d352b9433b4684e004b7c5c 100644 --- a/doc/develop/bloblist.rst +++ b/doc/develop/bloblist.rst @@ -11,6 +11,8 @@ a central structure. Each record of information is assigned a tag so that its owner can find it and update it. Each record is generally described by a C structure defined by the code that owns it. +For the design goals of bloblist, please see the comments at the top of the +`bloblist.h` header file. Passing state through the boot process -------------------------------------- diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst index c72d1b0aaad76871b052181cbc16613628352066..ede880d248c6b0115072f57443781a0cbe556db3 100644 --- a/doc/develop/commands.rst +++ b/doc/develop/commands.rst @@ -169,8 +169,8 @@ by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these .. code-block:: c - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } Writing tests diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst index 5f33f9fbb3275fb29e5da5221ccec4b95e454ba2..a75d637ec3315205b1b3ec9f26f43144505b90e3 100644 --- a/doc/develop/driver-model/design.rst +++ b/doc/develop/driver-model/design.rst @@ -1135,7 +1135,7 @@ constrained systems. To enable driver model in SPL, define CONFIG_SPL_DM. You might want to consider the following option also. See the main README for more details. - - CONFIG_SYS_MALLOC_SIMPLE + - CONFIG_SPL_SYS_MALLOC_SIMPLE - CONFIG_DM_WARN - CONFIG_DM_DEVICE_REMOVE - CONFIG_DM_STDIO diff --git a/doc/develop/driver-model/of-plat.rst b/doc/develop/driver-model/of-plat.rst index 237af38ad4d8b5bc281a962faf26d84bc59f7223..b454f7be85ef42e7321cd0488b67044fcb00b8c5 100644 --- a/doc/develop/driver-model/of-plat.rst +++ b/doc/develop/driver-model/of-plat.rst @@ -707,9 +707,9 @@ Link errors / undefined reference Sometimes dtoc does not find the problem for you, but something is wrong and you get a link error, e.g.:: - :(.u_boot_list_2_udevice_2_spl_test5+0x0): undefined reference to + :(__u_boot_list_2_udevice_2_spl_test5+0x0): undefined reference to `_u_boot_list_2_driver_2_sandbox_spl_test' - /usr/bin/ld: dts/dt-uclass.o:(.u_boot_list_2_uclass_2_misc+0x8): + /usr/bin/ld: dts/dt-uclass.o:(__u_boot_list_2_uclass_2_misc+0x8): undefined reference to `_u_boot_list_2_uclass_driver_2_misc' The first one indicates that the device cannot find its driver. This means that diff --git a/doc/develop/driver-model/serial-howto.rst b/doc/develop/driver-model/serial-howto.rst index 8af79a90f46a38f820bd2240ca21f7f544e45b24..9da0e57eab69bd443c13a98bd114129829c6f705 100644 --- a/doc/develop/driver-model/serial-howto.rst +++ b/doc/develop/driver-model/serial-howto.rst @@ -3,15 +3,6 @@ How to port a serial driver to driver model =========================================== -Almost all of the serial drivers have been converted as at January 2016. These -ones remain: - - * serial_bfin.c - * serial_pxa.c - -The deadline for this work was the end of January 2016. If no one steps -forward to convert these, at some point there may come a patch to remove them! - Here is a suggested approach for converting your serial driver over to driver model. Please feel free to update this file with your ideas and suggestions. diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt index 926e3e83b3fa70024b6633e9987e6cadb060c639..e6ea8d0ef54ba172e01448e694932f4d789ff076 100644 --- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -3,7 +3,8 @@ ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC) -------------------- Required properties: -------------------- -- compatible : Should be "st,stm32mp1-ddr" +- compatible : Should be "st,stm32mp1-ddr" for STM32MP15x + Should be "st,stm32mp13-ddr" for STM32MP13x - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address - clocks : controller clocks handle - clock-names : associated controller clock names @@ -13,6 +14,8 @@ Required properties: the next attributes are DDR parameters, they are generated by DDR tools included in STM32 Cube tool +They are required only in SPL, when TFABOOT is not activated. + info attributes: ---------------- - st,mem-name : name for DDR configuration, simple string for information @@ -24,7 +27,7 @@ controlleur attributes: ----------------------- - st,ctl-reg : controleur values depending of the DDR type (DDR3/LPDDR2/LPDDR3) - for STM32MP15x: 25 values are requested in this order + for STM32MP15x and STM32MP13x: 25 values are requested in this order MSTR MRCTRL0 MRCTRL1 @@ -53,7 +56,7 @@ controlleur attributes: - st,ctl-timing : controleur values depending of frequency and timing parameter of DDR - for STM32MP15x: 12 values are requested in this order + for STM32MP15x and STM32MP13x: 12 values are requested in this order RFSHTMG DRAMTMG0 DRAMTMG1 @@ -68,7 +71,7 @@ controlleur attributes: ODTCFG - st,ctl-map : controleur values depending of address mapping - for STM32MP15x: 9 values are requested in this order + for STM32MP15x and STM32MP13x: 9 values are requested in this order ADDRMAP1 ADDRMAP2 ADDRMAP3 @@ -99,6 +102,19 @@ controlleur attributes: PCFGWQOS0_1 PCFGWQOS1_1 + for STM32MP13x: 11 values are requested in this order + SCHED + SCHED1 + PERFHPR1 + PERFLPR1 + PERFWR1 + PCFGR_0 + PCFGW_0 + PCFGQOS0_0 + PCFGQOS1_0 + PCFGWQOS0_0 + PCFGWQOS1_0 + phyc attributes: ---------------- - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3) @@ -115,8 +131,19 @@ phyc attributes: DX2GCR DX3GCR + for STM32MP13x: 9 values are requested in this order + PGCR + ACIOCR + DXCCR + DSGCR + DCR + ODTCR + ZQ0CR1 + DX0GCR + DX1GCR + - st,phy-timing : phy values depending of frequency and timing parameter of DDR - for STM32MP15x: 10 values are requested in this order + for STM32MP15x and STM32MP13x: 10 values are requested in this order PTR0 PTR1 PTR2 @@ -128,16 +155,18 @@ phyc attributes: MR2 MR3 + for STM32MP13x: 6 values are requested in this order + DX0DLLCR + DX0DQTR + DX0DQSTR + DX1DLLCR + DX1DQTR + DX1DQSTR Example: / { soc { - u-boot,dm-spl; - ddr: ddr@0x5A003000{ - u-boot,dm-spl; - u-boot,dm-pre-reloc; - compatible = "st,stm32mp1-ddr"; reg = <0x5A003000 0x550 diff --git a/doc/device-tree-bindings/regulator/regulator.txt b/doc/device-tree-bindings/regulator/regulator.txt index 6c9a02120fdee37b514ed5889af93c8a296ad2e9..ddb02b7a3c41fa36207eb622a7a871db7b86ca61 100644 --- a/doc/device-tree-bindings/regulator/regulator.txt +++ b/doc/device-tree-bindings/regulator/regulator.txt @@ -36,6 +36,7 @@ Optional properties: - regulator-always-on: regulator should never be disabled - regulator-boot-on: enabled by bootloader/firmware - regulator-ramp-delay: ramp delay for regulator (in uV/us) +- regulator-force-boot-off: disabled during the boot stage - regulator-init-microvolt: a init allowed Voltage value - regulator-state-(standby|mem|disk) type: object diff --git a/doc/device-tree-bindings/spi/hpe,gxp-spi.yaml b/doc/device-tree-bindings/spi/hpe,gxp-spi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5e23de1847cfad6d73e77c751283e4110fd95cbe --- /dev/null +++ b/doc/device-tree-bindings/spi/hpe,gxp-spi.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/hpe,gxp-spi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: HPE GXP SPI Controller + +maintainers: + - Nick Hawkins + - Jean-Marie Verdun + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + const: mikrotik,rb4xx-spi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + spi@c00000200{ + compatible = "hpe,gxp-spi"; + reg = <0xc0000200 0x80>; + #address-cells = <1>; + #size-cells = <0>; + }; + diff --git a/doc/imx/common/imx6.txt b/doc/imx/common/imx6.txt index 9007cfbf587a8339fb8e0eb1fa5b1718ed76dd79..c5554d8d6b33ff14177e3fef66ff0332f82106eb 100644 --- a/doc/imx/common/imx6.txt +++ b/doc/imx/common/imx6.txt @@ -162,3 +162,34 @@ icorem6qdl> nand write ${loadaddr} uboot ${filesize} NAND write: device 0 offset 0x200000, size 0x8fd26 589094 bytes written: OK icorem6qdl> + +SPL Stack size and location notes +--------------------------------- + +If we have CONFIG_MX6_OCRAM_256KB then see Figure 8.4.1 in IMX6DQ Reference +manuals: + - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF + - BOOT ROM stack is at 0x0093FFB8 + - if icache/dcache is enabled (eFuse/strapping controlled) then the + IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to + fit between 0x00907000 and 0x00938000. + - Additionally the BOOT ROM loads what they consider the firmware image + which consists of a 4K header in front of us that contains the IVT, DCD + and some padding thus 'our' max size is really 0x00908000 - 0x00938000 + or 192KB + - Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the + SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + boot media (given that boot media specific offset is configured properly). +and if we don't, see Figure 8-3 in IMX6SDL Reference manuals: + - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF + - BOOT ROM stack is at 0x0091FFB8 + - if icache/dcache is enabled (eFuse/strapping controlled) then the + IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + fit between 0x00907000 and 0x00918000. + - Additionally the BOOT ROM loads what they consider the firmware image + which consists of a 4K header in front of us that contains the IVT, DCD + and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + or 64KB + - Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + boot media (given that boot media specific offset is configured properly). diff --git a/doc/imx/common/imx7.txt b/doc/imx/common/imx7.txt new file mode 100644 index 0000000000000000000000000000000000000000..b9db10341ad89f326de8a5983f48ddb933fcf24a --- /dev/null +++ b/doc/imx/common/imx7.txt @@ -0,0 +1,23 @@ +U-Boot for Freescale i.MX7 + +SPL Stack size and location notes +--------------------------------- +See figure 6-22 in i.MX 7Dual/Solo Reference manuals: + - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to + 0x00946C00. + - Set the stack at the end of the free area section, at 0x00946BB8. + - The BOOT ROM loads what they consider the firmware image + which consists of a 4K header in front of us that contains the IVT, DCD + and some padding. However, the manual also states that the ROM uses the + OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use + this range for stack and malloc, the SPL itself must fit below 0x920000, + or the image will be truncated in at least some boot modes like USB SDP. + Thus our max size is really 0x00920000 - 0x00912000. If necessary, + CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space + for the SPL, but 56KB should be more than enough for the SPL. + - Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding) + The extra padding could be removed, but this value was used historically + based on an incorrect CONFIG_SPL_MAX_SIZE definition. + This allows to write the SPL/U-Boot combination generated with + u-boot-with-spl.imx directly to a boot media (given that boot media specific + offset is configured properly). diff --git a/doc/mkimage.1 b/doc/mkimage.1 index c92e13373268211221fde02629e34e1aea03ee12..759dc2d12f5d787b5646dbcf7649e76365bab38b 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -99,6 +99,30 @@ Set image name to 'image name'. .BI "\-R [" "secondary image name" "]" Some image types support a second image for additional data. For these types, use \-R to specify this second image. +.TS +allbox; +lb lbx +l l. +Image Type Secondary Image Description +pblimage Additional RCW-style header, typically used for PBI commands. +zynqimage, zynqmpimage T{ +Initialization parameters, one per line. Each parameter has the form +.sp +.ti 4 +.I address data +.sp +where +.I address +and +.I data +are hexadecimal integers. The boot ROM will write each +.I data +to +.I address +when loading the image. At most 256 parameters may be specified in this +manner. +T} +.TE .TP .BI "\-d [" "image data file" "]" @@ -110,8 +134,8 @@ Set XIP (execute in place) flag. .TP .BI "\-s" -Create an image with no data. The header will be created, but the image itself -will not contain data (such as U-Boot or any specified kernel). +Don't copy in the image data. Depending on the image type, this may create +just the header, everything but the image data, or nothing at all. .TP .BI "\-v" @@ -176,6 +200,11 @@ Specifies the directory containing keys to use for signing. This directory should contain a private key file .key for use with signing and a certificate .crt (containing the public key) for use with verification. +.TP +.BI "\-G [" "key_file" "]" +Specifies the private key file to use when signing. This option may be used +instead of \-k. + .TP .BI "\-K [" "key_destination" "]" Specifies a compiled device tree binary file (typically .dtb) to write @@ -189,6 +218,13 @@ CONFIG_OF_CONTROL in U-Boot. Specifies the private key file to use when signing. This option may be used instead of \-k. +.TP +.BI "\-g [" "key_name_hint" "]" +Sets the key-name-hint property when used with \-f auto. This is the +part of the key. The directory part is set by \-k. This option also indicates +that the images included in the FIT should be signed. If this option is +specified, \-o must be specified as well. + .TP .BI "\-o [" "signing algorithm" "]" Specifies the algorithm to be used for signing a FIT image. The default is @@ -249,6 +285,15 @@ skipping those for which keys cannot be found. Also add a comment. .B -c """Kernel 3.8 image for production devices""" kernel.itb .fi +.P +Add public keys to u-boot.dtb without needing a FIT to sign. This will also +create a FIT containing an images node with no data named unused.itb. +.nf +.B mkimage -f auto -d /dev/null -k /public/signing-keys -g dev \\\\ +.br +.B -o sha256,rsa2048 -K u-boot.dtb unused.itb +.fi + .P Update an existing FIT image, signing it with additional keys. Add corresponding public keys into u-boot.dtb. This will resign all images @@ -277,6 +322,14 @@ automatic mode. No .its file is required. .B -c """Kernel 4.4 image for production devices""" -d vmlinuz \\\\ .B -b /path/to/rk3288-firefly.dtb -b /path/to/rk3288-jerry.dtb kernel.itb .fi +.P +Create a FIT image containing a signed kernel, using automatic mode. No .its +file is required. +.nf +.B mkimage -f auto -A arm -O linux -T kernel -C none -a 43e00000 -e 0 \\\\ +.br +.B -d vmlinuz -k /secret/signing-keys -g dev -o sha256,rsa2048 kernel.itb +.fi .SH HOMEPAGE http://www.denx.de/wiki/U-Boot/WebHome diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst new file mode 100644 index 0000000000000000000000000000000000000000..7bc1962a7546a2bf515f75f31998c3229eb258d7 --- /dev/null +++ b/doc/usage/cmd/dm.rst @@ -0,0 +1,487 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +dm command +========== + +Synopis +------- + +:: + + dm compat + dm devres + dm drivers + dm static + dm tree + dm uclass + +Description +----------- + +The *dm* command allows viewing information about driver model, including the +tree of devices and list of available uclasses. + + +dm compat +~~~~~~~~~ + +This shows the compatible strings associated with each driver. Often there +is only one, but multiple strings are shown on their own line. These strings +can be looked up in the device tree files for each board, to see which driver is +used for each node. + +dm devres +~~~~~~~~~ + +This shows a list of a `devres` (device resource) records for a device. Some +drivers use the devres API to allocate memory, so that it can be freed +automatically (without any code needed in the driver's remove() method) when the +device is removed. + +This feature is controlled by CONFIG_DEVRES so no useful output is obtained if +this option is disabled. + +dm drivers +~~~~~~~~~~ + +This shows all the available drivers, their uclass and a list of devices that +use that driver, each on its own line. Drivers with no devices are shown with +`` as the driver name. + + +dm mem +~~~~~~ + +This subcommand is really just for debugging and exploration. It can be enabled +with the `CONFIG_DM_STATS` option. + +All output is in hex except that in brackets which is decimal. + +The output consists of a header shows the size of the main device model +structures (struct udevice, struct driver, struct uclass and struct uc_driver) +and the count and memory used by each (number of devices, memory used by +devices, memory used by device names, number of uclasses, memory used by +uclasses). + +After that is a table of information about each type of data that can be +attached to a device, showing the number that have non-null data for that type, +the total size of all that data, the amount of memory used in total, the +amount that would be used if this type uses tags instead and the amount that +would be thus saved. + +The `driver_data` line shows the number of devices which have non-NULL driver +data. + +The `tags` line shows the number of tags and the memory used by those. + +At the bottom is an indication of the total memory usage obtained by undertaking +various changes, none of which is currently implemented in U-Boot: + +With tags + Using tags instead of all attached types + +Singly linked + Using a singly linked list + +driver index + Using a driver index instead of a pointer + +uclass index + Using a uclass index instead of a pointer + +Drop device name + Using empty device names + + +dm static +~~~~~~~~~ + +This shows devices bound by platform data, i.e. not from the device tree. There +are normally none of these, but some boards may use static devices for space +reasons. + + +dm tree +~~~~~~~ + +This shows the full tree of devices including the following fields: + +uclass + Shows the name of the uclass for the device + +Index + Shows the index number of the device, within the uclass. This shows the + ordering within the uclass, but not the sequence number. + +Probed + Shows `+` if the device is active + +Driver + Shows the name of the driver that this device uses + +Name + Shows the device name as well as the tree structure, since child devices are + shown attached to their parent. + + +dm uclass +~~~~~~~~~ + +This shows each uclass along with a list of devices in that uclass. The uclass +ID is shown (e.g. uclass 7) and its name. + +For each device, the format is:: + + n name @ a, seq s + +where `n` is the index within the uclass, `a` is the address of the device in +memory and `s` is the sequence number of the device. + + +Examples +-------- + +dm compat +~~~~~~~~~ + +This example shows an abridged version of the sandbox output:: + + => dm compat + Driver Compatible + -------------------------------- + act8846_reg + sandbox_adder sandbox,adder + axi_sandbox_bus sandbox,axi + blk_partition + bootcount-rtc u-boot,bootcount-rtc + ... + rockchip_rk805 rockchip,rk805 + rockchip,rk808 + rockchip,rk809 + rockchip,rk816 + rockchip,rk817 + rockchip,rk818 + root_driver + rtc-rv8803 microcrystal,rv8803 + epson,rx8803 + epson,rx8900 + ... + wdt_gpio linux,wdt-gpio + wdt_sandbox sandbox,wdt + + +dm devres +~~~~~~~~~ + +This example shows an abridged version of the sandbox test output (running +U-Boot with the -T flag):: + + => dm devres + - root_driver + - demo_shape_drv + - demo_simple_drv + - demo_shape_drv + ... + - h-test + - devres-test + 00000000130194e0 (100 byte) devm_kmalloc_release BIND + - another-test + ... + - syscon@3 + - a-mux-controller + 0000000013025e60 (96 byte) devm_kmalloc_release PROBE + 0000000013025f00 (24 byte) devm_kmalloc_release PROBE + 0000000013026010 (24 byte) devm_kmalloc_release PROBE + 0000000013026070 (24 byte) devm_kmalloc_release PROBE + 00000000130260d0 (24 byte) devm_kmalloc_release PROBE + - syscon@3 + - a-mux-controller + 0000000013026150 (96 byte) devm_kmalloc_release PROBE + 00000000130261f0 (24 byte) devm_kmalloc_release PROBE + 0000000013026300 (24 byte) devm_kmalloc_release PROBE + 0000000013026360 (24 byte) devm_kmalloc_release PROBE + 00000000130263c0 (24 byte) devm_kmalloc_release PROBE + - emul-mux-controller + 0000000013025fa0 (32 byte) devm_kmalloc_release PROBE + - testfdtm0 + - testfdtm1 + ... + - pinmux_spi0_pins + - pinmux_uart0_pins + - pinctrl-single-bits + 0000000013229180 (320 byte) devm_kmalloc_release PROBE + 0000000013229300 (40 byte) devm_kmalloc_release PROBE + 0000000013229370 (160 byte) devm_kmalloc_release PROBE + 000000001322c190 (40 byte) devm_kmalloc_release PROBE + 000000001322c200 (32 byte) devm_kmalloc_release PROBE + - pinmux_i2c0_pins + ... + - reg@0 + - reg@1 + + +dm drivers +~~~~~~~~~~ + +This example shows an abridged version of the sandbox output:: + + => dm drivers + Driver uid uclass Devices + ---------------------------------------------------------- + act8846_reg 087 regulator + sandbox_adder 021 axi adder + adder + axi_sandbox_bus 021 axi axi@0 + ... + da7219 061 misc + demo_shape_drv 001 demo demo_shape_drv + demo_shape_drv + demo_shape_drv + demo_simple_drv 001 demo demo_simple_drv + demo_simple_drv + testfdt_drv 003 testfdt a-test + b-test + d-test + e-test + f-test + g-test + another-test + chosen-test + testbus_drv 005 testbus some-bus + mmio-bus@0 + mmio-bus@1 + dsa-port 039 ethernet lan0 + lan1 + dsa_sandbox 035 dsa dsa-test + eep_sandbox 121 w1_eeprom + ... + pfuze100_regulator 087 regulator + phy_sandbox 077 phy bind-test-child1 + gen_phy@0 + gen_phy@1 + gen_phy@2 + pinconfig 078 pinconfig gpios + gpio0 + gpio1 + gpio2 + gpio3 + i2c + groups + pins + i2s + spi + cs + pinmux_pwm_pins + pinmux_spi0_pins + pinmux_uart0_pins + pinmux_i2c0_pins + pinmux_lcd_pins + pmc_sandbox 017 power-mgr pci@1e,0 + act8846 pmic 080 pmic + max77686_pmic 080 pmic + mc34708_pmic 080 pmic pmic@41 + ... + wdt_gpio 122 watchdog gpio-wdt + wdt_sandbox 122 watchdog wdt@0 + => + + +dm mem +~~~~~~ + +This example shows the sandbox output:: + + > dm mem + Struct sizes: udevice b0, driver 80, uclass 30, uc_driver 78 + Memory: device fe:aea0, device names a16, uclass 5e:11a0 + + Attached type Count Size Cur Tags Save + --------------- ----- ----- ----- ----- ----- + plat 45 a8f aea0 a7c4 6dc (1756) + parent_plat 1a 3b8 aea0 a718 788 (1928) + uclass_plat 3d 6b4 aea0 a7a4 6fc (1788) + priv 8a 68f3 aea0 a8d8 5c8 (1480) + parent_priv 8 38a0 aea0 a6d0 7d0 (2000) + uclass_priv 4e 14a6 aea0 a7e8 6b8 (1720) + driver_data f 0 aea0 a6ec 7b4 (1972) + uclass 6 20 + Attached total 191 cb54 3164 (12644) + tags 0 0 + + Total size: 18b94 (101268) + + With tags: 15a30 (88624) + - singly-linked: 14260 (82528) + - driver index: 13b6e (80750) + - uclass index: 1347c (78972) + Drop device name (not SRAM): a16 (2582) + => + + +dm static +~~~~~~~~~ + +This example shows the sandbox output:: + + => dm static + Driver Address + --------------------------------- + demo_shape_drv 0000562edab8dca0 + demo_simple_drv 0000562edab8dca0 + demo_shape_drv 0000562edab8dc90 + demo_simple_drv 0000562edab8dc80 + demo_shape_drv 0000562edab8dc80 + test_drv 0000562edaae8840 + test_drv 0000562edaae8848 + test_drv 0000562edaae8850 + sandbox_gpio 0000000000000000 + mod_exp_sw 0000000000000000 + sandbox_test_proc 0000562edabb5330 + qfw_sandbox 0000000000000000 + sandbox_timer 0000000000000000 + sandbox_serial 0000562edaa8ed00 + sysreset_sandbox 0000000000000000 + + +dm tree +------- + +This example shows the abridged sandbox output:: + + => dm tree + Class Index Probed Driver Name + ----------------------------------------------------------- + root 0 [ + ] root_driver root_driver + demo 0 [ ] demo_shape_drv |-- demo_shape_drv + demo 1 [ ] demo_simple_drv |-- demo_simple_drv + demo 2 [ ] demo_shape_drv |-- demo_shape_drv + demo 3 [ ] demo_simple_drv |-- demo_simple_drv + demo 4 [ ] demo_shape_drv |-- demo_shape_drv + test 0 [ ] test_drv |-- test_drv + test 1 [ ] test_drv |-- test_drv + test 2 [ ] test_drv |-- test_drv + .. + sysreset 0 [ ] sysreset_sandbox |-- sysreset_sandbox + bootstd 0 [ ] bootstd_drv |-- bootstd + bootmeth 0 [ ] bootmeth_distro | |-- syslinux + bootmeth 1 [ ] bootmeth_efi | `-- efi + reboot-mod 0 [ ] reboot-mode-gpio |-- reboot-mode0 + reboot-mod 1 [ ] reboot-mode-rtc |-- reboot-mode@14 + ... + ethernet 7 [ + ] dsa-port | `-- lan1 + pinctrl 0 [ + ] sandbox_pinctrl_gpio |-- pinctrl-gpio + gpio 1 [ + ] sandbox_gpio | |-- base-gpios + nop 0 [ + ] gpio_hog | | |-- hog_input_active_low + nop 1 [ + ] gpio_hog | | |-- hog_input_active_high + nop 2 [ + ] gpio_hog | | |-- hog_output_low + nop 3 [ + ] gpio_hog | | `-- hog_output_high + gpio 2 [ ] sandbox_gpio | |-- extra-gpios + gpio 3 [ ] sandbox_gpio | `-- pinmux-gpios + i2c 0 [ + ] sandbox_i2c |-- i2c@0 + i2c_eeprom 0 [ ] i2c_eeprom | |-- eeprom@2c + i2c_eeprom 1 [ ] i2c_eeprom_partition | | `-- bootcount@10 + rtc 0 [ ] sandbox_rtc | |-- rtc@43 + rtc 1 [ + ] sandbox_rtc | |-- rtc@61 + i2c_emul_p 0 [ + ] sandbox_i2c_emul_par | |-- emul + i2c_emul 0 [ ] sandbox_i2c_eeprom_e | | |-- emul-eeprom + i2c_emul 1 [ ] sandbox_i2c_rtc_emul | | |-- emul0 + i2c_emul 2 [ + ] sandbox_i2c_rtc_emul | | |-- emull + i2c_emul 3 [ ] sandbox_i2c_pmic_emu | | |-- pmic-emul0 + i2c_emul 4 [ ] sandbox_i2c_pmic_emu | | `-- pmic-emul1 + pmic 0 [ ] sandbox_pmic | |-- sandbox_pmic + regulator 0 [ ] sandbox_buck | | |-- buck1 + regulator 1 [ ] sandbox_buck | | |-- buck2 + regulator 2 [ ] sandbox_ldo | | |-- ldo1 + regulator 3 [ ] sandbox_ldo | | |-- ldo2 + regulator 4 [ ] sandbox_buck | | `-- no_match_by_nodename + pmic 1 [ ] mc34708_pmic | `-- pmic@41 + bootcount 0 [ + ] bootcount-rtc |-- bootcount@0 + bootcount 1 [ ] bootcount-i2c-eeprom |-- bootcount + ... + clk 4 [ ] fixed_clock |-- osc + firmware 0 [ ] sandbox_firmware |-- sandbox-firmware + scmi_agent 0 [ ] sandbox-scmi_agent `-- scmi + clk 5 [ ] scmi_clk |-- protocol@14 + reset 2 [ ] scmi_reset_domain |-- protocol@16 + nop 8 [ ] scmi_voltage_domain `-- regulators + regulator 5 [ ] scmi_regulator |-- reg@0 + regulator 6 [ ] scmi_regulator `-- reg@1 + => + + +dm uclass +~~~~~~~~~ + +This example shows the abridged sandbox output:: + + => dm uclass + uclass 0: root + 0 * root_driver @ 03015460, seq 0 + + uclass 1: demo + 0 demo_shape_drv @ 03015560, seq 0 + 1 demo_simple_drv @ 03015620, seq 1 + 2 demo_shape_drv @ 030156e0, seq 2 + 3 demo_simple_drv @ 030157a0, seq 3 + 4 demo_shape_drv @ 03015860, seq 4 + + uclass 2: test + 0 test_drv @ 03015980, seq 0 + 1 test_drv @ 03015a60, seq 1 + 2 test_drv @ 03015b40, seq 2 + ... + uclass 20: audio-codec + 0 audio-codec @ 030168e0, seq 0 + + uclass 21: axi + 0 adder @ 0301db60, seq 1 + 1 adder @ 0301dc40, seq 2 + 2 axi@0 @ 030217d0, seq 0 + + uclass 22: blk + 0 mmc2.blk @ 0301ca00, seq 0 + 1 mmc1.blk @ 0301cee0, seq 1 + 2 mmc0.blk @ 0301d380, seq 2 + + uclass 23: bootcount + 0 * bootcount@0 @ 0301b3f0, seq 0 + 1 bootcount @ 0301b4b0, seq 1 + 2 bootcount_4@0 @ 0301b570, seq 2 + 3 bootcount_2@0 @ 0301b630, seq 3 + + uclass 24: bootdev + 0 mmc2.bootdev @ 0301cbb0, seq 0 + 1 mmc1.bootdev @ 0301d050, seq 1 + 2 mmc0.bootdev @ 0301d4f0, seq 2 + + ... + uclass 78: pinconfig + 0 gpios @ 03022410, seq 0 + 1 gpio0 @ 030224d0, seq 1 + 2 gpio1 @ 03022590, seq 2 + 3 gpio2 @ 03022650, seq 3 + 4 gpio3 @ 03022710, seq 4 + 5 i2c @ 030227d0, seq 5 + 6 groups @ 03022890, seq 6 + 7 pins @ 03022950, seq 7 + 8 i2s @ 03022a10, seq 8 + 9 spi @ 03022ad0, seq 9 + 10 cs @ 03022b90, seq 10 + 11 pinmux_pwm_pins @ 03022e10, seq 11 + 12 pinmux_spi0_pins @ 03022ed0, seq 12 + 13 pinmux_uart0_pins @ 03022f90, seq 13 + 14 * pinmux_i2c0_pins @ 03023130, seq 14 + 15 * pinmux_lcd_pins @ 030231f0, seq 15 + + ... + uclass 119: virtio + 0 sandbox_virtio1 @ 030220d0, seq 0 + 1 sandbox_virtio2 @ 03022190, seq 1 + + uclass 120: w1 + uclass 121: w1_eeprom + uclass 122: watchdog + 0 * gpio-wdt @ 0301c070, seq 0 + 1 * wdt@0 @ 03021710, seq 1 + + => diff --git a/doc/usage/cmd/loadm.rst b/doc/usage/cmd/loadm.rst new file mode 100644 index 0000000000000000000000000000000000000000..b6571140437dc985a7a45bda74500a26829ae411 --- /dev/null +++ b/doc/usage/cmd/loadm.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +loadm command +============= + +Synopsis +-------- + +:: + + loadm + +Description +----------- + +The loadm command is used to copy memory content from source address +to destination address and, if efi is enabled, will setup a "Mem" efi +boot device. + +The number of transferred bytes must be set by bytes parameter + +src_addr + start address of the memory location to be loaded + +dst_addr + destination address of the byte stream to be loaded + +len + number of bytes to be copied in hexadecimal. Can not be 0 (zero). + +Example +------- + +:: + + => loadm ${kernel_addr} ${kernel_addr_r} ${kernel_size} + loaded bin to memory: size: 12582912 + +Configuration +------------- + +The command is only available if CONFIG_CMD_LOADM=y. + +Return value +------------ + +The return value $? is set 0 (true) if the loading is succefull, and +is set to 1 (false) in case of error. + diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 770418434ad98448a088bdb9244d014b8868af5a..8b98629d6bfe30aee48866ec264d1994c5933151 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -33,6 +33,7 @@ Shell commands cmd/bootz cmd/cbsysinfo cmd/conitrace + cmd/dm cmd/echo cmd/env cmd/event @@ -44,6 +45,7 @@ Shell commands cmd/fatload cmd/for cmd/load + cmd/loadm cmd/loady cmd/mbr cmd/md diff --git a/drivers/Kconfig b/drivers/Kconfig index b26ca8cf70c9ca0a672b47559e2fe595b39b0018..8b6fead3510835bf05f5523a276b050acda3caa3 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -40,6 +40,8 @@ source "drivers/fastboot/Kconfig" source "drivers/firmware/Kconfig" +source "drivers/fuzz/Kconfig" + source "drivers/fpga/Kconfig" source "drivers/gpio/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 67c8af74424e2c7f5ef1c100701acb460f70352d..d63fd1c04d1140bb80e025946113c9425bf10df3 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -115,6 +115,7 @@ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ +obj-$(CONFIG_FUZZ) += fuzz/ obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/ obj-$(CONFIG_DM_RNG) += rng/ endif diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index ce6907e6900812b9ce1fd514a6af0cb3e8c99dea..7715c40365625ef49091d1d8ead93cb23c5234ef 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -113,12 +113,20 @@ config SATA_CEVA config FSL_SATA bool "Enable Freescale SATA controller driver support" + depends on PPC select AHCI select LIBATA + imply LBA48 help Enable this driver to support the SATA controller found in some Freescale PowerPC SoCs. +config FSL_SATA_V2 + bool "Enable support for V2 of the Freescale SATA controller" + depends on FSL_SATA + help + Enable support for V2 of this controller, rather than V1. + config SATA_MV bool "Enable Marvell SATA controller driver support" select AHCI diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index d9fd850c6fae90e7b62a0c47b4f10986f8b87db1..1a2c3c2fe7078c977895e44db50a11ff44e129fb 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -844,138 +844,6 @@ static ulong sata_write_common(struct ahci_uc_priv *uc_priv, return rc; } -#if !CONFIG_IS_ENABLED(AHCI) -static int ahci_init_one(int pdev) -{ - int rc; - struct ahci_uc_priv *uc_priv = NULL; - - uc_priv = malloc(sizeof(struct ahci_uc_priv)); - if (!uc_priv) - return -ENOMEM; - - memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); - uc_priv->dev = pdev; - - uc_priv->host_flags = ATA_FLAG_SATA - | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO - | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - - uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; - - /* initialize adapter */ - rc = ahci_host_init(uc_priv); - if (rc) - goto err_out; - - ahci_print_info(uc_priv); - - /* Save the uc_private struct to block device struct */ - sata_dev_desc[pdev].priv = uc_priv; - - return 0; - -err_out: - if (uc_priv) - free(uc_priv); - return rc; -} - -int init_sata(int dev) -{ - struct ahci_uc_priv *uc_priv = NULL; - -#if defined(CONFIG_MX6) - if (!is_mx6dq() && !is_mx6dqp()) - return 1; -#endif - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { - printf("The sata index %d is out of ranges\n\r", dev); - return -1; - } - - ahci_init_one(dev); - - uc_priv = sata_dev_desc[dev].priv; - - return dwc_ahci_start_ports(uc_priv) ? 1 : 0; -} - -int reset_sata(int dev) -{ - struct ahci_uc_priv *uc_priv; - struct sata_host_regs *host_mmio; - - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { - printf("The sata index %d is out of ranges\n\r", dev); - return -1; - } - - uc_priv = sata_dev_desc[dev].priv; - if (NULL == uc_priv) - /* not initialized, so nothing to reset */ - return 0; - - host_mmio = uc_priv->mmio_base; - setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); - while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) - udelay(100); - - free(uc_priv); - memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc)); - - return 0; -} - -int sata_port_status(int dev, int port) -{ - struct sata_port_regs *port_mmio; - struct ahci_uc_priv *uc_priv = NULL; - - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) - return -EINVAL; - - if (sata_dev_desc[dev].priv == NULL) - return -ENODEV; - - uc_priv = sata_dev_desc[dev].priv; - port_mmio = uc_priv->port[port].port_mmio; - - return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; -} - -/* - * SATA interface between low level driver and command layer - */ -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - - return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, - buffer); -} - -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - - return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, - buffer); -} - -int scan_sata(int dev) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - struct blk_desc *pdev = &sata_dev_desc[dev]; - - return dwc_ahsata_scan_common(uc_priv, pdev); -} -#endif /* CONFIG_IS_ENABLED(AHCI) */ - -#if CONFIG_IS_ENABLED(AHCI) - int dwc_ahsata_port_status(struct udevice *dev, int port) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); @@ -1109,4 +977,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = { .probe = dwc_ahsata_probe, }; #endif -#endif diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index d1bab931895a60351a955c49f918fd24dcaa1a84..6db4247368eb7ee7d5dbe0c815146b47f645d02d 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -6,10 +6,13 @@ */ #include +#include #include #include #include #include +#include +#include #include #include #include @@ -21,33 +24,6 @@ #include #include "fsl_sata.h" -#if CONFIG_IS_ENABLED(BLK) -#include -#include -#include -#include -#else -#ifndef CONFIG_SYS_SATA1_FLAGS - #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#endif -#ifndef CONFIG_SYS_SATA2_FLAGS - #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#endif - -static struct fsl_sata_info fsl_sata_info[] = { -#ifdef CONFIG_SATA1 - {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS}, -#else - {0, 0}, -#endif -#ifdef CONFIG_SATA2 - {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS}, -#else - {0, 0}, -#endif -}; -#endif - static inline void sdelay(unsigned long sec) { unsigned long i; @@ -86,11 +62,7 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask, return (i < timeout_msec) ? 0 : -1; } -#if !CONFIG_IS_ENABLED(BLK) -int init_sata(int dev) -#else static int init_sata(struct fsl_ata_priv *priv, int dev) -#endif { u32 length, align; cmd_hdr_tbl_t *cmd_hdr; @@ -129,15 +101,9 @@ static int init_sata(struct fsl_ata_priv *priv, int dev) snprintf(sata->name, 12, "SATA%d:", dev); /* Set the controller register base address to device struct */ -#if !CONFIG_IS_ENABLED(BLK) - sata_dev_desc[dev].priv = (void *)sata; - reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base); - sata->dma_flag = fsl_sata_info[dev].flags; -#else reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev); sata->dma_flag = priv->flag; priv->fsl_sata = sata; -#endif sata->reg_base = reg; /* Allocate the command header table, 4 bytes aligned */ @@ -738,17 +704,11 @@ static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt, /* * SATA interface between low level driver and command layer */ -#if !CONFIG_IS_ENABLED(BLK) -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) { struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif u32 rc; if (sata->lba48) @@ -760,17 +720,11 @@ static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, return rc; } -#if !CONFIG_IS_ENABLED(BLK) -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) { struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif u32 rc; if (sata->lba48) { @@ -801,17 +755,11 @@ static void fsl_sata_identify(fsl_sata_t *sata, u16 *id) ata_swap_buf_le16(id, ATA_ID_WORDS); } -#if !CONFIG_IS_ENABLED(BLK) -int scan_sata(int dev) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static int scan_sata(struct udevice *dev) { struct blk_desc *desc = dev_get_uclass_plat(dev); struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif unsigned char serial[ATA_ID_SERNO_LEN + 1]; unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; @@ -853,22 +801,12 @@ static int scan_sata(struct udevice *dev) debug("Device supports LBA28\n\r"); #endif -#if !CONFIG_IS_ENABLED(BLK) - memcpy(sata_dev_desc[dev].product, serial, sizeof(serial)); - memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware)); - memcpy(sata_dev_desc[dev].vendor, product, sizeof(product)); - sata_dev_desc[dev].lba = (u32)n_sectors; -#ifdef CONFIG_LBA48 - sata_dev_desc[dev].lba48 = sata->lba48; -#endif -#else memcpy(desc->product, serial, sizeof(serial)); memcpy(desc->revision, firmware, sizeof(firmware)); memcpy(desc->vendor, product, sizeof(product)); desc->lba = n_sectors; #ifdef CONFIG_LBA48 desc->lba48 = sata->lba48; -#endif #endif /* Get the NCQ queue depth from device */ @@ -890,7 +828,6 @@ static int scan_sata(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(BLK) static const struct blk_ops sata_fsl_blk_ops = { .read = sata_read, .write = sata_write, @@ -1042,4 +979,3 @@ U_BOOT_DRIVER(fsl_ahci) = { .remove = fsl_ata_remove, .priv_auto = sizeof(struct fsl_ata_priv), }; -#endif diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h index 5b9daa79e02353109c96505c3429b94f9e448df8..e1ea8eb3a183b852f5672472401768291cc13e08 100644 --- a/drivers/ata/fsl_sata.h +++ b/drivers/ata/fsl_sata.h @@ -319,7 +319,6 @@ typedef struct fsl_sata { #define READ_CMD 0 #define WRITE_CMD 1 -#if CONFIG_IS_ENABLED(BLK) struct fsl_ata_priv { u32 base; u32 flag; @@ -327,6 +326,5 @@ struct fsl_ata_priv { u32 offset; fsl_sata_t *fsl_sata; }; -#endif #endif /* __FSL_SATA_H__ */ diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h index bea4322c919d3f6f7bc7aae5a66a790110fa5664..9ad09e5461d23eda67143f2284b8f8464ac45575 100644 --- a/drivers/ata/sata_sil.h +++ b/drivers/ata/sata_sil.h @@ -212,12 +212,10 @@ enum { CMD_ERR = 0x21, }; -#if CONFIG_IS_ENABLED(BLK) #define ATA_MAX_PORTS 32 struct sil_sata_priv { int port_num; struct sil_sata *sil_sata_desc[ATA_MAX_PORTS]; }; -#endif #endif diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index d6d1c6e32ccc1f71a4f90f80155727fd3fe239de..b5b482086af35d8de89cd43bf20eb68c2812ab3e 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -218,3 +218,19 @@ config IDE_RESET must be defined in a board-specific file. endif # IDE + +config LBA48 + bool "Enable LBA support for disks larger than 137GB" + depends on HAVE_BLOCK_DEVICE + help + Set this to enable support for disks larger than 137GB. + Also look at CONFIG_SYS_64BIT_LBA. Without both of these, LBA48 + support uses 32bit variables and will 'only' support disks up to + 2.1TB. + +config SYS_64BIT_LBA + bool "Enable 64bit number of blocks on a block device" + depends on HAVE_BLOCK_DEVICE + help + Make the block subsystem use 64bit sector addresses, rather than the + default of 32bit. diff --git a/drivers/block/ide.c b/drivers/block/ide.c index e8518ff3a11a2c38974aa1322d7e5b15789db1ba..3270a9f032f3de0cb0717bd998be789242aae078 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -695,15 +695,6 @@ void ide_init(void) unsigned char c; int i, bus; -#ifdef CONFIG_IDE_PREINIT - WATCHDOG_RESET(); - - if (ide_preinit()) { - puts("ide_preinit failed\n"); - return; - } -#endif /* CONFIG_IDE_PREINIT */ - WATCHDOG_RESET(); /* ATAPI Drives seems to need a proper IDE Reset */ diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 66ce4cc29baafffd1b1d949c8dac62cdec3ae898..e918f74694640678bf81bc1154be3f8c9891d789 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -237,4 +237,15 @@ config SYS_BOOTCOUNT_MAGIC help Set the magic value used for the boot counter. +choice + prompt "Endianness of bootcount accessors" + default SYS_BOOTCOUNT_LE + +config SYS_BOOTCOUNT_LE + bool "Little endian accessors" + +config SYS_BOOTCOUNT_BE + bool "Big endian accessors" + +endchoice endif diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a62b81a1232e9f3f3d273ef1819370cf4146b5b2..fd9e1a80c6aa0c2f4c24e22a15444577ac7f6acc 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -166,22 +166,6 @@ config CLK_SCMI by a SCMI agent based on SCMI clock protocol communication with a SCMI server. -config CLK_STM32F - bool "Enable clock driver support for STM32F family" - depends on CLK && (STM32F7 || STM32F4) - default y - help - This clock driver adds support for RCC clock management - for STM32F4 and STM32F7 SoCs. - -config CLK_STM32MP1 - bool "Enable RCC clock driver for STM32MP1" - depends on ARCH_STM32MP && CLK - default y - help - Enable the STM32 clock (RCC) driver. Enable support for - manipulating STM32MP1's on-SoC clocks. - config CLK_HSDK bool "Enable cgu clock driver for HSDK boards" depends on CLK && TARGET_HSDK @@ -251,6 +235,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f5b553172c271f5524a0d176a2a9fe2f4e7440aa..c274cda77c6abf2ca0946cb5f6d6f8d2688f0d39 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -23,6 +23,8 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ +obj-$(CONFIG_ARCH_STM32) += stm32/ +obj-$(CONFIG_ARCH_STM32MP) += stm32/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o @@ -39,8 +41,6 @@ obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ -obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o -obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o obj-$(CONFIG_CLK_VERSAL) += clk_versal.o @@ -53,4 +53,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o -obj-$(CONFIG_STM32H7) += clk_stm32h7.o diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index a1b4496ca2c6cf98b40991553f1f876e230b37eb..623c6915b81f5ba1fef1dfa249503bd7880c5353 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -173,6 +174,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = ast2500_get_uart_clk_rate(priv->scu, 5); break; default: + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } @@ -425,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) return new_rate; } +#define SCU_CLKSTOP_SDIO 27 +static ulong ast2500_enable_sdclk(struct ast2500_scu *scu) +{ + u32 reset_bit; + u32 clkstop_bit; + + reset_bit = BIT(ASPEED_RESET_SDIO); + clkstop_bit = BIT(SCU_CLKSTOP_SDIO); + + setbits_le32(&scu->sysreset_ctrl1, reset_bit); + udelay(100); + //enable clk + clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); + mdelay(10); + clrbits_le32(&scu->sysreset_ctrl1, reset_bit); + + return 0; +} + static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) { struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); @@ -438,6 +459,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) new_rate = ast2500_configure_d2pll(priv->scu, rate); break; default: + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } @@ -479,7 +501,11 @@ static int ast2500_clk_enable(struct clk *clk) case ASPEED_CLK_D2PLL: ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); break; + case ASPEED_CLK_GATE_SDCLK: + ast2500_enable_sdclk(priv->scu); + break; default: + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index f191b0f317076a8627e287771869ae9e50fd56dd..0df1dc3718d3bee41d387f2eaf48e01f5f42563c 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk) rate = ast2600_get_uart_huxclk_rate(priv->scu); break; default: - debug("can't get clk rate\n"); + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } @@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk) case ASPEED_CLK_GATE_SDCLK: ast2600_enable_sdclk(priv->scu); break; - case ASPEED_CLK_GATE_SDEXTCLK: + case ASPEED_CLK_SDIO: ast2600_enable_extsdclk(priv->scu); break; case ASPEED_CLK_GATE_EMMCCLK: ast2600_enable_emmcclk(priv->scu); break; - case ASPEED_CLK_GATE_EMMCEXTCLK: + case ASPEED_CLK_EMMC: ast2600_enable_extemmcclk(priv->scu); break; case ASPEED_CLK_GATE_FSICLK: @@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk) ast2600_enable_rsaclk(priv->scu); break; default: - pr_err("can't enable clk\n"); + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index 5aaabcf0b449676b3997f3d31a22bef77d0d86b2..d172fed24c9d93cedbb66e200af8087d2fdf97b8 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019-2020 Linaro Limited + * Copyright (C) 2019-2022 Linaro Limited */ #define LOG_CATEGORY UCLASS_CLK @@ -13,8 +13,17 @@ #include #include +/** + * struct scmi_clk_priv - Private data for SCMI clocks + * @channel: Reference to the SCMI channel to use + */ +struct scmi_clk_priv { + struct scmi_channel *channel; +}; + static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks) { + struct scmi_clk_priv *priv = dev_get_priv(dev); struct scmi_clk_protocol_attr_out out; struct scmi_msg msg = { .protocol_id = SCMI_PROTOCOL_ID_CLOCK, @@ -24,7 +33,7 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks) }; int ret; - ret = devm_scmi_process_msg(dev, &msg); + ret = devm_scmi_process_msg(dev, priv->channel, &msg); if (ret) return ret; @@ -35,6 +44,7 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks) static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name) { + struct scmi_clk_priv *priv = dev_get_priv(dev); struct scmi_clk_attribute_in in = { .clock_id = clkid, }; @@ -49,7 +59,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name) }; int ret; - ret = devm_scmi_process_msg(dev, &msg); + ret = devm_scmi_process_msg(dev, priv->channel, &msg); if (ret) return ret; @@ -60,6 +70,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name) static int scmi_clk_gate(struct clk *clk, int enable) { + struct scmi_clk_priv *priv = dev_get_priv(clk->dev); struct scmi_clk_state_in in = { .clock_id = clk->id, .attributes = enable, @@ -70,7 +81,7 @@ static int scmi_clk_gate(struct clk *clk, int enable) in, out); int ret; - ret = devm_scmi_process_msg(clk->dev, &msg); + ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg); if (ret) return ret; @@ -89,6 +100,7 @@ static int scmi_clk_disable(struct clk *clk) static ulong scmi_clk_get_rate(struct clk *clk) { + struct scmi_clk_priv *priv = dev_get_priv(clk->dev); struct scmi_clk_rate_get_in in = { .clock_id = clk->id, }; @@ -98,7 +110,7 @@ static ulong scmi_clk_get_rate(struct clk *clk) in, out); int ret; - ret = devm_scmi_process_msg(clk->dev, &msg); + ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg); if (ret < 0) return ret; @@ -111,6 +123,7 @@ static ulong scmi_clk_get_rate(struct clk *clk) static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) { + struct scmi_clk_priv *priv = dev_get_priv(clk->dev); struct scmi_clk_rate_set_in in = { .clock_id = clk->id, .flags = SCMI_CLK_RATE_ROUND_CLOSEST, @@ -123,7 +136,7 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) in, out); int ret; - ret = devm_scmi_process_msg(clk->dev, &msg); + ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg); if (ret < 0) return ret; @@ -136,10 +149,15 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) static int scmi_clk_probe(struct udevice *dev) { + struct scmi_clk_priv *priv = dev_get_priv(dev); struct clk *clk; size_t num_clocks, i; int ret; + ret = devm_scmi_of_get_channel(dev, &priv->channel); + if (ret) + return ret; + if (!CONFIG_IS_ENABLED(CLK_CCF)) return 0; @@ -186,5 +204,6 @@ U_BOOT_DRIVER(scmi_clock) = { .name = "scmi_clk", .id = UCLASS_CLK, .ops = &scmi_clk_ops, - .probe = &scmi_clk_probe, + .probe = scmi_clk_probe, + .priv_auto = sizeof(struct scmi_clk_priv *), }; diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..eac3fc1e9df5d7a3cdd4bd9021a64a7343326c18 --- /dev/null +++ b/drivers/clk/stm32/Kconfig @@ -0,0 +1,23 @@ +config CLK_STM32F + bool "Enable clock driver support for STM32F family" + depends on CLK && (STM32F7 || STM32F4) + default y + help + This clock driver adds support for RCC clock management + for STM32F4 and STM32F7 SoCs. + +config CLK_STM32H7 + bool "Enable clock driver support for STM32H7 family" + depends on CLK && STM32H7 + default y + help + This clock driver adds support for RCC clock management + for STM32H7 SoCs. + +config CLK_STM32MP1 + bool "Enable RCC clock driver for STM32MP15" + depends on ARCH_STM32MP && CLK + default y if STM32MP15x + help + Enable the STM32 clock (RCC) driver. Enable support for + manipulating STM32MP15's on-SoC clocks. diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f66f29540336479e81bf274959c2a4a967b775fb --- /dev/null +++ b/drivers/clk/stm32/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2022, STMicroelectronics - All Rights Reserved + +obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o +obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o +obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/stm32/clk-stm32f.c similarity index 100% rename from drivers/clk/clk_stm32f.c rename to drivers/clk/stm32/clk-stm32f.c diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c similarity index 100% rename from drivers/clk/clk_stm32h7.c rename to drivers/clk/stm32/clk-stm32h7.c diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c similarity index 100% rename from drivers/clk/clk_stm32mp1.c rename to drivers/clk/stm32/clk-stm32mp1.c diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 74beb4d8ebda13815788d427f0f05c3c028125b8..0dd65934b361b243e72c61e88afa2d36d98d6e82 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -73,6 +73,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = { .family = "J721S2", .data = &j721s2_clk_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_AM625 + { + .family = "AM62X", + .data = &am62x_clk_platdata, + }, #endif { /* sentinel */ } }; diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 408a8d8e28b1ea747d9013fa59a71c773fdd16a8..8eb0070d222e4f991cca720da3861f00dab8ebdc 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -15,7 +15,7 @@ config SPL_DM Enable driver model in SPL. You will need to provide a suitable malloc() implementation. If you are not using the full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, - consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you + consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses and devices in SPL, so 1KB should be enable. See @@ -28,7 +28,7 @@ config TPL_DM Enable driver model in TPL. You will need to provide a suitable malloc() implementation. If you are not using the full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, - consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you + consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses and devices in SPL, so 1KB should be enough. See @@ -43,7 +43,7 @@ config VPL_DM Enable driver model in VPL. You will need to provide a suitable malloc() implementation. If you are not using the full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, - consider using CONFIG_SYS_MALLOC_SIMPLE. + consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. config DM_WARN bool "Enable warnings in driver model" @@ -75,6 +75,27 @@ config DM_DEBUG help Say Y here if you want to compile in debug messages in DM core. +config DM_STATS + bool "Collect and show driver model stats" + depends on DM + default y if SANDBOX + help + Enable this to collect and display memory statistics about driver + model. This can help to figure out where all the memory is going and + to find optimisations. + + To display the memory stats, use the 'dm mem' command. + +config SPL_DM_STATS + bool "Collect and show driver model stats in SPL" + depends on DM_SPL + help + Enable this to collect and display memory statistics about driver + model. This can help to figure out where all the memory is going and + to find optimisations. + + The stats are displayed just before SPL boots to the next phase. + config DM_DEVICE_REMOVE bool "Support device removal" depends on DM @@ -89,8 +110,7 @@ config DM_DEVICE_REMOVE config DM_EVENT bool "Support events with driver model" - depends on DM - imply EVENT + depends on DM && EVENT default y if SANDBOX help This enables support for generating events related to driver model @@ -225,7 +245,7 @@ config SPL_SYSCON config TPL_SYSCON bool "Support system controllers in TPL" - depends on SPL_REGMAP + depends on TPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index 73d2e9e4208180a72d3874d1e74c06526552c6dd..a86b9325dd8d68047c52c54446ef2be2ef8290d7 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -29,7 +29,7 @@ int device_chld_unbind(struct udevice *dev, struct driver *drv) assert(dev); - list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + device_foreach_child_safe(pos, n, dev) { if (drv && (pos->driver != drv)) continue; @@ -52,7 +52,7 @@ int device_chld_remove(struct udevice *dev, struct driver *drv, assert(dev); - list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + device_foreach_child_safe(pos, n, dev) { int ret; if (drv && (pos->driver != drv)) diff --git a/drivers/core/device.c b/drivers/core/device.c index 3ab2583df3885cf99a9c2255037339a774491852..d9ce546c0c440cb5ea481d2a3c8f94b2d52d5f41 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -284,8 +284,7 @@ int device_reparent(struct udevice *dev, struct udevice *new_parent) assert(dev); assert(new_parent); - list_for_each_entry_safe(pos, n, &dev->parent->child_head, - sibling_node) { + device_foreach_child_safe(pos, n, dev->parent) { if (pos->driver != dev->driver) continue; @@ -328,13 +327,8 @@ static void *alloc_priv(int size, uint flags) * within this range at the start. The driver can then * use normal flush-after-write, invalidate-before-read * procedures. - * - * TODO(sjg@chromium.org): Drop this microblaze - * exception. */ -#ifndef CONFIG_MICROBLAZE flush_dcache_range((ulong)priv, (ulong)priv + size); -#endif } } else { priv = calloc(1, size); @@ -680,6 +674,71 @@ void *dev_get_parent_priv(const struct udevice *dev) return dm_priv_to_rw(dev->parent_priv_); } +void *dev_get_attach_ptr(const struct udevice *dev, enum dm_tag_t tag) +{ + switch (tag) { + case DM_TAG_PLAT: + return dev_get_plat(dev); + case DM_TAG_PARENT_PLAT: + return dev_get_parent_plat(dev); + case DM_TAG_UC_PLAT: + return dev_get_uclass_plat(dev); + case DM_TAG_PRIV: + return dev_get_priv(dev); + case DM_TAG_PARENT_PRIV: + return dev_get_parent_priv(dev); + case DM_TAG_UC_PRIV: + return dev_get_uclass_priv(dev); + default: + return NULL; + } +} + +int dev_get_attach_size(const struct udevice *dev, enum dm_tag_t tag) +{ + const struct udevice *parent = dev_get_parent(dev); + const struct uclass *uc = dev->uclass; + const struct uclass_driver *uc_drv = uc->uc_drv; + const struct driver *parent_drv = NULL; + int size = 0; + + if (parent) + parent_drv = parent->driver; + + switch (tag) { + case DM_TAG_PLAT: + size = dev->driver->plat_auto; + break; + case DM_TAG_PARENT_PLAT: + if (parent) { + size = parent_drv->per_child_plat_auto; + if (!size) + size = parent->uclass->uc_drv->per_child_plat_auto; + } + break; + case DM_TAG_UC_PLAT: + size = uc_drv->per_device_plat_auto; + break; + case DM_TAG_PRIV: + size = dev->driver->priv_auto; + break; + case DM_TAG_PARENT_PRIV: + if (parent) { + size = parent_drv->per_child_auto; + if (!size) + size = parent->uclass->uc_drv->per_child_auto; + } + break; + case DM_TAG_UC_PRIV: + size = uc_drv->per_device_auto; + break; + default: + break; + } + + return size; +} + static int device_get_device_tail(struct udevice *dev, int ret, struct udevice **devp) { @@ -729,7 +788,7 @@ int device_get_child(const struct udevice *parent, int index, { struct udevice *dev; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { if (!index--) return device_get_device_tail(dev, 0, devp); } @@ -742,7 +801,7 @@ int device_get_child_count(const struct udevice *parent) struct udevice *dev; int count = 0; - list_for_each_entry(dev, &parent->child_head, sibling_node) + device_foreach_child(dev, parent) count++; return count; @@ -753,7 +812,7 @@ int device_get_decendent_count(const struct udevice *parent) const struct udevice *dev; int count = 1; - list_for_each_entry(dev, &parent->child_head, sibling_node) + device_foreach_child(dev, parent) count += device_get_decendent_count(dev); return count; @@ -766,7 +825,7 @@ int device_find_child_by_seq(const struct udevice *parent, int seq, *devp = NULL; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { if (dev->seq_ == seq) { *devp = dev; return 0; @@ -795,7 +854,7 @@ int device_find_child_by_of_offset(const struct udevice *parent, int of_offset, *devp = NULL; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { if (dev_of_offset(dev) == of_offset) { *devp = dev; return 0; @@ -824,7 +883,7 @@ static struct udevice *_device_find_global_by_ofnode(struct udevice *parent, if (ofnode_equal(dev_ofnode(parent), ofnode)) return parent; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { found = _device_find_global_by_ofnode(dev, ofnode); if (found) return found; @@ -902,7 +961,7 @@ int device_find_first_inactive_child(const struct udevice *parent, struct udevice *dev; *devp = NULL; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { if (!device_active(dev) && device_get_uclass_id(dev) == uclass_id) { *devp = dev; @@ -920,7 +979,7 @@ int device_find_first_child_by_uclass(const struct udevice *parent, struct udevice *dev; *devp = NULL; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { if (device_get_uclass_id(dev) == uclass_id) { *devp = dev; return 0; @@ -937,7 +996,7 @@ int device_find_child_by_namelen(const struct udevice *parent, const char *name, *devp = NULL; - list_for_each_entry(dev, &parent->child_head, sibling_node) { + device_foreach_child(dev, parent) { if (!strncmp(dev->name, name, len) && strlen(dev->name) == len) { *devp = dev; @@ -1125,9 +1184,7 @@ bool device_is_compatible(const struct udevice *dev, const char *compat) bool of_machine_is_compatible(const char *compat) { - const void *fdt = gd->fdt_blob; - - return !fdt_node_check_compatible(fdt, 0, compat); + return ofnode_device_is_compatible(ofnode_root(), compat); } int dev_disable_by_path(const char *path) diff --git a/drivers/core/devres.c b/drivers/core/devres.c index 313ddc7089c967288887c53a2280a3d3e7caf4e0..78914bdf7f210c15e7eb75453e0be95e92812505 100644 --- a/drivers/core/devres.c +++ b/drivers/core/devres.c @@ -232,7 +232,7 @@ static void dump_resources(struct udevice *dev, int depth) (unsigned long)dr->size, dr->name, devres_phase_name[dr->phase]); - list_for_each_entry(child, &dev->child_head, sibling_node) + device_foreach_child(child, dev) dump_resources(child, depth + 1); } diff --git a/drivers/core/dump.c b/drivers/core/dump.c index f2f9cacc56c4d8af84645a849cc32800acede786..1c1f7e4d3082b73ce7d6c2154a6b7642d9611b13 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -39,13 +39,13 @@ static void show_devices(struct udevice *dev, int depth, int last_flag) printf("%s\n", dev->name); - list_for_each_entry(child, &dev->child_head, sibling_node) { + device_foreach_child(child, dev) { is_last = list_is_last(&child->sibling_node, &dev->child_head); show_devices(child, depth + 1, (last_flag << 1) | is_last); } } -void dm_dump_all(void) +void dm_dump_tree(void) { struct udevice *root; @@ -89,8 +89,6 @@ void dm_dump_uclass(void) continue; printf("uclass %d: %s\n", id, uc->uc_drv->name); - if (list_empty(&uc->dev_head)) - continue; uclass_foreach_dev(dev, uc) { dm_display_line(dev, i); i++; @@ -171,8 +169,79 @@ void dm_dump_static_driver_info(void) puts("Driver Address\n"); puts("---------------------------------\n"); - for (entry = drv; entry != drv + n_ents; entry++) { - printf("%-25.25s @%08lx\n", entry->name, - (ulong)map_to_sysmem(entry->plat)); + for (entry = drv; entry != drv + n_ents; entry++) + printf("%-25.25s %p\n", entry->name, entry->plat); +} + +void dm_dump_mem(struct dm_stats *stats) +{ + int total, total_delta; + int i; + + /* Support SPL printf() */ + printf("Struct sizes: udevice %x, driver %x, uclass %x, uc_driver %x\n", + (int)sizeof(struct udevice), (int)sizeof(struct driver), + (int)sizeof(struct uclass), (int)sizeof(struct uclass_driver)); + printf("Memory: device %x:%x, device names %x, uclass %x:%x\n", + stats->dev_count, stats->dev_size, stats->dev_name_size, + stats->uc_count, stats->uc_size); + printf("\n"); + printf("%-15s %5s %5s %5s %5s %5s\n", "Attached type", "Count", + "Size", "Cur", "Tags", "Save"); + printf("%-15s %5s %5s %5s %5s %5s\n", "---------------", "-----", + "-----", "-----", "-----", "-----"); + total_delta = 0; + for (i = 0; i < DM_TAG_ATTACH_COUNT; i++) { + int cur_size, new_size, delta; + + cur_size = stats->dev_count * sizeof(struct udevice); + new_size = stats->dev_count * (sizeof(struct udevice) - + sizeof(void *)); + /* + * Let's assume we can fit each dmtag_node into 32 bits. We can + * limit the 'tiny tags' feature to SPL with + * CONFIG_SPL_SYS_MALLOC_F_LEN <= 64KB, so needing 14 bits to + * point to anything in that region (with 4-byte alignment). + * So: + * 4 bits for tag + * 14 bits for offset of dev + * 14 bits for offset of data + */ + new_size += stats->attach_count[i] * sizeof(u32); + delta = cur_size - new_size; + total_delta += delta; + printf("%-16s %5x %6x %6x %6x %6x (%d)\n", tag_get_name(i), + stats->attach_count[i], stats->attach_size[i], + cur_size, new_size, delta > 0 ? delta : 0, delta); } + printf("%-16s %5x %6x\n", "uclass", stats->uc_attach_count, + stats->uc_attach_size); + printf("%-16s %5x %6x %5s %5s %6x (%d)\n", "Attached total", + stats->attach_count_total + stats->uc_attach_count, + stats->attach_size_total + stats->uc_attach_size, "", "", + total_delta > 0 ? total_delta : 0, total_delta); + printf("%-16s %5x %6x\n", "tags", stats->tag_count, stats->tag_size); + printf("\n"); + printf("Total size: %x (%d)\n", stats->total_size, stats->total_size); + printf("\n"); + + total = stats->total_size; + total -= total_delta; + printf("With tags: %x (%d)\n", total, total); + + /* Use singly linked lists in struct udevice (3 nodes in each) */ + total -= sizeof(void *) * 3 * stats->dev_count; + printf("- singly-linked: %x (%d)\n", total, total); + + /* Use an index into the struct_driver list instead of a pointer */ + total = total + stats->dev_count * (1 - sizeof(void *)); + printf("- driver index: %x (%d)\n", total, total); + + /* Same with the uclass */ + total = total + stats->dev_count * (1 - sizeof(void *)); + printf("- uclass index: %x (%d)\n", total, total); + + /* Drop the device name */ + printf("Drop device name (not SRAM): %x (%d)\n", stats->dev_name_size, + stats->dev_name_size); } diff --git a/drivers/core/root.c b/drivers/core/root.c index 17dd1205a32f2f88d9229c571b7b712ea91e94d9..f24ddfa52185d1b816f2d52d0da308681ca2b3c8 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -449,6 +449,59 @@ void dm_get_stats(int *device_countp, int *uclass_countp) *uclass_countp = uclass_get_count(); } +void dev_collect_stats(struct dm_stats *stats, const struct udevice *parent) +{ + const struct udevice *dev; + int i; + + stats->dev_count++; + stats->dev_size += sizeof(struct udevice); + stats->dev_name_size += strlen(parent->name) + 1; + for (i = 0; i < DM_TAG_ATTACH_COUNT; i++) { + int size = dev_get_attach_size(parent, i); + + if (size || + (i == DM_TAG_DRIVER_DATA && parent->driver_data)) { + stats->attach_count[i]++; + stats->attach_size[i] += size; + stats->attach_count_total++; + stats->attach_size_total += size; + } + } + + list_for_each_entry(dev, &parent->child_head, sibling_node) + dev_collect_stats(stats, dev); +} + +void uclass_collect_stats(struct dm_stats *stats) +{ + struct uclass *uc; + + list_for_each_entry(uc, gd->uclass_root, sibling_node) { + int size; + + stats->uc_count++; + stats->uc_size += sizeof(struct uclass); + size = uc->uc_drv->priv_auto; + if (size) { + stats->uc_attach_count++; + stats->uc_attach_size += size; + } + } +} + +void dm_get_mem(struct dm_stats *stats) +{ + memset(stats, '\0', sizeof(*stats)); + dev_collect_stats(stats, gd->dm_root); + uclass_collect_stats(stats); + dev_tag_collect_stats(stats); + + stats->total_size = stats->dev_size + stats->uc_size + + stats->attach_size_total + stats->uc_attach_size + + stats->tag_size; +} + #ifdef CONFIG_ACPIGEN static int root_acpi_get_name(const struct udevice *dev, char *out_name) { diff --git a/drivers/core/tag.c b/drivers/core/tag.c index 22999193a5a30b962a7c2809d106a43c828c83fc..a3c5cb7e57cc8c0f32bffab4fb763b55e1d1dc7a 100644 --- a/drivers/core/tag.c +++ b/drivers/core/tag.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,24 @@ struct udevice; DECLARE_GLOBAL_DATA_PTR; +static const char *const tag_name[] = { + [DM_TAG_PLAT] = "plat", + [DM_TAG_PARENT_PLAT] = "parent_plat", + [DM_TAG_UC_PLAT] = "uclass_plat", + + [DM_TAG_PRIV] = "priv", + [DM_TAG_PARENT_PRIV] = "parent_priv", + [DM_TAG_UC_PRIV] = "uclass_priv", + [DM_TAG_DRIVER_DATA] = "driver_data", + + [DM_TAG_EFI] = "efi", +}; + +const char *tag_get_name(enum dm_tag_t tag) +{ + return tag_name[tag]; +} + int dev_tag_set_ptr(struct udevice *dev, enum dm_tag_t tag, void *ptr) { struct dmtag_node *node; @@ -137,3 +156,13 @@ int dev_tag_del_all(struct udevice *dev) return -ENOENT; } + +void dev_tag_collect_stats(struct dm_stats *stats) +{ + struct dmtag_node *node; + + list_for_each_entry(node, &gd->dmtag_list, sibling) { + stats->tag_count++; + stats->tag_size += sizeof(struct dmtag_node); + } +} diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 789728167cebbc80443388e9caa4d6409c981762..21874335c873d89d3f23502f27ede39de07171cd 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -19,3 +19,12 @@ config CPU_RISCV depends on CPU && RISCV help Support CPU cores for RISC-V architecture. + +config CPU_MICROBLAZE + bool "Enable Microblaze CPU driver" + depends on CPU && MICROBLAZE + select EVENT + select DM_EVENT + select XILINX_MICROBLAZE0_PVR + help + Support CPU cores for Microblaze architecture. diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index c8532637ca7c32d69b7b31e94bc26cfd3c07d2aa..20884b1795311655e9868777b0608d059048a6ee 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o obj-$(CONFIG_ARCH_AT91) += at91_cpu.o obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o +obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o obj-$(CONFIG_SANDBOX) += cpu_sandbox.o diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index a5cda6a62c41511e9ff45df635b14f6c877caa87..71e5900d70e88ac83855445c7a28d3218b676258 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -14,6 +14,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; int cpu_probe_all(void) { @@ -136,9 +139,36 @@ static int uclass_cpu_init(struct uclass *uc) return ret; } +static int uclass_cpu_post_bind(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) && + (gd->flags & GD_FLG_RELOC)) { + struct cpu_ops *ops = cpu_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->get_desc) + MANUAL_RELOC(ops->get_desc); + if (ops->get_info) + MANUAL_RELOC(ops->get_info); + if (ops->get_count) + MANUAL_RELOC(ops->get_count); + if (ops->get_vendor) + MANUAL_RELOC(ops->get_vendor); + if (ops->is_current) + MANUAL_RELOC(ops->is_current); + + reloc_done++; + } + } + + return 0; +} + UCLASS_DRIVER(cpu) = { .id = UCLASS_CPU, .name = "cpu", .flags = DM_UC_FLAG_SEQ_ALIAS, .init = uclass_cpu_init, + .post_bind = uclass_cpu_post_bind, }; diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..969a1047e59699a315b446d789e850c1295a6b51 --- /dev/null +++ b/drivers/cpu/microblaze_cpu.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022, Ovidiu Panait + */ +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define update_cpuinfo_pvr(pvr, ci, name) \ +{ \ + u32 tmp = PVR_##name(pvr); \ + if (ci != tmp) \ + printf("PVR value for " #name " does not match static data!\n");\ + ci = tmp; \ +} + +static int microblaze_cpu_probe_all(void *ctx, struct event *event) +{ + int ret; + + ret = cpu_probe_all(); + if (ret) + return log_msg_ret("Microblaze cpus probe failed\n", ret); + + return 0; +} +EVENT_SPY(EVT_DM_POST_INIT, microblaze_cpu_probe_all); + +static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci) +{ + u32 pvr[PVR_FULL_COUNT]; + + microblaze_get_all_pvrs(pvr); + + update_cpuinfo_pvr(pvr, ci->icache_size, ICACHE_BYTE_SIZE); + update_cpuinfo_pvr(pvr, ci->icache_line_length, ICACHE_LINE_LEN); + + update_cpuinfo_pvr(pvr, ci->dcache_size, DCACHE_BYTE_SIZE); + update_cpuinfo_pvr(pvr, ci->dcache_line_length, DCACHE_LINE_LEN); + + update_cpuinfo_pvr(pvr, ci->use_mmu, USE_MMU); + update_cpuinfo_pvr(pvr, ci->ver_code, VERSION); + update_cpuinfo_pvr(pvr, ci->fpga_code, TARGET_FAMILY); +} + +static void microblaze_set_cpuinfo_static(struct udevice *dev, + struct microblaze_cpuinfo *ci) +{ + const char *hw_ver = CONFIG_XILINX_MICROBLAZE0_HW_VER; + const char *fpga_family = CONFIG_XILINX_MICROBLAZE0_FPGA_FAMILY; + + ci->icache_size = dev_read_u32_default(dev, "i-cache-size", 0); + ci->icache_line_length = dev_read_u32_default(dev, + "i-cache-line-size", 0); + + ci->dcache_size = dev_read_u32_default(dev, "d-cache-size", 0); + ci->dcache_line_length = dev_read_u32_default(dev, + "d-cache-line-size", 0); + + ci->cpu_freq = dev_read_u32_default(dev, "clock-frequency", 0); + ci->addr_size = dev_read_u32_default(dev, "xlnx,addr-size", 32); + ci->use_mmu = dev_read_u32_default(dev, "xlnx,use-mmu", 0); + + ci->ver_code = microblaze_lookup_cpu_version_code(hw_ver); + ci->fpga_code = microblaze_lookup_fpga_family_code(fpga_family); +} + +static int microblaze_cpu_probe(struct udevice *dev) +{ + microblaze_set_cpuinfo_static(dev, gd_cpuinfo()); + + if (microblaze_cpu_has_pvr_full()) + microblaze_set_cpuinfo_pvr(gd_cpuinfo()); + else + debug("No PVR support. Using only static CPU info.\n"); + + return 0; +} + +static int microblaze_cpu_get_desc(const struct udevice *dev, char *buf, + int size) +{ + struct microblaze_cpuinfo *ci = gd_cpuinfo(); + const char *cpu_ver, *fpga_family; + u32 cpu_freq_mhz; + int ret; + + cpu_freq_mhz = ci->cpu_freq / 1000000; + cpu_ver = microblaze_lookup_cpu_version_string(ci->ver_code); + fpga_family = microblaze_lookup_fpga_family_string(ci->fpga_code); + + ret = snprintf(buf, size, + "MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s", + cpu_freq_mhz, cpu_ver, fpga_family); + + return 0; +} + +static int microblaze_cpu_get_info(const struct udevice *dev, + struct cpu_info *info) +{ + struct microblaze_cpuinfo *ci = gd_cpuinfo(); + + info->cpu_freq = ci->cpu_freq; + info->address_width = ci->addr_size; + + if (ci->icache_size || ci->dcache_size) + info->features |= BIT(CPU_FEAT_L1_CACHE); + + if (ci->use_mmu) + info->features |= BIT(CPU_FEAT_MMU); + + return 0; +} + +static int microblaze_cpu_get_count(const struct udevice *dev) +{ + return 1; +} + +static const struct cpu_ops microblaze_cpu_ops = { + .get_desc = microblaze_cpu_get_desc, + .get_info = microblaze_cpu_get_info, + .get_count = microblaze_cpu_get_count, +}; + +static const struct udevice_id microblaze_cpu_ids[] = { + { .compatible = "xlnx,microblaze-11.0" }, + { .compatible = "xlnx,microblaze-10.0" }, + { .compatible = "xlnx,microblaze-9.6" }, + { .compatible = "xlnx,microblaze-9.5" }, + { .compatible = "xlnx,microblaze-9.4" }, + { .compatible = "xlnx,microblaze-9.3" }, + { .compatible = "xlnx,microblaze-9.2" }, + { .compatible = "xlnx,microblaze-9.1" }, + { .compatible = "xlnx,microblaze-9.0" }, + { .compatible = "xlnx,microblaze-8.50.c" }, + { .compatible = "xlnx,microblaze-8.50.b" }, + { .compatible = "xlnx,microblaze-8.50.a" }, + { .compatible = "xlnx,microblaze-8.40.b" }, + { .compatible = "xlnx,microblaze-8.40.a" }, + { .compatible = "xlnx,microblaze-8.30.a" }, + { .compatible = "xlnx,microblaze-8.20.b" }, + { .compatible = "xlnx,microblaze-8.20.a" }, + { .compatible = "xlnx,microblaze-8.10.a" }, + { .compatible = "xlnx,microblaze-8.00.b" }, + { .compatible = "xlnx,microblaze-8.00.a" }, + { .compatible = "xlnx,microblaze-7.30.b" }, + { .compatible = "xlnx,microblaze-7.30.a" }, + { .compatible = "xlnx,microblaze-7.20.d" }, + { .compatible = "xlnx,microblaze-7.20.c" }, + { .compatible = "xlnx,microblaze-7.20.b" }, + { .compatible = "xlnx,microblaze-7.20.a" }, + { .compatible = "xlnx,microblaze-7.10.d" }, + { .compatible = "xlnx,microblaze-7.10.c" }, + { .compatible = "xlnx,microblaze-7.10.b" }, + { .compatible = "xlnx,microblaze-7.10.a" }, + { .compatible = "xlnx,microblaze-7.00.b" }, + { .compatible = "xlnx,microblaze-7.00.a" }, + { .compatible = "xlnx,microblaze-6.00.b" }, + { .compatible = "xlnx,microblaze-6.00.a" }, + { .compatible = "xlnx,microblaze-5.00.c" }, + { .compatible = "xlnx,microblaze-5.00.b" }, + { .compatible = "xlnx,microblaze-5.00.a" }, + { } +}; + +U_BOOT_DRIVER(microblaze_cpu) = { + .name = "microblaze_cpu", + .id = UCLASS_CPU, + .of_match = microblaze_cpu_ids, + .probe = microblaze_cpu_probe, + .ops = µblaze_cpu_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 675081ecd3706a8ad01ffe42039552d851044e22..12ef84ca05ca006471d39c0c73801b547bea45c0 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -6,4 +6,6 @@ source drivers/crypto/fsl/Kconfig source drivers/crypto/aspeed/Kconfig +source drivers/crypto/nuvoton/Kconfig + endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 6b762565a1f6c9dfd643fcb8933696a51bdd0447..b91051860976e955293a43686550826803544743 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -8,3 +8,4 @@ obj-y += rsa_mod_exp/ obj-y += fsl/ obj-y += hash/ obj-y += aspeed/ +obj-y += nuvoton/ diff --git a/drivers/crypto/nuvoton/Kconfig b/drivers/crypto/nuvoton/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..034fcadfcc896af600fba027044568a41823d50d --- /dev/null +++ b/drivers/crypto/nuvoton/Kconfig @@ -0,0 +1,14 @@ +config NPCM_AES + bool "Support the NPCM AES algorithm" + select NPCM_OTP + help + This provides a means to encrypt and decrypt data using the NPCM + AES (Advanced Encryption Standard). This algorithm uses a symmetric + key and is widely used as a streaming cipher. This command only + supports AES256-CBC. + +config NPCM_SHA + bool "Enable NPCM cryptographic HW SHA accelerator" + help + This option enables support of NPCM cryptographic HW SHA accelerator. + It supports SHA1 and SHA256 hashing algorithms. diff --git a/drivers/crypto/nuvoton/Makefile b/drivers/crypto/nuvoton/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..5a1173dfe73ebc3cc14481b676288abc1f44f277 --- /dev/null +++ b/drivers/crypto/nuvoton/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_NPCM_AES) += npcm_aes.o +obj-$(CONFIG_NPCM_SHA) += npcm_sha.o diff --git a/drivers/crypto/nuvoton/npcm_aes.c b/drivers/crypto/nuvoton/npcm_aes.c new file mode 100644 index 0000000000000000000000000000000000000000..6493ea108ec7fafd92b14adf613cf29907411c64 --- /dev/null +++ b/drivers/crypto/nuvoton/npcm_aes.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ONE_SECOND 0xC00000 + +struct npcm_aes_priv { + struct npcm_aes_regs *regs; +}; + +static struct npcm_aes_priv *aes_priv; +static u8 fkeyind_to_set = 0xff; + +static int second_timeout(u32 *addr, u32 bitmask, u32 bitpol) +{ + ulong time, i = 0; + + time = get_timer(0); + + /* default 1 second timeout */ + while (((readl(addr) & bitmask) == bitpol) && i < ONE_SECOND) + i++; + + if (i == ONE_SECOND) { + printf("%xms timeout: addr = %x, mask = %x\n", (u32)get_timer(time), + *addr, bitmask); + return -1; + } + + return 0; +} + +int npcm_aes_select_key(u8 fkeyind) +{ + if (npcm_otp_is_fuse_array_disabled(NPCM_KEY_SA)) { + printf("AES key access denied\n"); + return -EACCES; + } + + if (fkeyind < 4) + fkeyind_to_set = fkeyind; + + return 0; +} + +static int npcm_aes_init(u8 dec_enc) +{ + struct npcm_aes_regs *regs = aes_priv->regs; + u32 ctrl, orgctrlval, wrtimeout; + + /* reset hw */ + writel(readl(®s->aes_sw_reset) | SW_RESET_BIT, ®s->aes_sw_reset); + writel(readl(®s->aes_fifo_status) | DIN_FIFO_OVERFLOW, ®s->aes_fifo_status); + writel(readl(®s->aes_fifo_status) | DOUT_FIFO_UNDERFLOW, ®s->aes_fifo_status); + + /* Workaround to over come Errata #648 */ + orgctrlval = readl(®s->aes_control); + ctrl = (0x00002004 | dec_enc); /* AES256(CBC) */ + + if (ctrl != orgctrlval) { + writel(ctrl, ®s->aes_control); + + if (ctrl != readl(®s->aes_control)) { + u32 read_ctrl; + int intwr; + + for (wrtimeout = 0; wrtimeout < 1000; wrtimeout++) { + for (intwr = 0 ; intwr < 10; intwr++) { + writel(ctrl, ®s->aes_control); + writew(ctrl, (u16 *)®s->aes_control + 1); + /* Write configurable info in a single write operation */ + mb(); + } + + read_ctrl = readl(®s->aes_control); + if (ctrl == read_ctrl) + break; + } + + if (wrtimeout == 1000) { + printf("\nTIMEOUT expected data=0x%x Actual AES_CONTROL data 0x%x\n\n", + ctrl, read_ctrl); + return -EAGAIN; + } + + printf("Workaround success, wrtimeout = %d\n", wrtimeout); + } + } + + if (second_timeout(®s->aes_busy, AES_BUSY_BIT, AES_BUSY_BIT)) + return -EAGAIN; + + return 0; +} + +static inline void npcm_aes_load_iv(u8 *iv) +{ + struct npcm_aes_regs *regs = aes_priv->regs; + u32 *p = (u32 *)iv; + u32 i; + + /* Initialization Vector is loaded in 32-bit chunks */ + for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++) + writel(p[i], ®s->aes_iv_0 + i); +} + +static inline void npcm_aes_load_key(u8 *key) +{ + struct npcm_aes_regs *regs = aes_priv->regs; + u32 *p = (u32 *)key; + u32 i; + + /* The key can be loaded either via the configuration or by using sideband + * key port (aes_select_key). + * If aes_select_key has been called ('fkeyind_to_set' was set to desired + * key index) and no key is specified (key is NULL), we should use the + * key index. Otherwise, we write the given key to the registers. + */ + if (!key && fkeyind_to_set < 4) { + npcm_otp_select_key(fkeyind_to_set); + + /* Sample the new key */ + writel(readl(®s->aes_sk) | AES_SK_BIT, ®s->aes_sk); + + } else { + /* Initialization Vector is loaded in 32-bit chunks */ + for (i = 0; i < (2 * SIZE_AES_BLOCK / sizeof(u32)); i++) + writel(p[i], ®s->aes_key_0 + i); + + fkeyind_to_set = 0xff; + } +} + +static inline void npcm_aes_write(u32 *in) +{ + struct npcm_aes_regs *regs = aes_priv->regs; + u32 i; + + /* 16 Byte AES Block is written in 32-bit chunks */ + for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++) + writel(in[i], ®s->aes_fifo_data); +} + +static inline void npcm_aes_read(u32 *out) +{ + struct npcm_aes_regs *regs = aes_priv->regs; + u32 i; + + /* Data is read in 32-bit chunks */ + for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++) + out[i] = readl(®s->aes_fifo_data); +} + +static void npcm_aes_feed(u32 num_aes_blocks, u32 *datain, u32 *dataout) +{ + struct npcm_aes_regs *regs = aes_priv->regs; + u32 aes_datablk; + u32 total_blocks = num_aes_blocks; + u32 blocks_left = num_aes_blocks; + + /* data mode */ + writel(readl(®s->aes_busy) | AES_BUSY_BIT, ®s->aes_busy); + + /* Clear overflow and underflow */ + writel(readl(®s->aes_fifo_status) | DIN_FIFO_OVERFLOW, ®s->aes_fifo_status); + writel(readl(®s->aes_fifo_status) | DOUT_FIFO_UNDERFLOW, ®s->aes_fifo_status); + + /* datain/dataout is advanced in 32-bit chunks */ + aes_datablk = (SIZE_AES_BLOCK / sizeof(u32)); + + /* Quit if there is no complete blocks */ + if (total_blocks == 0) + return; + + /* Write the first block */ + if (total_blocks > 1) { + npcm_aes_write(datain); + datain += aes_datablk; + blocks_left--; + } + + /* Write the second block */ + if (total_blocks > 2) { + second_timeout(®s->aes_fifo_status, DIN_FIFO_EMPTY, 0); + npcm_aes_write(datain); + datain += aes_datablk; + blocks_left--; + } + + /* Write & read available blocks */ + while (blocks_left > 0) { + second_timeout(®s->aes_fifo_status, DIN_FIFO_FULL, DIN_FIFO_FULL); + + /* Write next block */ + npcm_aes_write(datain); + datain += aes_datablk; + + /* Wait till DOUT FIFO is empty */ + second_timeout(®s->aes_fifo_status, DOUT_FIFO_EMPTY, DOUT_FIFO_EMPTY); + + /* Read next block */ + npcm_aes_read(dataout); + dataout += aes_datablk; + + blocks_left--; + } + + if (total_blocks > 2) { + second_timeout(®s->aes_fifo_status, DOUT_FIFO_FULL, 0); + + /* Read next block */ + npcm_aes_read(dataout); + dataout += aes_datablk; + + second_timeout(®s->aes_fifo_status, DOUT_FIFO_FULL, 0); + + /* Read next block */ + npcm_aes_read(dataout); + dataout += aes_datablk; + } else if (total_blocks > 1) { + second_timeout(®s->aes_fifo_status, DOUT_FIFO_FULL, 0); + + /* Read next block */ + npcm_aes_read(dataout); + dataout += aes_datablk; + } +} + +void aes_expand_key(u8 *key, u32 key_size, u8 *expkey) +{ + /* npcm hw expands the key automatically, just copy it */ + memcpy(expkey, key, SIZE_AES_BLOCK * 2); +} + +void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + if (npcm_aes_init(AES_OP_ENCRYPT)) + return; + + npcm_aes_load_iv(iv); + + npcm_aes_load_key(key_exp); + + npcm_aes_feed(num_aes_blocks, (u32 *)src, (u32 *)dst); +} + +void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + if (npcm_aes_init(AES_OP_DECRYPT)) + return; + + npcm_aes_load_iv(iv); + + npcm_aes_load_key(key_exp); + + npcm_aes_feed(num_aes_blocks, (u32 *)src, (u32 *)dst); +} + +static int npcm_aes_bind(struct udevice *dev) +{ + aes_priv = calloc(1, sizeof(struct npcm_aes_priv)); + if (!aes_priv) { + printf("%s: %d\n", __func__, __LINE__); + return -ENOMEM; + } + + aes_priv->regs = dev_read_addr_ptr(dev); + if (!aes_priv->regs) { + printf("Cannot find aes reg address, binding failed\n"); + return -EINVAL; + } + + printf("AES: NPCM AES module bind OK\n"); + + return 0; +} + +static const struct udevice_id npcm_aes_ids[] = { + { .compatible = "nuvoton,npcm845-aes" }, + { .compatible = "nuvoton,npcm750-aes" }, + { } +}; + +U_BOOT_DRIVER(npcm_aes) = { + .name = "npcm_aes", + .id = UCLASS_MISC, + .of_match = npcm_aes_ids, + .priv_auto = sizeof(struct npcm_aes_priv), + .bind = npcm_aes_bind, +}; diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c new file mode 100644 index 0000000000000000000000000000000000000000..7ebdfa16f4fcd37d25cd1b87e59edd40edf041de --- /dev/null +++ b/drivers/crypto/nuvoton/npcm_sha.c @@ -0,0 +1,897 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include + +#define HASH_DIG_H_NUM 8 + +#define HASH_CTR_STS_SHA_EN BIT(0) +#define HASH_CTR_STS_SHA_BUSY BIT(1) +#define HASH_CTR_STS_SHA_RST BIT(2) +#define HASH_CFG_SHA1_SHA2 BIT(0) + +/* SHA type */ +enum npcm_sha_type { + npcm_sha_type_sha2 = 0, + npcm_sha_type_sha1, + npcm_sha_type_num +}; + +struct npcm_sha_regs { + unsigned int hash_data_in; + unsigned char hash_ctr_sts; + unsigned char reserved_0[0x03]; + unsigned char hash_cfg; + unsigned char reserved_1[0x03]; + unsigned char hash_ver; + unsigned char reserved_2[0x13]; + unsigned int hash_dig[HASH_DIG_H_NUM]; +}; + +struct npcm_sha_priv { + struct npcm_sha_regs *regs; +}; + +static struct npcm_sha_priv *sha_priv; + +#ifdef SHA_DEBUG_MODULE +#define sha_print(fmt, args...) printf(fmt, ##args) +#else +#define sha_print(fmt, args...) (void)0 +#endif + +#define SHA_BLOCK_LENGTH (512 / 8) +#define SHA_2_HASH_LENGTH (256 / 8) +#define SHA_1_HASH_LENGTH (160 / 8) +#define SHA_HASH_LENGTH(type) ((type == npcm_sha_type_sha2) ? \ + (SHA_2_HASH_LENGTH) : (SHA_1_HASH_LENGTH)) + +#define SHA_SECRUN_BUFF_SIZE 64 +#define SHA_TIMEOUT 100 +#define SHA_DATA_LAST_BYTE 0x80 + +#define SHA2_NUM_OF_SELF_TESTS 3 +#define SHA1_NUM_OF_SELF_TESTS 4 + +#define NUVOTON_ALIGNMENT 4 + +/*-----------------------------------------------------------------------------*/ +/* SHA instance struct handler */ +/*-----------------------------------------------------------------------------*/ +struct SHA_HANDLE_T { + u32 hv[SHA_2_HASH_LENGTH / sizeof(u32)]; + u32 length0; + u32 length1; + u32 block[SHA_BLOCK_LENGTH / sizeof(u32)]; + u8 type; + bool active; +}; + +// The # of bytes currently in the sha block buffer +#define SHA_BUFF_POS(length) ((length) & (SHA_BLOCK_LENGTH - 1)) + +// The # of free bytes in the sha block buffer +#define SHA_BUFF_FREE(length) (SHA_BLOCK_LENGTH - SHA_BUFF_POS(length)) + +static void SHA_FlushLocalBuffer_l(const u32 *buff); +static int SHA_BusyWait_l(void); +static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type); +static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type); +static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block); +static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block); +static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block); + +static int SHA_Init(struct SHA_HANDLE_T *handleptr); +static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type); +static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len); +static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest); +static int SHA_Reset(void); +static int SHA_Power(bool on); +#ifdef SHA_PRINT +static void SHA_PrintRegs(void); +static void SHA_PrintVersion(void); +#endif + +static struct SHA_HANDLE_T sha_handle; + +/*----------------------------------------------------------------------------*/ +/* Checks if give function returns int error, and returns the error */ +/* immediately after SHA disabling */ +/*----------------------------------------------------------------------------*/ +int npcm_sha_check(int status) +{ + if (status != 0) { + SHA_Power(false); + return status; + } + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_sha_calc */ +/* */ +/* Parameters: type - SHA module type */ +/* inBuff - Pointer to a buffer containing the data to */ +/* be hashed */ +/* len - Length of the data to hash */ +/* hashDigest - Pointer to a buffer where the reseulting */ +/* digest will be copied to */ +/* */ +/* Returns: 0 on success or other int error code on error */ +/* Side effects: */ +/* Description: */ +/* This routine performs complete SHA calculation in one */ +/* step */ +/*----------------------------------------------------------------------------*/ +int npcm_sha_calc(u8 type, const u8 *inbuff, u32 len, u8 *hashdigest) +{ + int status; + struct SHA_HANDLE_T handle; + + SHA_Init(&handle); + SHA_Power(true); + SHA_Reset(); + SHA_Start(&handle, type); + status = SHA_Update(&handle, inbuff, len); + npcm_sha_check(status); + status = SHA_Finish(&handle, hashdigest); + npcm_sha_check(status); + SHA_Power(false); + + return 0; +} + +/* + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param chunk_size chunk size for sha256 + */ +void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size) +{ + puts("\nhw_sha256 using BMC HW accelerator\t"); + npcm_sha_calc(npcm_sha_type_sha2, (u8 *)in_addr, buflen, (u8 *)out_addr); +} + +/* + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param chunk_size chunk_size for sha1 + */ +void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size) +{ + puts("\nhw_sha1 using BMC HW accelerator\t"); + npcm_sha_calc(npcm_sha_type_sha1, (u8 *)in_addr, buflen, (u8 *)out_addr); +} + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + const char *algo_name1 = "sha1"; + const char *algo_name2 = "sha256"; + + SHA_Init(&sha_handle); + SHA_Power(true); + SHA_Reset(); + if (!strcmp(algo_name1, algo->name)) + return SHA_Start(&sha_handle, npcm_sha_type_sha1); + else if (!strcmp(algo_name2, algo->name)) + return SHA_Start(&sha_handle, npcm_sha_type_sha2); + else + return -EPROTO; +} + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) +{ + return SHA_Update(&sha_handle, buf, size); +} + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, int size) +{ + int status; + + status = SHA_Finish(&sha_handle, dest_buf); + npcm_sha_check(status); + return SHA_Power(false); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_Init */ +/* */ +/* Parameters: handlePtr - SHA processing handle pointer */ +/* Returns: 0 on success or other int error code on error. */ +/* Side effects: */ +/* Description: */ +/* This routine initialize the SHA module */ +/*----------------------------------------------------------------------------*/ +static int SHA_Init(struct SHA_HANDLE_T *handleptr) +{ + handleptr->active = false; + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_Start */ +/* */ +/* Parameters: handlePtr - SHA processing handle pointer */ +/* type - SHA module type */ +/* */ +/* Returns: 0 on success or other int error code on error. */ +/* Side effects: */ +/* Description: */ +/* This routine start a single SHA process */ +/*----------------------------------------------------------------------------*/ +static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + + // Initialize handle + handleptr->length0 = 0; + handleptr->length1 = 0; + handleptr->type = type; + handleptr->active = true; + + // Set SHA type + writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); + + // Reset SHA hardware + SHA_Reset(); + + /* The handlePtr->hv is initialized with the correct IV as the SHA engine + * automatically fill the HASH_DIG_Hn registers according to SHA spec + * (following SHA_RST assertion) + */ + SHA_GetShaDigest_l((u8 *)handleptr->hv, type); + + // Init block with zeros + memset(handleptr->block, 0, sizeof(handleptr->block)); + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_Update */ +/* */ +/* Parameters: handlePtr - SHA processing handle pointer */ +/* buffer - Pointer to the data that will be added to */ +/* the hash calculation */ +/* len - Length of data to add to SHA calculation */ +/* */ +/* */ +/* Returns: 0 on success or other int error code on error */ +/* Side effects: */ +/* Description: */ +/* This routine adds data to previously started SHA */ +/* calculation */ +/*----------------------------------------------------------------------------*/ +static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)]; + u32 bufferlen = len; + u16 pos = 0; + u8 *blockptr; + int status; + + // Error check + if (!handleptr->active) + return -EPROTO; + + // Wait till SHA is not busy + status = SHA_BusyWait_l(); + npcm_sha_check(status); + + // Set SHA type + writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); + + // Write SHA latest digest into SHA module + SHA_SetShaDigest_l(handleptr->hv, handleptr->type); + + // Set number of unhashed bytes which remained from last update + pos = SHA_BUFF_POS(handleptr->length0); + + // Copy unhashed bytes which remained from last update to secrun buffer + SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer); + + while (len) { + // Wait for the hardware to be available (in case we are hashing) + status = SHA_BusyWait_l(); + npcm_sha_check(status); + + // Move as much bytes as we can into the secrun buffer + bufferlen = min(len, SHA_BUFF_FREE(handleptr->length0)); + + // Copy current given buffer to the secrun buffer + SHA_SetBlock_l((u8 *)buffer, bufferlen, pos, localbuffer); + + // Update size of hashed bytes + handleptr->length0 += bufferlen; + + if (handleptr->length0 < bufferlen) + handleptr->length1++; + + // Update length of data left to digest + len -= bufferlen; + + // Update given buffer pointer + buffer += bufferlen; + + // If secrun buffer is full + if (SHA_BUFF_POS(handleptr->length0) == 0) { + /* We just filled up the buffer perfectly, so let it hash (we'll + * unload the hash only when we are done with all hashing) + */ + SHA_FlushLocalBuffer_l(localbuffer); + + pos = 0; + bufferlen = 0; + } + } + + // Wait till SHA is not busy + status = SHA_BusyWait_l(); + npcm_sha_check(status); + + /* Copy unhashed bytes from given buffer to handle block for next update/finish */ + blockptr = (u8 *)handleptr->block; + while (bufferlen) + blockptr[--bufferlen + pos] = *(--buffer); + + // Save SHA current digest + SHA_GetShaDigest_l((u8 *)handleptr->hv, handleptr->type); + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_Finish */ +/* */ +/* Parameters: handlePtr - SHA processing handle pointer */ +/* hashDigest - Pointer to a buffer where the final digest */ +/* will be copied to */ +/* */ +/* Returns: 0 on success or other int error code on error */ +/* Side effects: */ +/* Description: */ +/* This routine finish SHA calculation and get */ +/* the resulting SHA digest */ +/*----------------------------------------------------------------------------*/ +static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)]; + const u8 lastbyte = SHA_DATA_LAST_BYTE; + u16 pos; + int status; + + // Error check + if (!handleptr->active) + return -EPROTO; + + // Set SHA type + writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); + + // Wait till SHA is not busy + status = SHA_BusyWait_l(); + npcm_sha_check(status); + + // Finish off the current buffer with the SHA spec'ed padding + pos = SHA_BUFF_POS(handleptr->length0); + + // Init SHA digest + SHA_SetShaDigest_l(handleptr->hv, handleptr->type); + + // Load data into secrun buffer + SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer); + + // Set data last byte as in SHA algorithm spec + SHA_SetBlock_l(&lastbyte, 1, pos++, localbuffer); + + // If the remainder of data is longer then one block + if (pos > (SHA_BLOCK_LENGTH - 8)) { + /* The length will be in the next block Pad the rest of the last block with 0's */ + SHA_ClearBlock_l((SHA_BLOCK_LENGTH - pos), pos, localbuffer); + + // Hash the current block + SHA_FlushLocalBuffer_l(localbuffer); + + pos = 0; + + // Wait till SHA is not busy + status = SHA_BusyWait_l(); + npcm_sha_check(status); + } + + // Pad the rest of the last block with 0's except for the last 8-3 bytes + SHA_ClearBlock_l((SHA_BLOCK_LENGTH - (8 - 3)) - pos, pos, localbuffer); + + /* The last 8-3 bytes are set to the bit-length of the message in big-endian form */ + SHA_SetLength32_l(handleptr, localbuffer); + + // Hash all that, and save the hash for the caller + SHA_FlushLocalBuffer_l(localbuffer); + + // Wait till SHA is not busy + status = SHA_BusyWait_l(); + npcm_sha_check(status); + + // Save SHA final digest into given buffer + SHA_GetShaDigest_l(hashdigest, handleptr->type); + + // Free handle + handleptr->active = false; + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_Reset */ +/* */ +/* Parameters: none */ +/* Returns: none */ +/* Side effects: */ +/* Description: */ +/* This routine reset SHA module */ +/*----------------------------------------------------------------------------*/ +static int SHA_Reset(void) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + + writel(readl(®s->hash_ctr_sts) | HASH_CTR_STS_SHA_RST, ®s->hash_ctr_sts); + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_Power */ +/* */ +/* Parameters: on - true enable the module, false disable the module */ +/* Returns: none */ +/* Side effects: */ +/* Description: */ +/* This routine set SHA module power on/off */ +/*----------------------------------------------------------------------------*/ +static int SHA_Power(bool on) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u8 hash_sts; + + hash_sts = readb(®s->hash_ctr_sts) & ~HASH_CTR_STS_SHA_EN; + writeb(hash_sts | (on & HASH_CTR_STS_SHA_EN), ®s->hash_ctr_sts); + + return 0; +} + +#ifdef SHA_PRINT +/*----------------------------------------------------------------------------*/ +/* Function: SHA_PrintRegs */ +/* */ +/* Parameters: none */ +/* Returns: none */ +/* Side effects: */ +/* Description: */ +/* This routine prints the module registers */ +/*----------------------------------------------------------------------------*/ +static void SHA_PrintRegs(void) +{ +#ifdef SHA_DEBUG_MODULE + struct npcm_sha_regs *regs = sha_priv->regs; +#endif + unsigned int i; + + sha_print("/*--------------*/\n"); + sha_print("/* SHA */\n"); + sha_print("/*--------------*/\n\n"); + + sha_print("HASH_CTR_STS = 0x%02X\n", readb(®s->hash_ctr_sts)); + sha_print("HASH_CFG = 0x%02X\n", readb(®s->hash_cfg)); + + for (i = 0; i < HASH_DIG_H_NUM; i++) + sha_print("HASH_DIG_H%d = 0x%08X\n", i, readl(®s->hash_dig[i])); + + sha_print("HASH_VER = 0x%08X\n", readb(®s->hash_ver)); + + sha_print("\n"); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_PrintVersion */ +/* */ +/* Parameters: none */ +/* Returns: none */ +/* Side effects: */ +/* Description: */ +/* This routine prints the module version */ +/*----------------------------------------------------------------------------*/ +static void SHA_PrintVersion(void) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + + printf("SHA MODULE VER = %d\n", readb(®s->hash_ver)); +} +#endif + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_sha_selftest */ +/* */ +/* Parameters: type - SHA module type */ +/* Returns: 0 on success or other int error code on error */ +/* Side effects: */ +/* Description: */ +/* This routine performs various tests on the SHA HW and SW */ +/*----------------------------------------------------------------------------*/ +int npcm_sha_selftest(u8 type) +{ + int status; + struct SHA_HANDLE_T handle; + u8 hashdigest[max(SHA_1_HASH_LENGTH, SHA_2_HASH_LENGTH)]; + u16 i, j; + + /*------------------------------------------------------------------------*/ + /* SHA1 tests info */ + /*------------------------------------------------------------------------*/ + + static const u8 sha1selftestbuff[SHA1_NUM_OF_SELF_TESTS][94] = { + {"abc"}, + {"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"}, + {"0123456789012345678901234567890123456789012345678901234567890123"}, + {0x30, 0x5c, 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, + 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, + 0x01, 0x0c, 0x04, 0x14, 0xe1, 0xb6, 0x93, 0xfe, 0x33, 0x43, 0xc1, 0x20, + 0x5d, 0x4b, 0xaa, 0xb8, 0x63, 0xfb, 0xcf, 0x6c, 0x46, 0x1e, 0x88, 0x04, + 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, + 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, 0x01, 0x0c, + 0x04, 0x14, 0x13, 0xc1, 0x0c, 0xfc, 0xc8, 0x92, 0xd7, 0xde, 0x07, 0x1c, + 0x40, 0xde, 0x4f, 0xcd, 0x07, 0x5b, 0x68, 0x20, 0x5a, 0x6c} + }; + + static const u8 sha1selftestbufflen[SHA1_NUM_OF_SELF_TESTS] = { + 3, 56, 64, 94 + }; + + static const u8 sha1selftestexpres[SHA1_NUM_OF_SELF_TESTS][SHA_1_HASH_LENGTH] = { + {0xA9, 0x99, 0x3E, 0x36, + 0x47, 0x06, 0x81, 0x6A, + 0xBA, 0x3E, 0x25, 0x71, + 0x78, 0x50, 0xC2, 0x6C, + 0x9C, 0xD0, 0xD8, 0x9D}, + {0x84, 0x98, 0x3E, 0x44, + 0x1C, 0x3B, 0xD2, 0x6E, + 0xBA, 0xAE, 0x4A, 0xA1, + 0xF9, 0x51, 0x29, 0xE5, + 0xE5, 0x46, 0x70, 0xF1}, + {0xCF, 0x08, 0x00, 0xF7, + 0x64, 0x4A, 0xCE, 0x3C, + 0xB4, 0xC3, 0xFA, 0x33, + 0x38, 0x8D, 0x3B, 0xA0, + 0xEA, 0x3C, 0x8B, 0x6E}, + {0xc9, 0x84, 0x45, 0xc8, + 0x64, 0x04, 0xb1, 0xe3, + 0x3c, 0x6b, 0x0a, 0x8c, + 0x8b, 0x80, 0x94, 0xfc, + 0xf3, 0xc9, 0x98, 0xab} + }; + + /*------------------------------------------------------------------------*/ + /* SHA2 tests info */ + /*------------------------------------------------------------------------*/ + + static const u8 sha2selftestbuff[SHA2_NUM_OF_SELF_TESTS][100] = { + { "abc" }, + { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, + {'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', + 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a'} + }; + + static const u8 sha2selftestbufflen[SHA2_NUM_OF_SELF_TESTS] = { + 3, 56, 100 + }; + + static const u8 sha2selftestexpres[SHA2_NUM_OF_SELF_TESTS][SHA_2_HASH_LENGTH] = { + /* + * SHA-256 test vectors + */ + { 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, + 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, + 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, + 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }, + { 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, + 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, + 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, + 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }, + { 0xCD, 0xC7, 0x6E, 0x5C, 0x99, 0x14, 0xFB, 0x92, + 0x81, 0xA1, 0xC7, 0xE2, 0x84, 0xD7, 0x3E, 0x67, + 0xF1, 0x80, 0x9A, 0x48, 0xA4, 0x97, 0x20, 0x0E, + 0x04, 0x6D, 0x39, 0xCC, 0xC7, 0x11, 0x2C, 0xD0 }, + }; + + if (type == npcm_sha_type_sha1) { + /*--------------------------------------------------------------------*/ + /* SHA 1 TESTS */ + /*--------------------------------------------------------------------*/ + for (i = 0; i < SHA1_NUM_OF_SELF_TESTS; i++) { + if (i != 3) { + status = npcm_sha_calc(npcm_sha_type_sha1, sha1selftestbuff[i], sha1selftestbufflen[i], hashdigest); + npcm_sha_check(status); + } else { + SHA_Power(true); + SHA_Reset(); + status = SHA_Start(&handle, npcm_sha_type_sha1); + npcm_sha_check(status); + status = SHA_Update(&handle, sha1selftestbuff[i], 73); + npcm_sha_check(status); + status = SHA_Update(&handle, &sha1selftestbuff[i][73], sha1selftestbufflen[i] - 73); + npcm_sha_check(status); + status = SHA_Finish(&handle, hashdigest); + npcm_sha_check(status); + SHA_Power(false); + } + + if (memcmp(hashdigest, sha1selftestexpres[i], SHA_1_HASH_LENGTH)) + return -1; + } + + } else { + /*--------------------------------------------------------------------*/ + /* SHA 2 TESTS */ + /*--------------------------------------------------------------------*/ + for (i = 0; i < SHA2_NUM_OF_SELF_TESTS; i++) { + SHA_Power(true); + SHA_Reset(); + status = SHA_Start(&handle, npcm_sha_type_sha2); + npcm_sha_check(status); + if (i == 2) { + for (j = 0; j < 10000; j++) { //not working + status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]); + npcm_sha_check(status); + } + } else { + status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]); + npcm_sha_check(status); + } + + status = SHA_Finish(&handle, hashdigest); + npcm_sha_check(status); + SHA_Power(false); + if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH)) + return -1; + + npcm_sha_calc(npcm_sha_type_sha2, sha2selftestbuff[i], sha2selftestbufflen[i], hashdigest); + if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH)) + return -1; + } + } + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_FlushLocalBuffer_l */ +/* */ +/* Parameters: */ +/* Returns: none */ +/* Side effects: */ +/* Description: This routine flush secrun buffer to SHA module */ +/*----------------------------------------------------------------------------*/ +static void SHA_FlushLocalBuffer_l(const u32 *buff) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u32 i; + + for (i = 0; i < (SHA_BLOCK_LENGTH / sizeof(u32)); i++) + writel(buff[i], ®s->hash_data_in); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_BusyWait_l */ +/* */ +/* Parameters: */ +/* Returns: 0 if no error was found or DEFS_STATUS_ERROR otherwise */ +/* Side effects: */ +/* Description: This routine wait for SHA unit to no longer be busy */ +/*----------------------------------------------------------------------------*/ +static int SHA_BusyWait_l(void) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u32 timeout = SHA_TIMEOUT; + + do { + if (timeout-- == 0) + return -ETIMEDOUT; + } while ((readb(®s->hash_ctr_sts) & HASH_CTR_STS_SHA_BUSY) + == HASH_CTR_STS_SHA_BUSY); + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_GetShaDigest_l */ +/* */ +/* Parameters: hashDigest - buffer for the hash output. */ +/* type - SHA module type */ +/* Returns: none */ +/* Side effects: */ +/* Description: This routine copy the hash digest from the hardware */ +/* and into given buffer (in ram) */ +/*----------------------------------------------------------------------------*/ +static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u16 j; + u8 len = SHA_HASH_LENGTH(type) / sizeof(u32); + + // Copy Bytes from SHA module to given buffer + for (j = 0; j < len; j++) + ((u32 *)hashdigest)[j] = readl(®s->hash_dig[j]); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_SetShaDigest_l */ +/* */ +/* Parameters: hashDigest - input buffer to set as hash digest */ +/* type - SHA module type */ +/* Returns: none */ +/* Side effects: */ +/* Description: This routine set the hash digest in the hardware from */ +/* a given buffer (in ram) */ +/*----------------------------------------------------------------------------*/ +static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u16 j; + u8 len = SHA_HASH_LENGTH(type) / sizeof(u32); + + // Copy Bytes from given buffer to SHA module + for (j = 0; j < len; j++) + writel(hashdigest[j], ®s->hash_dig[j]); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_SetBlock_l */ +/* */ +/* Parameters: data - data to copy */ +/* len - size of data */ +/* position - byte offset into the block at which data */ +/* should be placed */ +/* block - block buffer */ +/* Returns: none */ +/* Side effects: */ +/* Description: This routine load bytes into block buffer */ +/*----------------------------------------------------------------------------*/ +static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block) +{ + u8 *dest = (u8 *)block; + + memcpy(dest + position, data, len); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_SetBlock_l */ +/* */ +/* Parameters: */ +/* len - size of data */ +/* position - byte offset into the block at which data */ +/* should be placed */ +/* block - block buffer */ +/* Returns: none */ +/* Side effects: */ +/* Description: This routine load zero's into the block buffer */ +/*----------------------------------------------------------------------------*/ +static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block) +{ + u8 *dest = (u8 *)block; + + memset(dest + position, 0, len); +} + +/*----------------------------------------------------------------------------*/ +/* Function: SHA_SetLength32_l */ +/* */ +/* Parameters: */ +/* handlePtr - SHA processing handle pointer */ +/* block - block buffer */ +/* Returns: none */ +/* Side effects: */ +/* Description: This routine set the length of the hash's data */ +/* len is the 32-bit byte length of the message */ +/*lint -efunc(734,SHA_SetLength32_l) Supperess loss of percision lint warning */ +/*----------------------------------------------------------------------------*/ +static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block) +{ + u16 *secrunbufferswappedptr = (u16 *)(void *)(block); + + secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 1] = (u16) + ((handleptr->length0 << 3) << 8) | ((u16)(handleptr->length0 << 3) >> 8); + secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 2] = (u16) + ((handleptr->length0 >> (16 - 3)) >> 8) | ((u16)(handleptr->length0 >> (16 - 3)) << 8); + secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 3] = (u16) + ((handleptr->length1 << 3) << 8) | ((u16)(handleptr->length1 << 3) >> 8); + secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 4] = (u16) + ((handleptr->length1 >> (16 - 3)) >> 8) | ((u16)(handleptr->length1 >> (16 - 3)) << 8); +} + +static int npcm_sha_bind(struct udevice *dev) +{ + sha_priv = calloc(1, sizeof(struct npcm_sha_priv)); + if (!sha_priv) + return -ENOMEM; + + sha_priv->regs = dev_remap_addr_index(dev, 0); + if (!sha_priv->regs) { + printf("Cannot find sha reg address, binding failed\n"); + return -EINVAL; + } + + printf("SHA: NPCM SHA module bind OK\n"); + + return 0; +} + +static const struct udevice_id npcm_sha_ids[] = { + { .compatible = "nuvoton,npcm845-sha" }, + { .compatible = "nuvoton,npcm750-sha" }, + { } +}; + +U_BOOT_DRIVER(npcm_sha) = { + .name = "npcm_sha", + .id = UCLASS_MISC, + .of_match = npcm_sha_ids, + .priv_auto = sizeof(struct npcm_sha_priv), + .bind = npcm_sha_bind, +}; diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index eec9d480b096ad265c8aa74016ea8b58d3f1dcd3..738b7884012f3fbfdd6d24b96f7e69da4ef5937f 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -30,5 +30,10 @@ config DDR_SPD For memory controllers that can utilize it, add enable support for using the JEDEC SDP standard. +config SYS_SPD_BUS_NUM + int "I2C bus number for DDR SPD" + depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY + default 0 + source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 5925fe9e287c08138c740245a9de1a6eb3b1408c..d93ed8d2feb6629e40cec6d2d8b7d4c239897ffd 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -10,6 +10,12 @@ config SYS_FSL_MMDC help Select Freescale Multi Mode DDR controller (MMDC). +config SYS_FSL_DDR_EMU + bool + help + Specify emulator support for DDR. Some DDR features such as deskew + training are not available. + if SYS_FSL_DDR || SYS_FSL_MMDC config SYS_FSL_DDR_BE @@ -169,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER Use the DDR controller to auto initialize memory. If not enabled, the DMA controller is responsible for doing this. +config SYS_DDR_RAW_TIMING + bool "Get DDR timing information from something other than SPD" + help + This is common with soldered DDR chips onboard without SPD. DDR raw + timing parameters are extracted from datasheet and hard-coded into + header files or board specific files. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" @@ -263,6 +276,20 @@ config SYS_OR7_PRELIM depends on SYS_BR7_PRELIM_BOOL endmenu +if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \ + TARGET_P1020RDB_PD || TARGET_P2020RDB + +config COMMON_INIT_DDR + bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)" + +config SPL_COMMON_INIT_DDR + bool "Do not have a TLB entry to cover common DDR init with SPD in SPL" + +config TPL_COMMON_INIT_DDR + bool "Do not have a TLB entry to cover common DDR init with SPD in TPL" + +endif + config SYS_FSL_ERRATUM_A008378 bool diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 6a4f4f1365bda909a52887d29bf7441a4bee8e76..56f348700d4ef6c2151aa6853d8392317566673d 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -7,3 +7,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o +k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o diff --git a/drivers/dma/ti/k3-psil-am62.c b/drivers/dma/ti/k3-psil-am62.c new file mode 100644 index 0000000000000000000000000000000000000000..9527da4cac5208b329f6e470fdfb0229a2e22f34 --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62_src_ep_map[] = { + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62_dst_ep_map[] = { + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62_ep_map = { + .name = "am62", + .src = am62_src_ep_map, + .src_count = ARRAY_SIZE(am62_src_ep_map), + .dst = am62_dst_ep_map, + .dst_count = ARRAY_SIZE(am62_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 77acaf21393a9732c2fbc5bfd92a589d16125522..28078c6bd8d7d2fcc0b3463690a31a520bb462cb 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -41,5 +41,6 @@ extern struct psil_ep_map am654_ep_map; extern struct psil_ep_map j721e_ep_map; extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am64_ep_map; +extern struct psil_ep_map am62_ep_map; #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 8b2129d4f58d30eedaf215b5e4493bd3d45acd3a..f1330bf4b034bad94f01f7e8832207e46b3bbe87 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -24,6 +24,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) soc_ep_map = &j721s2_ep_map; else if (IS_ENABLED(CONFIG_SOC_K3_AM642)) soc_ep_map = &am64_ep_map; + else if (IS_ENABLED(CONFIG_SOC_K3_AM625)) + soc_ep_map = &am62_ep_map; } if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) { diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index ef958b3a7a4e7babd16da3244dde5ae4e5e5385d..eae1c8ddc9f949736eff3ce6432ed497d2e49b72 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -3,7 +3,7 @@ config FIRMWARE config SPL_FIRMWARE bool "Enable Firmware driver support in SPL" - depends on FIRMWARE + depends on FIRMWARE && SPL config SPL_ARM_PSCI_FW bool @@ -37,4 +37,12 @@ config ZYNQMP_FIRMWARE Say yes to enable ZynqMP firmware interface driver. If in doubt, say N. +config ARM_SMCCC_FEATURES + bool "Arm SMCCC features discovery" + depends on ARM_PSCI_FW + help + Discover Arm SMCCC features for which a U-Boot driver is defined. When enabled, + the PSCI driver is always probed and binds dirvers registered to the Arm SMCCC + services if any and reported as supported by the SMCCC firmware. + source "drivers/firmware/scmi/Kconfig" diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 0f0d2b07c00597bcb3a7534cb1cb0ed18f76a640..b0cd647aa518b506cd75e27aa1c1e90bc920447a 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -26,7 +26,7 @@ struct zynqmp_power { struct mbox_chan tx_chan; struct mbox_chan rx_chan; -} zynqmp_power; +} zynqmp_power = {}; #define NODE_ID_LOCATION 5 @@ -79,6 +79,20 @@ int zynqmp_pmufw_node(u32 id) return 0; } +static int do_pm_probe(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, + DM_DRIVER_GET(zynqmp_power), + &dev); + if (ret) + debug("%s: Probing device failed: %d\n", __func__, ret); + + return ret; +} + static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) { struct zynqmp_ipi_msg msg; @@ -92,8 +106,11 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) res_maxlen > PMUFW_PAYLOAD_ARG_CNT) return -EINVAL; - if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev)) - return -EINVAL; + if (!(zynqmp_power.tx_chan.dev) || !(zynqmp_power.rx_chan.dev)) { + ret = do_pm_probe(); + if (ret) + return ret; + } debug("%s, Sending IPI message with ID: 0x%0x\n", __func__, req[0]); msg.buf = (u32 *)req; diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 657e7eb5aea387adf0c534c525a1d8263a7aa1e8..ef3e983646171632347b9403d604326558bbed75 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -9,18 +9,20 @@ #include #include #include +#include #include +#include #include -#include -#include #include -#include -#include +#include +#include +#include #include +#include #include +#include #include #include -#include #define DRIVER_NAME "psci" @@ -95,6 +97,76 @@ static bool psci_is_system_reset2_supported(void) return false; } +static void smccc_invoke_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res) +{ + arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res); +} + +static void smccc_invoke_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res) +{ + arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); +} + +static int bind_smccc_features(struct udevice *dev, int psci_method) +{ + struct psci_plat_data *pdata = dev_get_plat(dev); + struct arm_smccc_feature *feature; + size_t feature_cnt, n; + + if (!IS_ENABLED(CONFIG_ARM_SMCCC_FEATURES)) + return 0; + + /* + * SMCCC features discovery invoke SMCCC standard function ID + * ARM_SMCCC_ARCH_FEATURES but this sequence requires that this + * standard ARM_SMCCC_ARCH_FEATURES function ID itself is supported. + * It is queried here with invoking PSCI_FEATURES known available + * from PSCI 1.0. + */ + if (!device_is_compatible(dev, "arm,psci-1.0") || + PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0) + return 0; + + if (request_psci_features(ARM_SMCCC_ARCH_FEATURES) == + PSCI_RET_NOT_SUPPORTED) + return 0; + + if (psci_method == PSCI_METHOD_HVC) + pdata->invoke_fn = smccc_invoke_hvc; + else + pdata->invoke_fn = smccc_invoke_smc; + + feature_cnt = ll_entry_count(struct arm_smccc_feature, arm_smccc_feature); + feature = ll_entry_start(struct arm_smccc_feature, arm_smccc_feature); + + for (n = 0; n < feature_cnt; n++, feature++) { + const char *drv_name = feature->driver_name; + struct udevice *dev2; + int ret; + + if (!feature->is_supported || !feature->is_supported(pdata->invoke_fn)) + continue; + + ret = device_bind_driver(dev, drv_name, drv_name, &dev2); + if (ret) { + pr_warn("%s was not bound: %d, ignore\n", drv_name, ret); + continue; + } + + dev_set_parent_plat(dev2, dev_get_plat(dev)); + } + + return 0; +} + static int psci_bind(struct udevice *dev) { /* No SYSTEM_RESET support for PSCI 0.1 */ @@ -109,6 +181,10 @@ static int psci_bind(struct udevice *dev) pr_debug("PSCI System Reset was not bound.\n"); } + /* From PSCI v1.0 onward we can discover services through ARM_SMCCC_FEATURE */ + if (IS_ENABLED(CONFIG_ARM_SMCCC_FEATURES) && device_is_compatible(dev, "arm,psci-1.0")) + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + return 0; } @@ -136,7 +212,7 @@ static int psci_probe(struct udevice *dev) return -EINVAL; } - return 0; + return bind_smccc_features(dev, psci_method); } /** @@ -240,4 +316,7 @@ U_BOOT_DRIVER(psci) = { .of_match = psci_of_match, .bind = psci_bind, .probe = psci_probe, +#ifdef CONFIG_ARM_SMCCC_FEATURES + .plat_auto = sizeof(struct psci_plat_data), +#endif }; diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index 8e4af0c8faf08e06a7f903a624d33858eee12069..3efdab9e723bdb0226a3192228ee98332b67370a 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -31,9 +31,19 @@ struct scmi_mbox_channel { ulong timeout_us; }; -static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg) +/** + * struct scmi_channel - Channel instance referenced in SCMI drivers + * @ref: Reference to local channel instance + **/ +struct scmi_channel { + struct scmi_mbox_channel ref; +}; + +static int scmi_mbox_process_msg(struct udevice *dev, + struct scmi_channel *channel, + struct scmi_msg *msg) { - struct scmi_mbox_channel *chan = dev_get_plat(dev); + struct scmi_mbox_channel *chan = &channel->ref; int ret; ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); @@ -62,13 +72,10 @@ out: return ret; } -int scmi_mbox_of_to_plat(struct udevice *dev) +static int setup_channel(struct udevice *dev, struct scmi_mbox_channel *chan) { - struct scmi_mbox_channel *chan = dev_get_plat(dev); int ret; - chan->timeout_us = TIMEOUT_US_10MS; - ret = mbox_get_by_index(dev, 0, &chan->mbox); if (ret) { dev_err(dev, "Failed to find mailbox: %d\n", ret); @@ -76,10 +83,51 @@ int scmi_mbox_of_to_plat(struct udevice *dev) } ret = scmi_dt_get_smt_buffer(dev, &chan->smt); - if (ret) + if (ret) { dev_err(dev, "Failed to get shm resources: %d\n", ret); + return ret; + } - return ret; + chan->timeout_us = TIMEOUT_US_10MS; + + return 0; +} + +static int scmi_mbox_get_channel(struct udevice *dev, + struct scmi_channel **channel) +{ + struct scmi_mbox_channel *base_chan = dev_get_plat(dev->parent); + struct scmi_mbox_channel *chan; + int ret; + + if (!dev_read_prop(dev, "shmem", NULL)) { + /* Uses agent base channel */ + *channel = container_of(base_chan, struct scmi_channel, ref); + + return 0; + } + + chan = calloc(1, sizeof(*chan)); + if (!chan) + return -ENOMEM; + + /* Setup a dedicated channel for the protocol */ + ret = setup_channel(dev, chan); + if (ret) { + free(chan); + return ret; + } + + *channel = (void *)chan; + + return 0; +} + +int scmi_mbox_of_to_plat(struct udevice *dev) +{ + struct scmi_mbox_channel *chan = dev_get_plat(dev); + + return setup_channel(dev, chan); } static const struct udevice_id scmi_mbox_ids[] = { @@ -88,6 +136,7 @@ static const struct udevice_id scmi_mbox_ids[] = { }; static const struct scmi_agent_ops scmi_mbox_ops = { + .of_get_channel = scmi_mbox_get_channel, .process_msg = scmi_mbox_process_msg, }; diff --git a/drivers/firmware/scmi/optee_agent.c b/drivers/firmware/scmi/optee_agent.c index 1f2659223434a3c0db58c043a519ad85ccc8534f..2b2b8c1670a355b737dd76fe2c145d11e72f89fa 100644 --- a/drivers/firmware/scmi/optee_agent.c +++ b/drivers/firmware/scmi/optee_agent.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020-2021 Linaro Limited. + * Copyright (C) 2020-2022 Linaro Limited. */ #define LOG_CATEGORY UCLASS_SCMI_AGENT @@ -35,6 +35,14 @@ struct scmi_optee_channel { bool dyn_shm; }; +/** + * struct scmi_channel - Channel instance referenced in SCMI drivers + * @ref: Reference to local channel instance + **/ +struct scmi_channel { + struct scmi_optee_channel ref; +}; + /** * struct channel_session - Aggreates SCMI service session context references * @tee: OP-TEE device to invoke @@ -91,13 +99,27 @@ enum optee_smci_pta_cmd { /* * PTA_SCMI_CMD_GET_CHANNEL - Get channel handle * - * SCMI shm information are 0 if agent expects to use OP-TEE regular SHM - * * [in] value[0].a: Channel identifier * [out] value[0].a: Returned channel handle * [in] value[0].b: Requested capabilities mask (enum pta_scmi_caps) */ PTA_SCMI_CMD_GET_CHANNEL = 3, + + /* + * PTA_SCMI_CMD_PROCESS_MSG_CHANNEL - Process SCMI message in MSG + * buffers pointed by memref parameters + * + * [in] value[0].a: Channel handle + * [in] memref[1]: Message buffer (MSG header and SCMI payload) + * [out] memref[2]: Response buffer (MSG header and SCMI payload) + * + * Shared memories used for SCMI message/response are MSG buffers + * referenced by param[1] and param[2]. MSG transport protocol + * uses a 32bit header to carry SCMI meta-data (protocol ID and + * protocol message ID) followed by the effective SCMI message + * payload. + */ + PTA_SCMI_CMD_PROCESS_MSG_CHANNEL = 4, }; /* @@ -106,14 +128,22 @@ enum optee_smci_pta_cmd { * PTA_SCMI_CAPS_SMT_HEADER * When set, OP-TEE supports command using SMT header protocol (SCMI shmem) in * shared memory buffers to carry SCMI protocol synchronisation information. + * + * PTA_SCMI_CAPS_MSG_HEADER + * When set, OP-TEE supports command using MSG header protocol in an OP-TEE + * shared memory to carry SCMI protocol synchronisation information and SCMI + * message payload. */ #define PTA_SCMI_CAPS_NONE 0 #define PTA_SCMI_CAPS_SMT_HEADER BIT(0) +#define PTA_SCMI_CAPS_MSG_HEADER BIT(1) +#define PTA_SCMI_CAPS_MASK (PTA_SCMI_CAPS_SMT_HEADER | \ + PTA_SCMI_CAPS_MSG_HEADER) -static int open_channel(struct udevice *dev, struct channel_session *sess) +static int open_channel(struct udevice *dev, struct scmi_optee_channel *chan, + struct channel_session *sess) { const struct tee_optee_ta_uuid uuid = TA_SCMI_UUID; - struct scmi_optee_channel *chan = dev_get_plat(dev); struct tee_open_session_arg sess_arg = { }; struct tee_invoke_arg cmd_arg = { }; struct tee_param param[1] = { }; @@ -139,7 +169,10 @@ static int open_channel(struct udevice *dev, struct channel_session *sess) param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT; param[0].u.value.a = chan->channel_id; - param[0].u.value.b = PTA_SCMI_CAPS_SMT_HEADER; + if (chan->dyn_shm) + param[0].u.value.b = PTA_SCMI_CAPS_MSG_HEADER; + else + param[0].u.value.b = PTA_SCMI_CAPS_SMT_HEADER; ret = tee_invoke_func(sess->tee, &cmd_arg, ARRAY_SIZE(param), param); if (ret || cmd_arg.ret) { @@ -162,45 +195,58 @@ static void close_channel(struct channel_session *sess) tee_close_session(sess->tee, sess->tee_session); } -static int invoke_cmd(struct udevice *dev, struct channel_session *sess, - struct scmi_msg *msg) +static int invoke_cmd(struct udevice *dev, struct scmi_optee_channel *chan, + struct channel_session *sess, struct scmi_msg *msg) { - struct scmi_optee_channel *chan = dev_get_plat(dev); struct tee_invoke_arg arg = { }; - struct tee_param param[2] = { }; + struct tee_param param[3] = { }; int ret; - scmi_write_msg_to_smt(dev, &chan->smt, msg); - arg.session = sess->tee_session; param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT; param[0].u.value.a = sess->channel_hdl; - if (chan->dyn_shm) { - arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE; - param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT; + if (sess->tee_shm) { + size_t in_size; + + ret = scmi_msg_to_smt_msg(dev, &chan->smt, msg, &in_size); + if (ret < 0) + return ret; + + arg.func = PTA_SCMI_CMD_PROCESS_MSG_CHANNEL; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; param[1].u.memref.shm = sess->tee_shm; - param[1].u.memref.size = SCMI_SHM_SIZE; + param[1].u.memref.size = in_size; + param[2].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + param[2].u.memref.shm = sess->tee_shm; + param[2].u.memref.size = sess->tee_shm->size; } else { arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL; + scmi_write_msg_to_smt(dev, &chan->smt, msg); } ret = tee_invoke_func(sess->tee, &arg, ARRAY_SIZE(param), param); if (ret || arg.ret) { if (!ret) ret = -EPROTO; + + return ret; + } + + if (sess->tee_shm) { + ret = scmi_msg_from_smt_msg(dev, &chan->smt, msg, + param[2].u.memref.size); } else { ret = scmi_read_resp_from_smt(dev, &chan->smt, msg); + scmi_clear_smt_channel(&chan->smt); } - scmi_clear_smt_channel(&chan->smt); - return ret; } -static int prepare_shm(struct udevice *dev, struct channel_session *sess) +static int prepare_shm(struct udevice *dev, struct scmi_optee_channel *chan, + struct channel_session *sess) { - struct scmi_optee_channel *chan = dev_get_plat(dev); int ret; /* Static shm is already prepared by the firmware: nothing to do */ @@ -217,9 +263,6 @@ static int prepare_shm(struct udevice *dev, struct channel_session *sess) chan->smt.buf = sess->tee_shm->addr; - /* Initialize shm buffer for message exchanges */ - scmi_clear_smt_channel(&chan->smt); - return 0; } @@ -231,20 +274,23 @@ static void release_shm(struct udevice *dev, struct channel_session *sess) tee_shm_free(sess->tee_shm); } -static int scmi_optee_process_msg(struct udevice *dev, struct scmi_msg *msg) +static int scmi_optee_process_msg(struct udevice *dev, + struct scmi_channel *channel, + struct scmi_msg *msg) { - struct channel_session sess; + struct scmi_optee_channel *chan = &channel->ref; + struct channel_session sess = { }; int ret; - ret = open_channel(dev, &sess); + ret = open_channel(dev, chan, &sess); if (ret) return ret; - ret = prepare_shm(dev, &sess); + ret = prepare_shm(dev, chan, &sess); if (ret) goto out; - ret = invoke_cmd(dev, &sess, msg); + ret = invoke_cmd(dev, chan, &sess, msg); release_shm(dev, &sess); @@ -254,9 +300,8 @@ out: return ret; } -static int scmi_optee_of_to_plat(struct udevice *dev) +static int setup_channel(struct udevice *dev, struct scmi_optee_channel *chan) { - struct scmi_optee_channel *chan = dev_get_plat(dev); int ret; if (dev_read_u32(dev, "linaro,optee-channel-id", &chan->channel_id)) { @@ -278,13 +323,52 @@ static int scmi_optee_of_to_plat(struct udevice *dev) return 0; } +static int scmi_optee_get_channel(struct udevice *dev, + struct scmi_channel **channel) +{ + struct scmi_optee_channel *base_chan = dev_get_plat(dev->parent); + struct scmi_optee_channel *chan; + u32 channel_id; + int ret; + + if (dev_read_u32(dev, "linaro,optee-channel-id", &channel_id)) { + /* Uses agent base channel */ + *channel = container_of(base_chan, struct scmi_channel, ref); + + return 0; + } + + /* Setup a dedicated channel */ + chan = calloc(1, sizeof(*chan)); + if (!chan) + return -ENOMEM; + + ret = setup_channel(dev, chan); + if (ret) { + free(chan); + return ret; + } + + *channel = container_of(chan, struct scmi_channel, ref); + + return 0; +} + +static int scmi_optee_of_to_plat(struct udevice *dev) +{ + struct scmi_optee_channel *chan = dev_get_plat(dev); + + return setup_channel(dev, chan); +} + static int scmi_optee_probe(struct udevice *dev) { + struct scmi_optee_channel *chan = dev_get_plat(dev); struct channel_session sess; int ret; /* Check OP-TEE service acknowledges the SCMI channel */ - ret = open_channel(dev, &sess); + ret = open_channel(dev, chan, &sess); if (!ret) close_channel(&sess); @@ -297,6 +381,7 @@ static const struct udevice_id scmi_optee_ids[] = { }; static const struct scmi_agent_ops scmi_optee_ops = { + .of_get_channel = scmi_optee_get_channel, .process_msg = scmi_optee_process_msg, }; diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index c555164d1961013164efd7ef4e64ab1ddabfed9c..031882998dfaea9fa7043fffbec213b0d37d524b 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -471,6 +471,7 @@ static int sandbox_scmi_voltd_level_get(struct udevice *dev, } static int sandbox_scmi_test_process_msg(struct udevice *dev, + struct scmi_channel *channel, struct scmi_msg *msg) { switch (msg->protocol_id) { diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 3819f2fa993e57b5841be2f7d2595f054e7dc977..2b6211c4e6a09fbfc5b06563c809bb21e6cf2f94 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -109,30 +109,56 @@ static int scmi_bind_protocols(struct udevice *dev) return ret; } -static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev) +static struct udevice *find_scmi_transport_device(struct udevice *dev) { - return (const struct scmi_agent_ops *)dev->driver->ops; -} - -int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg) -{ - const struct scmi_agent_ops *ops; struct udevice *parent = dev; - /* Find related SCMI agent device */ do { parent = dev_get_parent(parent); } while (parent && device_get_uclass_id(parent) != UCLASS_SCMI_AGENT); - if (!parent) { + if (!parent) dev_err(dev, "Invalid SCMI device, agent not found\n"); + + return parent; +} + +static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev) +{ + return (const struct scmi_agent_ops *)dev->driver->ops; +} + +int devm_scmi_of_get_channel(struct udevice *dev, struct scmi_channel **channel) +{ + struct udevice *parent; + + parent = find_scmi_transport_device(dev); + if (!parent) + return -ENODEV; + + if (transport_dev_ops(parent)->of_get_channel) + return transport_dev_ops(parent)->of_get_channel(dev, channel); + + /* Drivers without a get_channel operator don't need a channel ref */ + *channel = NULL; + + return 0; +} + +int devm_scmi_process_msg(struct udevice *dev, struct scmi_channel *channel, + struct scmi_msg *msg) +{ + const struct scmi_agent_ops *ops; + struct udevice *parent; + + parent = find_scmi_transport_device(dev); + if (!parent) return -ENODEV; - } ops = transport_dev_ops(parent); if (ops->process_msg) - return ops->process_msg(parent, msg); + return ops->process_msg(parent, channel, msg); return -EPROTONOSUPPORT; } diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index 5e166ca93ee1f4dd332f623800e2278a826b715b..bc2eb67335b9764978800cf3f59f11aa676a835c 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -30,9 +30,19 @@ struct scmi_smccc_channel { struct scmi_smt smt; }; -static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) +/** + * struct scmi_channel - Channel instance referenced in SCMI drivers + * @ref: Reference to local channel instance + **/ +struct scmi_channel { + struct scmi_smccc_channel ref; +}; + +static int scmi_smccc_process_msg(struct udevice *dev, + struct scmi_channel *channel, + struct scmi_msg *msg) { - struct scmi_smccc_channel *chan = dev_get_plat(dev); + struct scmi_smccc_channel *chan = &channel->ref; struct arm_smccc_res res; int ret; @@ -51,9 +61,8 @@ static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) return ret; } -static int scmi_smccc_of_to_plat(struct udevice *dev) +static int setup_channel(struct udevice *dev, struct scmi_smccc_channel *chan) { - struct scmi_smccc_channel *chan = dev_get_plat(dev); u32 func_id; int ret; @@ -71,12 +80,51 @@ static int scmi_smccc_of_to_plat(struct udevice *dev) return ret; } +static int scmi_smccc_get_channel(struct udevice *dev, + struct scmi_channel **channel) +{ + struct scmi_smccc_channel *base_chan = dev_get_plat(dev->parent); + struct scmi_smccc_channel *chan; + u32 func_id; + int ret; + + if (dev_read_u32(dev, "arm,smc-id", &func_id)) { + /* Uses agent base channel */ + *channel = container_of(base_chan, struct scmi_channel, ref); + + return 0; + } + + /* Setup a dedicated channel */ + chan = calloc(1, sizeof(*chan)); + if (!chan) + return -ENOMEM; + + ret = setup_channel(dev, chan); + if (ret) { + free(chan); + return ret; + } + + *channel = container_of(chan, struct scmi_channel, ref); + + return 0; +} + +static int scmi_smccc_of_to_plat(struct udevice *dev) +{ + struct scmi_smccc_channel *chan = dev_get_plat(dev); + + return setup_channel(dev, chan); +} + static const struct udevice_id scmi_smccc_ids[] = { { .compatible = "arm,scmi-smc" }, { } }; static const struct scmi_agent_ops scmi_smccc_ops = { + .of_get_channel = scmi_smccc_get_channel, .process_msg = scmi_smccc_process_msg, }; diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c index e60c2aebc895fa11bac3a39002755b8c4cbe090b..509ed618a997ff7ecdc0d2ef953f68c3b944607f 100644 --- a/drivers/firmware/scmi/smt.c +++ b/drivers/firmware/scmi/smt.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. - * Copyright (C) 2019-2020 Linaro Limited. + * Copyright (C) 2019-2022 Linaro Limited. */ #define LOG_CATEGORY UCLASS_SCMI_AGENT @@ -137,3 +137,54 @@ void scmi_clear_smt_channel(struct scmi_smt *smt) hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR; } + +/** + * Write SCMI message @msg into a SMT_MSG shared buffer @smt. + * Return 0 on success and with a negative errno in case of error. + */ +int scmi_msg_to_smt_msg(struct udevice *dev, struct scmi_smt *smt, + struct scmi_msg *msg, size_t *buf_size) +{ + struct scmi_smt_msg_header *hdr = (void *)smt->buf; + + if ((!msg->in_msg && msg->in_msg_sz) || + (!msg->out_msg && msg->out_msg_sz)) + return -EINVAL; + + if (smt->size < (sizeof(*hdr) + msg->in_msg_sz) || + smt->size < (sizeof(*hdr) + msg->out_msg_sz)) { + dev_dbg(dev, "Buffer too small\n"); + return -ETOOSMALL; + } + + *buf_size = msg->in_msg_sz + sizeof(hdr->msg_header); + + hdr->msg_header = SMT_HEADER_TOKEN(0) | + SMT_HEADER_MESSAGE_TYPE(0) | + SMT_HEADER_PROTOCOL_ID(msg->protocol_id) | + SMT_HEADER_MESSAGE_ID(msg->message_id); + + memcpy(hdr->msg_payload, msg->in_msg, msg->in_msg_sz); + + return 0; +} + +/** + * Read SCMI message from a SMT shared buffer @smt and copy it into @msg. + * Return 0 on success and with a negative errno in case of error. + */ +int scmi_msg_from_smt_msg(struct udevice *dev, struct scmi_smt *smt, + struct scmi_msg *msg, size_t buf_size) +{ + struct scmi_smt_msg_header *hdr = (void *)smt->buf; + + if (buf_size > msg->out_msg_sz + sizeof(hdr->msg_header)) { + dev_err(dev, "Buffer to small\n"); + return -ETOOSMALL; + } + + msg->out_msg_sz = buf_size - sizeof(hdr->msg_header); + memcpy(msg->out_msg, hdr->msg_payload, msg->out_msg_sz); + + return 0; +} diff --git a/drivers/firmware/scmi/smt.h b/drivers/firmware/scmi/smt.h index a8c0987bd30e8c0034753e85ced580c2ecc9dab8..9d669a6c922666c48e7dce4c0affd7b47cb137e4 100644 --- a/drivers/firmware/scmi/smt.h +++ b/drivers/firmware/scmi/smt.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. - * Copyright (C) 2019-2020 Linaro Limited. + * Copyright (C) 2019-2022 Linaro Limited. */ #ifndef SCMI_SMT_H #define SCMI_SMT_H @@ -29,6 +29,17 @@ struct scmi_smt_header { u8 msg_payload[0]; }; +/** + * struct scmi_msg_header - Description of a MSG shared memory message buffer + * + * MSG communication protocol uses a 32bit header memory cell to store SCMI + * protocol data followed by the exchange SCMI message payload. + */ +struct scmi_smt_msg_header { + __le32 msg_header; + u8 msg_payload[0]; +}; + #define SMT_HEADER_TOKEN(token) (((token) << 18) & GENMASK(31, 18)) #define SMT_HEADER_PROTOCOL_ID(proto) (((proto) << 10) & GENMASK(17, 10)) #define SMT_HEADER_MESSAGE_TYPE(type) (((type) << 18) & GENMASK(9, 8)) @@ -75,12 +86,44 @@ static inline void scmi_smt_put_channel(struct scmi_smt *smt) int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt); +/* + * Write SCMI message to a SMT shared memory + * @dev: SCMI device + * @smt: Reference to shared memory using SMT header + * @msg: Input SCMI message transmitted + */ int scmi_write_msg_to_smt(struct udevice *dev, struct scmi_smt *smt, struct scmi_msg *msg); +/* + * Read SCMI message from a SMT shared memory + * @dev: SCMI device + * @smt: Reference to shared memory using SMT header + * @msg: Output SCMI message received + */ int scmi_read_resp_from_smt(struct udevice *dev, struct scmi_smt *smt, struct scmi_msg *msg); void scmi_clear_smt_channel(struct scmi_smt *smt); +/* + * Write SCMI message to SMT_MSG shared memory + * @dev: SCMI device + * @smt: Reference to shared memory using SMT_MSG header + * @msg: Input SCMI message transmitted + * @buf_size: Size of the full SMT_MSG buffer transmitted + */ +int scmi_msg_to_smt_msg(struct udevice *dev, struct scmi_smt *smt, + struct scmi_msg *msg, size_t *buf_size); + +/* + * Read SCMI message from SMT_MSG shared memory + * @dev: SCMI device + * @smt: Reference to shared memory using SMT_MSG header + * @msg: Output SCMI message received + * @buf_size: Size of the full SMT_MSG buffer received + */ +int scmi_msg_from_smt_msg(struct udevice *dev, struct scmi_smt *smt, + struct scmi_msg *msg, size_t buf_size); + #endif /* SCMI_SMT_H */ diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index e6a3b66c03fbe3397a9fe904bd1a1012ce76ce2c..5ae0556a9a4539399f9dfff6cbc27cd5f02f2dc2 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -16,7 +16,7 @@ struct ti_sci_resource_static_data { #if IS_ENABLED(CONFIG_K3_DM_FW) -#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM) +#if IS_ENABLED(CONFIG_SOC_K3_J721E) static struct ti_sci_resource_static_data rm_static_data[] = { /* Free rings */ { @@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_TARGET_J721E_R5_EVM */ +#endif /* CONFIG_SOC_K3_J721E */ -#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM) -static struct ti_sci_resource_static_data rm_static_data[] = { - /* Free rings */ - { - .dev_id = 235, - .subtype = 1, - .range_start = 124, - .range_num = 32, - }, - /* TX channels */ - { - .dev_id = 236, - .subtype = 13, - .range_start = 6, - .range_num = 2, - }, - /* RX channels */ - { - .dev_id = 236, - .subtype = 10, - .range_start = 6, - .range_num = 2, - }, - /* RX Free flows */ - { - .dev_id = 236, - .subtype = 0, - .range_start = 60, - .range_num = 8, - }, - { }, -}; -#endif /* CONFIG_TARGET_J7200_R5_EVM */ - -#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM) +#if IS_ENABLED(CONFIG_SOC_K3_J721S2) static struct ti_sci_resource_static_data rm_static_data[] = { /* Free rings */ { @@ -116,7 +82,20 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_TARGET_J721S2_R5_EVM */ +#endif /* CONFIG_SOC_K3_J721S2 */ + +#if IS_ENABLED(CONFIG_SOC_K3_AM625) +static struct ti_sci_resource_static_data rm_static_data[] = { + /* BC channels */ + { + .dev_id = 26, + .subtype = 32, + .range_start = 18, + .range_num = 2, + }, + { }, +}; +#endif /* CONFIG_SOC_K3_AM625 */ #else static struct ti_sci_resource_static_data rm_static_data[] = { diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dc0b3dd31b7d1d95371ef3afd72c28d48f5fb0d2..76719517f541f920bdaf282604fd3e1c30603bff 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,12 @@ config FPGA_SOCFPGA This provides common functionality for Gen5 and Arria10 devices. +config FPGA_STRATIX_V + bool "Enable Stratix V FPGA drivers" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Stratix V FPGA specific driver. + config FPGA_CYCLON2 bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA diff --git a/drivers/fuzz/Kconfig b/drivers/fuzz/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..6311385222f3577864d465b5b0e7731b0ef6ebb7 --- /dev/null +++ b/drivers/fuzz/Kconfig @@ -0,0 +1,17 @@ +config DM_FUZZING_ENGINE + bool "Driver support for fuzzing engine devices" + depends on DM + help + Enable driver model for fuzzing engine devices. This interface is + used to get fuzzing inputs from a fuzzing engine. + +if DM_FUZZING_ENGINE + +config FUZZING_ENGINE_SANDBOX + bool "Sanbox fuzzing engine" + depends on SANDBOX + default y + help + Enable fuzzing engine for sandbox. + +endif diff --git a/drivers/fuzz/Makefile b/drivers/fuzz/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..073743ba9468080d704d8cfa5c7a93b40420b9ca --- /dev/null +++ b/drivers/fuzz/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2022 Google, Inc. +# Written by Andrew Scull +# + +obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o +obj-$(CONFIG_FUZZING_ENGINE_SANDBOX) += sandbox_fuzzing_engine.o diff --git a/drivers/fuzz/fuzzing_engine-uclass.c b/drivers/fuzz/fuzzing_engine-uclass.c new file mode 100644 index 0000000000000000000000000000000000000000..b16f1c4cfb71024890bf7f689273a47104107b2e --- /dev/null +++ b/drivers/fuzz/fuzzing_engine-uclass.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#define LOG_CATEGORY UCLASS_FUZZING_ENGINE + +#include +#include +#include + +int dm_fuzzing_engine_get_input(struct udevice *dev, + const uint8_t **data, + size_t *size) +{ + const struct dm_fuzzing_engine_ops *ops = device_get_ops(dev); + + if (!ops->get_input) + return -ENOSYS; + + return ops->get_input(dev, data, size); +} + +UCLASS_DRIVER(fuzzing_engine) = { + .name = "fuzzing_engine", + .id = UCLASS_FUZZING_ENGINE, +}; diff --git a/drivers/fuzz/sandbox_fuzzing_engine.c b/drivers/fuzz/sandbox_fuzzing_engine.c new file mode 100644 index 0000000000000000000000000000000000000000..ebb938e5ba8610bf9ad72ae1ce7506dad51cec9a --- /dev/null +++ b/drivers/fuzz/sandbox_fuzzing_engine.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#include +#include +#include +#include + +static int get_input(struct udevice *dev, + const uint8_t **data, + size_t *size) +{ + return sandbox_fuzzing_engine_get_input(data, size); +} + +static const struct dm_fuzzing_engine_ops sandbox_fuzzing_engine_ops = { + .get_input = get_input, +}; + +static const struct udevice_id sandbox_fuzzing_engine_match[] = { + { + .compatible = "sandbox,fuzzing-engine", + }, + {}, +}; + +U_BOOT_DRIVER(sandbox_fuzzing_engine) = { + .name = "sandbox-fuzzing-engine", + .id = UCLASS_FUZZING_ENGINE, + .of_match = sandbox_fuzzing_engine_match, + .ops = &sandbox_fuzzing_engine_ops, +}; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d7f37f0471cb0c5412ade6460c8a0e6bc5cb9ed6..3c73a7f61838d534eda66932716bf27c97f87b47 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -89,7 +89,7 @@ config DM_GPIO_LOOKUP_LABEL config SPL_DM_GPIO_LOOKUP_LABEL bool "Enable searching for gpio labelnames" - depends on DM_GPIO && SPL_DM && SPL_GPIO + depends on SPL_DM_GPIO help This option enables searching for gpio names in the defined gpio labels, if the search for the @@ -491,7 +491,7 @@ config DM_PCA953X config SPL_DM_PCA953X bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL" - depends on DM_GPIO + depends on SPL_DM_GPIO help Say yes here to provide access to several register-oriented SMBus I/O expanders, made mostly by NXP or TI. Compatible diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index bea609db9df95ae0d93c112d0c5950eac469e4f8..77a76c1d5051443ae5604070b87702a01ab2c014 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -36,6 +36,11 @@ static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) case AT91_PIO_PORTD: base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD; break; +#if (ATMEL_PIO_PORTS > 4) + case AT91_PIO_PORTE: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOE; + break; +#endif default: printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n", port); diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index d25c5736ef086cf01b4a29b6fa005c59612598ce..72d06e4972b57319d7e3a6379606fa7f643ef0ab 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -687,9 +687,9 @@ config SYS_I2C_SPEED config SYS_I2C_BUS_MAX int "Max I2C busses" - depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA + depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA default 2 if TI816X - default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE + default 3 if OMAP34XX || AM33XX || AM43XX default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X default 5 if OMAP54XX help diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index 2d3fecaa14ea4d4047e1076374e8ce7e2b0a4fc7..c9ffe2d62820a8527cc22209f88e9608cdb24d33 100644 --- a/drivers/i2c/ast_i2c.c +++ b/drivers/i2c/ast_i2c.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "ast_i2c.h" @@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev) static int ast_i2c_probe(struct udevice *dev) { - struct ast2500_scu *scu; + struct reset_ctl reset_ctl; + int rc; debug("Enabling I2C%u\n", dev_seq(dev)); /* * Get all I2C devices out of Reset. - * Only needs to be done once, but doing it for every - * device does not hurt. + * + * Only needs to be done once so test before performing reset. */ - scu = ast_get_scu(); - ast_scu_unlock(scu); - clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C); - ast_scu_lock(scu); + rc = reset_get_by_index(dev, 0, &reset_ctl); + if (rc) { + printf("%s: Failed to get reset signal\n", __func__); + return rc; + } + + if (reset_status(&reset_ctl) > 0) { + reset_assert(&reset_ctl); + reset_deassert(&reset_ctl); + } ast_i2c_init_bus(dev); @@ -343,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = { static const struct udevice_id ast_i2c_ids[] = { { .compatible = "aspeed,ast2400-i2c-bus" }, { .compatible = "aspeed,ast2500-i2c-bus" }, + { .compatible = "aspeed,ast2600-i2c-bus" }, { }, }; diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index a4abd25c398798df159c65b6f0e5e066a2a8f483..ae177227dea34adc17db0c3492483904f93a768f 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -21,14 +21,12 @@ #include #include "davinci_i2c.h" -#if CONFIG_IS_ENABLED(DM_I2C) /* Information about i2c controller */ struct i2c_bus { int id; uint speed; struct i2c_regs *regs; }; -#endif #define CHECK_NACK() \ do {\ @@ -340,99 +338,6 @@ static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip) return rc; } -#if !CONFIG_IS_ENABLED(DM_I2C) -static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) -{ - switch (adap->hwadapnr) { -#if CONFIG_SYS_I2C_BUS_MAX >= 3 - case 2: - return (struct i2c_regs *)I2C2_BASE; -#endif -#if CONFIG_SYS_I2C_BUS_MAX >= 2 - case 1: - return (struct i2c_regs *)I2C1_BASE; -#endif - case 0: - return (struct i2c_regs *)I2C_BASE; - - default: - printf("wrong hwadapnr: %d\n", adap->hwadapnr); - } - - return NULL; -} - -static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed) -{ - struct i2c_regs *i2c_base = davinci_get_base(adap); - uint ret; - - adap->speed = speed; - ret = _davinci_i2c_setspeed(i2c_base, speed); - - return ret; -} - -static void davinci_i2c_init(struct i2c_adapter *adap, int speed, - int slaveadd) -{ - struct i2c_regs *i2c_base = davinci_get_base(adap); - - adap->speed = speed; - _davinci_i2c_init(i2c_base, speed, slaveadd); - - return; -} - -static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip, - uint32_t addr, int alen, uint8_t *buf, int len) -{ - struct i2c_regs *i2c_base = davinci_get_base(adap); - return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len); -} - -static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip, - uint32_t addr, int alen, uint8_t *buf, int len) -{ - struct i2c_regs *i2c_base = davinci_get_base(adap); - - return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len); -} - -static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip) -{ - struct i2c_regs *i2c_base = davinci_get_base(adap); - - return _davinci_i2c_probe_chip(i2c_base, chip); -} - -U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip, - davinci_i2c_read, davinci_i2c_write, - davinci_i2c_setspeed, - CONFIG_SYS_DAVINCI_I2C_SPEED, - CONFIG_SYS_DAVINCI_I2C_SLAVE, - 0) - -#if CONFIG_SYS_I2C_BUS_MAX >= 2 -U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip, - davinci_i2c_read, davinci_i2c_write, - davinci_i2c_setspeed, - CONFIG_SYS_DAVINCI_I2C_SPEED1, - CONFIG_SYS_DAVINCI_I2C_SLAVE1, - 1) -#endif - -#if CONFIG_SYS_I2C_BUS_MAX >= 3 -U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip, - davinci_i2c_read, davinci_i2c_write, - davinci_i2c_setspeed, - CONFIG_SYS_DAVINCI_I2C_SPEED2, - CONFIG_SYS_DAVINCI_I2C_SLAVE2, - 2) -#endif - -#else /* CONFIG_DM_I2C */ - static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { @@ -507,5 +412,3 @@ U_BOOT_DRIVER(i2c_davinci) = { .priv_auto = sizeof(struct i2c_bus), .ops = &davinci_i2c_ops, }; - -#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 1aae6b64bac320b778290649ec3a5409946bc12d..e54de42abc3957a98f21437c190a05694cf0ed4c 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #include diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index a9c50c90ace5f8c80fea244ca6d41fe12750444e..049976e8a2363510e0c3c0efca0ad22aca094086 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #ifndef __DW_I2C_H_ diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 1572c2c6bceec55c4b9a9d98a0bcbd02e0e14fbc..46c2545f214566f16714a84922b793ba3675b5bc 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. * Copyright 2019 Google Inc */ diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index 39bcacc17a7e122993daad35e46d045a7beb7ebd..a7349e06cfd363597c52c53130253bb1129e313a 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -147,7 +147,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) clkin = get_i2c_clk(); #else clkin = get_PCLK(); diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 39683fc43b4918c4f4f6131221f7e88ce0c2560a..323c4fbe9cccab4c25ea0ef81477857bfb59dd5b 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -9,7 +9,7 @@ config I2C_MUX config SPL_I2C_MUX bool "Support I2C multiplexers on SPL" - depends on I2C_MUX + depends on SPL && I2C_MUX help This enables I2C buses to be multiplexed, so that you can select one of several buses using some sort of control mechanism. The diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index aaccb3aa2280205b3aac14fcb1512d8f94070652..505e20bc61c8c4cea9700b5fc5ad49f8610e60f4 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -8,7 +8,7 @@ #include #include #include -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) #include #include #include @@ -53,7 +53,7 @@ static void read_write_byte(struct s3c24x0_i2c *i2c) static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { ulong freq, pres = 16, div; -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) freq = get_i2c_clk(); #else freq = get_PCLK(); diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 418ed215c57b758eba5802e5c6d96c6bcf63eaa4..ccdd7d7395c852b1b32a9bfe7b87698c1523a997 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -67,7 +67,7 @@ config LED_BLINK config SPL_LED bool "Enable LED support in SPL" - depends on SPL && SPL_DM + depends on SPL_DM help The LED subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use LEDs in SPL, @@ -85,7 +85,7 @@ config LED_GPIO config SPL_LED_GPIO bool "LED support for GPIO-connected LEDs in SPL" - depends on SPL_LED && DM_GPIO + depends on SPL_LED && SPL_DM_GPIO help This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index 10bd1636c3868605427a76071914ad351175ca66..0ebae358ebb73a0d082c61158d416e3710d7b676 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -95,27 +95,17 @@ static enum led_state_t led_pwm_get_state(struct udevice *dev) static int led_pwm_probe(struct udevice *dev) { struct led_pwm_priv *priv = dev_get_priv(dev); - struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); - - /* Ignore the top-level LED node */ - if (!uc_plat->label) - return 0; return led_pwm_set_state(dev, (priv->enabled) ? LEDST_ON : LEDST_OFF); } static int led_pwm_of_to_plat(struct udevice *dev) { - struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); struct led_pwm_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; uint def_brightness, max_brightness; int ret; - /* Ignore the top-level LED node */ - if (!uc_plat->label) - return 0; - ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, &args); if (ret) return ret; @@ -173,10 +163,15 @@ static const struct udevice_id led_pwm_ids[] = { U_BOOT_DRIVER(led_pwm) = { .name = LEDS_PWM_DRIVER_NAME, .id = UCLASS_LED, - .of_match = led_pwm_ids, .ops = &led_pwm_ops, .priv_auto = sizeof(struct led_pwm_priv), - .bind = led_pwm_bind, .probe = led_pwm_probe, .of_to_plat = led_pwm_of_to_plat, }; + +U_BOOT_DRIVER(led_pwm_wrap) = { + .name = LEDS_PWM_DRIVER_NAME "_wrap", + .id = UCLASS_NOP, + .of_match = led_pwm_ids, + .bind = led_pwm_bind, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 007c72819fb983f73caa36c1f2a3ad275d505bed..e839c08c191ee3a4ef5fb2af9177e41cac0a34e4 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -43,6 +43,22 @@ config VPL_MISC set of generic read, write and ioctl methods may be used to access the device. +config NVMEM + bool "NVMEM support" + help + This adds support for a common interface to different types of + non-volatile memory. Consumers can use nvmem-cells properties to look + up hardware configuration data such as MAC addresses and calibration + settings. + +config SPL_NVMEM + bool "NVMEM support in SPL" + help + This adds support for a common interface to different types of + non-volatile memory. Consumers can use nvmem-cells properties to look + up hardware configuration data such as MAC addresses and calibration + settings. + config ALTERA_SYSID bool "Altera Sysid support" depends on MISC @@ -125,7 +141,7 @@ config CROS_EC config SPL_CROS_EC bool "Enable Chrome OS EC in SPL" - depends on SPL + depends on SPL_MISC help Enable access to the Chrome OS EC in SPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -135,7 +151,7 @@ config SPL_CROS_EC config TPL_CROS_EC bool "Enable Chrome OS EC in TPL" - depends on TPL + depends on TPL_MISC help Enable access to the Chrome OS EC in TPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -145,7 +161,7 @@ config TPL_CROS_EC config VPL_CROS_EC bool "Enable Chrome OS EC in VPL" - depends on VPL + depends on VPL_MISC help Enable access to the Chrome OS EC in VPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -173,7 +189,7 @@ config CROS_EC_LPC config SPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in SPL" - depends on CROS_EC + depends on CROS_EC && SPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -182,7 +198,7 @@ config SPL_CROS_EC_LPC config TPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in TPL" - depends on CROS_EC + depends on CROS_EC && TPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -191,7 +207,7 @@ config TPL_CROS_EC_LPC config VPL_CROS_EC_LPC bool "Enable Chrome OS EC LPC driver in VPL" - depends on CROS_EC + depends on CROS_EC && VPL_MISC help Enable I2C access to the Chrome OS EC. This is used on x86 Chromebooks such as link and falco. The keyboard is provided @@ -259,6 +275,20 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. +choice + prompt "Security monitor interaction endianess" + depends on FSL_SEC_MON + default SYS_FSL_SEC_MON_BE if PPC + default SYS_FSL_SEC_MON_LE + +config SYS_FSL_SEC_MON_LE + bool "Security monitor interactions are little endian" + +config SYS_FSL_SEC_MON_BE + bool "Security monitor interactions are big endian" + +endchoice + config IRQ bool "Interrupt controller" help @@ -273,6 +303,20 @@ config JZ4780_EFUSE help This selects support for the eFUSE on Ingenic JZ4780 SoCs. +config LS2_SFP + bool "Layerscape Security Fuse Processor" + depends on FSL_LSCH2 || ARCH_LS1021A + depends on MISC + imply DM_REGULATOR + help + This adds support for the Security Fuse Processor found on Layerscape + SoCs. It contains various fuses related to secure boot, including the + Super Root Key hash, One-Time-Programmable Master Key, Debug + Challenge/Response values, and others. Fuses are numbered according + to their four-byte offset from the start of the bank. + + If you don't need to read/program fuses, say 'n'. + config MXC_OCOTP bool "Enable MXC OCOTP Driver" depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 @@ -282,15 +326,30 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config NPCM_HOST + bool "Enable support espi or LPC for Host" + depends on REGMAP && SYSCON + help + Enable NPCM BMC espi or LPC support for Host reading and writing. + config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" - depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) + depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) default y help If you say Y here, you will get support for the One Time Programmable memory pages, that are stored on some Freescale i.MX processors, in SPL. +config NPCM_OTP + bool "Nnvoton NPCM BMC On-Chip OTP Memory Support" + depends on (ARM && ARCH_NPCM) + default n + help + Support NPCM BMC OTP memory (fuse). + To compile this driver as a module, choose M here: the module + will be called npcm_otp. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help @@ -314,7 +373,7 @@ config P2SB config SPL_P2SB bool "Intel Primary to Sideband Bridge in SPL" - depends on SPL && (X86 || SANDBOX) + depends on SPL_MISC && (X86 || SANDBOX) help The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is @@ -324,7 +383,7 @@ config SPL_P2SB config TPL_P2SB bool "Intel Primary to Sideband Bridge in TPL" - depends on TPL && (X86 || SANDBOX) + depends on TPL_MISC && (X86 || SANDBOX) help The Primary to Sideband Bridge is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is @@ -343,7 +402,7 @@ config PWRSEQ config SPL_PWRSEQ bool "Enable power-sequencing drivers for SPL" - depends on PWRSEQ + depends on SPL_MISC && PWRSEQ help Power-sequencing drivers provide support for controlling power for devices. They are typically referenced by a phandle from another @@ -460,7 +519,7 @@ config I2C_EEPROM config SPL_I2C_EEPROM bool "Enable driver for generic I2C-attached EEPROMs for SPL" - depends on MISC && SPL && SPL_DM + depends on SPL_MISC help This option is an SPL-variant of the I2C_EEPROM option. See the help of I2C_EEPROM for details. @@ -513,6 +572,7 @@ config FS_LOADER config SPL_FS_LOADER bool "Enable loader driver for file system" + depends on SPL help This is file system generic loader which can be used to load the file image from the storage into target such as memory. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b9c54bdd99b85429777ad3e6f51b7b2b2565b5d0..022e54e065085b3cedccda6eeeb7224b8ce657b2 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -4,6 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_$(SPL_TPL_)MISC) += misc-uclass.o +obj-$(CONFIG_$(SPL_TPL_)NVMEM) += nvmem.o obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o @@ -52,8 +53,11 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o +obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NPCM_OTP) += npcm_otp.o +obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 89a450d0f8d6f83683e88e1af1a96ff20fd8270b..bdd7e018cc63e09e8501f6ae59e24b173e849ee2 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -33,7 +33,8 @@ int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size) return ops->read(dev, offset, buf, size); } -int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size) +int i2c_eeprom_write(struct udevice *dev, int offset, const uint8_t *buf, + int size) { const struct i2c_eeprom_ops *ops = device_get_ops(dev); @@ -169,13 +170,6 @@ static const struct i2c_eeprom_drv_data eeprom_data = { .offset_len = 1, }; -static const struct i2c_eeprom_drv_data mc24aa02e48_data = { - .size = 256, - .pagesize = 8, - .addr_offset_mask = 0, - .offset_len = 1, -}; - static const struct i2c_eeprom_drv_data atmel24c01a_data = { .size = 128, .pagesize = 8, @@ -263,7 +257,6 @@ static const struct i2c_eeprom_drv_data atmel24c512_data = { static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "i2c-eeprom", (ulong)&eeprom_data }, - { .compatible = "microchip,24aa02e48", (ulong)&mc24aa02e48_data }, { .compatible = "atmel,24c01", (ulong)&atmel24c01a_data }, { .compatible = "atmel,24c01a", (ulong)&atmel24c01a_data }, { .compatible = "atmel,24c02", (ulong)&atmel24c02_data }, diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 85b127c406c86d2c36019d42707028ac88b720e2..6f32087ede56d7eb98de2affdd64f52625a52342 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -171,11 +171,15 @@ static int sandbox_i2c_eeprom_probe(struct udevice *dev) { struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev); struct sandbox_i2c_flash *priv = dev_get_priv(dev); + /* For eth3 */ + const u8 mac[] = { 0x02, 0x00, 0x11, 0x22, 0x33, 0x45 }; priv->data = calloc(1, plat->size); if (!priv->data) return -ENOMEM; + memcpy(&priv->data[24], mac, sizeof(mac)); + return 0; } diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c new file mode 100644 index 0000000000000000000000000000000000000000..dd104962c28209337bc53a512b4f9b2ba67a4358 --- /dev/null +++ b/drivers/misc/ls2_sfp.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + * + * This driver supports the Security Fuse Processor device found on some + * Layerscape processors. At the moment, we only support a few processors. + * This driver was written with reference to the Layerscape SDK User + * Guide [1] and the ATF SFP driver [2]. + * + * [1] https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-27FC40AD-3321-4A82-B29E-7BB49EE94F23.html + * [2] https://source.codeaurora.org/external/qoriq/qoriq-components/atf/tree/drivers/nxp/sfp?h=github.com/master + */ + +#define LOG_CATEGORY UCLASS_MISC +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SFP_INGR 0x20 +#define SFP_SVHESR 0x24 +#define SFP_SFPCR 0x28 + +#define SFP_START 0x200 +#define SFP_END 0x284 +#define SFP_SIZE (SFP_END - SFP_START + 4) + +#define SFP_INGR_ERR BIT(8) +#define SFP_INGR_INST GENMASK(7, 0) + +#define SFP_INGR_READFB 0x01 +#define SFP_INGR_PROGFB 0x02 + +#define SFP_SFPCR_PPW GENMASK(15, 0) + +enum ls2_sfp_ioctl { + LS2_SFP_IOCTL_READ, + LS2_SFP_IOCTL_PROG, +}; + +/** + * struct ls2_sfp_priv - private data for LS2 SFP + * @base: Base address of SFP + * @supply: The (optional) supply for TA_PROG_SFP + * @programmed: Whether we've already programmed the fuses since the last + * reset. The SFP has a *very* limited amount of programming + * cycles (two to six, depending on the model), so we try and + * prevent accidentally performing additional programming + * cycles. + * @dirty: Whether the mirror registers have been written to (overridden) + * since we've last read the fuses (either as part of the reset + * process or using a READFB instruction). There is a much larger, + * but still finite, limit on the number of SFP read cycles (around + * 300,000), so we try and minimize reads as well. + */ +struct ls2_sfp_priv { + void __iomem *base; + struct udevice *supply; + bool programmed, dirty; +}; + +static u32 ls2_sfp_readl(struct ls2_sfp_priv *priv, ulong off) +{ + u32 val = be32_to_cpu(readl(priv->base + off)); + + log_debug("%08x = readl(%p)\n", val, priv->base + off); + return val; +} + +static void ls2_sfp_writel(struct ls2_sfp_priv *priv, ulong val, ulong off) +{ + log_debug("writel(%08lx, %p)\n", val, priv->base + off); + writel(cpu_to_be32(val), priv->base + off); +} + +static bool ls2_sfp_validate(struct udevice *dev, int offset, int size) +{ + if (offset < 0 || size < 0) { + dev_notice(dev, "size and offset must be positive\n"); + return false; + } + + if (offset & 3 || size & 3) { + dev_notice(dev, "size and offset must be multiples of 4\n"); + return false; + } + + if (offset + size > SFP_SIZE) { + dev_notice(dev, "size + offset must be <= %#x\n", SFP_SIZE); + return false; + } + + return true; +} + +static int ls2_sfp_read(struct udevice *dev, int offset, void *buf_bytes, + int size) +{ + int i; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + u32 *buf = buf_bytes; + + if (!ls2_sfp_validate(dev, offset, size)) + return -EINVAL; + + for (i = 0; i < size; i += 4) + buf[i >> 2] = ls2_sfp_readl(priv, SFP_START + offset + i); + + return size; +} + +static int ls2_sfp_write(struct udevice *dev, int offset, + const void *buf_bytes, int size) +{ + int i; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + const u32 *buf = buf_bytes; + + if (!ls2_sfp_validate(dev, offset, size)) + return -EINVAL; + + for (i = 0; i < size; i += 4) + ls2_sfp_writel(priv, buf[i >> 2], SFP_START + offset + i); + + priv->dirty = true; + return size; +} + +static int ls2_sfp_check_secret(struct udevice *dev) +{ + struct ls2_sfp_priv *priv = dev_get_priv(dev); + u32 svhesr = ls2_sfp_readl(priv, SFP_SVHESR); + + if (svhesr) { + dev_warn(dev, "secret value hamming error not zero: %08x\n", + svhesr); + return -EIO; + } + return 0; +} + +static int ls2_sfp_transaction(struct ls2_sfp_priv *priv, ulong inst) +{ + u32 ingr; + + ls2_sfp_writel(priv, inst, SFP_INGR); + + do { + ingr = ls2_sfp_readl(priv, SFP_INGR); + } while (FIELD_GET(SFP_INGR_INST, ingr)); + + return FIELD_GET(SFP_INGR_ERR, ingr) ? -EIO : 0; +} + +static int ls2_sfp_ioctl(struct udevice *dev, unsigned long request, void *buf) +{ + int ret; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + + switch (request) { + case LS2_SFP_IOCTL_READ: + if (!priv->dirty) { + dev_dbg(dev, "ignoring read request, since fuses are not dirty\n"); + return 0; + } + + ret = ls2_sfp_transaction(priv, SFP_INGR_READFB); + if (ret) { + dev_err(dev, "error reading fuses\n"); + return ret; + } + + ls2_sfp_check_secret(dev); + priv->dirty = false; + return 0; + case LS2_SFP_IOCTL_PROG: + if (priv->programmed) { + dev_warn(dev, "fuses already programmed\n"); + return -EPERM; + } + + ret = ls2_sfp_check_secret(dev); + if (ret) + return ret; + + if (priv->supply) { + ret = regulator_set_enable(priv->supply, true); + if (ret) + return ret; + } + + ret = ls2_sfp_transaction(priv, SFP_INGR_PROGFB); + priv->programmed = true; + if (priv->supply) + regulator_set_enable(priv->supply, false); + + if (ret) + dev_err(dev, "error programming fuses\n"); + return ret; + default: + dev_dbg(dev, "unknown ioctl %lu\n", request); + return -EINVAL; + } +} + +static const struct misc_ops ls2_sfp_ops = { + .read = ls2_sfp_read, + .write = ls2_sfp_write, + .ioctl = ls2_sfp_ioctl, +}; + +static int ls2_sfp_probe(struct udevice *dev) +{ + int ret; + struct clk clk; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + ulong rate; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) { + dev_dbg(dev, "could not read register base\n"); + return -EINVAL; + } + + ret = device_get_supply_regulator(dev, "ta-sfp-prog", &priv->supply); + if (ret && ret != -ENODEV && ret != -ENOSYS) { + dev_dbg(dev, "problem getting supply (err %d)\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "sfp", &clk); + if (ret == -ENOSYS) { + rate = gd->bus_clk / 4; + } else if (ret) { + dev_dbg(dev, "could not get clock (err %d)\n", ret); + return ret; + } else { + ret = clk_enable(&clk); + if (ret) { + dev_dbg(dev, "could not enable clock (err %d)\n", ret); + return ret; + } + + rate = clk_get_rate(&clk); + clk_free(&clk); + if (!rate || IS_ERR_VALUE(rate)) { + ret = rate ? rate : -ENOENT; + dev_dbg(dev, "could not get clock rate (err %d)\n", + ret); + return ret; + } + } + + /* sfp clock in MHz * 12 */ + ls2_sfp_writel(priv, FIELD_PREP(SFP_SFPCR_PPW, rate * 12 / 1000000), + SFP_SFPCR); + + ls2_sfp_check_secret(dev); + return 0; +} + +static const struct udevice_id ls2_sfp_ids[] = { + { .compatible = "fsl,ls1021a-sfp" }, + { } +}; + +U_BOOT_DRIVER(ls2_sfp) = { + .name = "ls2_sfp", + .id = UCLASS_MISC, + .of_match = ls2_sfp_ids, + .probe = ls2_sfp_probe, + .ops = &ls2_sfp_ops, + .priv_auto = sizeof(struct ls2_sfp_priv), +}; + +static int ls2_sfp_device(struct udevice **dev) +{ + int ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(ls2_sfp), dev); + + if (ret) + log_debug("device not found (err %d)\n", ret); + return ret; +} + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_ioctl(dev, LS2_SFP_IOCTL_READ, NULL); + if (ret) + return ret; + + ret = misc_read(dev, word << 2, val, sizeof(*val)); + return ret < 0 ? ret : 0; +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_read(dev, word << 2, val, sizeof(*val)); + return ret < 0 ? ret : 0; +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_write(dev, word << 2, &val, sizeof(val)); + if (ret < 0) + return ret; + + return misc_ioctl(dev, LS2_SFP_IOCTL_PROG, NULL); +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_write(dev, word << 2, &val, sizeof(val)); + return ret < 0 ? ret : 0; +} diff --git a/drivers/misc/misc_sandbox.c b/drivers/misc/misc_sandbox.c index 0e4292fd0aa97e097852d6bf3e0bd8420c770b5e..31cde2dbac07eb0c55a400ca12e303712edc3dec 100644 --- a/drivers/misc/misc_sandbox.c +++ b/drivers/misc/misc_sandbox.c @@ -112,8 +112,11 @@ static const struct misc_ops misc_sandbox_ops = { int misc_sandbox_probe(struct udevice *dev) { struct misc_sandbox_priv *priv = dev_get_priv(dev); + /* For eth5 */ + const u8 mac[] = { 0x02, 0x00, 0x11, 0x22, 0x33, 0x46 }; priv->enabled = true; + memcpy(&priv->mem[16], mac, sizeof(mac)); return 0; } diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c new file mode 100644 index 0000000000000000000000000000000000000000..0244e4045703bf8ccd6983526daadfd93fed29ec --- /dev/null +++ b/drivers/misc/npcm_host_intf.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Host interface (LPC or eSPI) configuration on Nuvoton BMC + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SMC_CTL_REG_ADDR 0xc0001001 +#define SMC_CTL_HOSTWAIT 0x80 + +/* GCR Register Offsets */ +#define HIFCR 0x50 +#define MFSEL1 0x260 +#define MFSEL4 0x26c + +/* ESPI Register offsets */ +#define ESPICFG 0x4 +#define ESPIHINDP 0x80 + +/* MFSEL bit fileds */ +#define MFSEL1_LPCSEL BIT(26) +#define MFSEL4_ESPISEL BIT(8) + +/* ESPICFG bit fileds */ +#define CHSUPP_MASK GENMASK(27, 24) +#define IOMODE_MASK GENMASK(9, 8) +#define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3) +#define MAXFREQ_MASK GENMASK(12, 10) +#define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2) + +/* ESPIHINDP bit fileds */ +#define AUTO_SBLD BIT(4) +#define AUTO_HS1 BIT(8) +#define AUTO_HS2 BIT(12) +#define AUTO_HS3 BIT(16) + +static int npcm_host_intf_bind(struct udevice *dev) +{ + struct regmap *syscon; + void __iomem *base; + u32 ch_supp, val; + u32 ioaddr; + const char *type; + int ret; + + /* Release host wait */ + setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); + + syscon = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(syscon)) { + dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name); + return PTR_ERR(syscon); + } + + ioaddr = dev_read_u32_default(dev, "ioaddr", 0); + if (ioaddr) + regmap_write(syscon, HIFCR, ioaddr); + + type = dev_read_string(dev, "type"); + if (!type) + return -EINVAL; + + if (!strcmp(type, "espi")) { + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + ret = dev_read_u32(dev, "channel-support", &ch_supp); + if (ret) + return ret; + + /* Select eSPI pins function */ + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0); + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL); + + val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp; + writel(val, base + ESPIHINDP); + + val = readl(base + ESPICFG); + val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK); + val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp); + writel(val, base + ESPICFG); + } else if (!strcmp(type, "lpc")) { + /* Select LPC pin function */ + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0); + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL); + } + + return 0; +} + +static const struct udevice_id npcm_hostintf_ids[] = { + { .compatible = "nuvoton,npcm750-host-intf" }, + { .compatible = "nuvoton,npcm845-host-intf" }, + { } +}; + +U_BOOT_DRIVER(npcm_host_intf) = { + .name = "npcm_host_intf", + .id = UCLASS_MISC, + .of_match = npcm_hostintf_ids, + .bind = npcm_host_intf_bind, +}; diff --git a/drivers/misc/npcm_otp.c b/drivers/misc/npcm_otp.c new file mode 100644 index 0000000000000000000000000000000000000000..304910888bbc5a89ee0088ae841933c8651f1125 --- /dev/null +++ b/drivers/misc/npcm_otp.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct npcm_otp_priv { + struct npcm_otp_regs *regs[2]; +}; + +static struct npcm_otp_priv *otp_priv; + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_check_inputs */ +/* */ +/* Parameters: arr - fuse array number to check */ +/* word - fuse word (offset) to check */ +/* Returns: int */ +/* Side effects: */ +/* Description: Checks is arr and word are illegal and do not exceed */ +/* their range. Return 0 if they are legal, -1 if not */ +/*----------------------------------------------------------------------------*/ +static int npcm_otp_check_inputs(u32 arr, u32 word) +{ + if (arr >= NPCM_NUM_OF_SA) { + if (IS_ENABLED(CONFIG_ARCH_NPCM8XX)) + printf("\nError: npcm8XX otp includs only one bank: 0\n"); + if (IS_ENABLED(CONFIG_ARCH_NPCM7XX)) + printf("\nError: npcm7XX otp includs only two banks: 0 and 1\n"); + return -1; + } + + if (word >= NPCM_OTP_ARR_BYTE_SIZE) { + printf("\nError: npcm otp array comprises only %d bytes, numbered from 0 to %d\n", + NPCM_OTP_ARR_BYTE_SIZE, NPCM_OTP_ARR_BYTE_SIZE - 1); + return -1; + } + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_wait_for_otp_ready */ +/* */ +/* Parameters: array - fuse array to wait for */ +/* Returns: int */ +/* Side effects: */ +/* Description: Initialize the Fuse HW module. */ +/*----------------------------------------------------------------------------*/ +static int npcm_otp_wait_for_otp_ready(u32 arr, u32 timeout) +{ + struct npcm_otp_regs *regs = otp_priv->regs[arr]; + u32 time = timeout; + + /*------------------------------------------------------------------------*/ + /* check parameters validity */ + /*------------------------------------------------------------------------*/ + if (arr > NPCM_FUSE_SA) + return -EINVAL; + + while (--time > 1) { + if (readl(®s->fst) & FST_RDY) { + /* fuse is ready, clear the status. */ + writel(readl(®s->fst) | FST_RDST, ®s->fst); + return 0; + } + } + + /* try to clear the status in case it was set */ + writel(readl(®s->fst) | FST_RDST, ®s->fst); + + return -EINVAL; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_read_byte */ +/* */ +/* Parameters: arr - Storage Array type [input]. */ +/* addr - Byte-address to read from [input]. */ +/* data - Pointer to result [output]. */ +/* Returns: none */ +/* Side effects: */ +/* Description: Read 8-bit data from an OTP storage array. */ +/*----------------------------------------------------------------------------*/ +static void npcm_otp_read_byte(u32 arr, u32 addr, u8 *data) +{ + struct npcm_otp_regs *regs = otp_priv->regs[arr]; + + /* Wait for the Fuse Box Idle */ + npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF); + + /* Configure the byte address in the fuse array for read operation */ + writel(FADDR_VAL(addr, 0), ®s->faddr); + + /* Initiate a read cycle */ + writel(READ_INIT, ®s->fctl); + + /* Wait for read operation completion */ + npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF); + + /* Read the result */ + *data = readl(®s->fdata) & FDATA_MASK; + + /* Clean FDATA contents to prevent unauthorized software from reading + * sensitive information + */ + writel(FDATA_CLEAN_VALUE, ®s->fdata); +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_bit_is_programmed */ +/* */ +/* Parameters: arr - Storage Array type [input]. */ +/* byte_offset - Byte offset in array [input]. */ +/* bit_offset - Bit offset in byte [input]. */ +/* Returns: Nonzero if bit is programmed, zero otherwise. */ +/* Side effects: */ +/* Description: Check if a bit is programmed in an OTP storage array. */ +/*----------------------------------------------------------------------------*/ +static bool npcm_otp_bit_is_programmed(u32 arr, + u32 byte_offset, u8 bit_offset) +{ + u32 data = 0; + + /* Read the entire byte you wish to program */ + npcm_otp_read_byte(arr, byte_offset, (u8 *)&data); + + /* Check whether the bit is already programmed */ + if (data & (1 << bit_offset)) + return true; + + return false; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_program_bit */ +/* */ +/* Parameters: arr - Storage Array type [input]. */ +/* byte)offset - Byte offset in array [input]. */ +/* bit_offset - Bit offset in byte [input]. */ +/* Returns: int */ +/* Side effects: */ +/* Description: Program (set to 1) a bit in an OTP storage array. */ +/*----------------------------------------------------------------------------*/ +static int npcm_otp_program_bit(u32 arr, u32 byte_offset, + u8 bit_offset) +{ + struct npcm_otp_regs *regs = otp_priv->regs[arr]; + int count; + u8 read_data; + + /* Wait for the Fuse Box Idle */ + npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF); + + /* Make sure the bit is not already programmed */ + if (npcm_otp_bit_is_programmed(arr, byte_offset, bit_offset)) + return 0; + + /* Configure the bit address in the fuse array for program operation */ + writel(FADDR_VAL(byte_offset, bit_offset), ®s->faddr); + writel(readl(®s->faddr) | FADDR_IN_PROG, ®s->faddr); + + // program up to MAX_PROGRAM_PULSES + for (count = 1; count <= MAX_PROGRAM_PULSES; count++) { + /* Initiate a program cycle */ + writel(PROGRAM_ARM, ®s->fctl); + writel(PROGRAM_INIT, ®s->fctl); + + /* Wait for program operation completion */ + npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF); + + // after MIN_PROGRAM_PULSES start verifying the result + if (count >= MIN_PROGRAM_PULSES) { + /* Initiate a read cycle */ + writel(READ_INIT, ®s->fctl); + + /* Wait for read operation completion */ + npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF); + + /* Read the result */ + read_data = readl(®s->fdata) & FDATA_MASK; + + /* If the bit is set the sequence ended correctly */ + if (read_data & (1 << bit_offset)) + break; + } + } + + // check if programmking failed + if (count > MAX_PROGRAM_PULSES) { + printf("program fail\n"); + return -EINVAL; + } + + /* + * Clean FDATA contents to prevent unauthorized software from reading + * sensitive information + */ + writel(FDATA_CLEAN_VALUE, ®s->fdata); + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_program_byte */ +/* */ +/* Parameters: arr - Storage Array type [input]. */ +/* byte_offset - Byte offset in array [input]. */ +/* value - Byte to program [input]. */ +/* Returns: int */ +/* Side effects: */ +/* Description: Program (set to 1) a given byte's relevant bits in an */ +/* OTP storage array. */ +/*----------------------------------------------------------------------------*/ +static int npcm_otp_program_byte(u32 arr, u32 byte_offset, + u8 value) +{ + int status = 0; + unsigned int i; + u8 data = 0; + int rc; + + rc = npcm_otp_check_inputs(arr, byte_offset); + if (rc != 0) + return rc; + + /* Wait for the Fuse Box Idle */ + npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF); + + /* Read the entire byte you wish to program */ + npcm_otp_read_byte(arr, byte_offset, &data); + + /* In case all relevant bits are already programmed - nothing to do */ + if ((~data & value) == 0) + return status; + + /* Program unprogrammed bits. */ + for (i = 0; i < 8; i++) { + if (value & (1 << i)) { + /* Program (set to 1) the relevant bit */ + int last_status = npcm_otp_program_bit(arr, byte_offset, (u8)i); + + if (last_status != 0) + status = last_status; + } + } + return status; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_is_fuse_array_disabled */ +/* */ +/* Parameters: arr - Storage Array type [input]. */ +/* Returns: bool */ +/* Side effects: */ +/* Description: Return true if access to the first 2048 bits of the */ +/* specified fuse array is disabled, false if not */ +/*----------------------------------------------------------------------------*/ +bool npcm_otp_is_fuse_array_disabled(u32 arr) +{ + struct npcm_otp_regs *regs = otp_priv->regs[arr]; + + return (readl(®s->fcfg) & FCFG_FDIS) != 0; +} + +int npcm_otp_select_key(u8 key_index) +{ + struct npcm_otp_regs *regs = otp_priv->regs[NPCM_KEY_SA]; + u32 idx = 0; + u32 time = 0xDAEDBEEF; + + if (key_index >= 4) + return -1; + + /* Do not destroy ECCDIS bit */ + idx = readl(®s->fustrap_fkeyind); + + /* Configure the key size */ + idx &= ~FKEYIND_KSIZE_MASK; + idx |= FKEYIND_KSIZE_256; + + /* Configure the key index (0 to 3) */ + idx &= ~FKEYIND_KIND_MASK; + idx |= FKEYIND_KIND_KEY(key_index); + + writel(idx, ®s->fustrap_fkeyind); + + /* Wait for selection completetion */ + while (--time > 1) { + if (readl(®s->fustrap_fkeyind) & FKEYIND_KVAL) + return 0; + udelay(1); + } + + return -1; +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_nibble_parity_ecc_encode */ +/* */ +/* Parameters: datain - pointer to decoded data buffer */ +/* dataout - pointer to encoded data buffer (buffer size */ +/* should be 2 x dataout) */ +/* size - size of encoded data (decoded data x 2) */ +/* Returns: none */ +/* Side effects: */ +/* Description: Decodes the data according to nibble parity ECC scheme. */ +/* Size specifies the encoded data size. */ +/* Decodes whole bytes only */ +/*----------------------------------------------------------------------------*/ +void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size) +{ + u32 i, idx; + u8 E0, E1, E2, E3; + + for (i = 0; i < (size / 2); i++) { + E0 = (datain[i] >> 0) & 0x01; + E1 = (datain[i] >> 1) & 0x01; + E2 = (datain[i] >> 2) & 0x01; + E3 = (datain[i] >> 3) & 0x01; + + idx = i * 2; + dataout[idx] = datain[i] & 0x0f; + dataout[idx] |= (E0 ^ E1) << 4; + dataout[idx] |= (E2 ^ E3) << 5; + dataout[idx] |= (E0 ^ E2) << 6; + dataout[idx] |= (E1 ^ E3) << 7; + + E0 = (datain[i] >> 4) & 0x01; + E1 = (datain[i] >> 5) & 0x01; + E2 = (datain[i] >> 6) & 0x01; + E3 = (datain[i] >> 7) & 0x01; + + idx = i * 2 + 1; + dataout[idx] = (datain[i] & 0xf0) >> 4; + dataout[idx] |= (E0 ^ E1) << 4; + dataout[idx] |= (E2 ^ E3) << 5; + dataout[idx] |= (E0 ^ E2) << 6; + dataout[idx] |= (E1 ^ E3) << 7; + } +} + +/*----------------------------------------------------------------------------*/ +/* Function: npcm_otp_majority_rule_ecc_encode */ +/* */ +/* Parameters: datain - pointer to decoded data buffer */ +/* dataout - pointer to encoded data buffer (buffer size */ +/* should be 3 x dataout) */ +/* size - size of encoded data (decoded data x 3) */ +/* Returns: none */ +/* Side effects: */ +/* Description: Decodes the data according to Major Rule ECC scheme. */ +/* Size specifies the encoded data size. */ +/* Decodes whole bytes only */ +/*----------------------------------------------------------------------------*/ +void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size) +{ + u32 byte; + u32 bit; + u8 bit_val; + u32 decoded_size = size / 3; + + for (byte = 0; byte < decoded_size; byte++) { + for (bit = 0; bit < 8; bit++) { + bit_val = (datain[byte] >> bit) & 0x01; + + if (bit_val) { + dataout[byte] |= (1 << bit); + dataout[decoded_size + byte] |= (1 << bit); + dataout[decoded_size * 2 + byte] |= (1 << bit); + } else { + dataout[byte] &= ~(1 << bit); + dataout[decoded_size + byte] &= ~(1 << bit); + dataout[decoded_size * 2 + byte] &= ~(1 << bit); + } + } + } +} + +/*----------------------------------------------------------------------------*/ +/* Function: fuse_program_data */ +/* */ +/* Parameters: bank - Storage Array type [input]. */ +/* word - Byte offset in array [input]. */ +/* data - Pointer to data buffer to program. */ +/* size - Number of bytes to program. */ +/* Returns: none */ +/* Side effects: */ +/* Description: Programs the given byte array (size bytes) to the given */ +/* OTP storage array, starting from offset word. */ +/*----------------------------------------------------------------------------*/ +int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size) +{ + u32 arr = (u32)bank; + u32 byte; + int rc; + + rc = npcm_otp_check_inputs(bank, word + size - 1); + if (rc != 0) + return rc; + + for (byte = 0; byte < size; byte++) { + u8 val; + + val = data[byte]; + if (val == 0) // optimization + continue; + + rc = npcm_otp_program_byte(arr, word + byte, data[byte]); + if (rc != 0) + return rc; + + // verify programming of every '1' bit + val = 0; + npcm_otp_read_byte((u32)bank, byte, &val); + if ((data[byte] & ~val) != 0) + return -1; + } + + return 0; +} + +int fuse_prog_image(u32 bank, uintptr_t address) +{ + return fuse_program_data(bank, 0, (u8 *)address, NPCM_OTP_ARR_BYTE_SIZE); +} + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int rc = npcm_otp_check_inputs(bank, word); + + if (rc != 0) + return rc; + + *val = 0; + npcm_otp_read_byte((u32)bank, word, (u8 *)val); + + return 0; +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + /* We do not support overriding */ + return -EINVAL; +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int rc; + + rc = npcm_otp_check_inputs(bank, word); + if (rc != 0) + return rc; + + return npcm_otp_program_byte(bank, word, (u8)val); +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + /* We do not support overriding */ + return -EINVAL; +} + +static int npcm_otp_bind(struct udevice *dev) +{ + struct npcm_otp_regs *regs; + + otp_priv = calloc(1, sizeof(struct npcm_otp_priv)); + if (!otp_priv) + return -ENOMEM; + + regs = dev_remap_addr_index(dev, 0); + if (!regs) { + printf("Cannot find reg address (arr #0), binding failed\n"); + return -EINVAL; + } + otp_priv->regs[0] = regs; + + if (IS_ENABLED(CONFIG_ARCH_NPCM7xx)) { + regs = dev_remap_addr_index(dev, 1); + if (!regs) { + printf("Cannot find reg address (arr #1), binding failed\n"); + return -EINVAL; + } + otp_priv->regs[1] = regs; + } + printf("OTP: NPCM OTP module bind OK\n"); + + return 0; +} + +static const struct udevice_id npcm_otp_ids[] = { + { .compatible = "nuvoton,npcm845-otp" }, + { .compatible = "nuvoton,npcm750-otp" }, + { } +}; + +U_BOOT_DRIVER(npcm_otp) = { + .name = "npcm_otp", + .id = UCLASS_MISC, + .of_match = npcm_otp_ids, + .priv_auto = sizeof(struct npcm_otp_priv), + .bind = npcm_otp_bind, +}; diff --git a/drivers/misc/nvmem.c b/drivers/misc/nvmem.c new file mode 100644 index 0000000000000000000000000000000000000000..5a2bd1f9f72c8c2bf67b61eac55a33e207fc16ea --- /dev/null +++ b/drivers/misc/nvmem.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size) +{ + dev_dbg(cell->nvmem, "%s: off=%u size=%zu\n", __func__, cell->offset, size); + if (size != cell->size) + return -EINVAL; + + switch (cell->nvmem->driver->id) { + case UCLASS_I2C_EEPROM: + return i2c_eeprom_read(cell->nvmem, cell->offset, buf, size); + case UCLASS_MISC: { + int ret = misc_read(cell->nvmem, cell->offset, buf, size); + + if (ret < 0) + return ret; + if (ret != size) + return -EIO; + return 0; + } + case UCLASS_RTC: + return dm_rtc_read(cell->nvmem, cell->offset, buf, size); + default: + return -ENOSYS; + } +} + +int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, size_t size) +{ + dev_dbg(cell->nvmem, "%s: off=%u size=%zu\n", __func__, cell->offset, size); + if (size != cell->size) + return -EINVAL; + + switch (cell->nvmem->driver->id) { + case UCLASS_I2C_EEPROM: + return i2c_eeprom_write(cell->nvmem, cell->offset, buf, size); + case UCLASS_MISC: { + int ret = misc_write(cell->nvmem, cell->offset, buf, size); + + if (ret < 0) + return ret; + if (ret != size) + return -EIO; + return 0; + } + case UCLASS_RTC: + return dm_rtc_write(cell->nvmem, cell->offset, buf, size); + default: + return -ENOSYS; + } +} + +/** + * nvmem_get_device() - Get an nvmem device for a cell + * @node: ofnode of the nvmem device + * @cell: Cell to look up + * + * Try to find a nvmem-compatible device by going through the nvmem interfaces. + * + * Return: + * * 0 on success + * * -ENODEV if we didn't find anything + * * A negative error if there was a problem looking up the device + */ +static int nvmem_get_device(ofnode node, struct nvmem_cell *cell) +{ + int i, ret; + enum uclass_id ids[] = { + UCLASS_I2C_EEPROM, + UCLASS_MISC, + UCLASS_RTC, + }; + + for (i = 0; i < ARRAY_SIZE(ids); i++) { + ret = uclass_get_device_by_ofnode(ids[i], node, &cell->nvmem); + if (!ret) + return 0; + if (ret != -ENODEV && ret != -EPFNOSUPPORT) + return ret; + } + + return -ENODEV; +} + +int nvmem_cell_get_by_index(struct udevice *dev, int index, + struct nvmem_cell *cell) +{ + fdt_addr_t offset; + fdt_size_t size = FDT_SIZE_T_NONE; + int ret; + struct ofnode_phandle_args args; + + dev_dbg(dev, "%s: index=%d\n", __func__, index); + + ret = dev_read_phandle_with_args(dev, "nvmem-cells", NULL, 0, index, + &args); + if (ret) + return ret; + + ret = nvmem_get_device(ofnode_get_parent(args.node), cell); + if (ret) + return ret; + + offset = ofnode_get_addr_size_index_notrans(args.node, 0, &size); + if (offset == FDT_ADDR_T_NONE || size == FDT_SIZE_T_NONE) { + dev_dbg(cell->nvmem, "missing address or size for %s\n", + ofnode_get_name(args.node)); + return -EINVAL; + } + + cell->offset = offset; + cell->size = size; + return 0; +} + +int nvmem_cell_get_by_name(struct udevice *dev, const char *name, + struct nvmem_cell *cell) +{ + int index; + + dev_dbg(dev, "%s, name=%s\n", __func__, name); + + index = dev_read_stringlist_search(dev, "nvmem-cell-names", name); + if (index < 0) + return index; + + return nvmem_cell_get_by_index(dev, index, cell); +} diff --git a/drivers/misc/qfw_sandbox.c b/drivers/misc/qfw_sandbox.c index b09974d33bd6e65d3afe37b40a535eef039634ff..1002df75339e13d6400bf2d7ba7a76f37c1c9c71 100644 --- a/drivers/misc/qfw_sandbox.c +++ b/drivers/misc/qfw_sandbox.c @@ -48,7 +48,7 @@ static void qfw_sandbox_read_entry_dma(struct udevice *dev, struct qfw_dma *dma) { u16 entry; u32 control = be32_to_cpu(dma->control); - void *address = (void *)be64_to_cpu(dma->address); + void *address = (void *)(uintptr_t)be64_to_cpu(dma->address); u32 length = be32_to_cpu(dma->length); struct qfw_sandbox_plat *plat = dev_get_plat(dev); struct fw_cfg_file *file; diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index f14d6e26d9c88ffd1b8e7ef9aec63f330616cb20..b816503bfa27c2212834e047b90b3cad790faf2f 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -39,6 +39,11 @@ struct stm32_rcc_clk stm32_rcc_clk_mp1 = { .soc = STM32MP1, }; +struct stm32_rcc_clk stm32_rcc_clk_mp13 = { + .drv_name = "stm32mp13_clk", + .soc = STM32MP1, +}; + static int stm32_rcc_bind(struct udevice *dev) { struct udevice *child; @@ -79,6 +84,7 @@ static const struct udevice_id stm32_rcc_ids[] = { {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 }, {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 }, {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 }, + {.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 }, { } }; diff --git a/drivers/misc/test_drv.c b/drivers/misc/test_drv.c index 5d72982f258ada9a50d48ddede86c5914a763f48..927618256f0ac88d73cf6e1955a8412a7101a2d0 100644 --- a/drivers/misc/test_drv.c +++ b/drivers/misc/test_drv.c @@ -108,8 +108,10 @@ UCLASS_DRIVER(testbus) = { .child_pre_probe = testbus_child_pre_probe_uclass, .child_post_probe = testbus_child_post_probe_uclass, - /* This is for dtoc testing only */ - .per_device_plat_auto = sizeof(struct dm_test_uclass_priv), + .per_device_auto = sizeof(struct dm_test_uclass_priv), + + /* Note: this is for dtoc testing as well as tags*/ + .per_device_plat_auto = sizeof(struct dm_test_uclass_plat), }; static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5e2921ce41a7169ed7193fe5484f849aae3fe384..6ff00a7cbd34a69d159ecdbe109c2bfd7c4eb90e 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -123,6 +123,7 @@ config MMC_IO_VOLTAGE config SPL_MMC_IO_VOLTAGE bool "Support IO voltage configuration in SPL" + depends on SPL_MMC help IO voltage configuration allows selecting the voltage level of the IO lines (not the level of main supply). This is required for UHS @@ -153,6 +154,7 @@ config MMC_HS400_ES_SUPPORT config SPL_MMC_HS400_ES_SUPPORT bool "enable HS400 Enhanced Strobe support in SPL" + depends on SPL_MMC help The HS400 Enhanced Strobe mode is support by some eMMC. The bus frequency is up to 200MHz. This mode does not tune the IO. @@ -166,6 +168,7 @@ config MMC_HS400_SUPPORT config SPL_MMC_HS400_SUPPORT bool "enable HS400 support in SPL" + depends on SPL_MMC select SPL_MMC_HS200_SUPPORT help The HS400 mode is support by some eMMC. The bus frequency is up to @@ -179,6 +182,7 @@ config MMC_HS200_SUPPORT config SPL_MMC_HS200_SUPPORT bool "enable HS200 support in SPL" + depends on SPL_MMC help The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -342,14 +346,6 @@ config MVEBU_MMC If unsure, say N. -config PXA_MMC_GENERIC - bool "Support for MMC controllers on PXA" - help - This selects MMC controllers on PXA. - If you are on a PXA architecture, say Y here. - - If unsure, say N. - config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR @@ -478,17 +474,31 @@ config MMC_SDHCI_ADMA config SPL_MMC_SDHCI_ADMA bool "Support SDHCI ADMA2 in SPL" - depends on MMC_SDHCI + depends on SPL_MMC && MMC_SDHCI select MMC_SDHCI_ADMA_HELPERS help This enables support for the ADMA (Advanced DMA) defined in the SD Host Controller Standard Specification Version 3.00 in SPL. +config FIXED_SDHCI_ALIGNED_BUFFER + hex "SDRAM address for fixed buffer" + depends on SPL && MVEBU_SPL_BOOT_DEVICE_MMC + default 0x00180000 + help + On the Marvell Armada 38x when the SPL runs it located in internal + SRAM which is the L2 cache locked to memory. When the MMC buffers + are located on the stack (or bss), the SDIO controller (SDHCI) can't + write into this L2 cache memory. + + This specifies the address of a fixed buffer located in SDRAM that + will be used for all SDHCI transfers in the SPL. + config MMC_SDHCI_ASPEED bool "Aspeed SDHCI controller" depends on ARCH_ASPEED depends on DM_MMC depends on MMC_SDHCI + select MISC help Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed SoCs. This device is compatible with SD 3.0 and/or MMC 4.3 @@ -826,6 +836,15 @@ config FSL_ESDHC_VS33_NOT_SUPPORT For eSDHC, power supply is through peripheral circuit. 3.3V support is common. Select this if 3.3V power supply not supported. +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH + int + depends on FSL_ESDHC + default 1 + +config ESDHC_DETECT_QUIRK + bool "QIXIS-based eSDHC quirk detection" + depends on FSL_ESDHC && FSL_QIXIS + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 9627509302295b493481178b87e4e472bb36d57e..7c4243289c4d2572ceffc9e4eb635bacd16074a4 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -46,7 +46,6 @@ obj-$(CONFIG_MMC_MXS) += mxsmmc.o obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o obj-$(CONFIG_MMC_OWL) += owl_mmc.o obj-$(CONFIG_MMC_PCI) += pci_mmc.o -obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 4305967d78457a59dde10b11ce0e06e52aec1aa4..42a61343645ab55b0160de8830efd814d53f17da 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -670,6 +670,10 @@ static const struct udevice_id am654_sdhci_ids[] = { .compatible = "ti,am64-sdhci-4bit", .data = (ulong)&sdhci_am64_4bit_drvdata, }, + { + .compatible = "ti,am62-sdhci", + .data = (ulong)&sdhci_am64_4bit_drvdata, + }, { } }; diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c index 45373157198790fc06224bd1794b031a344bcf51..9d79bf58cc70ba474a3f873c8efb38713443711f 100644 --- a/drivers/mmc/aspeed_sdhci.c +++ b/drivers/mmc/aspeed_sdhci.c @@ -10,6 +10,7 @@ #include #include #include +#include struct aspeed_sdhci_plat { struct mmc_config cfg; @@ -26,12 +27,16 @@ static int aspeed_sdhci_probe(struct udevice *dev) int ret; ret = clk_get_by_index(dev, 0, &clk); - if (ret) + if (ret) { + debug("%s: clock get failed %d\n", __func__, ret); return ret; + } ret = clk_enable(&clk); - if (ret) + if (ret) { + debug("%s: clock enable failed %d\n", __func__, ret); goto free; + } host->name = dev->name; host->ioaddr = dev_read_addr_ptr(dev); @@ -39,6 +44,7 @@ static int aspeed_sdhci_probe(struct udevice *dev) max_clk = clk_get_rate(&clk); if (IS_ERR_VALUE(max_clk)) { ret = max_clk; + debug("%s: clock rate get failed %d\n", __func__, ret); goto err; } @@ -89,3 +95,38 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = { .priv_auto = sizeof(struct sdhci_host), .plat_auto = sizeof(struct aspeed_sdhci_plat), }; + + +static int aspeed_sdc_probe(struct udevice *parent) +{ + struct clk clk; + int ret; + + ret = clk_get_by_index(parent, 0, &clk); + if (ret) { + debug("%s: clock get failed %d\n", __func__, ret); + return ret; + } + + ret = clk_enable(&clk); + if (ret) { + debug("%s: clock enable failed %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static const struct udevice_id aspeed_sdc_ids[] = { + { .compatible = "aspeed,ast2400-sd-controller" }, + { .compatible = "aspeed,ast2500-sd-controller" }, + { .compatible = "aspeed,ast2600-sd-controller" }, + { } +}; + +U_BOOT_DRIVER(aspeed_sdc_drv) = { + .name = "aspeed_sdc", + .id = UCLASS_MISC, + .of_match = aspeed_sdc_ids, + .probe = aspeed_sdc_probe, +}; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index fdf2cc290e068622df745d308daedf3c2bec5928..b49a7b425b9a01c64d37cd8747b5c68c05585727 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -30,6 +30,7 @@ #include #include #include +#include "../../board/freescale/common/qixis.h" DECLARE_GLOBAL_DATA_PTR; @@ -773,7 +774,7 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) struct fsl_esdhc *regs = priv->esdhc_regs; #ifdef CONFIG_ESDHC_DETECT_QUIRK - if (CONFIG_ESDHC_DETECT_QUIRK) + if (qixis_esdhc_detect_quirk()) return 1; #endif if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS) @@ -946,9 +947,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg) } else if (cfg->max_bus_width == 1) { mmc_cfg->host_caps |= MMC_MODE_1BIT; } else { - mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | - MMC_MODE_8BIT; - printf("No max bus width provided. Assume 8-bit supported.\n"); + mmc_cfg->host_caps |= MMC_MODE_1BIT; + printf("No max bus width provided. Fallback to 1-bit mode.\n"); } if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK)) @@ -972,6 +972,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH; /* Prefer peripheral clock which provides higher frequency. */ if (gd->arch.sdhc_per_clk) cfg->sdhc_clk = gd->arch.sdhc_per_clk; diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c deleted file mode 100644 index 2b45549a143645557b5e0e7194738601c96b1532..0000000000000000000000000000000000000000 --- a/drivers/mmc/pxa_mmc_gen.c +++ /dev/null @@ -1,536 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Marek Vasut - * - * Modified to add driver model (DM) support - * Copyright (C) 2019 Marcel Ziswiler - * - * Loosely based on the old code and Linux's PXA MMC driver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* PXAMMC Generic default config for various CPUs */ -#if defined(CONFIG_CPU_PXA25X) -#define PXAMMC_FIFO_SIZE 1 -#define PXAMMC_MIN_SPEED 312500 -#define PXAMMC_MAX_SPEED 20000000 -#define PXAMMC_HOST_CAPS (0) -#elif defined(CONFIG_CPU_PXA27X) -#define PXAMMC_CRC_SKIP -#define PXAMMC_FIFO_SIZE 32 -#define PXAMMC_MIN_SPEED 304000 -#define PXAMMC_MAX_SPEED 19500000 -#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT) -#elif defined(CONFIG_CPU_MONAHANS) -#define PXAMMC_FIFO_SIZE 32 -#define PXAMMC_MIN_SPEED 304000 -#define PXAMMC_MAX_SPEED 26000000 -#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS) -#else -#error "This CPU isn't supported by PXA MMC!" -#endif - -#define MMC_STAT_ERRORS \ - (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \ - MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \ - MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR) - -/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */ -#define PXA_MMC_TIMEOUT 100 - -struct pxa_mmc_priv { - struct pxa_mmc_regs *regs; -}; - -/* Wait for bit to be set */ -static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - unsigned int timeout = PXA_MMC_TIMEOUT; - - /* Wait for bit to be set */ - while (--timeout) { - if (readl(®s->stat) & mask) - break; - udelay(10); - } - - if (!timeout) - return -ETIMEDOUT; - - return 0; -} - -static int pxa_mmc_stop_clock(struct mmc *mmc) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - unsigned int timeout = PXA_MMC_TIMEOUT; - - /* If the clock aren't running, exit */ - if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) - return 0; - - /* Tell the controller to turn off the clock */ - writel(MMC_STRPCL_STOP_CLK, ®s->strpcl); - - /* Wait until the clock are off */ - while (--timeout) { - if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) - break; - udelay(10); - } - - /* The clock refused to stop, scream and die a painful death */ - if (!timeout) - return -ETIMEDOUT; - - /* The clock stopped correctly */ - return 0; -} - -static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - uint32_t cmdat) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - int ret; - - /* The card can send a "busy" response */ - if (cmd->resp_type & MMC_RSP_BUSY) - cmdat |= MMC_CMDAT_BUSY; - - /* Inform the controller about response type */ - switch (cmd->resp_type) { - case MMC_RSP_R1: - case MMC_RSP_R1b: - cmdat |= MMC_CMDAT_R1; - break; - case MMC_RSP_R2: - cmdat |= MMC_CMDAT_R2; - break; - case MMC_RSP_R3: - cmdat |= MMC_CMDAT_R3; - break; - default: - break; - } - - /* Load command and it's arguments into the controller */ - writel(cmd->cmdidx, ®s->cmd); - writel(cmd->cmdarg >> 16, ®s->argh); - writel(cmd->cmdarg & 0xffff, ®s->argl); - writel(cmdat, ®s->cmdat); - - /* Start the controller clock and wait until they are started */ - writel(MMC_STRPCL_START_CLK, ®s->strpcl); - - ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN); - if (ret) - return ret; - - /* Correct and happy end */ - return 0; -} - -static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - u32 a, b, c; - int i; - int stat; - - /* Read the controller status */ - stat = readl(®s->stat); - - /* - * Linux says: - * Did I mention this is Sick. We always need to - * discard the upper 8 bits of the first 16-bit word. - */ - a = readl(®s->res) & 0xffff; - for (i = 0; i < 4; i++) { - b = readl(®s->res) & 0xffff; - c = readl(®s->res) & 0xffff; - cmd->response[i] = (a << 24) | (b << 8) | (c >> 8); - a = c; - } - - /* The command response didn't arrive */ - if (stat & MMC_STAT_TIME_OUT_RESPONSE) { - return -ETIMEDOUT; - } else if (stat & MMC_STAT_RES_CRC_ERROR && - cmd->resp_type & MMC_RSP_CRC) { -#ifdef PXAMMC_CRC_SKIP - if (cmd->resp_type & MMC_RSP_136 && - cmd->response[0] & (1 << 31)) - printf("Ignoring CRC, this may be dangerous!\n"); - else -#endif - return -EILSEQ; - } - - /* The command response was successfully read */ - return 0; -} - -static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - u32 len; - u32 *buf = (uint32_t *)data->dest; - int size; - int ret; - - len = data->blocks * data->blocksize; - - while (len) { - /* The controller has data ready */ - if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) { - size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); - len -= size; - size /= 4; - - /* Read data into the buffer */ - while (size--) - *buf++ = readl(®s->rxfifo); - } - - if (readl(®s->stat) & MMC_STAT_ERRORS) - return -EIO; - } - - /* Wait for the transmission-done interrupt */ - ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); - if (ret) - return ret; - - return 0; -} - -static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - u32 len; - u32 *buf = (uint32_t *)data->src; - int size; - int ret; - - len = data->blocks * data->blocksize; - - while (len) { - /* The controller is ready to receive data */ - if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) { - size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); - len -= size; - size /= 4; - - while (size--) - writel(*buf++, ®s->txfifo); - - if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32) - writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf); - } - - if (readl(®s->stat) & MMC_STAT_ERRORS) - return -EIO; - } - - /* Wait for the transmission-done interrupt */ - ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); - if (ret) - return ret; - - /* Wait until the data are really written to the card */ - ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE); - if (ret) - return ret; - - return 0; -} - -static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data) -{ - struct pxa_mmc_regs *regs = priv->regs; - u32 cmdat = 0; - int ret; - - /* Stop the controller */ - ret = pxa_mmc_stop_clock(mmc); - if (ret) - return ret; - - /* If we're doing data transfer, configure the controller accordingly */ - if (data) { - writel(data->blocks, ®s->nob); - writel(data->blocksize, ®s->blklen); - /* This delay can be optimized, but stick with max value */ - writel(0xffff, ®s->rdto); - cmdat |= MMC_CMDAT_DATA_EN; - if (data->flags & MMC_DATA_WRITE) - cmdat |= MMC_CMDAT_WRITE; - } - - /* Run in 4bit mode if the card can do it */ - if (mmc->bus_width == 4) - cmdat |= MMC_CMDAT_SD_4DAT; - - /* Execute the command */ - ret = pxa_mmc_start_cmd(mmc, cmd, cmdat); - if (ret) - return ret; - - /* Wait until the command completes */ - ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES); - if (ret) - return ret; - - /* Read back the result */ - ret = pxa_mmc_cmd_done(mmc, cmd); - if (ret) - return ret; - - /* In case there was a data transfer scheduled, do it */ - if (data) { - if (data->flags & MMC_DATA_WRITE) - pxa_mmc_do_write_xfer(mmc, data); - else - pxa_mmc_do_read_xfer(mmc, data); - } - - return 0; -} - -static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc) -{ - struct pxa_mmc_regs *regs = priv->regs; - u32 tmp; - u32 pxa_mmc_clock; - - if (!mmc->clock) { - pxa_mmc_stop_clock(mmc); - return 0; - } - - /* PXA3xx can do 26MHz with special settings. */ - if (mmc->clock == 26000000) { - writel(0x7, ®s->clkrt); - return 0; - } - - /* Set clock to the card the usual way. */ - pxa_mmc_clock = 0; - tmp = mmc->cfg->f_max / mmc->clock; - tmp += tmp % 2; - - while (tmp > 1) { - pxa_mmc_clock++; - tmp >>= 1; - } - - writel(pxa_mmc_clock, ®s->clkrt); - - return 0; -} - -static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc) -{ - struct pxa_mmc_regs *regs = priv->regs; - - /* Make sure the clock are stopped */ - pxa_mmc_stop_clock(mmc); - - /* Turn off SPI mode */ - writel(0, ®s->spi); - - /* Set up maximum timeout to wait for command response */ - writel(MMC_RES_TO_MAX_MASK, ®s->resto); - - /* Mask all interrupts */ - writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ), - ®s->i_mask); - - return 0; -} - -#if !CONFIG_IS_ENABLED(DM_MMC) -static int pxa_mmc_init(struct mmc *mmc) -{ - struct pxa_mmc_priv *priv = mmc->priv; - - return pxa_mmc_init_common(priv, mmc); -} - -static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct pxa_mmc_priv *priv = mmc->priv; - - return pxa_mmc_send_cmd_common(priv, mmc, cmd, data); -} - -static int pxa_mmc_set_ios(struct mmc *mmc) -{ - struct pxa_mmc_priv *priv = mmc->priv; - - return pxa_mmc_set_ios_common(priv, mmc); -} - -static const struct mmc_ops pxa_mmc_ops = { - .send_cmd = pxa_mmc_request, - .set_ios = pxa_mmc_set_ios, - .init = pxa_mmc_init, -}; - -static struct mmc_config pxa_mmc_cfg = { - .name = "PXA MMC", - .ops = &pxa_mmc_ops, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .f_max = PXAMMC_MAX_SPEED, - .f_min = PXAMMC_MIN_SPEED, - .host_caps = PXAMMC_HOST_CAPS, - .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; - -int pxa_mmc_register(int card_index) -{ - struct mmc *mmc; - struct pxa_mmc_priv *priv; - u32 reg; - int ret = -ENOMEM; - - priv = malloc(sizeof(struct pxa_mmc_priv)); - if (!priv) - goto err0; - - memset(priv, 0, sizeof(*priv)); - - switch (card_index) { - case 0: - priv->regs = (struct pxa_mmc_regs *)MMC0_BASE; - break; - case 1: - priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; - break; - default: - ret = -EINVAL; - printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", - card_index); - goto err1; - } - -#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ - reg = readl(CKEN); - reg |= CKEN12_MMC; - writel(reg, CKEN); -#else /* PXA3xx */ - reg = readl(CKENA); - reg |= CKENA_12_MMC0 | CKENA_13_MMC1; - writel(reg, CKENA); -#endif - - mmc = mmc_create(&pxa_mmc_cfg, priv); - if (!mmc) - goto err1; - - return 0; - -err1: - free(priv); -err0: - return ret; -} -#else /* !CONFIG_IS_ENABLED(DM_MMC) */ -static int pxa_mmc_probe(struct udevice *dev) -{ - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct pxa_mmc_plat *plat = dev_get_plat(dev); - struct mmc_config *cfg = &plat->cfg; - struct mmc *mmc = &plat->mmc; - struct pxa_mmc_priv *priv = dev_get_priv(dev); - u32 reg; - - upriv->mmc = mmc; - - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - cfg->f_max = PXAMMC_MAX_SPEED; - cfg->f_min = PXAMMC_MIN_SPEED; - cfg->host_caps = PXAMMC_HOST_CAPS; - cfg->name = dev->name; - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - - mmc->priv = priv; - - priv->regs = plat->base; - -#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ - reg = readl(CKEN); - reg |= CKEN12_MMC; - writel(reg, CKEN); -#else /* PXA3xx */ - reg = readl(CKENA); - reg |= CKENA_12_MMC0 | CKENA_13_MMC1; - writel(reg, CKENA); -#endif - - return pxa_mmc_init_common(priv, mmc); -} - -static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct pxa_mmc_plat *plat = dev_get_plat(dev); - struct pxa_mmc_priv *priv = dev_get_priv(dev); - - return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data); -} - -static int pxa_mmc_set_ios(struct udevice *dev) -{ - struct pxa_mmc_plat *plat = dev_get_plat(dev); - struct pxa_mmc_priv *priv = dev_get_priv(dev); - - return pxa_mmc_set_ios_common(priv, &plat->mmc); -} - -static const struct dm_mmc_ops pxa_mmc_ops = { - .get_cd = NULL, - .send_cmd = pxa_mmc_send_cmd, - .set_ios = pxa_mmc_set_ios, -}; - -#if CONFIG_IS_ENABLED(BLK) -static int pxa_mmc_bind(struct udevice *dev) -{ - struct pxa_mmc_plat *plat = dev_get_plat(dev); - - return mmc_bind(dev, &plat->mmc, &plat->cfg); -} -#endif - -U_BOOT_DRIVER(pxa_mmc) = { -#if CONFIG_IS_ENABLED(BLK) - .bind = pxa_mmc_bind, -#endif - .id = UCLASS_MMC, - .name = "pxa_mmc", - .ops = &pxa_mmc_ops, - .priv_auto = sizeof(struct pxa_mmc_priv), - .probe = pxa_mmc_probe, -}; -#endif /* !CONFIG_IS_ENABLED(DM_MMC) */ diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 44bfc911af23e6637f9c0ecb58610de46973d6db..81b07609a912ca890c026d75be856d0c317ca3da 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -514,10 +514,12 @@ retry_cmd: */ static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv) { - /* Reset */ - reset_assert(&priv->reset_ctl); - udelay(2); - reset_deassert(&priv->reset_ctl); + if (reset_valid(&priv->reset_ctl)) { + /* Reset */ + reset_assert(&priv->reset_ctl); + udelay(2); + reset_deassert(&priv->reset_ctl); + } /* init the needed SDMMC register after reset */ writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER); @@ -735,7 +737,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) ret = reset_get_by_index(dev, 0, &priv->reset_ctl); if (ret) - goto clk_disable; + dev_dbg(dev, "No reset provided\n"); gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); @@ -755,8 +757,6 @@ static int stm32_sdmmc2_probe(struct udevice *dev) stm32_sdmmc2_reset(priv); return 0; -clk_disable: - clk_disable(&priv->clk); clk_free: clk_free(&priv->clk); diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 4088267dd111d5bf453746984131c0529673a5f9..3d1f6e43fd526a0e56343470f7105fdd433b33d8 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -48,6 +48,35 @@ config FLASH_CFI_DRIVER option. Visit for more information on CFI. +choice + prompt "Data-width of the flash device" + depends on FLASH_CFI_DRIVER + default SYS_FLASH_CFI_WIDTH_8BIT + +config SYS_FLASH_CFI_WIDTH_8BIT + bool "Data-width of the device is 8-bit" + +config SYS_FLASH_CFI_WIDTH_16BIT + bool "Data-width of the device is 16-bit" + +config SYS_FLASH_CFI_WIDTH_32BIT + bool "Data-width of the device is 32-bit" + +config SYS_FLASH_CFI_WIDTH_64BIT + bool "Data-width of the device is 64-bit" + +endchoice + +config SYS_FLASH_CFI_WIDTH + hex + depends on FLASH_CFI_DRIVER + default 0x1 if SYS_FLASH_CFI_WIDTH_8BIT + default 0x2 if SYS_FLASH_CFI_WIDTH_16BIT + default 0x4 if SYS_FLASH_CFI_WIDTH_32BIT + default 0x8 if SYS_FLASH_CFI_WIDTH_64BIT + help + This must be kept in sync with the table in include/flash.h + config CFI_FLASH bool "Enable Driver Model for CFI Flash driver" depends on DM_MTD @@ -67,6 +96,10 @@ config CFI_FLASH_USE_WEAK_ACCESSORS Enable this option to allow for the flash_{read,write}{8,16,32,64} functions to be overridden by the platform. +config SYS_CFI_FLASH_STATUS_POLL + bool "Poll status on AMD flash chips" + depends on FLASH_CFI_DRIVER + config SYS_FLASH_USE_BUFFER_WRITE bool "Enable buffered writes to flash" depends on FLASH_CFI_DRIVER @@ -135,6 +168,9 @@ config STM32_FLASH This is the driver of embedded flash for some STMicroelectronics STM32 MCU. +config SAMSUNG_ONENAND + bool "Samsung OneNAND driver support" + config USE_SYS_MAX_FLASH_BANKS bool "Enable Max number of Flash memory banks" help diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index aae3ea0d1b45451f5249e083f3a9b30ed9e2b4a6..495041070650f70a5f0cbc5f5356698e87a55b93 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -68,13 +68,6 @@ static uint flash_verbose = 1; flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ -/* - * Check if chip width is defined. If not, start detecting with 8bit. - */ -#ifndef CONFIG_SYS_FLASH_CFI_WIDTH -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#endif - #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define __maybe_weak __weak #else diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index d077897e4a757b847bd65e2b38fc1a43a93fb76e..56aa58b58bb7f62d9d166e6bf81342d8cc300839 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -902,7 +902,8 @@ int add_mtd_partitions_of(struct mtd_info *master) ofnode_for_each_subnode(child, parts) { struct mtd_partition part = { 0 }; struct mtd_info *slave; - fdt_addr_t offset, size; + fdt_addr_t offset; + fdt_size_t size; if (!ofnode_is_available(child)) continue; diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d75f371c951ff0f6ef0f5fd2ff6827ff87d21ac7..190300fc17902b6ffd893cb1ec2d86f58a88c224 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -23,6 +23,9 @@ config TPL_SYS_NAND_SELF_INIT This option, if enabled, provides more flexible and linux-like NAND initialization process, in SPL. +config TPL_NAND_INIT + bool + config SYS_NAND_DRIVER_ECC_LAYOUT bool "Omit standard ECC layouts to save space" help @@ -70,6 +73,7 @@ config PMECC_SECTOR_SIZE config SPL_GENERATE_ATMEL_PMECC_HEADER bool "Atmel PMECC Header Generation" + depends on SPL select ATMEL_NAND_HWECC select ATMEL_NAND_HW_PMECC help @@ -165,6 +169,7 @@ config NAND_FSL_ELBC_DT config NAND_FSL_IFC bool "Support Freescale Integrated Flash Controller NAND driver" select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT + select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK select SPL_SYS_NAND_SELF_INIT select SYS_NAND_SELF_INIT select FSL_IFC @@ -643,7 +648,7 @@ config SYS_NAND_U_BOOT_OFFS_REDUND config SPL_NAND_AM33XX_BCH bool "Enables SPL-NAND driver which supports ELM based" - depends on NAND_OMAP_GPMC && !OMAP34XX + depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX default y help Hardware ECC correction. This is useful for platforms which have ELM @@ -654,6 +659,7 @@ config SPL_NAND_AM33XX_BCH config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" + depends on SPL_NAND_SUPPORT help This is a small implementation of the Denali NAND controller for use on SPL. @@ -669,7 +675,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES config SPL_NAND_SIMPLE bool "Use simple SPL NAND driver" - depends on !SPL_NAND_AM33XX_BCH + depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT help Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 6ec3581d20e919704621432d76e4f5c5a2936ee0..e3f6b903f75f9ec52730bc80bd55c26c4e536f6d 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o -obj-$(CONFIG_SPL_NAND_INIT) += nand.o +obj-$(CONFIG_TPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o endif diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index e734139b5ea595e0024113bb587d1079b86bc72a..48a3687f27282420193037cef6446867d5ee36b0 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -668,7 +668,7 @@ static void fsl_elbc_ctrl_init(void) elbc_ctrl->addr = NULL; } -static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) +static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) { struct mtd_info *mtd; struct nand_chip *nand; @@ -716,7 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) elbc_ctrl->chips[priv->bank] = priv; /* fill in nand_chip structure */ - nand->flash_node = flash_node; + mtd->dev = dev; + nand->flash_node = dev ? dev_ofnode(dev) : ofnode_null(); /* set up function call table */ nand->read_byte = fsl_elbc_read_byte; @@ -744,7 +745,11 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) return ret; /* If nand_scan_ident() has not selected ecc.mode, do it now */ - if (nand->ecc.mode == NAND_ECC_NONE) { + if (nand->ecc.mode == 0 +#if CONFIG_IS_ENABLED(OF_CONTROL) + && !ofnode_read_string(nand->flash_node, "nand-ecc-mode") +#endif + ) { /* If CS Base Register selects full hardware ECC then use it */ if ((br & BR_DECC) == BR_DECC_CHK_GEN) { nand->ecc.mode = NAND_ECC_HW; @@ -827,14 +832,14 @@ void board_nand_init(void) int i; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null()); + fsl_elbc_chip_init(i, (u8 *)base_address[i], NULL); } #else static int fsl_elbc_nand_probe(struct udevice *dev) { - return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev)); + return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev); } static const struct udevice_id fsl_elbc_nand_dt_ids[] = { diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index b7e37416a49b8d0c27ed10be5773f476eba219c6..4d11922a65038c7e03c5a5796f95e7549a00c6d8 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -297,7 +297,7 @@ void nand_boot(void) uboot(); } -#ifndef CONFIG_SPL_NAND_INIT +#ifndef CONFIG_TPL_NAND_INIT void nand_init(void) { } diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index 5d197ce0c51c1cadefa27ba5b764df10ef9ee4df..a92c6252a5dc6f68c91482d59e8a31e31b665979 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2010 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. * * (C) Copyright 2012 - * Amit Virdi, ST Microelectronics, amit.virdi@st.com. + * Amit Virdi, STMicroelectronics, amit.virdi@st.com. */ #include diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6f81257cf1f5313e05f649904b798674446fba2f..e8ece0a4a0dd59d370428fc3f14305ec098de1ad 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -974,6 +974,22 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) return ret; } +static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip) +{ + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) + return 0; + + u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { + chip->onfi_timing_mode_default, + }; + + return chip->onfi_set_features(mtd, chip, + ONFI_FEATURE_ADDR_TIMING_MODE, + tmode_param); +} + /** * nand_setup_data_interface - Setup the best data interface and timings * @chip: The NAND chip @@ -999,17 +1015,9 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) * Ensure the timing mode has been changed on the chip side * before changing timings on the controller side. */ - if (chip->onfi_version) { - u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { - chip->onfi_timing_mode_default, - }; - - ret = chip->onfi_set_features(mtd, chip, - ONFI_FEATURE_ADDR_TIMING_MODE, - tmode_param); - if (ret) - goto err; - } + ret = nand_onfi_set_timings(mtd, chip); + if (ret) + goto err; ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); err: diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index f350c7e5dc218f3584b56ebbd55f2190d3265f4a..f83876c57613f04ad7ce96fa2f8aebef7bd3569c 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -248,7 +248,7 @@ config SPI_FLASH_MTD config SPL_SPI_FLASH_MTD bool "SPI flash MTD support for SPL" - depends on SPI_FLASH + depends on SPI_FLASH && SPL help Enable the MTD support for the SPI flash layer in SPL. diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7050ddc397162c5bd624259eef04572082be27e3..67278c40e35b770a076858dbfc670db8bc563446 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = { /* EON -- en25xxx */ { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif @@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, @@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, @@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_4B_OPCODES) }, { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, @@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ @@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -275,12 +296,13 @@ const struct flash_info spi_nor_ids[] = { { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) }, { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - /* ST Microelectronics -- newer production may have feature updates */ + /* STMicroelectronics -- newer production may have feature updates */ { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, @@ -311,11 +333,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, { INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -362,6 +392,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 84d859c21eb8c2cd1781064d80ec31b77e017e99..b671e72580e2ba3f9087ea733495e53fdd550bc4 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -239,6 +239,10 @@ config E1000 +config E1000_NO_NVM + bool "Intel PRO/1000 has no NVMEM / EEPROM" + depends on E1000 + config E1000_SPI_GENERIC bool "Allow access to the Intel 8257x SPI bus" depends on E1000 @@ -308,6 +312,7 @@ config ETH_DESIGNWARE_MESON8B config ETH_DESIGNWARE_SOCFPGA select REGMAP select SYSCON + select DW_ALTDESCRIPTOR bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" depends on DM_ETH && ETH_DESIGNWARE help @@ -322,6 +327,10 @@ config ETH_DESIGNWARE_S700 This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. +config DW_ALTDESCRIPTOR + bool "Designware Ethernet MAC uses alternate (enhanced) descriptors" + depends on ETH_DESIGNWARE + config ETHOC bool "OpenCores 10/100 Mbps Ethernet MAC" help @@ -391,19 +400,27 @@ config FTGMAC100 offers high-priority transmit queue for QoS and CoS applications. +config SYS_DISCOVER_PHY + bool config MCFFEC bool "ColdFire Ethernet Support" depends on DM_ETH select PHYLIB + select SYS_DISCOVER_PHY help This driver supports the network interface units in the ColdFire family. +config SYS_UNIFY_CACHE + depends on MCFFEC + bool "Invalidate icache during ethernet operations" + config FSLDMAFEC bool "ColdFire DMA Ethernet Support" depends on DM_ETH select PHYLIB + select SYS_DISCOVER_PHY help This driver supports the network interface units in the ColdFire family. @@ -719,6 +736,7 @@ config MPC8XX_FEC bool "Fast Ethernet Controller on MPC8XX" depends on MPC8xx select MII + select SYS_DISCOVER_PHY help This driver implements support for the Fast Ethernet Controller on MPC8XX diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 1584b9eac173b1ba6ca0c41b93b90bb46fd7974f..0e63f70934c0c9eac0ece55ed18be285b0835e61 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ /* diff --git a/drivers/net/designware.h b/drivers/net/designware.h index a82afb99cabd7d956065edce4d67ab7fc92a5d2a..3793d550980e673dc122b1e211a7cd70d5f32097 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #ifndef _DW_ETH_H @@ -85,10 +85,8 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) -/* Default DMA Burst length */ -#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 -#endif +/* DMA Burst length */ +#define GMAC_DEFAULT_DMA_PBL 8 /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) @@ -96,7 +94,7 @@ struct eth_dma_regs { #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) +#define DMA_PBL (GMAC_DEFAULT_DMA_PBL << 8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index e103f79305e788e2effc5fe29e7bc2eb77e262b1..6825f9e27c06b830a3c139ed5a50ddbd1506aee2 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -243,16 +243,8 @@ static int fec_init(struct udevice *dev) fecpin_setclear(info, 1); fec_halt(dev); -#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CONFIG_SYS_DISCOVER_PHY) - mii_init(); set_fec_duplex_speed(fecp, info->dup_spd); -#else -#ifndef CONFIG_SYS_DISCOVER_PHY - set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ -#endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ fecp->eimr = 0; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index cef9eecac2145f0cdc9975032d658ae0d48ba635..4dd848932b961ce61cc4fda742d96febffc70556 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -278,17 +278,9 @@ int mcffec_init(struct udevice *dev) fecpin_setclear(info, 1); fec_reset(info); -#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CONFIG_SYS_DISCOVER_PHY) - mii_init(); set_fec_duplex_speed(fecp, info->dup_spd); -#else -#ifndef CONFIG_SYS_DISCOVER_PHY - set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ -#endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ fecp->eimr = 0; diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 37459dfa0a409bb6a66ab06fef76d687f5c27681..13022addb6a3e18720981fc9d9772f294a6ddd48 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -395,9 +395,11 @@ static void sb_eth_stop(struct udevice *dev) static int sb_eth_write_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); + struct eth_sandbox_priv *priv = dev_get_priv(dev); debug("eth_sandbox %s: Write HW ADDR - %pM\n", dev->name, pdata->enetaddr); + memcpy(priv->fake_host_hwaddr, pdata->enetaddr, ARP_HLEN); return 0; } @@ -419,16 +421,8 @@ static int sb_eth_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct eth_sandbox_priv *priv = dev_get_priv(dev); - const u8 *mac; pdata->iobase = dev_read_addr(dev); - - mac = dev_read_u8_array_ptr(dev, "fake-host-hwaddr", ARP_HLEN); - if (!mac) { - printf("'fake-host-hwaddr' is missing from the DT\n"); - return -EINVAL; - } - memcpy(priv->fake_host_hwaddr, mac, ARP_HLEN); priv->disabled = false; priv->tx_handler = sb_default_handler; diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index db324c17d67992b549210e66e10bd62acd57a6ac..f2ba34474598f562e24916c97c6a9fd6f4bbace2 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -66,155 +66,7 @@ struct smc91111_priv{ #define SMC_IO_EXTENT 16 -#ifdef CONFIG_CPU_PXA25X - -#ifdef CONFIG_XSENGINE -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) -#define SMC_inb(a,p) ({ \ - unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ - unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ - if (__p & 2) __v >>= 8; \ - else __v &= 0xff; \ - __v; }) -#else -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) -#define SMC_inb(a,p) ({ \ - unsigned int __p = (unsigned int)((a)->iobase + (p)); \ - unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ - if (__p & 1) __v >>= 8; \ - else __v &= 0xff; \ - __v; }) -#endif - -#ifdef CONFIG_XSENGINE -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) -#else -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) -#endif - -#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((a),(r)&~1); \ - __w &= ((r)&1) ? 0x00FF : 0xFF00; \ - __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw((a),__w,(r)&~1); \ - }) - -#define SMC_outsl(a,r,b,l) ({ int __i; \ - dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ - SMC_outl((a), *(__b2 + __i), r); \ - } \ - }) - -#define SMC_outsw(a,r,b,l) ({ int __i; \ - word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ - SMC_outw((a), *(__b2 + __i), r); \ - } \ - }) - -#define SMC_insl(a,r,b,l) ({ int __i ; \ - dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl((a),(r)); \ - SMC_inl((a),0); \ - }; \ - }) - -#define SMC_insw(a,r,b,l) ({ int __i ; \ - word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw((a),(r)); \ - SMC_inw((a),0); \ - }; \ - }) - -#define SMC_insb(a,r,b,l) ({ int __i ; \ - byte *__b2; \ - __b2 = (byte *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb((a),(r)); \ - SMC_inb((a),0); \ - }; \ - }) - -#elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ - -#define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) - -#define SMC_LEON_SWAP32(_x_) \ - ({ dword _x = (_x_); \ - ((_x << 24) | \ - ((0x0000FF00UL & _x) << 8) | \ - ((0x00FF0000UL & _x) >> 8) | \ - (_x >> 24)); }) - -#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) -#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) -#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) -#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) -#define SMC_inb(a,p) ({ \ - word ___v = SMC_inw((a),(p) & ~1); \ - if ((p) & 1) ___v >>= 8; \ - else ___v &= 0xff; \ - ___v; }) - -#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) -#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) -#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) -#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) -#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ - word __w = SMC_inw((a),(r)&~1); \ - __w &= ((r)&1) ? 0x00FF : 0xFF00; \ - __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw((a),__w,(r)&~1); \ - }while(0) -#define SMC_outsl(a,r,b,l) do{ int __i; \ - dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ - SMC_outl_nosw((a), *(__b2 + __i), r); \ - } \ - }while(0) -#define SMC_outsw(a,r,b,l) do{ int __i; \ - word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ - SMC_outw_nosw((a), *(__b2 + __i), r); \ - } \ - }while(0) -#define SMC_insl(a,r,b,l) do{ int __i ; \ - dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ - }; \ - }while(0) - -#define SMC_insw(a,r,b,l) do{ int __i ; \ - word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ - }; \ - }while(0) - -#define SMC_insb(a,r,b,l) do{ int __i ; \ - byte *__b2; \ - __b2 = (byte *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb((a),(r)); \ - }; \ - }while(0) -#elif defined(CONFIG_MS7206SE) +#if defined(CONFIG_MS7206SE) #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) @@ -244,7 +96,7 @@ struct smc91111_priv{ __b2++; \ } \ } while (0) -#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ +#else #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ /* diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index a4715735c3c442c8418ce9cc1e612b43f705a1bf..04277b1269f3357fdaed3691742c97cbb6f4ed89 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -19,6 +19,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -295,6 +296,9 @@ static int axiemac_phy_init(struct udevice *dev) /* Set default MDIO divisor */ writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc); + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + priv->phyaddr = eth_phy_get_addr(dev); + if (priv->phyaddr == -1) { /* Detect the PHY address */ for (i = 31; i >= 0; i--) { @@ -778,18 +782,29 @@ static int axi_emac_probe(struct udevice *dev) priv->phy_of_handle = plat->phy_of_handle; priv->interface = pdata->phy_interface; - priv->bus = mdio_alloc(); - priv->bus->read = axiemac_miiphy_read; - priv->bus->write = axiemac_miiphy_write; - priv->bus->priv = priv; + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + priv->bus = eth_phy_get_mdio_bus(dev); - ret = mdio_register_seq(priv->bus, dev_seq(dev)); - if (ret) - return ret; + if (!priv->bus) { + priv->bus = mdio_alloc(); + priv->bus->read = axiemac_miiphy_read; + priv->bus->write = axiemac_miiphy_write; + priv->bus->priv = priv; + + ret = mdio_register_seq(priv->bus, dev_seq(dev)); + if (ret) + return ret; + } + + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + eth_phy_set_mdio_bus(dev, priv->bus); axiemac_phy_init(dev); } + printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, + priv->phyaddr, phy_string_for_interface(pdata->phy_interface)); + return 0; } @@ -844,8 +859,10 @@ static int axi_emac_of_to_plat(struct udevice *dev) offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); if (offset > 0) { - plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, - "reg", -1); + if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) + plat->phyaddr = fdtdec_get_int(gd->fdt_blob, + offset, + "reg", -1); plat->phy_of_handle = offset; } @@ -857,9 +874,6 @@ static int axi_emac_of_to_plat(struct udevice *dev) "xlnx,eth-hasnobuf"); } - printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, - plat->phyaddr, phy_string_for_interface(pdata->phy_interface)); - return 0; } diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 43fc36dc6a82b34a22c2d3e635b90a75ae76d5ed..6c9f1f7c2728922108949176f698726608144c24 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -564,14 +565,27 @@ static int emaclite_probe(struct udevice *dev) struct xemaclite *emaclite = dev_get_priv(dev); int ret; - emaclite->bus = mdio_alloc(); - emaclite->bus->read = emaclite_miiphy_read; - emaclite->bus->write = emaclite_miiphy_write; - emaclite->bus->priv = emaclite; + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + emaclite->bus = eth_phy_get_mdio_bus(dev); - ret = mdio_register_seq(emaclite->bus, dev_seq(dev)); - if (ret) - return ret; + if (!emaclite->bus) { + emaclite->bus = mdio_alloc(); + emaclite->bus->read = emaclite_miiphy_read; + emaclite->bus->write = emaclite_miiphy_write; + emaclite->bus->priv = emaclite; + + ret = mdio_register_seq(emaclite->bus, dev_seq(dev)); + if (ret) + return ret; + } + + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) { + eth_phy_set_mdio_bus(dev, emaclite->bus); + emaclite->phyaddr = eth_phy_get_addr(dev); + } + + printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, + emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); return 0; } @@ -606,20 +620,19 @@ static int emaclite_of_to_plat(struct udevice *dev) emaclite->phyaddr = -1; - offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), - "phy-handle"); - if (offset > 0) - emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, - "reg", -1); + if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) { + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), + "phy-handle"); + if (offset > 0) + emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, + offset, "reg", -1); + } emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "xlnx,tx-ping-pong", 0); emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "xlnx,rx-ping-pong", 0); - printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, - emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); - return 0; } diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index fd2203420c3bee86faaee18a62fc3c90c3cc7643..436acca898e496a42d965dd803e143982ee7fcf3 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -48,6 +48,10 @@ config PCI_REGION_MULTI_ENTRY region type. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on the PCI bus. +config PCI_CONFIG_HOST_BRIDGE + bool "Configure PCI host bridges" + default y if X86 + config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" depends on MIPS @@ -81,6 +85,10 @@ config PCI_ARID support on PCI devices. This helps to skip some devices in BDF scan that are not present. +config PCI_SCAN_SHOW + bool "Show PCI devices during startup" + depends on PCIE_IMX + config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" help @@ -97,6 +105,10 @@ config PCIE_ECAM_SYNQUACER Note that this must be configured when boot because Linux driver expects the PCIe RC has been configured in the bootloader. +config PCI_GT64120 + bool "GT64120 PCI support" + depends on MIPS + config PCI_PHYTIUM bool "Phytium PCIe support" help @@ -121,8 +133,12 @@ config PCIE_DW_SIFIVE Say Y here if you want to enable PCIe controller support on FU740. +config SYS_FSL_PCI_VER_3_X + bool + config PCIE_FSL bool "FSL PowerPC PCIe support" + select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240 help Say Y here if you want to enable PCIe controller support on FSL PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. @@ -134,6 +150,10 @@ config PCI_MPC85XX Say Y here if you want to enable PCI controller support on FSL PowerPC MPC85xx SoC. +config PCI_MSC01 + bool "MSC01 PCI support" + depends on TARGET_MALTA + config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" depends on RCAR_32 @@ -159,6 +179,12 @@ config PCI_SANDBOX the device tree but the normal PCI scan technique is used to find then. +config SH7751_PCI + bool "SH7751 PCI controller support" + depends on SH + help + SuperH PCI Bridge Configuration + config PCI_TEGRA bool "Tegra PCI support" depends on ARCH_TEGRA @@ -254,6 +280,10 @@ config FSL_PCIE_EP_COMPAT This compatible is used to find pci controller ep node in Kernel DT to complete fixup. +config PCIE_IMX + bool "i.MX PCIe support" + depends on ARCH_MX6 + config PCIE_INTEL_FPGA bool "Intel FPGA PCIe support" help diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 04f623652f09557e8c8f9d0d3bc1a1a39b511b25..cfcd6fd6c52f8df2026ec3c943f9bcce10cf11ee 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o -obj-$(CONFIG_SH4_PCI) += pci_sh4.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 970ee1adf1ba406a30e4c5fa7e15e59b8e6d2c10..2c85e78a13652c6f2a7b8f804c530f31c24d4bd5 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -954,7 +954,7 @@ int pci_bind_bus_devices(struct udevice *bus) return 0; } -static void decode_regions(struct pci_controller *hose, ofnode parent_node, +static int decode_regions(struct pci_controller *hose, ofnode parent_node, ofnode node) { int pci_addr_cells, addr_cells, size_cells; @@ -968,7 +968,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, prop = ofnode_get_property(node, "ranges", &len); if (!prop) { debug("%s: Cannot decode regions\n", __func__); - return; + return -EINVAL; } pci_addr_cells = ofnode_read_simple_addr_cells(node); @@ -986,6 +986,8 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS; hose->regions = (struct pci_region *) calloc(1, max_regions * sizeof(struct pci_region)); + if (!hose->regions) + return -ENOMEM; for (i = 0; i < max_regions; i++, len -= cells_per_record) { u64 pci_addr, addr, size; @@ -1053,7 +1055,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, /* Add a region for our local memory */ bd = gd->bd; if (!bd) - return; + return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { @@ -1068,7 +1070,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, } } - return; + return 0; } static int pci_uclass_pre_probe(struct udevice *bus) @@ -1097,7 +1099,10 @@ static int pci_uclass_pre_probe(struct udevice *bus) /* For bridges, use the top-level PCI controller */ if (!device_is_on_pci_bus(bus)) { hose->ctlr = bus; - decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus)); + ret = decode_regions(hose, dev_ofnode(bus->parent), + dev_ofnode(bus)); + if (ret) + return ret; } else { struct pci_controller *parent_hose; diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c deleted file mode 100644 index aac9be055e2cb1db40ba2c5a73f997adae358af3..0000000000000000000000000000000000000000 --- a/drivers/pci/pci_sh4.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SH4 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu - * (C) 2008 Yusuke Goda - * - * u-boot/arch/sh/cpu/sh4/pci-sh4.c - */ - -#include -#include - -#include -#include -#include -#include - -int pci_sh4_init(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->region_count = 0; - hose->last_busno = 0xff; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - hose->region_count++; - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - hose->region_count++; - -#if defined(CONFIG_PCI_SYS_BUS) - /* PCI System Memory space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_SYS_BUS, - CONFIG_PCI_SYS_PHYS, - CONFIG_PCI_SYS_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - hose->region_count++; -#endif - - udelay(1000); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci_sh4_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci_sh4_write_config_dword); - - pci_register_hose(hose); - - udelay(1000); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - hose->last_busno = pci_hose_scan(hose); - return 0; -} - -int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) -{ - return 0; -} - -#ifdef CONFIG_PCI_SCAN_SHOW -int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) -{ - return 1; -} -#endif /* CONFIG_PCI_SCAN_SHOW */ diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c01d9e09b901190ec400b039a5722831a022db7c..4a3856d3c2f51bcc3b4678c6d290bf1ad635391c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -274,6 +274,13 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config PHY_NPCM_USB + bool "Nuvoton NPCM USB PHY support" + depends on PHY + depends on ARCH_NPCM + help + Support the USB PHY in NPCM SoCs + config PHY_IMX8MQ_USB bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bf9b40932fe3af62cc1f87b9cf6570f0d4b2438f..d95439c4257b7cb41abf4c55078444477ed28699 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c new file mode 100644 index 0000000000000000000000000000000000000000..24eba6655435c763808f5271d92c9dc0d3983155 --- /dev/null +++ b/drivers/phy/phy-npcm-usb.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR Register Offsets */ +#define GCR_INTCR3 0x9C +#define GCR_USB1PHYCTL 0x140 +#define GCR_USB2PHYCTL 0x144 +#define GCR_USB3PHYCTL 0x148 + +/* USBnPHYCTL bit fields */ +#define PHYCTL_RS BIT(28) + +#define USBPHY2SW GENMASK(13, 12) +#define USBPHY3SW GENMASK(15, 14) + +#define USBPHY2SW_DEV9_PHY1 FIELD_PREP(USBPHY2SW, 0) +#define USBPHY2SW_HOST1 FIELD_PREP(USBPHY2SW, 1) +#define USBPHY2SW_DEV9_PHY2 FIELD_PREP(USBPHY2SW, 3) +#define USBPHY3SW_DEV8_PHY1 FIELD_PREP(USBPHY3SW, 0) +#define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1) +#define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3) + +enum controller_id { + UDC0_7, + UDC8, + UDC9, + USBH1, + USBH2, +}; + +enum phy_id { + PHY1 = 1, + PHY2, + PHY3, +}; + +/* Phy Switch Settings */ +#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */ +#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */ +#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */ +#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */ +#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */ +#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */ +#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */ + +struct npcm_usbphy { + struct regmap *syscon; + u8 id; + u16 phy_switch; /* (phy_id << 8) | controller_id */ +}; + +static int npcm_usb_phy_init(struct phy *phy) +{ + struct npcm_usbphy *priv = dev_get_priv(phy->dev); + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(phy->dev, 0, &reset); + if (ret && ret != -ENOENT && ret != -ENOTSUPP) { + dev_err(phy->dev, "can't get phy reset ctrl (err %d)", ret); + return ret; + } + + /* setup PHY switch */ + switch (priv->phy_switch) { + case USBD8PHY1: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_DEV8_PHY1); + break; + case USBD8PHY3: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_DEV8_PHY3); + break; + case USBD9PHY1: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_DEV9_PHY1); + break; + case USBD9PHY2: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_DEV9_PHY2); + break; + case USBH1PHY2: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_HOST1); + break; + case USBH2PHY3: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_HOST2); + break; + default: + break; + } + /* reset phy */ + if (reset_valid(&reset)) + reset_assert(&reset); + + /* Wait for PHY clocks to stablize for 50us or more */ + udelay(100); + + /* release phy from reset */ + if (reset_valid(&reset)) + reset_deassert(&reset); + + /* PHY RS bit should be set after reset */ + switch (priv->id) { + case PHY1: + regmap_update_bits(priv->syscon, GCR_USB1PHYCTL, PHYCTL_RS, PHYCTL_RS); + break; + case PHY2: + regmap_update_bits(priv->syscon, GCR_USB2PHYCTL, PHYCTL_RS, PHYCTL_RS); + break; + case PHY3: + regmap_update_bits(priv->syscon, GCR_USB3PHYCTL, PHYCTL_RS, PHYCTL_RS); + break; + default: + break; + } + + return 0; +} + +static int npcm_usb_phy_exit(struct phy *phy) +{ + struct npcm_usbphy *priv = dev_get_priv(phy->dev); + + /* set PHY switch to default state */ + switch (priv->phy_switch) { + case USBD8PHY1: + case USBD8PHY3: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_HOST2); + break; + case USBD9PHY1: + case USBD9PHY2: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_HOST1); + break; + default: + break; + } + return 0; +} + +static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +{ + struct npcm_usbphy *priv = dev_get_priv(phy->dev); + u16 phy_switch; + + if (args->args_count < 1 || args->args[0] > USBH2) + return -EINVAL; + + phy_switch = (priv->id << 8) | args->args[0]; + switch (phy_switch) { + case USBD9PHY1: + case USBH2PHY3: + case USBD8PHY3: + if (!IS_ENABLED(CONFIG_ARCH_NPCM8XX)) + return -EINVAL; + case USBDPHY1: + case USBD8PHY1: + case USBD9PHY2: + case USBH1PHY2: + priv->phy_switch = phy_switch; + return 0; + default: + return -EINVAL; + } +} + +static int npcm_usb_phy_probe(struct udevice *dev) +{ + struct npcm_usbphy *priv = dev_get_priv(dev); + + priv->syscon = syscon_regmap_lookup_by_phandle(dev->parent, "syscon"); + if (IS_ERR(priv->syscon)) { + dev_err(dev, "%s: unable to get syscon\n", __func__); + return PTR_ERR(priv->syscon); + } + priv->id = dev_read_u32_default(dev, "reg", -1); + + return 0; +} + +static const struct udevice_id npcm_phy_ids[] = { + { .compatible = "nuvoton,npcm845-usb-phy",}, + { .compatible = "nuvoton,npcm750-usb-phy",}, + { } +}; + +static struct phy_ops npcm_phy_ops = { + .init = npcm_usb_phy_init, + .exit = npcm_usb_phy_exit, + .of_xlate = npcm_usb_phy_xlate, +}; + +U_BOOT_DRIVER(npcm_phy) = { + .name = "npcm-usb-phy", + .id = UCLASS_PHY, + .of_match = npcm_phy_ids, + .ops = &npcm_phy_ops, + .probe = npcm_usb_phy_probe, + .priv_auto = sizeof(struct npcm_usbphy), +}; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 563d96d4f5d5c77b68da5a566efd9f5116341e7c..b6ef2acced2d9b7bd95cd418209975f4944f4294 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -272,7 +272,7 @@ config PINCTRL_STI depends on DM && ARCH_STI default y help - Support pin multiplexing control on STMicrolectronics STi SoCs. + Support pin multiplexing control on STMicroelectronics STi SoCs. The driver is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available @@ -353,6 +353,7 @@ source "drivers/pinctrl/mscc/Kconfig" source "drivers/pinctrl/mtmips/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nexell/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9b4978253b943796dc1064771c8a413231a2a0c8..3b167d099fcae23915eeb8aec22c2a3cb52dc1b5 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ +obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..07f65f7637f97b341f25fb41655a414dadfb47fb --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on DM && PINCTRL_GENERIC && ARCH_NPCM7xx + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..886d00784cef589caad2e79d44c8a8277af8cb04 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index 0000000000000000000000000000000000000000..f6e20415e2eabd8c4ad18d515638db73d2e3222a --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,1607 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Nuvoton Technology Corp. + * Author: Joseph Liu + * Author: Tomer Maimon + */ + +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_INTCR2 0x60 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_RESSR 0x6C +#define NPCM7XX_GCR_FLOCKR1 0x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* reset registers */ +#define NPCM7XX_RST_WD0RCR 0x38 +#define NPCM7XX_RST_WD1RCR 0x3C +#define NPCM7XX_RST_WD2RCR 0x40 +#define NPCM7XX_RST_SWRSTC1 0x44 +#define NPCM7XX_RST_SWRSTC2 0x48 +#define NPCM7XX_RST_SWRSTC3 0x4C +#define NPCM7XX_RST_SWRSTC4 0x50 +#define NPCM7XX_RST_CORSTC 0x5C + +#define PORST BIT(31) +#define CORST BIT(30) +#define WD0RST BIT(29) +#define WD1RST BIT(24) +#define WD2RST BIT(23) + +#define GPIOX_MODULE_RESET 16 +#define CA9C_RESET BIT(0) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK1 0x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE 0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP 0x18 +#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD 0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */ +#define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */ +#define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */ +#define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */ +#define NPCM7XX_GP_N_TLOCK2 0x7c + +#define NPCM7XX_GPIO_BANK_OFFSET 0x1000 +#define NPCM7XX_GPIO_PER_BITS 32 +#define NPCM7XX_GPIO_PER_BANK 32 +#define NPCM7XX_GPIO_BANK_NUM 8 +#define NPCM7XX_GCR_NONE 0 + +/* pinmux handing in the pinctrl driver*/ +static const int smb0_pins[] = { 115, 114 }; +static const int smb0b_pins[] = { 195, 194 }; +static const int smb0c_pins[] = { 202, 196 }; +static const int smb0d_pins[] = { 198, 199 }; +static const int smb0den_pins[] = { 197 }; + +static const int smb1_pins[] = { 117, 116 }; +static const int smb1b_pins[] = { 126, 127 }; +static const int smb1c_pins[] = { 124, 125 }; +static const int smb1d_pins[] = { 4, 5 }; + +static const int smb2_pins[] = { 119, 118 }; +static const int smb2b_pins[] = { 122, 123 }; +static const int smb2c_pins[] = { 120, 121 }; +static const int smb2d_pins[] = { 6, 7 }; + +static const int smb3_pins[] = { 30, 31 }; +static const int smb3b_pins[] = { 39, 40 }; +static const int smb3c_pins[] = { 37, 38 }; +static const int smb3d_pins[] = { 59, 60 }; + +static const int smb4_pins[] = { 28, 29 }; +static const int smb4b_pins[] = { 18, 19 }; +static const int smb4c_pins[] = { 20, 21 }; +static const int smb4d_pins[] = { 22, 23 }; +static const int smb4den_pins[] = { 17 }; + +static const int smb5_pins[] = { 26, 27 }; +static const int smb5b_pins[] = { 13, 12 }; +static const int smb5c_pins[] = { 15, 14 }; +static const int smb5d_pins[] = { 94, 93 }; +static const int ga20kbc_pins[] = { 94, 93 }; + +static const int smb6_pins[] = { 172, 171 }; +static const int smb7_pins[] = { 174, 173 }; +static const int smb8_pins[] = { 129, 128 }; +static const int smb9_pins[] = { 131, 130 }; +static const int smb10_pins[] = { 133, 132 }; +static const int smb11_pins[] = { 135, 134 }; +static const int smb12_pins[] = { 221, 220 }; +static const int smb13_pins[] = { 223, 222 }; +static const int smb14_pins[] = { 22, 23 }; +static const int smb15_pins[] = { 20, 21 }; + +static const int fanin0_pins[] = { 64 }; +static const int fanin1_pins[] = { 65 }; +static const int fanin2_pins[] = { 66 }; +static const int fanin3_pins[] = { 67 }; +static const int fanin4_pins[] = { 68 }; +static const int fanin5_pins[] = { 69 }; +static const int fanin6_pins[] = { 70 }; +static const int fanin7_pins[] = { 71 }; +static const int fanin8_pins[] = { 72 }; +static const int fanin9_pins[] = { 73 }; +static const int fanin10_pins[] = { 74 }; +static const int fanin11_pins[] = { 75 }; +static const int fanin12_pins[] = { 76 }; +static const int fanin13_pins[] = { 77 }; +static const int fanin14_pins[] = { 78 }; +static const int fanin15_pins[] = { 79 }; +static const int faninx_pins[] = { 175, 176, 177, 203 }; + +static const int pwm0_pins[] = { 80 }; +static const int pwm1_pins[] = { 81 }; +static const int pwm2_pins[] = { 82 }; +static const int pwm3_pins[] = { 83 }; +static const int pwm4_pins[] = { 144 }; +static const int pwm5_pins[] = { 145 }; +static const int pwm6_pins[] = { 146 }; +static const int pwm7_pins[] = { 147 }; + +static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; +static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; + +/* RGMII 1 pin group */ +static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, + 106, 107 }; +/* RGMII 1 MD interface pin group */ +static const int rg1mdio_pins[] = { 108, 109 }; + +/* RGMII 2 pin group */ +static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, + 213, 214, 215 }; +/* RGMII 2 MD interface pin group */ +static const int rg2mdio_pins[] = { 216, 217 }; + +static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, + 213, 214, 215, 216, 217 }; +/* Serial I/O Expander 1 */ +static const int iox1_pins[] = { 0, 1, 2, 3 }; +/* Serial I/O Expander 2 */ +static const int iox2_pins[] = { 4, 5, 6, 7 }; +/* Host Serial I/O Expander 2 */ +static const int ioxh_pins[] = { 10, 11, 24, 25 }; + +static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 }; +static const int mmcwp_pins[] = { 153 }; +static const int mmccd_pins[] = { 155 }; +static const int mmcrst_pins[] = { 155 }; +static const int mmc8_pins[] = { 148, 149, 150, 151 }; + +/* RMII 1 pin groups */ +static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 }; +static const int r1err_pins[] = { 56 }; +static const int r1md_pins[] = { 57, 58 }; + +/* RMII 2 pin groups */ +static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 }; +static const int r2err_pins[] = { 90 }; +static const int r2md_pins[] = { 91, 92 }; + +static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 }; +static const int sd1pwr_pins[] = { 143 }; + +static const int wdog1_pins[] = { 218 }; +static const int wdog2_pins[] = { 219 }; + +/* BMC serial port 0 */ +static const int bmcuart0a_pins[] = { 41, 42 }; +static const int bmcuart0b_pins[] = { 48, 49 }; + +static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; + +/* System Control Interrupt and Power Management Event pin group */ +static const int scipme_pins[] = { 169 }; +/* System Management Interrupt pin group */ +static const int sci_pins[] = { 170 }; +/* Serial Interrupt Line pin group */ +static const int serirq_pins[] = { 162 }; + +static const int clkout_pins[] = { 160 }; +static const int clkreq_pins[] = { 231 }; + +static const int jtag2_pins[] = { 43, 44, 45, 46, 47 }; +/* Graphics SPI Clock pin group */ +static const int gspi_pins[] = { 12, 13, 14, 15 }; + +static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 }; +static const int spixcs1_pins[] = { 228 }; + +static const int pspi1_pins[] = { 175, 176, 177 }; +static const int pspi2_pins[] = { 17, 18, 19 }; + +static const int spi0cs1_pins[] = { 32 }; + +static const int spi3_pins[] = { 183, 184, 185, 186 }; +static const int spi3cs1_pins[] = { 187 }; +static const int spi3quad_pins[] = { 188, 189 }; +static const int spi3cs2_pins[] = { 188 }; +static const int spi3cs3_pins[] = { 189 }; + +static const int ddc_pins[] = { 204, 205, 206, 207 }; + +static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 }; +static const int lpcclk_pins[] = { 168 }; +static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 }; + +static const int lkgpo0_pins[] = { 16 }; +static const int lkgpo1_pins[] = { 8 }; +static const int lkgpo2_pins[] = { 9 }; + +static const int nprd_smi_pins[] = { 190 }; + +static const int hgpio0_pins[] = { 20 }; +static const int hgpio1_pins[] = { 21 }; +static const int hgpio2_pins[] = { 22 }; +static const int hgpio3_pins[] = { 23 }; +static const int hgpio4_pins[] = { 24 }; +static const int hgpio5_pins[] = { 25 }; +static const int hgpio6_pins[] = { 59 }; +static const int hgpio7_pins[] = { 60 }; + +/* + * pin: name, number + * group: name, npins, pins + * function: name, ngroups, groups + */ +struct npcm7xx_group { + const char *name; + const int *pins; + int npins; +}; + +#define NPCM7XX_GRPS \ + NPCM7XX_GRP(smb0), \ + NPCM7XX_GRP(smb0b), \ + NPCM7XX_GRP(smb0c), \ + NPCM7XX_GRP(smb0d), \ + NPCM7XX_GRP(smb0den), \ + NPCM7XX_GRP(smb1), \ + NPCM7XX_GRP(smb1b), \ + NPCM7XX_GRP(smb1c), \ + NPCM7XX_GRP(smb1d), \ + NPCM7XX_GRP(smb2), \ + NPCM7XX_GRP(smb2b), \ + NPCM7XX_GRP(smb2c), \ + NPCM7XX_GRP(smb2d), \ + NPCM7XX_GRP(smb3), \ + NPCM7XX_GRP(smb3b), \ + NPCM7XX_GRP(smb3c), \ + NPCM7XX_GRP(smb3d), \ + NPCM7XX_GRP(smb4), \ + NPCM7XX_GRP(smb4b), \ + NPCM7XX_GRP(smb4c), \ + NPCM7XX_GRP(smb4d), \ + NPCM7XX_GRP(smb4den), \ + NPCM7XX_GRP(smb5), \ + NPCM7XX_GRP(smb5b), \ + NPCM7XX_GRP(smb5c), \ + NPCM7XX_GRP(smb5d), \ + NPCM7XX_GRP(ga20kbc), \ + NPCM7XX_GRP(smb6), \ + NPCM7XX_GRP(smb7), \ + NPCM7XX_GRP(smb8), \ + NPCM7XX_GRP(smb9), \ + NPCM7XX_GRP(smb10), \ + NPCM7XX_GRP(smb11), \ + NPCM7XX_GRP(smb12), \ + NPCM7XX_GRP(smb13), \ + NPCM7XX_GRP(smb14), \ + NPCM7XX_GRP(smb15), \ + NPCM7XX_GRP(fanin0), \ + NPCM7XX_GRP(fanin1), \ + NPCM7XX_GRP(fanin2), \ + NPCM7XX_GRP(fanin3), \ + NPCM7XX_GRP(fanin4), \ + NPCM7XX_GRP(fanin5), \ + NPCM7XX_GRP(fanin6), \ + NPCM7XX_GRP(fanin7), \ + NPCM7XX_GRP(fanin8), \ + NPCM7XX_GRP(fanin9), \ + NPCM7XX_GRP(fanin10), \ + NPCM7XX_GRP(fanin11), \ + NPCM7XX_GRP(fanin12), \ + NPCM7XX_GRP(fanin13), \ + NPCM7XX_GRP(fanin14), \ + NPCM7XX_GRP(fanin15), \ + NPCM7XX_GRP(faninx), \ + NPCM7XX_GRP(pwm0), \ + NPCM7XX_GRP(pwm1), \ + NPCM7XX_GRP(pwm2), \ + NPCM7XX_GRP(pwm3), \ + NPCM7XX_GRP(pwm4), \ + NPCM7XX_GRP(pwm5), \ + NPCM7XX_GRP(pwm6), \ + NPCM7XX_GRP(pwm7), \ + NPCM7XX_GRP(rg1), \ + NPCM7XX_GRP(rg1mdio), \ + NPCM7XX_GRP(rg2), \ + NPCM7XX_GRP(rg2mdio), \ + NPCM7XX_GRP(ddr), \ + NPCM7XX_GRP(uart1), \ + NPCM7XX_GRP(uart2), \ + NPCM7XX_GRP(bmcuart0a), \ + NPCM7XX_GRP(bmcuart0b), \ + NPCM7XX_GRP(bmcuart1), \ + NPCM7XX_GRP(iox1), \ + NPCM7XX_GRP(iox2), \ + NPCM7XX_GRP(ioxh), \ + NPCM7XX_GRP(gspi), \ + NPCM7XX_GRP(mmc), \ + NPCM7XX_GRP(mmcwp), \ + NPCM7XX_GRP(mmccd), \ + NPCM7XX_GRP(mmcrst), \ + NPCM7XX_GRP(mmc8), \ + NPCM7XX_GRP(r1), \ + NPCM7XX_GRP(r1err), \ + NPCM7XX_GRP(r1md), \ + NPCM7XX_GRP(r2), \ + NPCM7XX_GRP(r2err), \ + NPCM7XX_GRP(r2md), \ + NPCM7XX_GRP(sd1), \ + NPCM7XX_GRP(sd1pwr), \ + NPCM7XX_GRP(wdog1), \ + NPCM7XX_GRP(wdog2), \ + NPCM7XX_GRP(scipme), \ + NPCM7XX_GRP(sci), \ + NPCM7XX_GRP(serirq), \ + NPCM7XX_GRP(jtag2), \ + NPCM7XX_GRP(spix), \ + NPCM7XX_GRP(spixcs1), \ + NPCM7XX_GRP(pspi1), \ + NPCM7XX_GRP(pspi2), \ + NPCM7XX_GRP(ddc), \ + NPCM7XX_GRP(clkreq), \ + NPCM7XX_GRP(clkout), \ + NPCM7XX_GRP(spi3), \ + NPCM7XX_GRP(spi3cs1), \ + NPCM7XX_GRP(spi3quad), \ + NPCM7XX_GRP(spi3cs2), \ + NPCM7XX_GRP(spi3cs3), \ + NPCM7XX_GRP(spi0cs1), \ + NPCM7XX_GRP(lpc), \ + NPCM7XX_GRP(lpcclk), \ + NPCM7XX_GRP(espi), \ + NPCM7XX_GRP(lkgpo0), \ + NPCM7XX_GRP(lkgpo1), \ + NPCM7XX_GRP(lkgpo2), \ + NPCM7XX_GRP(nprd_smi), \ + NPCM7XX_GRP(hgpio0), \ + NPCM7XX_GRP(hgpio1), \ + NPCM7XX_GRP(hgpio2), \ + NPCM7XX_GRP(hgpio3), \ + NPCM7XX_GRP(hgpio4), \ + NPCM7XX_GRP(hgpio5), \ + NPCM7XX_GRP(hgpio6), \ + NPCM7XX_GRP(hgpio7), \ + \ + +enum { +#define NPCM7XX_GRP(x) fn_ ## x + NPCM7XX_GRPS + /* add placeholder for none/gpio */ + NPCM7XX_GRP(none), + NPCM7XX_GRP(gpio), +#undef NPCM7XX_GRP +}; + +static struct npcm7xx_group npcm7xx_groups[] = { +#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \ + .npins = ARRAY_SIZE(x ## _pins) } + NPCM7XX_GRPS +#undef NPCM7XX_GRP +}; + +#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a) +#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b } +#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ + .groups = nm ## _grp } +struct npcm7xx_func { + const char *name; + const unsigned int ngroups; + const char *const *groups; +}; + +NPCM7XX_SFUNC(smb0); +NPCM7XX_SFUNC(smb0b); +NPCM7XX_SFUNC(smb0c); +NPCM7XX_SFUNC(smb0d); +NPCM7XX_SFUNC(smb0den); +NPCM7XX_SFUNC(smb1); +NPCM7XX_SFUNC(smb1b); +NPCM7XX_SFUNC(smb1c); +NPCM7XX_SFUNC(smb1d); +NPCM7XX_SFUNC(smb2); +NPCM7XX_SFUNC(smb2b); +NPCM7XX_SFUNC(smb2c); +NPCM7XX_SFUNC(smb2d); +NPCM7XX_SFUNC(smb3); +NPCM7XX_SFUNC(smb3b); +NPCM7XX_SFUNC(smb3c); +NPCM7XX_SFUNC(smb3d); +NPCM7XX_SFUNC(smb4); +NPCM7XX_SFUNC(smb4b); +NPCM7XX_SFUNC(smb4c); +NPCM7XX_SFUNC(smb4d); +NPCM7XX_SFUNC(smb4den); +NPCM7XX_SFUNC(smb5); +NPCM7XX_SFUNC(smb5b); +NPCM7XX_SFUNC(smb5c); +NPCM7XX_SFUNC(smb5d); +NPCM7XX_SFUNC(ga20kbc); +NPCM7XX_SFUNC(smb6); +NPCM7XX_SFUNC(smb7); +NPCM7XX_SFUNC(smb8); +NPCM7XX_SFUNC(smb9); +NPCM7XX_SFUNC(smb10); +NPCM7XX_SFUNC(smb11); +NPCM7XX_SFUNC(smb12); +NPCM7XX_SFUNC(smb13); +NPCM7XX_SFUNC(smb14); +NPCM7XX_SFUNC(smb15); +NPCM7XX_SFUNC(fanin0); +NPCM7XX_SFUNC(fanin1); +NPCM7XX_SFUNC(fanin2); +NPCM7XX_SFUNC(fanin3); +NPCM7XX_SFUNC(fanin4); +NPCM7XX_SFUNC(fanin5); +NPCM7XX_SFUNC(fanin6); +NPCM7XX_SFUNC(fanin7); +NPCM7XX_SFUNC(fanin8); +NPCM7XX_SFUNC(fanin9); +NPCM7XX_SFUNC(fanin10); +NPCM7XX_SFUNC(fanin11); +NPCM7XX_SFUNC(fanin12); +NPCM7XX_SFUNC(fanin13); +NPCM7XX_SFUNC(fanin14); +NPCM7XX_SFUNC(fanin15); +NPCM7XX_SFUNC(faninx); +NPCM7XX_SFUNC(pwm0); +NPCM7XX_SFUNC(pwm1); +NPCM7XX_SFUNC(pwm2); +NPCM7XX_SFUNC(pwm3); +NPCM7XX_SFUNC(pwm4); +NPCM7XX_SFUNC(pwm5); +NPCM7XX_SFUNC(pwm6); +NPCM7XX_SFUNC(pwm7); +NPCM7XX_SFUNC(rg1); +NPCM7XX_SFUNC(rg1mdio); +NPCM7XX_SFUNC(rg2); +NPCM7XX_SFUNC(rg2mdio); +NPCM7XX_SFUNC(ddr); +NPCM7XX_SFUNC(uart1); +NPCM7XX_SFUNC(uart2); +NPCM7XX_SFUNC(bmcuart0a); +NPCM7XX_SFUNC(bmcuart0b); +NPCM7XX_SFUNC(bmcuart1); +NPCM7XX_SFUNC(iox1); +NPCM7XX_SFUNC(iox2); +NPCM7XX_SFUNC(ioxh); +NPCM7XX_SFUNC(gspi); +NPCM7XX_SFUNC(mmc); +NPCM7XX_SFUNC(mmcwp); +NPCM7XX_SFUNC(mmccd); +NPCM7XX_SFUNC(mmcrst); +NPCM7XX_SFUNC(mmc8); +NPCM7XX_SFUNC(r1); +NPCM7XX_SFUNC(r1err); +NPCM7XX_SFUNC(r1md); +NPCM7XX_SFUNC(r2); +NPCM7XX_SFUNC(r2err); +NPCM7XX_SFUNC(r2md); +NPCM7XX_SFUNC(sd1); +NPCM7XX_SFUNC(sd1pwr); +NPCM7XX_SFUNC(wdog1); +NPCM7XX_SFUNC(wdog2); +NPCM7XX_SFUNC(scipme); +NPCM7XX_SFUNC(sci); +NPCM7XX_SFUNC(serirq); +NPCM7XX_SFUNC(jtag2); +NPCM7XX_SFUNC(spix); +NPCM7XX_SFUNC(spixcs1); +NPCM7XX_SFUNC(pspi1); +NPCM7XX_SFUNC(pspi2); +NPCM7XX_SFUNC(ddc); +NPCM7XX_SFUNC(clkreq); +NPCM7XX_SFUNC(clkout); +NPCM7XX_SFUNC(spi3); +NPCM7XX_SFUNC(spi3cs1); +NPCM7XX_SFUNC(spi3quad); +NPCM7XX_SFUNC(spi3cs2); +NPCM7XX_SFUNC(spi3cs3); +NPCM7XX_SFUNC(spi0cs1); +NPCM7XX_SFUNC(lpc); +NPCM7XX_SFUNC(lpcclk); +NPCM7XX_SFUNC(espi); +NPCM7XX_SFUNC(lkgpo0); +NPCM7XX_SFUNC(lkgpo1); +NPCM7XX_SFUNC(lkgpo2); +NPCM7XX_SFUNC(nprd_smi); +NPCM7XX_SFUNC(hgpio0); +NPCM7XX_SFUNC(hgpio1); +NPCM7XX_SFUNC(hgpio2); +NPCM7XX_SFUNC(hgpio3); +NPCM7XX_SFUNC(hgpio4); +NPCM7XX_SFUNC(hgpio5); +NPCM7XX_SFUNC(hgpio6); +NPCM7XX_SFUNC(hgpio7); + +/* Function names */ +static struct npcm7xx_func npcm7xx_funcs[] = { + NPCM7XX_MKFUNC(smb0), + NPCM7XX_MKFUNC(smb0b), + NPCM7XX_MKFUNC(smb0c), + NPCM7XX_MKFUNC(smb0d), + NPCM7XX_MKFUNC(smb0den), + NPCM7XX_MKFUNC(smb1), + NPCM7XX_MKFUNC(smb1b), + NPCM7XX_MKFUNC(smb1c), + NPCM7XX_MKFUNC(smb1d), + NPCM7XX_MKFUNC(smb2), + NPCM7XX_MKFUNC(smb2b), + NPCM7XX_MKFUNC(smb2c), + NPCM7XX_MKFUNC(smb2d), + NPCM7XX_MKFUNC(smb3), + NPCM7XX_MKFUNC(smb3b), + NPCM7XX_MKFUNC(smb3c), + NPCM7XX_MKFUNC(smb3d), + NPCM7XX_MKFUNC(smb4), + NPCM7XX_MKFUNC(smb4b), + NPCM7XX_MKFUNC(smb4c), + NPCM7XX_MKFUNC(smb4d), + NPCM7XX_MKFUNC(smb4den), + NPCM7XX_MKFUNC(smb5), + NPCM7XX_MKFUNC(smb5b), + NPCM7XX_MKFUNC(smb5c), + NPCM7XX_MKFUNC(smb5d), + NPCM7XX_MKFUNC(ga20kbc), + NPCM7XX_MKFUNC(smb6), + NPCM7XX_MKFUNC(smb7), + NPCM7XX_MKFUNC(smb8), + NPCM7XX_MKFUNC(smb9), + NPCM7XX_MKFUNC(smb10), + NPCM7XX_MKFUNC(smb11), + NPCM7XX_MKFUNC(smb12), + NPCM7XX_MKFUNC(smb13), + NPCM7XX_MKFUNC(smb14), + NPCM7XX_MKFUNC(smb15), + NPCM7XX_MKFUNC(fanin0), + NPCM7XX_MKFUNC(fanin1), + NPCM7XX_MKFUNC(fanin2), + NPCM7XX_MKFUNC(fanin3), + NPCM7XX_MKFUNC(fanin4), + NPCM7XX_MKFUNC(fanin5), + NPCM7XX_MKFUNC(fanin6), + NPCM7XX_MKFUNC(fanin7), + NPCM7XX_MKFUNC(fanin8), + NPCM7XX_MKFUNC(fanin9), + NPCM7XX_MKFUNC(fanin10), + NPCM7XX_MKFUNC(fanin11), + NPCM7XX_MKFUNC(fanin12), + NPCM7XX_MKFUNC(fanin13), + NPCM7XX_MKFUNC(fanin14), + NPCM7XX_MKFUNC(fanin15), + NPCM7XX_MKFUNC(faninx), + NPCM7XX_MKFUNC(pwm0), + NPCM7XX_MKFUNC(pwm1), + NPCM7XX_MKFUNC(pwm2), + NPCM7XX_MKFUNC(pwm3), + NPCM7XX_MKFUNC(pwm4), + NPCM7XX_MKFUNC(pwm5), + NPCM7XX_MKFUNC(pwm6), + NPCM7XX_MKFUNC(pwm7), + NPCM7XX_MKFUNC(rg1), + NPCM7XX_MKFUNC(rg1mdio), + NPCM7XX_MKFUNC(rg2), + NPCM7XX_MKFUNC(rg2mdio), + NPCM7XX_MKFUNC(ddr), + NPCM7XX_MKFUNC(uart1), + NPCM7XX_MKFUNC(uart2), + NPCM7XX_MKFUNC(bmcuart0a), + NPCM7XX_MKFUNC(bmcuart0b), + NPCM7XX_MKFUNC(bmcuart1), + NPCM7XX_MKFUNC(iox1), + NPCM7XX_MKFUNC(iox2), + NPCM7XX_MKFUNC(ioxh), + NPCM7XX_MKFUNC(gspi), + NPCM7XX_MKFUNC(mmc), + NPCM7XX_MKFUNC(mmcwp), + NPCM7XX_MKFUNC(mmccd), + NPCM7XX_MKFUNC(mmcrst), + NPCM7XX_MKFUNC(mmc8), + NPCM7XX_MKFUNC(r1), + NPCM7XX_MKFUNC(r1err), + NPCM7XX_MKFUNC(r1md), + NPCM7XX_MKFUNC(r2), + NPCM7XX_MKFUNC(r2err), + NPCM7XX_MKFUNC(r2md), + NPCM7XX_MKFUNC(sd1), + NPCM7XX_MKFUNC(sd1pwr), + NPCM7XX_MKFUNC(wdog1), + NPCM7XX_MKFUNC(wdog2), + NPCM7XX_MKFUNC(scipme), + NPCM7XX_MKFUNC(sci), + NPCM7XX_MKFUNC(serirq), + NPCM7XX_MKFUNC(jtag2), + NPCM7XX_MKFUNC(spix), + NPCM7XX_MKFUNC(spixcs1), + NPCM7XX_MKFUNC(pspi1), + NPCM7XX_MKFUNC(pspi2), + NPCM7XX_MKFUNC(ddc), + NPCM7XX_MKFUNC(clkreq), + NPCM7XX_MKFUNC(clkout), + NPCM7XX_MKFUNC(spi3), + NPCM7XX_MKFUNC(spi3cs1), + NPCM7XX_MKFUNC(spi3quad), + NPCM7XX_MKFUNC(spi3cs2), + NPCM7XX_MKFUNC(spi3cs3), + NPCM7XX_MKFUNC(spi0cs1), + NPCM7XX_MKFUNC(lpc), + NPCM7XX_MKFUNC(lpcclk), + NPCM7XX_MKFUNC(espi), + NPCM7XX_MKFUNC(lkgpo0), + NPCM7XX_MKFUNC(lkgpo1), + NPCM7XX_MKFUNC(lkgpo2), + NPCM7XX_MKFUNC(nprd_smi), + NPCM7XX_MKFUNC(hgpio0), + NPCM7XX_MKFUNC(hgpio1), + NPCM7XX_MKFUNC(hgpio2), + NPCM7XX_MKFUNC(hgpio3), + NPCM7XX_MKFUNC(hgpio4), + NPCM7XX_MKFUNC(hgpio5), + NPCM7XX_MKFUNC(hgpio6), + NPCM7XX_MKFUNC(hgpio7), +}; + +#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ + [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ + .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \ + .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \ + .flag = k } + +/* Drive strength controlled by NPCM7XX_GP_N_ODSC */ +#define DRIVE_STRENGTH_LO_SHIFT 8 +#define DRIVE_STRENGTH_HI_SHIFT 12 +#define DRIVE_STRENGTH_MASK 0x0000FF00 + +#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ + ((hi) << DRIVE_STRENGTH_HI_SHIFT)) +#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) +#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) + +#define GPI 0x1 /* Not GPO */ +#define GPO 0x2 /* Not GPI */ +#define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */ +#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */ + +struct npcm7xx_pincfg { + int flag; + int fn0, reg0, bit0; + int fn1, reg1, bit1; + int fn2, reg2, bit2; +}; + +static const struct npcm7xx_pincfg pincfgs[] = { + /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ + NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, 0), + NPCM7XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, 0), + NPCM7XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, 0), + NPCM7XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, 0), + NPCM7XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), + + NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO), + NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), + NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), + NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), + NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), + NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), + NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), + NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO), + NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO), + NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, none, NONE, 0, 0), + NPCM7XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, none, NONE, 0, 0), + NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), + NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO), + NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO), + + NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), + NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), + NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), + + NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW), + + NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), + NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ + NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ + NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + + NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)), + NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), + NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), + NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), + NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), + NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), + NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0), + NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ + + NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ + NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), + + NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ + NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ + NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ +}; + +#define NPCM7XX_PIN(a, b) { .number = a, .name = b } +struct npcm7xx_pin_desc { + unsigned int number; + const char *name; +}; + +/* number, name, drv_data */ +static const struct npcm7xx_pin_desc npcm7xx_pins[] = { + NPCM7XX_PIN(0, "GPIO0/IOX1DI"), + NPCM7XX_PIN(1, "GPIO1/IOX1LD"), + NPCM7XX_PIN(2, "GPIO2/IOX1CK"), + NPCM7XX_PIN(3, "GPIO3/IOX1D0"), + NPCM7XX_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"), + NPCM7XX_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"), + NPCM7XX_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"), + NPCM7XX_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"), + NPCM7XX_PIN(8, "GPIO8/LKGPO1"), + NPCM7XX_PIN(9, "GPIO9/LKGPO2"), + NPCM7XX_PIN(10, "GPIO10/IOXHLD"), + NPCM7XX_PIN(11, "GPIO11/IOXHCK"), + NPCM7XX_PIN(12, "GPIO12/GSPICK/SMB5BSCL"), + NPCM7XX_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"), + NPCM7XX_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"), + NPCM7XX_PIN(15, "GPIO15/GSPICS/SMB5CSDA"), + NPCM7XX_PIN(16, "GPIO16/LKGPO0"), + NPCM7XX_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"), + NPCM7XX_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"), + NPCM7XX_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"), + NPCM7XX_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"), + NPCM7XX_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"), + NPCM7XX_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"), + NPCM7XX_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"), + NPCM7XX_PIN(24, "GPIO24/IOXHDO"), + NPCM7XX_PIN(25, "GPIO25/IOXHDI"), + NPCM7XX_PIN(26, "GPIO26/SMB5SDA"), + NPCM7XX_PIN(27, "GPIO27/SMB5SCL"), + NPCM7XX_PIN(28, "GPIO28/SMB4SDA"), + NPCM7XX_PIN(29, "GPIO29/SMB4SCL"), + NPCM7XX_PIN(30, "GPIO30/SMB3SDA"), + NPCM7XX_PIN(31, "GPIO31/SMB3SCL"), + + NPCM7XX_PIN(32, "GPIO32/nSPI0CS1"), + NPCM7XX_PIN(33, "SPI0D2"), + NPCM7XX_PIN(34, "SPI0D3"), + NPCM7XX_PIN(35, "NA"), + NPCM7XX_PIN(36, "NA"), + NPCM7XX_PIN(37, "GPIO37/SMB3CSDA"), + NPCM7XX_PIN(38, "GPIO38/SMB3CSCL"), + NPCM7XX_PIN(39, "GPIO39/SMB3BSDA"), + NPCM7XX_PIN(40, "GPIO40/SMB3BSCL"), + NPCM7XX_PIN(41, "GPIO41/BSPRXD"), + NPCM7XX_PIN(42, "GPO42/BSPTXD/STRAP11"), + NPCM7XX_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"), + NPCM7XX_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"), + NPCM7XX_PIN(45, "GPIO45/nDCD1/JTDO2"), + NPCM7XX_PIN(46, "GPIO46/nDSR1/JTCK2"), + NPCM7XX_PIN(47, "GPIO47/nRI1/JCP_RDY2"), + NPCM7XX_PIN(48, "GPIO48/TXD2/BSPTXD"), + NPCM7XX_PIN(49, "GPIO49/RXD2/BSPRXD"), + NPCM7XX_PIN(50, "GPIO50/nCTS2"), + NPCM7XX_PIN(51, "GPO51/nRTS2/STRAP2"), + NPCM7XX_PIN(52, "GPIO52/nDCD2"), + NPCM7XX_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"), + NPCM7XX_PIN(54, "GPIO54/nDSR2"), + NPCM7XX_PIN(55, "GPIO55/nRI2"), + NPCM7XX_PIN(56, "GPIO56/R1RXERR"), + NPCM7XX_PIN(57, "GPIO57/R1MDC"), + NPCM7XX_PIN(58, "GPIO58/R1MDIO"), + NPCM7XX_PIN(59, "GPIO59/SMB3DSDA"), + NPCM7XX_PIN(60, "GPIO60/SMB3DSCL"), + NPCM7XX_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"), + NPCM7XX_PIN(62, "GPO62/nRTST1/STRAP5"), + NPCM7XX_PIN(63, "GPO63/TXD1/STRAP4"), + + NPCM7XX_PIN(64, "GPIO64/FANIN0"), + NPCM7XX_PIN(65, "GPIO65/FANIN1"), + NPCM7XX_PIN(66, "GPIO66/FANIN2"), + NPCM7XX_PIN(67, "GPIO67/FANIN3"), + NPCM7XX_PIN(68, "GPIO68/FANIN4"), + NPCM7XX_PIN(69, "GPIO69/FANIN5"), + NPCM7XX_PIN(70, "GPIO70/FANIN6"), + NPCM7XX_PIN(71, "GPIO71/FANIN7"), + NPCM7XX_PIN(72, "GPIO72/FANIN8"), + NPCM7XX_PIN(73, "GPIO73/FANIN9"), + NPCM7XX_PIN(74, "GPIO74/FANIN10"), + NPCM7XX_PIN(75, "GPIO75/FANIN11"), + NPCM7XX_PIN(76, "GPIO76/FANIN12"), + NPCM7XX_PIN(77, "GPIO77/FANIN13"), + NPCM7XX_PIN(78, "GPIO78/FANIN14"), + NPCM7XX_PIN(79, "GPIO79/FANIN15"), + NPCM7XX_PIN(80, "GPIO80/PWM0"), + NPCM7XX_PIN(81, "GPIO81/PWM1"), + NPCM7XX_PIN(82, "GPIO82/PWM2"), + NPCM7XX_PIN(83, "GPIO83/PWM3"), + NPCM7XX_PIN(84, "GPIO84/R2TXD0"), + NPCM7XX_PIN(85, "GPIO85/R2TXD1"), + NPCM7XX_PIN(86, "GPIO86/R2TXEN"), + NPCM7XX_PIN(87, "GPIO87/R2RXD0"), + NPCM7XX_PIN(88, "GPIO88/R2RXD1"), + NPCM7XX_PIN(89, "GPIO89/R2CRSDV"), + NPCM7XX_PIN(90, "GPIO90/R2RXERR"), + NPCM7XX_PIN(91, "GPIO91/R2MDC"), + NPCM7XX_PIN(92, "GPIO92/R2MDIO"), + NPCM7XX_PIN(93, "GPIO93/GA20/SMB5DSCL"), + NPCM7XX_PIN(94, "GPIO94/nKBRST/SMB5DSDA"), + NPCM7XX_PIN(95, "GPIO95/nLRESET/nESPIRST"), + + NPCM7XX_PIN(96, "GPIO96/RG1TXD0"), + NPCM7XX_PIN(97, "GPIO97/RG1TXD1"), + NPCM7XX_PIN(98, "GPIO98/RG1TXD2"), + NPCM7XX_PIN(99, "GPIO99/RG1TXD3"), + NPCM7XX_PIN(100, "GPIO100/RG1TXC"), + NPCM7XX_PIN(101, "GPIO101/RG1TXCTL"), + NPCM7XX_PIN(102, "GPIO102/RG1RXD0"), + NPCM7XX_PIN(103, "GPIO103/RG1RXD1"), + NPCM7XX_PIN(104, "GPIO104/RG1RXD2"), + NPCM7XX_PIN(105, "GPIO105/RG1RXD3"), + NPCM7XX_PIN(106, "GPIO106/RG1RXC"), + NPCM7XX_PIN(107, "GPIO107/RG1RXCTL"), + NPCM7XX_PIN(108, "GPIO108/RG1MDC"), + NPCM7XX_PIN(109, "GPIO109/RG1MDIO"), + NPCM7XX_PIN(110, "GPIO110/RG2TXD0/DDRV0"), + NPCM7XX_PIN(111, "GPIO111/RG2TXD1/DDRV1"), + NPCM7XX_PIN(112, "GPIO112/RG2TXD2/DDRV2"), + NPCM7XX_PIN(113, "GPIO113/RG2TXD3/DDRV3"), + NPCM7XX_PIN(114, "GPIO114/SMB0SCL"), + NPCM7XX_PIN(115, "GPIO115/SMB0SDA"), + NPCM7XX_PIN(116, "GPIO116/SMB1SCL"), + NPCM7XX_PIN(117, "GPIO117/SMB1SDA"), + NPCM7XX_PIN(118, "GPIO118/SMB2SCL"), + NPCM7XX_PIN(119, "GPIO119/SMB2SDA"), + NPCM7XX_PIN(120, "GPIO120/SMB2CSDA"), + NPCM7XX_PIN(121, "GPIO121/SMB2CSCL"), + NPCM7XX_PIN(122, "GPIO122/SMB2BSDA"), + NPCM7XX_PIN(123, "GPIO123/SMB2BSCL"), + NPCM7XX_PIN(124, "GPIO124/SMB1CSDA"), + NPCM7XX_PIN(125, "GPIO125/SMB1CSCL"), + NPCM7XX_PIN(126, "GPIO126/SMB1BSDA"), + NPCM7XX_PIN(127, "GPIO127/SMB1BSCL"), + + NPCM7XX_PIN(128, "GPIO128/SMB8SCL"), + NPCM7XX_PIN(129, "GPIO129/SMB8SDA"), + NPCM7XX_PIN(130, "GPIO130/SMB9SCL"), + NPCM7XX_PIN(131, "GPIO131/SMB9SDA"), + NPCM7XX_PIN(132, "GPIO132/SMB10SCL"), + NPCM7XX_PIN(133, "GPIO133/SMB10SDA"), + NPCM7XX_PIN(134, "GPIO134/SMB11SCL"), + NPCM7XX_PIN(135, "GPIO135/SMB11SDA"), + NPCM7XX_PIN(136, "GPIO136/SD1DT0"), + NPCM7XX_PIN(137, "GPIO137/SD1DT1"), + NPCM7XX_PIN(138, "GPIO138/SD1DT2"), + NPCM7XX_PIN(139, "GPIO139/SD1DT3"), + NPCM7XX_PIN(140, "GPIO140/SD1CLK"), + NPCM7XX_PIN(141, "GPIO141/SD1WP"), + NPCM7XX_PIN(142, "GPIO142/SD1CMD"), + NPCM7XX_PIN(143, "GPIO143/SD1CD/SD1PWR"), + NPCM7XX_PIN(144, "GPIO144/PWM4"), + NPCM7XX_PIN(145, "GPIO145/PWM5"), + NPCM7XX_PIN(146, "GPIO146/PWM6"), + NPCM7XX_PIN(147, "GPIO147/PWM7"), + NPCM7XX_PIN(148, "GPIO148/MMCDT4"), + NPCM7XX_PIN(149, "GPIO149/MMCDT5"), + NPCM7XX_PIN(150, "GPIO150/MMCDT6"), + NPCM7XX_PIN(151, "GPIO151/MMCDT7"), + NPCM7XX_PIN(152, "GPIO152/MMCCLK"), + NPCM7XX_PIN(153, "GPIO153/MMCWP"), + NPCM7XX_PIN(154, "GPIO154/MMCCMD"), + NPCM7XX_PIN(155, "GPIO155/nMMCCD/nMMCRST"), + NPCM7XX_PIN(156, "GPIO156/MMCDT0"), + NPCM7XX_PIN(157, "GPIO157/MMCDT1"), + NPCM7XX_PIN(158, "GPIO158/MMCDT2"), + NPCM7XX_PIN(159, "GPIO159/MMCDT3"), + + NPCM7XX_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"), + NPCM7XX_PIN(161, "GPIO161/nLFRAME/nESPICS"), + NPCM7XX_PIN(162, "GPIO162/SERIRQ"), + NPCM7XX_PIN(163, "GPIO163/LCLK/ESPICLK"), + NPCM7XX_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/), + NPCM7XX_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/), + NPCM7XX_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/), + NPCM7XX_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/), + NPCM7XX_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"), + NPCM7XX_PIN(169, "GPIO169/nSCIPME"), + NPCM7XX_PIN(170, "GPIO170/nSMI"), + NPCM7XX_PIN(171, "GPIO171/SMB6SCL"), + NPCM7XX_PIN(172, "GPIO172/SMB6SDA"), + NPCM7XX_PIN(173, "GPIO173/SMB7SCL"), + NPCM7XX_PIN(174, "GPIO174/SMB7SDA"), + NPCM7XX_PIN(175, "GPIO175/PSPI1CK/FANIN19"), + NPCM7XX_PIN(176, "GPIO176/PSPI1DO/FANIN18"), + NPCM7XX_PIN(177, "GPIO177/PSPI1DI/FANIN17"), + NPCM7XX_PIN(178, "GPIO178/R1TXD0"), + NPCM7XX_PIN(179, "GPIO179/R1TXD1"), + NPCM7XX_PIN(180, "GPIO180/R1TXEN"), + NPCM7XX_PIN(181, "GPIO181/R1RXD0"), + NPCM7XX_PIN(182, "GPIO182/R1RXD1"), + NPCM7XX_PIN(183, "GPIO183/SPI3CK"), + NPCM7XX_PIN(184, "GPO184/SPI3D0/STRAP9"), + NPCM7XX_PIN(185, "GPO185/SPI3D1/STRAP10"), + NPCM7XX_PIN(186, "GPIO186/nSPI3CS0"), + NPCM7XX_PIN(187, "GPIO187/nSPI3CS1"), + NPCM7XX_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"), + NPCM7XX_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"), + NPCM7XX_PIN(190, "GPIO190/nPRD_SMI"), + NPCM7XX_PIN(191, "GPIO191"), + + NPCM7XX_PIN(192, "GPIO192"), + NPCM7XX_PIN(193, "GPIO193/R1CRSDV"), + NPCM7XX_PIN(194, "GPIO194/SMB0BSCL"), + NPCM7XX_PIN(195, "GPIO195/SMB0BSDA"), + NPCM7XX_PIN(196, "GPIO196/SMB0CSCL"), + NPCM7XX_PIN(197, "GPIO197/SMB0DEN"), + NPCM7XX_PIN(198, "GPIO198/SMB0DSDA"), + NPCM7XX_PIN(199, "GPIO199/SMB0DSCL"), + NPCM7XX_PIN(200, "GPIO200/R2CK"), + NPCM7XX_PIN(201, "GPIO201/R1CK"), + NPCM7XX_PIN(202, "GPIO202/SMB0CSDA"), + NPCM7XX_PIN(203, "GPIO203/FANIN16"), + NPCM7XX_PIN(204, "GPIO204/DDC2SCL"), + NPCM7XX_PIN(205, "GPIO205/DDC2SDA"), + NPCM7XX_PIN(206, "GPIO206/HSYNC2"), + NPCM7XX_PIN(207, "GPIO207/VSYNC2"), + NPCM7XX_PIN(208, "GPIO208/RG2TXC/DVCK"), + NPCM7XX_PIN(209, "GPIO209/RG2TXCTL/DDRV4"), + NPCM7XX_PIN(210, "GPIO210/RG2RXD0/DDRV5"), + NPCM7XX_PIN(211, "GPIO211/RG2RXD1/DDRV6"), + NPCM7XX_PIN(212, "GPIO212/RG2RXD2/DDRV7"), + NPCM7XX_PIN(213, "GPIO213/RG2RXD3/DDRV8"), + NPCM7XX_PIN(214, "GPIO214/RG2RXC/DDRV9"), + NPCM7XX_PIN(215, "GPIO215/RG2RXCTL/DDRV10"), + NPCM7XX_PIN(216, "GPIO216/RG2MDC/DDRV11"), + NPCM7XX_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"), + NPCM7XX_PIN(218, "GPIO218/nWDO1"), + NPCM7XX_PIN(219, "GPIO219/nWDO2"), + NPCM7XX_PIN(220, "GPIO220/SMB12SCL"), + NPCM7XX_PIN(221, "GPIO221/SMB12SDA"), + NPCM7XX_PIN(222, "GPIO222/SMB13SCL"), + NPCM7XX_PIN(223, "GPIO223/SMB13SDA"), + NPCM7XX_PIN(224, "GPIO224/SPIXCK"), + NPCM7XX_PIN(225, "GPO225/SPIXD0/STRAP12"), + NPCM7XX_PIN(226, "GPO226/SPIXD1/STRAP13"), + NPCM7XX_PIN(227, "GPIO227/nSPIXCS0"), + NPCM7XX_PIN(228, "GPIO228/nSPIXCS1"), + NPCM7XX_PIN(229, "GPO229/SPIXD2/STRAP3"), + NPCM7XX_PIN(230, "GPIO230/SPIXD3"), + NPCM7XX_PIN(231, "GPIO231/nCLKREQ"), + NPCM7XX_PIN(232, "NA"), + NPCM7XX_PIN(233, "NA"), + NPCM7XX_PIN(234, "NA"), + NPCM7XX_PIN(235, "NA"), + NPCM7XX_PIN(236, "NA"), + NPCM7XX_PIN(237, "NA"), + NPCM7XX_PIN(238, "NA"), + NPCM7XX_PIN(239, "NA"), + NPCM7XX_PIN(240, "NA"), + NPCM7XX_PIN(241, "NA"), + NPCM7XX_PIN(242, "NA"), + NPCM7XX_PIN(243, "NA"), + NPCM7XX_PIN(244, "NA"), + NPCM7XX_PIN(245, "NA"), + NPCM7XX_PIN(246, "NA"), + NPCM7XX_PIN(247, "NA"), + NPCM7XX_PIN(248, "NA"), + NPCM7XX_PIN(249, "NA"), + NPCM7XX_PIN(250, "NA"), + NPCM7XX_PIN(251, "NA"), + NPCM7XX_PIN(252, "NA"), + NPCM7XX_PIN(253, "NA"), + NPCM7XX_PIN(254, "NA"), + NPCM7XX_PIN(255, "GPI255/DACOSEL"), +}; + +struct npcm7xx_pinctrl_priv { + void __iomem *gpio_base; + struct regmap *gcr_regmap; + struct regmap *rst_regmap; +}; + +static int npcm7xx_pinctrl_probe(struct udevice *dev) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + + priv->gpio_base = dev_read_addr_ptr(dev); + if (!priv->gpio_base) + return -EINVAL; + + priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr"); + if (IS_ERR(priv->gcr_regmap)) + return -EINVAL; + + priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst"); + if (IS_ERR(priv->rst_regmap)) + return -EINVAL; + + return 0; +} + +/* Enable mode in pin group */ +static void npcm7xx_setfunc(struct udevice *dev, const int *pin, + int pin_number, int mode) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + const struct npcm7xx_pincfg *cfg; + int i; + + for (i = 0 ; i < pin_number ; i++) { + cfg = &pincfgs[pin[i]]; + if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) { + if (cfg->reg0) { + if (cfg->fn0 == mode) + regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), BIT(cfg->bit0)); + else + regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), 0); + } + if (cfg->reg1) { + if (cfg->fn1 == mode) + regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), BIT(cfg->bit1)); + else + regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), 0); + } + if (cfg->reg2) { + if (cfg->fn2 == mode) + regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), BIT(cfg->bit2)); + else + regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), 0); + } + } + } +} + +static int npcm7xx_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(npcm7xx_pins); +} + +static const char *npcm7xx_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + return npcm7xx_pins[selector].name; +} + +static int npcm7xx_get_groups_count(struct udevice *dev) +{ + return ARRAY_SIZE(npcm7xx_groups); +} + +static const char *npcm7xx_get_group_name(struct udevice *dev, + unsigned int selector) +{ + return npcm7xx_groups[selector].name; +} + +static int npcm7xx_get_functions_count(struct udevice *dev) +{ + return ARRAY_SIZE(npcm7xx_funcs); +} + +static const char *npcm7xx_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return npcm7xx_funcs[selector].name; +} + +static int npcm7xx_pinmux_set(struct udevice *dev, + unsigned int group, + unsigned int function) +{ + dev_dbg(dev, "set_mux: %d, %d[%s]\n", function, group, + npcm7xx_groups[group].name); + + npcm7xx_setfunc(dev, npcm7xx_groups[group].pins, + npcm7xx_groups[group].npins, group); + + return 0; +} + +#if CONFIG_IS_ENABLED(PINCONF) + +#define PIN_CONFIG_PERSIST_STATE (PIN_CONFIG_END + 1) +#define PIN_CONFIG_POLARITY_STATE (PIN_CONFIG_END + 2) +#define PIN_CONFIG_EVENT_CLEAR (PIN_CONFIG_END + 3) + +static const struct pinconf_param npcm7xx_conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 1 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 1 }, + { "persist-enable", PIN_CONFIG_PERSIST_STATE, 1 }, + { "persist-disable", PIN_CONFIG_PERSIST_STATE, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "active-high", PIN_CONFIG_POLARITY_STATE, 0 }, + { "active-low", PIN_CONFIG_POLARITY_STATE, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, + { "event-clear", PIN_CONFIG_EVENT_CLEAR, 0}, +}; + +static bool is_gpio_persist(struct udevice *dev, u8 bank) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + u32 value, tmp; + + u8 offset = bank + GPIOX_MODULE_RESET; + u32 mask = 1 << offset; + + regmap_read(priv->gcr_regmap, NPCM7XX_GCR_RESSR, &value); + if (value == 0) { + regmap_read(priv->gcr_regmap, NPCM7XX_GCR_INTCR2, &tmp); + value = ~tmp; + } + + dev_dbg(dev, "reboot reason: 0x%x\n", value); + + if (value & CORST) + regmap_read(priv->rst_regmap, NPCM7XX_RST_CORSTC, &tmp); + else if (value & WD0RST) + regmap_read(priv->rst_regmap, NPCM7XX_RST_WD0RCR, &tmp); + else if (value & WD1RST) + regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp); + else if (value & WD2RST) + regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp); + else + return false; + + return !((tmp & mask) >> offset); +} + +static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum, int enable) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + u32 num = GPIOX_MODULE_RESET + banknum; + + dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable); + + if (enable) { + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, 0); + } else { + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + } + + return 0; +} + +/* Set drive strength for a pin, if supported */ +static int npcm7xx_set_drive_strength(struct udevice *dev, + unsigned int pin, int nval) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + int bank = pin / NPCM7XX_GPIO_PER_BANK; + int gpio = (pin % NPCM7XX_GPIO_PER_BITS); + void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank); + int v; + + v = (pincfgs[pin].flag & DRIVE_STRENGTH_MASK); + if (!nval || !v) + return -ENOTSUPP; + + if (DSLO(v) == nval) { + dev_dbg(dev, + "setting pin %d to low strength [%d]\n", pin, nval); + clrbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio)); + return 0; + } else if (DSHI(v) == nval) { + dev_dbg(dev, + "setting pin %d to high strength [%d]\n", pin, nval); + setbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio)); + return 0; + } + + return -ENOTSUPP; +} + +/* Set slew rate of pin (high/low) */ +static int npcm7xx_set_slew_rate(struct udevice *dev, unsigned int pin, + int arg) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + int bank = pin / NPCM7XX_GPIO_PER_BANK; + int gpio = (pin % NPCM7XX_GPIO_PER_BITS); + void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank); + + if (pincfgs[pin].flag & SLEW) { + switch (arg) { + case 0: + dev_dbg(dev, + "setting pin %d slew rate to low\n", pin); + clrbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio)); + return 0; + case 1: + dev_dbg(dev, + "setting pin %d slew rate to high\n", pin); + setbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio)); + return 0; + default: + return -ENOTSUPP; + } + } + + /* LPC Slew rate in SRCNT register */ + if (pincfgs[pin].flag & SLEWLPC) { + switch (arg) { + case 0: + dev_dbg(dev, + "setting LPC/ESPI(%d) slew rate to low\n", pin); + regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, 0); + return 0; + case 1: + dev_dbg(dev, "setting LPC/ESPI(%d) slew rate to high\n", pin); + regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, SRCNT_ESPI); + return 0; + default: + return -ENOTSUPP; + } + } + + return -ENOTSUPP; +} + +static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev); + int err = 0; + int bank = pin / NPCM7XX_GPIO_PER_BANK; + int gpio = (pin % NPCM7XX_GPIO_PER_BITS); + void __iomem *base = priv->gpio_base + (0x1000 * bank); + + npcm7xx_setfunc(dev, (const int *)&pin, 1, fn_gpio); + + /* To prevent unexpected IRQ trap at verctor 00 in linux kernel */ + if (param == PIN_CONFIG_EVENT_CLEAR) { + dev_dbg(dev, "set pin %d event clear\n", pin); + clrbits_le32(base + NPCM7XX_GP_N_EVEN, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_EVST, BIT(gpio)); + return err; + } + + // allow set persist state disable + if (param == PIN_CONFIG_PERSIST_STATE) { + npcm7xx_gpio_reset_persist(dev, bank, arg); + return err; + } + + if (is_gpio_persist(dev, bank)) + return err; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + dev_dbg(dev, "set pin %d bias dsiable\n", pin); + clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio)); + clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + dev_dbg(dev, "set pin %d bias pull down\n", pin); + clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + dev_dbg(dev, "set pin %d bias pull up\n", pin); + setbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio)); + clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio)); + break; + case PIN_CONFIG_INPUT_ENABLE: + dev_dbg(dev, "set pin %d input enable\n", pin); + setbits_le32(base + NPCM7XX_GP_N_OEC, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); + break; + case PIN_CONFIG_OUTPUT_ENABLE: + dev_dbg(dev, "set pin %d output enable\n", pin); + clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); + case PIN_CONFIG_OUTPUT: + dev_dbg(dev, "set pin %d output %d\n", pin, arg); + clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); + if (arg) + setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio)); + else + clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio)); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + dev_dbg(dev, "set pin %d push pull\n", pin); + clrbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio)); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + dev_dbg(dev, "set pin %d open drain\n", pin); + setbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio)); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + dev_dbg(dev, "set pin %d input debounce\n", pin); + setbits_le32(base + NPCM7XX_GP_N_DBNC, BIT(gpio)); + break; + case PIN_CONFIG_POLARITY_STATE: + dev_dbg(dev, "set pin %d active %d\n", pin, arg); + if (arg) + setbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio)); + else + clrbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio)); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + dev_dbg(dev, "set pin %d driver strength %d\n", pin, arg); + err = npcm7xx_set_drive_strength(dev, pin, arg); + break; + case PIN_CONFIG_SLEW_RATE: + dev_dbg(dev, "set pin %d slew rate %d\n", pin, arg); + err = npcm7xx_set_slew_rate(dev, pin, arg); + break; + default: + err = -ENOTSUPP; + } + return err; +} + +#endif + +static struct pinctrl_ops npcm7xx_pinctrl_ops = { + .set_state = pinctrl_generic_set_state, + .get_pins_count = npcm7xx_get_pins_count, + .get_pin_name = npcm7xx_get_pin_name, + .get_groups_count = npcm7xx_get_groups_count, + .get_group_name = npcm7xx_get_group_name, + .get_functions_count = npcm7xx_get_functions_count, + .get_function_name = npcm7xx_get_function_name, + .pinmux_set = npcm7xx_pinmux_set, + .pinmux_group_set = npcm7xx_pinmux_set, +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(npcm7xx_conf_params), + .pinconf_params = npcm7xx_conf_params, + .pinconf_set = npcm7xx_pinconf_set, + .pinconf_group_set = npcm7xx_pinconf_set, +#endif +}; + +static const struct udevice_id npcm7xx_pinctrl_ids[] = { + { .compatible = "nuvoton,npcm750-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_npcm7xx) = { + .name = "nuvoton_npcm7xx_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = npcm7xx_pinctrl_ids, + .priv_auto = sizeof(struct npcm7xx_pinctrl_priv), + .ops = &npcm7xx_pinctrl_ops, + .probe = npcm7xx_pinctrl_probe, +}; diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7c5a02db1b98ae3c6e70e5304a53ac52f308c8fb..52d428f566fc754acf8cd3a3c0e672d948861c02 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -467,6 +467,10 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, pin); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_ENABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; case PIN_CONFIG_LOW_POWER_MODE: /* * This cases are mentioned in dts but configurable @@ -475,6 +479,11 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, */ ret = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; default: dev_warn(dev, "unsupported configuration parameter '%u'\n", param); diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 56a20e8bd25fd4730432291487093508b62b7c5a..990cd19286fcfd2cfd8593996cb791065b7186d6 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -488,6 +488,7 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32h743-pinctrl" }, { .compatible = "st,stm32mp157-pinctrl" }, { .compatible = "st,stm32mp157-z-pinctrl" }, + { .compatible = "st,stm32mp135-pinctrl" }, { } }; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 2c20dc7c8318f2470326d9abd7553c6ccbb147f1..bc47cf144dd0885f8c31c64e470d8cb45d101b37 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -29,6 +29,7 @@ config POWER_LEGACY config SPL_POWER_LEGACY bool "Legacy power support in SPL" + depends on SPL && !SPL_DM_PMIC default y if POWER_LEGACY help Note: This is a legacy option. Use SPL_DM_PMIC instead. @@ -425,6 +426,10 @@ config POWER_MT6323 This adds poweroff driver for mt6323 this pmic is used on mt7623 / Bananapi R2 +config PALMAS_POWER + bool "Palmas power support" + depends on OMAP54XX + config POWER_I2C bool "I2C-based power control for legacy power" depends on POWER_LEGACY diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig index fcd50e36cad424cdd1cc73863fc9f0f7324f96e0..629acb071427bfc6dd1d3b3fb1c1913e0f8bf846 100644 --- a/drivers/power/acpi_pmc/Kconfig +++ b/drivers/power/acpi_pmc/Kconfig @@ -8,6 +8,7 @@ config ACPI_PMC config SPL_ACPI_PMC bool "Power Manager (x86 PMC) support in SPL" + depends on SPL default y if ACPI_PMC help Enable support for an x86-style power-management controller which @@ -17,6 +18,7 @@ config SPL_ACPI_PMC config TPL_ACPI_PMC bool "Power Manager (x86 PMC) support in TPL" + depends on TPL default y if ACPI_PMC help Enable support for an x86-style power-management controller which diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 292fff0dfbf28bcad83873dc1e36210dcb70c1e8..a7f64d04f5c20c7272a28f1bc4708b5c2f5584a7 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -86,6 +86,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .family = "J721S2", .data = &j721s2_pd_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_AM625 + { + .family = "AM62X", + .data = &am62x_pd_platdata, + }, #endif { /* sentinel */ } }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index d6cea8ec6667cc0a5a501237d0d5b1376f6d0186..c519e066ef028503d2c10822148308a5a27b25e6 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -55,7 +55,7 @@ config DM_REGULATOR_BD71837 config SPL_DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL" - depends on DM_REGULATOR_BD71837 + depends on DM_REGULATOR_BD71837 && SPL help This config enables implementation of driver-model regulator uclass features for regulators on ROHM BD71837 and BD71847 in SPL. @@ -70,7 +70,7 @@ config DM_REGULATOR_PCA9450 config SPL_DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators in SPL" - depends on DM_REGULATOR_PCA9450 + depends on DM_REGULATOR_PCA9450 && SPL help This config enables implementation of driver-model regulator uclass features for regulators on ROHM PCA9450 in SPL. @@ -115,7 +115,7 @@ config REGULATOR_PWM config SPL_REGULATOR_PWM bool "Enable Driver for PWM regulators in SPL" - depends on REGULATOR_PWM + depends on REGULATOR_PWM && SPL help This config enables implementation of driver-model regulator uclass features for PWM regulators in SPL. @@ -163,7 +163,7 @@ config DM_REGULATOR_FIXED config SPL_DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value in SPL" - depends on DM_REGULATOR_FIXED + depends on DM_REGULATOR_FIXED && SPL select SPL_DM_REGULATOR_COMMON ---help--- This config enables implementation of driver-model regulator uclass @@ -345,7 +345,7 @@ config SPL_DM_REGULATOR_STPMIC1 config SPL_DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" - depends on SPL_PMIC_PALMAS + depends on SPL_PMIC_PALMAS help This enables implementation of driver-model regulator uclass features for REGULATOR PALMAS and the family of PALMAS PMICs. @@ -353,7 +353,7 @@ config SPL_DM_REGULATOR_PALMAS config SPL_DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" - depends on SPL_PMIC_LP87565 + depends on SPL_PMIC_LP87565 help This enables implementation of driver-model regulator uclass features for REGULATOR LP87565 and the family of LP87565 PMICs. diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 2966bdcf830f80fef0c853436a917af45bcd5824..801148036ff6cf1adeaeffc0e61092f293d72b94 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020-2021 Linaro Limited + * Copyright (C) 2020-2022 Linaro Limited */ #define LOG_CATEGORY UCLASS_REGULATOR @@ -25,9 +25,18 @@ struct scmi_regulator_platdata { u32 domain_id; }; +/** + * struct scmi_regulator_priv - Private data for SCMI voltage regulator + * @channel: Reference to the SCMI channel to use + */ +struct scmi_regulator_priv { + struct scmi_channel *channel; +}; + static int scmi_voltd_set_enable(struct udevice *dev, bool enable) { struct scmi_regulator_platdata *pdata = dev_get_plat(dev); + struct scmi_regulator_priv *priv = dev_get_priv(dev); struct scmi_voltd_config_set_in in = { .domain_id = pdata->domain_id, .config = enable ? SCMI_VOLTD_CONFIG_ON : SCMI_VOLTD_CONFIG_OFF, @@ -38,20 +47,17 @@ static int scmi_voltd_set_enable(struct udevice *dev, bool enable) in, out); int ret; - ret = devm_scmi_process_msg(dev, &msg); - if (ret) - return ret; - - ret = scmi_to_linux_errno(out.status); + ret = devm_scmi_process_msg(dev, priv->channel, &msg); if (ret) return ret; - return ret; + return scmi_to_linux_errno(out.status); } static int scmi_voltd_get_enable(struct udevice *dev) { struct scmi_regulator_platdata *pdata = dev_get_plat(dev); + struct scmi_regulator_priv *priv = dev_get_priv(dev); struct scmi_voltd_config_get_in in = { .domain_id = pdata->domain_id, }; @@ -61,7 +67,7 @@ static int scmi_voltd_get_enable(struct udevice *dev) in, out); int ret; - ret = devm_scmi_process_msg(dev, &msg); + ret = devm_scmi_process_msg(dev, priv->channel, &msg); if (ret < 0) return ret; @@ -74,6 +80,7 @@ static int scmi_voltd_get_enable(struct udevice *dev) static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV) { + struct scmi_regulator_priv *priv = dev_get_priv(dev); struct scmi_regulator_platdata *pdata = dev_get_plat(dev); struct scmi_voltd_level_set_in in = { .domain_id = pdata->domain_id, @@ -85,7 +92,7 @@ static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV) in, out); int ret; - ret = devm_scmi_process_msg(dev, &msg); + ret = devm_scmi_process_msg(dev, priv->channel, &msg); if (ret < 0) return ret; @@ -94,6 +101,7 @@ static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV) static int scmi_voltd_get_voltage_level(struct udevice *dev) { + struct scmi_regulator_priv *priv = dev_get_priv(dev); struct scmi_regulator_platdata *pdata = dev_get_plat(dev); struct scmi_voltd_level_get_in in = { .domain_id = pdata->domain_id, @@ -104,7 +112,7 @@ static int scmi_voltd_get_voltage_level(struct udevice *dev) in, out); int ret; - ret = devm_scmi_process_msg(dev, &msg); + ret = devm_scmi_process_msg(dev, priv->channel, &msg); if (ret < 0) return ret; @@ -132,6 +140,7 @@ static int scmi_regulator_of_to_plat(struct udevice *dev) static int scmi_regulator_probe(struct udevice *dev) { struct scmi_regulator_platdata *pdata = dev_get_plat(dev); + struct scmi_regulator_priv *priv = dev_get_priv(dev); struct scmi_voltd_attr_in in = { 0 }; struct scmi_voltd_attr_out out = { 0 }; struct scmi_msg scmi_msg = { @@ -144,10 +153,14 @@ static int scmi_regulator_probe(struct udevice *dev) }; int ret; + ret = devm_scmi_of_get_channel(dev->parent, &priv->channel); + if (ret) + return ret; + /* Check voltage domain is known from SCMI server */ in.domain_id = pdata->domain_id; - ret = devm_scmi_process_msg(dev, &scmi_msg); + ret = devm_scmi_process_msg(dev, priv->channel, &scmi_msg); if (ret) { dev_err(dev, "Failed to query voltage domain %u: %d\n", pdata->domain_id, ret); @@ -171,6 +184,7 @@ U_BOOT_DRIVER(scmi_regulator) = { .probe = scmi_regulator_probe, .of_to_plat = scmi_regulator_of_to_plat, .plat_auto = sizeof(struct scmi_regulator_platdata), + .priv_auto = sizeof(struct scmi_regulator_priv *), }; static int scmi_regulator_bind(struct udevice *dev) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cb54e67faebfb33b77f1308a9b9334a1b8fe2a1b..8fd5a2e205192c35300f3695a6ff0b4acd3c47d0 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -84,6 +84,11 @@ config PWM_SANDBOX useful. The PWM can be enabled but is not connected to any outputs so this is not very useful. +config PWM_S5P + bool "Enable non-DM support for S5P PWM" + depends on (S5P || ARCH_NEXELL) + default y + config PWM_SIFIVE bool "Enable support for SiFive PWM" depends on DM_PWM diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 709c916a2a112bca623e9f657ae01bfb4c21ca33..7c346180baef5a88d425e71aeaec734a431b4354 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -19,7 +19,7 @@ config SPL_RAM config TPL_RAM bool "Enable RAM support in TPL" - depends on RAM + depends on RAM && TPL help The RAM subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use RAM drivers in @@ -64,6 +64,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 + default K3_AM64_DDRSS if SOC_K3_AM625 config K3_J721E_DDRSS bool "Enable J721E DDRSS support" diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 49b1262461be323d6f40fa61e4f27f321cb3de0c..a6c19af9722001f3156c53289b31cdf979481e4d 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -230,29 +230,29 @@ static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width) reg = readl(&ctl->addrmap3); /* addrmap3.addrmap_col_b6 */ - val = (reg & GENMASK(3, 0)) >> 0; + val = (reg & GENMASK(4, 0)) >> 0; if (val <= 7) bits++; /* addrmap3.addrmap_col_b7 */ - val = (reg & GENMASK(11, 8)) >> 8; + val = (reg & GENMASK(12, 8)) >> 8; if (val <= 7) bits++; /* addrmap3.addrmap_col_b8 */ - val = (reg & GENMASK(19, 16)) >> 16; + val = (reg & GENMASK(20, 16)) >> 16; if (val <= 7) bits++; /* addrmap3.addrmap_col_b9 */ - val = (reg & GENMASK(27, 24)) >> 24; + val = (reg & GENMASK(28, 24)) >> 24; if (val <= 7) bits++; reg = readl(&ctl->addrmap4); /* addrmap4.addrmap_col_b10 */ - val = (reg & GENMASK(3, 0)) >> 0; + val = (reg & GENMASK(4, 0)) >> 0; if (val <= 7) bits++; /* addrmap4.addrmap_col_b11 */ - val = (reg & GENMASK(11, 8)) >> 8; + val = (reg & GENMASK(12, 8)) >> 8; if (val <= 7) bits++; @@ -296,21 +296,24 @@ static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) reg = readl(&ctl->addrmap6); /* addrmap6.addrmap_row_b12 */ val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 7) + if (val <= 11) bits++; /* addrmap6.addrmap_row_b13 */ val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 7) + if (val <= 11) bits++; /* addrmap6.addrmap_row_b14 */ val = (reg & GENMASK(19, 16)) >> 16; - if (val <= 7) + if (val <= 11) bits++; /* addrmap6.addrmap_row_b15 */ val = (reg & GENMASK(27, 24)) >> 24; - if (val <= 7) + if (val <= 11) bits++; + if (reg & BIT(31)) + printf("warning: LPDDR3_6GB_12GB is not supported\n"); + return bits; } @@ -392,12 +395,17 @@ static struct ram_ops stm32mp1_ddr_ops = { .get_info = stm32mp1_ddr_get_info, }; +static const struct stm32mp1_ddr_cfg stm32mp13x_ddr_cfg = { + .nb_bytes = 2, +}; + static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = { .nb_bytes = 4, }; static const struct udevice_id stm32mp1_ddr_ids[] = { { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg}, + { .compatible = "st,stm32mp13-ddr", .data = (ulong)&stm32mp13x_ddr_cfg}, { } }; diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index 0a1dd236aff3c2e5559936955d9d54afd05b50da..d9cecf3a72e8aa59ad704654aac0dfc8a0145b8f 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl *reset_ctl) return 0; } +static int ast2500_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2500_scu *scu = priv->scu; + int status; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1); + else + status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2); + + return !!status; +} + + + static int ast2500_reset_probe(struct udevice *dev) { int rc; @@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = { struct reset_ops ast2500_reset_ops = { .rst_assert = ast2500_reset_assert, .rst_deassert = ast2500_reset_deassert, + .rst_status = ast2500_reset_status, }; U_BOOT_DRIVER(ast2500_reset) = { diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index 985235a3ac461f8394246c152de5b15be0f65b26..1732a450efc07a16569ca83578a2c323a87ad710 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl *reset_ctl) return 0; } +static int ast2600_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2600_scu *scu = priv->scu; + int status; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1); + else + status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2); + + return !!status; +} + static int ast2600_reset_probe(struct udevice *dev) { int rc; @@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = { struct reset_ops ast2600_reset_ops = { .rst_assert = ast2600_reset_assert, .rst_deassert = ast2600_reset_deassert, + .rst_status = ast2600_reset_status, }; U_BOOT_DRIVER(ast2600_reset) = { diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c index 81d195a06a9630d0ae293008f8aa571feeb02e41..122556162ec3be967683b7d634a0d90c6afa40aa 100644 --- a/drivers/reset/reset-scmi.c +++ b/drivers/reset/reset-scmi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019-2020 Linaro Limited + * Copyright (C) 2019-2022 Linaro Limited */ #define LOG_CATEGORY UCLASS_RESET @@ -13,8 +13,17 @@ #include #include +/** + * struct scmi_reset_priv - Private data for SCMI reset controller + * @channel: Reference to the SCMI channel to use + */ +struct scmi_reset_priv { + struct scmi_channel *channel; +}; + static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert) { + struct scmi_reset_priv *priv = dev_get_priv(rst->dev); struct scmi_rd_reset_in in = { .domain_id = rst->id, .flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0, @@ -26,7 +35,7 @@ static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert) in, out); int ret; - ret = devm_scmi_process_msg(rst->dev, &msg); + ret = devm_scmi_process_msg(rst->dev, priv->channel, &msg); if (ret) return ret; @@ -45,6 +54,7 @@ static int scmi_reset_deassert(struct reset_ctl *rst) static int scmi_reset_request(struct reset_ctl *rst) { + struct scmi_reset_priv *priv = dev_get_priv(rst->dev); struct scmi_rd_attr_in in = { .domain_id = rst->id, }; @@ -58,7 +68,7 @@ static int scmi_reset_request(struct reset_ctl *rst) * We don't really care about the attribute, just check * the reset domain exists. */ - ret = devm_scmi_process_msg(rst->dev, &msg); + ret = devm_scmi_process_msg(rst->dev, priv->channel, &msg); if (ret) return ret; @@ -71,8 +81,17 @@ static const struct reset_ops scmi_reset_domain_ops = { .rst_deassert = scmi_reset_deassert, }; +static int scmi_reset_probe(struct udevice *dev) +{ + struct scmi_reset_priv *priv = dev_get_priv(dev); + + return devm_scmi_of_get_channel(dev, &priv->channel); +} + U_BOOT_DRIVER(scmi_reset_domain) = { .name = "scmi_reset_domain", .id = UCLASS_RESET, .ops = &scmi_reset_domain_ops, + .probe = scmi_reset_probe, + .priv_auto = sizeof(struct scmi_reset_priv *), }; diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index c10f7d345bdafdb9546dc98ad08793961bb7f3c2..21a9ff01954279abffb491a5995232871a6a9c6b 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -31,6 +31,13 @@ config RNG_MSM This driver provides support for the Random Number Generator hardware found on Qualcomm SoCs. +config RNG_NPCM + bool "Nuvoton NPCM SoCs Random Number Generator support" + depends on DM_RNG + help + Enable random number generator on NPCM SoCs. + This unit can provide 750 to 1000 random bits per second + config RNG_OPTEE bool "OP-TEE based Random Number Generator support" depends on DM_RNG && OPTEE @@ -58,4 +65,13 @@ config RNG_IPROC200 depends on DM_RNG help Enable random number generator for RPI4. + +config RNG_SMCCC_TRNG + bool "Arm SMCCC TRNG interface" + depends on DM_RNG && ARM_PSCI_FW + default y if ARM_SMCCC_FEATURES + help + Enable random number generator for platforms that support Arm + SMCCC TRNG interface. + endif diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 435b3b965adbd6f0ccc0bb2226871f6b9d848f50..2494717d7c756b5e074a996a07a47e92a067e708 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -7,7 +7,9 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o obj-$(CONFIG_RNG_MESON) += meson-rng.o obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o obj-$(CONFIG_RNG_MSM) += msm_rng.o +obj-$(CONFIG_RNG_NPCM) += npcm_rng.o obj-$(CONFIG_RNG_OPTEE) += optee_rng.o obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o +obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o diff --git a/drivers/rng/npcm_rng.c b/drivers/rng/npcm_rng.c new file mode 100644 index 0000000000000000000000000000000000000000..70c1c032b6d31d56b8a1299171217cfaec091863 --- /dev/null +++ b/drivers/rng/npcm_rng.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include + +#define RNGCS_RNGE BIT(0) +#define RNGCS_DVALID BIT(1) +#define RNGCS_CLKP(range) ((0x0f & (range)) << 2) +#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */ + +enum { + RNG_CLKP_80_100_MHZ = 0x00, /*default */ + RNG_CLKP_60_80_MHZ = 0x01, + RNG_CLKP_50_60_MHZ = 0x02, + RNG_CLKP_40_50_MHZ = 0x03, + RNG_CLKP_30_40_MHZ = 0x04, + RNG_CLKP_25_30_MHZ = 0x05, + RNG_CLKP_20_25_MHZ = 0x06, + RNG_CLKP_5_20_MHZ = 0x07, + RNG_CLKP_2_15_MHZ = 0x08, + RNG_CLKP_9_12_MHZ = 0x09, + RNG_CLKP_7_9_MHZ = 0x0A, + RNG_CLKP_6_7_MHZ = 0x0B, + RNG_CLKP_5_6_MHZ = 0x0C, + RNG_CLKP_4_5_MHZ = 0x0D, + RNG_CLKP_3_4_MHZ = 0x0E, + RNG_NUM_OF_CLKP +}; + +struct npcm_rng_regs { + unsigned int rngcs; + unsigned int rngd; + unsigned int rngmode; +}; + +struct npcm_rng_priv { + struct npcm_rng_regs *regs; +}; + +static struct npcm_rng_priv *rng_priv; + +void npcm_rng_init(void) +{ + struct npcm_rng_regs *regs = rng_priv->regs; + int init; + + /* check if rng enabled */ + init = readb(®s->rngcs); + if ((init & RNGCS_RNGE) == 0) { + /* init rng */ + writeb(RNGCS_CLKP(RNG_CLKP_20_25_MHZ) | RNGCS_RNGE, ®s->rngcs); + writeb(RNGMODE_M1ROSEL_VAL, ®s->rngmode); + } +} + +void npcm_rng_disable(void) +{ + struct npcm_rng_regs *regs = rng_priv->regs; + + /* disable rng */ + writeb(0, ®s->rngcs); + writeb(0, ®s->rngmode); +} + +void srand(unsigned int seed) +{ + /* no need to seed for now */ +} + +int npcm_rng_read(struct udevice *dev, void *data, size_t max) +{ + struct npcm_rng_regs *regs = rng_priv->regs; + int i; + int ret_val = 0; + char *buf = data; + + npcm_rng_init(); + + printf("NPCM HW RNG\n"); + /* Wait for RNG done (max bytes) */ + for (i = 0; i < max; i++) { + /* wait until DVALID is set */ + while ((readb(®s->rngcs) & RNGCS_DVALID) == 0) + ; + buf[i] = ((unsigned int)readb(®s->rngd) & 0x000000FF); + } + + return ret_val; +} + +unsigned int rand_r(unsigned int *seedp) +{ + struct npcm_rng_regs *regs = rng_priv->regs; + int i; + unsigned int ret_val = 0; + + npcm_rng_init(); + + /* Wait for RNG done (4 bytes) */ + for (i = 0; i < 4 ; i++) { + /* wait until DVALID is set */ + while ((readb(®s->rngcs) & RNGCS_DVALID) == 0) + ; + ret_val |= (((unsigned int)readb(®s->rngd) & 0x000000FF) << (i * 8)); + } + + return ret_val; +} + +unsigned int rand(void) +{ + return rand_r(NULL); +} + +static int npcm_rng_bind(struct udevice *dev) +{ + rng_priv = calloc(1, sizeof(struct npcm_rng_priv)); + if (!rng_priv) + return -ENOMEM; + + rng_priv->regs = dev_remap_addr_index(dev, 0); + if (!rng_priv->regs) { + printf("Cannot find rng reg address, binding failed\n"); + return -EINVAL; + } + + printf("RNG: NPCM RNG module bind OK\n"); + + return 0; +} + +static const struct udevice_id npcm_rng_ids[] = { + { .compatible = "nuvoton,npcm845-rng" }, + { .compatible = "nuvoton,npcm750-rng" }, + { } +}; + +static const struct dm_rng_ops npcm_rng_ops = { + .read = npcm_rng_read, +}; + +U_BOOT_DRIVER(npcm_rng) = { + .name = "npcm_rng", + .id = UCLASS_RNG, + .ops = &npcm_rng_ops, + .of_match = npcm_rng_ids, + .priv_auto = sizeof(struct npcm_rng_priv), + .bind = npcm_rng_bind, +}; diff --git a/drivers/rng/smccc_trng.c b/drivers/rng/smccc_trng.c new file mode 100644 index 0000000000000000000000000000000000000000..3a4bb3394159b5a912b772fc903fb60b34bbd7c8 --- /dev/null +++ b/drivers/rng/smccc_trng.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_RNG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "smccc-trng" + +/** + * Arm SMCCC TRNG firmware interface specification: + * https://developer.arm.com/documentation/den0098/latest/ + */ +#define ARM_SMCCC_TRNG_VERSION 0x84000050 +#define ARM_SMCCC_TRNG_FEATURES 0x84000051 +#define ARM_SMCCC_TRNG_GET_UUID 0x84000052 +#define ARM_SMCCC_TRNG_RND_32 0x84000053 +#define ARM_SMCCC_TRNG_RND_64 0xC4000053 + +#define ARM_SMCCC_RET_TRNG_SUCCESS ((ulong)0) +#define ARM_SMCCC_RET_TRNG_NOT_SUPPORTED ((ulong)-1) +#define ARM_SMCCC_RET_TRNG_INVALID_PARAMETER ((ulong)-2) +#define ARM_SMCCC_RET_TRNG_NO_ENTROPY ((ulong)-3) + +#define TRNG_MAJOR_MASK GENMASK(30, 16) +#define TRNG_MAJOR_SHIFT 16 +#define TRNG_MINOR_MASK GENMASK(15, 0) +#define TRNG_MINOR_SHIFT 0 + +#define TRNG_MAX_RND_64 (192 / 8) +#define TRNG_MAX_RND_32 (96 / 8) + +/** + * struct smccc_trng_priv - Private data for SMCCC TRNG support + * + * @smc64 - True if TRNG_RND_64 is supported, false if TRNG_RND_32 is supported + */ +struct smccc_trng_priv { + bool smc64; +}; + +/* + * Copy random bytes from ulong SMCCC output register to target buffer + * Defines 2 function flavors for whether ARM_SMCCC_TRNG_RND_32 or + * ARM_SMCCC_TRNG_RND_64 was used to invoke the service. + */ +static size_t smc32_copy_sample(u8 **ptr, size_t size, ulong *rnd) +{ + size_t len = min(size, sizeof(u32)); + u32 sample = *rnd; + + memcpy(*ptr, &sample, len); + *ptr += len; + + return size - len; +} + +static size_t smc64_copy_sample(u8 **ptr, size_t size, ulong *rnd) +{ + size_t len = min(size, sizeof(u64)); + u64 sample = *rnd; + + memcpy(*ptr, &sample, len); + *ptr += len; + + return size - len; +} + +static int smccc_trng_read(struct udevice *dev, void *data, size_t len) +{ + struct psci_plat_data *smccc = dev_get_parent_plat(dev); + struct smccc_trng_priv *priv = dev_get_priv(dev); + struct arm_smccc_res res; + u32 func_id; + u8 *ptr = data; + size_t rem = len; + size_t max_sz; + size_t (*copy_sample)(u8 **ptr, size_t size, ulong *rnd); + + if (priv->smc64) { + copy_sample = smc64_copy_sample; + func_id = ARM_SMCCC_TRNG_RND_64; + max_sz = TRNG_MAX_RND_64; + } else { + copy_sample = smc32_copy_sample; + func_id = ARM_SMCCC_TRNG_RND_32; + max_sz = TRNG_MAX_RND_32; + } + + while (rem) { + size_t sz = min(rem, max_sz); + + smccc->invoke_fn(func_id, sz * 8, 0, 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case ARM_SMCCC_RET_TRNG_SUCCESS: + break; + case ARM_SMCCC_RET_TRNG_NO_ENTROPY: + continue; + default: + return -EIO; + } + + rem -= sz; + + sz = copy_sample(&ptr, sz, &res.a3); + if (sz) + sz = copy_sample(&ptr, sz, &res.a2); + if (sz) + sz = copy_sample(&ptr, sz, &res.a1); + } + + return 0; +} + +static const struct dm_rng_ops smccc_trng_ops = { + .read = smccc_trng_read, +}; + +static bool smccc_trng_is_supported(void (*invoke_fn)(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res)) +{ + struct arm_smccc_res res; + + (*invoke_fn)(ARM_SMCCC_ARCH_FEATURES, ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 == ARM_SMCCC_RET_NOT_SUPPORTED) + return false; + + (*invoke_fn)(ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 & BIT(31)) + return false; + + /* Test 64bit interface and fallback to 32bit interface */ + invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_64, + 0, 0, 0, 0, 0, 0, &res); + + if (res.a0 == ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) + invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_32, + 0, 0, 0, 0, 0, 0, &res); + + return res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS; +} + +ARM_SMCCC_FEATURE_DRIVER(smccc_trng) = { + .driver_name = DRIVER_NAME, + .is_supported = smccc_trng_is_supported, +}; + +static int smccc_trng_probe(struct udevice *dev) +{ + struct psci_plat_data *smccc = dev_get_parent_plat(dev); + struct smccc_trng_priv *priv = dev_get_priv(dev); + struct arm_smccc_res res; + + if (!(smccc_trng_is_supported(smccc->invoke_fn))) + return -ENODEV; + + /* At least one of 64bit and 32bit interfaces is available */ + smccc->invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_64, + 0, 0, 0, 0, 0, 0, &res); + priv->smc64 = (res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS); + +#ifdef DEBUG + smccc->invoke_fn(ARM_SMCCC_TRNG_GET_UUID, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) { + unsigned long uuid_a0 = res.a0; + unsigned long uuid_a1 = res.a1; + unsigned long uuid_a2 = res.a2; + unsigned long uuid_a3 = res.a3; + unsigned long major, minor; + + smccc->invoke_fn(ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + major = (res.a0 & TRNG_MAJOR_MASK) >> TRNG_MAJOR_SHIFT; + minor = (res.a0 & TRNG_MINOR_MASK) >> TRNG_MINOR_SHIFT; + + dev_dbg(dev, "Version %lu.%lu, UUID %08lx-%04lx-%04lx-%04lx-%04lx%08lx\n", + major, minor, uuid_a0, uuid_a1 >> 16, uuid_a1 & GENMASK(16, 0), + uuid_a2 >> 16, uuid_a2 & GENMASK(16, 0), uuid_a3); + } else { + dev_warn(dev, "Can't get TRNG UUID\n"); + } +#endif + + return 0; +} + +U_BOOT_DRIVER(smccc_trng) = { + .name = DRIVER_NAME, + .id = UCLASS_RNG, + .ops = &smccc_trng_ops, + .probe = smccc_trng_probe, + .priv_auto = sizeof(struct smccc_trng_priv), +}; diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index ba418c25daf6b99fa6b692ca9decdba7294010a3..c307d6036dd5b87ca4fc256a47d3938ccdbb980e 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -203,6 +203,15 @@ static int sandbox_i2c_rtc_bind(struct udevice *dev) return 0; } +static int sandbox_i2c_rtc_probe(struct udevice *dev) +{ + const u8 mac[] = { 0x02, 0x00, 0x11, 0x22, 0x33, 0x48 }; + struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev); + + memcpy(&plat->reg[0x40], mac, sizeof(mac)); + return 0; +} + static const struct udevice_id sandbox_i2c_rtc_ids[] = { { .compatible = "sandbox,i2c-rtc-emul" }, { } @@ -213,6 +222,7 @@ U_BOOT_DRIVER(sandbox_i2c_rtc_emul) = { .id = UCLASS_I2C_EMUL, .of_match = sandbox_i2c_rtc_ids, .bind = sandbox_i2c_rtc_bind, + .probe = sandbox_i2c_rtc_probe, .priv_auto = sizeof(struct sandbox_i2c_rtc), .plat_auto = sizeof(struct sandbox_i2c_rtc_plat_data), .ops = &sandbox_i2c_rtc_emul_ops, diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 45c284a408d82fb3152f7600f813f83b5bc8f422..de02e08a299620e8ccd779d1f8c37f2aa49933c4 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -476,6 +476,8 @@ config DEBUG_UART_BASE depends on DEBUG_UART default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX + default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP + default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ help This is the base address of your UART for memory-mapped UARTs. @@ -502,6 +504,8 @@ config DEBUG_UART_CLOCK default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX default 0 if DEBUG_MVEBU_A3700_UART + default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP + default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input @@ -936,12 +940,6 @@ config OWL_SERIAL serial port, say Y to this option. If unsure, say N. Single baudrate is supported in current implementation (115200). -config PXA_SERIAL - bool "PXA serial port support" - help - If you have a machine based on a Marvell XScale PXA2xx CPU you - can enable its onboard serial ports by enabling this option. - config HTIF_CONSOLE bool "RISC-V HTIF console support" depends on DM_SERIAL && 64BIT diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 51de06a78c58107997a39cd72cfc7b2b39227c4e..eb7b8f23ee904a30fe5a6f1ae4459cc9f3be1311 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -43,7 +43,6 @@ obj-$(CONFIG_MCFUART) += serial_mcf.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o obj-$(CONFIG_MXC_UART) += serial_mxc.o -obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o obj-$(CONFIG_MESON_SERIAL) += serial_meson.o obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 4435fcf56b9a329d0e594180b4273b1669d8b035..9e39da7dd24619ca84a9e899dc200e5d69a7b43f 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -134,7 +134,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; + struct altera_jtaguart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); while (1) { u32 st = readl(®s->control); diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index b18be6e245490ab65cdc6c707a6594e13d2bc977..35920480841a8beffa5ea6a26bb2bdc9476e18c9 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -123,7 +123,7 @@ U_BOOT_DRIVER(altera_uart) = { static inline void _debug_uart_init(void) { - struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; + struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); u32 div; div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1; @@ -132,7 +132,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; + struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); while (1) { u32 st = readl(®s->status); diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index bd14f3e78192edcb48d4a7dc5b3b12f724f6cfb6..1fb9ee5cc94a34a47ade95a8667b684446550539 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -319,14 +319,14 @@ U_BOOT_DRIVER(serial_atmel) = { #ifdef CONFIG_DEBUG_UART_ATMEL static inline void _debug_uart_init(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); } static inline void _debug_uart_putc(int ch) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); while (!(readl(&usart->csr) & USART3_BIT(TXRDY))) ; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 78bfe6281ce3fd4920276ddb517bd794c3bfaebf..47bad6f8e2a9613f97e3c3756de0a6c5f09590e1 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -328,6 +328,10 @@ static inline void _debug_uart_init(void) struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); int baud_divisor; + /* Wait until tx buffer is empty */ + while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT)) + ; + /* * We copy the code from above because it is already horribly messy. * Trying to refactor to nicely remove the duplication doesn't seem diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index e726e19c46f7bd288968da8d58d91a77117786a6..13b54921c419be21cc07458287e4cc8d8a7579ac 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -114,7 +114,7 @@ static ssize_t sandbox_serial_puts(struct udevice *dev, const char *s, struct sandbox_serial_priv *priv = dev_get_priv(dev); ssize_t ret; - if (s[len - 1] == '\n') + if (len && s[len - 1] == '\n') priv->start_of_line = true; if (sandbox_serial_enabled) { diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index da06bef97c77a0ac9838a84d70fc93ca69f59d89..4f9163497626f9cfea1a2c4c350c8311c355da36 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_ar933x) = { static inline void _debug_uart_init(void) { - void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; + void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); u32 val, scale, step; /* @@ -227,7 +227,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int c) { - void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; + void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); u32 data; do { diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 8f3e4dd44f15352447ba1f695d3024d7c747bfac..b2d95bdbe18df60561c7130a39fc27a31cdc6df4 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -137,7 +137,7 @@ U_BOOT_DRIVER(serial_arc) = { static inline void _debug_uart_init(void) { - struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE; + struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE); int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1; writeb(arc_console_baud & 0xff, ®s->baudl); @@ -146,7 +146,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int c) { - struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE; + struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE); while (!(readb(®s->status) & UART_TXEMPTY)) ; diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c index f08e91ff3ba4525aeb281731aad4eab645b13a16..2359656a239a5b39f8499d6d2eff2fefa2b11288 100644 --- a/drivers/serial/serial_bcm6345.c +++ b/drivers/serial/serial_bcm6345.c @@ -269,7 +269,7 @@ U_BOOT_DRIVER(bcm6345_serial) = { #ifdef CONFIG_DEBUG_UART_BCM6345 static inline void _debug_uart_init(void) { - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); } @@ -285,7 +285,7 @@ static inline void wait_xfered(void __iomem *base) static inline void _debug_uart_putc(int ch) { - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); wait_xfered(base); writel(ch, base + UART_FIFO_REG); diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c index 876a4baa9fc6bbc70e6c7147aab3c29447539995..b449e55a6506fb5a92fd6ef1bc2441a985fd5dcb 100644 --- a/drivers/serial/serial_linflexuart.c +++ b/drivers/serial/serial_linflexuart.c @@ -201,14 +201,14 @@ U_BOOT_DRIVER(serial_linflex) = { static inline void _debug_uart_init(void) { - struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE; + struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); linflex_serial_init_internal(base); } static inline void _debug_uart_putc(int ch) { - struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE; + struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); /* XXX: Is this OK? Should this use the non-DM version? */ _linflex_serial_putc(base, ch); diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index d69ec221e4567800cbe95b1075b3d61260475c00..c5ed3ede45edd166c5fa815b40f5f11dd796d4ac 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c @@ -182,7 +182,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE; + struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE); while (readl(®s->status) & AML_UART_TX_FULL) ; diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 3e255a99dccaf12df0a120fce04778f16d3eda96..3943ca43e49e8068493f4689ccacc2a1463f5a07 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -569,7 +569,7 @@ U_BOOT_DRIVER(serial_msm_geni) = { #ifdef CONFIG_DEBUG_UART_MSM_GENI static struct msm_serial_data init_serial_data = { - .base = CONFIG_DEBUG_UART_BASE + .base = CONFIG_VAL(DEBUG_UART_BASE) }; /* Serial dumb device, to reuse driver code */ @@ -587,7 +587,7 @@ static struct udevice init_dev = { static inline void _debug_uart_init(void) { - phys_addr_t base = CONFIG_DEBUG_UART_BASE; + phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); geni_serial_init(&init_dev); geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); @@ -596,7 +596,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - phys_addr_t base = CONFIG_DEBUG_UART_BASE; + phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); qcom_geni_serial_setup_tx(base, 1); diff --git a/drivers/serial/serial_mt7620.c b/drivers/serial/serial_mt7620.c index 76ecc2b38ce6e7c8e63aa9178a36e3f61bcdc529..5c5264bc962927589f3c6813f8747fa094d3680c 100644 --- a/drivers/serial/serial_mt7620.c +++ b/drivers/serial/serial_mt7620.c @@ -220,7 +220,7 @@ static inline void _debug_uart_init(void) { struct mt7620_serial_plat plat; - plat.regs = (void *)CONFIG_DEBUG_UART_BASE; + plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); plat.clock = CONFIG_DEBUG_UART_CLOCK; writel(0, &plat.regs->ier); @@ -233,7 +233,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { struct mt7620_serial_regs __iomem *regs = - (void *)CONFIG_DEBUG_UART_BASE; + (void *)CONFIG_VAL(DEBUG_UART_BASE); while (!(readl(®s->lsr) & UART_LSR_THRE)) ; diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 4145d9fdb3d3daa1ff225f9015a68a6f757b0d30..a84f39b3fa2ea1396b6a425590a54a93885ff113 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -426,7 +426,7 @@ static inline void _debug_uart_init(void) { struct mtk_serial_priv priv; - priv.regs = (void *) CONFIG_DEBUG_UART_BASE; + priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); priv.clock = CONFIG_DEBUG_UART_CLOCK; writel(0, &priv.regs->ier); @@ -439,7 +439,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { struct mtk_serial_regs __iomem *regs = - (void *) CONFIG_DEBUG_UART_BASE; + (void *) CONFIG_VAL(DEBUG_UART_BASE); while (!(readl(®s->lsr) & UART_LSR_THRE)) ; diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c index 3e673bde57b824d1af4e5f5bedb3617c3c43c110..0fcd7e88acee604c64d56a77d6d192b40cf54e59 100644 --- a/drivers/serial/serial_mvebu_a3700.c +++ b/drivers/serial/serial_mvebu_a3700.c @@ -321,7 +321,7 @@ U_BOOT_DRIVER(serial_mvebu) = { static inline void _debug_uart_init(void) { - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); u32 parent_rate, divider; /* reset FIFOs */ @@ -349,7 +349,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) ; diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index e4970a169bd838b0a9c6c9a6806ed62a212891a0..70a0e5e9197d8b5f560a87dbfcda1a13dbce5cb9 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -372,7 +372,7 @@ U_BOOT_DRIVER(serial_mxc) = { static inline void _debug_uart_init(void) { - struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; + struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE); _mxc_serial_init(base, false); _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK, @@ -381,7 +381,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; + struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE); while (!(readl(&base->ts) & UTS_TXEMPTY)) WATCHDOG_RESET(); diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index ee938f67632b5f3e41b93361fd3ee0133f0f26d2..e9ff61a0bac582e4b6d459c9c10d05a0834c47de 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -66,7 +66,7 @@ static inline int serial_in_shift(void *addr, int shift) static inline void _debug_uart_init(void) { - struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; + struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); int baud_divisor; baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, @@ -85,7 +85,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; + struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) ; diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c index ccdda9f03344b4b46d4f1c1377e183d4f6c1a46c..3c5d37ce0ab72c8acb61b5681433499e84cc10a3 100644 --- a/drivers/serial/serial_pic32.c +++ b/drivers/serial/serial_pic32.c @@ -187,14 +187,14 @@ U_BOOT_DRIVER(pic32_serial) = { static inline void _debug_uart_init(void) { - void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); } static inline void _debug_uart_putc(int ch) { - writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR); + writel(ch, CONFIG_VAL(DEBUG_UART_BASE) + U_TXR); } DEBUG_UART_FUNCS diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 67caa063c9a38f93f6399d442462efe25924d9ca..9b0d16f1645b2260c5893c0987c326e163f4f5fa 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -403,7 +403,7 @@ U_BOOT_DRIVER(serial_pl01x) = { static void _debug_uart_init(void) { #ifndef CONFIG_DEBUG_UART_SKIP_INIT - struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE); enum pl01x_type type; if (IS_ENABLED(CONFIG_DEBUG_UART_PL011)) @@ -419,7 +419,7 @@ static void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE); while (pl01x_putc(regs, ch) == -EAGAIN) ; diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c deleted file mode 100644 index 330fc127ecb3e03634a4193c16d33993e3047823..0000000000000000000000000000000000000000 --- a/drivers/serial/serial_pxa.c +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Marek Vasut - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * Modified to add driver model (DM) support - * (C) Copyright 2016 Marcel Ziswiler - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static uint32_t pxa_uart_get_baud_divider(int baudrate) -{ - return 921600 / baudrate; -} - -static void pxa_uart_toggle_clock(uint32_t uart_index, int enable) -{ - uint32_t clk_reg, clk_offset, reg; - - clk_reg = UART_CLK_REG; - clk_offset = UART_CLK_BASE << uart_index; - - reg = readl(clk_reg); - - if (enable) - reg |= clk_offset; - else - reg &= ~clk_offset; - - writel(reg, clk_reg); -} - -/* - * Enable clock and set baud rate, parity etc. - */ -void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate) -{ - uint32_t divider = pxa_uart_get_baud_divider(baudrate); - if (!divider) - hang(); - - - pxa_uart_toggle_clock(port, 1); - - /* Disable interrupts and FIFOs */ - writel(0, &uart_regs->ier); - writel(0, &uart_regs->fcr); - - /* Set baud rate */ - writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr); - writel(divider & 0xff, &uart_regs->dll); - writel(divider >> 8, &uart_regs->dlh); - writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr); - - /* Enable UART */ - writel(IER_UUE, &uart_regs->ier); -} - -#ifndef CONFIG_DM_SERIAL -static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index) -{ - switch (uart_index) { - case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE; - case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE; - case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE; - case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE; - default: - return NULL; - } -} - -/* - * Enable clock and set baud rate, parity etc. - */ -void pxa_setbrg_dev(uint32_t uart_index) -{ - struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - panic("Failed getting UART registers\n"); - - pxa_setbrg_common(uart_regs, uart_index, gd->baudrate); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int pxa_init_dev(unsigned int uart_index) -{ - pxa_setbrg_dev(uart_index); - return 0; -} - -/* - * Output a single byte to the serial port. - */ -void pxa_putc_dev(unsigned int uart_index, const char c) -{ - struct pxa_uart_regs *uart_regs; - - /* If \n, also do \r */ - if (c == '\n') - pxa_putc_dev(uart_index, '\r'); - - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - hang(); - - while (!(readl(&uart_regs->lsr) & LSR_TEMT)) - WATCHDOG_RESET(); - writel(c, &uart_regs->thr); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int pxa_tstc_dev(unsigned int uart_index) -{ - struct pxa_uart_regs *uart_regs; - - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - return -1; - - return readl(&uart_regs->lsr) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int pxa_getc_dev(unsigned int uart_index) -{ - struct pxa_uart_regs *uart_regs; - - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - return -1; - - while (!(readl(&uart_regs->lsr) & LSR_DR)) - WATCHDOG_RESET(); - return readl(&uart_regs->rbr) & 0xff; -} - -void pxa_puts_dev(unsigned int uart_index, const char *s) -{ - while (*s) - pxa_putc_dev(uart_index, *s++); -} - -#define pxa_uart(uart, UART) \ - int uart##_init(void) \ - { \ - return pxa_init_dev(UART##_INDEX); \ - } \ - \ - void uart##_setbrg(void) \ - { \ - return pxa_setbrg_dev(UART##_INDEX); \ - } \ - \ - void uart##_putc(const char c) \ - { \ - return pxa_putc_dev(UART##_INDEX, c); \ - } \ - \ - void uart##_puts(const char *s) \ - { \ - return pxa_puts_dev(UART##_INDEX, s); \ - } \ - \ - int uart##_getc(void) \ - { \ - return pxa_getc_dev(UART##_INDEX); \ - } \ - \ - int uart##_tstc(void) \ - { \ - return pxa_tstc_dev(UART##_INDEX); \ - } \ - -#define pxa_uart_desc(uart) \ - struct serial_device serial_##uart##_device = \ - { \ - .name = "serial_"#uart, \ - .start = uart##_init, \ - .stop = NULL, \ - .setbrg = uart##_setbrg, \ - .getc = uart##_getc, \ - .tstc = uart##_tstc, \ - .putc = uart##_putc, \ - .puts = uart##_puts, \ - }; - -#define pxa_uart_multi(uart, UART) \ - pxa_uart(uart, UART) \ - pxa_uart_desc(uart) - -#if defined(CONFIG_HWUART) - pxa_uart_multi(hwuart, HWUART) -#endif -#if defined(CONFIG_STUART) - pxa_uart_multi(stuart, STUART) -#endif -#if defined(CONFIG_FFUART) - pxa_uart_multi(ffuart, FFUART) -#endif -#if defined(CONFIG_BTUART) - pxa_uart_multi(btuart, BTUART) -#endif - -__weak struct serial_device *default_serial_console(void) -{ -#if CONFIG_CONS_INDEX == 1 - return &serial_hwuart_device; -#elif CONFIG_CONS_INDEX == 2 - return &serial_stuart_device; -#elif CONFIG_CONS_INDEX == 3 - return &serial_ffuart_device; -#elif CONFIG_CONS_INDEX == 4 - return &serial_btuart_device; -#else -#error "Bad CONFIG_CONS_INDEX." -#endif -} - -void pxa_serial_initialize(void) -{ -#if defined(CONFIG_FFUART) - serial_register(&serial_ffuart_device); -#endif -#if defined(CONFIG_BTUART) - serial_register(&serial_btuart_device); -#endif -#if defined(CONFIG_STUART) - serial_register(&serial_stuart_device); -#endif -} -#endif /* CONFIG_DM_SERIAL */ - -#ifdef CONFIG_DM_SERIAL -static int pxa_serial_probe(struct udevice *dev) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - - pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port, - plat->baudrate); - return 0; -} - -static int pxa_serial_putc(struct udevice *dev, const char ch) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - - /* Wait for last character to go. */ - if (!(readl(&uart_regs->lsr) & LSR_TEMT)) - return -EAGAIN; - - writel(ch, &uart_regs->thr); - - return 0; -} - -static int pxa_serial_getc(struct udevice *dev) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - - /* Wait for a character to arrive. */ - if (!(readl(&uart_regs->lsr) & LSR_DR)) - return -EAGAIN; - - return readl(&uart_regs->rbr) & 0xff; -} - -int pxa_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - int port = plat->port; - - pxa_setbrg_common(uart_regs, port, baudrate); - - return 0; -} - -static int pxa_serial_pending(struct udevice *dev, bool input) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - - if (input) - return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0; - else - return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1; - - return 0; -} - -static const struct dm_serial_ops pxa_serial_ops = { - .putc = pxa_serial_putc, - .pending = pxa_serial_pending, - .getc = pxa_serial_getc, - .setbrg = pxa_serial_setbrg, -}; - -U_BOOT_DRIVER(serial_pxa) = { - .name = "serial_pxa", - .id = UCLASS_SERIAL, - .probe = pxa_serial_probe, - .ops = &pxa_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; -#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index de420d2d94533664a703cfbb7df2bae29f1d9c5f..4b3947e7f6b52a62d64be7d1e29b4f6497791b68 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -276,7 +276,7 @@ static inline void _debug_uart_init(void) if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT)) return; - struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; + struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE); s5p_serial_init(uart); #if CONFIG_IS_ENABLED(ARCH_APPLE) @@ -288,7 +288,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; + struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE); #if CONFIG_IS_ENABLED(ARCH_APPLE) while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL); diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c index 2561414e40f8f866d7328c46f3b5a34327afa934..cfa1ec3148c5a1d8d6cc3198b501fe76ee36ec64 100644 --- a/drivers/serial/serial_semihosting.c +++ b/drivers/serial/serial_semihosting.c @@ -13,10 +13,12 @@ * struct smh_serial_priv - Semihosting serial private data * @infd: stdin file descriptor (or error) * @outfd: stdout file descriptor (or error) + * @counter: Counter used to fake pending every other call */ struct smh_serial_priv { int infd; int outfd; + unsigned counter; }; #if CONFIG_IS_ENABLED(DM_SERIAL) @@ -68,10 +70,20 @@ static ssize_t smh_serial_puts(struct udevice *dev, const char *s, size_t len) return ret; } +static int smh_serial_pending(struct udevice *dev, bool input) +{ + struct smh_serial_priv *priv = dev_get_priv(dev); + + if (input) + return priv->counter++ & 1; + return false; +} + static const struct dm_serial_ops smh_serial_ops = { .putc = smh_serial_putc, .puts = smh_serial_puts, .getc = smh_serial_getc, + .pending = smh_serial_pending, }; static int smh_serial_bind(struct udevice *dev) @@ -106,6 +118,7 @@ U_BOOT_DRVINFO(smh_serial) = { #else /* DM_SERIAL */ static int infd = -ENODEV; static int outfd = -ENODEV; +static unsigned counter = 1; static int smh_serial_start(void) { @@ -138,7 +151,7 @@ static int smh_serial_getc(void) static int smh_serial_tstc(void) { - return 1; + return counter++ & 1; } static void smh_serial_puts(const char *s) diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c index 794f9c924bc415dd1babcc5ac02a05f0f51e2c74..4af1ff5060a93eaee51db681ca0e260c2db8d1cf 100644 --- a/drivers/serial/serial_sifive.c +++ b/drivers/serial/serial_sifive.c @@ -212,7 +212,7 @@ U_BOOT_DRIVER(serial_sifive) = { static inline void _debug_uart_init(void) { struct uart_sifive *regs = - (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE); _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); @@ -222,7 +222,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { struct uart_sifive *regs = - (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE); while (_sifive_serial_putc(regs, ch) == -EAGAIN) WATCHDOG_RESET(); diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index f6cb708c370fe9aad610d107102839d667927204..2ba92bf9c4842739310fc8e0296da3486fb19855 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -270,7 +270,7 @@ static inline struct stm32_uart_info *_debug_uart_info(void) static inline void _debug_uart_init(void) { - fdt_addr_t base = CONFIG_DEBUG_UART_BASE; + fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); struct stm32_uart_info *uart_info = _debug_uart_info(); _stm32_serial_init(base, uart_info); @@ -281,7 +281,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int c) { - fdt_addr_t base = CONFIG_DEBUG_UART_BASE; + fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); struct stm32_uart_info *uart_info = _debug_uart_info(); while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN) diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 9780a44d09ee14ad37f432357105659f7c30b5f3..b6197da97cc1e4aeb8b2fcb076573996f705ab98 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -143,7 +143,7 @@ U_BOOT_DRIVER(serial_uartlite) = { static inline void _debug_uart_init(void) { - struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; + struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); int ret; uart_out32(®s->control, 0); @@ -159,7 +159,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; + struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); while (uart_in32(®s->status) & SR_TX_FIFO_FULL) ; diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 6bb003dc1558f43db0a7308455de35179137f061..83adfb5fb98ab1ad53a70c1cd2319c3146bbb52b 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -295,7 +295,7 @@ U_BOOT_DRIVER(serial_zynq) = { #ifdef CONFIG_DEBUG_UART_ZYNQ static inline void _debug_uart_init(void) { - struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE); _uart_zynq_serial_init(regs); _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, @@ -304,7 +304,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE); while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) WATCHDOG_RESET(); diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 05b3c01e5fc1ad9d5b2e08f9d6bf3fec08568843..0d89fc085fb530c3ad0658bf90f7261e7ed2a5ba 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -13,8 +13,6 @@ #include #if defined(CONFIG_PPC) #include -#elif defined(CONFIG_CPU_PXA27X) -#include #elif defined(CONFIG_DW_UDC) #include #elif defined(CONFIG_CI_UDC) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 965728e8185a0a2415ad9e7c9c154755c95b98d1..b1e7c4ae5f6aa52ca19200daeed3b2ea50de9947 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -15,6 +15,7 @@ #define J7200 0xbb6d #define AM64X 0xbb38 #define J721S2 0xbb75 +#define AM62X 0xbb7e #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) @@ -49,6 +50,9 @@ static const char *get_family_string(u32 idreg) case J721S2: family = "J721S2"; break; + case AM62X: + family = "AM62X"; + break; default: family = "Unknown Silicon"; }; @@ -60,8 +64,8 @@ static char *j721e_rev_string_map[] = { "1.0", "1.1", }; -static char *am65x_rev_string_map[] = { - "1.0", "2.0", +static char *typical_rev_string_map[] = { + "1.0", "2.0", "3.0", }; static const char *get_rev_string(u32 idreg) @@ -78,16 +82,10 @@ static const char *get_rev_string(u32 idreg) goto bail; return j721e_rev_string_map[rev]; - case AM65X: - if (rev > ARRAY_SIZE(am65x_rev_string_map)) - goto bail; - return am65x_rev_string_map[rev]; - - case AM64X: - case J7200: default: - if (!rev) - return "1.0"; + if (rev > ARRAY_SIZE(typical_rev_string_map)) + goto bail; + return typical_rev_string_map[rev]; }; bail: diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index a71115b17ccd26199ef01c3bfd2a140ca960dea3..c10fc7d4449bff6d26fc1a539cd59ae25afb597a 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -3,10 +3,15 @@ * Xilinx ZynqMP SOC driver * * Copyright (C) 2021 Xilinx, Inc. + * Michal Simek + * + * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG + * Stefan Herbrechtsmeier */ #include #include +#include #include #include #include @@ -22,11 +27,257 @@ */ static const char zynqmp_family[] = "ZynqMP"; +#define EFUSE_VCU_DIS_SHIFT 8 +#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT) +#define EFUSE_GPU_DIS_SHIFT 5 +#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT) +#define IDCODE_DEV_TYPE_MASK GENMASK(27, 0) +#define IDCODE2_PL_INIT_SHIFT 9 +#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT) + +#define ZYNQMP_VERSION_SIZE 7 + +enum { + ZYNQMP_VARIANT_EG = BIT(0), + ZYNQMP_VARIANT_EV = BIT(1), + ZYNQMP_VARIANT_CG = BIT(2), + ZYNQMP_VARIANT_DR = BIT(3), +}; + +struct zynqmp_device { + u32 id; + u8 device; + u8 variants; +}; + struct soc_xilinx_zynqmp_priv { const char *family; + char machine[ZYNQMP_VERSION_SIZE]; char revision; }; +static const struct zynqmp_device zynqmp_devices[] = { + { + .id = 0x04688093, + .device = 1, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04711093, + .device = 2, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04710093, + .device = 3, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04721093, + .device = 4, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | + ZYNQMP_VARIANT_EV, + }, + { + .id = 0x04720093, + .device = 5, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | + ZYNQMP_VARIANT_EV, + }, + { + .id = 0x04739093, + .device = 6, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04730093, + .device = 7, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | + ZYNQMP_VARIANT_EV, + }, + { + .id = 0x04738093, + .device = 9, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04740093, + .device = 11, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04750093, + .device = 15, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04759093, + .device = 17, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04758093, + .device = 19, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x047E1093, + .device = 21, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E3093, + .device = 23, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E5093, + .device = 25, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E4093, + .device = 27, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E0093, + .device = 28, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E2093, + .device = 29, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E6093, + .device = 39, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FD093, + .device = 43, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047F8093, + .device = 46, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FF093, + .device = 47, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FB093, + .device = 48, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FE093, + .device = 49, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046d0093, + .device = 67, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x04714093, + .device = 24, + .variants = 0, + }, + { + .id = 0x04724093, + .device = 26, + .variants = 0, + }, +}; + +static const struct zynqmp_device *zynqmp_get_device(u32 idcode) +{ + idcode &= IDCODE_DEV_TYPE_MASK; + + for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { + if (zynqmp_devices[i].id == idcode) + return &zynqmp_devices[i]; + } + + return NULL; +} + +static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, + u32 idcode2) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + const struct zynqmp_device *device; + int ret; + + device = zynqmp_get_device(idcode); + if (!device) + return 0; + + /* Add device prefix to the name */ + ret = snprintf(priv->machine, sizeof(priv->machine), "%s%d", + device->variants ? "zu" : "xck", device->device); + if (ret < 0) + return ret; + + if (device->variants & ZYNQMP_VARIANT_EV) { + /* Devices with EV variant might be EG/CG/EV family */ + if (idcode2 & IDCODE2_PL_INIT_MASK) { + u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >> + EFUSE_VCU_DIS_SHIFT) << 1 | + ((idcode2 & EFUSE_GPU_DIS_MASK) >> + EFUSE_GPU_DIS_SHIFT); + + /* + * Get family name based on extended idcode values as + * determined on UG1087, EXTENDED_IDCODE register + * description + */ + switch (family) { + case 0x00: + strlcat(priv->machine, "ev", + sizeof(priv->machine)); + break; + case 0x10: + strlcat(priv->machine, "eg", + sizeof(priv->machine)); + break; + case 0x11: + strlcat(priv->machine, "cg", + sizeof(priv->machine)); + break; + default: + /* Do not append family name*/ + break; + } + } else { + /* + * When PL powered down the VCU Disable efuse cannot be + * read. So, ignore the bit and just findout if it is CG + * or EG/EV variant. + */ + strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ? + "cg" : "e", sizeof(priv->machine)); + } + } else if (device->variants & ZYNQMP_VARIANT_CG) { + /* Devices with CG variant might be EG or CG family */ + strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ? + "cg" : "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_EG) { + strlcat(priv->machine, "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_DR) { + strlcat(priv->machine, "dr", sizeof(priv->machine)); + } + + return 0; +} + static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size) { struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); @@ -34,6 +285,17 @@ static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size return snprintf(buf, size, "%s", priv->family); } +int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + const char *machine = priv->machine; + + if (!machine[0]) + machine = "unknown"; + + return snprintf(buf, size, "%s", machine); +} + static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size) { struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); @@ -44,6 +306,7 @@ static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int si static const struct soc_ops soc_xilinx_zynqmp_ops = { .get_family = soc_xilinx_zynqmp_get_family, .get_revision = soc_xilinx_zynqmp_get_revision, + .get_machine = soc_xilinx_zynqmp_get_machine, }; static int soc_xilinx_zynqmp_probe(struct udevice *dev) @@ -54,8 +317,7 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev) priv->family = zynqmp_family; - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3 || - !IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) + if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]); else ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, @@ -65,6 +327,26 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev) priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK; + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + /* + * Firmware returns: + * payload[0][31:0] = status of the operation + * payload[1] = IDCODE + * payload[2][19:0] = Version + * payload[2][28:20] = EXTENDED_IDCODE + * payload[2][29] = PL_INIT + */ + u32 idcode = ret_payload[1]; + u32 idcode2 = ret_payload[2] >> + ZYNQMP_CSU_VERSION_EMPTY_SHIFT; + dev_dbg(dev, "IDCODE: 0x%0x, IDCODE2: 0x%0x\n", idcode, + idcode2); + + ret = soc_xilinx_zynqmp_detect_machine(dev, idcode, idcode2); + if (ret) + return ret; + } + return 0; } diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 8d674bcb4fa32788e237a50176b00407ce832d27..c1edef4436082fcfca0b13ccd41c1bcc80afa6cd 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -23,6 +23,7 @@ #define DA7219_ACPI_HID "DLGS7219" +__maybe_unused static int da7219_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) { @@ -171,10 +172,12 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev, #endif struct acpi_ops da7219_acpi_ops = { +#ifdef CONFIG_ACPIGEN .fill_ssdt = da7219_acpi_fill_ssdt, #ifdef CONFIG_X86 .setup_nhlt = da7219_acpi_setup_nhlt, #endif +#endif }; static const struct udevice_id da7219_ids[] = { diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index a2088f0301435cb2cbb27086815e7e53ad7ca73f..bdf6dc236ec38db62b37b9a0315c4564b7312584 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -38,6 +38,7 @@ static int max98357a_of_to_plat(struct udevice *dev) return 0; } +__maybe_unused static int max98357a_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) { @@ -137,10 +138,12 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev, #endif struct acpi_ops max98357a_acpi_ops = { +#ifdef CONFIG_ACPIGEN .fill_ssdt = max98357a_acpi_fill_ssdt, #ifdef CONFIG_X86 .setup_nhlt = max98357a_acpi_setup_nhlt, #endif +#endif }; static const struct audio_codec_ops max98357a_ops = { diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2bc91a322a30344029b3f8d067f76837..766d5636c09a9ab901504732a94f35653e53b758 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -136,6 +136,14 @@ config CQSPI_REF_CLK int "Cadence QSPI reference clock value in Hz" depends on HAS_CQSPI_REF_CLK +config CADENCE_OSPI_VERSAL + bool "Configure Versal OSPI" + depends on ARCH_VERSAL && CADENCE_QSPI + imply DM_GPIO + help + This option is used to enable Versal OSPI DMA operations which + are used for ospi flash read using cadence qspi controller. + config CF_SPI bool "ColdFire SPI driver" help @@ -186,6 +194,12 @@ config FSL_QSPI_AHB_FULL_MAP Enable the Freescale QSPI driver to use full AHB memory map space for flash access. +config GXP_SPI + bool "SPI driver for GXP" + imply SPI_FLASH_BAR + help + Enable support for SPI on GXP. + config ICH_SPI bool "Intel ICH SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465bca633985568392ac45a9edbb7b3d5f..4de77c260adf8ece653f87dbdfecdf4bdc92002d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_$(SPL_TPL_)DM_SPI obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o +obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o @@ -33,6 +34,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o +obj-$(CONFIG_GXP_SPI) += gxp_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c new file mode 100644 index 0000000000000000000000000000000000000000..52bcad053fe6229f008f367e09788e69a0ef1838 --- /dev/null +++ b/drivers/spi/cadence_ospi_versal.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx + * + * Cadence QSPI controller DMA operations + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cadence_qspi.h" +#include + +#define CMD_4BYTE_READ 0x13 +#define CMD_4BYTE_FAST_READ 0x0C + +int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data; + u8 opcode, addr_bytes, *rxbuf, dummy_cycles; + + n_rx = op->data.nbytes; + rxbuf = op->data.buf.in; + rx_rem = n_rx % 4; + bytes_to_dma = n_rx - rx_rem; + + if (bytes_to_dma) { + cadence_qspi_apb_enable_linear_mode(false); + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENBL_DMA; + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); + + writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE, + plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); + writel(CQSPI_DFLT_DMA_PERIPH_CFG, + plat->regbase + CQSPI_REG_DMA_PERIPH_CFG); + writel((unsigned long)rxbuf, plat->regbase + + CQSPI_DMA_DST_ADDR_REG); + writel(plat->trigger_address, plat->regbase + + CQSPI_DMA_SRC_RD_ADDR_REG); + writel(bytes_to_dma, plat->regbase + + CQSPI_DMA_DST_SIZE_REG); + flush_dcache_range((unsigned long)rxbuf, + (unsigned long)rxbuf + bytes_to_dma); + writel(CQSPI_DFLT_DST_CTRL_REG_VAL, + plat->regbase + CQSPI_DMA_DST_CTRL_REG); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START, plat->regbase + + CQSPI_REG_INDIRECTRD); + /* Wait for dma to complete transfer */ + ret = cadence_qspi_apb_wait_for_dma_cmplt(plat); + if (ret) + return ret; + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + + CQSPI_REG_INDIRECTRD); + rxbuf += bytes_to_dma; + } + + if (rx_rem) { + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENBL_DMA; + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + reg += bytes_to_dma; + writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS); + + addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) & + CQSPI_REG_SIZE_ADDRESS_MASK; + + opcode = CMD_4BYTE_FAST_READ; + dummy_cycles = 8; + writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode, + plat->regbase + CQSPI_REG_RD_INSTR); + + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + dummy_cycles = (readl(plat->regbase + CQSPI_REG_RD_INSTR) >> + CQSPI_REG_RD_INSTR_DUMMY_LSB) & + CQSPI_REG_RD_INSTR_DUMMY_MASK; + reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) << + CQSPI_REG_CMDCTRL_DUMMY_LSB; + reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + ret = cadence_qspi_apb_exec_flash_cmd(plat->regbase, reg); + if (ret) + return ret; + + data = readl(plat->regbase + CQSPI_REG_CMDREADDATALOWER); + memcpy(rxbuf, &data, rx_rem); + } + + return 0; +} + +int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat) +{ + u32 timeout = CQSPI_DMA_TIMEOUT; + + while (!(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG) & + CQSPI_DMA_DST_I_STS_DONE) && timeout--) + udelay(1); + + if (!timeout) { + printf("DMA timeout\n"); + return -ETIMEDOUT; + } + + writel(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG), + plat->regbase + CQSPI_DMA_DST_I_STS_REG); + return 0; +} + +#if defined(CONFIG_DM_GPIO) +int cadence_spi_versal_flash_reset(struct udevice *dev) +{ + struct gpio_desc gpio; + u32 reset_gpio; + int ret; + + /* request gpio and set direction as output set to 1 */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + printf("%s: unable to reset ospi flash device", __func__); + return ret; + } + + reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; + + /* Request for pin */ + xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); + + /* Enable hysteresis in cmos receiver */ + xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, + PM_PINCTRL_CONFIG_SCHMITT_CMOS, + PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); + + /* Disable Tri-state */ + xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, + PM_PINCTRL_CONFIG_TRI_STATE, + PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); + udelay(1); + + /* Set value 0 to pin */ + dm_gpio_set_value(&gpio, 0); + udelay(1); + + /* Set value 1 to pin */ + dm_gpio_set_value(&gpio, 1); + udelay(1); + + return 0; +} +#else +int cadence_spi_versal_flash_reset(struct udevice *dev) +{ + /* CRP WPROT */ + writel(0, WPROT_CRP); + /* GPIO Reset */ + writel(0, RST_GPIO); + + /* disable IOU write protection */ + writel(0, WPROT_LPD_MIO); + + /* set direction as output */ + writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)), + BOOT_MODE_POR_0); + + /* Data output enable */ + writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)), + BOOT_MODE_POR_1); + + /* IOU SLCR write enable */ + writel(0, WPROT_PMC_MIO); + + /* set MIO as GPIO */ + writel(0x60, MIO_PIN_12); + + /* Set value 1 to pin */ + writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + /* Disable Tri-state */ + writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI); + udelay(1); + + /* Set value 0 to pin */ + writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + /* Set value 1 to pin */ + writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + return 0; +} +#endif + +void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) { + if (enable) + /* ahb read mode */ + xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, + IOCTL_OSPI_MUX_SELECT, + PM_OSPI_MUX_SEL_LINEAR, 0, NULL); + else + /* DMA mode */ + xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, + IOCTL_OSPI_MUX_SELECT, + PM_OSPI_MUX_SEL_DMA, 0, NULL); + } else { + if (enable) + writel(readl(VERSAL_AXI_MUX_SEL) | + VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); + else + writel(readl(VERSAL_AXI_MUX_SEL) & + ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); + } +} diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 7209bb43a776c7d274cce270915973c85b146f38..907f5dadc4fb4bf000543683e48b5cff30fd8681 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -18,7 +18,9 @@ #include #include #include +#include #include "cadence_qspi.h" +#include #define NSEC_PER_SEC 1000000000L @@ -27,6 +29,17 @@ #define CQSPI_READ 2 #define CQSPI_WRITE 3 +__weak int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + return 0; +} + +__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) +{ + return 0; +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_plat *plat = dev_get_plat(bus); @@ -138,7 +151,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err; - if (hz > plat->max_hz) + if (!hz || hz > plat->max_hz) hz = plat->max_hz; /* Disable QSPI */ @@ -185,6 +198,11 @@ static int cadence_spi_probe(struct udevice *bus) priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) + xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, + ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, + ZYNQMP_PM_REQUEST_ACK_NO, NULL); + if (plat->ref_clk_hz == 0) { ret = clk_get_by_index(bus, 0, &clk); if (ret) { @@ -214,6 +232,16 @@ static int cadence_spi_probe(struct udevice *bus) plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) { + /* Versal platform uses spi calibration to set read delay */ + if (plat->read_delay >= 0) + plat->read_delay = -1; + /* Reset ospi flash device */ + ret = cadence_qspi_versal_flash_reset(bus); + if (ret) + return ret; + } + return 0; } @@ -288,8 +316,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, break; case CQSPI_READ: err = cadence_qspi_apb_read_setup(plat, op); - if (!err) - err = cadence_qspi_apb_read_execute(plat, op); + if (!err) { + if (plat->is_dma) + err = cadence_qspi_apb_dma_read(plat, op); + else + err = cadence_qspi_apb_read_execute(plat, op); + } break; case CQSPI_WRITE: err = cadence_qspi_apb_write_setup(plat, op); @@ -342,6 +374,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus) if (plat->ahbsize >= SZ_8M) plat->use_dac_mode = true; + plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); + /* All other paramters are embedded in the child node */ subnode = dev_read_first_subnode(bus); if (!ofnode_valid(subnode)) { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index a2b620a5fe297592d48952fd59e0aee0619bbf63..c8d16bb0e44fe7c9b8cb303319aefe1f593ba495 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -8,6 +8,8 @@ #define __CADENCE_QSPI_H__ #include +#include +#include #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) @@ -15,6 +17,186 @@ #define CQSPI_DECODER_MAX_CS 16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16 +#define CQSPI_REG_POLL_US 1 /* 1us */ +#define CQSPI_REG_RETRY 10000 +#define CQSPI_POLL_IDLE_RETRY 3 + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE 0 +#define CQSPI_INST_TYPE_DUAL 1 +#define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 + +#define CQSPI_STIG_DATA_LEN_MAX 8 + +#define CQSPI_DUMMY_CLKS_PER_BYTE 8 +#define CQSPI_DUMMY_BYTES_MAX 4 +#define CQSPI_DUMMY_CLKS_MAX 31 + +/**************************************************************************** + * Controller's configuration and status register (offset from QSPI_BASE) + ****************************************************************************/ +#define CQSPI_REG_CONFIG 0x00 +#define CQSPI_REG_CONFIG_ENABLE BIT(0) +#define CQSPI_REG_CONFIG_CLK_POL BIT(1) +#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) +#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) +#define CQSPI_REG_CONFIG_DIRECT BIT(7) +#define CQSPI_REG_CONFIG_DECODE BIT(9) +#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) +#define CQSPI_REG_CONFIG_XIP_IMM BIT(18) +#define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK BIT(24) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) +#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF + +#define CQSPI_REG_RD_INSTR 0x04 +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F + +#define CQSPI_REG_WR_INSTR 0x08 +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 + +#define CQSPI_REG_DELAY 0x0C +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF + +#define CQSPI_REG_RD_DATA_CAPTURE 0x10 +#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) +#define CQSPI_REG_READCAPTURE_DQS_ENABLE BIT(8) +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF + +#define CQSPI_REG_SIZE 0x14 +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F + +#define CQSPI_REG_SRAMPARTITION 0x18 +#define CQSPI_REG_INDIRECTTRIGGER 0x1C + +#define CQSPI_REG_REMAP 0x24 +#define CQSPI_REG_MODE_BIT 0x28 + +#define CQSPI_REG_SDRAMLEVEL 0x2C +#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF + +#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 +#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) + +#define CQSPI_REG_IRQSTATUS 0x40 +#define CQSPI_REG_IRQMASK 0x44 + +#define CQSPI_REG_INDIRECTRD 0x60 +#define CQSPI_REG_INDIRECTRD_START BIT(0) +#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) +#define CQSPI_REG_INDIRECTRD_DONE BIT(5) + +#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 +#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 +#define CQSPI_REG_INDIRECTRDBYTES 0x6C + +#define CQSPI_REG_CMDCTRL 0x90 +#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) +#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF + +#define CQSPI_REG_INDIRECTWR 0x70 +#define CQSPI_REG_INDIRECTWR_START BIT(0) +#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) +#define CQSPI_REG_INDIRECTWR_DONE BIT(5) + +#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 +#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 +#define CQSPI_REG_INDIRECTWRBYTES 0x7C + +#define CQSPI_REG_CMDADDRESS 0x94 +#define CQSPI_REG_CMDREADDATALOWER 0xA0 +#define CQSPI_REG_CMDREADDATAUPPER 0xA4 +#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 +#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC + +#define CQSPI_REG_OP_EXT_LOWER 0xE0 +#define CQSPI_REG_OP_EXT_READ_LSB 24 +#define CQSPI_REG_OP_EXT_WRITE_LSB 16 +#define CQSPI_REG_OP_EXT_STIG_LSB 0 + +#define CQSPI_REG_PHY_CONFIG 0xB4 +#define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000 + +#define CQSPI_DMA_DST_ADDR_REG 0x1800 +#define CQSPI_DMA_DST_SIZE_REG 0x1804 +#define CQSPI_DMA_DST_STS_REG 0x1808 +#define CQSPI_DMA_DST_CTRL_REG 0x180C +#define CQSPI_DMA_DST_I_STS_REG 0x1814 +#define CQSPI_DMA_DST_I_ENBL_REG 0x1818 +#define CQSPI_DMA_DST_I_DISBL_REG 0x181C +#define CQSPI_DMA_DST_CTRL2_REG 0x1824 +#define CQSPI_DMA_DST_ADDR_MSB_REG 0x1828 + +#define CQSPI_DMA_SRC_RD_ADDR_REG 0x1000 + +#define CQSPI_REG_DMA_PERIPH_CFG 0x20 +#define CQSPI_REG_INDIR_TRIG_ADDR_RANGE 0x80 +#define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE 6 +#define CQSPI_DFLT_DMA_PERIPH_CFG 0x602 +#define CQSPI_DFLT_DST_CTRL_REG_VAL 0xF43FFA00 + +#define CQSPI_DMA_DST_I_STS_DONE BIT(1) +#define CQSPI_DMA_TIMEOUT 10000000 + +#define CQSPI_REG_IS_IDLE(base) \ + ((readl((base) + CQSPI_REG_CONFIG) >> \ + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + +#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ + (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) + +#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ + (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) + struct cadence_spi_plat { unsigned int ref_clk_hz; unsigned int max_hz; @@ -42,6 +224,7 @@ struct cadence_spi_plat { u8 addr_width; u8 data_width; bool dtr; + bool is_dma; }; struct cadence_spi_priv { @@ -96,5 +279,11 @@ void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); void cadence_qspi_apb_readdata_capture(void *reg_base, unsigned int bypass, unsigned int delay); unsigned int cm_get_qspi_controller_clk_hz(void); +int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat); +int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); +int cadence_qspi_versal_flash_reset(struct udevice *dev); +void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f8dc7387ef23d3a260926d97f3c8a7e..c00755050e1ccdd149f2247dd4845572ede5f7a2 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -38,156 +38,10 @@ #include #include "cadence_qspi.h" -#define CQSPI_REG_POLL_US 1 /* 1us */ -#define CQSPI_REG_RETRY 10000 -#define CQSPI_POLL_IDLE_RETRY 3 - -/* Transfer mode */ -#define CQSPI_INST_TYPE_SINGLE 0 -#define CQSPI_INST_TYPE_DUAL 1 -#define CQSPI_INST_TYPE_QUAD 2 -#define CQSPI_INST_TYPE_OCTAL 3 - -#define CQSPI_STIG_DATA_LEN_MAX 8 - -#define CQSPI_DUMMY_CLKS_PER_BYTE 8 -#define CQSPI_DUMMY_CLKS_MAX 31 - -/**************************************************************************** - * Controller's configuration and status register (offset from QSPI_BASE) - ****************************************************************************/ -#define CQSPI_REG_CONFIG 0x00 -#define CQSPI_REG_CONFIG_ENABLE BIT(0) -#define CQSPI_REG_CONFIG_CLK_POL BIT(1) -#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) -#define CQSPI_REG_CONFIG_DIRECT BIT(7) -#define CQSPI_REG_CONFIG_DECODE BIT(9) -#define CQSPI_REG_CONFIG_XIP_IMM BIT(18) -#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 -#define CQSPI_REG_CONFIG_BAUD_LSB 19 -#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) -#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) -#define CQSPI_REG_CONFIG_IDLE_LSB 31 -#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF -#define CQSPI_REG_CONFIG_BAUD_MASK 0xF - -#define CQSPI_REG_RD_INSTR 0x04 -#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 -#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 -#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 -#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F - -#define CQSPI_REG_WR_INSTR 0x08 -#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 -#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 -#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 - -#define CQSPI_REG_DELAY 0x0C -#define CQSPI_REG_DELAY_TSLCH_LSB 0 -#define CQSPI_REG_DELAY_TCHSH_LSB 8 -#define CQSPI_REG_DELAY_TSD2D_LSB 16 -#define CQSPI_REG_DELAY_TSHSL_LSB 24 -#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF -#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF -#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF -#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF - -#define CQSPI_REG_RD_DATA_CAPTURE 0x10 -#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) -#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 -#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF - -#define CQSPI_REG_SIZE 0x14 -#define CQSPI_REG_SIZE_ADDRESS_LSB 0 -#define CQSPI_REG_SIZE_PAGE_LSB 4 -#define CQSPI_REG_SIZE_BLOCK_LSB 16 -#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF -#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF -#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F - -#define CQSPI_REG_SRAMPARTITION 0x18 -#define CQSPI_REG_INDIRECTTRIGGER 0x1C - -#define CQSPI_REG_REMAP 0x24 -#define CQSPI_REG_MODE_BIT 0x28 - -#define CQSPI_REG_SDRAMLEVEL 0x2C -#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 -#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 -#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF -#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF - -#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 -#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) - -#define CQSPI_REG_IRQSTATUS 0x40 -#define CQSPI_REG_IRQMASK 0x44 - -#define CQSPI_REG_INDIRECTRD 0x60 -#define CQSPI_REG_INDIRECTRD_START BIT(0) -#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) -#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) -#define CQSPI_REG_INDIRECTRD_DONE BIT(5) - -#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 -#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 -#define CQSPI_REG_INDIRECTRDBYTES 0x6C - -#define CQSPI_REG_CMDCTRL 0x90 -#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) -#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) -#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 -#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 -#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 -#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 -#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 -#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 -#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 -#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F -#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 -#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF - -#define CQSPI_REG_INDIRECTWR 0x70 -#define CQSPI_REG_INDIRECTWR_START BIT(0) -#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) -#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) -#define CQSPI_REG_INDIRECTWR_DONE BIT(5) - -#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 -#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 -#define CQSPI_REG_INDIRECTWRBYTES 0x7C - -#define CQSPI_REG_CMDADDRESS 0x94 -#define CQSPI_REG_CMDREADDATALOWER 0xA0 -#define CQSPI_REG_CMDREADDATAUPPER 0xA4 -#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 -#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC - -#define CQSPI_REG_OP_EXT_LOWER 0xE0 -#define CQSPI_REG_OP_EXT_READ_LSB 24 -#define CQSPI_REG_OP_EXT_WRITE_LSB 16 -#define CQSPI_REG_OP_EXT_STIG_LSB 0 - -#define CQSPI_REG_IS_IDLE(base) \ - ((readl(base + CQSPI_REG_CONFIG) >> \ - CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) - -#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ - (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ - CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) - -#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ - (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ - CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) +__weak void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + return; +} void cadence_qspi_apb_controller_enable(void *reg_base) { @@ -487,8 +341,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat) cadence_qspi_apb_controller_enable(plat->regbase); } -static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, - unsigned int reg) +int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) { unsigned int retry = CQSPI_REG_RETRY; @@ -882,6 +735,9 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat, void *buf = op->data.buf.in; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + if (plat->use_dac_mode && (from + len < plat->ahbsize)) { if (len < 256 || dma_memcpy(buf, plat->ahbbase + from, len) < 0) { @@ -1049,6 +905,9 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + /* * Some flashes like the Cypress Semper flash expect a dummy 4-byte * address (all 0s) with the read status register command in DTR mode. diff --git a/drivers/spi/gxp_spi.c b/drivers/spi/gxp_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..70d76ac66adf39650149967d9ddc9dd2232ca337 --- /dev/null +++ b/drivers/spi/gxp_spi.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GXP SPI driver + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins + * Author: Jean-Marie Verdun + */ + +#include +#include +#include + +#define GXP_SPI0_MAX_CHIPSELECT 2 + +#define MANUAL_MODE 0 +#define AUTO_MODE 1 +#define OFFSET_SPIMCFG 0x00 +#define OFFSET_SPIMCTRL 0x04 +#define OFFSET_SPICMD 0x05 +#define OFFSET_SPIDCNT 0x06 +#define OFFSET_SPIADDR 0x08 +#define OFFSET_SPILDAT 0x40 +#define GXP_SPILDAT_SIZE 64 + +#define SPIMCTRL_START 0x01 +#define SPIMCTRL_BUSY 0x02 + +#define CMD_READ_ARRAY_FAST 0x0b + +struct gxp_spi_priv { + struct spi_slave slave; + void __iomem *base; + unsigned int mode; + +}; + +static void spi_set_mode(struct gxp_spi_priv *priv, int mode) +{ + unsigned char value; + + value = readb(priv->base + OFFSET_SPIMCTRL); + if (mode == MANUAL_MODE) { + writeb(0x55, priv->base + OFFSET_SPICMD); + writeb(0xaa, priv->base + OFFSET_SPICMD); + /* clear bit5 and bit4, auto_start and start_mask */ + value &= ~(0x03 << 4); + } else { + value |= (0x03 << 4); + } + writeb(value, priv->base + OFFSET_SPIMCTRL); +} + +static int gxp_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, + unsigned long flags) +{ + struct gxp_spi_priv *priv = dev_get_priv(dev->parent); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + + unsigned int len = bitlen / 8; + unsigned int value; + unsigned int addr = 0; + unsigned char uchar_out[len]; + unsigned char *uchar_in = (unsigned char *)din; + int read_len; + int read_ptr; + + if (dout && din) { + /* + * error: gxp spi engin cannot send data to dout and read data from din at the same + * time + */ + return -1; + } + + memset(uchar_out, 0, sizeof(uchar_out)); + if (dout) + memcpy(uchar_out, dout, len); + + if (flags & SPI_XFER_BEGIN) { + /* the dout is cmd + addr, cmd=dout[0], add1~3=dout[1~3]. */ + /* cmd reg */ + writeb(uchar_out[0], priv->base + OFFSET_SPICMD); + + /* config reg */ + value = readl(priv->base + OFFSET_SPIMCFG); + value &= ~(1 << 24); + /* set chipselect */ + value |= (slave_plat->cs << 24); + + /* addr reg and addr size */ + if (len >= 4) { + addr = uchar_out[1] << 16 | uchar_out[2] << 8 | uchar_out[3]; + writel(addr, priv->base + OFFSET_SPIADDR); + value &= ~(0x07 << 16); + /* set the address size to 3 byte */ + value |= (3 << 16); + } else { + writel(0, priv->base + OFFSET_SPIADDR); + /* set the address size to 0 byte */ + value &= ~(0x07 << 16); + } + + /* dummy */ + /* clear dummy_cnt to */ + value &= ~(0x1f << 19); + if (uchar_out[0] == CMD_READ_ARRAY_FAST) { + /* fast read needs 8 dummy clocks */ + value |= (8 << 19); + } + + writel(value, priv->base + OFFSET_SPIMCFG); + + if (flags & SPI_XFER_END) { + /* no data cmd just start it */ + /* set the data direction bit to 1 */ + value = readb(priv->base + OFFSET_SPIMCTRL); + value |= (1 << 3); + writeb(value, priv->base + OFFSET_SPIMCTRL); + + /* set the data byte count */ + writeb(0, priv->base + OFFSET_SPIDCNT); + + /* set the start bit */ + value = readb(priv->base + OFFSET_SPIMCTRL); + value |= SPIMCTRL_START; + writeb(value, priv->base + OFFSET_SPIMCTRL); + + /* wait busy bit is cleared */ + do { + value = readb(priv->base + OFFSET_SPIMCTRL); + } while (value & SPIMCTRL_BUSY); + return 0; + } + } + + if (!(flags & SPI_XFER_END) && (flags & SPI_XFER_BEGIN)) { + /* first of spi_xfer calls */ + return 0; + } + + /* if dout != null, write data to buf and start transaction */ + if (dout) { + if (len > slave->max_write_size) { + printf("SF: write length is too big(>%d)\n", slave->max_write_size); + return -1; + } + + /* load the data bytes */ + memcpy((u8 *)priv->base + OFFSET_SPILDAT, dout, len); + + /* write: set the data direction bit to 1 */ + value = readb(priv->base + OFFSET_SPIMCTRL); + value |= (1 << 3); + writeb(value, priv->base + OFFSET_SPIMCTRL); + + /* set the data byte count */ + writeb(len, priv->base + OFFSET_SPIDCNT); + + /* set the start bit */ + value = readb(priv->base + OFFSET_SPIMCTRL); + value |= SPIMCTRL_START; + writeb(value, priv->base + OFFSET_SPIMCTRL); + + /* wait busy bit is cleared */ + do { + value = readb(priv->base + OFFSET_SPIMCTRL); + } while (value & SPIMCTRL_BUSY); + + return 0; + } + + /* if din !=null, start and read data */ + if (uchar_in) { + read_ptr = 0; + + while (read_ptr < len) { + read_len = len - read_ptr; + if (read_len > GXP_SPILDAT_SIZE) + read_len = GXP_SPILDAT_SIZE; + + /* read: set the data direction bit to 0 */ + value = readb(priv->base + OFFSET_SPIMCTRL); + value &= ~(1 << 3); + writeb(value, priv->base + OFFSET_SPIMCTRL); + + /* set the data byte count */ + writeb(read_len, priv->base + OFFSET_SPIDCNT); + + /* set the start bit */ + value = readb(priv->base + OFFSET_SPIMCTRL); + value |= SPIMCTRL_START; + writeb(value, priv->base + OFFSET_SPIMCTRL); + + /* wait busy bit is cleared */ + do { + value = readb(priv->base + OFFSET_SPIMCTRL); + } while (value & SPIMCTRL_BUSY); + + /* store the data bytes */ + memcpy(uchar_in + read_ptr, (u8 *)priv->base + OFFSET_SPILDAT, read_len); + /* update read_ptr and addr reg */ + read_ptr += read_len; + + addr = readl(priv->base + OFFSET_SPIADDR); + addr += read_len; + writel(addr, priv->base + OFFSET_SPIADDR); + } + + return 0; + } + return -2; +} + +static int gxp_spi_set_speed(struct udevice *dev, unsigned int speed) +{ + /* Accept any speed */ + return 0; +} + +static int gxp_spi_set_mode(struct udevice *dev, unsigned int mode) +{ + struct gxp_spi_priv *priv = dev_get_priv(dev->parent); + + priv->mode = mode; + + return 0; +} + +static int gxp_spi_claim_bus(struct udevice *dev) +{ + struct gxp_spi_priv *priv = dev_get_priv(dev->parent); + unsigned char cmd; + + spi_set_mode(priv, MANUAL_MODE); + + /* exit 4 bytes addr mode, uboot spi_flash only supports 3 byets address mode */ + cmd = 0xe9; + gxp_spi_xfer(dev, 1 * 8, &cmd, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + return 0; +} + +static int gxp_spi_release_bus(struct udevice *dev) +{ + struct gxp_spi_priv *priv = dev_get_priv(dev->parent); + + spi_set_mode(priv, AUTO_MODE); + + return 0; +} + +int gxp_spi_cs_info(struct udevice *bus, unsigned int cs, struct spi_cs_info *info) +{ + if (cs < GXP_SPI0_MAX_CHIPSELECT) + return 0; + else + return -ENODEV; +} + +static int gxp_spi_probe(struct udevice *bus) +{ + struct gxp_spi_priv *priv = dev_get_priv(bus); + + priv->base = dev_read_addr_ptr(bus); + if (!priv->base) + return -ENOENT; + + return 0; +} + +static int gxp_spi_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + + slave->max_write_size = GXP_SPILDAT_SIZE; + + return 0; +} + +static const struct dm_spi_ops gxp_spi_ops = { + .claim_bus = gxp_spi_claim_bus, + .release_bus = gxp_spi_release_bus, + .xfer = gxp_spi_xfer, + .set_speed = gxp_spi_set_speed, + .set_mode = gxp_spi_set_mode, + .cs_info = gxp_spi_cs_info, +}; + +static const struct udevice_id gxp_spi_ids[] = { + { .compatible = "hpe,gxp-spi" }, + { } +}; + +U_BOOT_DRIVER(gxp_spi) = { + .name = "gxp_spi", + .id = UCLASS_SPI, + .of_match = gxp_spi_ids, + .ops = &gxp_spi_ops, + .priv_auto = sizeof(struct gxp_spi_priv), + .probe = gxp_spi_probe, + .child_pre_probe = gxp_spi_child_pre_probe, +}; + diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index ea1691438be6efd9a1235807d97b4872dd3e27ac..828eab3d3427d7bae62d352d5fc7fff11d41a56e 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2012 - * Armando Visconti, ST Microelectronics, armando.visconti@st.com. + * Armando Visconti, STMicroelectronics, armando.visconti@st.com. * * (C) Copyright 2018 * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index ce558c4bc072e8da0a77df7dfc0691cea42bfcab..0cae3dfc778fad1f5f7140b528d81e5c130fc69a 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -45,8 +45,11 @@ #define RXF 0x20 #define RXE 0x24 #define RXC 0x28 +#define TFES 1 #define TFLETE 4 +#define TSSRS 6 #define RFMTE 5 +#define RSSRS 6 #define FAULTF 0x2c #define FAULTC 0x30 @@ -170,6 +173,11 @@ static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active) priv->rx_words = 16; read_fifo(priv); } + + /* wait until slave is deselected */ + while (!(readl(priv->base + TXF) & BIT(TSSRS)) || + !(readl(priv->base + RXF) & BIT(RSSRS))) + ; } } @@ -275,7 +283,7 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, { struct udevice *bus = dev->parent; struct synquacer_spi_priv *priv = dev_get_priv(bus); - u32 val, words, busy; + u32 val, words, busy = 0; val = readl(priv->base + FIFOCFG); val |= (1 << RX_FLUSH); @@ -323,9 +331,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, writel(~0, priv->base + RXC); /* Trigger */ - val = readl(priv->base + DMSTART); - val |= BIT(TRIGGER); - writel(val, priv->base + DMSTART); + if (flags & SPI_XFER_BEGIN) { + val = readl(priv->base + DMSTART); + val |= BIT(TRIGGER); + writel(val, priv->base + DMSTART); + } while (busy & (BIT(RXBIT) | BIT(TXBIT))) { if (priv->rx_words) @@ -336,13 +346,10 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, if (priv->tx_words) { write_fifo(priv); } else { - u32 len; - - do { /* wait for shifter to empty out */ + /* wait for shifter to empty out */ + while (!(readl(priv->base + TXF) & BIT(TFES))) cpu_relax(); - len = readl(priv->base + DMSTATUS); - len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; - } while (tx_buf && len); + busy &= ~BIT(TXBIT); } } diff --git a/drivers/tee/optee/rpmb.c b/drivers/tee/optee/rpmb.c index 0804fc963cf53059de42fd243153dff8e6a79f6b..cf5e0a08e619b295aa8b4ac70766da3cdbadd23f 100644 --- a/drivers/tee/optee/rpmb.c +++ b/drivers/tee/optee/rpmb.c @@ -72,6 +72,10 @@ static struct mmc *get_mmc(struct optee_private *priv, int dev_id) debug("Cannot find RPMB device\n"); return NULL; } + if (mmc_init(mmc)) { + log(LOGC_BOARD, LOGL_ERR, "%s:MMC device %d init failed\n", __func__, dev_id); + return NULL; + } if (!(mmc->version & MMC_VERSION_MMC)) { debug("Device id %d is not an eMMC device\n", dev_id); return NULL; @@ -104,6 +108,11 @@ static u32 rpmb_get_dev_info(u16 dev_id, struct rpmb_dev_info *info) if (!mmc) return TEE_ERROR_ITEM_NOT_FOUND; + if (mmc_init(mmc)) { + log(LOGC_BOARD, LOGL_ERR, "%s:MMC device %d init failed\n", __func__, dev_id); + return TEE_ERROR_NOT_SUPPORTED; + } + if (!mmc->ext_csd) return TEE_ERROR_GENERIC; diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 7b8ab56ed3239d86e3554285b60771f577f60735..20b5af7e260f6e5fbcbd39c81be994d8b14445e7 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER Enables support for the Designware APB Timer driver. This timer is present on Altera SoCFPGA SoCs. +config GXP_TIMER + bool "HPE GXP Timer" + depends on TIMER + help + Enables support for the GXP Timer driver. This timer is + present on HPE GXP SoCs. + config MPC83XX_TIMER bool "MPC83xx timer support" depends on TIMER @@ -272,4 +279,13 @@ config IMX_GPT_TIMER Select this to enable support for the timer found on NXP i.MX devices. +config XILINX_TIMER + bool "Xilinx timer support" + depends on TIMER + select REGMAP + select SPL_REGMAP if SPL + help + Select this to enable support for the timer found on + any Xilinx boards (axi timer). + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index b2f002d597892bbcbf14ec38125187fb917d8e53..d9822a5370099d0094bac628075c4d10faa3a9da 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o +obj-$(CONFIG_GXP_TIMER) += gxp-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o @@ -27,3 +28,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o +obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c new file mode 100644 index 0000000000000000000000000000000000000000..6f316bc8c5c41dca5ef38eb6c6439cdb445c90e2 --- /dev/null +++ b/drivers/timer/gxp-timer.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GXP timer driver + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins + * Author: Jean-Marie Verdun + */ + +#include +#include +#include +#include + +#define USTIMELO 0x18 +#define USTIMEHI 0x1C + +struct gxp_timer_priv { + void __iomem *base; +}; + +static u64 gxp_timer_get_count(struct udevice *dev) +{ + struct gxp_timer_priv *priv = dev_get_priv(dev); + u64 val; + + val = readl(priv->base + USTIMEHI); + val = (val << 32) | readl(priv->base + USTIMELO); + + return val; +} + +static int gxp_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct gxp_timer_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + uc_priv->clock_rate = 1000000; + + return 0; +} + +static const struct timer_ops gxp_timer_ops = { + .get_count = gxp_timer_get_count, +}; + +static const struct udevice_id gxp_timer_ids[] = { + { .compatible = "hpe,gxp-timer" }, + {} +}; + +U_BOOT_DRIVER(gxp_timer) = { + .name = "gxp-timer", + .id = UCLASS_TIMER, + .of_match = gxp_timer_ids, + .priv_auto = sizeof(struct gxp_timer_priv), + .probe = gxp_timer_probe, + .ops = &gxp_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c index 25a6108fef2cbc24138fd1c4082e1c5e7577d809..aa2e4360c1bb31f626306c7a9cfd6561bd0f3793 100644 --- a/drivers/timer/omap-timer.c +++ b/drivers/timer/omap-timer.c @@ -11,6 +11,7 @@ #include #include #include +#include #include /* Timer register bits */ @@ -61,13 +62,13 @@ static int omap_timer_probe(struct udevice *dev) if (!uc_priv->clock_rate) uc_priv->clock_rate = V_SCLK; - uc_priv->clock_rate /= (2 << CONFIG_SYS_PTV); + uc_priv->clock_rate /= (2 << SYS_PTV); /* start the counter ticking up, reload value on overflow */ writel(0, &priv->regs->tldr); writel(0, &priv->regs->tcrr); /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD | + writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD | TCLR_START, &priv->regs->tclr); return 0; diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c new file mode 100644 index 0000000000000000000000000000000000000000..75b4473b6397737355196b3b7c5378ad39844d52 --- /dev/null +++ b/drivers/timer/xilinx-timer.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 Advanced Micro Devices, Inc + * Michal Simek + * + * (C) Copyright 2007 Michal Simek + * Michal SIMEK + */ + +#include +#include +#include +#include +#include + +#define TIMER_ENABLE_ALL 0x400 /* ENALL */ +#define TIMER_PWM 0x200 /* PWMA0 */ +#define TIMER_INTERRUPT 0x100 /* T0INT */ +#define TIMER_ENABLE 0x080 /* ENT0 */ +#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ +#define TIMER_RESET 0x020 /* LOAD0 */ +#define TIMER_RELOAD 0x010 /* ARHT0 */ +#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ +#define TIMER_EXT_COMPARE 0x004 /* GENT0 */ +#define TIMER_DOWN_COUNT 0x002 /* UDT0 */ +#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ + +#define TIMER_CONTROL_OFFSET 0 +#define TIMER_LOADREG_OFFSET 4 +#define TIMER_COUNTER_OFFSET 8 + +struct xilinx_timer_priv { + struct regmap *regs; +}; + +static u64 xilinx_timer_get_count(struct udevice *dev) +{ + struct xilinx_timer_priv *priv = dev_get_priv(dev); + u32 value; + + regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value); + + return value; +} + +static int xilinx_timer_probe(struct udevice *dev) +{ + struct xilinx_timer_priv *priv = dev_get_priv(dev); + int ret; + + /* uc_priv->clock_rate has already clock rate */ + ret = regmap_init_mem(dev_ofnode(dev), &priv->regs); + if (ret) { + dev_dbg(dev, "failed to get regbase of timer\n"); + return ret; + } + + regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0); + regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET); + regmap_write(priv->regs, TIMER_CONTROL_OFFSET, + TIMER_ENABLE | TIMER_RELOAD); + + return 0; +} + +static const struct timer_ops xilinx_timer_ops = { + .get_count = xilinx_timer_get_count, +}; + +static const struct udevice_id xilinx_timer_ids[] = { + { .compatible = "xlnx,xps-timer-1.00.a" }, + {} +}; + +U_BOOT_DRIVER(xilinx_timer) = { + .name = "xilinx_timer", + .id = UCLASS_TIMER, + .of_match = xilinx_timer_ids, + .priv_auto = sizeof(struct xilinx_timer_priv), + .probe = xilinx_timer_probe, + .ops = &xilinx_timer_ops, +}; diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c index 4d7a2acd8e54a12b0d2889c5a30e2f32968521a2..00b8cd368b1af569e5c50e2188628fad74dfa62b 100644 --- a/drivers/usb/common/fsl-dt-fixup.c +++ b/drivers/usb/common/fsl-dt-fixup.c @@ -16,10 +16,6 @@ #include #include -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /* USB Controllers */ #define FSL_USB2_MPH "fsl-usb2-mph" #define FSL_USB2_DR "fsl-usb2-dr" diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c index cc80f671337974a91bf7da269090ad917350d716..01b2b41cce92ac36a2537f2da6a2059bf304c2c9 100644 --- a/drivers/usb/emul/sandbox_flash.c +++ b/drivers/usb/emul/sandbox_flash.c @@ -228,9 +228,9 @@ static void handle_read(struct sandbox_flash_priv *priv, ulong lba, ulong transfer_len) { debug("%s: lba=%lx, transfer_len=%lx\n", __func__, lba, transfer_len); + priv->read_len = transfer_len; if (priv->fd != -1) { os_lseek(priv->fd, lba * SANDBOX_FLASH_BLOCK_LEN, OS_SEEK_SET); - priv->read_len = transfer_len; setup_response(priv, priv->buff, transfer_len * SANDBOX_FLASH_BLOCK_LEN); } else { @@ -336,6 +336,9 @@ static int sandbox_flash_bulk(struct udevice *dev, struct usb_device *udev, if (priv->read_len) { ulong bytes_read; + if (priv->fd == -1) + return -EIO; + bytes_read = os_read(priv->fd, buff, len); if (bytes_read != len) return -EIO; diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 8c6cf47404f343da3e554c69a4a499e34d6da099..da9c9e3f10d496fbd46ac85c31a0a47eadb8ee13 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -93,6 +93,11 @@ config USB_GADGET_DWC2_OTG if USB_GADGET_DWC2_OTG +config USB_GADGET_DWC2_OTG_PHY + bool "DesignWare USB2.0 HS OTG PHY" + help + Enable the DesignWare USB2.0 HS OTG physical device interface. + config USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 bool "DesignWare USB2.0 HS OTG controller 8-bit PHY bus width" help diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index d5d891b20539b3ebac37ec4b4f0b79d2feac5c78..306dd3127f41297f6098a3f91b5f9f1bfa4246ad 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -37,13 +37,11 @@ ifdef CONFIG_USB_ETHER obj-y += ether.o obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o obj-$(CONFIG_CI_UDC) += ci_udc.o -obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o else # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o -obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif endif diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index 7fc5d27d436f837c35458ba4384473ce77907676..41a6e8cb7d34caf0c90dbbc1bc2e325d36a1e73e 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -4,7 +4,7 @@ * TI OMAP1510 USB bus interface driver * * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #include diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 01337d6511b3e4c0107ca0b7ffae4e106ba92eba..bb0d2971d06b0b7bdd19698011202e9eb04585e5 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -79,12 +79,6 @@ static int ep_matches( */ if ('s' == tmp[2]) /* == "-iso" */ return 0; - /* for now, avoid PXA "interrupt-in"; - * it's documented as never using DATA1. - */ - if (gadget_is_pxa(gadget) - && 'i' == tmp[1]) - return 0; break; case USB_ENDPOINT_XFER_BULK: if ('b' != tmp[1]) /* != "-bulk" */ diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 430732865723f2e7eb9a8bfc1a39335bfcad4ce5..abb5332f1394f5269423a88d5d90ab55a0589296 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -1048,13 +1048,6 @@ static int eth_set_config(struct eth_dev *dev, unsigned number, int result = 0; struct usb_gadget *gadget = dev->gadget; - if (gadget_is_sa1100(gadget) - && dev->config - && dev->tx_qlen != 0) { - /* tx fifo is full, but we can't clear it...*/ - pr_err("can't change configurations"); - return -ESPIPE; - } eth_reset_config(dev); switch (number) { @@ -1325,24 +1318,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (!cdc_active(dev) && wIndex != 0) break; - /* - * PXA hardware partially handles SET_INTERFACE; - * we need to kluge around that interference. - */ - if (gadget_is_pxa(gadget)) { - value = eth_set_config(dev, DEV_CONFIG_VALUE, - GFP_ATOMIC); - /* - * PXA25x driver use non-CDC ethernet gadget. - * But only _CDC and _RNDIS code can signalize - * that network is working. So we signalize it - * here. - */ - dev->network_started = 1; - debug("USB network up!\n"); - goto done_set_intf; - } - #ifdef CONFIG_USB_ETH_CDC switch (wIndex) { case 0: /* control/master intf */ @@ -1386,8 +1361,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) */ debug("set_interface ignored!\n"); #endif /* CONFIG_USB_ETH_CDC */ - -done_set_intf: break; case USB_REQ_GET_INTERFACE: if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE) @@ -2032,24 +2005,13 @@ static int eth_bind(struct usb_gadget *gadget) * standard protocol is _strongly_ preferred for interop purposes. * (By everyone except Microsoft.) */ - if (gadget_is_pxa(gadget)) { - /* pxa doesn't support altsettings */ - cdc = 0; - } else if (gadget_is_musbhdrc(gadget)) { + if (gadget_is_musbhdrc(gadget)) { /* reduce tx dma overhead by avoiding special cases */ zlp = 0; } else if (gadget_is_sh(gadget)) { /* sh doesn't support multiple interfaces or configs */ cdc = 0; rndis = 0; - } else if (gadget_is_sa1100(gadget)) { - /* hardware can't write zlps */ - zlp = 0; - /* - * sa1100 CAN do CDC, without status endpoint ... we use - * non-CDC to be compatible with ARM Linux-2.4 "usb-eth". - */ - cdc = 0; } gcnum = usb_gadget_controller_number(gadget); diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 06e6a4894954e463d1a788ef94479d61a9bafd22..abc6dc7f89fc032b150433a1e913af30c603e4e5 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -32,12 +32,6 @@ #define gadget_is_dummy(g) 0 #endif -#ifdef CONFIG_USB_GADGET_PXA2XX -#define gadget_is_pxa(g) (!strcmp("pxa2xx_udc", (g)->name)) -#else -#define gadget_is_pxa(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_GOKU #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name)) #else @@ -51,13 +45,6 @@ #define gadget_is_sh(g) 0 #endif -/* not yet stable on 2.6 (would help "original Zaurus") */ -#ifdef CONFIG_USB_GADGET_SA1100 -#define gadget_is_sa1100(g) (!strcmp("sa1100_udc", (g)->name)) -#else -#define gadget_is_sa1100(g) 0 -#endif - /* handhelds.org tree (?) */ #ifdef CONFIG_USB_GADGET_MQ11XX #define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name)) @@ -78,13 +65,6 @@ #define gadget_is_n9604(g) 0 #endif -/* various unstable versions available */ -#ifdef CONFIG_USB_GADGET_PXA27X -#define gadget_is_pxa27x(g) (!strcmp("pxa27x_udc", (g)->name)) -#else -#define gadget_is_pxa27x(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_ATMEL_USBA #define gadget_is_atmel_usba(g) (!strcmp("atmel_usba_udc", (g)->name)) #else @@ -194,12 +174,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x01; else if (gadget_is_dummy(gadget)) return 0x02; - else if (gadget_is_pxa(gadget)) - return 0x03; else if (gadget_is_sh(gadget)) return 0x04; - else if (gadget_is_sa1100(gadget)) - return 0x05; else if (gadget_is_goku(gadget)) return 0x06; else if (gadget_is_mq11xx(gadget)) @@ -208,8 +184,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x08; else if (gadget_is_n9604(gadget)) return 0x09; - else if (gadget_is_pxa27x(gadget)) - return 0x10; else if (gadget_is_at91(gadget)) return 0x12; else if (gadget_is_imx(gadget)) diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c deleted file mode 100644 index d19ac1d035318d2d31c6a0bd4c634b098350e70c..0000000000000000000000000000000000000000 --- a/drivers/usb/gadget/pxa25x_udc.c +++ /dev/null @@ -1,2049 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Intel PXA25x and IXP4xx on-chip full speed USB device controllers - * - * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) - * Copyright (C) 2003 Robert Schwebel, Pengutronix - * Copyright (C) 2003 Benedikt Spranger, Pengutronix - * Copyright (C) 2003 David Brownell - * Copyright (C) 2003 Joshua Wise - * Copyright (C) 2012 Lukasz Dalek - * - * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); - */ - -#define CONFIG_USB_PXA25X_SMALL -#define DRIVER_NAME "pxa25x_udc_linux" -#define ARCH_HAS_PREFETCH - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "pxa25x_udc.h" - -/* - * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x - * series processors. The UDC for the IXP 4xx series is very similar. - * There are fifteen endpoints, in addition to ep0. - * - * Such controller drivers work with a gadget driver. The gadget driver - * returns descriptors, implements configuration and data protocols used - * by the host to interact with this device, and allocates endpoints to - * the different protocol interfaces. The controller driver virtualizes - * usb hardware so that the gadget drivers will be more portable. - * - * This UDC hardware wants to implement a bit too much USB protocol, so - * it constrains the sorts of USB configuration change events that work. - * The errata for these chips are misleading; some "fixed" bugs from - * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. - * - * Note that the UDC hardware supports DMA (except on IXP) but that's - * not used here. IN-DMA (to host) is simple enough, when the data is - * suitably aligned (16 bytes) ... the network stack doesn't do that, - * other software can. OUT-DMA is buggy in most chip versions, as well - * as poorly designed (data toggle not automatic). So this driver won't - * bother using DMA. (Mostly-working IN-DMA support was available in - * kernels before 2.6.23, but was never enabled or well tested.) - */ - -#define DRIVER_VERSION "18-August-2012" -#define DRIVER_DESC "PXA 25x USB Device Controller driver" - -static const char driver_name[] = "pxa25x_udc"; -static const char ep0name[] = "ep0"; - -/* Watchdog */ -static inline void start_watchdog(struct pxa25x_udc *udc) -{ - debug("Started watchdog\n"); - udc->watchdog.base = get_timer(0); - udc->watchdog.running = 1; -} - -static inline void stop_watchdog(struct pxa25x_udc *udc) -{ - udc->watchdog.running = 0; - debug("Stopped watchdog\n"); -} - -static inline void test_watchdog(struct pxa25x_udc *udc) -{ - if (!udc->watchdog.running) - return; - - debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base), - udc->watchdog.period); - - if (get_timer(udc->watchdog.base) >= udc->watchdog.period) { - stop_watchdog(udc); - udc->watchdog.function(udc); - } -} - -static void udc_watchdog(struct pxa25x_udc *dev) -{ - uint32_t udccs0 = readl(&dev->regs->udccs[0]); - - debug("Fired up udc_watchdog\n"); - - local_irq_disable(); - if (dev->ep0state == EP0_STALL - && (udccs0 & UDCCS0_FST) == 0 - && (udccs0 & UDCCS0_SST) == 0) { - writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]); - debug("ep0 re-stall\n"); - start_watchdog(dev); - } - local_irq_enable(); -} - -#ifdef DEBUG - -static const char * const state_name[] = { - "EP0_IDLE", - "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", - "EP0_END_XFER", "EP0_STALL" -}; - -static void -dump_udccr(const char *label) -{ - u32 udccr = readl(&UDC_REGS->udccr); - debug("%s %02X =%s%s%s%s%s%s%s%s\n", - label, udccr, - (udccr & UDCCR_REM) ? " rem" : "", - (udccr & UDCCR_RSTIR) ? " rstir" : "", - (udccr & UDCCR_SRM) ? " srm" : "", - (udccr & UDCCR_SUSIR) ? " susir" : "", - (udccr & UDCCR_RESIR) ? " resir" : "", - (udccr & UDCCR_RSM) ? " rsm" : "", - (udccr & UDCCR_UDA) ? " uda" : "", - (udccr & UDCCR_UDE) ? " ude" : ""); -} - -static void -dump_udccs0(const char *label) -{ - u32 udccs0 = readl(&UDC_REGS->udccs[0]); - - debug("%s %s %02X =%s%s%s%s%s%s%s%s\n", - label, state_name[the_controller->ep0state], udccs0, - (udccs0 & UDCCS0_SA) ? " sa" : "", - (udccs0 & UDCCS0_RNE) ? " rne" : "", - (udccs0 & UDCCS0_FST) ? " fst" : "", - (udccs0 & UDCCS0_SST) ? " sst" : "", - (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", - (udccs0 & UDCCS0_FTF) ? " ftf" : "", - (udccs0 & UDCCS0_IPR) ? " ipr" : "", - (udccs0 & UDCCS0_OPR) ? " opr" : ""); -} - -static void -dump_state(struct pxa25x_udc *dev) -{ - u32 tmp; - unsigned i; - - debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", - state_name[dev->ep0state], - readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0), - readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0), - readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl)); - dump_udccr("udccr"); - if (dev->has_cfr) { - tmp = readl(&UDC_REGS->udccfr); - debug("udccfr %02X =%s%s\n", tmp, - (tmp & UDCCFR_AREN) ? " aren" : "", - (tmp & UDCCFR_ACM) ? " acm" : ""); - } - - if (!dev->driver) { - debug("no gadget driver bound\n"); - return; - } else - debug("ep0 driver '%s'\n", "ether"); - - dump_udccs0("udccs0"); - debug("ep0 IN %lu/%lu, OUT %lu/%lu\n", - dev->stats.write.bytes, dev->stats.write.ops, - dev->stats.read.bytes, dev->stats.read.ops); - - for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { - if (dev->ep[i].desc == NULL) - continue; - debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs); - } -} - -#else /* DEBUG */ - -static inline void dump_udccr(const char *label) { } -static inline void dump_udccs0(const char *label) { } -static inline void dump_state(struct pxa25x_udc *dev) { } - -#endif /* DEBUG */ - -/* - * --------------------------------------------------------------------------- - * endpoint related parts of the api to the usb controller hardware, - * used by gadget driver; and the inner talker-to-hardware core. - * --------------------------------------------------------------------------- - */ - -static void pxa25x_ep_fifo_flush(struct usb_ep *ep); -static void nuke(struct pxa25x_ep *, int status); - -/* one GPIO should control a D+ pullup, so host sees this device (or not) */ -static void pullup_off(void) -{ - struct pxa2xx_udc_mach_info *mach = the_controller->mach; - - if (mach->udc_command) - mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); -} - -static void pullup_on(void) -{ - struct pxa2xx_udc_mach_info *mach = the_controller->mach; - - if (mach->udc_command) - mach->udc_command(PXA2XX_UDC_CMD_CONNECT); -} - -static void pio_irq_enable(int bEndpointAddress) -{ - bEndpointAddress &= 0xf; - if (bEndpointAddress < 8) { - clrbits_le32(&the_controller->regs->uicr0, - 1 << bEndpointAddress); - } else { - bEndpointAddress -= 8; - clrbits_le32(&the_controller->regs->uicr1, - 1 << bEndpointAddress); - } -} - -static void pio_irq_disable(int bEndpointAddress) -{ - bEndpointAddress &= 0xf; - if (bEndpointAddress < 8) { - setbits_le32(&the_controller->regs->uicr0, - 1 << bEndpointAddress); - } else { - bEndpointAddress -= 8; - setbits_le32(&the_controller->regs->uicr1, - 1 << bEndpointAddress); - } -} - -static inline void udc_set_mask_UDCCR(int mask) -{ - /* - * The UDCCR reg contains mask and interrupt status bits, - * so using '|=' isn't safe as it may ack an interrupt. - */ - const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; - - mask &= mask_bits; - clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); -} - -static inline void udc_clear_mask_UDCCR(int mask) -{ - const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; - - mask = ~mask & mask_bits; - clrbits_le32(&the_controller->regs->udccr, ~mask); -} - -static inline void udc_ack_int_UDCCR(int mask) -{ - const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE; - - mask &= ~mask_bits; - clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask); -} - -/* - * endpoint enable/disable - * - * we need to verify the descriptors used to enable endpoints. since pxa25x - * endpoint configurations are fixed, and are pretty much always enabled, - * there's not a lot to manage here. - * - * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, - * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except - * for a single interface (with only the default altsetting) and for gadget - * drivers that don't halt endpoints (not reset by set_interface). that also - * means that if you use ISO, you must violate the USB spec rule that all - * iso endpoints must be in non-default altsettings. - */ -static int pxa25x_ep_enable(struct usb_ep *_ep, - const struct usb_endpoint_descriptor *desc) -{ - struct pxa25x_ep *ep; - struct pxa25x_udc *dev; - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (!_ep || !desc || ep->desc || _ep->name == ep0name - || desc->bDescriptorType != USB_DT_ENDPOINT - || ep->bEndpointAddress != desc->bEndpointAddress - || ep->fifo_size < - le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) { - printf("%s, bad ep or descriptor\n", __func__); - return -EINVAL; - } - - /* xfer types must match, except that interrupt ~= bulk */ - if (ep->bmAttributes != desc->bmAttributes - && ep->bmAttributes != USB_ENDPOINT_XFER_BULK - && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { - printf("%s, %s type mismatch\n", __func__, _ep->name); - return -EINVAL; - } - - /* hardware _could_ do smaller, but driver doesn't */ - if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK - && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) - != BULK_FIFO_SIZE) - || !get_unaligned(&desc->wMaxPacketSize)) { - printf("%s, bad %s maxpacket\n", __func__, _ep->name); - return -ERANGE; - } - - dev = ep->dev; - if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { - printf("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - ep->desc = desc; - ep->stopped = 0; - ep->pio_irqs = 0; - ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)); - - /* flush fifo (mostly for OUT buffers) */ - pxa25x_ep_fifo_flush(_ep); - - /* ... reset halt state too, if we could ... */ - - debug("enabled %s\n", _ep->name); - return 0; -} - -static int pxa25x_ep_disable(struct usb_ep *_ep) -{ - struct pxa25x_ep *ep; - unsigned long flags; - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (!_ep || !ep->desc) { - printf("%s, %s not enabled\n", __func__, - _ep ? ep->ep.name : NULL); - return -EINVAL; - } - local_irq_save(flags); - - nuke(ep, -ESHUTDOWN); - - /* flush fifo (mostly for IN buffers) */ - pxa25x_ep_fifo_flush(_ep); - - ep->desc = NULL; - ep->stopped = 1; - - local_irq_restore(flags); - debug("%s disabled\n", _ep->name); - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* - * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers - * must still pass correctly initialized endpoints, since other controller - * drivers may care about how it's currently set up (dma issues etc). - */ - -/* - * pxa25x_ep_alloc_request - allocate a request data structure - */ -static struct usb_request * -pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) -{ - struct pxa25x_request *req; - - req = kzalloc(sizeof(*req), gfp_flags); - if (!req) - return NULL; - - INIT_LIST_HEAD(&req->queue); - return &req->req; -} - - -/* - * pxa25x_ep_free_request - deallocate a request data structure - */ -static void -pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) -{ - struct pxa25x_request *req; - - req = container_of(_req, struct pxa25x_request, req); - WARN_ON(!list_empty(&req->queue)); - kfree(req); -} - -/*-------------------------------------------------------------------------*/ - -/* - * done - retire a request; caller blocked irqs - */ -static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) -{ - unsigned stopped = ep->stopped; - - list_del_init(&req->queue); - - if (likely(req->req.status == -EINPROGRESS)) - req->req.status = status; - else - status = req->req.status; - - if (status && status != -ESHUTDOWN) - debug("complete %s req %p stat %d len %u/%u\n", - ep->ep.name, &req->req, status, - req->req.actual, req->req.length); - - /* don't modify queue heads during completion callback */ - ep->stopped = 1; - req->req.complete(&ep->ep, &req->req); - ep->stopped = stopped; -} - - -static inline void ep0_idle(struct pxa25x_udc *dev) -{ - dev->ep0state = EP0_IDLE; -} - -static int -write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max) -{ - u8 *buf; - unsigned length, count; - - debug("%s(): uddr %p\n", __func__, uddr); - - buf = req->req.buf + req->req.actual; - prefetch(buf); - - /* how big will this packet be? */ - length = min(req->req.length - req->req.actual, max); - req->req.actual += length; - - count = length; - while (likely(count--)) - writeb(*buf++, uddr); - - return length; -} - -/* - * write to an IN endpoint fifo, as many packets as possible. - * irqs will use this to write the rest later. - * caller guarantees at least one packet buffer is ready (or a zlp). - */ -static int -write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) -{ - unsigned max; - - max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize)); - do { - unsigned count; - int is_last, is_short; - - count = write_packet(ep->reg_uddr, req, max); - - /* last packet is usually short (or a zlp) */ - if (unlikely(count != max)) - is_last = is_short = 1; - else { - if (likely(req->req.length != req->req.actual) - || req->req.zero) - is_last = 0; - else - is_last = 1; - /* interrupt/iso maxpacket may not fill the fifo */ - is_short = unlikely(max < ep->fifo_size); - } - - debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n", - ep->ep.name, count, - is_last ? "/L" : "", is_short ? "/S" : "", - req->req.length - req->req.actual, req); - - /* - * let loose that packet. maybe try writing another one, - * double buffering might work. TSP, TPC, and TFS - * bit values are the same for all normal IN endpoints. - */ - writel(UDCCS_BI_TPC, ep->reg_udccs); - if (is_short) - writel(UDCCS_BI_TSP, ep->reg_udccs); - - /* requests complete when all IN data is in the FIFO */ - if (is_last) { - done(ep, req, 0); - if (list_empty(&ep->queue)) - pio_irq_disable(ep->bEndpointAddress); - return 1; - } - - /* - * TODO experiment: how robust can fifo mode tweaking be? - * double buffering is off in the default fifo mode, which - * prevents TFS from being set here. - */ - - } while (readl(ep->reg_udccs) & UDCCS_BI_TFS); - return 0; -} - -/* - * caller asserts req->pending (ep0 irq status nyet cleared); starts - * ep0 data stage. these chips want very simple state transitions. - */ -static inline -void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) -{ - writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]); - writel(USIR0_IR0, &dev->regs->usir0); - dev->req_pending = 0; - debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n", - __func__, tag, readl(&dev->regs->udccs[0]), flags, - readl(&dev->regs->usir1), readl(&dev->regs->usir0)); -} - -static int -write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) -{ - unsigned count; - int is_short; - - count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE); - ep->dev->stats.write.bytes += count; - - /* last packet "must be" short (or a zlp) */ - is_short = (count != EP0_FIFO_SIZE); - - debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count, - req->req.length - req->req.actual, req); - - if (unlikely(is_short)) { - if (ep->dev->req_pending) - ep0start(ep->dev, UDCCS0_IPR, "short IN"); - else - writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]); - - count = req->req.length; - done(ep, req, 0); - ep0_idle(ep->dev); - - /* - * This seems to get rid of lost status irqs in some cases: - * host responds quickly, or next request involves config - * change automagic, or should have been hidden, or ... - * - * FIXME get rid of all udelays possible... - */ - if (count >= EP0_FIFO_SIZE) { - count = 100; - do { - if ((readl(&ep->dev->regs->udccs[0]) & - UDCCS0_OPR) != 0) { - /* clear OPR, generate ack */ - writel(UDCCS0_OPR, - &ep->dev->regs->udccs[0]); - break; - } - count--; - udelay(1); - } while (count); - } - } else if (ep->dev->req_pending) - ep0start(ep->dev, 0, "IN"); - - return is_short; -} - - -/* - * read_fifo - unload packet(s) from the fifo we use for usb OUT - * transfers and put them into the request. caller should have made - * sure there's at least one packet ready. - * - * returns true if the request completed because of short packet or the - * request buffer having filled (and maybe overran till end-of-packet). - */ -static int -read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) -{ - u32 udccs; - u8 *buf; - unsigned bufferspace, count, is_short; - - for (;;) { - /* - * make sure there's a packet in the FIFO. - * UDCCS_{BO,IO}_RPC are all the same bit value. - * UDCCS_{BO,IO}_RNE are all the same bit value. - */ - udccs = readl(ep->reg_udccs); - if (unlikely((udccs & UDCCS_BO_RPC) == 0)) - break; - buf = req->req.buf + req->req.actual; - prefetchw(buf); - bufferspace = req->req.length - req->req.actual; - - /* read all bytes from this packet */ - if (likely(udccs & UDCCS_BO_RNE)) { - count = 1 + (0x0ff & readl(ep->reg_ubcr)); - req->req.actual += min(count, bufferspace); - } else /* zlp */ - count = 0; - is_short = (count < ep->ep.maxpacket); - debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", - ep->ep.name, udccs, count, - is_short ? "/S" : "", - req, req->req.actual, req->req.length); - while (likely(count-- != 0)) { - u8 byte = readb(ep->reg_uddr); - - if (unlikely(bufferspace == 0)) { - /* - * this happens when the driver's buffer - * is smaller than what the host sent. - * discard the extra data. - */ - if (req->req.status != -EOVERFLOW) - printf("%s overflow %d\n", - ep->ep.name, count); - req->req.status = -EOVERFLOW; - } else { - *buf++ = byte; - bufferspace--; - } - } - writel(UDCCS_BO_RPC, ep->reg_udccs); - /* RPC/RSP/RNE could now reflect the other packet buffer */ - - /* iso is one request per packet */ - if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { - if (udccs & UDCCS_IO_ROF) - req->req.status = -EHOSTUNREACH; - /* more like "is_done" */ - is_short = 1; - } - - /* completion */ - if (is_short || req->req.actual == req->req.length) { - done(ep, req, 0); - if (list_empty(&ep->queue)) - pio_irq_disable(ep->bEndpointAddress); - return 1; - } - - /* finished that packet. the next one may be waiting... */ - } - return 0; -} - -/* - * special ep0 version of the above. no UBCR0 or double buffering; status - * handshaking is magic. most device protocols don't need control-OUT. - * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other - * protocols do use them. - */ -static int -read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req) -{ - u8 *buf, byte; - unsigned bufferspace; - - buf = req->req.buf + req->req.actual; - bufferspace = req->req.length - req->req.actual; - - while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) { - byte = (u8)readb(&ep->dev->regs->uddr0); - - if (unlikely(bufferspace == 0)) { - /* - * this happens when the driver's buffer - * is smaller than what the host sent. - * discard the extra data. - */ - if (req->req.status != -EOVERFLOW) - printf("%s overflow\n", ep->ep.name); - req->req.status = -EOVERFLOW; - } else { - *buf++ = byte; - req->req.actual++; - bufferspace--; - } - } - - writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]); - - /* completion */ - if (req->req.actual >= req->req.length) - return 1; - - /* finished that packet. the next one may be waiting... */ - return 0; -} - -/*-------------------------------------------------------------------------*/ - -static int -pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) -{ - struct pxa25x_request *req; - struct pxa25x_ep *ep; - struct pxa25x_udc *dev; - unsigned long flags; - - req = container_of(_req, struct pxa25x_request, req); - if (unlikely(!_req || !_req->complete || !_req->buf - || !list_empty(&req->queue))) { - printf("%s, bad params\n", __func__); - return -EINVAL; - } - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { - printf("%s, bad ep\n", __func__); - return -EINVAL; - } - - dev = ep->dev; - if (unlikely(!dev->driver - || dev->gadget.speed == USB_SPEED_UNKNOWN)) { - printf("%s, bogus device state\n", __func__); - return -ESHUTDOWN; - } - - /* - * iso is always one packet per request, that's the only way - * we can report per-packet status. that also helps with dma. - */ - if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC - && req->req.length > - le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize)))) - return -EMSGSIZE; - - debug_cond(NOISY, "%s queue req %p, len %d buf %p\n", - _ep->name, _req, _req->length, _req->buf); - - local_irq_save(flags); - - _req->status = -EINPROGRESS; - _req->actual = 0; - - /* kickstart this i/o queue? */ - if (list_empty(&ep->queue) && !ep->stopped) { - if (ep->desc == NULL/* ep0 */) { - unsigned length = _req->length; - - switch (dev->ep0state) { - case EP0_IN_DATA_PHASE: - dev->stats.write.ops++; - if (write_ep0_fifo(ep, req)) - req = NULL; - break; - - case EP0_OUT_DATA_PHASE: - dev->stats.read.ops++; - /* messy ... */ - if (dev->req_config) { - debug("ep0 config ack%s\n", - dev->has_cfr ? "" : " raced"); - if (dev->has_cfr) - writel(UDCCFR_AREN|UDCCFR_ACM - |UDCCFR_MB1, - &ep->dev->regs->udccfr); - done(ep, req, 0); - dev->ep0state = EP0_END_XFER; - local_irq_restore(flags); - return 0; - } - if (dev->req_pending) - ep0start(dev, UDCCS0_IPR, "OUT"); - if (length == 0 || - ((readl( - &ep->dev->regs->udccs[0]) - & UDCCS0_RNE) != 0 - && read_ep0_fifo(ep, req))) { - ep0_idle(dev); - done(ep, req, 0); - req = NULL; - } - break; - - default: - printf("ep0 i/o, odd state %d\n", - dev->ep0state); - local_irq_restore(flags); - return -EL2HLT; - } - /* can the FIFO can satisfy the request immediately? */ - } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { - if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0 - && write_fifo(ep, req)) - req = NULL; - } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0 - && read_fifo(ep, req)) { - req = NULL; - } - - if (likely(req && ep->desc)) - pio_irq_enable(ep->bEndpointAddress); - } - - /* pio or dma irq handler advances the queue. */ - if (likely(req != NULL)) - list_add_tail(&req->queue, &ep->queue); - local_irq_restore(flags); - - return 0; -} - - -/* - * nuke - dequeue ALL requests - */ -static void nuke(struct pxa25x_ep *ep, int status) -{ - struct pxa25x_request *req; - - /* called with irqs blocked */ - while (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, - struct pxa25x_request, - queue); - done(ep, req, status); - } - if (ep->desc) - pio_irq_disable(ep->bEndpointAddress); -} - - -/* dequeue JUST ONE request */ -static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) -{ - struct pxa25x_ep *ep; - struct pxa25x_request *req; - unsigned long flags; - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (!_ep || ep->ep.name == ep0name) - return -EINVAL; - - local_irq_save(flags); - - /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; - } - if (&req->req != _req) { - local_irq_restore(flags); - return -EINVAL; - } - - done(ep, req, -ECONNRESET); - - local_irq_restore(flags); - return 0; -} - -/*-------------------------------------------------------------------------*/ - -static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) -{ - struct pxa25x_ep *ep; - unsigned long flags; - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (unlikely(!_ep - || (!ep->desc && ep->ep.name != ep0name)) - || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { - printf("%s, bad ep\n", __func__); - return -EINVAL; - } - if (value == 0) { - /* - * this path (reset toggle+halt) is needed to implement - * SET_INTERFACE on normal hardware. but it can't be - * done from software on the PXA UDC, and the hardware - * forgets to do it as part of SET_INTERFACE automagic. - */ - printf("only host can clear %s halt\n", _ep->name); - return -EROFS; - } - - local_irq_save(flags); - - if ((ep->bEndpointAddress & USB_DIR_IN) != 0 - && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0 - || !list_empty(&ep->queue))) { - local_irq_restore(flags); - return -EAGAIN; - } - - /* FST bit is the same for control, bulk in, bulk out, interrupt in */ - writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs); - - /* ep0 needs special care */ - if (!ep->desc) { - start_watchdog(ep->dev); - ep->dev->req_pending = 0; - ep->dev->ep0state = EP0_STALL; - - /* and bulk/intr endpoints like dropping stalls too */ - } else { - unsigned i; - for (i = 0; i < 1000; i += 20) { - if (readl(ep->reg_udccs) & UDCCS_BI_SST) - break; - udelay(20); - } - } - local_irq_restore(flags); - - debug("%s halt\n", _ep->name); - return 0; -} - -static int pxa25x_ep_fifo_status(struct usb_ep *_ep) -{ - struct pxa25x_ep *ep; - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (!_ep) { - printf("%s, bad ep\n", __func__); - return -ENODEV; - } - /* pxa can't report unclaimed bytes from IN fifos */ - if ((ep->bEndpointAddress & USB_DIR_IN) != 0) - return -EOPNOTSUPP; - if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN - || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0) - return 0; - else - return (readl(ep->reg_ubcr) & 0xfff) + 1; -} - -static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) -{ - struct pxa25x_ep *ep; - - ep = container_of(_ep, struct pxa25x_ep, ep); - if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { - printf("%s, bad ep\n", __func__); - return; - } - - /* toggle and halt bits stay unchanged */ - - /* for OUT, just read and discard the FIFO contents. */ - if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { - while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0) - (void)readb(ep->reg_uddr); - return; - } - - /* most IN status is the same, but ISO can't stall */ - writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR - | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC - ? 0 : UDCCS_BI_SST), ep->reg_udccs); -} - - -static struct usb_ep_ops pxa25x_ep_ops = { - .enable = pxa25x_ep_enable, - .disable = pxa25x_ep_disable, - - .alloc_request = pxa25x_ep_alloc_request, - .free_request = pxa25x_ep_free_request, - - .queue = pxa25x_ep_queue, - .dequeue = pxa25x_ep_dequeue, - - .set_halt = pxa25x_ep_set_halt, - .fifo_status = pxa25x_ep_fifo_status, - .fifo_flush = pxa25x_ep_fifo_flush, -}; - - -/* --------------------------------------------------------------------------- - * device-scoped parts of the api to the usb controller hardware - * --------------------------------------------------------------------------- - */ - -static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) -{ - return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) | - (readl(&the_controller->regs->ufnrl) & 0xff); -} - -static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) -{ - /* host may not have enabled remote wakeup */ - if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0) - return -EHOSTUNREACH; - udc_set_mask_UDCCR(UDCCR_RSM); - return 0; -} - -static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); -static void udc_enable(struct pxa25x_udc *); -static void udc_disable(struct pxa25x_udc *); - -/* - * We disable the UDC -- and its 48 MHz clock -- whenever it's not - * in active use. - */ -static int pullup(struct pxa25x_udc *udc) -{ - if (udc->pullup) - pullup_on(); - else - pullup_off(); - - - int is_active = udc->pullup; - if (is_active) { - if (!udc->active) { - udc->active = 1; - udc_enable(udc); - } - } else { - if (udc->active) { - if (udc->gadget.speed != USB_SPEED_UNKNOWN) - stop_activity(udc, udc->driver); - udc_disable(udc); - udc->active = 0; - } - - } - return 0; -} - -/* VBUS reporting logically comes from a transceiver */ -static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) -{ - struct pxa25x_udc *udc; - - udc = container_of(_gadget, struct pxa25x_udc, gadget); - printf("vbus %s\n", is_active ? "supplied" : "inactive"); - pullup(udc); - return 0; -} - -/* drivers may have software control over D+ pullup */ -static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) -{ - struct pxa25x_udc *udc; - - udc = container_of(_gadget, struct pxa25x_udc, gadget); - - /* not all boards support pullup control */ - if (!udc->mach->udc_command) - return -EOPNOTSUPP; - - udc->pullup = (is_active != 0); - pullup(udc); - return 0; -} - -/* - * boards may consume current from VBUS, up to 100-500mA based on config. - * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs - * violate USB specs. - */ -static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) -{ - return -EOPNOTSUPP; -} - -static const struct usb_gadget_ops pxa25x_udc_ops = { - .get_frame = pxa25x_udc_get_frame, - .wakeup = pxa25x_udc_wakeup, - .vbus_session = pxa25x_udc_vbus_session, - .pullup = pxa25x_udc_pullup, - .vbus_draw = pxa25x_udc_vbus_draw, -}; - -/*-------------------------------------------------------------------------*/ - -/* - * udc_disable - disable USB device controller - */ -static void udc_disable(struct pxa25x_udc *dev) -{ - /* block all irqs */ - udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); - writel(0xff, &dev->regs->uicr0); - writel(0xff, &dev->regs->uicr1); - writel(UFNRH_SIM, &dev->regs->ufnrh); - - /* if hardware supports it, disconnect from usb */ - pullup_off(); - - udc_clear_mask_UDCCR(UDCCR_UDE); - - ep0_idle(dev); - dev->gadget.speed = USB_SPEED_UNKNOWN; -} - -/* - * udc_reinit - initialize software state - */ -static void udc_reinit(struct pxa25x_udc *dev) -{ - u32 i; - - /* device/ep0 records init */ - INIT_LIST_HEAD(&dev->gadget.ep_list); - INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); - dev->ep0state = EP0_IDLE; - - /* basic endpoint records init */ - for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { - struct pxa25x_ep *ep = &dev->ep[i]; - - if (i != 0) - list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); - - ep->desc = NULL; - ep->stopped = 0; - INIT_LIST_HEAD(&ep->queue); - ep->pio_irqs = 0; - } - - /* the rest was statically initialized, and is read-only */ -} - -/* - * until it's enabled, this UDC should be completely invisible - * to any USB host. - */ -static void udc_enable(struct pxa25x_udc *dev) -{ - debug("udc: enabling udc\n"); - - udc_clear_mask_UDCCR(UDCCR_UDE); - - /* - * Try to clear these bits before we enable the udc. - * Do not touch reset ack bit, we would take care of it in - * interrupt handle routine - */ - udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR); - - ep0_idle(dev); - dev->gadget.speed = USB_SPEED_UNKNOWN; - dev->stats.irqs = 0; - - /* - * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: - * - enable UDC - * - if RESET is already in progress, ack interrupt - * - unmask reset interrupt - */ - udc_set_mask_UDCCR(UDCCR_UDE); - if (!(readl(&dev->regs->udccr) & UDCCR_UDA)) - udc_ack_int_UDCCR(UDCCR_RSTIR); - - if (dev->has_cfr /* UDC_RES2 is defined */) { - /* - * pxa255 (a0+) can avoid a set_config race that could - * prevent gadget drivers from configuring correctly - */ - writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr); - } - - /* enable suspend/resume and reset irqs */ - udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); - - /* enable ep0 irqs */ - clrbits_le32(&dev->regs->uicr0, UICR0_IM0); - - /* if hardware supports it, pullup D+ and wait for reset */ - pullup_on(); -} - -static inline void clear_ep_state(struct pxa25x_udc *dev) -{ - unsigned i; - - /* - * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint - * fifos, and pending transactions mustn't be continued in any case. - */ - for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) - nuke(&dev->ep[i], -ECONNABORTED); -} - -static void handle_ep0(struct pxa25x_udc *dev) -{ - u32 udccs0 = readl(&dev->regs->udccs[0]); - struct pxa25x_ep *ep = &dev->ep[0]; - struct pxa25x_request *req; - union { - struct usb_ctrlrequest r; - u8 raw[8]; - u32 word[2]; - } u; - - if (list_empty(&ep->queue)) - req = NULL; - else - req = list_entry(ep->queue.next, struct pxa25x_request, queue); - - /* clear stall status */ - if (udccs0 & UDCCS0_SST) { - nuke(ep, -EPIPE); - writel(UDCCS0_SST, &dev->regs->udccs[0]); - stop_watchdog(dev); - ep0_idle(dev); - } - - /* previous request unfinished? non-error iff back-to-back ... */ - if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { - nuke(ep, 0); - stop_watchdog(dev); - ep0_idle(dev); - } - - switch (dev->ep0state) { - case EP0_IDLE: - /* late-breaking status? */ - udccs0 = readl(&dev->regs->udccs[0]); - - /* start control request? */ - if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) - == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { - int i; - - nuke(ep, -EPROTO); - - /* read SETUP packet */ - for (i = 0; i < 8; i++) { - if (unlikely(!(readl(&dev->regs->udccs[0]) & - UDCCS0_RNE))) { -bad_setup: - debug("SETUP %d!\n", i); - goto stall; - } - u.raw[i] = (u8)readb(&dev->regs->uddr0); - } - if (unlikely((readl(&dev->regs->udccs[0]) & - UDCCS0_RNE) != 0)) - goto bad_setup; - -got_setup: - debug("SETUP %02x.%02x v%04x i%04x l%04x\n", - u.r.bRequestType, u.r.bRequest, - le16_to_cpu(u.r.wValue), - le16_to_cpu(u.r.wIndex), - le16_to_cpu(u.r.wLength)); - - /* cope with automagic for some standard requests. */ - dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) - == USB_TYPE_STANDARD; - dev->req_config = 0; - dev->req_pending = 1; - switch (u.r.bRequest) { - /* hardware restricts gadget drivers here! */ - case USB_REQ_SET_CONFIGURATION: - debug("GOT SET_CONFIGURATION\n"); - if (u.r.bRequestType == USB_RECIP_DEVICE) { - /* - * reflect hardware's automagic - * up to the gadget driver. - */ -config_change: - dev->req_config = 1; - clear_ep_state(dev); - /* - * if !has_cfr, there's no synch - * else use AREN (later) not SA|OPR - * USIR0_IR0 acts edge sensitive - */ - } - break; - /* ... and here, even more ... */ - case USB_REQ_SET_INTERFACE: - if (u.r.bRequestType == USB_RECIP_INTERFACE) { - /* - * udc hardware is broken by design: - * - altsetting may only be zero; - * - hw resets all interfaces' eps; - * - ep reset doesn't include halt(?). - */ - printf("broken set_interface (%d/%d)\n", - le16_to_cpu(u.r.wIndex), - le16_to_cpu(u.r.wValue)); - goto config_change; - } - break; - /* hardware was supposed to hide this */ - case USB_REQ_SET_ADDRESS: - debug("GOT SET ADDRESS\n"); - if (u.r.bRequestType == USB_RECIP_DEVICE) { - ep0start(dev, 0, "address"); - return; - } - break; - } - - if (u.r.bRequestType & USB_DIR_IN) - dev->ep0state = EP0_IN_DATA_PHASE; - else - dev->ep0state = EP0_OUT_DATA_PHASE; - - i = dev->driver->setup(&dev->gadget, &u.r); - if (i < 0) { - /* hardware automagic preventing STALL... */ - if (dev->req_config) { - /* - * hardware sometimes neglects to tell - * tell us about config change events, - * so later ones may fail... - */ - printf("config change %02x fail %d?\n", - u.r.bRequest, i); - return; - /* - * TODO experiment: if has_cfr, - * hardware didn't ACK; maybe we - * could actually STALL! - */ - } - if (0) { -stall: - /* uninitialized when goto stall */ - i = 0; - } - debug("protocol STALL, " - "%02x err %d\n", - readl(&dev->regs->udccs[0]), i); - - /* - * the watchdog timer helps deal with cases - * where udc seems to clear FST wrongly, and - * then NAKs instead of STALLing. - */ - ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); - start_watchdog(dev); - dev->ep0state = EP0_STALL; - - /* deferred i/o == no response yet */ - } else if (dev->req_pending) { - if (likely(dev->ep0state == EP0_IN_DATA_PHASE - || dev->req_std || u.r.wLength)) - ep0start(dev, 0, "defer"); - else - ep0start(dev, UDCCS0_IPR, "defer/IPR"); - } - - /* expect at least one data or status stage irq */ - return; - - } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) - == (UDCCS0_OPR|UDCCS0_SA))) { - unsigned i; - - /* - * pxa210/250 erratum 131 for B0/B1 says RNE lies. - * still observed on a pxa255 a0. - */ - debug("e131\n"); - nuke(ep, -EPROTO); - - /* read SETUP data, but don't trust it too much */ - for (i = 0; i < 8; i++) - u.raw[i] = (u8)readb(&dev->regs->uddr0); - if ((u.r.bRequestType & USB_RECIP_MASK) - > USB_RECIP_OTHER) - goto stall; - if (u.word[0] == 0 && u.word[1] == 0) - goto stall; - goto got_setup; - } else { - /* - * some random early IRQ: - * - we acked FST - * - IPR cleared - * - OPR got set, without SA (likely status stage) - */ - debug("random IRQ %X %X\n", udccs0, - readl(&dev->regs->udccs[0])); - writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR), - &dev->regs->udccs[0]); - } - break; - case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ - if (udccs0 & UDCCS0_OPR) { - debug("ep0in premature status\n"); - if (req) - done(ep, req, 0); - ep0_idle(dev); - } else /* irq was IPR clearing */ { - if (req) { - debug("next ep0 in packet\n"); - /* this IN packet might finish the request */ - (void) write_ep0_fifo(ep, req); - } /* else IN token before response was written */ - } - break; - case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ - if (udccs0 & UDCCS0_OPR) { - if (req) { - /* this OUT packet might finish the request */ - if (read_ep0_fifo(ep, req)) - done(ep, req, 0); - /* else more OUT packets expected */ - } /* else OUT token before read was issued */ - } else /* irq was IPR clearing */ { - debug("ep0out premature status\n"); - if (req) - done(ep, req, 0); - ep0_idle(dev); - } - break; - case EP0_END_XFER: - if (req) - done(ep, req, 0); - /* - * ack control-IN status (maybe in-zlp was skipped) - * also appears after some config change events. - */ - if (udccs0 & UDCCS0_OPR) - writel(UDCCS0_OPR, &dev->regs->udccs[0]); - ep0_idle(dev); - break; - case EP0_STALL: - writel(UDCCS0_FST, &dev->regs->udccs[0]); - break; - } - - writel(USIR0_IR0, &dev->regs->usir0); -} - -static void handle_ep(struct pxa25x_ep *ep) -{ - struct pxa25x_request *req; - int is_in = ep->bEndpointAddress & USB_DIR_IN; - int completed; - u32 udccs, tmp; - - do { - completed = 0; - if (likely(!list_empty(&ep->queue))) - req = list_entry(ep->queue.next, - struct pxa25x_request, queue); - else - req = NULL; - - /* TODO check FST handling */ - - udccs = readl(ep->reg_udccs); - if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ - tmp = UDCCS_BI_TUR; - if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) - tmp |= UDCCS_BI_SST; - tmp &= udccs; - if (likely(tmp)) - writel(tmp, ep->reg_udccs); - if (req && likely((udccs & UDCCS_BI_TFS) != 0)) - completed = write_fifo(ep, req); - - } else { /* irq from RPC (or for ISO, ROF) */ - if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) - tmp = UDCCS_BO_SST | UDCCS_BO_DME; - else - tmp = UDCCS_IO_ROF | UDCCS_IO_DME; - tmp &= udccs; - if (likely(tmp)) - writel(tmp, ep->reg_udccs); - - /* fifos can hold packets, ready for reading... */ - if (likely(req)) - completed = read_fifo(ep, req); - else - pio_irq_disable(ep->bEndpointAddress); - } - ep->pio_irqs++; - } while (completed); -} - -/* - * pxa25x_udc_irq - interrupt handler - * - * avoid delays in ep0 processing. the control handshaking isn't always - * under software control (pxa250c0 and the pxa255 are better), and delays - * could cause usb protocol errors. - */ -static struct pxa25x_udc memory; -static int -pxa25x_udc_irq(void) -{ - struct pxa25x_udc *dev = &memory; - int handled; - - test_watchdog(dev); - - dev->stats.irqs++; - do { - u32 udccr = readl(&dev->regs->udccr); - - handled = 0; - - /* SUSpend Interrupt Request */ - if (unlikely(udccr & UDCCR_SUSIR)) { - udc_ack_int_UDCCR(UDCCR_SUSIR); - handled = 1; - debug("USB suspend\n"); - - if (dev->gadget.speed != USB_SPEED_UNKNOWN - && dev->driver - && dev->driver->suspend) - dev->driver->suspend(&dev->gadget); - ep0_idle(dev); - } - - /* RESume Interrupt Request */ - if (unlikely(udccr & UDCCR_RESIR)) { - udc_ack_int_UDCCR(UDCCR_RESIR); - handled = 1; - debug("USB resume\n"); - - if (dev->gadget.speed != USB_SPEED_UNKNOWN - && dev->driver - && dev->driver->resume) - dev->driver->resume(&dev->gadget); - } - - /* ReSeT Interrupt Request - USB reset */ - if (unlikely(udccr & UDCCR_RSTIR)) { - udc_ack_int_UDCCR(UDCCR_RSTIR); - handled = 1; - - if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) { - debug("USB reset start\n"); - - /* - * reset driver and endpoints, - * in case that's not yet done - */ - stop_activity(dev, dev->driver); - - } else { - debug("USB reset end\n"); - dev->gadget.speed = USB_SPEED_FULL; - memset(&dev->stats, 0, sizeof dev->stats); - /* driver and endpoints are still reset */ - } - - } else { - u32 uicr0 = readl(&dev->regs->uicr0); - u32 uicr1 = readl(&dev->regs->uicr1); - u32 usir0 = readl(&dev->regs->usir0); - u32 usir1 = readl(&dev->regs->usir1); - - usir0 = usir0 & ~uicr0; - usir1 = usir1 & ~uicr1; - int i; - - if (unlikely(!usir0 && !usir1)) - continue; - - debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0); - - /* control traffic */ - if (usir0 & USIR0_IR0) { - dev->ep[0].pio_irqs++; - handle_ep0(dev); - handled = 1; - } - - /* endpoint data transfers */ - for (i = 0; i < 8; i++) { - u32 tmp = 1 << i; - - if (i && (usir0 & tmp)) { - handle_ep(&dev->ep[i]); - setbits_le32(&dev->regs->usir0, tmp); - handled = 1; - } -#ifndef CONFIG_USB_PXA25X_SMALL - if (usir1 & tmp) { - handle_ep(&dev->ep[i+8]); - setbits_le32(&dev->regs->usir1, tmp); - handled = 1; - } -#endif - } - } - - /* we could also ask for 1 msec SOF (SIR) interrupts */ - - } while (handled); - return IRQ_HANDLED; -} - -/*-------------------------------------------------------------------------*/ - -/* - * this uses load-time allocation and initialization (instead of - * doing it at run-time) to save code, eliminate fault paths, and - * be more obviously correct. - */ -static struct pxa25x_udc memory = { - .regs = UDC_REGS, - - .gadget = { - .ops = &pxa25x_udc_ops, - .ep0 = &memory.ep[0].ep, - .name = driver_name, - }, - - /* control endpoint */ - .ep[0] = { - .ep = { - .name = ep0name, - .ops = &pxa25x_ep_ops, - .maxpacket = EP0_FIFO_SIZE, - }, - .dev = &memory, - .reg_udccs = &UDC_REGS->udccs[0], - .reg_uddr = &UDC_REGS->uddr0, - }, - - /* first group of endpoints */ - .ep[1] = { - .ep = { - .name = "ep1in-bulk", - .ops = &pxa25x_ep_ops, - .maxpacket = BULK_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = BULK_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 1, - .bmAttributes = USB_ENDPOINT_XFER_BULK, - .reg_udccs = &UDC_REGS->udccs[1], - .reg_uddr = &UDC_REGS->uddr1, - }, - .ep[2] = { - .ep = { - .name = "ep2out-bulk", - .ops = &pxa25x_ep_ops, - .maxpacket = BULK_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = BULK_FIFO_SIZE, - .bEndpointAddress = 2, - .bmAttributes = USB_ENDPOINT_XFER_BULK, - .reg_udccs = &UDC_REGS->udccs[2], - .reg_ubcr = &UDC_REGS->ubcr2, - .reg_uddr = &UDC_REGS->uddr2, - }, -#ifndef CONFIG_USB_PXA25X_SMALL - .ep[3] = { - .ep = { - .name = "ep3in-iso", - .ops = &pxa25x_ep_ops, - .maxpacket = ISO_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = ISO_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 3, - .bmAttributes = USB_ENDPOINT_XFER_ISOC, - .reg_udccs = &UDC_REGS->udccs[3], - .reg_uddr = &UDC_REGS->uddr3, - }, - .ep[4] = { - .ep = { - .name = "ep4out-iso", - .ops = &pxa25x_ep_ops, - .maxpacket = ISO_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = ISO_FIFO_SIZE, - .bEndpointAddress = 4, - .bmAttributes = USB_ENDPOINT_XFER_ISOC, - .reg_udccs = &UDC_REGS->udccs[4], - .reg_ubcr = &UDC_REGS->ubcr4, - .reg_uddr = &UDC_REGS->uddr4, - }, - .ep[5] = { - .ep = { - .name = "ep5in-int", - .ops = &pxa25x_ep_ops, - .maxpacket = INT_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = INT_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 5, - .bmAttributes = USB_ENDPOINT_XFER_INT, - .reg_udccs = &UDC_REGS->udccs[5], - .reg_uddr = &UDC_REGS->uddr5, - }, - - /* second group of endpoints */ - .ep[6] = { - .ep = { - .name = "ep6in-bulk", - .ops = &pxa25x_ep_ops, - .maxpacket = BULK_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = BULK_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 6, - .bmAttributes = USB_ENDPOINT_XFER_BULK, - .reg_udccs = &UDC_REGS->udccs[6], - .reg_uddr = &UDC_REGS->uddr6, - }, - .ep[7] = { - .ep = { - .name = "ep7out-bulk", - .ops = &pxa25x_ep_ops, - .maxpacket = BULK_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = BULK_FIFO_SIZE, - .bEndpointAddress = 7, - .bmAttributes = USB_ENDPOINT_XFER_BULK, - .reg_udccs = &UDC_REGS->udccs[7], - .reg_ubcr = &UDC_REGS->ubcr7, - .reg_uddr = &UDC_REGS->uddr7, - }, - .ep[8] = { - .ep = { - .name = "ep8in-iso", - .ops = &pxa25x_ep_ops, - .maxpacket = ISO_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = ISO_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 8, - .bmAttributes = USB_ENDPOINT_XFER_ISOC, - .reg_udccs = &UDC_REGS->udccs[8], - .reg_uddr = &UDC_REGS->uddr8, - }, - .ep[9] = { - .ep = { - .name = "ep9out-iso", - .ops = &pxa25x_ep_ops, - .maxpacket = ISO_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = ISO_FIFO_SIZE, - .bEndpointAddress = 9, - .bmAttributes = USB_ENDPOINT_XFER_ISOC, - .reg_udccs = &UDC_REGS->udccs[9], - .reg_ubcr = &UDC_REGS->ubcr9, - .reg_uddr = &UDC_REGS->uddr9, - }, - .ep[10] = { - .ep = { - .name = "ep10in-int", - .ops = &pxa25x_ep_ops, - .maxpacket = INT_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = INT_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 10, - .bmAttributes = USB_ENDPOINT_XFER_INT, - .reg_udccs = &UDC_REGS->udccs[10], - .reg_uddr = &UDC_REGS->uddr10, - }, - - /* third group of endpoints */ - .ep[11] = { - .ep = { - .name = "ep11in-bulk", - .ops = &pxa25x_ep_ops, - .maxpacket = BULK_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = BULK_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 11, - .bmAttributes = USB_ENDPOINT_XFER_BULK, - .reg_udccs = &UDC_REGS->udccs[11], - .reg_uddr = &UDC_REGS->uddr11, - }, - .ep[12] = { - .ep = { - .name = "ep12out-bulk", - .ops = &pxa25x_ep_ops, - .maxpacket = BULK_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = BULK_FIFO_SIZE, - .bEndpointAddress = 12, - .bmAttributes = USB_ENDPOINT_XFER_BULK, - .reg_udccs = &UDC_REGS->udccs[12], - .reg_ubcr = &UDC_REGS->ubcr12, - .reg_uddr = &UDC_REGS->uddr12, - }, - .ep[13] = { - .ep = { - .name = "ep13in-iso", - .ops = &pxa25x_ep_ops, - .maxpacket = ISO_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = ISO_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 13, - .bmAttributes = USB_ENDPOINT_XFER_ISOC, - .reg_udccs = &UDC_REGS->udccs[13], - .reg_uddr = &UDC_REGS->uddr13, - }, - .ep[14] = { - .ep = { - .name = "ep14out-iso", - .ops = &pxa25x_ep_ops, - .maxpacket = ISO_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = ISO_FIFO_SIZE, - .bEndpointAddress = 14, - .bmAttributes = USB_ENDPOINT_XFER_ISOC, - .reg_udccs = &UDC_REGS->udccs[14], - .reg_ubcr = &UDC_REGS->ubcr14, - .reg_uddr = &UDC_REGS->uddr14, - }, - .ep[15] = { - .ep = { - .name = "ep15in-int", - .ops = &pxa25x_ep_ops, - .maxpacket = INT_FIFO_SIZE, - }, - .dev = &memory, - .fifo_size = INT_FIFO_SIZE, - .bEndpointAddress = USB_DIR_IN | 15, - .bmAttributes = USB_ENDPOINT_XFER_INT, - .reg_udccs = &UDC_REGS->udccs[15], - .reg_uddr = &UDC_REGS->uddr15, - }, -#endif /* !CONFIG_USB_PXA25X_SMALL */ -}; - -static void udc_command(int cmd) -{ - switch (cmd) { - case PXA2XX_UDC_CMD_CONNECT: - setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), - GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); - - /* enable pullup */ - writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), - GPCR(CONFIG_USB_DEV_PULLUP_GPIO)); - - debug("Connected to USB\n"); - break; - - case PXA2XX_UDC_CMD_DISCONNECT: - /* disable pullup resistor */ - writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), - GPSR(CONFIG_USB_DEV_PULLUP_GPIO)); - - /* setup pin as input, line will float */ - clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO), - GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO)); - - debug("Disconnected from USB\n"); - break; - } -} - -static struct pxa2xx_udc_mach_info mach_info = { - .udc_command = udc_command, -}; - -/* - * when a driver is successfully registered, it will receive - * control requests including set_configuration(), which enables - * non-control requests. then usb traffic follows until a - * disconnect is reported. then a host may connect again, or - * the driver might get unbound. - */ -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -{ - struct pxa25x_udc *dev = &memory; - int retval; - uint32_t chiprev; - - if (!driver - || driver->speed < USB_SPEED_FULL - || !driver->disconnect - || !driver->setup) - return -EINVAL; - if (!dev) - return -ENODEV; - if (dev->driver) - return -EBUSY; - - /* Enable clock for usb controller */ - setbits_le32(CKEN, CKEN11_USB); - - /* first hook up the driver ... */ - dev->driver = driver; - dev->pullup = 1; - - /* trigger chiprev-specific logic */ - switch ((chiprev = pxa_get_cpu_revision())) { - case PXA255_A0: - dev->has_cfr = 1; - break; - case PXA250_A0: - case PXA250_A1: - /* A0/A1 "not released"; ep 13, 15 unusable */ - /* fall through */ - case PXA250_B2: case PXA210_B2: - case PXA250_B1: case PXA210_B1: - case PXA250_B0: case PXA210_B0: - /* OUT-DMA is broken ... */ - /* fall through */ - case PXA250_C0: case PXA210_C0: - break; - default: - printf("%s: unrecognized processor: %08x\n", - DRIVER_NAME, chiprev); - return -ENODEV; - } - - the_controller = dev; - - /* prepare watchdog timer */ - dev->watchdog.running = 0; - dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */ - dev->watchdog.function = udc_watchdog; - - dev->mach = &mach_info; - - udc_disable(dev); - udc_reinit(dev); - - dev->gadget.name = "pxa2xx_udc"; - retval = driver->bind(&dev->gadget); - if (retval) { - printf("bind to driver %s --> error %d\n", - DRIVER_NAME, retval); - dev->driver = NULL; - return retval; - } - - /* - * ... then enable host detection and ep0; and we're ready - * for set_configuration as well as eventual disconnect. - */ - printf("registered gadget driver '%s'\n", DRIVER_NAME); - - pullup(dev); - dump_state(dev); - return 0; -} - -static void -stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) -{ - int i; - - /* don't disconnect drivers more than once */ - if (dev->gadget.speed == USB_SPEED_UNKNOWN) - driver = NULL; - dev->gadget.speed = USB_SPEED_UNKNOWN; - - /* prevent new request submissions, kill any outstanding requests */ - for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { - struct pxa25x_ep *ep = &dev->ep[i]; - - ep->stopped = 1; - nuke(ep, -ESHUTDOWN); - } - stop_watchdog(dev); - - /* report disconnect; the driver is already quiesced */ - if (driver) - driver->disconnect(&dev->gadget); - - /* re-init driver-visible data structures */ - udc_reinit(dev); -} - -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - struct pxa25x_udc *dev = the_controller; - - if (!dev) - return -ENODEV; - if (!driver || driver != dev->driver || !driver->unbind) - return -EINVAL; - - local_irq_disable(); - dev->pullup = 0; - pullup(dev); - stop_activity(dev, driver); - local_irq_enable(); - - driver->unbind(&dev->gadget); - dev->driver = NULL; - - printf("unregistered gadget driver '%s'\n", DRIVER_NAME); - dump_state(dev); - - the_controller = NULL; - - clrbits_le32(CKEN, CKEN11_USB); - - return 0; -} - -extern void udc_disconnect(void) -{ - setbits_le32(CKEN, CKEN11_USB); - udc_clear_mask_UDCCR(UDCCR_UDE); - udc_command(PXA2XX_UDC_CMD_DISCONNECT); - clrbits_le32(CKEN, CKEN11_USB); -} - -/*-------------------------------------------------------------------------*/ - -extern int -usb_gadget_handle_interrupts(int index) -{ - return pxa25x_udc_irq(); -} diff --git a/drivers/usb/gadget/pxa25x_udc.h b/drivers/usb/gadget/pxa25x_udc.h deleted file mode 100644 index 7c3882aa1e028ac0f4acf3ded713a21386b7d061..0000000000000000000000000000000000000000 --- a/drivers/usb/gadget/pxa25x_udc.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Intel PXA25x on-chip full speed USB device controller - * - * Copyright (C) 2003 Robert Schwebel , Pengutronix - * Copyright (C) 2003 David Brownell - * Copyright (C) 2012 Lukasz Dalek - */ - -#ifndef __LINUX_USB_GADGET_PXA25X_H -#define __LINUX_USB_GADGET_PXA25X_H - -#include -#include - -/* - * Prefetching support - only ARMv5. - */ - -#ifdef ARCH_HAS_PREFETCH -static inline void prefetch(const void *ptr) -{ - __asm__ __volatile__( - "pld\t%a0" - : - : "p" (ptr) - : "cc"); -} - -#define prefetchw(ptr) prefetch(ptr) -#endif /* ARCH_HAS_PREFETCH */ - -/*-------------------------------------------------------------------------*/ - -#define UDC_REGS ((struct pxa25x_udc_regs *)PXA25X_UDC_BASE) - -/*-------------------------------------------------------------------------*/ - -struct pxa2xx_udc_mach_info { - int (*udc_is_connected)(void); /* do we see host? */ - void (*udc_command)(int cmd); -#define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */ -#define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ -}; - -struct pxa25x_udc; - -struct pxa25x_ep { - struct usb_ep ep; - struct pxa25x_udc *dev; - - const struct usb_endpoint_descriptor *desc; - struct list_head queue; - unsigned long pio_irqs; - - unsigned short fifo_size; - u8 bEndpointAddress; - u8 bmAttributes; - - unsigned stopped:1; - - /* UDCCS = UDC Control/Status for this EP - * UBCR = UDC Byte Count Remaining (contents of OUT fifo) - * UDDR = UDC Endpoint Data Register (the fifo) - * DRCM = DMA Request Channel Map - */ - u32 *reg_udccs; - u32 *reg_ubcr; - u32 *reg_uddr; -}; - -struct pxa25x_request { - struct usb_request req; - struct list_head queue; -}; - -enum ep0_state { - EP0_IDLE, - EP0_IN_DATA_PHASE, - EP0_OUT_DATA_PHASE, - EP0_END_XFER, - EP0_STALL, -}; - -#define EP0_FIFO_SIZE 16U -#define BULK_FIFO_SIZE 64U -#define ISO_FIFO_SIZE 256U -#define INT_FIFO_SIZE 8U - -struct udc_stats { - struct ep0stats { - unsigned long ops; - unsigned long bytes; - } read, write; - unsigned long irqs; -}; - -#ifdef CONFIG_USB_PXA25X_SMALL -/* when memory's tight, SMALL config saves code+data. */ -#define PXA_UDC_NUM_ENDPOINTS 3 -#endif - -#ifndef PXA_UDC_NUM_ENDPOINTS -#define PXA_UDC_NUM_ENDPOINTS 16 -#endif - -struct pxa25x_watchdog { - unsigned running:1; - ulong period; - ulong base; - struct pxa25x_udc *udc; - - void (*function)(struct pxa25x_udc *udc); -}; - -struct pxa25x_udc { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - struct pxa25x_udc_regs *regs; - - enum ep0_state ep0state; - struct udc_stats stats; - unsigned got_irq:1, - pullup:1, - has_cfr:1, - req_pending:1, - req_std:1, - req_config:1, - active:1; - - struct clk *clk; - struct pxa2xx_udc_mach_info *mach; - u64 dma_mask; - struct pxa25x_ep ep[PXA_UDC_NUM_ENDPOINTS]; - - struct pxa25x_watchdog watchdog; -}; - -/*-------------------------------------------------------------------------*/ - -static struct pxa25x_udc *the_controller; - -/*-------------------------------------------------------------------------*/ - -#ifndef DEBUG -# define NOISY 0 -#endif - -#endif /* __LINUX_USB_GADGET_PXA25X_H */ diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c deleted file mode 100644 index 583ceb4d55c62cff7ad9ba14aa6bc36ac709d571..0000000000000000000000000000000000000000 --- a/drivers/usb/gadget/pxa27x_udc.c +++ /dev/null @@ -1,703 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PXA27x USB device driver for u-boot. - * - * Copyright (C) 2007 Rodolfo Giometti - * Copyright (C) 2007 Eurotech S.p.A. - * Copyright (C) 2008 Vivek Kutal - */ - - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ep0.h" - -/* number of endpoints on this UDC */ -#define UDC_MAX_ENDPOINTS 24 - -static struct urb *ep0_urb; -static struct usb_device_instance *udc_device; -static int ep0state = EP0_IDLE; - -#ifdef USBDDBG -static void udc_dump_buffer(char *name, u8 *buf, int len) -{ - usbdbg("%s - buf %p, len %d", name, buf, len); - print_buffer(0, buf, 1, len, 0); -} -#else -#define udc_dump_buffer(name, buf, len) /* void */ -#endif - -static inline void udc_ack_int_UDCCR(int mask) -{ - writel(readl(USIR1) | mask, USIR1); -} - -/* - * If the endpoint has an active tx_urb, then the next packet of data from the - * URB is written to the tx FIFO. - * The total amount of data in the urb is given by urb->actual_length. - * The maximum amount of data that can be sent in any one packet is given by - * endpoint->tx_packetSize. - * The number of data bytes from this URB that have already been transmitted - * is given by endpoint->sent. - * endpoint->last is updated by this routine with the number of data bytes - * transmitted in this packet. - */ -static int udc_write_urb(struct usb_endpoint_instance *endpoint) -{ - struct urb *urb = endpoint->tx_urb; - int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - u32 *data32 = (u32 *) urb->buffer; - u8 *data8 = (u8 *) urb->buffer; - unsigned int i, n, w, b, is_short; - int timeout = 2000; /* 2ms */ - - if (!urb || !urb->actual_length) - return -1; - - n = min_t(unsigned int, urb->actual_length - endpoint->sent, - endpoint->tx_packetSize); - if (n <= 0) - return -1; - - usbdbg("write urb on ep %d", ep_num); -#if defined(USBDDBG) && defined(USBDPARANOIA) - usbdbg("urb: buf %p, buf_len %d, actual_len %d", - urb->buffer, urb->buffer_length, urb->actual_length); - usbdbg("endpoint: sent %d, tx_packetSize %d, last %d", - endpoint->sent, endpoint->tx_packetSize, endpoint->last); -#endif - - is_short = n != endpoint->tx_packetSize; - w = n / 4; - b = n % 4; - usbdbg("n %d%s w %d b %d", n, is_short ? "-s" : "", w, b); - udc_dump_buffer("urb write", data8 + endpoint->sent, n); - - /* Prepare for data send */ - if (ep_num) - writel(UDCCSR_PC ,UDCCSN(ep_num)); - - for (i = 0; i < w; i++) - writel(data32[endpoint->sent / 4 + i], UDCDN(ep_num)); - - for (i = 0; i < b; i++) - writeb(data8[endpoint->sent + w * 4 + i], UDCDN(ep_num)); - - /* Set "Packet Complete" if less data then tx_packetSize */ - if (is_short) - writel(ep_num ? UDCCSR_SP : UDCCSR0_IPR, UDCCSN(ep_num)); - - /* Wait for data sent */ - if (ep_num) { - while (!(readl(UDCCSN(ep_num)) & UDCCSR_PC)) { - if (timeout-- == 0) - return -1; - else - udelay(1); - } - } - - endpoint->last = n; - - if (ep_num) { - usbd_tx_complete(endpoint); - } else { - endpoint->sent += n; - endpoint->last -= n; - } - - if (endpoint->sent >= urb->actual_length) { - urb->actual_length = 0; - endpoint->sent = 0; - endpoint->last = 0; - } - - if ((endpoint->sent >= urb->actual_length) && (!ep_num)) { - usbdbg("ep0 IN stage done"); - if (is_short) - ep0state = EP0_IDLE; - else - ep0state = EP0_XFER_COMPLETE; - } - - return 0; -} - -static int udc_read_urb(struct usb_endpoint_instance *endpoint) -{ - struct urb *urb = endpoint->rcv_urb; - int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - u32 *data32 = (u32 *) urb->buffer; - unsigned int i, n; - - usbdbg("read urb on ep %d", ep_num); -#if defined(USBDDBG) && defined(USBDPARANOIA) - usbdbg("urb: buf %p, buf_len %d, actual_len %d", - urb->buffer, urb->buffer_length, urb->actual_length); - usbdbg("endpoint: rcv_packetSize %d", - endpoint->rcv_packetSize); -#endif - - if (readl(UDCCSN(ep_num)) & UDCCSR_BNE) - n = readl(UDCBCN(ep_num)) & 0x3ff; - else /* zlp */ - n = 0; - - usbdbg("n %d%s", n, n != endpoint->rcv_packetSize ? "-s" : ""); - for (i = 0; i < n; i += 4) - data32[urb->actual_length / 4 + i / 4] = readl(UDCDN(ep_num)); - - udc_dump_buffer("urb read", (u8 *) data32, urb->actual_length + n); - usbd_rcv_complete(endpoint, n, 0); - - return 0; -} - -static int udc_read_urb_ep0(void) -{ - u32 *data32 = (u32 *) ep0_urb->buffer; - u8 *data8 = (u8 *) ep0_urb->buffer; - unsigned int i, n, w, b; - - usbdbg("read urb on ep 0"); -#if defined(USBDDBG) && defined(USBDPARANOIA) - usbdbg("urb: buf %p, buf_len %d, actual_len %d", - ep0_urb->buffer, ep0_urb->buffer_length, ep0_urb->actual_length); -#endif - - n = readl(UDCBCR0); - w = n / 4; - b = n % 4; - - for (i = 0; i < w; i++) { - data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0)); - /* ep0_urb->actual_length += 4; */ - } - - for (i = 0; i < b; i++) { - data8[ep0_urb->actual_length + w * 4 + i] = readb(UDCDN(0)); - /* ep0_urb->actual_length++; */ - } - - ep0_urb->actual_length += n; - - udc_dump_buffer("urb read", (u8 *) data32, ep0_urb->actual_length); - - writel(UDCCSR0_OPC | UDCCSR0_IPR, UDCCSR0); - if (ep0_urb->actual_length == ep0_urb->device_request.wLength) - return 1; - - return 0; -} - -static void udc_handle_ep0(struct usb_endpoint_instance *endpoint) -{ - u32 udccsr0 = readl(UDCCSR0); - u32 *data = (u32 *) &ep0_urb->device_request; - int i; - - usbdbg("udccsr0 %x", udccsr0); - - /* Clear stall status */ - if (udccsr0 & UDCCSR0_SST) { - usberr("clear stall status"); - writel(UDCCSR0_SST, UDCCSR0); - ep0state = EP0_IDLE; - } - - /* previous request unfinished? non-error iff back-to-back ... */ - if ((udccsr0 & UDCCSR0_SA) != 0 && ep0state != EP0_IDLE) - ep0state = EP0_IDLE; - - switch (ep0state) { - - case EP0_IDLE: - udccsr0 = readl(UDCCSR0); - /* Start control request? */ - if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)) - == (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)) { - - /* Read SETUP packet. - * SETUP packet size is 8 bytes (aka 2 words) - */ - usbdbg("try reading SETUP packet"); - for (i = 0; i < 2; i++) { - if ((readl(UDCCSR0) & UDCCSR0_RNE) == 0) { - usberr("setup packet too short:%d", i); - goto stall; - } - data[i] = readl(UDCDR0); - } - - writel(readl(UDCCSR0) | UDCCSR0_OPC | UDCCSR0_SA, UDCCSR0); - if ((readl(UDCCSR0) & UDCCSR0_RNE) != 0) { - usberr("setup packet too long"); - goto stall; - } - - udc_dump_buffer("ep0 setup read", (u8 *) data, 8); - - if (ep0_urb->device_request.wLength == 0) { - usbdbg("Zero Data control Packet\n"); - if (ep0_recv_setup(ep0_urb)) { - usberr("Invalid Setup Packet\n"); - udc_dump_buffer("ep0 setup read", - (u8 *)data, 8); - goto stall; - } - writel(UDCCSR0_IPR, UDCCSR0); - ep0state = EP0_IDLE; - } else { - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType & - USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - ep0state = EP0_OUT_DATA; - ep0_urb->buffer = - (u8 *)ep0_urb->buffer_data; - ep0_urb->buffer_length = - sizeof(ep0_urb->buffer_data); - ep0_urb->actual_length = 0; - writel(UDCCSR0_IPR, UDCCSR0); - } else { - /* The ep0_recv_setup function has - * already placed our response packet - * data in ep0_urb->buffer and the - * packet length in - * ep0_urb->actual_length. - */ - if (ep0_recv_setup(ep0_urb)) { -stall: - usberr("Invalid setup packet"); - udc_dump_buffer("ep0 setup read" - , (u8 *) data, 8); - ep0state = EP0_IDLE; - - writel(UDCCSR0_SA | - UDCCSR0_OPC | UDCCSR0_FST | - UDCCS0_FTF, UDCCSR0); - - return; - } - - endpoint->tx_urb = ep0_urb; - endpoint->sent = 0; - usbdbg("EP0_IN_DATA"); - ep0state = EP0_IN_DATA; - if (udc_write_urb(endpoint) < 0) - goto stall; - - } - } - return; - } else if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA)) - == (UDCCSR0_OPC|UDCCSR0_SA)) { - usberr("Setup Active but no data. Stalling ....\n"); - goto stall; - } else { - usbdbg("random early IRQs"); - /* Some random early IRQs: - * - we acked FST - * - IPR cleared - * - OPC got set, without SA (likely status stage) - */ - writel(udccsr0 & (UDCCSR0_SA | UDCCSR0_OPC), UDCCSR0); - } - break; - - case EP0_OUT_DATA: - - if ((udccsr0 & UDCCSR0_OPC) && !(udccsr0 & UDCCSR0_SA)) { - if (udc_read_urb_ep0()) { -read_complete: - ep0state = EP0_IDLE; - if (ep0_recv_setup(ep0_urb)) { - /* Not a setup packet, stall next - * EP0 transaction - */ - udc_dump_buffer("ep0 setup read", - (u8 *) data, 8); - usberr("can't parse setup packet\n"); - goto stall; - } - } - } else if (!(udccsr0 & UDCCSR0_OPC) && - !(udccsr0 & UDCCSR0_IPR)) { - if (ep0_urb->device_request.wLength == - ep0_urb->actual_length) - goto read_complete; - - usberr("Premature Status\n"); - ep0state = EP0_IDLE; - } - break; - - case EP0_IN_DATA: - /* GET_DESCRIPTOR etc */ - if (udccsr0 & UDCCSR0_OPC) { - writel(UDCCSR0_OPC | UDCCSR0_FTF, UDCCSR0); - usberr("ep0in premature status"); - ep0state = EP0_IDLE; - } else { - /* irq was IPR clearing */ - if (udc_write_urb(endpoint) < 0) { - usberr("ep0_write_error\n"); - goto stall; - } - } - break; - - case EP0_XFER_COMPLETE: - writel(UDCCSR0_IPR, UDCCSR0); - ep0state = EP0_IDLE; - break; - - default: - usbdbg("Default\n"); - } - writel(USIR0_IR0, USIR0); -} - -static void udc_handle_ep(struct usb_endpoint_instance *endpoint) -{ - int ep_addr = endpoint->endpoint_address; - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - int ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT; - - u32 flags = readl(UDCCSN(ep_num)) & (UDCCSR_SST | UDCCSR_TRN); - if (flags) - writel(flags, UDCCSN(ep_num)); - - if (ep_isout) - udc_read_urb(endpoint); - else - udc_write_urb(endpoint); - - writel(UDCCSR_PC, UDCCSN(ep_num)); -} - -static void udc_state_changed(void) -{ - - writel(readl(UDCCR) | UDCCR_SMAC, UDCCR); - - usbdbg("New UDC settings are: conf %d - inter %d - alter %d", - (readl(UDCCR) & UDCCR_ACN) >> UDCCR_ACN_S, - (readl(UDCCR) & UDCCR_AIN) >> UDCCR_AIN_S, - (readl(UDCCR) & UDCCR_AAISN) >> UDCCR_AAISN_S); - - usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); - writel(UDCISR1_IRCC, UDCISR1); -} - -void udc_irq(void) -{ - int handled; - struct usb_endpoint_instance *endpoint; - int ep_num, i; - u32 udcisr0; - - do { - handled = 0; - /* Suspend Interrupt Request */ - if (readl(USIR1) & UDCCR_SUSIR) { - usbdbg("Suspend\n"); - udc_ack_int_UDCCR(UDCCR_SUSIR); - handled = 1; - ep0state = EP0_IDLE; - } - - /* Resume Interrupt Request */ - if (readl(USIR1) & UDCCR_RESIR) { - udc_ack_int_UDCCR(UDCCR_RESIR); - handled = 1; - usbdbg("USB resume\n"); - } - - if (readl(USIR1) & (1<<31)) { - handled = 1; - udc_state_changed(); - } - - /* Reset Interrupt Request */ - if (readl(USIR1) & UDCCR_RSTIR) { - udc_ack_int_UDCCR(UDCCR_RSTIR); - handled = 1; - usbdbg("Reset\n"); - usbd_device_event_irq(udc_device, DEVICE_RESET, 0); - } else { - if (readl(USIR0)) - usbdbg("UISR0: %x \n", readl(USIR0)); - - if (readl(USIR0) & 0x2) - writel(0x2, USIR0); - - /* Control traffic */ - if (readl(USIR0) & USIR0_IR0) { - handled = 1; - writel(USIR0_IR0, USIR0); - udc_handle_ep0(udc_device->bus->endpoint_array); - } - - endpoint = udc_device->bus->endpoint_array; - for (i = 0; i < udc_device->bus->max_endpoints; i++) { - ep_num = (endpoint[i].endpoint_address) & - USB_ENDPOINT_NUMBER_MASK; - if (!ep_num) - continue; - udcisr0 = readl(UDCISR0); - if (udcisr0 & - UDCISR_INT(ep_num, UDC_INT_PACKETCMP)) { - writel(UDCISR_INT(ep_num, UDC_INT_PACKETCMP), - UDCISR0); - udc_handle_ep(&endpoint[i]); - } - } - } - - } while (handled); -} - -/* The UDCCR reg contains mask and interrupt status bits, - * so using '|=' isn't safe as it may ack an interrupt. - */ -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) - -static inline void udc_set_mask_UDCCR(int mask) -{ - writel((readl(UDCCR) & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR); -} - -static inline void udc_clear_mask_UDCCR(int mask) -{ - writel((readl(UDCCR) & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR); -} - -static void pio_irq_enable(int ep_num) -{ - if (ep_num < 16) - writel(readl(UDCICR0) | 3 << (ep_num * 2), UDCICR0); - else { - ep_num -= 16; - writel(readl(UDCICR1) | 3 << (ep_num * 2), UDCICR1); - } -} - -/* - * udc_set_nak - * - * Allow upper layers to signal lower layers should not accept more RX data - */ -void udc_set_nak(int ep_num) -{ - /* TODO */ -} - -/* - * udc_unset_nak - * - * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint. - * Switch off NAKing on this endpoint to accept more data output from host. - */ -void udc_unset_nak(int ep_num) -{ - /* TODO */ -} - -int udc_endpoint_write(struct usb_endpoint_instance *endpoint) -{ - return udc_write_urb(endpoint); -} - -/* Associate a physical endpoint with endpoint instance */ -void udc_setup_ep(struct usb_device_instance *device, unsigned int id, - struct usb_endpoint_instance *endpoint) -{ - int ep_num, ep_addr, ep_isout, ep_type, ep_size; - int config, interface, alternate; - u32 tmp; - - usbdbg("setting up endpoint id %d", id); - - if (!endpoint) { - usberr("endpoint void!"); - return; - } - - ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - if (ep_num >= UDC_MAX_ENDPOINTS) { - usberr("unable to setup ep %d!", ep_num); - return; - } - - pio_irq_enable(ep_num); - if (ep_num == 0) { - /* Done for ep0 */ - return; - } - - config = 1; - interface = 0; - alternate = 0; - - usbdbg("config %d - interface %d - alternate %d", - config, interface, alternate); - - ep_addr = endpoint->endpoint_address; - ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT; - ep_type = ep_isout ? endpoint->rcv_attributes : endpoint->tx_attributes; - ep_size = ep_isout ? endpoint->rcv_packetSize : endpoint->tx_packetSize; - - usbdbg("addr %x, num %d, dir %s, type %s, packet size %d", - ep_addr, ep_num, - ep_isout ? "out" : "in", - ep_type == USB_ENDPOINT_XFER_ISOC ? "isoc" : - ep_type == USB_ENDPOINT_XFER_BULK ? "bulk" : - ep_type == USB_ENDPOINT_XFER_INT ? "int" : "???", - ep_size - ); - - /* Configure UDCCRx */ - tmp = 0; - tmp |= (config << UDCCONR_CN_S) & UDCCONR_CN; - tmp |= (interface << UDCCONR_IN_S) & UDCCONR_IN; - tmp |= (alternate << UDCCONR_AISN_S) & UDCCONR_AISN; - tmp |= (ep_num << UDCCONR_EN_S) & UDCCONR_EN; - tmp |= (ep_type << UDCCONR_ET_S) & UDCCONR_ET; - tmp |= ep_isout ? 0 : UDCCONR_ED; - tmp |= (ep_size << UDCCONR_MPS_S) & UDCCONR_MPS; - tmp |= UDCCONR_EE; - - writel(tmp, UDCCN(ep_num)); - - usbdbg("UDCCR%c = %x", 'A' + ep_num-1, readl(UDCCN(ep_num))); - usbdbg("UDCCSR%c = %x", 'A' + ep_num-1, readl(UDCCSN(ep_num))); -} - -/* Connect the USB device to the bus */ -void udc_connect(void) -{ - usbdbg("UDC connect"); - -#ifdef CONFIG_USB_DEV_PULLUP_GPIO - /* Turn on the USB connection by enabling the pullup resistor */ - writel(readl(GPDR(CONFIG_USB_DEV_PULLUP_GPIO)) - | GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), - GPDR(CONFIG_USB_DEV_PULLUP_GPIO)); - writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPSR(CONFIG_USB_DEV_PULLUP_GPIO)); -#else - /* Host port 2 transceiver D+ pull up enable */ - writel(readl(UP2OCR) | UP2OCR_DPPUE, UP2OCR); -#endif -} - -/* Disconnect the USB device to the bus */ -void udc_disconnect(void) -{ - usbdbg("UDC disconnect"); - -#ifdef CONFIG_USB_DEV_PULLUP_GPIO - /* Turn off the USB connection by disabling the pullup resistor */ - writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPCR(CONFIG_USB_DEV_PULLUP_GPIO)); -#else - /* Host port 2 transceiver D+ pull up disable */ - writel(readl(UP2OCR) & ~UP2OCR_DPPUE, UP2OCR); -#endif -} - -/* Switch on the UDC */ -void udc_enable(struct usb_device_instance *device) -{ - - ep0state = EP0_IDLE; - - /* enable endpoint 0, A, B's Packet Complete Interrupt. */ - writel(0xffffffff, UDCICR0); - writel(0xa8000000, UDCICR1); - - /* clear the interrupt status/control registers */ - writel(0xffffffff, UDCISR0); - writel(0xffffffff, UDCISR1); - - /* set UDC-enable */ - udc_set_mask_UDCCR(UDCCR_UDE); - - udc_device = device; - if (!ep0_urb) - ep0_urb = usbd_alloc_urb(udc_device, - udc_device->bus->endpoint_array); - else - usbinfo("ep0_urb %p already allocated", ep0_urb); - - usbdbg("UDC Enabled\n"); -} - -/* Need to check this again */ -void udc_disable(void) -{ - usbdbg("disable UDC"); - - udc_clear_mask_UDCCR(UDCCR_UDE); - - /* Disable clock for USB device */ - writel(readl(CKEN) & ~CKEN11_USB, CKEN); - - /* Free ep0 URB */ - if (ep0_urb) { - usbd_dealloc_urb(ep0_urb); - ep0_urb = NULL; - } - - /* Reset device pointer */ - udc_device = NULL; -} - -/* Allow udc code to do any additional startup */ -void udc_startup_events(struct usb_device_instance *device) -{ - /* The DEVICE_INIT event puts the USB device in the state STATE_INIT */ - usbd_device_event_irq(device, DEVICE_INIT, 0); - - /* The DEVICE_CREATE event puts the USB device in the state - * STATE_ATTACHED */ - usbd_device_event_irq(device, DEVICE_CREATE, 0); - - /* Some USB controller driver implementations signal - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. - * DEVICE_HUB_CONFIGURED causes a transition to the state - * STATE_POWERED, and DEVICE_RESET causes a transition to - * the state STATE_DEFAULT. - */ - udc_enable(device); -} - -/* Initialize h/w stuff */ -int udc_init(void) -{ - udc_device = NULL; - usbdbg("PXA27x usbd start"); - - /* Enable clock for USB device */ - writel(readl(CKEN) | CKEN11_USB, CKEN); - - /* Disable the UDC */ - udc_clear_mask_UDCCR(UDCCR_UDE); - - /* Disable IRQs: we don't use them */ - writel(0, UDCICR0); - writel(0, UDCICR1); - - return 0; -} diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8f77412cc71b8dcaf2b0eed0794d1d644b861831..31ae9f74e7ace90c6c5c831c244f23421d235f53 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -32,6 +32,14 @@ config USB_XHCI_DWC3_OF_SIMPLE Support USB2/3 functionality in simple SoC integrations with USB controller based on the DesignWare USB3 IP Core. +config USB_XHCI_EXYNOS + bool "Support for Samsung Exynos5 family on-chip xHCI USB controller" + depends on ARCH_EXYNOS5 + default y + help + Enables support for he on-chip xHCI controller on Samsung Exynos5 + SoCs. + config USB_XHCI_MTK bool "Support for MediaTek on-chip xHCI USB controller" depends on ARCH_MEDIATEK @@ -116,11 +124,19 @@ config USB_XHCI_BRCM endif # USB_XHCI_HCD +config EHCI_DESC_BIG_ENDIAN + bool + +config EHCI_MMIO_BIG_ENDIAN + bool + config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" default y if ARCH_MX5 || ARCH_MX6 depends on DM && OF_CONTROL select USB_HOST + select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN + select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. @@ -149,6 +165,14 @@ config USB_EHCI_ATMEL ---help--- Enables support for the on-chip EHCI controller on Atmel chips. +config USB_EHCI_EXYNOS + bool "Support for Samsung Exynos EHCI USB controller" + depends on ARCH_EXYNOS + default y + ---help--- + Enables support for the on-chip EHCI controller on Samsung Exynos + SoCs. + config USB_EHCI_MARVELL bool "Support for Marvell on-chip EHCI USB controller" depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X @@ -166,6 +190,7 @@ config USB_EHCI_MX5 config USB_EHCI_MX6 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT + select EHCI_HCD_INIT_AFTER_RESET default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. @@ -173,6 +198,7 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" depends on ARCH_MX7 || IMX8M + select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 select PHY if IMX8M select NOP_PHY if IMX8M default y @@ -250,17 +276,38 @@ config USB_EHCI_GENERIC ---help--- Enables support for generic EHCI controller. +config EHCI_HCD_INIT_AFTER_RESET + bool + config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" - select CONFIG_EHCI_HCD_INIT_AFTER_RESET + select EHCI_HCD_INIT_AFTER_RESET ---help--- Enables support for the on-chip EHCI controller on FSL chips. + +config USB_EHCI_TXFIFO_THRESH + hex + depends on USB_EHCI_TEGRA + default 0x10 + help + This parameter affects a TXFILLTUNING field that controls how much + data is sent to the latency fifo before it is sent to the wire. + Without this parameter, the default (2) causes occasional Data Buffer + Errors in OUT packets depending on the buffer address and size. + endif # USB_EHCI_HCD +config USB_OHCI_NEW + bool + +config SYS_USB_OHCI_CPU_INIT + bool + config USB_OHCI_HCD bool "OHCI HCD (USB 1.1) support" depends on DM && OF_CONTROL select USB_HOST + select USB_OHCI_NEW ---help--- The Open Host Controller Interface (OHCI) is a standard for accessing USB 1.1 host controller hardware. It does more in hardware than Intel's @@ -292,6 +339,19 @@ config USB_OHCI_DA8XX endif # USB_OHCI_HCD +config SYS_USB_OHCI_SLOT_NAME + string "Display name for the OHCI controller" + depends on USB_OHCI_NEW && !DM_USB + +config SYS_USB_OHCI_MAX_ROOT_PORTS + int "Maximal number of ports of the root hub" + depends on USB_OHCI_NEW + default 1 if ARCH_SUNXI + +config SYS_OHCI_SWAP_REG_ACCESS + bool "Perform byte swapping on OHCI controller register accesses" + depends on USB_OHCI_NEW + config USB_UHCI_HCD bool "UHCI HCD (most Intel and VIA) support" select USB_HOST @@ -340,3 +400,33 @@ config USB_R8A66597_HCD ---help--- This enables support for the on-chip Renesas R8A66597 USB 2.0 controller, present in various RZ and SH SoCs. + +config USB_ATMEL + bool "AT91 OHCI USB support" + depends on ARCH_AT91 + select SYS_USB_OHCI_CPU_INIT + select USB_OHCI_NEW + +choice + prompt "Clock for OHCI" + depends on USB_ATMEL + +config USB_ATMEL_CLK_SEL_PLLB + bool "PLLB" + +config USB_ATMEL_CLK_SEL_UPLL + bool "UPLL" + +endchoice + +config USB_OHCI_LPC32XX + bool "LPC32xx USB OHCI support" + depends on ARCH_LPC32XX + select SYS_USB_OHCI_CPU_INIT + select USB_OHCI_NEW + +config USB_MAX_CONTROLLER_COUNT + int "Maximum number of USB host controllers" + depends on USB_EHCI_FSL || USB_XHCI_FSL || \ + (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB) + default 1 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7785b3744ef70f981f2a5ce89573e4ff553ddef6..5fdb8041167a6b81f1eea416854c04ab83e37b0d 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o -obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index cf1f882441bfb7f2550d7ee96e2b58c8d7f61c6f..0569dd54fff937af7ac0f8fc32ed3609e7e73118 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -25,26 +25,15 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#if CONFIG_IS_ENABLED(DM_USB) struct ehci_fsl_priv { struct ehci_ctrl ehci; fdt_addr_t hcd_base; char *phy_type; }; -#endif static void set_txfifothresh(struct usb_ehci *, u32); -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor); -#else -static int ehci_fsl_init(int index, struct usb_ehci *ehci, - struct ehci_hccr *hccr, struct ehci_hcor *hcor); -#endif /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) @@ -58,7 +47,6 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci) } } -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_of_to_plat(struct udevice *dev) { struct ehci_fsl_priv *priv = dev_get_priv(dev); @@ -150,64 +138,11 @@ U_BOOT_DRIVER(ehci_fsl) = { .priv_auto = sizeof(struct ehci_fsl_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#else -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - * - * Excerpts from linux ehci fsl driver. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct ehci_ctrl *ehci_ctrl = container_of(hccr, - struct ehci_ctrl, hccr); - struct usb_ehci *ehci = NULL; - - switch (index) { - case 0: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - break; - case 1: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; - break; - default: - printf("ERROR: wrong controller index!!\n"); - return -EINVAL; - }; - - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); - - return ehci_fsl_init(index, ehci, *hccr, *hcor); -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor) -#else -static int ehci_fsl_init(int index, struct usb_ehci *ehci, - struct ehci_hccr *hccr, struct ehci_hcor *hcor) -#endif { const char *phy_type = NULL; -#if !CONFIG_IS_ENABLED(DM_USB) - size_t len; - char current_usb_controller[5]; -#endif #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; @@ -230,18 +165,8 @@ static int ehci_fsl_init(int index, struct usb_ehci *ehci, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ -#if CONFIG_IS_ENABLED(DM_USB) if (priv->phy_type) phy_type = priv->phy_type; -#else - memset(current_usb_controller, '\0', 5); - snprintf(current_usb_controller, sizeof(current_usb_controller), - "usb%d", index+1); - - if (hwconfig_sub(current_usb_controller, "phy_type")) - phy_type = hwconfig_subarg(current_usb_controller, - "phy_type", &len); -#endif else phy_type = env_get("usb_phy_type"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index e6355263cb974f1815fd469615fa0093e2866157..f033198a7c193231ab26d84770d63d6314c1f221 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -25,10 +25,6 @@ #include "ehci.h" -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /* * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. * Let's time out after 8 to have a little safety margin on top of that. diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index ab863f41b24e96d94dd1433502b5984e8e258271..964a53bb7c0ed8a048802fd0fd83364e76a72c34 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -228,52 +228,6 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, mdelay(50); } -#if !CONFIG_IS_ENABLED(DM_USB) -static const struct ehci_ops mx5_ehci_ops = { - .powerup_fixup = mx5_ehci_powerup_fixup, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct usb_ehci *ehci; - - /* The only user for this is efikamx-usb */ - ehci_set_controller_priv(index, NULL, &mx5_ehci_ops); - set_usboh3_clk(); - enable_usboh3_clk(true); - set_usb_phy_clk(); - enable_usb_phy1_clk(true); - enable_usb_phy2_clk(true); - mdelay(1); - - /* Do board specific initialization */ - board_ehci_hcd_init(CONFIG_MXC_USB_PORT); - - ehci = (struct usb_ehci *)(OTG_BASE_ADDR + - (0x200 * CONFIG_MXC_USB_PORT)); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); - - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - setbits_le32(&ehci->portsc, USB_EN); - - mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); - mdelay(10); - - /* Do board specific post-initialization */ - board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); - - return 0; -} - -int ehci_hcd_stop(int index) -{ - return 0; -} -#else /* CONFIG_IS_ENABLED(DM_USB) */ struct ehci_mx5_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; @@ -372,4 +326,3 @@ U_BOOT_DRIVER(usb_mx5) = { .priv_auto = sizeof(struct ehci_mx5_priv_data), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* !CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c deleted file mode 100644 index 1fb685e58d80f32f84e6dd8d0fc9b9522c94c877..0000000000000000000000000000000000000000 --- a/drivers/usb/host/ehci-mxc.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2009 Daniel Mack - */ - - -#include -#include -#include -#include -#include -#include -#include - -#include "ehci.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX25_OTG_SIC_SHIFT 29 -#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) - -#define MX25_H1_SIC_SHIFT 21 -#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 16) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) - -static int mxc_set_usbcontrol(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); -#if defined(CONFIG_MX31) - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } -#else -#error MXC EHCI USB driver not supported on this platform -#endif - writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); - - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct usb_ehci *ehci; -#ifdef CONFIG_MX31 - struct clock_control_regs *sc_regs = - (struct clock_control_regs *)CCM_BASE; - - __raw_readl(&sc_regs->ccmr); - __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; -#endif - - udelay(80); - - ehci = (struct usb_ehci *)(IMX_USB_BASE + - IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); - - udelay(10000); - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 9a614955fc16686af8b03b885746adb74b82d004..147b2fa145d6533095314bbd8cfe90569f32f02f 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -112,82 +112,6 @@ static int __ehci_hcd_stop(struct ehci_mxs_port *port) return ehci_mxs_toggle_clock(port, 0); } -#if !CONFIG_IS_ENABLED(DM_USB) -static const struct ehci_mxs_port mxs_port[] = { -#ifdef CONFIG_EHCI_MXS_PORT0 - { - MXS_USBCTRL0_BASE, - (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE, - (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + - offsetof(struct mxs_clkctrl_regs, - hw_clkctrl_pll0ctrl0_reg)), - CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, - CLKCTRL_PLL0CTRL0_EN_USB_CLKS, - HW_DIGCTL_CTRL_USB0_CLKGATE, - }, -#endif -#ifdef CONFIG_EHCI_MXS_PORT1 - { - MXS_USBCTRL1_BASE, - (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE, - (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + - offsetof(struct mxs_clkctrl_regs, - hw_clkctrl_pll1ctrl0_reg)), - CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, - CLKCTRL_PLL1CTRL0_EN_USB_CLKS, - HW_DIGCTL_CTRL_USB1_CLKGATE, - }, -#endif -}; - -int __weak board_ehci_hcd_init(int port) -{ - return 0; -} - -int __weak board_ehci_hcd_exit(int port) -{ - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - - int ret; - const struct ehci_mxs_port *port; - - if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { - printf("Invalid port index (index = %d)!\n", index); - return -EINVAL; - } - - ret = board_ehci_hcd_init(index); - if (ret) - return ret; - - port = &mxs_port[index]; - return __ehci_hcd_init(port, init, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - int ret; - const struct ehci_mxs_port *port; - - if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { - printf("Invalid port index (index = %d)!\n", index); - return -EINVAL; - } - - port = &mxs_port[index]; - - ret = __ehci_hcd_stop(port); - board_ehci_hcd_exit(index); - - return ret; -} -#else /* CONFIG_IS_ENABLED(DM_USB) */ struct ehci_mxs_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; @@ -367,4 +291,3 @@ U_BOOT_DRIVER(usb_mxs) = { .priv_auto = sizeof(struct ehci_mxs_priv_data), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* !CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 8ceabaf45c1b98501789b1039d03e8a937072b89..9b955c1bd678eb70475b0a4002ed8457b1ec462a 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -5,9 +5,6 @@ */ #include - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - #include int usb_cpu_init(void) @@ -65,5 +62,3 @@ int usb_cpu_init_fail(void) { return usb_cpu_stop(); } - -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index 163f0ef17b118f9d12587657f9a57c12dee7f2c5..5d23058aaf6acdc65aa703cd1e7ddc2251d4ac58 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -14,10 +14,6 @@ #include #include "ohci.h" -#if !defined(CONFIG_USB_OHCI_NEW) -# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW" -#endif - struct generic_ohci { ohci_t ohci; struct clk *clocks; /* clock list */ diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index fedf0db9c7e4f081ae6f73e594cc5c25bf2de416..9acef5ee4f84813fc5037d94ec20b0a1ac77835d 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -35,13 +35,6 @@ #include #include -#if defined(CONFIG_PCI_OHCI) -# include -#if !defined(CONFIG_PCI_OHCI_DEVNO) -#define CONFIG_PCI_OHCI_DEVNO 0 -#endif -#endif - #include #include #include @@ -53,7 +46,6 @@ #endif #if defined(CONFIG_CPU_ARM920T) || \ - defined(CONFIG_PCI_OHCI) || \ defined(CONFIG_PCI) || \ defined(CONFIG_SYS_OHCI_USE_NPS) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ @@ -68,26 +60,6 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#if !CONFIG_IS_ENABLED(DM_USB) -#ifdef CONFIG_PCI_OHCI -static struct pci_device_id ohci_pci_ids[] = { - {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ - {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ - {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ - /* Please add supported PCI OHCI controller ids here */ - {0, 0} -}; -#endif -#endif - -#ifdef CONFIG_PCI_EHCI_DEVNO -static struct pci_device_id ehci_pci_ids[] = { - {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ - /* Please add supported PCI EHCI controller ids here */ - {0, 0} -}; -#endif - #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else @@ -2007,21 +1979,6 @@ static char ohci_inited = 0; int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { -#ifdef CONFIG_PCI_OHCI - pci_dev_t pdev; -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant init */ - if (usb_cpu_init()) - return -1; -#endif - -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant init */ - if (board_usb_init(index, USB_INIT_HOST)) - return -1; -#endif memset(&gohci, 0, sizeof(ohci_t)); /* align the storage */ @@ -2036,28 +1993,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; -#ifdef CONFIG_PCI_OHCI - pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); - - if (pdev != -1) { - u16 vid, did; - u32 base; - pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); - pci_read_config_word(pdev, PCI_DEVICE_ID, &did); - printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", - vid, did, (pdev >> 16) & 0xff, - (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); - printf("OHCI regs address 0x%08x\n", base); - gohci.regs = (struct ohci_regs *)base; - } else { - printf("%s: OHCI devnr: %d not found\n", __func__, - CONFIG_PCI_OHCI_DEVNO); - return -1; - } -#else gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; -#endif gohci.flags = 0; gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; @@ -2065,15 +2001,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (hc_reset (&gohci) < 0) { hc_release_ohci (&gohci); err ("can't reset usb-%s", gohci.slot_name); -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant cleanup */ - board_usb_cleanup(index, USB_INIT_HOST); -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant cleanup */ - usb_cpu_init_fail(); -#endif return -1; } @@ -2081,15 +2008,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant cleanup */ - usb_board_stop(); -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant cleanup */ - usb_cpu_stop(); -#endif return -1; } @@ -2112,17 +2030,6 @@ int usb_lowlevel_stop(int index) /* call hc_release_ohci() here ? */ hc_reset(&gohci); -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant cleanup */ - if (usb_board_stop()) - return -1; -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant cleanup */ - if (usb_cpu_stop()) - return -1; -#endif /* This driver is no longer initialised. It needs a new low-level * init (board/cpu) before it can be used again. */ ohci_inited = 0; diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index a38cd25eb85fc0d24a13b07a58aeaac13232ce16..7699f2e6b15aeb8c67005c7a347aff8a5ce27276 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -151,7 +151,7 @@ struct ohci_hcca { * Maximum number of root hub ports. */ #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS -# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #endif /* diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 80871908dc12e801353a6ce7f1118ae560f7ced1..e67e09e31e4af8a21296f8b30084ea5507c5588f 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -20,16 +20,11 @@ #include /* Declare global data pointer */ -#if !CONFIG_IS_ENABLED(DM_USB) -static struct fsl_xhci fsl_xhci; -unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; -#else struct xhci_fsl_priv { struct xhci_ctrl xhci; fdt_addr_t hcd_base; struct fsl_xhci ctx; }; -#endif __weak int __board_usb_init(int index, enum usb_init_type init) { @@ -108,7 +103,6 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) return 0; } -#if CONFIG_IS_ENABLED(DM_USB) static int xhci_fsl_probe(struct udevice *dev) { struct xhci_fsl_priv *priv = dev_get_priv(dev); @@ -174,44 +168,3 @@ U_BOOT_DRIVER(xhci_fsl) = { .priv_auto = sizeof(struct xhci_fsl_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#else -int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) -{ - struct fsl_xhci *ctx = &fsl_xhci; - int ret = 0; - - ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; - ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); - - ret = board_usb_init(index, USB_INIT_HOST); - if (ret != 0) { - puts("Failed to initialize board for USB\n"); - return ret; - } - - fsl_apply_xhci_errata(); - - ret = fsl_xhci_core_init(ctx); - if (ret < 0) { - puts("Failed to initialize xhci\n"); - return ret; - } - - *hccr = (struct xhci_hccr *)ctx->hcd; - *hcor = (struct xhci_hcor *)((uintptr_t) *hccr - + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n", - (uintptr_t)*hccr, (uintptr_t)*hcor, - (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - return ret; -} - -void xhci_hcd_stop(int index) -{ - struct fsl_xhci *ctx = &fsl_xhci; - - fsl_xhci_core_exit(ctx); -} -#endif diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index ad73ba12e2be51ee793838958cb07427d66c58d4..dbeb88afe37025392f337ef1dc6ce2ee78971fc9 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -37,10 +37,6 @@ #include #include -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - static struct descriptor { struct usb_hub_descriptor hub; struct usb_device_descriptor device; @@ -115,13 +111,8 @@ static struct descriptor { }, }; -#if !CONFIG_IS_ENABLED(DM_USB) -static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; -#endif - struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) { -#if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; /* Find the USB controller */ @@ -130,9 +121,6 @@ struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) dev = dev->parent) ; return dev_get_priv(dev); -#else - return udev->controller; -#endif } /** @@ -752,13 +740,6 @@ static int _xhci_alloc_device(struct usb_device *udev) return 0; } -#if !CONFIG_IS_ENABLED(DM_USB) -int usb_alloc_device(struct usb_device *udev) -{ - return _xhci_alloc_device(udev); -} -#endif - /* * Full speed devices may have a max packet size greater than 8 bytes, but the * USB core doesn't know that until it reads the first 8 bytes of the @@ -1267,95 +1248,6 @@ static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) return 0; } -#if !CONFIG_IS_ENABLED(DM_USB) -int submit_control_msg(struct usb_device *udev, unsigned long pipe, - void *buffer, int length, struct devrequest *setup) -{ - struct usb_device *hop = udev; - - if (hop->parent) - while (hop->parent->parent) - hop = hop->parent; - - return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, - hop->portnr); -} - -int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, - int length) -{ - return _xhci_submit_bulk_msg(udev, pipe, buffer, length); -} - -int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer, - int length, int interval, bool nonblock) -{ - return _xhci_submit_int_msg(udev, pipe, buffer, length, interval, - nonblock); -} - -/** - * Intialises the XHCI host controller - * and allocates the necessary data structures - * - * @param index index to the host controller data structure - * Return: pointer to the intialised controller - */ -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - struct xhci_hccr *hccr; - struct xhci_hcor *hcor; - struct xhci_ctrl *ctrl; - int ret; - - *controller = NULL; - - if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) - return -ENODEV; - - if (xhci_reset(hcor) != 0) - return -ENODEV; - - ctrl = &xhcic[index]; - - ctrl->hccr = hccr; - ctrl->hcor = hcor; - - ret = xhci_lowlevel_init(ctrl); - - if (ret) { - ctrl->hccr = NULL; - ctrl->hcor = NULL; - } else { - *controller = &xhcic[index]; - } - - return ret; -} - -/** - * Stops the XHCI host controller - * and cleans up all the related data structures - * - * @param index index to the host controller data structure - * Return: none - */ -int usb_lowlevel_stop(int index) -{ - struct xhci_ctrl *ctrl = (xhcic + index); - - if (ctrl->hcor) { - xhci_lowlevel_stop(ctrl); - xhci_hcd_stop(index); - xhci_cleanup(ctrl); - } - - return 0; -} -#endif /* CONFIG_IS_ENABLED(DM_USB) */ - -#if CONFIG_IS_ENABLED(DM_USB) - static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) @@ -1546,5 +1438,3 @@ struct dm_usb_ops xhci_usb_ops = { .update_hub_device = xhci_update_hub_device, .get_max_xfer_size = xhci_get_max_xfer_size, }; - -#endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 965b5879274ef253fea78768442fe9e1e3250059..4ecc158c4605e05f2923be568ea41f4cc2afec0f 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -583,6 +583,8 @@ config ATMEL_HLCD source "drivers/video/ti/Kconfig" +source "drivers/video/exynos/Kconfig" + config LOGICORE_DP_TX bool "Enable Logicore DP TX driver" depends on DISPLAY diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 259658074bc1ee2d925ff90b6f9550007ead04cb..7019b26396393e36d822975e803beef7e8aaf358 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -36,9 +36,7 @@ obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o -obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..37e661b1edd2f03d652fccd400afe20887995909 --- /dev/null +++ b/drivers/video/exynos/Kconfig @@ -0,0 +1,20 @@ + +menuconfig VIDEO_EXYNOS + bool "Enable Exynos video support" + depends on DM_VIDEO + help + Enable support for various video output options on Exynos SoCs. + +if VIDEO_EXYNOS + +config EXYNOS_DP + bool "Exynos Display Port support" + +config EXYNOS_FB + bool "Exynos FIMD support" + +config EXYNOS_MIPI_DSIM + bool "Exynos MIPI DSI support" + depends on EXYNOS_FB + +endif diff --git a/drivers/video/exynos/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c deleted file mode 100644 index a3d467aa23b5cb79b914ec152030d03da0f89573..0000000000000000000000000000000000000000 --- a/drivers/video/exynos/exynos_pwm_bl.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PWM BACKLIGHT driver for Board based on EXYNOS. - * - * Author: Donghwa Lee - * - * Derived from linux/drivers/video/backlight/pwm_backlight.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static struct pwm_backlight_data *pwm; - -static int exynos_pwm_backlight_update_status(void) -{ - int brightness = pwm->brightness; - int max = pwm->max_brightness; - - if (brightness == 0) { - pwm_config(pwm->pwm_id, 0, pwm->period); - pwm_disable(pwm->pwm_id); - } else { - pwm_config(pwm->pwm_id, - brightness * pwm->period / max, pwm->period); - pwm_enable(pwm->pwm_id); - } - return 0; -} - -int exynos_pwm_backlight_init(struct pwm_backlight_data *pd) -{ - pwm = pd; - - exynos_pwm_backlight_update_status(); - - return 0; -} diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c deleted file mode 100644 index 21ade8d93c4ade3d43681edebd02dafe293642c6..0000000000000000000000000000000000000000 --- a/drivers/video/pxa_lcd.c +++ /dev/null @@ -1,549 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PXA LCD Controller - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* #define DEBUG */ - -#ifdef CONFIG_LCD - -/*----------------------------------------------------------------------*/ -/* - * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for - * your display. - */ - -#ifdef CONFIG_PXA_VGA -/* LCD outputs connected to a video DAC */ -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f8 -# define REG_LCCR3 0x0300FF01 - -/* 640x480x16 @ 61 Hz */ -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_width = 640, - .vl_height = 480, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 0, - .vl_clor = 0, - .vl_tft = 1, - .vl_hpw = 40, - .vl_blw = 56, - .vl_elw = 56, - .vl_vpw = 20, - .vl_bfw = 8, - .vl_efw = 8, -}; -#endif /* CONFIG_PXA_VIDEO */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_SHARP_LM8V31 - -# define LCD_BPP LCD_COLOR8 -# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x0030087C -# define REG_LCCR3 0x0340FF08 - -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_width = 157, - .vl_height = 118, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 0, - .vl_hpw = 1, - .vl_blw = 3, - .vl_elw = 3, - .vl_vpw = 1, - .vl_bfw = 0, - .vl_efw = 0, -}; -#endif /* CONFIG_SHARP_LM8V31 */ -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_VOIPAC_LCD - -# define LCD_BPP LCD_COLOR8 -# define LCD_INVERT_COLORS - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x043008f8 -# define REG_LCCR3 0x0340FF08 - -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_width = 157, - .vl_height = 118, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 32, - .vl_blw = 144, - .vl_elw = 32, - .vl_vpw = 2, - .vl_bfw = 13, - .vl_efw = 30, -}; -#endif /* CONFIG_VOIPAC_LCD */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SX14 -/* Hitachi SX14Q004-ZZA color STN LCD */ -#define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -#define REG_LCCR0 0x00301079 -#define REG_LCCR3 0x0340FF20 - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 240, - .vl_width = 167, - .vl_height = 109, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 1, - .vl_splt = 0, - .vl_clor = 1, - .vl_tft = 0, - .vl_hpw = 1, - .vl_blw = 1, - .vl_elw = 1, - .vl_vpw = 7, - .vl_bfw = 0, - .vl_efw = 0, -}; -#endif /* CONFIG_HITACHI_SX14 */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_LMS283GF05 - -# define LCD_BPP LCD_COLOR8 -/*# define LCD_INVERT_COLORS*/ - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x043008f8 -# define REG_LCCR3 0x03b00009 - -vidinfo_t panel_info = { - .vl_col = 240, - .vl_row = 320, - .vl_rot = 3, - .vl_width = 240, - .vl_height = 320, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 4, - .vl_blw = 4, - .vl_elw = 8, - .vl_vpw = 4, - .vl_bfw = 4, - .vl_efw = 8, -}; -#endif /* CONFIG_LMS283GF05 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_LQ038J7DH53 - -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f9 -# define REG_LCCR3 0x03700004 - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 480, - .vl_width = 320, - .vl_height = 480, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 0x04, - .vl_blw = 0x20, - .vl_elw = 0x01, - .vl_vpw = 0x01, - .vl_bfw = 0x04, - .vl_efw = 0x01, -}; -#endif /* CONFIG_LQ038J7DH53 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_LITTLETON_LCD -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f8 -# define REG_LCCR3 0x0300FF04 - -vidinfo_t panel_info = { - .vl_col = 480, - .vl_row = 640, - .vl_width = 480, - .vl_height = 640, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 0, - .vl_clor = 0, - .vl_tft = 1, - .vl_hpw = 9, - .vl_blw = 8, - .vl_elw = 24, - .vl_vpw = 2, - .vl_bfw = 2, - .vl_efw = 4, -}; -#endif /* CONFIG_LITTLETON_LCD */ - -/*----------------------------------------------------------------------*/ - -static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); -static void pxafb_setup_gpio (vidinfo_t *vid); -static void pxafb_enable_controller (vidinfo_t *vid); -static int pxafb_init (vidinfo_t *vid); - -/************************************************************************/ -/* --------------- PXA chipset specific functions ------------------- */ -/************************************************************************/ - -ushort *configuration_get_cmap(void) -{ - struct pxafb_info *fbi = &panel_info.pxa; - return (ushort *)fbi->palette; -} - -void lcd_ctrl_init (void *lcdbase) -{ - pxafb_init_mem(lcdbase, &panel_info); - pxafb_init(&panel_info); - pxafb_setup_gpio(&panel_info); - pxafb_enable_controller(&panel_info); -} - -/*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - struct pxafb_info *fbi = &panel_info.pxa; - unsigned short *palette = (unsigned short *)fbi->palette; - u_int val; - - if (regno < fbi->palette_size) { - val = ((red << 8) & 0xf800); - val |= ((green << 4) & 0x07e0); - val |= (blue & 0x001f); - -#ifdef LCD_INVERT_COLORS - palette[regno] = ~val; -#else - palette[regno] = val; -#endif - } - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", - regno, &palette[regno], - red, green, blue, - palette[regno]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ -__weak void lcd_enable(void) -{ -} - -/************************************************************************/ -/* ** PXA255 specific routines */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, - * descriptors and palette areas. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - size += PAGE_SIZE; - - return size; -} - -static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) -{ - u_long palette_mem_size; - struct pxafb_info *fbi = &vid->pxa; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (u_long)lcdbase; - - fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; - palette_mem_size = fbi->palette_size * sizeof(u16); - - debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); - /* locate palette and descs at end of page following fb */ - fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} -#ifdef CONFIG_CPU_MONAHANS -static inline void pxafb_setup_gpio (vidinfo_t *vid) {} -#else -static void pxafb_setup_gpio (vidinfo_t *vid) -{ - u_long lccr0; - - /* - * setup is based on type of panel supported - */ - - lccr0 = vid->pxa.reg_lccr0; - - /* 4 bit interface */ - if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) - { - debug("Setting GPIO for 4 bit data\n"); - /* bits 58-61 */ - writel(readl(GPDR1) | (0xf << 26), GPDR1); - writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), - GAFR1_U); - - /* bits 74-77 */ - writel(readl(GPDR2) | (0xf << 10), GPDR2); - writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), - GAFR2_L); - } - - /* 8 bit interface */ - else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || - (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) - { - debug("Setting GPIO for 8 bit data\n"); - /* bits 58-65 */ - writel(readl(GPDR1) | (0x3f << 26), GPDR1); - writel(readl(GPDR2) | (0x3), GPDR2); - - writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), - GAFR1_U); - writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); - - /* bits 74-77 */ - writel(readl(GPDR2) | (0xf << 10), GPDR2); - writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), - GAFR2_L); - } - - /* 16 bit interface */ - else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) - { - debug("Setting GPIO for 16 bit data\n"); - /* bits 58-77 */ - writel(readl(GPDR1) | (0x3f << 26), GPDR1); - writel(readl(GPDR2) | 0x00003fff, GPDR2); - - writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), - GAFR1_U); - writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); - } - else - { - printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); - } -} -#endif - -static void pxafb_enable_controller (vidinfo_t *vid) -{ - debug("Enabling LCD controller\n"); - - /* Sequence from 11.7.10 */ - writel(vid->pxa.reg_lccr3, LCCR3); - writel(vid->pxa.reg_lccr2, LCCR2); - writel(vid->pxa.reg_lccr1, LCCR1); - writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); - writel(vid->pxa.fdadr0, FDADR0); - writel(vid->pxa.fdadr1, FDADR1); - writel(readl(LCCR0) | LCCR0_ENB, LCCR0); - -#ifdef CONFIG_CPU_MONAHANS - writel(readl(CKENA) | CKENA_1_LCD, CKENA); -#else - writel(readl(CKEN) | CKEN16_LCD, CKEN); -#endif - - debug("FDADR0 = 0x%08x\n", readl(FDADR0)); - debug("FDADR1 = 0x%08x\n", readl(FDADR1)); - debug("LCCR0 = 0x%08x\n", readl(LCCR0)); - debug("LCCR1 = 0x%08x\n", readl(LCCR1)); - debug("LCCR2 = 0x%08x\n", readl(LCCR2)); - debug("LCCR3 = 0x%08x\n", readl(LCCR3)); -} - -static int pxafb_init (vidinfo_t *vid) -{ - struct pxafb_info *fbi = &vid->pxa; - - debug("Configuring PXA LCD\n"); - - fbi->reg_lccr0 = REG_LCCR0; - fbi->reg_lccr3 = REG_LCCR3; - - debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", - vid->vl_col, vid->vl_hpw, - vid->vl_blw, vid->vl_elw); - debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", - vid->vl_row, vid->vl_vpw, - vid->vl_bfw, vid->vl_efw); - - fbi->reg_lccr1 = - LCCR1_DisWdth(vid->vl_col) + - LCCR1_HorSnchWdth(vid->vl_hpw) + - LCCR1_BegLnDel(vid->vl_blw) + - LCCR1_EndLnDel(vid->vl_elw); - - fbi->reg_lccr2 = - LCCR2_DisHght(vid->vl_row) + - LCCR2_VrtSnchWdth(vid->vl_vpw) + - LCCR2_BegFrmDel(vid->vl_bfw) + - LCCR2_EndFrmDel(vid->vl_efw); - - fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); - fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) - | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); - - - /* setup dma descriptors */ - fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ - (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ - (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; - fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; - - fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = fbi->screen; - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; - - fbi->dmadesc_palette->fsadr = fbi->palette; - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; - - if( NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; - fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = (u_long)fbi->dmadesc_palette; - } - else - { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; - fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ - } - - debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); - debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); - debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); - - debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); - debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); - debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); - - debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); - debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); - debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); - - debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); - debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); - debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); - - return 0; -} - -/************************************************************************/ -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c deleted file mode 100644 index 497258f3de92b68d5b04877dc781cb91706cc7f4..0000000000000000000000000000000000000000 --- a/drivers/video/s6e8ax0.c +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee - */ - -#include -#include -#include - -#include "exynos/exynos_mipi_dsi_lowlevel.h" -#include "exynos/exynos_mipi_dsi_common.h" - -static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - int reverse = dsim_dev->dsim_lcd_dev->reverse_panel; - static const unsigned char data_to_send[] = { - 0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c, - 0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20, - 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, - 0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3, - 0xff, 0xff, 0xc8 - }; - - static const unsigned char data_to_send_reverse[] = { - 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c, - 0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20, - 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, - 0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1, - 0xf6, 0xf6, 0xc1 - }; - - if (reverse) { - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send_reverse, - ARRAY_SIZE(data_to_send_reverse)); - } else { - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); - } -} - -static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf2, 0x80, 0x03, 0x0d - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - /* 7500K 2.2 Set : 30cd */ - static const unsigned char data_to_send[] = { - 0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad, - 0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1, - 0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74, - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf7, 0x03 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf6, 0x00, 0x02, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, - 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe3, 0x40 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xb1, 0x04, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0x29, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0x11, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf0, 0x5a, 0x5a - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf1, 0x5a, 0x5a - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) -{ - /* - * in case of setting gamma and panel condition at first, - * it shuold be setting like below. - * set_gamma() -> set_panel_condition() - */ - - s6e8ax0_apply_level1_key(dsim_dev); - s6e8ax0_apply_mtp_key(dsim_dev); - - s6e8ax0_sleep_out(dsim_dev); - mdelay(5); - s6e8ax0_panel_cond(dsim_dev); - s6e8ax0_display_cond(dsim_dev); - s6e8ax0_gamma_cond(dsim_dev); - s6e8ax0_gamma_update(dsim_dev); - - s6e8ax0_etc_source_control(dsim_dev); - s6e8ax0_elvss_set(dsim_dev); - s6e8ax0_etc_pentile_control(dsim_dev); - s6e8ax0_etc_mipi_control1(dsim_dev); - s6e8ax0_etc_mipi_control2(dsim_dev); - s6e8ax0_etc_power_control(dsim_dev); - s6e8ax0_etc_mipi_control3(dsim_dev); - s6e8ax0_etc_mipi_control4(dsim_dev); -} - -static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev) -{ - s6e8ax0_panel_init(dsim_dev); - - return 0; -} - -static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev) -{ - s6e8ax0_display_on(dsim_dev); -} - -static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = { - .name = "s6e8ax0", - .id = -1, - - .mipi_panel_init = s6e8ax0_panel_set, - .mipi_display_on = s6e8ax0_display_enable, -}; - -void s6e8ax0_init(void) -{ - exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver); -} diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 7f1cbc59329ef3b7b14e257ca4eb86b03dea5b72..f71bab784773b46ba1fee10cdfecdacc484e16f9 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -16,21 +16,40 @@ #include #include +static unsigned int virtqueue_attach_desc(struct virtqueue *vq, unsigned int i, + struct virtio_sg *sg, u16 flags) +{ + struct vring_desc_shadow *desc_shadow = &vq->vring_desc_shadow[i]; + struct vring_desc *desc = &vq->vring.desc[i]; + + /* Update the shadow descriptor. */ + desc_shadow->addr = (u64)(uintptr_t)sg->addr; + desc_shadow->len = sg->length; + desc_shadow->flags = flags; + + /* Update the shared descriptor to match the shadow. */ + desc->addr = cpu_to_virtio64(vq->vdev, desc_shadow->addr); + desc->len = cpu_to_virtio32(vq->vdev, desc_shadow->len); + desc->flags = cpu_to_virtio16(vq->vdev, desc_shadow->flags); + desc->next = cpu_to_virtio16(vq->vdev, desc_shadow->next); + + return desc_shadow->next; +} + int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[], unsigned int out_sgs, unsigned int in_sgs) { struct vring_desc *desc; - unsigned int total_sg = out_sgs + in_sgs; - unsigned int i, n, avail, descs_used, uninitialized_var(prev); + unsigned int descs_used = out_sgs + in_sgs; + unsigned int i, n, avail, uninitialized_var(prev); int head; - WARN_ON(total_sg == 0); + WARN_ON(descs_used == 0); head = vq->free_head; desc = vq->vring.desc; i = head; - descs_used = total_sg; if (vq->num_free < descs_used) { debug("Can't add buf len %i - avail = %i\n", @@ -45,30 +64,17 @@ int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[], return -ENOSPC; } - for (n = 0; n < out_sgs; n++) { - struct virtio_sg *sg = sgs[n]; - - desc[i].flags = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT); - desc[i].addr = cpu_to_virtio64(vq->vdev, (u64)(size_t)sg->addr); - desc[i].len = cpu_to_virtio32(vq->vdev, sg->length); - - prev = i; - i = virtio16_to_cpu(vq->vdev, desc[i].next); - } - for (; n < (out_sgs + in_sgs); n++) { - struct virtio_sg *sg = sgs[n]; - - desc[i].flags = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT | - VRING_DESC_F_WRITE); - desc[i].addr = cpu_to_virtio64(vq->vdev, - (u64)(uintptr_t)sg->addr); - desc[i].len = cpu_to_virtio32(vq->vdev, sg->length); + for (n = 0; n < descs_used; n++) { + u16 flags = VRING_DESC_F_NEXT; + if (n >= out_sgs) + flags |= VRING_DESC_F_WRITE; prev = i; - i = virtio16_to_cpu(vq->vdev, desc[i].next); + i = virtqueue_attach_desc(vq, i, sgs[n], flags); } /* Last one doesn't continue */ - desc[prev].flags &= cpu_to_virtio16(vq->vdev, ~VRING_DESC_F_NEXT); + vq->vring_desc_shadow[prev].flags &= ~VRING_DESC_F_NEXT; + desc[prev].flags = cpu_to_virtio16(vq->vdev, vq->vring_desc_shadow[prev].flags); /* We're using some buffers from the free list. */ vq->num_free -= descs_used; @@ -76,6 +82,9 @@ int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[], /* Update free pointer */ vq->free_head = i; + /* Mark the descriptor as the head of a chain. */ + vq->vring_desc_shadow[head].chain_head = true; + /* * Put entry in available array (but don't update avail->idx * until they do sync). @@ -137,17 +146,19 @@ void virtqueue_kick(struct virtqueue *vq) static void detach_buf(struct virtqueue *vq, unsigned int head) { unsigned int i; - __virtio16 nextflag = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT); + + /* Unmark the descriptor as the head of a chain. */ + vq->vring_desc_shadow[head].chain_head = false; /* Put back on free list: unmap first-level descriptors and find end */ i = head; - while (vq->vring.desc[i].flags & nextflag) { - i = virtio16_to_cpu(vq->vdev, vq->vring.desc[i].next); + while (vq->vring_desc_shadow[i].flags & VRING_DESC_F_NEXT) { + i = vq->vring_desc_shadow[i].next; vq->num_free++; } - vq->vring.desc[i].next = cpu_to_virtio16(vq->vdev, vq->free_head); + vq->vring_desc_shadow[i].next = vq->free_head; vq->free_head = head; /* Plus final descriptor */ @@ -189,6 +200,12 @@ void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len) return NULL; } + if (unlikely(!vq->vring_desc_shadow[i].chain_head)) { + printf("(%s.%d): id %u is not a head\n", + vq->vdev->name, vq->index, i); + return NULL; + } + detach_buf(vq, i); vq->last_used_idx++; /* @@ -200,8 +217,7 @@ void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len) virtio_store_mb(&vring_used_event(&vq->vring), cpu_to_virtio16(vq->vdev, vq->last_used_idx)); - return (void *)(uintptr_t)virtio64_to_cpu(vq->vdev, - vq->vring.desc[i].addr); + return (void *)(uintptr_t)vq->vring_desc_shadow[i].addr; } static struct virtqueue *__vring_new_virtqueue(unsigned int index, @@ -210,6 +226,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, { unsigned int i; struct virtqueue *vq; + struct vring_desc_shadow *vring_desc_shadow; struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); struct udevice *vdev = uc_priv->vdev; @@ -217,10 +234,17 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, if (!vq) return NULL; + vring_desc_shadow = calloc(vring.num, sizeof(struct vring_desc_shadow)); + if (!vring_desc_shadow) { + free(vq); + return NULL; + } + vq->vdev = vdev; vq->index = index; vq->num_free = vring.num; vq->vring = vring; + vq->vring_desc_shadow = vring_desc_shadow; vq->last_used_idx = 0; vq->avail_flags_shadow = 0; vq->avail_idx_shadow = 0; @@ -238,7 +262,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, /* Put everything in free lists */ vq->free_head = 0; for (i = 0; i < vring.num - 1; i++) - vq->vring.desc[i].next = cpu_to_virtio16(vdev, i + 1); + vq->vring_desc_shadow[i].next = i + 1; return vq; } @@ -291,6 +315,7 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num, void vring_del_virtqueue(struct virtqueue *vq) { free(vq->vring.desc); + free(vq->vring_desc_shadow); list_del(&vq->list); free(vq); } @@ -336,11 +361,12 @@ void virtqueue_dump(struct virtqueue *vq) printf("\tlast_used_idx %u, avail_flags_shadow %u, avail_idx_shadow %u\n", vq->last_used_idx, vq->avail_flags_shadow, vq->avail_idx_shadow); - printf("Descriptor dump:\n"); + printf("Shadow descriptor dump:\n"); for (i = 0; i < vq->vring.num; i++) { - printf("\tdesc[%u] = { 0x%llx, len %u, flags %u, next %u }\n", - i, vq->vring.desc[i].addr, vq->vring.desc[i].len, - vq->vring.desc[i].flags, vq->vring.desc[i].next); + struct vring_desc_shadow *desc = &vq->vring_desc_shadow[i]; + + printf("\tdesc_shadow[%u] = { 0x%llx, len %u, flags %u, next %u }\n", + i, desc->addr, desc->len, desc->flags, desc->next); } printf("Avail ring dump:\n"); diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c index 9314c0a03ed70412851863db2a357a31020a9aad..b85545c2ee5c1b74679b4e0f27ba6353704f276c 100644 --- a/drivers/virtio/virtio_rng.c +++ b/drivers/virtio/virtio_rng.c @@ -41,6 +41,9 @@ static int virtio_rng_read(struct udevice *dev, void *data, size_t len) while (!virtqueue_get_buf(priv->rng_vq, &rsize)) ; + if (rsize > sg.length) + return -EIO; + memcpy(ptr, buf, rsize); len -= rsize; ptr += rsize; diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c index aafb7beb949d2c6d03f79df3d8445d6b53ec31f0..5484ae3a1a0417315f48bd80e1693de8c3bdf154 100644 --- a/drivers/virtio/virtio_sandbox.c +++ b/drivers/virtio/virtio_sandbox.c @@ -160,8 +160,8 @@ static int virtio_sandbox_probe(struct udevice *udev) struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); /* fake some information for testing */ - priv->device_features = VIRTIO_F_VERSION_1; - uc_priv->device = VIRTIO_ID_BLOCK; + priv->device_features = BIT_ULL(VIRTIO_F_VERSION_1); + uc_priv->device = VIRTIO_ID_RNG; uc_priv->vendor = ('u' << 24) | ('b' << 16) | ('o' << 8) | 't'; return 0; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index c3eb8a8aec1beec6c98f4a2a29e15c83a00095ac..532ada89c1b263f86dbb1361d03f8747e213ee0e 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -64,8 +64,8 @@ config ULP_WATCHDOG config DESIGNWARE_WATCHDOG bool "Designware watchdog timer support" - select HW_WATCHDOG if !WDT - default y if WDT && ROCKCHIP_RK3399 + depends on WDT + default y if ROCKCHIP_RK3399 help Enable this to support Designware Watchdog Timer IP, present e.g. on Altera SoCFPGA SoCs. diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index cfec29bd158c7a9a976536177793a990f60e005b..cad756aeaf20bb8007a5e82ace4d50a7d02f0336 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -60,26 +60,6 @@ static void designware_wdt_reset_common(void __iomem *base) writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR); } -#if !CONFIG_IS_ENABLED(WDT) -void hw_watchdog_reset(void) -{ - designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE); -} - -void hw_watchdog_init(void) -{ - /* reset to disable the watchdog */ - hw_watchdog_reset(); - /* set timer in miliseconds */ - designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE, - CONFIG_DW_WDT_CLOCK_KHZ, - CONFIG_WATCHDOG_TIMEOUT_MSECS); - /* enable the watchdog */ - designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE); - /* reset the watchdog */ - hw_watchdog_reset(); -} -#else static int designware_wdt_reset(struct udevice *dev) { struct designware_wdt_priv *priv = dev_get_priv(dev); @@ -195,4 +175,3 @@ U_BOOT_DRIVER(designware_wdt) = { .ops = &designware_wdt_ops, .flags = DM_FLAG_PRE_RELOC, }; -#endif diff --git a/dts/Kconfig b/dts/Kconfig index f1d05cc0803f1eb2606cbaa6c3b9912557f52964..bc5f22029ff9543ca8ef9fa356abc0b282582a9e 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -534,6 +534,7 @@ endif config VPL_OF_REAL def_bool y + depends on VPL help Indicates that a real devicetree is available which can be accessed at runtime. This means that dev_read_...() functions can be used to diff --git a/env/Kconfig b/env/Kconfig index 2f625b22575a1e4ec3f582031c63e0c598ac142a..238e4c70cf05fe4f02f2b2dd20a12ac020620f8e 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -30,6 +30,22 @@ config ENV_OVERWRITE Use this to permit overriding of certain environmental variables like Ethernet and Serial +config ENV_MIN_ENTRIES + int "Minimum number of entries in the environment hashtable" + default 64 + help + Minimum number of entries in the hash table that is used internally + to store the environment settings. + +config ENV_MAX_ENTRIES + int "Maximumm number of entries in the environment hashtable" + default 512 + help + Maximum number of entries in the hash table that is used internally + to store the environment settings. The default setting is supposed to + be generous and should work in most cases. This setting can be used + to tune behaviour; see lib/hashtable.c for details. + config ENV_IS_NOWHERE bool "Environment is not stored" default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ @@ -248,14 +264,6 @@ config ENV_IS_IN_NAND during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be aligned to an erase block boundary. - - CONFIG_ENV_RANGE (optional): - - Specifies the length of the region in which the environment - can be written. This should be a multiple of the NAND device's - block size. Specifying a range with more erase blocks than - are needed to hold CONFIG_ENV_SIZE allows bad blocks within - the range to be avoided. - - CONFIG_ENV_OFFSET_OOB (optional): Enables support for dynamically retrieving the offset of the @@ -264,6 +272,16 @@ config ENV_IS_IN_NAND Currently, CONFIG_ENV_OFFSET_REDUND is not supported when using CONFIG_ENV_OFFSET_OOB. +config ENV_RANGE + hex "Length of the region in which the environment can be written" + depends on ENV_IS_IN_NAND + range ENV_SIZE 0x7fffffff + default ENV_SIZE + help + This should be a multiple of the NAND device's block size. + Specifying a range with more erase blocks than are needed to hold + CONFIG_ENV_SIZE allows bad blocks within the range to be avoided. + config ENV_IS_IN_NVRAM bool "Environment in a non-volatile RAM" depends on !CHAIN_OF_TRUST diff --git a/env/ext4.c b/env/ext4.c index 9f65afb8a4235036ae2faafec8f483c78264ef52..47e05a489193103d2599da89616d5aba8557bd08 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -31,6 +31,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -146,6 +147,10 @@ static int env_ext4_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(ifname, "scsi")) + scsi_scan(true); +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); diff --git a/env/fat.c b/env/fat.c index 6251d9649b194237f12047d72faa2296cb5a9784..3172130d75d3d639f730d20b3c5aa39a6b3d46b5 100644 --- a/env/fat.c +++ b/env/fat.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -128,7 +129,12 @@ static int env_fat_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif - +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) + scsi_scan(true); +#endif +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); if (part < 0) diff --git a/env/nand.c b/env/nand.c index 21aa367d5bdfedf45fb7805bfa5b7f35b3b1ec9b..df300b13179312babc6ee3c47e2cba1d165c30fb 100644 --- a/env/nand.c +++ b/env/nand.c @@ -33,10 +33,6 @@ #error CONFIG_ENV_OFFSET_REDUND must have CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND #endif -#ifndef CONFIG_ENV_RANGE -#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE -#endif - #if defined(ENV_IS_EMBEDDED) static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) @@ -201,10 +197,6 @@ static int env_nand_save(void) #endif }; - - if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) - return 1; - ret = env_export(env_new); if (ret) return ret; diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index d00b5153336d9b13dfedf7403a5b3d5c5dfd2e6f..0173d30cd8ab392712221d00bbb1bad76bd50122 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -546,15 +546,12 @@ static int lookup_data_extent(struct btrfs_root *root, struct btrfs_path *path, /* Error or we're already at the file extent */ if (ret <= 0) return ret; - if (ret > 0) { - /* Check previous file extent */ - ret = btrfs_previous_item(root, path, ino, - BTRFS_EXTENT_DATA_KEY); - if (ret < 0) - return ret; - if (ret > 0) - goto check_next; - } + /* Check previous file extent */ + ret = btrfs_previous_item(root, path, ino, BTRFS_EXTENT_DATA_KEY); + if (ret < 0) + return ret; + if (ret > 0) + goto check_next; /* Now the key.offset must be smaller than @file_offset */ btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]); if (key.objectid != ino || diff --git a/fs/cbfs/Kconfig b/fs/cbfs/Kconfig index 03980d830d304487c12f5abecdbf913c309b71be..b6639928f4afeabc40c5b72225057043cd3272a3 100644 --- a/fs/cbfs/Kconfig +++ b/fs/cbfs/Kconfig @@ -9,6 +9,7 @@ config FS_CBFS config SPL_FS_CBFS bool "Enable CBFS (Coreboot Filesystem) in SPL" + depends on SPL help Define this to enable support for reading from a Coreboot filesystem. This is a ROM-based filesystem used for accessing files diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 9c1f87caca10d607d8b7ff0d816c8963c52d56cf..74ca70c3ff4ef063680707ab41c3b65a4bf985cb 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -50,7 +50,7 @@ static int sqfs_read_sblk(struct squashfs_super_block **sblk) if (sqfs_disk_read(0, 1, *sblk) != 1) { free(*sblk); - sblk = NULL; + *sblk = NULL; return -EINVAL; } diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index e3a4c0bca27055791f7f4119b3e4b83d0d96fe1c..034c41a703568611ac2390987a0afaa2f4e4a36a 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -1757,6 +1757,8 @@ void ubifs_umount(struct ubifs_info *c) kfree(c->bottom_up_buf); ubifs_debugging_exit(c); #ifdef __UBOOT__ + ubi_close_volume(c->ubi); + mutex_unlock(&c->umount_mutex); /* Finally free U-Boot's global copy of superblock */ if (ubifs_sb != NULL) { free(ubifs_sb->s_fs_info); @@ -2058,9 +2060,9 @@ static void ubifs_put_super(struct super_block *sb) ubifs_umount(c); #ifndef __UBOOT__ bdi_destroy(&c->bdi); -#endif ubi_close_volume(c->ubi); mutex_unlock(&c->umount_mutex); +#endif } #endif @@ -2327,6 +2329,9 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) out_umount: ubifs_umount(c); +#ifdef __UBOOT__ + goto out; +#endif out_unlock: mutex_unlock(&c->umount_mutex); #ifndef __UBOOT__ diff --git a/include/SA-1100.h b/include/SA-1100.h deleted file mode 100644 index 7589df238a6f9dc556541d8cb452a0543a93cc8a..0000000000000000000000000000000000000000 --- a/include/SA-1100.h +++ /dev/null @@ -1,2833 +0,0 @@ -/* - * FILE SA-1100.h - * - * Version 1.2 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date January 1998 (April 1997) - * System StrongARM SA-1100 - * Language C or ARM Assembly - * Purpose Definition of constants related to the StrongARM - * SA-1100 microprocessor (Advanced RISC Machine (ARM) - * architecture version 4). This file is based on the - * StrongARM SA-1100 data sheet version 2.2. - * - * Language-specific definitions are selected by the - * macro "LANGUAGE", which should be defined as either - * "C" (default) or "Assembly". - */ - - -#ifndef LANGUAGE -# ifdef __ASSEMBLY__ -# define LANGUAGE Assembly -# else -# define LANGUAGE C -# endif -#endif - -#ifndef io_p2v -#define io_p2v(PhAdd) (PhAdd) -#endif - -#include - -#define C 0 -#define Assembly 1 - - -#if LANGUAGE == C -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; -#endif /* LANGUAGE == C */ - - -/* - * Memory - */ - -#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ - -#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ -#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ - /* [byte] */ -#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ - /* [byte] */ -#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ - /* [byte] */ -#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ - /* [byte] */ - -#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ -#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ -#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ -#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ -#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ - -#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ - -#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ - (0x00000000 + (Nb)*StMemBnkSp) -#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ -#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ -#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ -#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ - -#if LANGUAGE == C -typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; -#define StMemBnk /* Static Memory Bank [0..3] */ \ - ((StMemBnkType *) io_p2v (_StMemBnk (0))) -#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ -#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ -#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ -#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ -#endif /* LANGUAGE == C */ - -#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ - (0xC0000000 + (Nb)*DRAMBnkSp) -#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ -#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ -#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ -#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ - -#if LANGUAGE == C -typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; -#define DRAMBnk /* DRAM Bank [0..3] */ \ - ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) -#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ -#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ -#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ -#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ -#endif /* LANGUAGE == C */ - -#define _ZeroMem 0xE0000000 /* Zero Memory bank */ - -#if LANGUAGE == C -typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; -#define ZeroMem /* Zero Memory bank */ \ - (*((ZeroMemType *) io_p2v (_ZeroMem))) -#endif /* LANGUAGE == C */ - - -/* - * Personal Computer Memory Card International Association (PCMCIA) sockets - */ - -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ - -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ - -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ - -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) - -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ - -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ - -#if LANGUAGE == C - -typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; -typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; - -#define PCMCIA0 /* PCMCIA 0 */ \ - (*((PCMCIAType *) io_p2v (_PCMCIA0))) -#define PCMCIA0IO /* PCMCIA 0 I/O */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) -#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) -#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) - -#define PCMCIA1 /* PCMCIA 1 */ \ - (*((PCMCIAType *) io_p2v (_PCMCIA1))) -#define PCMCIA1IO /* PCMCIA 1 I/O */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) -#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) -#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) - -#endif /* LANGUAGE == C */ - - -/* - * Universal Serial Bus (USB) Device Controller (UDC) control registers - * - * Registers - * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control Register (read/write). - * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Address Register (read/write). - * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Output Maximum Packet size register - * (read/write). - * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Input Maximum Packet size register - * (read/write). - * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 0 - * (read/write). - * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 1 - * (output, read/write). - * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 2 - * (input, read/write). - * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data register end-point 0 - * (read/write). - * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Write Count register end-point 0 - * (read). - * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data Register (read/write). - * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Status Register (read/write). - */ - -#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ -#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ -#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ - /* Packet size reg. */ -#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ - /* Packet size reg. */ -#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 0 */ -#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 1 (output) */ -#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 2 (input) */ -#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ - /* end-point 0 */ -#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ - /* reg. end-point 0 */ -#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ -#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ - -#if LANGUAGE == C -#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCR))) -#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCAR))) -#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ - /* Packet size reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCOMP))) -#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ - /* Packet size reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCIMP))) -#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS0))) -#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 1 (output) */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS1))) -#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 2 (input) */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS2))) -#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ - /* end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCD0))) -#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ - /* reg. end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCWC))) -#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCDR))) -#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCSR))) -#endif /* LANGUAGE == C */ - -#define UDCCR_UDD 0x00000001 /* UDC Disable */ -#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ -#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ -#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ - /* (disable) */ -#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ - /* (disable) */ -#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ - /* (disable) */ -#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ - /* (disable) */ -#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ -#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ - -#define UDCAR_ADD Fld (7, 0) /* function ADDress */ - -#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) - -#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCIMP_INMAXP)) - -#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ -#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ -#define UDCCS0_SST 0x00000004 /* Sent STall */ -#define UDCCS0_FST 0x00000008 /* Force STall */ -#define UDCCS0_DE 0x00000010 /* Data End */ -#define UDCCS0_SE 0x00000020 /* Setup End (read) */ -#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ - /* (write) */ -#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ - -#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ - /* Service request (read) */ -#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ -#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ -#define UDCCS1_SST 0x00000008 /* Sent STall */ -#define UDCCS1_FST 0x00000010 /* Force STall */ -#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ - -#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ - /* Service request (read) */ -#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ -#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ -#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ -#define UDCCS2_SST 0x00000010 /* Sent STall */ -#define UDCCS2_FST 0x00000020 /* Force STall */ - -#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ - -#define UDCWC_WC Fld (4, 0) /* Write Count */ - -#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ - -#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ -#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ -#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ -#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ -#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ -#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ - - -/* - * Universal Asynchronous Receiver/Transmitter (UART) control registers - * - * Registers - * Ser1UTCR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser1UTCR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser1UTCR2 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser1UTCR3 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser1UTDR Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser1UTSR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser1UTSR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Ser2UTCR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser2UTCR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser2UTCR2 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser2UTCR3 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser2UTCR4 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 4 - * (read/write). - * Ser2UTDR Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser2UTSR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser2UTSR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Ser3UTCR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser3UTCR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser3UTCR2 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser3UTCR3 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser3UTDR Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser3UTSR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser3UTSR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fua, Tua Frequency, period of the UART communication. - */ - -#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ - (0x80010000 + ((Nb) - 1)*0x00020000) -#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ - (0x80010004 + ((Nb) - 1)*0x00020000) -#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ - (0x80010008 + ((Nb) - 1)*0x00020000) -#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ - (0x8001000C + ((Nb) - 1)*0x00020000) -#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ - (0x80010010 + ((Nb) - 1)*0x00020000) -#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ - (0x80010014 + ((Nb) - 1)*0x00020000) -#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ - (0x8001001C + ((Nb) - 1)*0x00020000) -#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ - (0x80010020 + ((Nb) - 1)*0x00020000) - -#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ -#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ -#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ -#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ -#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ -#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ -#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ - -#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ -#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ -#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ -#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ -#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ -#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ -#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ -#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ - -#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ -#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ -#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ -#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ -#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ -#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ -#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ - -#if LANGUAGE == C - -#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR0))) -#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR1))) -#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR2))) -#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR3))) -#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser1UTDR))) -#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1UTSR0))) -#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1UTSR1))) - -#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR0))) -#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR1))) -#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR2))) -#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR3))) -#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR4))) -#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser2UTDR))) -#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2UTSR0))) -#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2UTSR1))) - -#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR0))) -#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR1))) -#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR2))) -#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR3))) -#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser3UTDR))) -#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser3UTSR0))) -#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser3UTSR1))) - -#elif LANGUAGE == Assembly -#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0)) -#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1)) -#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2)) -#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3)) -#define Ser1UTDR ( io_p2v (_Ser1UTDR)) -#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0)) -#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1)) - -#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0)) -#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1)) -#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2)) -#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3)) -#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4)) -#define Ser2UTDR ( io_p2v (_Ser2UTDR)) -#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0)) -#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1)) - -#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0)) -#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1)) -#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2)) -#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3)) -#define Ser3UTDR ( io_p2v (_Ser3UTDR)) -#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0)) -#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1)) - -#endif /* LANGUAGE == C */ - -#define UTCR0_PE 0x00000001 /* Parity Enable */ -#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ -#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ -#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ -#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ -#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ -#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ -#define UTCR0_DSS 0x00000008 /* Data Size Select */ -#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ -#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ -#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ - /* (ser. port 1: GPIO [18], */ - /* ser. port 3: GPIO [20]) */ -#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ -#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ -#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ -#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ -#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ -#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ - (UTCR0_1StpBit + UTCR0_8BitData) - -#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ -#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fua = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tua = 16*(BRD [11:0] + 1)*Txtl */ -#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) -#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Floor (Div/16)) */ - /* Tua = 16*Floor (Div/16)*Txtl */ -#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) -#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Ceil (Div/16)) */ - /* Tua = 16*Ceil (Div/16)*Txtl */ - -#define UTCR3_RXE 0x00000001 /* Receive Enable */ -#define UTCR3_TXE 0x00000002 /* Transmit Enable */ -#define UTCR3_BRK 0x00000004 /* BReaK mode */ -#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ -#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ -#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ - /* TIE, LBM can be set or cleared) */ \ - (UTCR3_RXE + UTCR3_TXE) - -#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ - /* (HP-SIR) modulation Enable */ -#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ -#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ -#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ -#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ -#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ - -#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ -#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ -#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ -#define UTSR0_RID 0x00000004 /* Receiver IDle */ -#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ -#define UTSR0_REB 0x00000010 /* Receive End of Break */ -#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ - -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ -#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ -#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ -#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ -#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ -#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ - - -/* - * Synchronous Data Link Controller (SDLC) control registers - * - * Registers - * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 0 (read/write). - * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 1 (read/write). - * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 2 (read/write). - * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 3 (read/write). - * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 4 (read/write). - * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) - * Data Register (read/write). - * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 0 (read/write). - * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 1 (read/write). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fsd, Tsd Frequency, period of the SDLC communication. - */ - -#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ -#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */ -#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ -#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ -#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ -#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ -#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ -#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ - -#if LANGUAGE == C -#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR0))) -#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR1))) -#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR2))) -#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR3))) -#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR4))) -#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser1SDDR))) -#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1SDSR0))) -#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1SDSR1))) -#endif /* LANGUAGE == C */ - -#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ -#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ -#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ -#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ -#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ -#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ -#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ -#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ -#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ -#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ -#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ -#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ - /* (GPIO [16]) */ -#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ -#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ -#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ -#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ -#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ -#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ -#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ -#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ - -#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ - /* (GPIO [17]) */ -#define SDCR1_TXE 0x00000002 /* Transmit Enable */ -#define SDCR1_RXE 0x00000004 /* Receive Enable */ -#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ -#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SDCR1_AME 0x00000020 /* Address Match Enable */ -#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ -#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ -#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ -#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ - -#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ - -#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ -#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ -#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) -#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Floor (Div/16)) */ - /* Tsd = 16*Floor (Div/16)*Txtl */ -#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) -#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Ceil (Div/16)) */ - /* Tsd = 16*Ceil (Div/16)*Txtl */ - -#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ -#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define SDSR0_RAB 0x00000004 /* Receive ABort */ -#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ - -#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ -#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ -#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ -#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ -#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ - - -/* - * High-Speed Serial to Parallel controller (HSSP) control registers - * - * Registers - * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 0 (read/write). - * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 1 (read/write). - * Ser2HSDR Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Data Register (read/write). - * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 0 (read/write). - * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 1 (read). - * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 2 (read/write). - * [The HSCR2 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - */ - -#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ -#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ -#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ -#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ -#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ -#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ - -#if LANGUAGE == C -#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR0))) -#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR1))) -#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser2HSDR))) -#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2HSSR0))) -#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2HSSR1))) -#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR2))) -#endif /* LANGUAGE == C */ - -#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ -#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ -#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ -#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ -#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ -#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ -#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ -#define HSCR0_TXE 0x00000008 /* Transmit Enable */ -#define HSCR0_RXE 0x00000010 /* Receive Enable */ -#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Interrupt Enable */ -#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define HSCR0_AME 0x00000080 /* Address Match Enable */ - -#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ - -#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ -#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ -#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ -#endif /* 0 */ - -#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define HSSR0_RAB 0x00000004 /* Receive ABort */ -#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Service request (read) */ -#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ - -#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ -#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ -#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ -#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ - -#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ -#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ - /* (inverted) */ -#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ - /* (non-inverted) */ -#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ -#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ - /* (inverted) */ -#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ - /* (non-inverted) */ - - -/* - * Multi-media Communications Port (MCP) control registers - * - * Registers - * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 0 (read/write). - * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 0 (audio, read/write). - * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 1 (telecom, read/write). - * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 2 (CODEC registers, read/write). - * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) - * Status Register (read/write). - * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 1 (read/write). - * [The MCCR1 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * - * Clocks - * fmc, Tmc Frequency, period of the MCP communication (10 MHz, - * 12 MHz, or GPIO [21]). - * faud, Taud Frequency, period of the audio sampling. - * ftcm, Ttcm Frequency, period of the telecom sampling. - */ - -#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ -#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ - /* (audio) */ -#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ - /* (telecom) */ -#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ - /* (CODEC reg.) */ -#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ -#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ - -#if LANGUAGE == C -#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser4MCCR0))) -#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ - /* (audio) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR0))) -#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ - /* (telecom) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR1))) -#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ - /* (CODEC reg.) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR2))) -#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4MCSR))) -#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser4MCCR1))) -#endif /* LANGUAGE == C */ - -#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ - /* [6..127] */ - /* faud = fmc/(32*ASD) */ - /* Taud = 32*ASD*Tmc */ -#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ - /* [192..4064] */ \ - ((Div)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Floor (Div/32)) */ - /* Taud = 32*Floor (Div/32)*Tmc */ -#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Ceil (Div/32)) */ - /* Taud = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ - /* Divisor/32 [16..127] */ - /* ftcm = fmc/(32*TSD) */ - /* Ttcm = 32*TSD*Tmc */ -#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ - /* [512..4064] */ \ - ((Div)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Floor (Div/32)) */ - /* Ttcm = 32*Floor (Div/32)*Tmc */ -#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Ceil (Div/32)) */ - /* Ttcm = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_MCE 0x00010000 /* MCP Enable */ -#define MCCR0_ECS 0x00020000 /* External Clock Select */ -#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ -#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ -#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ - /* sampling/storing Mode */ -#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ -#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ -#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ -#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ - /* or more interrupt Enable */ -#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ -#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ - /* more interrupt Enable */ -#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ -#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ -#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ - (((Div) - 1) << FShft (MCCR0_ECP)) - -#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ - /* FIFOs */ - -#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ - /* FIFOs */ - - /* receive/transmit CODEC reg. */ - /* FIFOs: */ -#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ -#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ -#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ -#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ -#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ - -#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ - /* or less Service request (read) */ -#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ - /* more Service request (read) */ -#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ - /* or less Service request (read) */ -#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ - /* or more Service request (read) */ -#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ -#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ -#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ -#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ -#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ - /* (read) */ -#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ - /* (read) */ -#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ - /* (read) */ -#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ - /* (read) */ -#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ - /* (read) */ -#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ - /* (read) */ -#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ -#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ - -#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ -#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ - /* (11.981 MHz) */ -#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ - /* (9.585 MHz) */ - - -/* - * Synchronous Serial Port (SSP) control registers - * - * Registers - * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 0 (read/write). - * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 1 (read/write). - * [Bits SPO and SP are only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data - * Register (read/write). - * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status - * Register (read/write). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fss, Tss Frequency, period of the SSP communication. - */ - -#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ -#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ -#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ -#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ - -#if LANGUAGE == C -#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser4SSCR0))) -#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser4SSCR1))) -#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4SSDR))) -#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4SSSR))) -#endif /* LANGUAGE == C */ - -#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ -#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ - (((Size) - 1) << FShft (SSCR0_DSS)) -#define SSCR0_FRF Fld (2, 4) /* FRame Format */ -#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ - /* Interface (SPI) format */ \ - (0 << FShft (SSCR0_FRF)) -#define SSCR0_TI /* Texas Instruments Synchronous */ \ - /* Serial format */ \ - (1 << FShft (SSCR0_FRF)) -#define SSCR0_National /* National Microwire format */ \ - (2 << FShft (SSCR0_FRF)) -#define SSCR0_SSE 0x00000080 /* SSP Enable */ -#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ - /* fss = fxtl/(2*(SCR + 1)) */ - /* Tss = 2*(SCR + 1)*Txtl */ -#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Floor (Div/2)) */ - /* Tss = 2*Floor (Div/2)*Txtl */ -#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Ceil (Div/2)) */ - /* Tss = 2*Ceil (Div/2)*Txtl */ - -#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ - /* Interrupt Enable */ -#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ -#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ -#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ -#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ -#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ -#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ - /* after frame (SFRM, 1st edge) */ -#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ - /* after frame (SFRM, 1st edge) */ -#define SSCR1_ECS 0x00000020 /* External Clock Select */ -#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ -#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ - -#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ - -#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ -#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ -#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ -#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ - /* Service request (read) */ -#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ - - -/* - * Operating System (OS) timer control registers - * - * Registers - * OSMR0 Operating System (OS) timer Match Register 0 - * (read/write). - * OSMR1 Operating System (OS) timer Match Register 1 - * (read/write). - * OSMR2 Operating System (OS) timer Match Register 2 - * (read/write). - * OSMR3 Operating System (OS) timer Match Register 3 - * (read/write). - * OSCR Operating System (OS) timer Counter Register - * (read/write). - * OSSR Operating System (OS) timer Status Register - * (read/write). - * OWER Operating System (OS) timer Watch-dog Enable Register - * (read/write). - * OIER Operating System (OS) timer Interrupt Enable Register - * (read/write). - */ - -#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ - (0x90000000 + (Nb)*4) -#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ -#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ -#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ -#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ -#define _OSCR 0x90000010 /* OS timer Counter Reg. */ -#define _OSSR 0x90000014 /* OS timer Status Reg. */ -#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ -#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ - -#if LANGUAGE == C -#define OSMR /* OS timer Match Reg. [0..3] */ \ - ((volatile Word *) io_p2v (_OSMR (0))) -#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ -#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ -#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ -#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ -#define OSCR /* OS timer Counter Reg. */ \ - (*((volatile Word *) io_p2v (_OSCR))) -#define OSSR /* OS timer Status Reg. */ \ - (*((volatile Word *) io_p2v (_OSSR))) -#define OWER /* OS timer Watch-dog Enable Reg. */ \ - (*((volatile Word *) io_p2v (_OWER))) -#define OIER /* OS timer Interrupt Enable Reg. */ \ - (*((volatile Word *) io_p2v (_OIER))) -#endif /* LANGUAGE == C */ - -#define OSSR_M(Nb) /* Match detected [0..3] */ \ - (0x00000001 << (Nb)) -#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ -#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ -#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ -#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ - -#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ - /* (set only) */ - -#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ - (0x00000001 << (Nb)) -#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ -#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ -#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ -#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ - - -/* - * Real-Time Clock (RTC) control registers - * - * Registers - * RTAR Real-Time Clock (RTC) Alarm Register (read/write). - * RCNR Real-Time Clock (RTC) CouNt Register (read/write). - * RTTR Real-Time Clock (RTC) Trim Register (read/write). - * RTSR Real-Time Clock (RTC) Status Register (read/write). - * - * Clocks - * frtx, Trtx Frequency, period of the real-time clock crystal - * (32.768 kHz nominal). - * frtc, Trtc Frequency, period of the real-time clock counter - * (1 Hz nominal). - */ - -#define _RTAR 0x90010000 /* RTC Alarm Reg. */ -#define _RCNR 0x90010004 /* RTC CouNt Reg. */ -#define _RTTR 0x90010008 /* RTC Trim Reg. */ -#define _RTSR 0x90010010 /* RTC Status Reg. */ - -#if LANGUAGE == C -#define RTAR /* RTC Alarm Reg. */ \ - (*((volatile Word *) io_p2v (_RTAR))) -#define RCNR /* RTC CouNt Reg. */ \ - (*((volatile Word *) io_p2v (_RCNR))) -#define RTTR /* RTC Trim Reg. */ \ - (*((volatile Word *) io_p2v (_RTTR))) -#define RTSR /* RTC Status Reg. */ \ - (*((volatile Word *) io_p2v (_RTSR))) -#endif /* LANGUAGE == C */ - -#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ -#define RTTR_D Fld (10, 16) /* trim Delete count */ - /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ - /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ - -#define RTSR_AL 0x00000001 /* ALarm detected */ -#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ -#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ -#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ - - -/* - * Power Manager (PM) control registers - * - * Registers - * PMCR Power Manager (PM) Control Register (read/write). - * PSSR Power Manager (PM) Sleep Status Register (read/write). - * PSPR Power Manager (PM) Scratch-Pad Register (read/write). - * PWER Power Manager (PM) Wake-up Enable Register - * (read/write). - * PCFR Power Manager (PM) general ConFiguration Register - * (read/write). - * PPCR Power Manager (PM) Phase-Locked Loop (PLL) - * Configuration Register (read/write). - * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) - * Sleep state Register (read/write, see GPIO pins). - * POSR Power Manager (PM) Oscillator Status Register (read). - * - * Clocks - * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - */ - -#define _PMCR 0x90020000 /* PM Control Reg. */ -#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ -#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ -#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ -#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ -#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ -#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ -#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ - -#if LANGUAGE == C -#define PMCR /* PM Control Reg. */ \ - (*((volatile Word *) io_p2v (_PMCR))) -#define PSSR /* PM Sleep Status Reg. */ \ - (*((volatile Word *) io_p2v (_PSSR))) -#define PSPR /* PM Scratch-Pad Reg. */ \ - (*((volatile Word *) io_p2v (_PSPR))) -#define PWER /* PM Wake-up Enable Reg. */ \ - (*((volatile Word *) io_p2v (_PWER))) -#define PCFR /* PM general ConFiguration Reg. */ \ - (*((volatile Word *) io_p2v (_PCFR))) -#define PPCR /* PM PLL Configuration Reg. */ \ - (*((volatile Word *) io_p2v (_PPCR))) -#define PGSR /* PM GPIO Sleep state Reg. */ \ - (*((volatile Word *) io_p2v (_PGSR))) -#define POSR /* PM Oscillator Status Reg. */ \ - (*((volatile Word *) io_p2v (_POSR))) - -#elif LANGUAGE == Assembly -#define PMCR (io_p2v (_PMCR)) -#define PSSR (io_p2v (_PSSR)) -#define PSPR (io_p2v (_PSPR)) -#define PWER (io_p2v (_PWER)) -#define PCFR (io_p2v (_PCFR)) -#define PPCR (io_p2v (_PPCR)) -#define PGSR (io_p2v (_PGSR)) -#define POSR (io_p2v (_POSR)) - -#endif /* LANGUAGE == C */ - -#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ - -#define PSSR_SS 0x00000001 /* Software Sleep */ -#define PSSR_BFS 0x00000002 /* Battery Fault Status */ - /* (BATT_FAULT) */ -#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ -#define PSSR_DH 0x00000008 /* DRAM control Hold */ -#define PSSR_PH 0x00000010 /* Peripheral control Hold */ - -#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ -#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ -#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ -#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ -#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ -#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ -#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ -#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ -#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ -#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ -#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ -#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - -#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ -#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ -#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ -#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ -#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ -#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ -#define PCFR_FS 0x00000004 /* Float Static memory pins */ -#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ -#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ -#define PCFR_FO 0x00000008 /* Force RTC oscillator */ - /* (32.768 kHz) enable On */ - -#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ -#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ - (0x00 << FShft (PPCR_CCF)) -#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ - (0x01 << FShft (PPCR_CCF)) -#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ - (0x02 << FShft (PPCR_CCF)) -#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ - (0x03 << FShft (PPCR_CCF)) -#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ - (0x04 << FShft (PPCR_CCF)) -#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ - (0x05 << FShft (PPCR_CCF)) -#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ - (0x06 << FShft (PPCR_CCF)) -#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ - (0x07 << FShft (PPCR_CCF)) -#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ - (0x08 << FShft (PPCR_CCF)) -#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ - (0x09 << FShft (PPCR_CCF)) -#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ - (0x0A << FShft (PPCR_CCF)) -#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ - (0x0B << FShft (PPCR_CCF)) -#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ - (0x0C << FShft (PPCR_CCF)) -#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ - (0x0D << FShft (PPCR_CCF)) -#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ - (0x0E << FShft (PPCR_CCF)) -#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ - (0x0F << FShft (PPCR_CCF)) - /* 3.6864 MHz crystal (fxtl): */ -#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ -#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ -#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ -#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ -#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ -#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ -#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ -#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ -#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ -#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ -#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ -#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ -#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ -#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ -#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ -#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ - /* 3.5795 MHz crystal (fxtl): */ -#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ -#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ -#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ -#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ -#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ -#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ -#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ -#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ -#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ -#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ -#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ -#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ -#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ -#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ -#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ -#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ - -#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ - - -/* - * Reset Controller (RC) control registers - * - * Registers - * RSRR Reset Controller (RC) Software Reset Register - * (read/write). - * RCSR Reset Controller (RC) Status Register (read/write). - */ - -#define _RSRR 0x90030000 /* RC Software Reset Reg. */ -#define _RCSR 0x90030004 /* RC Status Reg. */ - -#if LANGUAGE == C -#define RSRR /* RC Software Reset Reg. */ \ - (*((volatile Word *) io_p2v (_RSRR))) -#define RCSR /* RC Status Reg. */ \ - (*((volatile Word *) io_p2v (_RCSR))) -#endif /* LANGUAGE == C */ - -#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ - -#define RCSR_HWR 0x00000001 /* HardWare Reset */ -#define RCSR_SWR 0x00000002 /* SoftWare Reset */ -#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ -#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ - - -/* - * Test unit control registers - * - * Registers - * TUCR Test Unit Control Register (read/write). - */ - -#define _TUCR 0x90030008 /* Test Unit Control Reg. */ - -#if LANGUAGE == C -#define TUCR /* Test Unit Control Reg. */ \ - (*((volatile Word *) io_p2v (_TUCR))) -#endif /* LANGUAGE == C */ - -#define TUCR_TIC 0x00000040 /* TIC mode */ -#define TUCR_TTST 0x00000080 /* Trim TeST mode */ -#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ - /* Check */ -#define TUCR_PMD 0x00000200 /* Power Management Disable */ -#define TUCR_MR 0x00000400 /* Memory Request mode */ -#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ -#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ - /* grant (MBGNT) on GPIO [22:21] */ -#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ -#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ -#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ -#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ -#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ -#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ -#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ - (0 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ - (1 << FShft (TUCR_TSEL)) -#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ - (2 << FShft (TUCR_TSEL)) -#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ - (3 << FShft (TUCR_TSEL)) -#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ - /* Clocks on GPIO [26:27] */ \ - (4 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ - /* (Alternative) */ \ - (5 << FShft (TUCR_TSEL)) -#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ - (6 << FShft (TUCR_TSEL)) -#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ - (7 << FShft (TUCR_TSEL)) - - -/* - * General-Purpose Input/Output (GPIO) control registers - * - * Registers - * GPLR General-Purpose Input/Output (GPIO) Pin Level - * Register (read). - * GPDR General-Purpose Input/Output (GPIO) Pin Direction - * Register (read/write). - * GPSR General-Purpose Input/Output (GPIO) Pin output Set - * Register (write). - * GPCR General-Purpose Input/Output (GPIO) Pin output Clear - * Register (write). - * GRER General-Purpose Input/Output (GPIO) Rising-Edge - * detect Register (read/write). - * GFER General-Purpose Input/Output (GPIO) Falling-Edge - * detect Register (read/write). - * GEDR General-Purpose Input/Output (GPIO) Edge Detect - * status Register (read/write). - * GAFR General-Purpose Input/Output (GPIO) Alternate - * Function Register (read/write). - * - * Clock - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - */ - -#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ -#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ -#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ -#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ -#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ -#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ -#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ -#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ - -#if LANGUAGE == C -#define GPLR /* GPIO Pin Level Reg. */ \ - (*((volatile Word *) io_p2v (_GPLR))) -#define GPDR /* GPIO Pin Direction Reg. */ \ - (*((volatile Word *) io_p2v (_GPDR))) -#define GPSR /* GPIO Pin output Set Reg. */ \ - (*((volatile Word *) io_p2v (_GPSR))) -#define GPCR /* GPIO Pin output Clear Reg. */ \ - (*((volatile Word *) io_p2v (_GPCR))) -#define GRER /* GPIO Rising-Edge detect Reg. */ \ - (*((volatile Word *) io_p2v (_GRER))) -#define GFER /* GPIO Falling-Edge detect Reg. */ \ - (*((volatile Word *) io_p2v (_GFER))) -#define GEDR /* GPIO Edge Detect status Reg. */ \ - (*((volatile Word *) io_p2v (_GEDR))) -#define GAFR /* GPIO Alternate Function Reg. */ \ - (*((volatile Word *) io_p2v (_GAFR))) -#elif LANGUAGE == Assembly - -#define GPLR (io_p2v (_GPLR)) -#define GPDR (io_p2v (_GPDR)) -#define GPSR (io_p2v (_GPSR)) -#define GPCR (io_p2v (_GPCR)) -#define GRER (io_p2v (_GRER)) -#define GFER (io_p2v (_GFER)) -#define GEDR (io_p2v (_GEDR)) -#define GAFR (io_p2v (_GAFR)) - -#endif /* LANGUAGE == C */ - -#define GPIO_MIN (0) -#define GPIO_MAX (27) - -#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ - (0x00000001 << (Nb)) -#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ -#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ -#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ -#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ -#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ -#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ -#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ -#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ -#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ -#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ -#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ -#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ -#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ -#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ -#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ -#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ -#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ -#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ -#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ -#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ -#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ -#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ -#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ -#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ -#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ -#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ -#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ -#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ - -#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ - GPIO_GPIO ((Nb) - 6) -#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ -#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ -#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ -#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ -#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ -#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ -#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ -#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ - /* ser. port 4: */ -#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ -#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ -#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ -#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ - /* ser. port 1: */ -#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ -#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ -#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ -#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ -#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ - /* ser. port 4: */ -#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ - /* ser. port 3: */ -#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ - /* ser. port 4: */ -#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ - /* test controller: */ -#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ -#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ -#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ -#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ -#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ -#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ -#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ -#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ - -#define GPDR_In 0 /* Input */ -#define GPDR_Out 1 /* Output */ - - -/* - * Interrupt Controller (IC) control registers - * - * Registers - * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) - * Pending register (read). - * ICMR Interrupt Controller (IC) Mask Register (read/write). - * ICLR Interrupt Controller (IC) Level Register (read/write). - * ICCR Interrupt Controller (IC) Control Register - * (read/write). - * [The ICCR register is only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * ICFP Interrupt Controller (IC) Fast Interrupt reQuest - * (FIQ) Pending register (read). - * ICPR Interrupt Controller (IC) Pending Register (read). - * [The ICPR register is active low (inverted) in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it is active high (non-inverted) in - * versions 2.0 (rev. = 8) and higher.] - */ - -#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ -#define _ICMR 0x90050004 /* IC Mask Reg. */ -#define _ICLR 0x90050008 /* IC Level Reg. */ -#define _ICCR 0x9005000C /* IC Control Reg. */ -#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ -#define _ICPR 0x90050020 /* IC Pending Reg. */ - -#if LANGUAGE == C -#define ICIP /* IC IRQ Pending reg. */ \ - (*((volatile Word *) io_p2v (_ICIP))) -#define ICMR /* IC Mask Reg. */ \ - (*((volatile Word *) io_p2v (_ICMR))) -#define ICLR /* IC Level Reg. */ \ - (*((volatile Word *) io_p2v (_ICLR))) -#define ICCR /* IC Control Reg. */ \ - (*((volatile Word *) io_p2v (_ICCR))) -#define ICFP /* IC FIQ Pending reg. */ \ - (*((volatile Word *) io_p2v (_ICFP))) -#define ICPR /* IC Pending Reg. */ \ - (*((volatile Word *) io_p2v (_ICPR))) -#endif /* LANGUAGE == C */ - -#define IC_GPIO(Nb) /* GPIO [0..10] */ \ - (0x00000001 << (Nb)) -#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ -#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ -#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ -#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ -#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ -#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ -#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ -#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ -#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ -#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ -#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ -#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ -#define IC_LCD 0x00001000 /* LCD controller */ -#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ -#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ -#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ -#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ -#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ -#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ -#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ -#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ - (0x00100000 << (Nb)) -#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ -#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ -#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ -#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ -#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ -#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ -#define IC_OST(Nb) /* OS Timer match [0..3] */ \ - (0x04000000 << (Nb)) -#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ -#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ -#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ -#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ -#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ -#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ - -#define ICLR_IRQ 0 /* Interrupt ReQuest */ -#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ - -#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ - /* Mask */ -#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ - /* (ICMR ignored) */ -#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ - /* enable (ICMR used) */ - - -/* - * Peripheral Pin Controller (PPC) control registers - * - * Registers - * PPDR Peripheral Pin Controller (PPC) Pin Direction - * Register (read/write). - * PPSR Peripheral Pin Controller (PPC) Pin State Register - * (read/write). - * PPAR Peripheral Pin Controller (PPC) Pin Assignment - * Register (read/write). - * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin - * Direction Register (read/write). - * PPFR Peripheral Pin Controller (PPC) Pin Flag Register - * (read). - */ - -#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ -#define _PPSR 0x90060004 /* PPC Pin State Reg. */ -#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ -#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ - /* Reg. */ -#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ - -#if LANGUAGE == C -#define PPDR /* PPC Pin Direction Reg. */ \ - (*((volatile Word *) io_p2v (_PPDR))) -#define PPSR /* PPC Pin State Reg. */ \ - (*((volatile Word *) io_p2v (_PPSR))) -#define PPAR /* PPC Pin Assignment Reg. */ \ - (*((volatile Word *) io_p2v (_PPAR))) -#define PSDR /* PPC Sleep-mode pin Direction */ \ - /* Reg. */ \ - (*((volatile Word *) io_p2v (_PSDR))) -#define PPFR /* PPC Pin Flag Reg. */ \ - (*((volatile Word *) io_p2v (_PPFR))) -#endif /* LANGUAGE == C */ - -#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ - (0x00000001 << (Nb)) -#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ -#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ -#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ -#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ -#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ -#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ -#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ -#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ -#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ -#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ -#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ -#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ - /* ser. port 1: */ -#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ -#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ - /* ser. port 2: */ -#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ -#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ - /* ser. port 3: */ -#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ -#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ - /* ser. port 4: */ -#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ -#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ -#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ -#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ - -#define PPDR_In 0 /* Input */ -#define PPDR_Out 1 /* Output */ - - /* ser. port 1: */ -#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ -#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ -#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ - /* ser. port 4: */ -#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ -#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ - /* & SFRM_C */ -#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ - -#define PSDR_OutL 0 /* Output Low in sleep mode */ -#define PSDR_Flt 1 /* Floating (input) in sleep mode */ - -#define PPFR_LCD 0x00000001 /* LCD controller */ -#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ -#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ -#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ -#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ -#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ -#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ -#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ -#define PPFR_PerEn 0 /* Peripheral Enabled */ -#define PPFR_PPCEn 1 /* PPC Enabled */ - - -/* - * Dynamic Random-Access Memory (DRAM) control registers - * - * Registers - * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) - * CoNFiGuration register (read/write). - * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 0 - * (read/write). - * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 1 - * (read/write). - * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 2 - * (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fcas, Tcas Frequency, period of the DRAM CAS shift registers. - */ - - /* Memory system: */ -#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ -#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ - (0xA0000004 + (Nb)*4) -#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ -#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ -#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ - -#if LANGUAGE == C - /* Memory system: */ -#define MDCNFG /* DRAM CoNFiGuration reg. */ \ - (*((volatile Word *) io_p2v (_MDCNFG))) -#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ - ((volatile Word *) io_p2v (_MDCAS (0))) -#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ -#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ -#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ - -#elif LANGUAGE == Assembly - -#define MDCNFG (io_p2v(_MDCNFG)) - -#endif /* LANGUAGE == C */ - -/* SA1100 MDCNFG values */ -#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ - (0x00000001 << (Nb)) -#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ -#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ -#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ -#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ -#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ -#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ - (((Add) - 9) << FShft (MDCNFG_DRAC)) -#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ - /* (fcas = fcpu/2) */ -#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ -#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ -#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ -#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ - ((Tcpu) << FShft (MDCNFG_TDL)) -#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ - /* [Tmem] */ -#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ - /* [0..262136 Tcpu] */ \ - ((Tcpu)/8 << FShft (MDCNFG_DRI)) - -/* SA1110 MDCNFG values */ -#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ -#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ -#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ - /* bank 0/1 */ -#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ -#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ - /* deassertion 0/1 */ -#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ -#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ -#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ -#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ - /* bank 0/1 */ -#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ -#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ - /* deassertion 0/1 */ -#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ - - -/* - * Static memory control registers - * - * Registers - * MSC0 Memory system: Static memory Control register 0 - * (read/write). - * MSC1 Memory system: Static memory Control register 1 - * (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - */ - - /* Memory system: */ -#define _MSC(Nb) /* Static memory Control reg. */ \ - /* [0..1] */ \ - (0xA0000010 + (Nb)*4) -#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ -#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ -#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ - -#if LANGUAGE == C - /* Memory system: */ -#define MSC /* Static memory Control reg. */ \ - /* [0..1] */ \ - ((volatile Word *) io_p2v (_MSC (0))) -#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ -#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ -#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ - -#elif LANGUAGE == Assembly - -#define MSC0 io_p2v(0xa0000010) -#define MSC1 io_p2v(0xa0000014) -#define MSC2 io_p2v(0xa000002c) - -#endif /* LANGUAGE == C */ - -#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ - Fld (16, ((Nb) Modulo 2)*16) -#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ -#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ -#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ -#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ - -#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ -#define MSC_NonBrst /* Non-Burst static memory */ \ - (0 << FShft (MSC_RT)) -#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ - (1 << FShft (MSC_RT)) -#define MSC_Brst4 /* Burst-of-4 static memory */ \ - (2 << FShft (MSC_RT)) -#define MSC_Brst8 /* Burst-of-8 static memory */ \ - (3 << FShft (MSC_RT)) -#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ -#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ -#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ -#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ - /* First access - 1(.5) [Tmem] */ -#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ - /* static memory) [3..65 Tcpu] */ \ - ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) -#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) -#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ - /* Next access - 1 [Tmem] */ -#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ - /* time/2 [Tmem] */ -#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ - (((Tcpu)/4) << FShft (MSC_RRR)) -#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ - ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) - - -/* - * Personal Computer Memory Card International Association (PCMCIA) control - * register - * - * Register - * MECR Memory system: Expansion memory bus (PCMCIA) - * Configuration Register (read/write). - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). - */ - - /* Memory system: */ -#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ - /* Configuration Reg. */ - -#if LANGUAGE == C - /* Memory system: */ -#define MECR /* Expansion memory bus (PCMCIA) */ \ - /* Configuration Reg. */ \ - (*((volatile Word *) io_p2v (_MECR))) -#endif /* LANGUAGE == C */ - -#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ - Fld (15, (Nb)*16) -#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ -#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ - -#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ -#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) -#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) -#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ - /* [Tmem] */ -#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) -#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) -#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ -#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) -#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) - -/* - * On SA1110 only - */ - -#define _MDREFR 0xA000001C - -#if LANGUAGE == C - /* Memory system: */ -#define MDREFR \ - (*((volatile Word *) io_p2v (_MDREFR))) - -#elif LANGUAGE == Assembly - -#define MDREFR (io_p2v(_MDREFR)) - -#endif /* LANGUAGE == C */ - -#define MDREFR_TRASR Fld (4, 0) -#define MDREFR_DRI Fld (12, 4) -#define MDREFR_E0PIN (1 << 16) -#define MDREFR_K0RUN (1 << 17) -#define MDREFR_K0DB2 (1 << 18) -#define MDREFR_E1PIN (1 << 20) -#define MDREFR_K1RUN (1 << 21) -#define MDREFR_K1DB2 (1 << 22) -#define MDREFR_K2RUN (1 << 25) -#define MDREFR_K2DB2 (1 << 26) -#define MDREFR_EAPD (1 << 28) -#define MDREFR_KAPD (1 << 29) -#define MDREFR_SLFRSH (1 << 31) - - -/* - * Direct Memory Access (DMA) control registers - * - * Registers - * DDAR0 Direct Memory Access (DMA) Device Address Register - * channel 0 (read/write). - * DCSR0 Direct Memory Access (DMA) Control and Status - * Register channel 0 (read/write). - * DBSA0 Direct Memory Access (DMA) Buffer Start address - * register A channel 0 (read/write). - * DBTA0 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 0 (read/write). - * DBSB0 Direct Memory Access (DMA) Buffer Start address - * register B channel 0 (read/write). - * DBTB0 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 0 (read/write). - * - * DDAR1 Direct Memory Access (DMA) Device Address Register - * channel 1 (read/write). - * DCSR1 Direct Memory Access (DMA) Control and Status - * Register channel 1 (read/write). - * DBSA1 Direct Memory Access (DMA) Buffer Start address - * register A channel 1 (read/write). - * DBTA1 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 1 (read/write). - * DBSB1 Direct Memory Access (DMA) Buffer Start address - * register B channel 1 (read/write). - * DBTB1 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 1 (read/write). - * - * DDAR2 Direct Memory Access (DMA) Device Address Register - * channel 2 (read/write). - * DCSR2 Direct Memory Access (DMA) Control and Status - * Register channel 2 (read/write). - * DBSA2 Direct Memory Access (DMA) Buffer Start address - * register A channel 2 (read/write). - * DBTA2 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 2 (read/write). - * DBSB2 Direct Memory Access (DMA) Buffer Start address - * register B channel 2 (read/write). - * DBTB2 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 2 (read/write). - * - * DDAR3 Direct Memory Access (DMA) Device Address Register - * channel 3 (read/write). - * DCSR3 Direct Memory Access (DMA) Control and Status - * Register channel 3 (read/write). - * DBSA3 Direct Memory Access (DMA) Buffer Start address - * register A channel 3 (read/write). - * DBTA3 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 3 (read/write). - * DBSB3 Direct Memory Access (DMA) Buffer Start address - * register B channel 3 (read/write). - * DBTB3 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 3 (read/write). - * - * DDAR4 Direct Memory Access (DMA) Device Address Register - * channel 4 (read/write). - * DCSR4 Direct Memory Access (DMA) Control and Status - * Register channel 4 (read/write). - * DBSA4 Direct Memory Access (DMA) Buffer Start address - * register A channel 4 (read/write). - * DBTA4 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 4 (read/write). - * DBSB4 Direct Memory Access (DMA) Buffer Start address - * register B channel 4 (read/write). - * DBTB4 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 4 (read/write). - * - * DDAR5 Direct Memory Access (DMA) Device Address Register - * channel 5 (read/write). - * DCSR5 Direct Memory Access (DMA) Control and Status - * Register channel 5 (read/write). - * DBSA5 Direct Memory Access (DMA) Buffer Start address - * register A channel 5 (read/write). - * DBTA5 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 5 (read/write). - * DBSB5 Direct Memory Access (DMA) Buffer Start address - * register B channel 5 (read/write). - * DBTB5 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 5 (read/write). - */ - -#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ - -#define _DDAR(Nb) /* DMA Device Address Reg. */ \ - /* channel [0..5] */ \ - (0xB0000000 + (Nb)*DMASp) -#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ - (0xB0000004 + (Nb)*DMASp) -#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ - (0xB0000008 + (Nb)*DMASp) -#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ - /* channel [0..5] (read) */ \ - (0xB000000C + (Nb)*DMASp) -#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ - /* channel [0..5] */ \ - (0xB0000010 + (Nb)*DMASp) -#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ - /* reg. A channel [0..5] */ \ - (0xB0000014 + (Nb)*DMASp) -#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ - /* channel [0..5] */ \ - (0xB0000018 + (Nb)*DMASp) -#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ - /* reg. B channel [0..5] */ \ - (0xB000001C + (Nb)*DMASp) - -#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ - /* channel 0 */ -#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ - /* channel 0 (write) */ -#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ - /* channel 0 (write) */ -#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ - /* channel 0 (read) */ -#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ - /* channel 0 */ -#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ - /* reg. A channel 0 */ -#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ - /* channel 0 */ -#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ - /* reg. B channel 0 */ - -#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ - /* channel 1 */ -#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ - /* channel 1 (write) */ -#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ - /* channel 1 (write) */ -#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ - /* channel 1 (read) */ -#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ - /* channel 1 */ -#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ - /* reg. A channel 1 */ -#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ - /* channel 1 */ -#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ - /* reg. B channel 1 */ - -#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ - /* channel 2 */ -#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ - /* channel 2 (write) */ -#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ - /* channel 2 (write) */ -#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ - /* channel 2 (read) */ -#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ - /* channel 2 */ -#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ - /* reg. A channel 2 */ -#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ - /* channel 2 */ -#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ - /* reg. B channel 2 */ - -#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ - /* channel 3 */ -#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ - /* channel 3 (write) */ -#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ - /* channel 3 (write) */ -#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ - /* channel 3 (read) */ -#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ - /* channel 3 */ -#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ - /* reg. A channel 3 */ -#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ - /* channel 3 */ -#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ - /* reg. B channel 3 */ - -#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ - /* channel 4 */ -#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ - /* channel 4 (write) */ -#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ - /* channel 4 (write) */ -#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ - /* channel 4 (read) */ -#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ - /* channel 4 */ -#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ - /* reg. A channel 4 */ -#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ - /* channel 4 */ -#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ - /* reg. B channel 4 */ - -#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ - /* channel 5 */ -#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ - /* channel 5 (write) */ -#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ - /* channel 5 (write) */ -#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ - /* channel 5 (read) */ -#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ - /* channel 5 */ -#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ - /* reg. A channel 5 */ -#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ - /* channel 5 */ -#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ - /* reg. B channel 5 */ - -#if LANGUAGE == C - -#define DDAR0 /* DMA Device Address Reg. */ \ - /* channel 0 */ \ - (*((volatile Word *) io_p2v (_DDAR0))) -#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR0))) -#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR0))) -#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ - /* channel 0 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR0))) -#define DBSA0 /* DMA Buffer Start address reg. A */ \ - /* channel 0 */ \ - (*((volatile Address *) io_p2v (_DBSA0))) -#define DBTA0 /* DMA Buffer Transfer count */ \ - /* reg. A channel 0 */ \ - (*((volatile Word *) io_p2v (_DBTA0))) -#define DBSB0 /* DMA Buffer Start address reg. B */ \ - /* channel 0 */ \ - (*((volatile Address *) io_p2v (_DBSB0))) -#define DBTB0 /* DMA Buffer Transfer count */ \ - /* reg. B channel 0 */ \ - (*((volatile Word *) io_p2v (_DBTB0))) - -#define DDAR1 /* DMA Device Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Word *) io_p2v (_DDAR1))) -#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR1))) -#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR1))) -#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ - /* channel 1 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR1))) -#define DBSA1 /* DMA Buffer Start address reg. A */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBSA1))) -#define DBTA1 /* DMA Buffer Transfer count */ \ - /* reg. A channel 1 */ \ - (*((volatile Word *) io_p2v (_DBTA1))) -#define DBSB1 /* DMA Buffer Start address reg. B */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBSB1))) -#define DBTB1 /* DMA Buffer Transfer count */ \ - /* reg. B channel 1 */ \ - (*((volatile Word *) io_p2v (_DBTB1))) - -#define DDAR2 /* DMA Device Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Word *) io_p2v (_DDAR2))) -#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR2))) -#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR2))) -#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ - /* channel 2 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR2))) -#define DBSA2 /* DMA Buffer Start address reg. A */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBSA2))) -#define DBTA2 /* DMA Buffer Transfer count */ \ - /* reg. A channel 2 */ \ - (*((volatile Word *) io_p2v (_DBTA2))) -#define DBSB2 /* DMA Buffer Start address reg. B */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBSB2))) -#define DBTB2 /* DMA Buffer Transfer count */ \ - /* reg. B channel 2 */ \ - (*((volatile Word *) io_p2v (_DBTB2))) - -#define DDAR3 /* DMA Device Address Reg. */ \ - /* channel 3 */ \ - (*((volatile Word *) io_p2v (_DDAR3))) -#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR3))) -#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR3))) -#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ - /* channel 3 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR3))) -#define DBSA3 /* DMA Buffer Start address reg. A */ \ - /* channel 3 */ \ - (*((volatile Address *) io_p2v (_DBSA3))) -#define DBTA3 /* DMA Buffer Transfer count */ \ - /* reg. A channel 3 */ \ - (*((volatile Word *) io_p2v (_DBTA3))) -#define DBSB3 /* DMA Buffer Start address reg. B */ \ - /* channel 3 */ \ - (*((volatile Address *) io_p2v (_DBSB3))) -#define DBTB3 /* DMA Buffer Transfer count */ \ - /* reg. B channel 3 */ \ - (*((volatile Word *) io_p2v (_DBTB3))) - -#define DDAR4 /* DMA Device Address Reg. */ \ - /* channel 4 */ \ - (*((volatile Word *) io_p2v (_DDAR4))) -#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR4))) -#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR4))) -#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ - /* channel 4 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR4))) -#define DBSA4 /* DMA Buffer Start address reg. A */ \ - /* channel 4 */ \ - (*((volatile Address *) io_p2v (_DBSA4))) -#define DBTA4 /* DMA Buffer Transfer count */ \ - /* reg. A channel 4 */ \ - (*((volatile Word *) io_p2v (_DBTA4))) -#define DBSB4 /* DMA Buffer Start address reg. B */ \ - /* channel 4 */ \ - (*((volatile Address *) io_p2v (_DBSB4))) -#define DBTB4 /* DMA Buffer Transfer count */ \ - /* reg. B channel 4 */ \ - (*((volatile Word *) io_p2v (_DBTB4))) - -#define DDAR5 /* DMA Device Address Reg. */ \ - /* channel 5 */ \ - (*((volatile Word *) io_p2v (_DDAR5))) -#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR5))) -#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR5))) -#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ - /* channel 5 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR5))) -#define DBSA5 /* DMA Buffer Start address reg. A */ \ - /* channel 5 */ \ - (*((volatile Address *) io_p2v (_DBSA5))) -#define DBTA5 /* DMA Buffer Transfer count */ \ - /* reg. A channel 5 */ \ - (*((volatile Word *) io_p2v (_DBTA5))) -#define DBSB5 /* DMA Buffer Start address reg. B */ \ - /* channel 5 */ \ - (*((volatile Address *) io_p2v (_DBSB5))) -#define DBTB5 /* DMA Buffer Transfer count */ \ - /* reg. B channel 5 */ \ - (*((volatile Word *) io_p2v (_DBTB5))) - -#endif /* LANGUAGE == C */ - -#define DDAR_RW 0x00000001 /* device data Read/Write */ -#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ -#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ -#define DDAR_E 0x00000002 /* big/little Endian device */ -#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ -#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ -#define DDAR_BS 0x00000004 /* device Burst Size */ -#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ -#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ -#define DDAR_DW 0x00000008 /* device Data Width */ -#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ -#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ -#define DDAR_DS Fld (4, 4) /* Device Select */ -#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ - (0x0 << FShft (DDAR_DS)) -#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ - (0x1 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ - (0x2 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ - (0x3 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ - (0x4 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ - (0x5 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ - (0x6 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ - (0x7 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ - (0x8 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ - (0x9 << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ - (0xA << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ - (0xB << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ - (0xC << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ - (0xD << FShft (DDAR_DS)) -#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ - (0xE << FShft (DDAR_DS)) -#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ - (0xF << FShft (DDAR_DS)) -#define DDAR_DA Fld (24, 8) /* Device Address */ -#define DDAR_DevAdd(Add) /* Device Address */ \ - (((Add) & 0xF0000000) | \ - (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) -#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) -#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) - -#define DCSR_RUN 0x00000001 /* DMA RUNing */ -#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ -#define DCSR_ERROR 0x00000004 /* DMA ERROR */ -#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ -#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ -#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ -#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ -#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ -#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ -#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ - -#define DBT_TC Fld (13, 0) /* Transfer Count */ -#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ -#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ - - -/* - * Liquid Crystal Display (LCD) control registers - * - * Registers - * LCCR0 Liquid Crystal Display (LCD) Control Register 0 - * (read/write). - * [Bits LDM, BAM, and ERM are only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * LCSR Liquid Crystal Display (LCD) Status Register - * (read/write). - * [Bit LDD can be only read in versions 1.0 (rev. = 1) - * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be - * read and written (cleared) in versions 2.0 (rev. = 8) - * and higher.] - * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 1 (read/write). - * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 1 (read). - * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 2 (read/write). - * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 2 (read). - * LCCR1 Liquid Crystal Display (LCD) Control Register 1 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR2 Liquid Crystal Display (LCD) Control Register 2 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR3 Liquid Crystal Display (LCD) Control Register 3 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher. Bit PCP is only - * implemented in versions 2.0 (rev. = 8) and higher of - * the StrongARM SA-1100.] - * - * Clocks - * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). - * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). - * fpix, Tpix Frequency, period of the pixel clock. - * fln, Tln Frequency, period of the line clock. - * fac, Tac Frequency, period of the AC bias clock. - */ - -#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ -#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ - /* [byte] */ \ - (16*LCD_PEntrySp) -#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ - /* [byte] */ \ - (256*LCD_PEntrySp) -#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ - /* dummy-Palette Space [byte] */ \ - (16*LCD_PEntrySp) - -#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ -#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ -#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ -#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ -#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ -#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ - (0 << FShft (LCD_PBS)) -#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ - (1 << FShft (LCD_PBS)) -#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ - (2 << FShft (LCD_PBS)) - -#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ -#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ -#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ -#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ -#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ -#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ -#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ -#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ -#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ -#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ -#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ -#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ -#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ -#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ -#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ -#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ - /* (Alternative) */ - -#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ -#define _LCSR 0xB0100004 /* LCD Status Reg. */ -#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ - /* channel 1 */ -#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ - /* channel 1 */ -#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ - /* channel 2 */ -#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ - /* channel 2 */ -#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ -#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ -#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ - -#if LANGUAGE == C -#define LCCR0 /* LCD Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_LCCR0))) -#define LCSR /* LCD Status Reg. */ \ - (*((volatile Word *) io_p2v (_LCSR))) -#define DBAR1 /* LCD DMA Base Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBAR1))) -#define DCAR1 /* LCD DMA Current Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DCAR1))) -#define DBAR2 /* LCD DMA Base Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBAR2))) -#define DCAR2 /* LCD DMA Current Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DCAR2))) -#define LCCR1 /* LCD Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_LCCR1))) -#define LCCR2 /* LCD Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_LCCR2))) -#define LCCR3 /* LCD Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_LCCR3))) -#endif /* LANGUAGE == C */ - -#define LCCR0_LEN 0x00000001 /* LCD ENable */ -#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ - /* Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ -#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ - /* interrupt Mask (disable) */ -#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ - /* interrupt Mask (disable) */ -#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ - /* IUU, OOL, OUL, OOU, and OUU) */ - /* interrupt Mask (disable) */ -#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ -#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ -#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ -#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ - /* display mode) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ - /* [Tmem] */ -#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ - /* [0..510 Tcpu] */ \ - ((Tcpu)/2 << FShft (LCCR0_PDD)) - -#define LCSR_LDD 0x00000001 /* LCD Disable Done */ -#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ -#define LCSR_BER 0x00000004 /* Bus ERror */ -#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ -#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ - /* panel */ -#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ - /* panel */ -#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ - /* panel */ -#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ - /* panel */ -#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ - /* panel */ -#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ - /* panel */ -#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ - /* panel */ -#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ - /* panel */ - -#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ - (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ - /* pulse Width - 2 [Tpix] (L_LCLK) */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [2..65 Tpix] */ \ - (((Tpix) - 2) << FShft (LCCR1_HSW)) -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ - /* [1..255] (L_PCLK) */ - /* fpix = fcpu/(2*(PCD + 2)) */ - /* Tpix = 2*(PCD + 2)*Tcpu */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ - (((Div) - 4)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Floor (Div/2)) */ - /* Tpix = 2*Floor (Div/2)*Tcpu */ -#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ - (((Div) - 3)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Ceil (Div/2)) */ - /* Tpix = 2*Ceil (Div/2)*Tcpu */ -#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ - /* [Tln] (L_BIAS) */ -#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Floor (Div/2)) */ - /* Tac = 2*Floor (Div/2)*Tln */ -#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Ceil (Div/2)) */ - /* Tac = 2*Ceil (Div/2)*Tln */ -#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ - /* Interrupt */ -#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ - /* Off */ \ - (0 << FShft (LCCR3_API)) -#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ - /* [1..15] */ \ - ((Trans) << FShft (LCCR3_API)) -#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ - /* Polarity (L_FCLK) */ -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ -#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ - /* pulse Polarity (L_LCLK) */ -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - /* pulse active Low */ -#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ -#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ - /* active display mode) */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ - - -#undef C -#undef Assembly diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 1becc669aee90ff5f1ac78ed057efde880ae69a6..70303acd5581cc1998273c7e59f731db08759c8f 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -48,7 +48,6 @@ struct bd_info { #endif unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ diff --git a/include/binman_sym.h b/include/binman_sym.h index 72e6765fe52004504c7de1738d04aa1d2c1250c9..528d7e4e90ed321f3baf0f637621fa960b568532 100644 --- a/include/binman_sym.h +++ b/include/binman_sym.h @@ -11,9 +11,11 @@ #ifndef __BINMAN_SYM_H #define __BINMAN_SYM_H +/* BSYM in little endian, keep in sync with tools/binman/elf.py */ +#define BINMAN_SYM_MAGIC_VALUE (0x4d595342UL) #define BINMAN_SYM_MISSING (-1UL) -#ifdef CONFIG_BINMAN +#if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) /** * binman_symname() - Internal function to get a binman symbol name @@ -62,6 +64,37 @@ __attribute__((aligned(4), weak, unused, \ section(".binman_sym"))) +/** + * _binman_sym_magic - Internal magic symbol for validity checks + * + * When building images, binman fills in this symbol with the magic + * value #defined above. This is used to check at runtime if the + * symbol values were filled in and are OK to use. + */ +extern ulong _binman_sym_magic; + +/** + * DECLARE_BINMAN_MAGIC_SYM - Declare the internal magic symbol + * + * This macro declares the _binman_sym_magic symbol so that it exists. + * Declaring it here would cause errors during linking due to multiple + * definitions of the symbol. + */ +#define DECLARE_BINMAN_MAGIC_SYM \ + ulong _binman_sym_magic \ + __attribute__((aligned(4), section(".binman_sym"))) + +/** + * BINMAN_SYMS_OK - Check if the symbol values are valid + * + * This macro checks if the magic symbol's value is filled properly, + * which indicates that other symbols are OK to use as well. + * + * Return: 1 if binman symbol values are usable, 0 if not + */ +#define BINMAN_SYMS_OK \ + (*(ulong *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE) + /** * binman_sym() - Access a previously declared symbol * @@ -72,12 +105,16 @@ * @_type: Type f the symbol (e.g. unsigned long) * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') * @_prop_name: Property value to get from that entry (e.g. 'pos') - * @returns value of that property (filled in by binman) + * + * Return: value of that property (filled in by binman), or + * BINMAN_SYM_MISSING if the value is unavailable */ #define binman_sym(_type, _entry_name, _prop_name) \ - (*(_type *)&binman_symname(_entry_name, _prop_name)) + (BINMAN_SYMS_OK ? \ + (*(_type *)&binman_symname(_entry_name, _prop_name)) : \ + BINMAN_SYM_MISSING) -#else /* !BINMAN */ +#else /* !CONFIG_IS_ENABLED(BINMAN_SYMBOLS) */ #define binman_sym_declare(_type, _entry_name, _prop_name) @@ -85,8 +122,12 @@ #define binman_sym_extern(_type, _entry_name, _prop_name) +#define DECLARE_BINMAN_MAGIC_SYM + +#define BINMAN_SYMS_OK (0) + #define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING -#endif /* BINMAN */ +#endif /* CONFIG_IS_ENABLED(BINMAN_SYMBOLS) */ #endif diff --git a/include/bloblist.h b/include/bloblist.h index d0e128acf1031cb61488dabb8d190834b24dc4fc..9684bfd5f4bb039375a0a0b5290cf93466a6a63e 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -3,8 +3,66 @@ * This provides a standard way of passing information between boot phases * (TPL -> SPL -> U-Boot proper.) * - * A list of blobs of data, tagged with their owner. The list resides in memory - * and can be updated by SPL, U-Boot, etc. + * It consists of a list of blobs of data, tagged with their owner / contents. + * The list resides in memory and can be updated by SPL, U-Boot, etc. + * + * Design goals for bloblist: + * + * 1. Small and efficient structure. This avoids UUIDs or 16-byte name fields, + * since a 32-bit tag provides enough space for all the tags we will even need. + * If UUIDs are desired, they can be added inside a particular blob. + * + * 2. Avoids use of pointers, so the structure can be relocated in memory. The + * data in each blob is inline, rather than using pointers. + * + * 3. Bloblist is designed to start small in TPL or SPL, when only a few things + * are needed, like the memory size or whether console output should be enabled. + * Then it can grow in U-Boot proper, e.g. to include space for ACPI tables. + * + * 4. The bloblist structure is simple enough that it can be implemented in a + * small amount of C code. The API does not require use of strings or UUIDs, + * which would add to code size. For Thumb-2 the code size needed in SPL is + * approximately 940 bytes (e.g. for chromebook_bob). + * + * 5. Bloblist uses 16-byte alignment internally and is designed to start on a + * 16-byte boundary. Its headers are multiples of 16 bytes. This makes it easier + * to deal with data structures which need this level of alignment, such as ACPI + * tables. For use in SPL and TPL the alignment can be relaxed, since it can be + * relocated to an aligned address in U-Boot proper. + * + * 6. Bloblist is designed to be passed to Linux as reserved memory. While linux + * doesn't understand the bloblist header, it can be passed the indivdual blobs. + * For example, ACPI tables can reside in a blob and the address of those is + * passed to Linux, without Linux ever being away of the existence of a + * bloblist. Having all the blobs contiguous in memory simplifies the + * reserved-memory space. + * + * 7. Bloblist tags are defined in the enum below. There is an area for + * project-specific stuff (e.g. U-Boot, TF-A) and vendor-specific stuff, e.g. + * something used only on a particular SoC. There is also a private area for + * temporary, local use. + * + * 8. Bloblist includes a simple checksum, so that each boot phase can update + * this and allow the next phase to check that all is well. While the bloblist + * is small, this is quite cheap to calculate. When it grows (e.g. in U-Boot\ + * proper), the CPU is likely running faster, so it is not prohibitive. Having + * said that, U-Boot is often the last phase that uses bloblist, so calculating + * the checksum there may not be necessary. + * + * 9. It would be possible to extend bloblist to support a non-contiguous + * structure, e.g. by creating a blob type that points to the next bloblist. + * This does not seem necessary for now. It adds complexity and code. We can + * always just copy it. + * + * 10. Bloblist is designed for simple structures, those that can be defined by + * a single C struct. More complex structures should be passed in a device tree. + * There are some exceptions, chiefly the various binary structures that Intel + * is fond of creating. But device tree provides a dictionary-type format which + * is fairly efficient (for use in U-Boot proper and Linux at least), along with + * a schema and a good set of tools. New formats should be designed around + * device tree rather than creating new binary formats, unless they are needed + * early in boot (where libfdt's 3KB of overhead is too large) and are trival + * enough to be described by a C struct. * * Copyright 2018 Google, Inc * Written by Simon Glass diff --git a/include/bootcount.h b/include/bootcount.h index fccee7e15bf73c2ec9605fbfa2eee3a1a26702c2..bfa5d4642764777dbfd37a51899b4df6ec5efecd 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -72,14 +72,6 @@ ulong bootcount_load(void); #if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_TPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT) -#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE) -# if __BYTE_ORDER == __LITTLE_ENDIAN -# define CONFIG_SYS_BOOTCOUNT_LE -# else -# define CONFIG_SYS_BOOTCOUNT_BE -# endif -#endif - #ifdef CONFIG_SYS_BOOTCOUNT_LE static inline void raw_bootcount_store(volatile u32 *addr, u32 data) { diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index c55023889cabc39e0d3a9336a5a60948c990a929..c6e9c497413de9e3bd28a6eb3d1053bce810b23d 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -70,18 +70,23 @@ #ifdef CONFIG_CMD_UBIFS #define BOOTENV_SHARED_UBIFS \ "ubifs_boot=" \ - "env exists bootubipart || " \ - "env set bootubipart UBI; " \ - "env exists bootubivol || " \ - "env set bootubivol boot; " \ "if ubi part ${bootubipart} && " \ - "ubifsmount ubi${devnum}:${bootubivol}; " \ + "ubifsmount ubi0:${bootubivol}; " \ "then " \ "devtype=ubi; " \ + "devnum=ubi0; " \ + "bootfstype=ubifs; " \ + "distro_bootpart=${bootubivol}; " \ "run scan_dev_for_boot; " \ + "ubifsumount; " \ "fi\0" -#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV -#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV +#define BOOTENV_DEV_UBIFS(devtypeu, devtypel, instance, bootubipart, bootubivol) \ + "bootcmd_ubifs" #instance "=" \ + "bootubipart=" #bootubipart "; " \ + "bootubivol=" #bootubivol "; " \ + "run ubifs_boot\0" +#define BOOTENV_DEV_NAME_UBIFS(devtypeu, devtypel, instance, bootubipart, bootubivol) \ + #devtypel #instance " " #else #define BOOTENV_SHARED_UBIFS #define BOOTENV_DEV_UBIFS \ @@ -411,13 +416,13 @@ BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE #endif -#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \ - BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance, ...) \ + BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__) #define BOOTENV_BOOT_TARGETS \ "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" -#define BOOTENV_DEV(devtypeu, devtypel, instance) \ - BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_DEV(devtypeu, devtypel, instance, ...) \ + BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__) #define BOOTENV \ BOOTENV_SHARED_HOST \ BOOTENV_SHARED_MMC \ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 167d44e400f305127bf5f24214942a1a3eb05d13..17c76bcf3dbc53cdf3d82a46dca98a3859946728 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -9,41 +9,16 @@ #ifndef __CONFIG_FALLBACKS_H #define __CONFIG_FALLBACKS_H -#ifdef CONFIG_SPL #ifdef CONFIG_SPL_PAD_TO #ifdef CONFIG_SPL_MAX_SIZE #if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE #error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE #endif #endif -#else -#ifdef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE -#else -#define CONFIG_SPL_PAD_TO 0 -#endif -#endif #endif #ifndef CONFIG_SYS_BAUDRATE_TABLE #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif -/* Console I/O Buffer Size */ -#ifndef CONFIG_SYS_CBSIZE -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#endif - -#ifndef CONFIG_SYS_PBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#endif - -#ifndef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 16 -#endif - #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 3922241be005c234230d850c4c0f6ce5d52e3dd2..380c906ba834055ee8a51cca1a9804fb57905cd1 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -10,10 +10,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - /* * Control should not reach back to uboot after validation of images * for secure boot flow and therefore bootscript should have @@ -21,43 +17,22 @@ * after validating images, core should just spin. */ -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - #ifdef CONFIG_USE_BOOTARGS -#define CONFIG_SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" +#define SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" #else -#define CONFIG_SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ +#define SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ "rw console=ttyS0,115200 ramdisk_size=600000\';" #endif - -#ifdef CONFIG_BOOTSCRIPT_KEY_HASH -#define CONFIG_SECBOOT \ +#define SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr " \ - __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ - "source $img_addr;" \ - "esbc_halt\0" -#else -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ + SET_BOOTARGS \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt\0" -#endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_COPY_ENV \ +#define BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ @@ -68,33 +43,28 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \ defined(CONFIG_SD_BOOT) -#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_COPY_CMD \ +#if defined(CONFIG_NAND_BOOT) +#define BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "nand read $bs_ram $bs_device $bs_size ;" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "mmc read $bs_ram $bs_device $bs_size ;" #endif #else -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ "cp.b $bs_device $bs_ram $bs_size ;" #endif +#else /* !CONFIG_BOOTSCRIPT_COPY_RAM */ +#define BS_COPY_ENV +#define BS_COPY_CMD #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ -#ifndef CONFIG_BS_COPY_ENV -#define CONFIG_BS_COPY_ENV -#endif - -#ifndef CONFIG_BS_COPY_CMD -#define CONFIG_BS_COPY_CMD -#endif - -#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ - CONFIG_BS_COPY_CMD \ - CONFIG_SECBOOT +#define CHAIN_BOOT_CMD BS_COPY_ENV \ + BS_COPY_CMD \ + SECBOOT #endif #endif diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 9db0f0efb15051617ee918712f84c92d585a3996..2d52dc6f66080d78bd8ddfdda01b7bfe407564ab 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -19,7 +19,6 @@ /* * CFI Flash */ -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 275fb5665fd8b37d77bd9c4e007d7911557ce985..c773164c869b3ae67a02d296e4e7cbdf9701063d 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,15 +17,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -65,8 +56,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -83,20 +72,16 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 13743dab52dbd38ac8cae317f17dab70c571c6bf..79448cf440485ece061b00f21f415ba73cd1df0e 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -22,15 +22,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) @@ -75,8 +66,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -88,8 +77,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -97,18 +84,12 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -#ifdef CONFIG_NORFLASH_PS32BIT -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#else -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index f68eb979bddc4231f37e77a637257bbea49f41dd..1889a235a2a153f0008eab9425d42d32c20df92e 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -44,8 +44,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -65,7 +63,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -80,7 +77,6 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CONFIG_SYS_FLASH_CHECKSUM # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 079675be5bcbc0e421c4647838f47a0b05ef2907..cac9b24ead8e980052680ddf929abfd83961dac9 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -19,12 +19,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#ifdef CONFIG_IDE -/* ATA */ -# define CONFIG_IDE_PREINIT 1 -# undef CONFIG_LBA48 -#endif - #ifdef CONFIG_DRIVER_DM9000 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE @@ -79,8 +73,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -91,7 +83,6 @@ #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) /* * For booting Linux, the board info and command line data @@ -99,7 +90,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) @@ -116,7 +106,6 @@ * 0x30 is block erase in SST */ # define CONFIG_SYS_FLASH_SIZE 0x800000 -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_FLASH_CFI_LEGACY #else # define CONFIG_SYS_SST_SECT 2048 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index b8918680c14a1e8e5f42031b79466ab9bdcd0c58..2fa1e4356e3ec76af94eecd4ac0a64a3133b879f 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -31,15 +31,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - #ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 @@ -76,8 +67,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -89,7 +78,6 @@ #define CONFIG_SYS_FLASH_BASE 0xffe00000 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -103,7 +91,6 @@ */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 68e3c89a1cd87374dca14aa0781a3d5e85b17fa3..292578fc15b9653a7a2b7dac2dde5ca375cf543b 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -33,15 +33,6 @@ /* Available command configuration */ -#ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#endif -#endif - /* I2C */ #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) @@ -78,8 +69,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -91,7 +80,6 @@ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -99,7 +87,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index b6e569d82025df229dedfb77be801fa9b6048439..9f06f41ce11b7b9cc64c790252f82e9bdae352d4 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -29,15 +29,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - #ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 @@ -77,8 +68,6 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -92,7 +81,6 @@ #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -107,7 +95,6 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CONFIG_SYS_FLASH_CHECKSUM # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 34b5ceb20c4dba58879feb1a0616a8b03426549d..4d8f752777d08cf1e6e0f35c226be47c41c31edf 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -22,18 +22,9 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 -#define CONFIG_SYS_UNIFY_CACHE - #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_TX_ETH_BUFFER 8 # define CONFIG_SYS_FEC_BUF_USE_SRAM - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ #endif #define CONFIG_SYS_RTC_CNT (0x8000) @@ -79,8 +70,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -97,15 +86,12 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization @@ -113,7 +99,6 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_SPANSION_S29WS_N 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 673b0dc2e8db2421b94c2a874ee92982f2647a4c..87d3e8fb153b72109d583bdacb3a58d79b913cff 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,17 +22,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define CONFIG_SYS_UNIFY_CACHE - -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -75,8 +64,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -93,22 +80,18 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 4c9fc43fd6ca69edea1e554a52b29f457863fb5c..d920587c37908f3641ed9506787250344894dd25 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,17 +24,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ -#define CONFIG_SYS_UNIFY_CACHE - -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -77,8 +66,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -95,22 +82,18 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ #endif diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 01b33c77a88e9e0de9a10762402cc74dfb7aa93d..41ab860850833710142aa3220ce94a8bd8c40858 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -86,7 +86,6 @@ /* environment is in FLASH */ /* Ethernet configuration part */ -#define CONFIG_SYS_DISCOVER_PHY 1 /* NAND configuration part */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index eb4ccb17eaaf0789e6031b55c8e68b2bb4134ade..d56d60306abf7f9efc84498f603d9bf3d84d30d3 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -61,7 +61,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) @@ -127,12 +126,6 @@ * The reserved memory */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ /* @@ -141,8 +134,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * FLASH on the Local Bus @@ -200,43 +191,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ /* * TSEC @@ -257,29 +220,12 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x1c #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC2_PHYIDX 0 #endif #endif -/* - * SATA - */ -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - /* * Environment */ @@ -302,15 +248,11 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration */ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - #define CONFIG_NETDEV "eth1" #define CONFIG_HOSTNAME "mpc837x_rdb" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 244f811ff65bd66c801228735c2c74c676642f72..c3c68071f2f2f3197d02c7074ece3ce46b442743 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -16,10 +16,6 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#undef CONFIG_PCI2 - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #ifndef __ASSEMBLY__ @@ -34,7 +30,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR @@ -244,8 +239,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) @@ -265,8 +259,6 @@ */ #if !CONFIG_IS_ENABLED(DM_I2C) #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#else -#define CONFIG_SYS_SPD_BUS_NUM 0 #endif /* EEPROM */ @@ -320,10 +312,6 @@ #endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #define CONFIG_TSEC1 1 @@ -368,7 +356,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0c19b92940e30efde363b5ab49555d45ccbae31d..12a78eac17c90e9596205f7fec105635a957b713 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -16,18 +16,10 @@ #include #ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #endif #ifdef CONFIG_SPIFLASH @@ -35,65 +27,32 @@ #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #endif #endif #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #else #ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 -#else -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif #endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif #endif #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif @@ -104,9 +63,6 @@ /* High Level Configuration Options */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -138,8 +94,6 @@ #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif #define CONFIG_HWCONFIG @@ -148,12 +102,7 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ - -#define CONFIG_ENABLE_36BIT_PHYS - /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -169,7 +118,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 @@ -206,11 +154,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -/* Don't relocate CCSRBAR while in NAND_SPL */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - /* * Memory map * @@ -398,20 +341,11 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -424,29 +358,17 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) #else #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) #endif #endif #endif @@ -456,7 +378,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -524,46 +446,16 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */ -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif /* #ifdef CONFIG_FSL_SATA */ - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ -#endif #endif #endif @@ -584,7 +476,6 @@ extern unsigned long get_sdram_size(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 3d9e3e1c78b79302ffc90a8dbf04528c02c8e3a9..2d552835b7766533e48acfcb82868bae414c77e8 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -25,17 +25,12 @@ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ @@ -43,11 +38,6 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) - #define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - #ifndef __ASSEMBLY__ #include #endif @@ -55,11 +45,8 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -91,7 +78,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -141,10 +127,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -196,9 +178,7 @@ #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -334,24 +314,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 @@ -375,16 +337,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -400,7 +352,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index f1417b1bfc1555b6664c345263eca7dc4a3ed609..bc8aa3ce05498477f53b509226709863bb0b3b95 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -9,9 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN #define CONFIG_SYS_SRIO diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 8a0c7039f6679b2ae5c33a9f06f9610a4d00586d..6375c65d483b96818ff12e77e8caed285cf793f9 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -9,10 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 - -#define CONFIG_LBA48 - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index fc2a07b97410051014a93a0a77a02d9836dad343..fb73f0b953901c6aff11d9ca3ae1e46d7f0ee02d 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -9,8 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 8114373655f36015c3c15a174d3b3619c76e1843..e42e6d56532fd6e3497e7a6d13dd742de928abf1 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index b70829c09d58807e4e58a17d54557b4c02603ebe..8926c26b0bdfcf4bf8930131db0f8b9060173eb7 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e7cc39e78a92b3ef6a27699b8ab13bcdcc476374..c90ffe048c6f3237c01c7f113488d8e66b86fca5 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -14,43 +14,25 @@ #include /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -59,9 +41,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -116,7 +95,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -127,11 +105,7 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (256 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 @@ -149,11 +123,9 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif @@ -313,10 +285,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -337,9 +305,7 @@ #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -379,9 +345,6 @@ * General PCIe * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ @@ -407,18 +370,11 @@ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif /* * SDHC @@ -500,7 +456,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index de31f695c601195a23536ab0d569ed7832fb3a19..56486cf5c9345ba8ab911137155fd57aef6ca661 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -15,14 +15,6 @@ #include #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -40,21 +32,14 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -63,46 +48,26 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_NAND -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -#endif /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ @@ -114,11 +79,7 @@ */ #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -130,7 +91,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -297,10 +257,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -315,9 +271,7 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -401,30 +355,11 @@ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -511,7 +446,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 82e0fc46c7b658357a97245a90fdca741654ff04..710254a8fb47070face0a682305ad9bf86837ca2 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -15,50 +15,31 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #if defined(CONFIG_ARCH_T2080) -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -67,9 +48,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -90,7 +68,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -100,11 +77,7 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -119,7 +92,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -293,10 +265,6 @@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -310,9 +278,7 @@ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* @@ -395,10 +361,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -422,10 +384,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 @@ -473,26 +431,9 @@ #define SGMII_CARD_PORT4_PHY_ADDR 0x1F #endif -/* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - /* * USB */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif /* * SDHC @@ -522,7 +463,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 94385443253550b2b72b1bca855dd1101819f11e..8ade2e3c8292755512120e7669a57b9904ed8363 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -14,46 +14,27 @@ #include #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_SATA_V2 /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -62,9 +43,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -85,7 +63,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -95,11 +72,7 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -114,7 +87,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -252,10 +224,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -269,9 +237,7 @@ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* @@ -348,10 +314,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -375,10 +337,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 @@ -429,26 +387,9 @@ #define AQR113C_PHY_ADDR2 0x08 #endif -/* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - /* * USB */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif /* * SDHC @@ -476,7 +417,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 834855c336c922c9ec936ac441568662eb8db867..653483cc99f0c0cc7bf2de822462959e2198a615 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,9 +12,6 @@ #include -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL @@ -22,9 +19,6 @@ #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -34,53 +28,32 @@ #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif #endif #endif /* CONFIG_RAMBOOT_PBL */ /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -112,9 +85,7 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -164,22 +135,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * Environment */ @@ -196,7 +151,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration @@ -211,7 +165,6 @@ /* * DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 @@ -365,10 +318,6 @@ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ @@ -448,23 +397,9 @@ #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR #endif -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR diff --git a/include/configs/alt.h b/include/configs/alt.h index 090bee7d2d662b3e4b07112ec9af991baa52a404..fe303fda78a015d30d60b1f9d5c9ad237aee1940 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -11,10 +11,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -38,8 +37,4 @@ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 - #endif /* __ALT_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index fd5b209a52db25bcb4b17dfb854d91ecd649c63d..4b59759f818eb6e64fbec078693d24c60110cb18 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -19,22 +19,18 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN SZ_16M - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ @@ -172,14 +168,6 @@ /* PMIC support */ #define CONFIG_POWER_TPS65910 -/* SPL */ -#ifndef CONFIG_NOR_BOOT -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* USB gadget RNDIS */ -#endif - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ @@ -193,10 +181,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif #endif /* !CONFIG_MTD_RAW_NAND */ /* USB Device Firmware Update support */ @@ -241,7 +225,6 @@ #if defined(CONFIG_NOR) #define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE 0x01000000 #endif /* NOR support */ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index b92703205cde6b0e5b8b79b57c398ee750d86c0d..7fa1847c1fc239364ea9a75836e320e348eb56ef 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -12,8 +12,6 @@ #include -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -29,7 +27,7 @@ "ramdisk_addr_r=0x88080000\0" \ #define BOOT_TARGET_DEVICES(func) \ - func(UBIFS, ubifs, 0) + func(UBIFS, ubifs, 0, UBI, rootfs) #define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" @@ -52,9 +50,7 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ GUARDIAN_DEFAULT_PROD_ENV \ - "autoload=no\0" \ "backlight_brightness=50\0" \ - "bootubivol=rootfs\0" \ "distro_bootcmd=" \ "setenv rootflags \"bulk_read,chk_data_crc\"; " \ "setenv ethact usb_ether; " \ @@ -94,9 +90,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_LE - #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index 2cf77a67c0c2fced2c560e7ca7d1e240c9235cf0..3952783ee1a796d9170ed31646e0a2fcb03e2d30 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -20,7 +20,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "bootdir=/boot\0" \ @@ -55,8 +54,6 @@ "bootz ${loadaddr} - ${fdtaddr};" \ "fi;" \ "fi;\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=1\0" \ "nandrootfstype=ubifs rootwait\0" \ "nandload=ubi part UBI; " \ @@ -89,7 +86,6 @@ "setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \ "if test ${fdtfile} = ''; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 5964ccc74c26d70705c2ee8bcf03e2005aa0c16b..08bae9b886f283d4a916ac48b5ccdc95043703fa 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -16,8 +16,6 @@ /* settings we don;t want on this board */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index a57d551bcf172972454de19f41b3dbfc0d1eaec7..7df5f140551267a26ccfdae1b3d45d9c666ca2bc 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -10,14 +10,10 @@ #include -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ @@ -39,8 +35,6 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV -#endif - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ @@ -54,9 +48,6 @@ /* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* Network. */ #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b872ade1443d918329a1074a9910d6236fdf66be..93beed4ad7369d15a5659655e1949e75d2a4a8aa 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 /* NAND block size is 128 KiB. Synchronize these values with * corresponding Device Tree entries in Linux: * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 @@ -50,8 +49,6 @@ "bootenv=uEnv.txt\0" \ "cmdline=\0" \ "optargs=\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ @@ -86,20 +83,8 @@ /* Miscellaneous configurable options */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* memtest works on */ -/* Physical Memory Map */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - /* FLASH and environment organization */ /* **** PISMO SUPPORT *** */ @@ -113,8 +98,4 @@ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -/* Defines for SPL */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 5057441f7506b5670c5c9f7d39ed8fb26c3ca92d..87d3a27099bd326241cba8b814cff4c1c85ffcb9 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -27,8 +27,6 @@ #define CONFIG_POWER_TPS62362 /* SPL defines. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 @@ -50,12 +48,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -/* SPL USB Support */ - -#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 -#endif - #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ #define DFUARGS \ @@ -153,20 +145,13 @@ } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 26 -/* NAND: SPL related configs */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ -#endif #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c36311e06d79c345a83158c6b86fb6716b248c1d..d8b0531673f1acde15a7813698150375c715656b 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -16,8 +16,6 @@ #define CONFIG_IODELAY_RECALIBRATION -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h new file mode 100644 index 0000000000000000000000000000000000000000..78201adc07f54d814126f8b8ba65b57f429995d7 --- /dev/null +++ b/include/configs/am62x_evm.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM625 SoC family + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#ifndef __CONFIG_AM625_EVM_H +#define __CONFIG_AM625_EVM_H + +#include +#include + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM625_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM625_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM625_BOARD_SETTINGS \ + EXTRA_ENV_AM625_BOARD_SETTINGS_MMC + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_AM625_EVM_H */ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index d84a8db97edeafe5808c1c31a19bc11c7403fcae..140940730d0ef8706645339b483bbc4a3fa77c3a 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -18,37 +18,6 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE -#if defined(CONFIG_TARGET_AM642_A53_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) -#else -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (TI_SRAM_SCRATCH_BOARD_EEPROM_START -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#endif - #define PARTS_DEFAULT \ /* Linux partitions */ \ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" @@ -137,6 +106,4 @@ /* Now for the remaining common defines */ #include -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 - #endif /* __CONFIG_AM642_EVM_H */ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index b1f9050f3f5baf9148299a10ca2a63272dad3061..0345160787ef33fdb45e9e058c1894d58f9688fe 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -17,41 +17,6 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 -/* SPL Loader Configuration */ -#ifdef CONFIG_TARGET_AM654_A53_EVM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) -#else -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xc00 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define PARTS_DEFAULT \ /* Linux partitions */ \ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" @@ -98,14 +63,6 @@ "0 /lib/firmware/am65x-mcu-r5f0_0-fw " \ "1 /lib/firmware/am65x-mcu-r5f0_1-fw " -#ifdef CONFIG_TARGET_AM654_A53_EVM -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD -#endif - #define EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ "init_ubi=run args_all args_ubi; sf probe; " \ "ubi part ospi.rootfs; ubifsmount ubi:rootfs;\0" \ @@ -137,14 +94,11 @@ DEFAULT_FIT_TI_ARGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ - EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ BOOTENV -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 - /* Now for the remaining common defines */ #include diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 898978eb96ab75cfd88dd1adbc95e2eb92791018..3c9267b14ec98a4aef39dbdd05399c632fe6ea44 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -32,9 +32,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* size of internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 @@ -46,7 +43,6 @@ #define CONFIG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index e1c2e066131c722a96684cf71617c629560e6cbf..099aac5421978ca6616eec5e64de95200f2d3cf8 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 200 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* Miscellaneous configurable options */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 37fc196514f6822a1348dfb6829a007754564021..60b9e779fa926773e231383bc620ba53e1e047a0 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 325 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* * Serial Port diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 9f47633371087c728be30ac94ad6c94066658fb4..d165ead7bb4d1852c23ed7b542f0a23e529bf4f0 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 375 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* * Serial Port diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index c8422264b755f79820353d76cf5efb820847d58d..c9f876f5da7e5d0c35b8e56daa2043547a0771dd 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -60,24 +60,13 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ #define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif /* __APALIS_IMX8_H */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index face78e1dd405f1b00495b61c1c572feb3556116..6a4092a83e2e3c2ccbf2fe0de644ccae9a260c77 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -19,12 +19,6 @@ #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" -/* PCI host support */ -#undef CONFIG_PCI_SCAN_SHOW - -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - /* * Custom Distro Boot configuration: * 1. 8bit SD port (MMC1) @@ -89,18 +83,6 @@ "source ${loadaddr}\0" \ "vidargs=fbcon=map:1\0" -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index aa93d10f852d761ac19bac1e845878bd0fec6d7e..4922b063309e2c5d7b4aaa4d9d319236fd24452b 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -25,20 +25,11 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_LBA48 -#endif - /* Network */ #define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ /* USB Configs */ /* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Client */ @@ -56,7 +47,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -66,9 +56,6 @@ #include #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ @@ -119,10 +106,6 @@ "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -131,9 +114,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index d1d518a53407fd2289ceb0abf471c0194c601d35..84bd88f835ae62f2153f61caaa5bcec7e5f37773 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -23,21 +23,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=0\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8ee97f1d4e35ec7d71cc0faf8b17fe4af56ce13d..8997c6a0ea9001303c3581ce3a761168858aeb32 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -14,10 +14,8 @@ #define CONFIG_HOSTNAME "aristainetos2" #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #endif @@ -112,9 +110,6 @@ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ - "mtdids=nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor)\0" \ "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ @@ -417,17 +412,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_FSL_USDHC_NUM 2 /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index acd140ee35eed2d6149d8b65a5b189ecb0a9f820..1c7494183a4d5c73ca34ef819065c78a257c73f1 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -20,16 +20,14 @@ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) /* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 #define STACK_AREA_SIZE 0xC000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 #define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ @@ -48,7 +46,6 @@ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 5109f7de53433dadfbcef0ae619c65ef9f3ef5c4..7a244769e30a3ef687f9021924bf86f7da6d2f2d 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -14,16 +14,9 @@ #include "exynos5250-common.h" #include -/* MMC SPL */ -#define CONFIG_EXYNOS_SPL - /* Miscellaneous configurable options */ -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -#define CONFIG_S5P_PA_SYSRAM 0x02020000 -#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM +#define CONFIG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 0954bc02aa27555940a8e54e0c17b212298e2ba9..5c9005805e1f97cdb9e4fb49f11d42a7a695195d 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) #endif -#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \ - + CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ - - GENERATED_GBL_DATA_SIZE) - /* * NS16550 Configuration */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 9d1203f397805d0ff5ff9dedbc8f29638af3f63b..a8265e961a26e0482791813b670c719f7000cd84 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -65,8 +65,6 @@ #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 #define CONFIG_SYS_CORE_SRAM 0x80000000 -#define CONFIG_SYS_UNIFY_CACHE - /* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud @@ -133,7 +131,6 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 @@ -162,9 +159,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Start addresses for the final memory configuration @@ -204,8 +198,6 @@ /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index f5cc0b2b9125d001a0a92a63675564728271d198..ef9335c523f48586e0b6d5f35326f3be51f6b69e 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -34,17 +34,11 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM #else -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 #endif /* NAND flash */ @@ -59,12 +53,6 @@ #endif /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 2089fe52e45608147f826c5bec6d2a4930a09892..12726c10bd6d5725eb1ba76e7fb13381f094d65e 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -26,8 +26,8 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -51,16 +51,6 @@ #define CONFIG_DM9000_NO_SROM /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ -#ifdef CONFIG_AT91SAM9G10EK -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" -#else -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#endif -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b63cd4bb83925c21f6b10263fbc86e78ff4ac597..9497f055035dea942c5548b61c4526a53c8b8ad3 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH @@ -173,12 +173,6 @@ #endif /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 38b9061080ab2a76f495fd72e13b23953e70ec0b..b55d2e3925532d7f77e2f8ddc170fdc646dd78da 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -23,9 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x70000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -40,23 +37,10 @@ #endif -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - #define CONFIG_SYS_MONITOR_LEN 0x80000 #ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x70000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 #define CONFIG_SYS_NAND_ECCSIZE 256 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 7d378177b043e9309f37994a5826349fafb67b57..4d492988eba7feb446d427c7d32e835d4c5dd80b 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -22,14 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -# define CONFIG_SYS_INIT_SP_ADDR \ - (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* DataFlash */ /* NAND flash */ @@ -44,29 +36,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" -/* USB host */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) @@ -75,8 +48,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e0aeae88d142ea1bd36281b9e27150fc31e68d6c..e418edddfbe5bfacfc9de31e114e7bc6da2bd46a 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -22,15 +22,13 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -/* Let board_init_f handle the framebuffer allocation */ -#undef CONFIG_FB_ADDR /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 013c7cfc59ce856c2c714501ada84f6edf64efaa..0e7665843dba5189a14e2b87bf24b0e9f12d18d6 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -23,9 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* DataFlash */ /* NAND flash */ @@ -41,27 +38,7 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#ifndef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) @@ -70,8 +47,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index ba314026ce9f1bc677bc43950404e8d3bf2875e2..daa5cdf5b26bbcbd566f96b9d85063a390936790 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -7,16 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_SPL -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x04000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 - -#ifdef CONFIG_SPL_MMC -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -#endif -#endif - #define RISCV_MMODE_TIMERBASE 0xe6000000 #define RISCV_MMODE_TIMER_FREQ 60000000 @@ -29,26 +19,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* - * Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * max number of command args - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot Argument Buffer Size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE 0x800f0000 /* * Physical Memory Map @@ -70,13 +40,6 @@ #define CONFIG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ - GENERATED_GBL_DATA_SIZE) - -/* use CFI framework */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* support JEDEC */ #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ @@ -110,7 +73,6 @@ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Support autoboot from RAM (kernel image is loaded via debug port) */ #define KERNEL_IMAGE_ADDR "0x2000000 " diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index cb400be77a638020bdb3ea1716bbc30539670dad..f2357b5785a11bce864682e5915b053bd280433a 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -23,11 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_512M -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -42,8 +37,6 @@ /* * USB 1.1 configuration */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 /* * Environment settings diff --git a/include/configs/baltos.h b/include/configs/baltos.h index b881d8c03fd777a15ae160643d7f578ff738e6f5..266b2ae04b3ff808747854550b538d9a71b32523 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -24,20 +24,17 @@ #define V_SCLK (V_OSCK) /* FIT support */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "setenv loadaddr 0x84000000; " \ @@ -52,7 +49,6 @@ #define NANDARGS "" #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "boot_fdt=try\0" \ @@ -183,7 +179,6 @@ "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ NANDARGS /*DFUARGS*/ -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h new file mode 100644 index 0000000000000000000000000000000000000000..d0c46a2c823b229829597abd2e7d42006ceaefbb --- /dev/null +++ b/include/configs/bcm947622.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#ifndef __BCM947622_H +#define __BCM947622_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define COUNTER_FREQUENCY 50000000 +#endif diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 81b4218c88822cade30c7d80862717cd3e5ec34d..795de469384c3708cb06d2cae6562d0f28a29348 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -23,23 +23,15 @@ * Just before re-loaction, new SP is updated and re-location happens. * So pointing the initial SP to end of 2GB DDR is not a problem */ -#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000) /* 12MB Malloc size */ /* console configuration */ #define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * Increase max uncompressed/gunzip size, keeping size same as EMMC linux * partition. */ -#define CONFIG_SYS_BOOTM_LEN 0x01800000 /* Access eMMC Boot_1 and Boot_2 partitions */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 98c815961c04e321df7cbf0b3870810140a108c5..134a3ec28920a5627c24ccd6642df98eacebf26a 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -83,20 +83,14 @@ extern phys_addr_t prior_stage_fdt_address; */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 /* * Large kernel image bootm configuration. */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* * NS16550 configuration. diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 2bcd0e1a989d97e782101f590f4c965b6d245c7c..829e816ad664be656c074f9e23c1d8d588a2e071 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "pxefile_addr_r=0x2000000\0" \ "scriptaddr=0x3000000\0" \ "kernel_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index bd07b4b031b411a5cbf834f9e25064b3d9dc9b19..925a68787c91f0322cfee3d21bba5a914952e247 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -67,7 +67,6 @@ /* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ BK4_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -81,7 +80,6 @@ "nfs_root=/path/to/nfs/root\0" \ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "ipaddr=192.168.0.60\0" \ "serverip=192.168.0.1\0" \ "bootargs_base=setenv bootargs rw " \ @@ -213,9 +211,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 4f8da5940431f5a8747bf0aa1f445a756ed4d6f3..25b6e7005e7aebe4a68881424477220d597df398 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -12,10 +12,9 @@ #include "rcar-gen2-common.h" /* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -28,7 +27,6 @@ #if !defined(CONFIG_MTD_NOR_FLASH) #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 412471a4aaa16368a372076793a3514d0fe1ab2d..55c1d439d58bfd317224057e5a12a69d746eacd6 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 8caddf384628955e9a6ecb734298563a268764ae..f046b7e6622f697afb377479cc2b1c09d7441a8a 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 892a3e2c41e0d7d020a2b08e5da9de5992b2f158..7e488072edc0b1302a5aaf1a665fcd4ee2e97e08 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index af1c3673fbb9bda8a54326e9d7f9499b63591503..f704fe26ca0dd18bea83f579b7a3fe38509da61e 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,13 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 6cb09492aa8968fad7a80256a9a165683d6047fc..9aaa694cad916401213126932a7f5691ee8721fb 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 92ab0ba7a2f0a47e72f11f5adcf18fd19c283685..34e542544cb890e947a7892fb3becb3c9f38ac83 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 8a22dc1a3c32fb28209c6a4dc9fbe652418880e3..0319124a0eddb05f255298df9ca0ec528fcd2654 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 899a538082edceece80dc4ddaf7b8ac5c32afc58..7e358a6314bfef83ba32180ecd58c8eb436ccadb 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -12,9 +12,4 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K -#define CONFIG_SYS_CBSIZE SZ_512 - #endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h index 3bf85b6c28d1b92a65aafe4fbe2326d1ce1b4986..8b04492753a870887b84ae3afa1fc988ff6709e2 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -9,7 +9,6 @@ /* * General board configuration */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* * CPU diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 5aa784d88cac3ab44cec17f4dd94f038099ecbde..0c8d352be97ce12f161b00301dec319ac87a4a60 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) /* * 63158 @@ -24,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm96753ref.h b/include/configs/broadcom_bcm96753ref.h index c002985cf451ca138e764d9c7ad23512a6b22f02..33c70c73c1fca0f66cd6168f3542ac98789f2f76 100644 --- a/include/configs/broadcom_bcm96753ref.h +++ b/include/configs/broadcom_bcm96753ref.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 /* * 6853 @@ -23,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h index 01bab046ddb0963814f999181c3e09efe06ef155..8a802357123688bd44287d5d4645a10886769506 100644 --- a/include/configs/broadcom_bcm968360bg.h +++ b/include/configs/broadcom_bcm968360bg.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 /* * 6858 @@ -23,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index ebfc2ecc0be14226cfe37b7185cca20d6cd9e001..abc2da3d1fe3cfb5d77ea9aeb6ead7762976dbdc 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 /* * 6858 @@ -23,7 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 769b3f073acca8b053f583882bb576477249e121..789e6a4c9d597b240ddbce1c613191d49272dca2 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -16,7 +16,6 @@ #include /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ @@ -29,16 +28,8 @@ */ #ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 - /* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ -/* NAND */ -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 -#endif /* CONFIG_MTD_RAW_NAND */ #endif /* CONFIG_SPL_OS_BOOT */ #ifdef CONFIG_MTD_RAW_NAND @@ -47,8 +38,6 @@ #ifdef CONFIG_MTD_RAW_NAND #define NANDTGTS \ -"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ -"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ @@ -107,11 +96,9 @@ MMCSPI_TGTS \ #define LOAD_OFFSET(x) 0x8##x -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "verify=no\0" \ -"autoload=0\0" \ "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ @@ -131,7 +118,6 @@ NANDTGTS \ "b_default=run b_deftgts; for target in ${b_tgts};"\ " do echo \"### booting ${target} ###\"; run b_${target};" \ " if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ #ifdef CONFIG_MTD_RAW_NAND /* diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 92f69ba9b0f5d2f198c112dc35b42ba0e7446d20..adaba410ce9714a429fd193026101b33b55066f7 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -29,7 +29,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "cfgaddr=0x106F0000\0" \ "scraddr=0x10700000\0" \ "loadaddr=0x10800000\0" \ @@ -81,16 +80,11 @@ BUR_COMMON_ENV \ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Ethernet */ #define CONFIG_FEC_FIXED_SPEED _1000BASET /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* SPL */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index f1e6dbf613583c39bde8c04374ec7a2e48a9be9c..f9908352b0dc9c8feb327c96fd1fb7335b3f77fe 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -18,18 +18,14 @@ /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "cfgscr=mw ${dtbaddr} 0;" \ " sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \ @@ -56,7 +52,6 @@ BUR_COMMON_ENV \ " fdt boardsetup\0" \ "startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \ " bootm ${loadaddr} - ${dtbaddr}\0" -#endif /* !CONFIG_SPL_BUILD*/ /* SPI Flash */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index d34d69778f1ba5399fa73d53d69823747cfa5dfb..4d91a776ba8410170026937bc5dc1a1372ca7088 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -23,12 +23,9 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ "bootdev=cpsw(0,0)\0" \ @@ -51,7 +48,6 @@ BUR_COMMON_ENV \ "b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ "b_default=run b_deftgts; for target in ${b_tgts};"\ " do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ /* Environment */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 5fc8ce622b1f54ec0cb229d551111952cff82b79..a6de28a42b2ed5b94ead73ce6d9cf89510d5002b 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -24,7 +24,6 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include @@ -37,8 +36,6 @@ * Y-MODEM to load u-boot.img, when booted over UART. We must also include * the scratch space that U-Boot uses in SRAM. */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) /* * Since SPL did pll and ddr initialization for us, @@ -51,8 +48,6 @@ * and we place the initial stack pointer in our SRAM. */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /* * Our platforms make use of SPL to initalize the hardware (primarily @@ -73,11 +68,6 @@ * * ---------------------------------------------------------------------------- */ -#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN /* General parts of the framework, required. */ diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h index 69850117637c9885109ba5b15c298350c0afcb9b..304abc6d2e21d8dadc440cb2beb92baa8c6f5ab5 100644 --- a/include/configs/bur_cfg_common.h +++ b/include/configs/bur_cfg_common.h @@ -27,10 +27,4 @@ /* As stated above, the following choices are optional. */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - #endif /* __BUR_CFG_COMMON_H__ */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 364bd50b5912fc52c34b6e4df8427cd926e26bdb..6b1e82ad3b17e04ad3388643a32530975899bb8e 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -15,36 +15,22 @@ /* SPL config */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - #endif /* CONFIG_SPL_BUILD */ -#define CONFIG_FACTORYSET - /* ENET1 connects to base board and MUX with ESAI */ #define CONFIG_FEC_ENET_DEV 1 #define CONFIG_FEC_MXC_PHYADDR 0x0 -/* I2C Configuration */ -#ifndef CONFIG_SPL_BUILD /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ #define EEPROM_I2C_ADDR 0x50 /* PCA9552 */ #define PCA9552_1_I2C_BUS 1 /* I2C1 */ #define PCA9552_1_I2C_ADDR 0x60 -#endif /* !CONFIG_SPL_BUILD */ /* AHAB */ #ifdef CONFIG_AHAB_BOOT @@ -106,7 +92,6 @@ ENV_NET /* Default location for tftp and bootm */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 /* On CCP board, USDHC1 is for eMMC */ @@ -117,11 +102,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -/* Console buffer and boot args */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 4c04bbf644717049e4effa5c602085e5f6d6a92b..6ac8487851952c53eb2f2acf9d9a846aee78e74f 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -12,20 +12,11 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Flat Device Tree Definitions */ @@ -120,8 +111,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 82acda595f0922443fbca735180917d36ca57bd6..965eba58b311d49b9b477f41fa569cb24dac8d65 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -13,14 +13,12 @@ #define V_SCLK (V_OSCK) #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} ${optargs} " \ "${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdt_addr} NAND.u-boot-spl-os; " \ @@ -107,8 +105,6 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 96d5cf1a33893cc24d3ce60bd2257110703546ee..0787359674d656a73401fe526bb8cdce7aaa8e89 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -15,6 +15,4 @@ #include #include -#define CONFIG_SPL_BOARD_LOAD_IMAGE - #endif /* __CONFIG_H */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index cc70a59e7280a89f3197e075ed97ed6287130c0c..192da015e188b18332d6aa6739364198c349a3db 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -15,7 +15,6 @@ /* Memory configuration */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 @@ -28,22 +27,6 @@ #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE + 2) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - /* Miscellaneous configuration options */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -/* SPL */ -#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ - -#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) - -#define CONFIG_SPL_BSS_START_ADDR 0xf4004000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ - -#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" #endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 4b494d8aeef7967c7819ef1138ead477c4a2ee8b..1043eb75060fd644d3ea40916b595226383c9012 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -26,13 +26,9 @@ #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } -#undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_SYS_AUTOLOAD "no" - #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=off\0" \ "script=boot.scr\0" \ "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ @@ -90,11 +86,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* SPI Flash support */ /* FLASH and environment organization */ @@ -107,10 +98,8 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* SPL */ #include "imx7_spl.h" diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 871e87c26d015a7e600e052bd29a5a799567a1c1..9c9e9506dc64da8166a8dfdffbb50fe135fe27af 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -18,8 +18,6 @@ * U-Boot into it. */ -#define CONFIG_ENV_MIN_ENTRIES 128 - /* Environment in MMC */ /* * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC @@ -30,39 +28,11 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -70,8 +40,6 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) #else @@ -148,6 +116,4 @@ "console=ttyS0,115200\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif /* _CONFIG_CLEARFOG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 600999b8e72e70c4684539a3d9b77631c8e8fca3..cbba7264400264914f43a5239aa261058d865351 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -24,17 +24,12 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE /* Environment */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -48,7 +43,6 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "panel=HDMI\0" \ - "autoload=no\0" \ "uImage=uImage-cm-fx6\0" \ "zImage=zImage-cm-fx6\0" \ "kernel=uImage-cm-fx6\0" \ @@ -59,8 +53,6 @@ "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ "doboot=bootm ${kernel_addr_r}\0" \ "doloadfdt=false\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setboottypez=setenv kernel ${zImage};" \ "setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \ "setenv doloadfdt true;\0" \ @@ -134,16 +126,11 @@ func(SATA, sata, 0) #include -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* NAND */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* APBH DMA is required for NAND support */ -#endif /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 0 @@ -151,13 +138,6 @@ /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - -/* SATA */ -#define CONFIG_LBA48 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR /* Boot */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index ad2e88189075ee50ef0a14d7d9defe8dc68065a2..4baf7f7e24aed09884d06645e865d64ac9975f80 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -19,7 +19,6 @@ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD #define MMCARGS \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ @@ -32,8 +31,6 @@ "bootm ${loadaddr}\0" #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:rootfs rw\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs console=${console} " \ @@ -55,9 +52,6 @@ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ MMCARGS \ NANDARGS -#endif /* CONFIG_SPL_BUILD */ - -#define CONFIG_SYS_AUTOLOAD "no" /* Serial console configuration */ @@ -86,9 +80,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 -#endif /* GPIO pin + bank to pin ID mapping */ #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) @@ -98,7 +89,6 @@ /* EEPROM */ -#ifndef CONFIG_SPL_BUILD /* * Enable PCA9555 at I2C0-0x26. * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. @@ -106,6 +96,5 @@ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } -#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_CM_T335_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index eb015e1b20f2de75e3e3cb4f2e82d807aa359deb..07c5cb8ded1b506a5c35bf1c2ef9f82c647c62b1 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -56,7 +56,6 @@ "loadaddr=0x80200000\0" \ "fdtaddr=0x81200000\0" \ "bootm_size=0x8000000\0" \ - "autoload=no\0" \ "console=ttyO0,115200n8\0" \ "fdtfile=am437x-sb-som-t43.dtb\0" \ "kernel=zImage-cm-t43\0" \ @@ -76,7 +75,6 @@ "bootz ${loadaddr} - ${fdtaddr}\0" /* SPL defines. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* EEPROM */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 1822ce5120ac76eef7cde841e5e79477b7f1d4ce..dd7b6c08730cc838254f78f313da45ee15bb3e5c 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -85,15 +85,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* *----------------------------------------------------------------------------- * Define user parameters that have to be customized most likely @@ -157,7 +148,6 @@ enter a valid image address in flash */ * --- */ -#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_SYS_ENET_BD_BASE 0x780000 /*----------------------------------------------------------------------- @@ -165,8 +155,6 @@ enter a valid image address in flash */ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -190,7 +178,6 @@ enter a valid image address in flash */ #define CONFIG_SYS_FLASH_BASE 0xffe00000 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 9e5212acb2eea1f51e9662efe9e4fd57e5e42cd7..04cde9530adba8393954304956b9b43801b167c8 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -65,7 +65,6 @@ #define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" #define MODULE_EXTRA_ENV_SETTINGS \ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #else #define MODULE_EXTRA_ENV_SETTINGS "" @@ -91,7 +90,6 @@ UBI_BOOTCMD \ UBOOT_UPDATE \ "boot_script_dhcp=boot.scr\0" \ - "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ "fdt_board=eval-v3\0" \ @@ -122,16 +120,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE) -#endif - #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -140,11 +128,9 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 3ed89c2776c793edfcf6467643ce51a1e0ab3892..5d6449c7f74a4b203e6193ba4b72ac41566e5912 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -91,28 +91,17 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* Environment in eMMC, before config block at the end of 1st "boot sector" */ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* Generic Timer Definitions */ #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 9ca6bef192fd1fdf9a417dad3a37c428696c53d7..3c220e0d6e3ee5e635733bb3d97f3356a0bb4530 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -27,8 +27,6 @@ /* USB Configs */ /* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Client */ @@ -46,7 +44,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ @@ -55,9 +52,6 @@ #include #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ @@ -106,10 +100,6 @@ "vidargs=fbmem=8M\0" /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -118,9 +108,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 3dba7bcef2586b13af245174f4d05247ac73640c..9543e0233ee131d50060b745704282c8bede3132 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -102,7 +102,6 @@ #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) #define MODULE_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ @@ -131,7 +130,6 @@ UBOOT_UPDATE \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ - "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=\0" \ "fdt_board=eval-v3\0" \ @@ -166,16 +164,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE) -#endif - #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -184,11 +172,9 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index f6b3ab1b041ad45352f96b343020ad375b0a9665..73d18444215a2c969690012094cfbfc63e826a55 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -25,21 +25,8 @@ /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ #define BOARD_EXTRA_ENV_SETTINGS \ "boot_script_dhcp=boot.scr\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBOOT_UPDATE -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 1ce0def4ddf09b07a92cf6017c6a706defb64482..c9d384e2bdbebf68a9d186bfc9be5757ea0ee248 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -24,18 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=0\0" \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 99b0cbb3420f61830b8e2f38ac299e1aaa31db9e..268afbb7fa389cfa2c36cdffc8c388087dda7dfa 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -68,7 +68,6 @@ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ "kernel_image=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setsdupdate=mmc rescan && set interface mmc && " \ "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ @@ -82,8 +81,6 @@ "video-mode=dcufb:640x480-16@60,monitor=lcd\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Physical memory map */ #define PHYS_SDRAM (0x80000000) @@ -93,19 +90,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_RANGE (4 * 64 * 2048) -#endif - /* USB Host Support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB DFU */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index b499d7085fd4af2707a120fc85ce8cfcda151d8e..5da2778b67bee4a8070871191cdafa8cb71f961e 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -17,49 +17,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (160 << 10) - -#if defined(CONFIG_SECURED_MODE_IMAGE) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) -#else -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) -#endif - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * Environment Configuration */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 121963fe5ce5ff6cc6556bb9a0719c1bf21c893d..4eeca47c2534faac0971b7c144b865911a930d3d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -15,17 +15,8 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL -#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_RAMBOOT_NAND -#endif -#define CONFIG_BOOTSCRIPT_COPY_RAM -#else -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -37,33 +28,21 @@ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -94,7 +73,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -139,10 +117,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -194,8 +168,7 @@ #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -334,22 +307,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d @@ -372,16 +329,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -397,7 +344,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h new file mode 100644 index 0000000000000000000000000000000000000000..38d7fe8d0d428d72233cf0e5390f703e07b7bee2 --- /dev/null +++ b/include/configs/corstone1000.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva + * Abdellatif El Khlifi + * + * Configuration for Corstone1000. Parts were derived from other ARM + * configurations. + */ + +#ifndef __CORSTONE1000_H +#define __CORSTONE1000_H + +#include + +#define V2M_BASE 0x80000000 + +#define CONFIG_PL011_CLOCK 50000000 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#endif diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 4809b59ecc394a571a20a6a21db378ccb7a043bd..698da6b6dac8d331dd3b07e74bffda1929e357e5 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -35,9 +35,6 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -57,14 +54,7 @@ /* bootstrap + u-boot + env in nandflash */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) -#define CONFIG_SPL_STACK (SZ_16K) - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -81,7 +71,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 4dbc75826699e3d94f47ebab27b07af94e800299..25bcc2a6841cd4c75fdb11597c9c2922102030c2 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -10,8 +10,6 @@ * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ - /* Environment in SPI NOR flash */ /* Keep device tree and initrd in lower memory so the kernel can access them */ @@ -24,7 +22,5 @@ * to enable certain macros */ #include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 #endif /* _CONFIG_CRS3XX_98DX3236_H */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 855711e62907e9b27d60f242f2d4581735265a70..3db97205dab8711ad4f0307139d3e2d708d38eec 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -32,8 +32,6 @@ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ -#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE -#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 /* memtest start addr */ /* memtest will be run on 16MB */ @@ -103,9 +101,7 @@ /* * I2C Configuration */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 -#endif /* * Flash & Environment @@ -148,8 +144,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ /* * Linux Information @@ -176,21 +170,8 @@ "console=ttyS2,115200n8\0" \ "hwconfig=dsp:wake=yes" -/* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#ifndef CONFIG_MTD_NOR_FLASH -#define CONFIG_SPL_PAD_TO 32768 -#endif - #ifdef CONFIG_SPL_BUILD /* defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_STACK 0x8001ff00 -#define CONFIG_SPL_MAX_FOOTPRINT 32768 #endif @@ -199,13 +180,6 @@ /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_MTD_NOR_FLASH */ - #include #endif /* __CONFIG_H */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index ad28fa012021a8750c8802877761a03e5725a8bb..36052fe7d8677b205494a154d1f5832c35e30a47 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -49,16 +49,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 16c83a88daceac723bf293ca1a73224ad2e26980..ef9c457e1020782a9792a7a0a591fe763725d42b 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -20,7 +20,6 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ @@ -34,16 +33,5 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) #endif /* _CONFIG_DB_88F6720_H */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 6538e66052aaca8f4ba2f5ac533c9e5119284f4f..b9d03d253d99d9d793d6b1b921d4cb742dc8538f 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -14,11 +14,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ @@ -26,39 +21,10 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * - * MMC is not populated on this board. - * NAND support may be added in the future. - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros */ #include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 #endif /* _CONFIG_DB_88F6820_AMC_H */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 8dc73e8b1cc9a870dbc3bc0981a7ee9a2a4d89ba..bba2b607aa8621e11ddef16f5e792502bff61b04 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -17,49 +17,11 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index d6850bd32e72856035bfa710b3a8561fdb37d19b..7b305955c9629b15d9dd265d3cc80fe828661ca0 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -16,20 +16,11 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* SATA support */ -#define CONFIG_LBA48 - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ /* @@ -53,17 +44,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SPD_EEPROM 0x4e diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 1d242bf4e6503a8626ae540dfe0ede38cfbe3605..84ea1baa99799b8167f9635f7d14a9a10b20f302 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -20,7 +20,5 @@ * to enable certain macros */ #include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 #endif /* _CONFIG_DB_XC3_24G4G_H */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index bc5282a48934c03cb4da9d709ba14811b3da1ffe..328e4958f86a2c991dce570d4c68a8fe3ea49937 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - - GENERATED_GBL_DATA_SIZE) - /* * DMA */ @@ -58,14 +55,11 @@ /* * USB */ -#define CONFIG_USB_OHCI_LPC32XX #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d /* * U-Boot General Configurations */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * Pass open firmware flat tree @@ -76,7 +70,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "ethaddr=00:01:90:00:C0:81\0" \ "dtbaddr=0x81000000\0" \ "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ @@ -87,26 +80,6 @@ * U-Boot Commands */ -/* - * SPL specific defines - */ -/* SPL will be executed at offset 0 */ - -/* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 - -/* Use the framework and generic lib */ - -/* SPL will use serial */ - -/* SPL loads an image from NAND */ -#define CONFIG_SPL_NAND_RAW_ONLY - -#define CONFIG_SPL_NAND_SOFTECC - -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE - /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 5dbd126a2a0f0af152508e491d015f8d4745eb58..d45115bdf68343938612a3a9eb376b9bbd766752 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -14,23 +14,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -/* Physical Memory Map */ - #include /* Hardware drivers */ @@ -46,9 +29,12 @@ /* BOOTP/DHCP options */ +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + /* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ + MEM_LAYOUT_ENV_SETTINGS \ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ "vram=12M\0" \ @@ -111,8 +97,6 @@ "fi; " \ "else run nandboot; fi\0" -/* Boot Argument Buffer Size */ - /* Defines for SPL */ /* NAND boot config */ @@ -124,15 +108,4 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 -/* SPL OS boot options */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 - -#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR -#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ - -#undef CONFIG_SYS_SPL_ARGS_ADDR -#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) - #endif /* __CONFIG_H */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 178f5a6e7d60c674186d84b46ba3ab7be75624d0..79424647f61805a15bb41779a9da98ec7ca49b8f 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -23,29 +23,20 @@ /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* Miscellaneous configurable options */ -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* SATA Configs */ -#define CONFIG_LBA48 - /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) @@ -57,7 +48,6 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ @@ -82,7 +72,6 @@ func(DHCP, dhcp, na) #include -#endif /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -91,12 +80,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment */ #endif /* __DH_IMX6_CONFIG_H */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 7bd653364d3365c171bfa78ea3702f33d5118d70..c23a57ee7a2b3dab41a257e5ccf1d26e468f49d0 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -10,12 +10,8 @@ #include "mx6_common.h" /* Falcon Mode */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ - (CONFIG_CMD_SPL_WRITE_SIZE / 512) /* * display5 SPI-NOR memory layout @@ -284,14 +280,6 @@ "\0" \ /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 2048 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 @@ -302,11 +290,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 0590704000ec7b50c5d5a5950ce8b49a8522a3d4..015bc78648f375ab005c505128785eaf65c22ffe 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -40,9 +40,7 @@ "stdout=serial\0" \ "stderr=serial\0" \ "loadaddr=0x800000\0" \ - "autoload=no\0" \ "console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "optargs=\0" \ "bootenv=uEnv.txt\0" \ "importbootenv=echo Importing environment ...; " \ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 381a189149ea169eed744d92453984293a0cb373..33ae7d654b0bead1d966d25beebbebac1049dd5c 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -24,8 +24,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "initrd=/boot/uInitrd\0" \ "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e16af8824b40fe4ac163d62c387082ab4421d778..9247720f8b6d8660ed0977f7467ac7edf76641a0 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -84,18 +84,12 @@ 50, 51, 52, 53, 54, 55, 56, 57, } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -/* NAND: SPL related configs */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif #endif /* !CONFIG_MTD_RAW_NAND */ /* Parallel NOR Support */ #if defined(CONFIG_NOR) /* NOR: device related configs */ #define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ #define CONFIG_SYS_FLASH_BASE (0x08000000) /* Reduce SPL size by removing unlikey targets */ diff --git a/include/configs/draak.h b/include/configs/draak.h index 476b4c3710a27d26a1f6b27745cccd82bc79b1ea..a38e48634835b8093975f7da427de5ad0dd1f81a 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -15,7 +15,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/draco.h b/include/configs/draco.h index d305608101331937bcf514bcf031db0cc4d514e4..4869008da440e084751b28c0bf0859aaed22ade4 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -27,13 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=draco\0" \ @@ -45,8 +38,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 14ba52a2eb338419d69bf48a123d728d86a1f275..c37b4c635b2740bb7084f3808586091c83c89519 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -18,15 +18,8 @@ /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* UART */ - -/* Fixup - in init code we switch from device to host mode, - * it has to be done after each HCD reset */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +/* Environment */ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 1) \ @@ -35,47 +28,6 @@ #include -/* Does what recovery does */ -#define REFLASH(file, part) \ -"part start mmc 0 "#part" start && "\ -"part size mmc 0 "#part" size && "\ -"tftp $loadaddr "#file" && " \ -"mmc write $loadaddr $start $size && " - -#define CONFIG_ENV_REFLASH \ -"mmc dev 0 && "\ -"usb start && "\ -"dhcp && "\ -"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\ -"mmc write $loadaddr 0 43 && " \ -"mmc rescan && "\ -REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\ -REFLASH(dragonboard/rescue/sbl1.mbn, 2)\ -REFLASH(dragonboard/rescue/rpm.mbn, 3)\ -REFLASH(dragonboard/rescue/tz.mbn, 4)\ -REFLASH(dragonboard/rescue/hyp.mbn, 5)\ -REFLASH(dragonboard/rescue/sec.dat, 6)\ -REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\ -REFLASH(dragonboard/u-boot.img, 8)\ -"usb stop &&"\ -"echo Reflash completed" - -/* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "reflash="CONFIG_ENV_REFLASH"\0"\ - "loadaddr=0x81000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "linux_image=Image\0" \ - "kernel_addr_r=0x81000000\0"\ - "fdtfile=qcom/apq8016-sbc.dtb\0" \ - "fdt_addr_r=0x83000000\0"\ - "ramdisk_addr_r=0x84000000\0"\ - "scriptaddr=0x90000000\0"\ - "pxefile_addr_r=0x90100000\0"\ - BOOTENV - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV #endif diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 1e2b15b33f9fd39c1c9305fc6ceb630315fe53a2..1fa5d05e7b473d4496b80a611ccfcc7506fa0b93 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -20,12 +20,8 @@ #define PHYS_SDRAM_2_SIZE 0x5ea4ffff #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#ifndef CONFIG_SPL_BUILD #include -#endif #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -43,8 +39,4 @@ "pxefile_addr_r=0x90100000\0"\ BOOTENV -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 - #endif diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 07e2b8781fd205a4f74f99ada7c4d2f788365db3..fbd83d629c0285d6d23a74fef23f0a4e945bea6d 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -30,9 +30,4 @@ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 -/* - * SATA Driver configuration - */ -#define CONFIG_LBA48 - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index dbccd46bbdb15d303214a77f4819ef0270f9f037..f8273a92f11a315b99276a3667bf38580c63d86c 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -19,11 +19,6 @@ /* I2C */ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -45,17 +40,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Default Environment */ diff --git a/include/configs/durian.h b/include/configs/durian.h index f0789d5fb3ad85f429a566ba8ea6ae91e1491d31..8f0e8be433073b5be64e4a15317e6a14e0caa789 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -13,13 +13,7 @@ #define PHYS_SDRAM_1_SIZE 0x7B000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) - -/* PCI CONFIG */ -#define CONFIG_PCI_SCAN_SHOW - /* BOOT */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS \ "load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index 2d0e7878799028d535b0b23b2220de486416dc27..1d655292d7efd8908493f1648655e4ab5f614b19 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -18,7 +18,6 @@ /* * cmd */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) /* * SoC-specific config diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 28bf35ca9889ab9fa89310a56de774bc3f778001..6e444c478922c9261a2adcdc6629da88ded6d3cb 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -29,9 +29,6 @@ * Environment is in the second sector of the first 256k of flash * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*#define CONFIG_SYS_DRAM_TEST 1 */ #undef CONFIG_SYS_DRAM_TEST @@ -50,7 +47,6 @@ *----------------------------------------------------------------------*/ #ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_OVERWRITE_ETHADDR_ONCE #endif @@ -68,9 +64,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -84,7 +77,6 @@ #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data @@ -106,7 +98,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 3adc4180efd9b33c9cb0ca7009017c0c2c910d1a..3dc111f5248d419d988e5332c712d5fac55722da 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -18,7 +18,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/edison.h b/include/configs/edison.h index 70cccc6fe6b22159d264c594f7f8354d1e6a8c51..34536ecf85057ac5ff196b79a4bc346af3082fc0 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -10,10 +10,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 128 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_LEN (256 * 1024) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 8e2c24594fab7e31445a4dfbed8891e0d109a3dc..86257016824fc11f2a56d58e75ae4e0f52eab210 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -15,12 +15,6 @@ * SPL */ -#define CONFIG_SPL_MAX_SIZE 0x0000fff0 -#define CONFIG_SPL_STACK 0x00020000 -#define CONFIG_SPL_BSS_START_ADDR 0x00020000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff -#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff #define CONFIG_SYS_UBOOT_BASE 0xfff90000 #define CONFIG_SYS_UBOOT_START 0x00800000 @@ -90,8 +84,6 @@ /* auto boot */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Network */ @@ -109,8 +101,6 @@ #define __io /* Data, registers and alternate blocks are at the same offset */ /* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 /* A single bus, a single device */ /* ATA registers base is at SATA controller base */ /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ @@ -141,7 +131,5 @@ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) #endif /* _CONFIG_EDMINIV2_H */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bcd7b84cf3828d833824f9f677fcc0ba9d99f177..7fc3459ef2952bc32dfe0c087163dd17bae1f04d 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -58,11 +58,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #endif /* __EL6Q_COMMON_CONFIG_H */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 1bf564c360656909c72090e15ac6c273ec603d5e..7526d3b0f515c1c66308fec45496fbfa5e915be5 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -32,11 +31,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #if defined(CONFIG_ENV_IS_IN_MMC) @@ -58,12 +52,6 @@ #ifdef CONFIG_SPL #include "imx6_spl.h" /* RiOTboard */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb" - -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */ #endif diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index a560673512e6b7f8bd44d389e4b2606931760092..60fab0419f5da7f61d54cf2959cc8890d7067a96 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -11,8 +11,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x10000000 #define CONFIG_SYS_SDRAM_SIZE SZ_16M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) - /* * Environment */ diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index d936b7f09fcd99866cca6c4f98912e0c9b825a18..2f067a4424824b051e5e325ec0d3d5cc269cfcb9 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,11 +10,7 @@ #include -#define CONFIG_ESPRESSO7420 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SPL_STACK CONFIG_IRAM_END -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 9cf93924df938ac1503bbaac7115ef411dd647ce..3acc62d9e178649b4d922afe65c5b2e4d3655e33 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -75,20 +75,8 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* use both define to compile a SPL compliance test */ -/* -#define CONFIG_SPL_CMT -#define CONFIG_SPL_CMT_DEBUG -*/ - /* nedded by compliance test in read mode */ -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - - #undef COMMON_ENV_DFU_ARGS #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs};" \ @@ -113,7 +101,7 @@ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ - "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_root_fs_type=ubifs rootwait\0" \ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 3231f3cc0350e09a1fbc002b131b85f22f218f63..88a702f1af27bb99ee64d41bbe5eb79c284bb9a8 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -22,10 +22,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ /* 32kB internal SRAM */ -#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SRAM_SIZE (32 << 10) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 @@ -34,7 +32,6 @@ /* 512kB on-chip NOR flash */ # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ # define CONFIG_SYS_MAX_FLASH_SECT 32 -# define CONFIG_EFLASH_PROTSECTORS 1 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -62,17 +59,6 @@ #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) #define CONFIG_SYS_I2C_RTC_ADDR 0x51 @@ -101,11 +87,6 @@ #define I2C_DELAY udelay(100) #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) -/* DHCP/BOOTP options */ -#ifdef CONFIG_CMD_DHCP -#define CONFIG_SYS_AUTOLOAD "n" -#endif - /* File systems */ /* Boot command */ diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index 492b7b4df1281f0ed99c6c6e9cc3d689f5c558cc..b7e850370b3193ef35a2026884506bad5ad00d5c 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -15,7 +15,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index dd1cbd7ab84d40476bb9ed95079289c9f28b8e9a..246aa9b7ab99d25eb1c19c06a0a598b0e540cd77 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -8,10 +8,6 @@ #ifndef __EXYNOS_COMMON_H #define __EXYNOS_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ - #include /* get chip and board defs */ #include #include @@ -22,14 +18,6 @@ /* select serial console configuration */ -/* PWM */ -#define CONFIG_PWM - /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 4202c6261262bb86fea0d54679257a49ab13af0c..054cb5309e70f5ff8066fc3d295cbeffa95a9111 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_EXYNOS4_COMMON_H #define __CONFIG_EXYNOS4_COMMON_H -#define CONFIG_EXYNOS4 /* Exynos4 Family */ - #include "exynos-common.h" /* SD/MMC configuration */ @@ -25,8 +23,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 7ab821d08ca380661ad72d9b1df144011cbe6617..44f5cb1e83f450b6aa9c93cce8242e098d321326 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -8,15 +8,8 @@ #ifndef __CONFIG_EXYNOS5_COMMON_H #define __CONFIG_EXYNOS5_COMMON_H -#define CONFIG_EXYNOS5 /* Exynos5 Family */ - #include "exynos-common.h" -#define CONFIG_EXYNOS_SPL - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -31,9 +24,6 @@ /* select serial console configuration */ #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU - /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index bcbdfa7ae35a68fc7c69005c759e2a42bfb6b59e..a94f5a15f0d13ac77048ac51f0eed437dfd9a1cc 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,17 +15,8 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define CONFIG_EXYNOS5_DT - #define CONFIG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - #endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 36c3a613eb75322288d374ea16a69e00e120f48f..8e2f135f934cf05b8831bea9241c66c85dc6c8b7 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,21 +9,8 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#define CONFIG_EXYNOS5250 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - -#define CONFIG_USB_XHCI_EXYNOS - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 51f9f221742e107b50e93fdb7bc49af388131ed5..7a9307ccc3dbc7e89518d252fb311837e36470e6 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,27 +8,16 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_EXYNOS5420 - -#define CONFIG_EXYNOS5_DT - #define CONFIG_VAR_SIZE_SPL #define CONFIG_IRAM_TOP 0x02074000 -#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) - #define CONFIG_PHY_IRAM_BASE 0x02020000 -/* Address for relocating helper code (Last 4 KB of IRAM) */ -#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) - /* * Low Power settings */ #define CONFIG_LOWPOWER_FLAG 0x02020028 #define CONFIG_LOWPOWER_ADDR 0x0202002C -#define CONFIG_USB_XHCI_EXYNOS - #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 5658da474cbf7795304e206c68c47fe9aeb2e72d..a8bef860c2f77b13dd8553161e5e54b460788a76 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -8,19 +8,10 @@ #ifndef __CONFIG_EXYNOS7420_COMMON_H #define __CONFIG_EXYNOS7420_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P - #include /* get chip and board defs */ #include /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* select serial console configuration */ diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index ec43e133dde00e6cd79427bfa71161e596bcc7b0..b05846d0b920541f59bf396f3b3da0e1bbdd77d2 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -11,19 +11,10 @@ #ifndef __CONFIG_EXYNOS78x0_COMMON_H #define __CONFIG_EXYNOS78x0_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P - #include /* get chip and board defs */ #include /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CPU_RELEASE_ADDR secondary_boot_addr @@ -31,8 +22,6 @@ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/galileo.h b/include/configs/galileo.h index c50ecf27e44c27e389e0378ebbfefd28d23a8621..49f57dda58fb8a2168bb0c0eee1471f031a1cf28 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -21,9 +21,6 @@ "stdout=serial\0" \ "stderr=serial\0" -/* 10/100M Ethernet support */ -#define CONFIG_DW_ALTDESCRIPTOR - /* Environment configuration */ #endif /* __CONFIG_H */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 5e6a8ee770e055b58177ef808b51288a957443cf..331e9ca8ba19b1ef6db193c1e29abe806bb8657b 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -21,9 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -36,13 +33,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x7000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) @@ -51,12 +41,8 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SPL_NAND_RAW_ONLY #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 269bb93272c5878b4a61afbc9833fb03e7fb4f0a..d21a9b9383ad4ff2b1cd1d3ddfc7a4761fec7d5c 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -17,10 +17,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -39,11 +35,6 @@ /* RAM */ -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - /* Environment settings */ #endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 6b910d55193490ef3fce2f929b1931d99d7d5100..25095e192f0bcf66fb73cf04b9f1e0e0f8d058d4 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -33,8 +33,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * FLASH on the Local Bus @@ -58,13 +56,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * For booting Linux, the board info and command line data * have to be in the first 256 MB of memory, since this is diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index b4f94992e64621a62b64a71709fc5772ecd2c1a1..95ba20c686ba3f1001be4088ec89abbfc628fb73 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -13,7 +13,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000 @@ -30,10 +29,8 @@ #endif /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #define CONFIG_USBD_HS /* Video */ @@ -47,11 +44,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Command definition */ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=/boot/fitImage\0" \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index c80a07655ecd8b7a2d110bc99f35d57eba99393e..ad00769bdeefaab22027b089c1214207ece934c6 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -17,13 +17,6 @@ #include "mx6_common.h" #include -/* SATA Configs */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ @@ -105,11 +98,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -121,7 +109,4 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 832441a7b72155ed85b46e9b028e9310c93a5e64..66eed9e14f819601f7eb43f686daaf884087251a 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -33,8 +33,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" @@ -44,7 +42,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* SATA driver configuration */ -#define CONFIG_LBA48 - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 4ffa5bea8f83047011ee8181d924f8dfdac4d1ca..d1fe375a2c1f950bb3410c0b8a507c8fcb319ab4 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -10,10 +10,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -33,8 +32,4 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 - #endif /* __GOSE_H */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 347845f1d501d49d8ea69132e66d95e644e5d848..fb69716bcbf4307b84a77b2d79d018cc4477499c 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -11,13 +11,10 @@ /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ /* Miscellaneous */ -#define CONFIG_SYS_PBSIZE 256 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) diff --git a/include/configs/gru.h b/include/configs/gru.h index b1084bb21d4da8f8afa8222c325b9f1d30a12fed..be2dc79968c042bf085da782e39cb8c51417dfc3 100644 --- a/include/configs/gru.h +++ b/include/configs/gru.h @@ -13,7 +13,4 @@ #include -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index d5655e4ada69cbccf4d5f6ba5274cc3a9ed5185d..4954c5ca0800902297b1dd891d06892b026aced9 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -26,7 +26,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/guruplug-server-plus.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 86d0fb60f1d59357c7d5842b00e16ab02e266ea5..82076ff74ff691c0a89b9f845121fa5b72f16b03 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -10,14 +10,8 @@ /* Location in NAND to read U-Boot from */ /* Falcon Mode */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - NAND support: args@17MB kernel@18MB */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M) /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" @@ -28,27 +22,12 @@ /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#undef CONFIG_SYS_BOOTM_LEN -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR - #define CONFIG_LBA48 -#endif - /* * PCI express */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX -#endif /* * PMIC @@ -61,7 +40,6 @@ /* Various command support */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS @@ -82,11 +60,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * MTD Command for mtdparts */ @@ -97,154 +70,4 @@ #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.146 -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "usb_pgood_delay=2000\0" \ - "console=ttymxc1\0" \ - "bootdevs=usb mmc sata flash\0" \ - "hwconfig=_UNKNOWN_\0" \ - "video=\0" \ - \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "disk=0\0" \ - "part=1\0" \ - \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x18000000\0" \ - "initrd_high=0xffffffff\0" \ - "fixfdt=" \ - "fdt addr ${fdt_addr}\0" \ - "bootdir=boot\0" \ - "loadfdt=" \ - "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ - "run fixfdt; " \ - "fi\0" \ - \ - "fs=ext4\0" \ - "script=6x_bootscript-ventana\0" \ - "loadscript=" \ - "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ - "source ${loadaddr}; " \ - "fi\0" \ - \ - "uimage=uImage\0" \ - "mmc_root=mmcblk0p1\0" \ - "mmc_boot=" \ - "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ - "mmc dev ${disk} && mmc rescan && " \ - "setenv dtype mmc; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${mmc_root} rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - \ - "sata_boot=" \ - "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \ - "sata init && " \ - "setenv dtype sata; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - "usb_boot=" \ - "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \ - "usb start && usb dev ${disk} && " \ - "setenv dtype usb; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" - -#ifdef CONFIG_SPI_FLASH - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ - "image_uboot=ventana/u-boot_spi.imx\0" \ - \ - "spi_koffset=0x90000\0" \ - "spi_klen=0x200000\0" \ - \ - "spi_updateuboot=echo Updating uboot from " \ - "${serverip}:${image_uboot}...; " \ - "tftpboot ${loadaddr} ${image_uboot} && " \ - "sf probe && sf erase 0 80000 && " \ - "sf write ${loadaddr} 400 ${filesize}\0" \ - "spi_update=echo Updating OS from ${serverip}:${image_os} " \ - "to ${spi_koffset} ...; " \ - "tftp ${loadaddr} ${image_os} && " \ - "sf probe && " \ - "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ - \ - "flash_boot=" \ - "if sf probe && " \ - "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mtdblock3 " \ - "rootfstype=squashfs,jffs2 " \ - "${video} ${extra}; " \ - "bootm; " \ - "fi\0" -#else - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ - "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ - "tftp ${loadaddr} ${image_rootfs} && " \ - "nand erase.part rootfs && " \ - "nand write ${loadaddr} rootfs ${filesize}\0" \ - \ - "flash_boot=" \ - "setenv fsload 'ubifsload'; " \ - "ubi part rootfs; " \ - "if ubi check boot; then " \ - "ubifsmount ubi0:boot; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=squashfs,ubifs; " \ - "setenv bootdir; " \ - "elif ubi check rootfs; then " \ - "ubifsmount ubi0:rootfs; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs; " \ - "fi; " \ - "setenv dtype nand; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=${root} ${video} ${extra}; " \ - "if run loadfdt; then " \ - "ubifsumount; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "ubifsumount; bootm; " \ - "fi; " \ - "fi\0" -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/gxp.h b/include/configs/gxp.h new file mode 100644 index 0000000000000000000000000000000000000000..e3c97b20d51ef1efddbfefaf9efdde8d4e76c36f --- /dev/null +++ b/include/configs/gxp.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * GXP board + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins + * Author: Jean-Marie Verdun + */ + +#ifndef _GXP_H_ +#define _GXP_H_ + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#endif diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 151ab66f4c3f12fa2aa358d94e5f729e599c2556..fc32487e1c7b4a6fd5590d4ac4a18785dbbf2b87 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -18,8 +18,6 @@ * U-Boot into it. */ -#define CONFIG_ENV_MIN_ENTRIES 128 - /* Environment in MMC */ /* * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC @@ -30,39 +28,11 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) -/* SPL related MMC defines */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -70,8 +40,6 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) #else @@ -149,6 +117,4 @@ "console=ttyS0,115200\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif /* _CONFIG_HELIOS4_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 0ff70fdc668bd626a2002824009c1c03427e082b..bb6cc957261a82a6ee15eaf6a637b8264169244d 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,15 +14,9 @@ #define CONFIG_PL011_CLOCK 150000000 -#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_64BIT_LBA /* Environment data setup */ @@ -30,7 +24,6 @@ #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x01000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 19d5b6261f105ab98b4337a5cbf34144f2e5d034..5be6eb4e766c5000d063d6ddf542a36fa7c1ec99 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -15,8 +15,6 @@ #define CONFIG_POWER_HI6553 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -30,8 +28,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 @@ -61,8 +57,4 @@ /* Preserve environment on eMMC */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #endif /* __HIKEY_H */ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index c088f2f2b6913b6ce739c92d503516c099bb7603..ad070439d002d2635716a4745f0692c03f8288a4 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -9,8 +9,6 @@ #include -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ @@ -22,8 +20,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xe82b1000 #define GICC_BASE 0xe82b2000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index d3d8896ecff1b1b72d45b121efd47bac4dc3fcd4..4af845ea9c2d48b5df1ee01de4a4634d00cdf7f6 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -25,11 +25,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -41,12 +36,6 @@ * Ethernet PHY configuration */ -/* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - /* * Environment settings */ @@ -105,7 +94,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" */ /* Cli configuration */ -#define CONFIG_SYS_CBSIZE SZ_2K /* * Callback configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 64dce521056a586a4fa3fb1f8da274fce378dd17..0ce65e7755eaead298a4e1ff38b7921db59fae70 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -40,12 +35,6 @@ * Ethernet PHY configuration */ -/* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - /* * Environment settings */ @@ -100,7 +89,6 @@ setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" /* Cli configuration */ -#define CONFIG_SYS_CBSIZE SZ_2K /* * Callback configuration diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index aff948cfe70819be8fe97d132dab43740cbfa18e..05192218d2253977cd080af415570281bcd00791 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -20,8 +20,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index cb4cf9beb7409b2d9fc4108f1ccbf8692c1bb815..f2e3608d3a3fe6ab2daabe8b3788509791f87cf9 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -13,8 +13,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 356bf6c636d1caf22b24dc65193d14297e81a285..a8bb2090ec4a227ce3e1841c5302f92c4345f543 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -28,10 +28,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Internal Definitions @@ -108,7 +104,6 @@ /* * NOR FLASH setup */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_FLASH_SHOW_PROGRESS 50 #define CONFIG_SYS_FLASH_BASE 0xFF800000 @@ -169,7 +164,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x3 #define TSEC2_FLAGS TSEC_GIGABIT #define TSEC2_PHYIDX 0 @@ -187,7 +181,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) -#define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3 /* @@ -216,8 +209,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_LOADS_ECHO #undef CONFIG_SYS_LOADS_BAUD_CHANGE @@ -252,8 +243,6 @@ "${netmask}:${hostname}:${netdev}:off " \ "console=${console},${baudrate} ${othbootargs}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "\0" /* UBI Support */ diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index edd24a4b556ce9704eddb73f4c6408f7819ff8c2..599b0c50defe64a7cb0277242cfcb0b85b90672d 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -25,8 +25,6 @@ /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) /*---------------------------------------------------------------------- * Commands @@ -35,7 +33,6 @@ /*------------------------------------------------------------ * Console Configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* ------------------------------------------------- * Environment diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 6790053bb8d0847b58212522131413e3f57fc47f..17430f15d139292532ddbc2b1e20d9ee0ace38cd 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -106,10 +106,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -136,11 +132,7 @@ " +${filesize};cp.b ${fileaddr} " \ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 26d7a88ebde82958245acc1726be15dc7ae2cbcb..a2d5080a10e424cd1e5a7c05bcc4bc52859308c8 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -113,11 +113,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - /* UART */ #ifdef CONFIG_MXC_UART # ifdef CONFIG_MX6UL @@ -140,13 +135,7 @@ /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT -# define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -# define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -# define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - /* MMC support: args@1MB kernel@2MB */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif /* Framebuffer */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 65f8944ccaf67d06f53b9d00f9d9682ef7e523c0..2913549c88354156ffc07615d6a874e3e4fd7583 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -113,34 +113,21 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif /* __IMX6LOGIC_CONFIG_H */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 234aacb3b9143267f51cae9946a1cadf7184e79e..488b2f1696a9af79a62688d6116e356fc92ea2f2 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -8,51 +8,6 @@ #ifdef CONFIG_SPL -#ifdef CONFIG_MX6_OCRAM_256KB -/* - * see Figure 8.4.1 in IMX6DQ Reference manuals: - * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF - * - BOOT ROM stack is at 0x0093FFB8 - * - if icache/dcache is enabled (eFuse/strapping controlled) then the - * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to - * fit between 0x00907000 and 0x00938000. - * - Additionally the BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 - * or 192KB - */ -#define CONFIG_SPL_MAX_SIZE 0x30000 -#define CONFIG_SPL_STACK 0x0093FFB8 -/* - * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x31000 -#else -/* - * see Figure 8-3 in IMX6SDL Reference manuals: - * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF - * - BOOT ROM stack is at 0x0091FFB8 - * - if icache/dcache is enabled (eFuse/strapping controlled) then the - * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to - * fit between 0x00907000 and 0x00918000. - * - Additionally the BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 - * or 64KB - */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_STACK 0x0091FFB8 -/* - * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x11000 - -#endif - /* MMC support */ #if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ @@ -60,31 +15,9 @@ /* SATA support */ #if defined(CONFIG_SPL_SATA) -#define CONFIG_SPL_SATA_BOOT_DEVICE 0 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 #endif -/* Define the payload for FAT/EXT support */ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -# ifdef CONFIG_OF_CONTROL -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif -#endif - -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_SPL_BSS_START_ADDR 0x88200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#else -#define CONFIG_SPL_BSS_START_ADDR 0x18200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#endif #endif #endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index ba79e1bccfa839b22ef9f9ad25915a74cebf7e0c..909453cd66f416ee2530f36f4946a1a9626f8b83 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -20,7 +20,6 @@ /* Environment in MMC */ #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x14000000\0" \ "fdt_addr_r=0x13000000\0" \ @@ -34,7 +33,6 @@ func(MMC, mmc, 2) #include -#endif /* UART */ #define CONFIG_MXC_UART_BASE UART3_BASE @@ -45,19 +43,12 @@ #define CONFIG_FEC_MXC_PHYADDR 1 /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Falcon */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 /* MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) /* Miscellaneous configurable options */ @@ -68,11 +59,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - /* SPL */ #include "imx6_spl.h" diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 6d362557ac61f22883e184d8ea95433b15b967a0..201684ba802cae6a374f93ad1eaa8fdd5f9356ad 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -89,9 +89,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* SPL */ #ifdef CONFIG_SPL #include "imx6_spl.h" @@ -114,9 +111,7 @@ #endif #endif -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 2d9f8bb510b87c410d1ce82631c01a26e829bbb9..f0f800b8409bd291e3d1e4fbeb1ec013705925e8 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,7 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -#undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS /* @@ -74,11 +73,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index 128f612392fafab27d46d5cfef6636422d3fb477..5900c05db1fbd2690bb3122bf38cc28aa7fadc28 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -11,52 +11,12 @@ #define __IMX7_SPL_CONFIG_H #ifdef CONFIG_SPL -/* - * see figure 6-22 in i.MX 7Dual/Solo Reference manuals: - * - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to - * 0x00946C00. - * - Set the stack at the end of the free area section, at 0x00946BB8. - * - The BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding. However, the manual also states that the ROM uses the - * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use - * this range for stack and malloc, the SPL itself must fit below 0x920000, - * or the image will be truncated in at least some boot modes like USB SDP. - * Thus our max size is really 0x00920000 - 0x00912000. If necessary, - * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space - * for the SPL, but 56KB should be more than enough for the SPL. - */ -#define CONFIG_SPL_MAX_SIZE 0xE000 -#define CONFIG_SPL_STACK 0x00946BB8 -/* - * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding) - * The extra padding could be removed, but this value was used historically - * based on an incorrect CONFIG_SPL_MAX_SIZE definition. - * This allows to write the SPL/U-Boot combination generated with - * u-boot-with-spl.imx directly to a boot media (given that boot media specific - * offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x11000 /* MMC support */ #if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #endif -/* Define the payload for FAT/EXT support */ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -# ifdef CONFIG_OF_CONTROL -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif -#endif - -#define CONFIG_SPL_BSS_START_ADDR 0x88200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - #endif /* CONFIG_SPL */ #endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 8d9212ec64c99803f51ec5bd4ae12cd5459bd098..c69f2fa19f3057f61c2701477ca52e059bb079fa 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,23 +11,14 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif @@ -135,25 +126,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -162,8 +140,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 573ddaf29526a8b651d603977cb8a7e4481bcbd9..79ed397122502eac2a62625e02e7a3daba4426da 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,22 +9,14 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif @@ -82,21 +74,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) #endif diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 419258f949a7abf2ea800204eb6b027a9416a4bf..a5b7e9f5b6455a5cff297743e6ee713f8a04b65c 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -10,43 +10,24 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN SZ_128M - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_1M -#define CONFIG_SPL_STACK 0x920000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 kiB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */ - #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 @@ -55,8 +36,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ "bootlimit=3\0" \ @@ -102,5 +81,3 @@ "fi" #endif - -#endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 5e8f19c43fb63ca959a80463c6506d5fc95f4a49..5e9e3e800d8f5920a10aaf9f54135e884a6e2799 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -10,34 +10,23 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -58,25 +47,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_FEC_MXC_PHYADDR 0 #endif diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index b9b24a8c51df50b835414fc8120c27e46c548d92..6b7f3af53a2163caee0678644af9c8e4bd267f3a 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,32 +10,20 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -# define CONFIG_SPL_STACK 0x920000 -# define CONFIG_SPL_BSS_START_ADDR 0x910000 -# define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -# define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -# define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ # define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -# define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) #include -#else -#define BOOTENV -#endif #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x44000000\0" \ @@ -53,27 +41,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 9836d5b73caf876b3538791dd56d505b72eddf4d..13015604509134b0a9049fc6ac077f0ec27f897e 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,22 +9,14 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif @@ -36,7 +28,6 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -44,9 +35,6 @@ func(USB, usb, 1) \ func(DHCP, dhcp, na) #include -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -89,26 +77,15 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +/* FEC */ +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC #endif diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 79c6b1076ff32a6b439e0ddd7a05ba9b1757680a..6faecbde776da96778181d71c1e1462b808817c3 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,23 +9,15 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ @@ -94,10 +86,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -107,12 +95,4 @@ #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ #endif -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) #endif diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index d09c2ab01610feadfaa060fb75dbc02f9effc51c..c6b296281424f22d690691b3144e39d0313f6e2b 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -14,15 +14,13 @@ #include #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs " \ + "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "mtdparts=${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:root rw ubi.mtd=nandrootfs\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdt_addr_r} nanddtb; " \ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2dadf1605cbac0332a2b7e1d324e7fe1..a371c5b3832c0f49152a41bf420d710344f09446 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,21 +10,10 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - - - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ @@ -37,23 +26,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* I2C */ - #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 805ae2a7518990740115ce6480a89126786cb5a4..ae7fcb1027a0a4feec045db6167384f7cbfe37fa 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,33 +10,16 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#endif - -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ /* see include/configs/ti_armv7_common.h */ @@ -65,23 +48,10 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 00358892b2840764b388ab5728289b73101ac97d..c8604e0de592f5e93d06c085dc1a3b9984ad7fb9 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,19 +10,10 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -55,24 +46,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* USDHC */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 3cbe11a9035ab1c8bc9ecfb3173ca378fa71b2cf..c43c4da6fbf8d4731b8dec7669ea2b5d94eb88be 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,20 +9,12 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ @@ -33,16 +25,12 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -85,26 +73,15 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +/* FEC */ +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC #endif diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 7d5403fa9f499c095d6c70af7998813538e4fff1..4b4731c3035bd7d71023b627c46de4333a4b4000 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -10,30 +10,11 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN SZ_128M - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_1M -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x96FC00 -#define CONFIG_SPL_BSS_START_ADDR 0x0096FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KiB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x4c000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 kiB */ - -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#endif - /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -41,13 +22,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 #define FEC_QUIRK_ENET_MAC @@ -56,8 +30,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ @@ -109,5 +81,3 @@ #include #endif - -#endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1e7c44c42a42feffd793362e3d4a588bc6d768d5..5581c0fac024ffc785ae277bc7ec0176ea25b47d 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,21 +10,12 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 @@ -39,13 +30,11 @@ #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -66,10 +55,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Totally 6GB DDR */ @@ -79,13 +64,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 52e8ea8f86af606dfba023447661cfcf03d202f2..17e00f958b6c65168fdfc64815ab42a0119660aa 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,9 +12,6 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) @@ -28,18 +25,11 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #if defined(CONFIG_NAND_BOOT) #define CONFIG_SPL_NAND_MXS @@ -149,10 +139,6 @@ /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Totally 6GB or 4G DDR */ @@ -168,12 +154,7 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 4120e4cc6bad9baef20c68f3f8d3f3698f98be0e..9f4c1b161f7a502b127a308657e7dc41f22d2015 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,20 +9,12 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ @@ -33,16 +25,12 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -85,27 +73,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) /* FEC */ #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 6eecfc813a4337433410731e9b3a73e536e20c6f..ab74d5b26b6fd3a3ad40903fc856705fb489031b 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -10,37 +10,26 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ /* ENET1 */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -61,10 +50,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -73,13 +58,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index e31f4135ae5607b9b98e679a1090cbb96cc13d6c..ea4305667f244461015bab20f5768019742c4804 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,24 +10,15 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 @@ -39,14 +30,12 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -67,10 +56,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -79,13 +64,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 57e45b0447cc0434a0ccce61a00d61a69ecb8bad..97bd5044501f6dafeb77afff5f2ab9a7a74b0ea8 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -9,22 +9,15 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (172 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ @@ -95,10 +88,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -107,13 +96,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 61d56e269ac49a5f846b50c879510752466db5df..5f9d06e0f6f4bff7b2b17ef9331e9069c122a709 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -10,23 +10,12 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) - #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #ifdef CONFIG_AHAB_BOOT @@ -112,8 +101,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* Default environment is in SD */ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 81ab5d8caa5723eaa251573b1bc0937d3c0a4e49..308f17fd59597a70b59f6a6c5b3b45b6c13affaa 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -10,18 +10,12 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (124 * 1024) -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ - #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 #define USDHC3_BASE_ADDR 0x5B030000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* FUSE command */ /* Boot M4 */ @@ -108,8 +102,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND, * USDHC2 is for SD, USDHC3 is for SD on base board diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 26dc4ded0303535025c7d0b9b477c4b5f5803119..f8ec16ebb197bbfa9c1fc38a29b419b808353053 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -11,20 +11,11 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #ifdef CONFIG_AHAB_BOOT @@ -110,8 +101,6 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - /* Default environment is in SD */ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ @@ -128,8 +117,5 @@ #endif /* Misc configuration */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 05df43b39b45198a25787d7dfc87bbc7cf371ade..ebfc166b4d46810b48a633186e6d3cd9cde9032e 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,21 +9,12 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (SZ_64M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x22050000 -#define CONFIG_SPL_BSS_START_ADDR 0x22048000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x22040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */ - #define CONFIG_MALLOC_F_ADDR 0x22040000 -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ #endif @@ -62,20 +53,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_RBASE #endif diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index 79feab389e322fa739cde0a39adfa8bec5db992b..a2c004880a7e64e911c27693d61eceaa545c6466 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -9,8 +9,6 @@ #include -#define CONFIG_SYS_INIT_SP_ADDR 0x20240000 - #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 #define PHYS_SDRAM 0x80000000 @@ -24,12 +22,6 @@ * Configuration of the external SDRAM memory */ -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_LEN 0x00008000 #define CONFIG_SYS_UBOOT_START 0x800023FD -#endif -/* For SPL ends */ #endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 5c2f975ba7f0acaa3fbd1b4bab66e75e1b71fcff..e36718dc825b7c672b4c7b20b4bb25cedcec9e7d 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -9,8 +9,6 @@ #include -#define CONFIG_SYS_INIT_SP_ADDR 0x20280000 - #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 #define PHYS_SDRAM 0x80000000 @@ -31,12 +29,6 @@ * Configuration of the external SDRAM memory */ -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_LEN 0x00008000 #define CONFIG_SYS_UBOOT_START 0x800023FD -#endif -/* For SPL ends */ #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index d578b02460518b24b84e454a152f07788242b538..34eec5a33d258ceef6bb8dd97ad3255fc6c64dda 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -31,11 +31,6 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET /* * FLASH and environment organization diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 91ed76bb40b6382cee8a1b384a4d90c22c854cd8..0f6150fc9c7edd1fa448559e28ad6bc6983e128a 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -14,19 +14,11 @@ #include /* SPL Loader Configuration */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* U-Boot general configuration */ #define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ "usb_pgood_delay=900\0" -#ifndef CONFIG_SPL_BUILD - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) \ func(USB, usb, 0) \ @@ -48,8 +40,6 @@ #include -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ BOOTENV \ diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index 56a67f2891471089db74286c9e3baae86a4b065f..a2e50c3b8df2a436f016b4f2d0688cdd91d1f0ad 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -30,12 +30,12 @@ * : : | * : : CONFIG_SYS_MALLOC_LEN * : : - * : Specified explicitly by CONFIG_SYS_INIT_SP_ADDR + * : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR * : * Specified explicitly by CONFIG_SYS_SDRAM_BASE * * NOTES: - * - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down, + * - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down, * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on * stack any longer and values popped from stack will contain garbage @@ -53,16 +53,12 @@ #define CONFIG_SYS_SDRAM_BASE DCCM_BASE #define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_BOOTM_LEN SZ_128K - #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K -#define RAM_DATA_BASE CONFIG_SYS_INIT_SP_ADDR +#define RAM_DATA_BASE SYS_INIT_SP_ADDR #define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ - (CONFIG_SYS_INIT_SP_ADDR - \ + (SYS_INIT_SP_ADDR - \ CONFIG_SYS_SDRAM_BASE) - \ CONFIG_SYS_MALLOC_LEN - \ CONFIG_ENV_SIZE diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 2590ee6b01401c28d74eb9ee6e21dde3083c44b5..9f54f259994a94fc2f252f52ec7ea5c624cd3884 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -17,46 +17,17 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 +/* FLASH Configuration */ +#define CONFIG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else #define CONFIG_SYS_UBOOT_BASE 0x50080000 -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -/* Image load address in RAM for DFU boot*/ -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* HyperFlash related configuration */ /* U-Boot general configuration */ @@ -178,14 +149,6 @@ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_OSPI -#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD -#endif - #if CONFIG_IS_ENABLED(CMD_PXE) # define BOOT_TARGET_PXE(func) func(PXE, pxe, na) #else @@ -216,7 +179,6 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ BOOTENV diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index a5505f079b43a3f34330d05e717ad0d528a13b0d..932d7d3c8cb56952fa2599c084f9d2258014be66 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -21,43 +21,12 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else #define CONFIG_SYS_UBOOT_BASE 0x50080000 -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (0x41c80000 -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -/* Image load address in RAM for DFU boot*/ -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* U-Boot general configuration */ #define EXTRA_ENV_J721S2_BOARD_SETTINGS \ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ @@ -157,14 +126,6 @@ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_OSPI -#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD -#endif - /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -175,7 +136,6 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY /* Now for the remaining common defines */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 85cf516e1627b19c4cc22a42a8ee352f12a6bc91..1bfc89bf44ca9f4b8c61c39e67901e04bf3ef6a7 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -12,15 +12,6 @@ /* * Miscellaneous configurable options */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_HUSH_INIT_VAR #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -180,8 +171,6 @@ "init=/sbin/init-overlay.sh\0" \ "load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index e1c161586b4fc4ca77edab70d5c51a25a596412d..9f76f48a5c6bc32532713d829c19e941663ad18b 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -25,10 +25,6 @@ */ #define CONFIG_SYS_FLASH_BASE 0xF0000000 -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - /* Reserve 768 kB for Mon */ #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -38,8 +34,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* * Init Local Bus Memory Controller: * @@ -83,10 +77,6 @@ * Environment */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif /* CFG_SYS_RAMBOOT */ - /* * Environment Configuration */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index a9a6a41f6b782d221ef3f00f9744c32dfb7ec298..6becd7cd31a85ff25184921d58fc4108b698afa2 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE /* Increase max size of compressed kernel */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ /****************************************************************************** * (PRAM usage) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index a485c3ac6d1d3f00ebf684e86531768a3a389d76..eee71db37c2bfaa5947d3af33cf5e410ef2e83e4 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -25,7 +25,6 @@ #include "keymile-common.h" /* Increase max size of compressed kernel */ -#define CONFIG_SYS_BOOTM_LEN (32 << 20) #include "asm/arch/config.h" diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index dca5589a3ef457f87732df68777ffff4ca669b0d..f83739013507938958819bc59cef60486422a749 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ @@ -174,7 +173,6 @@ {1, {I2C_NULL_HOP} }, \ } -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -187,15 +185,8 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* * Environment */ @@ -258,7 +249,6 @@ "ethrotate=no\0" \ "" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index e58a69501b3327673648840b43c6d56207ba021b..01482d5319969444c341523f747f9e621f9f6506 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -23,7 +23,6 @@ /* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_HOSTNAME "km_kirkwood" -#define CONFIG_KM_DISABLE_PCIE /* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) @@ -34,7 +33,6 @@ /* KM_KIRKWOOD_128M16 */ #elif defined(CONFIG_KM_KIRKWOOD_128M16) #define CONFIG_HOSTNAME "km_kirkwood_128m16" -#define CONFIG_KM_DISABLE_PCIE /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) @@ -44,7 +42,6 @@ /* KMCOGE5UN */ #elif defined(CONFIG_KM_COGE5UN) #define CONFIG_HOSTNAME "kmcoge5un" -#define CONFIG_KM_DISABLE_PCIE /* KM_SUSE2 */ #elif defined(CONFIG_KM_SUSE2) @@ -118,8 +115,4 @@ MVGBE_SET_MII_SPEED_TO_100) #endif -#ifdef CONFIG_KM_DISABLE_PCIE -#undef CONFIG_KIRKWOOD_PCIE_INIT -#endif - #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index dc45d16bfe1a6af3e54411c6b7b0c2d691287528..b389229b7546064d062ec3d46d4f107a40f24e74 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -133,14 +133,11 @@ #define KM_I2C_DEBLOCK_SDA 21 /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 @@ -149,11 +146,8 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - /* POST memory regions test */ #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS @@ -173,7 +167,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -339,9 +332,7 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ @@ -417,7 +408,6 @@ int get_scl(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 8f4685c271c61ef5f8fab63a43ca60d143a9a299..b9d20c9c8eb9938ef379559b561f70958918708f 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -35,12 +35,6 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -/* - * BFTIC3 on the local bus CS4 - */ -#define CONFIG_SYS_BFTIC3_BASE 0xB0000000 -#define CONFIG_SYS_BFTIC3_SIZE 256 - /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c0997aa3ddd559404dfdf0b10d80c8d3f1de64f9..736865ad80af5a96234e7ed9c1f742bcd84b433b 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -10,10 +10,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -34,7 +33,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __KOELSCH_H */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 7bc402d578e80ffe6da85ff804aa0c1a0a1cd08b..7aac5d3f5a184eb846a670e68c4cb76d0a2574f1 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -22,11 +22,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE /* Board and environment settings */ @@ -34,25 +29,19 @@ #define CONFIG_HOSTNAME "kontron-mx6ul" #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* Boot order for distro boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include -#else -#define BOOTENV -#endif /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 231571b05eb87090d6e8fa2bdb829a00688eece9..622ab5976247822e1f42b289096c82b18ecdaffd 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -22,20 +22,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) #define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* GUID for capsule updatable firmware image */ @@ -43,7 +35,6 @@ EFI_GUID(0xd488e45a, 0x4929, 0x4b55, 0x8c, 0x14, \ 0x86, 0xce, 0xa2, 0xcd, 0x66, 0x29) -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ @@ -53,19 +44,8 @@ /* Do not try to probe USB net adapters for net boot */ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START -#else -#define BOOTENV -#endif - -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x91fff0 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 1834991ac3b94d448b6d4c3f587efd01dcce1d31..d77e4b4e100999fe07f680963c243d960d19b8c6 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -7,9 +7,6 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K) /* GUID for capsule updatable firmware image */ @@ -18,17 +15,11 @@ 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PFUZE100 @@ -74,10 +65,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index c47b5940fb297ccae9310ef9f59c7e14931f4818..2373abf3e31d5951ddc269a327c8c721c23ff40c 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SL28_H -#define __SL28_H +#ifndef __SL28_CONFIG_H +#define __SL28_CONFIG_H #include #include @@ -26,7 +26,6 @@ #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 /* early stack pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) /* SMP */ #define CPU_RELEASE_ADDR secondary_boot_addr @@ -42,13 +41,7 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) /* SPL */ -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) /* GUID for capsule updatable firmware image */ @@ -87,4 +80,4 @@ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif /* __SL28_H */ +#endif /* __SL28_CONFIG_H */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 534263f62b38ef46a54cdc95730a7e0c3e7399c0..c401fd32169d2b42850d1b31ab3c6e2db990686a 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -61,7 +61,6 @@ #include /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -72,11 +71,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #endif /* __CONFIG_H_ */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 7d879477d705d4ef4211c00dbd5e8ec2a6dac531..1823a7939882d774c382a2ef1258d977efa9a63f 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -21,13 +21,10 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ @@ -88,7 +85,6 @@ func(DHCP, dhcp, na) #include -#endif /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -97,12 +93,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment */ #endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h index 75fc03f147234805ff676d8c9eb26d2fa98695fd..fea7c835fdcb19e38180079a6413d3890850d0ed 100644 --- a/include/configs/kylin_rk3036.h +++ b/include/configs/kylin_rk3036.h @@ -9,10 +9,4 @@ #include #include -#ifndef CONFIG_SPL_BUILD - -/* Store env in emmc */ - -#endif - #endif diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 7e99490e5271f5120acc9162fcf8df928cac718e..e084f87d14dda8c2341cd457516833240027d22d 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -19,11 +19,9 @@ /* NOR Flash */ #define KZM_FLASH_BASE (0x00000000) #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) -#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) #define CONFIG_SYS_MAX_FLASH_SECT (512) /* prompt */ -#define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ @@ -33,9 +31,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 0a988e2fadf2328e3e59d583ab2b6d50db3c2b9c..9b70eed46f7cd324037c809186817c1a1039e1e4 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -21,18 +21,6 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #endif -/* - * SATA Driver configuration - */ - -#ifdef CONFIG_SATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ - defined(CONFIG_NET2BIG_V2) -#endif -#endif /* CONFIG_SATA */ - /* * Enable GPI0 support */ @@ -69,7 +57,6 @@ "stderr=serial\0" \ "bootfile=uImage\0" \ "loadaddr=0x800000\0" \ - "autoload=no\0" \ "netconsole=" \ "set stdin $stdin,nc; " \ "set stdout $stdout,nc; " \ diff --git a/include/configs/lager.h b/include/configs/lager.h index a5abbaaeab1fe2561c03aa03ae5afee2b313f0f7..f3feaa539fcc8ad78681db1e3f471d8713cc9a21 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -11,10 +11,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -35,7 +34,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __LAGER_H */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 4c132c6851ac5945cb78605cf2f6a43ed25a9d19..f0ae9248af342c247aa4686d7949f0f35b7bab5d 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -41,17 +41,9 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) -/* - * I2C Configuration - */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ - /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ /* * Linux Information @@ -96,8 +88,6 @@ /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x80010000 - #include #endif /* __CONFIG_H */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 86bad6fa036340b64ddba416f4a90d3ae8b03a6d..2e077dd5161f3d0d373153eb0dfb86e2efda3d12 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -17,10 +17,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -40,11 +36,6 @@ /* RAM */ -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - /* Environment settings */ #endif /* __CONFIG_LINKIT_SMART_7688_H */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index fdea7241b024cc9bdda91a8b1f5ac82dfde3be73..a1fc056c305a321fc891ede380005dc2fbb850cb 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -94,19 +94,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* FLASH and environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 67da01f5e3ab8dea31470d8563923f1ae530b6cf..87eb10db19fd760f75f6553fc86de03eb88040fe 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,20 +10,11 @@ #include #include -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -/* CSU */ -#define CONFIG_LAYERSCAPE_NS_ACCESS - /*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 @@ -42,14 +33,12 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -68,12 +57,6 @@ "bootm $kernel_load" #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include #endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index cb79d6362fcbcd0c269ca997484d9dca22b85ff6..674bcbeb75844f24a19b9d923b515a0479681aa6 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -12,11 +12,9 @@ /* DDR */ #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) -#endif #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index a1d23b64630dbe6b94fe85f22e9abaef90d82d1d..a0ff3b897904e831278e767a327f7dccfc40b115 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -19,17 +19,11 @@ /* ENV */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b5992366cf42c3e0972657da72808197b94f5497..b124ce52620cae2dcd4522048b043ca9182b4d45 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -82,10 +82,6 @@ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ DSPI_CTAR_DT(0)) -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c57b598d70de73741889da5ee5fe704089c8fcb9..4f77acdaedec021f2fbd397e3e4c9480aff2eaca 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -36,10 +36,6 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 82ae3492a2f2605c7d9c1e69bf382f8ec40e705d..ec688741a07e9e1f80edba72efb64906e844daab 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -42,15 +42,6 @@ #define SDRAM_CFG_BI 0x00000001 #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif @@ -106,18 +97,9 @@ #define TSEC2_PHYIDX 0 #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ - #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -136,11 +118,6 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #include #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 7b79e0841a5a06caeed14edbb67e9d6d8fc4cd6b..517ade383beea973b12d094dea61c6985f99fc14 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,40 +11,18 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE @@ -323,16 +301,7 @@ #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -359,16 +328,10 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * Environment */ #include -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 09168a28e7d549f7749e38c06461c3a762055dec..2fbd495e1193fd1e6ccd70f9c348129c0433daac 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -44,16 +43,6 @@ #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #ifdef CONFIG_U_BOOT_HDR_SIZE /* * HDR would be appended at end of image and copied to DDR along @@ -91,14 +80,7 @@ #define FSL_QSPI_FLASH_NUM 2 /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 @@ -176,21 +158,8 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment */ -#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ - #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b36c8dccf172f35f9c179a61fd73311175e3a938..1aa29e541ec5bb73a8db02c97ca805e34a23be11 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -46,16 +46,6 @@ #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #ifdef CONFIG_U_BOOT_HDR_SIZE /* * HDR would be appended at end of image and copied to DDR along @@ -181,16 +171,7 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -338,16 +319,10 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * Environment */ #include -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index a98d8dd7200fd87112a1b70451b67a8cbd76d631..b104524becb1454e2483ec02d5f7e2c6510f1fee 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -11,7 +11,6 @@ #include /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL @@ -58,16 +57,6 @@ "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ "env exists secureboot && esbc_halt;" -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #define OCRAM_NONSECURE_SIZE 0x00010000 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 35363ccda1aa60965e60e43719d50fccc1d0c220..253911518669f723bd5463ce3a404c6d5811d154 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -60,7 +60,6 @@ /* SATA */ -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 #ifndef SPL_NO_ENV #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -88,7 +87,6 @@ "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1028aqds_boot.scr\0" \ "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 91223789b83974403f69faffd530a9ffd4cf2f28..e7b2543b7301865dadc48706ff57b318924f6542 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -53,7 +53,6 @@ #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 /* Initial environment variables */ #ifndef SPL_NO_ENV @@ -83,7 +82,6 @@ "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1028ardb_boot.scr\0" \ "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 26db8ffe7e28b1e0bdc3cd4a2e0db498b5dc4ebb..95cbcb036eb83183bf74810573997bcd5168224e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -30,11 +30,6 @@ #include /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -51,17 +46,6 @@ /* SD boot SPL */ #ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_MAX_SIZE 0x17000 -#define CONFIG_SPL_STACK 0x1001e000 -#define CONFIG_SPL_PAD_TO 0x1d000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* @@ -78,15 +62,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PBL_PAD -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) @@ -131,17 +108,6 @@ /* I2C */ -/* PCIe */ -#ifndef SPL_NO_PCIE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif -#endif - /* DSPI */ /* FMan ucode */ @@ -160,13 +126,11 @@ #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -192,7 +156,6 @@ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1043ardb_boot.scr\0" \ "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ @@ -254,13 +217,6 @@ #endif #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index b4329c2e89ef7d9a063060daba4848161e7250c4..15c3ff53fe8e7544681ffc4aa0fe1bb96a0de86b 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -8,12 +8,9 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -128,7 +125,6 @@ #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif @@ -315,9 +311,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - /* * Environment */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 3ac4cb7643db96501bae1ab1932a8c87dd038657..6c33847b27b6e5bc287c380ab74c7781cca94f11 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -8,23 +8,12 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - #ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 -#endif - /* * NOR Flash Definitions */ @@ -101,7 +90,6 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index fb2011aa559243668b8bfade9b2b19b8b3074d4e..2e48ea0f8aadfee270f8f10c71e9dc7932d7f3b7 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -30,11 +30,6 @@ #include /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -51,15 +46,6 @@ /* SD boot SPL */ #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ -#define CONFIG_SPL_STACK 0x10020000 -#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* @@ -75,32 +61,14 @@ #endif #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) -#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" -#define CONFIG_SPL_MAX_SIZE 0x1f000 -#define CONFIG_SPL_STACK 0x10020000 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PBL_PAD - -#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ -#define CONFIG_SPL_STACK 0x1001f000 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif @@ -108,15 +76,6 @@ /* I2C */ -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* SATA */ #ifndef SPL_NO_SATA #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -136,14 +95,12 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#endif #if defined(CONFIG_TARGET_LS1046AFRWY) #define LS1046A_BOOT_SRC_AND_HDR\ @@ -234,13 +191,6 @@ #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include #endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index d56d0c029474435843d7648244e00aa6c2e7ef17..43717cdd4e63aa55249c7f0a95b6b28a789231da 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,8 +8,6 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - #define CONFIG_SYS_UBOOT_BASE 0x40100000 /* @@ -80,13 +78,11 @@ */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#endif /* FMan */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 05aeedc4107323acf9676b1357b4808ad891f937..36c64db8f5d17a2e061001a97c411109a7399378 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -8,12 +8,9 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -145,7 +142,6 @@ #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif @@ -333,9 +329,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - /* * Environment */ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 3dfbae268e4ec7b281f6daf36011d4df809e2e4a..382d5c76461e3c7ecd2e00f775c84623094bf5c5 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,18 +9,14 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #if defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_UBOOT_BASE 0x40100000 -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #endif #define CONFIG_SYS_NAND_BASE 0x7e800000 @@ -139,8 +135,6 @@ #endif #endif -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #include #endif /* __LS1046ARDB_H__ */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 0c73a9e0dce4cd17a097c031941bc0cee96cb997..4b8462da7bcd7472b676e3000be7a305276f5ad0 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -25,11 +25,6 @@ #define LS1088ARDB_PB_BOARD 0x4A /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif /* Link Definitions */ #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 @@ -120,11 +115,6 @@ unsigned long long get_qixis_addr(void); /* Miscellaneous configurable options */ -/* SATA */ -#ifdef CONFIG_SCSI -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#endif - /* Physical Memory Map */ #define CONFIG_HWCONFIG @@ -148,23 +138,7 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #endif -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #ifdef CONFIG_SPL -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* @@ -179,6 +153,5 @@ unsigned long long get_qixis_addr(void); #endif /* ifdef CONFIG_NXP_ESBC */ #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif /* __LS1088_COMMON_H */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index e532c343f48b1ef94ddadd3cb431455c2fd68924..debb60d25cef92b773823f30d3033e2561470b7b 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -16,7 +16,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* @@ -306,10 +305,6 @@ #define CONFIG_FSL_MEMAC -/* MMC */ -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) - #define COMMON_ENV \ "kernelheader_addr_r=0x80200000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index c69003018bfcb377b86a10d20a12a090523f5b58..c0567c3fe580a9e8e54970316a046521b638f144 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -15,13 +15,8 @@ #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#ifdef CONFIG_EMU -#define CONFIG_SYS_FSL_DDR_EMU -#else #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e77e9b7f376418f16f4adb62f07c3e79ba2fc556..3e86d1bff215c32dc019a9fedf6f845080fa7049 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -11,20 +11,11 @@ #include /* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif /* We need architecture specific misc initializations */ /* Link Definitions */ -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ #define CONFIG_VERY_BIG_RAM @@ -142,26 +133,12 @@ unsigned long long get_qixis_addr(void); "mcinitcmd=fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #endif -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include #endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4975fb782b310ea4fbb7de6088b2b6305d2de83b..9ba7258572fcdf25cc112ae2ecc45b814aababd7 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -24,15 +24,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) @@ -191,7 +182,6 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else @@ -248,14 +238,6 @@ */ #define FSL_QIXIS_BRDCFG9_QSPI 0x1 -/* - * MMC - */ -#ifdef CONFIG_MMC -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) -#endif - /* * RTC configuration */ @@ -269,10 +251,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC @@ -416,7 +394,7 @@ "env exists secureboot && esbc_halt;" #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) #define CONFIG_FSL_MEMAC #define SGMII_CARD_PORT1_PHY_ADDR 0x1C #define SGMII_CARD_PORT2_PHY_ADDR 0x1d diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 52a48bd4b891c5a47cb9de79ea5b27a7a6284d78..a504a0ea462a1c34d3bd7cede7285895457b07f4 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -29,15 +29,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) @@ -174,7 +165,6 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SPL_PAD_TO 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT @@ -248,10 +238,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 19fd702ab2455be45494e2140e119c3c934cb3cd..81c93375e2efa5b79a2d4ccd99bc6718b55c92c3 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -94,9 +94,4 @@ #define CONFIG_PHY_BASE_ADR 7 #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_SATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#endif - #endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index aaba8fc26d9cd30f34db846290f619b57e838e1b..b7543731691fc41a70eec82d40e1b781eb481973 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -12,7 +12,6 @@ #define CONFIG_FSL_MEMAC -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_FLASH_BASE 0x20000000 /* DDR */ @@ -32,7 +31,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ @@ -91,39 +89,13 @@ /* Qixis */ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SATA */ - -#ifdef CONFIG_SCSI -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 -#endif - /* USB */ -#ifdef CONFIG_USB_HOST -#ifndef CONFIG_TARGET_LX2162AQDS -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif -#endif #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - /* Initial environment variables */ #define XSPI_MC_INIT_CMD \ "sf probe 0:0 && " \ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index e7aec6bc5964efe9d0b63e4a8be447a1f6b526ce..585aab26bff7cc5cf2e52a7de03f05e68e1414b2 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -11,16 +11,6 @@ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* MAC/PHY configuration */ /* EEPROM */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 126d226ebc72e627ffc201df27527c3e3f529379..d1ae403473148daedb2103fe21321dfd1f552ded 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -9,22 +9,10 @@ #include "lx2160a_common.h" /* USB */ -#undef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* EEPROM */ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 90877f548d6921feeb63bb865f9f0c9b587353ce..b3348bc63bb9c663759229e1af297defbdea2f5b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -24,18 +24,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ /* * Serial Driver @@ -60,9 +51,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC - -/* Environment is in NAND */ -#define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */ #endif /* @@ -91,15 +79,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #endif -/* - * SATA - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* * LCD */ @@ -117,9 +96,6 @@ /* * NAND SPL */ -#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" -#define CONFIG_SPL_PAD_TO 0x8000 -#define CONFIG_SPL_STACK 0x70004000 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) @@ -136,8 +112,6 @@ "mmcpart=1\0" \ "rootpath=/srv/\0" \ "kernel_addr_r=0x72000000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "netdev=eth0\0" \ "splashsource=mmc_fs\0" \ "splashfile=boot/usplash.bmp.gz\0" \ diff --git a/include/configs/malta.h b/include/configs/malta.h index 84e5f985b1aa0d6f98ae4deba83657b7b2f0b713..c8b230ab21e9c22c6ccfd76b2bf787273fe09e90 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -13,9 +13,6 @@ #define CONFIG_MEMSIZE_IN_BYTES -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_MSC01 - #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 /* @@ -37,9 +34,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - /* * Serial driver */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index e4df9d8dfff3b8e111e976b8a80ea380dde5587d..db84302231a6dfeb12ca964557d70dee5fd7cdc9 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -46,22 +46,6 @@ * L2 cache thus cannot be used. */ -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ - /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_SDRAM_SIZE SZ_1G diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index dcce52eb7d37bc86748b93db6dcbc6a831d8145e..02a22351874bf88e25799a9b8cfb10cabdb574c5 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -12,16 +12,12 @@ #include "imx6_spl.h" #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* * Below defines are set but NOT really used since we by * design force U-Boot run when we boot in development * mode from SD card (SD2) */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" #define CONFIG_MXC_UART_BASE UART1_BASE @@ -31,7 +27,6 @@ /* NOR 16-bit mode */ #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_FLASH_VERIFY @@ -114,7 +109,6 @@ "fi;" \ "fi;" \ "fi\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootdev=1\0" \ "bootpart=1\0" \ "netdev=eth0\0" \ @@ -227,11 +221,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* Envs are stored in NOR flash */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index ab8fa85f25ebb1411f41f9e044c5f30e2227e510..c6ce8837474e66be395d40c2ff262dcbc17ccb80 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -21,15 +21,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment configs */ /* USB configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 6b6c90eb5ed87e307aea86321dca82f0f3d20a0a..6b2296788dc7ac46956eb6fcd4b566eacfb47feb 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -47,13 +47,8 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -69,6 +64,4 @@ /* hw-controller addresses */ #define CONFIG_ET1100_BASE 0x70000000 -#define CONFIG_SYS_CBSIZE 512 - #endif diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 196e58ed9a3f4ddcd12d825a470395503aa93073..40803ee9da1a226c9ab61d22f6d416c66938478f 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -29,12 +29,7 @@ #define STDIN_CFG "serial" #endif -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 663837f33dc4fb58eeb11e8f3cb3fe00227cda2f..73f84922288091b62852a62bed26e908b11883be 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -11,17 +11,11 @@ /* Microblaze is microblaze_0 */ #define XILINX_FSL_NUMBER 3 -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - /* uart */ /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -/* Stack location before relocation */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_F_LEN) - #ifdef CONFIG_CFI_FLASH /* ?empty sector */ # define CONFIG_SYS_FLASH_EMPTY_INFO 1 @@ -30,15 +24,6 @@ # define CONFIG_SYS_MAX_FLASH_SECT 2048 #endif -#ifndef XILINX_DCACHE_BYTE_SIZE -#define XILINX_DCACHE_BYTE_SIZE 32768 -#endif - -/* size of console buffer */ -#define CONFIG_SYS_CBSIZE 512 -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 15 - #define CONFIG_HOSTNAME "microblaze-generic" /* architecture dependent code */ @@ -120,28 +105,10 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* for booting directly linux */ -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_TEXT_BASE + \ - 0x40000) - -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ - 0x1000000) - /* SP location before relocation, must use scratch RAM */ /* BRAM start */ #define CONFIG_SYS_INIT_RAM_ADDR 0x0 /* BRAM size - will be generated */ #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) - -/* Just for sure that there is a space for stack */ -#define CONFIG_SPL_STACK_SIZE 0x100 - -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_INIT_RAM_ADDR - \ - CONFIG_SYS_MALLOC_F_LEN - \ - CONFIG_SPL_STACK_SIZE) - #endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 655c8d6af5dab785c0573473e6e2dd3ebfe69998..4c7cfac8af75f5d31b8bbd2c18256de5b4239544 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -10,9 +10,6 @@ #include #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 703efcd8f34003d105c27cf21cb37ad8f04ca3c6..049d9a1b55bb33587951238b7d7e73ede9b8cdcb 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -10,24 +10,13 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_CBSIZE 1024 - /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index 97fcf2f87bdc6adfe09e48479aec026d5e5c4453..78d79b7780bccd0845fae1b4e108fc870b848712 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -11,11 +11,6 @@ #include -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Uboot definition */ @@ -23,8 +18,6 @@ /* SPL -> Uboot */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 6023f8128efc78a4f5a7cd3fde73833f4cc668e5..0cd8b08552cfe04f9e8f2487e6906f9fb82caa1e 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -13,19 +13,11 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ /* Preloader -> Uboot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) /* MMC */ #define MMC_SUPPORTS_TUNING diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 1008aaab1d2eecc5ebb4310cddd9cf7145d271c3..3680c0fe442a2a5f9ca2cbc4553f895beadd298f 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -10,17 +10,10 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_CBSIZE 1024 - /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 @@ -36,10 +29,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index c58545be04b6d7b76fc3ef4a54528db9f918ef44..22d11d014761c33550aff51860481def810b4e0a 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -13,31 +13,18 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ /* Defines for SPL */ -#define CONFIG_SPL_STACK 0x106000 -#define CONFIG_SPL_MAX_SIZE SZ_64K -#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K -#define CONFIG_SPL_PAD_TO 0x10000 #define CONFIG_SPI_ADDR 0x30000000 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) /* UBoot -> Kernel */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index ee31c02e6ef9dd3a71eea77595289f928a4126c9..c93d70ddf1a61ba2f2a8cc1cc25a3b3d2c1ad083 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -18,11 +18,6 @@ #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Environment settings */ #include diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 1af8d2e480c2d31599590d17c8c0c1400a97889b..964c9578133852feada539a8b99799546909db3c 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -13,14 +13,8 @@ #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ - SZ_2M - \ - GENERATED_GBL_DATA_SIZE) #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index cb2af5843fcaa9665a18e8cecd78c3a2f9f708b2..7228f3e42884aad7cf3c3af794e827f23ccf5532 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -18,11 +18,6 @@ #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Environment settings */ #include diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8ca8d25148a318ebf194c94e2ae1fe66cfae7aa4..6d4704644e4f2cfe7bce1d3497fa7feb26405c82 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -18,12 +18,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Uboot definition */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ - SZ_2M - \ - GENERATED_GBL_DATA_SIZE) #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index cc3b597f286e10bc286c6bc47c85d746ea7008ed..384a8f7d1dd8ddbde06b9fdd34b7fd8002399a17 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -50,12 +50,9 @@ /* auto boot */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ /* ====> Include platform Common Definitions */ #include diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 06882fb51e8f6aae6599d7ec8b980b885a562178..51f7e16ece1a51a883fa7d73d09f63e3f837c22c 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -15,8 +15,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ @@ -25,29 +23,15 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) /* * Environment */ #define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 8e325e8f4a00921ecda66eb58ef6a2e13537ba90..5a956f0a3e36c031c24675480c07af51bf864c19 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -19,30 +19,16 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) /* When runtime detection fails this is the default */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - /* USB ethernet */ -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - /* * PCI configuration */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index ab466b65ac43990790b84feea5292df8e24d6f2d..dd303a17d61c7b1f8a7cac13901b1e872d00270a 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -15,10 +15,6 @@ /* Status LED */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Ethernet */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 3fb00031075d1a3a42efffb63e8f3cd9939487b5..3507e83fb38bab383b09e499fd74c5ff38030cfb 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -20,10 +20,6 @@ /* Environment is in MMC */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Framebuffer support */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index fe096d424c3a99caf431db8e61aa7ee250fc0154..9f3ac48b70a2be95ac7c4db6062e12f24100bdec 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -15,17 +15,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Environment */ - -/* Environment is in MMC */ - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - -/* Environment is in SPI flash */ - /* UBI and NAND partitioning */ /* RTC */ @@ -34,10 +23,6 @@ #endif /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Framebuffer support */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ccfe292f6c697fac8ab2c170d49ecb938f9ac73f..a423dd28b07d36a800bd8beb2ee82970ac78861d 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -117,11 +117,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 #define CONFIG_SYS_MAIN_PWR_ON diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index fafc5f1adcb68889ba4f2e97c46466198d823a23..f1d751f15a2424ba53e07366670877f0f05cce76 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -16,8 +16,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_FPGA_COUNT 1 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 2 @@ -55,7 +53,6 @@ BOOTENV /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -68,11 +65,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* Framebuffer and LCD */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8b9f0a290179ff07d4e0a8b6c0da5e1f47439d51..9ceed12e4872d94b741c233f9b0d2f5e5f799c9b 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -88,7 +88,6 @@ "fi;\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -101,17 +100,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR - #define CONFIG_LBA48 -#endif - /* Framebuffer and LCD */ #endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 572261b042677826bdeafdb5b54494e37d882c74..b26613a2ea8344d5965dff7d9b4d54c82f9604de 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -86,10 +86,6 @@ "lcd:800x480-24@60,monitor=lcd\0" \ /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 48 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ @@ -104,11 +100,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* FLASH and environment organization */ #define CONFIG_FSL_IIM diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 10e46c628d5265f212aac4b13560ba8f5ff220e0..e416f81e43a164613c857bff02e2f3b569537939 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -19,15 +19,11 @@ #endif #define CONFIG_MXC_GPT_HCLK -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - #include #include #include /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 /* MMC */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 832f73f05ef25364ad1f03846a6a9b2d30a067a6..cffbb64bcd539fee1584ec794a1bf0834e6fbe88 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -16,13 +16,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* SATA Configuration */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP @@ -34,7 +27,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ "has_emmc=undefined\0" \ @@ -94,20 +86,11 @@ #include -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - /* Physical Memory Map */ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #endif /* __MX6CUBOXI_CONFIG_H */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 42d5e248ba16f6aa2d0a4c8b5df680838543c674..ad53f17d671610b6988406643202a4d5572aedce 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -25,8 +25,6 @@ #error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16) - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -34,11 +32,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index d7408e06a06063ee3e8bcfe1f644765682e0a9fa..bfcab1bed5b88292b048df6f0fef652500bb6ac9 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -143,11 +143,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* Framebuffer */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index a212652fd7f083ccb97837774771ffc61971f3ea..bc4aa52f5bf178983378d550cea99aa23ff8fc8c 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -16,8 +16,6 @@ #define CONSOLE_DEV "ttymxc3" /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -28,13 +26,7 @@ /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #ifdef CONFIG_MTD_NOR_FLASH @@ -42,7 +34,6 @@ #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5a854b9d194630b1e88bffc40daa64a02667cea3..16f8858abb8fff07a6a3512ef3f55516c40881df 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -18,19 +18,12 @@ #include "mx6sabre_common.h" /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #define CONFIG_SYS_FSL_USDHC_NUM 3 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif @@ -41,10 +34,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3da796d03a083b9a4b8f3a9678b894e32ab6a39b..9f890938f982e70663bf15fb0feab691846a6aa1 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -90,19 +90,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 1b32f58afca363862cca779399aea9d5928da1c5..e9ccb99d3cecd18ee02ceb942e4c83eac6aeeec2 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -86,11 +86,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* MMC Configs */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 372cf8dd71145a1547e6870a356850ea89f5a072..c878041400465887e4ed649424c6bff7eb4f0460 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -82,11 +82,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR @@ -102,10 +97,8 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 76e3dc8b3828c003fdc495c994ba223ea8239169..570e2ce687ac8e87f12ef714689b07722562e29e 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -19,8 +19,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI2 B flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ @@ -35,7 +33,7 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 1:0; bootaux 0x78000000\0" #else #define UPDATE_M4_ENV "" #endif @@ -116,11 +114,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR @@ -129,23 +122,15 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_DM_VIDEO #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR -#endif -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 03d799ce654d9fb183aaed2494170fad469c8e26..ab56ea0205da5e273ecbeb26d4a3806ab247c4f7 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -115,19 +115,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_NET @@ -140,10 +133,6 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD -#if defined(CONFIG_DM_VIDEO) #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif #endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index bc494b46b693b044e5f87d10d0d3a7dd000425d4..00cc547b900cfc0aac724cd15eedc0e90daabe2d 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -21,14 +21,8 @@ /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ @@ -112,11 +106,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #define CONFIG_IOMUX_LPSR diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 9f7d60f8fbd872fe9870f989ae4d6e2e58f4ae84..4704276a74de840ed00ae398d8c4340fb48a3b69 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -17,14 +17,10 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 /* UART */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index aaad232f0e4f17c3cf288cd70bcd0288387ad903..b96341a587c4f4c0b00c525ba90502d37a697aa2 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -12,11 +12,7 @@ #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI1 A flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ @@ -31,7 +27,7 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 0:0; bootaux 0x60000000\0" #else #define UPDATE_M4_ENV "" #endif @@ -89,11 +85,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index f8a5009637dc30b44490af537c7bd2a5863da1ce..62e8e62991185074d3a71926bd62b4cc31c4a6f9 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -15,8 +15,6 @@ #include "imx7ulp_spl.h" #endif -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE @@ -53,10 +51,5 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 7644274d84b6bda71fa03205fdd4eb623e97eb81..e93824928b322927bc1c7e51ed7b14e0dd5d9623 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -11,8 +11,6 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE @@ -23,9 +21,6 @@ #define LPUART_BASE LPUART4_RBASE /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 - -#define CONFIG_SYS_MAXARGS 256 /* Physical Memory Map */ @@ -100,9 +95,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 8dcc45c9e5d6a9138298de39e3bd8008183e00c3..fc15ed82c6ed1ad18eb4be8719c451b273b1f7f3 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -43,11 +43,6 @@ /* Startup hooks */ -/* SPL */ -#ifndef CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#endif - /* Memory sizes */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ @@ -59,10 +54,6 @@ #endif /* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* * We need to sacrifice first 4 bytes of RAM here to avoid triggering some @@ -78,10 +69,6 @@ */ /* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ /* * Drivers diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 6801fc109eaef48d68f85e72f54fc4ad0b2f1f71..4162ee8caa21ff74ea9b260520a0d233aa5f2169 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -29,25 +29,16 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -59,7 +50,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 815f81f6493d9a4cc38f918cec5b86de46cfcde1..1b7eb3433483678fa9a1c9cdb9c58b2a38e67874 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -37,13 +37,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=console=ttyS0,115200\0" \ - "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ - "0x010000@0xa0000(env),"\ - "0x500000@0xc0000(uimage),"\ - "0x1a40000@0x5c0000(rootfs)\0" \ - "mtdids=nand0=orion_nand\0"\ - "autostart=no\0"\ - "autoload=no\0" + "autostart=no\0" /* * Ethernet Driver configuration diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index afa4ca5b5af3ef59a42fd5520b8ce75aa3c4dcce..2007b48868f69d955299a35a9454e51763f5bc74 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -19,21 +19,10 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 6 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -106,19 +95,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index f273e243e55df79e138ade9ea566c848332b911f..97aafc5f72500fd341acae2a8ce2a74f510adf6d 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -153,7 +153,6 @@ * This rate is divided by a local divisor. */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* * Physical Memory Map @@ -167,8 +166,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Attached kernel image diff --git a/include/configs/novena.h b/include/configs/novena.h index dbde7a0ade5a3d71ca08b8a20c57a60b49eb4a16..1696aa28520f3743729d477d7711e23c83e4960f 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -34,17 +34,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ /* I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ @@ -54,8 +48,6 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif @@ -64,15 +56,11 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -/* SATA Configs */ -#define CONFIG_LBA48 - /* UART */ #define CONFIG_MXC_UART_BASE UART2_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Gadget part */ @@ -84,7 +72,6 @@ #define CONFIG_IMX_VIDEO_SKIP /* Extra U-Boot environment. */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -155,8 +142,4 @@ #include -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - #endif /* __CONFIG_H */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index c250fa650603572c61df9f93aa4206758e13a8c6..217427a302e79a4cf5dfb3c8e7b9d57f05001643 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -30,20 +30,13 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC_PHYADDR 0x1 @@ -55,8 +48,6 @@ "console=ttymxc0,115200n8\0" \ "image=zImage\0" \ "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "kernel_addr_r=0x81000000\0" \ "pxefile_addr_r=0x87100000\0" \ @@ -67,7 +58,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 1e6b8d8b0e730697112bee942dac6dc2fb96602b..027a47b5a32f9373c9fe5a5d959bfc9c5d5548c4 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -15,8 +15,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/nsa310s.dtb\0" \ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" @@ -25,8 +23,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 1 -/* Support large HDDs for USB and SATA */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nsim.h b/include/configs/nsim.h index de07b6b15f6dc43b558108662572d25860ffc70d..d469ef83c240d5cf03ccfe7c6a92fc99e345a3f8 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -16,11 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_32M - /* * Console configuration */ diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 7777935ba6ee39a7c69924c0ee2850911ebea6b6..00f7d871271dd0aefcb2b27e24d9e119d5e0a008 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -10,8 +10,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #if IS_ENABLED(CONFIG_CMD_USB) # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 7e71c83887f39f3f6e742e6be54ed4548b127bab..0fa7490e7de621783f698b2bcdb067a41bb3fa66 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -16,6 +16,4 @@ #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h index 8c6c57bd546a13d7794a0f00f72014bdbfe0444e..7035e6313420690d18a6c557d64cb5b73ca5b096 100644 --- a/include/configs/octeon_ebb7304.h +++ b/include/configs/octeon_ebb7304.h @@ -13,7 +13,6 @@ * CFI flash */ #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h index 0a7b4d8f93e2ba1139fc774edacb0337aecf239e..7d99fd1b01954b5162c03026a324980aab5fe310 100644 --- a/include/configs/octeon_nic23.h +++ b/include/configs/octeon_nic23.h @@ -7,15 +7,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -/* - * SATA/SCSI/AHCI configuration - */ -/* AHCI support Definitions */ -/** Enable 48-bit SATA addressing */ -#define CONFIG_LBA48 -/** Enable 64-bit addressing */ -#define CONFIG_SYS_64BIT_LBA - #include "octeon_common.h" #endif /* __CONFIG_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 6ec2d3e2688958e2e5ea12e6381ac984ee38fbc7..2c430e8d3762249c7bda92d5994cec97e0f18c1a 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -8,25 +8,16 @@ #define __OCTEONTX2_COMMON_H__ /** Maximum size of image supported for bootm (and bootable FIT images) */ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /** Memory base address */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE /** Stack starting address */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) /** Extra environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ - "ethrotate=yes\0" \ - "autoload=0\0" - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MAXARGS 64 /** max command args */ + "ethrotate=yes\0" #define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 81dbff2d672fc76f2a4dbc70e0d4b65f968d2b8e..e7a6bd41db05873814934ed559dd257943e0fa2c 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -18,7 +18,6 @@ #include /* Extra environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=0\0" \ "loadaddr=0x20080000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x03000000\0" \ @@ -35,30 +34,14 @@ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ /** Maximum size of image supported for bootm (and bootable FIT images) */ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /** Memory base address */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE /** Stack starting address */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) /** Heap size for U-Boot */ -/* AHCI support Definitions */ -#ifdef CONFIG_DM_SCSI -/** Enable 48-bit SATA addressing */ -# define CONFIG_LBA48 -/** Enable 64-bit addressing */ -# define CONFIG_SYS_64BIT_LBA -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MAXARGS 64 /** max command args */ - #define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 /** EMMC specific defines */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b8b47af4712bf453f3dec9e0452bd3dfe351bc09..7448cc9520364ab95ce1ee36b2b03e2635187d31 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -24,9 +24,6 @@ #include -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Partitions name */ #define PARTS_BOOT "boot" #define PARTS_ROOT "platform" @@ -147,14 +144,6 @@ "kernel_addr_r=0x41000000\0" \ BOOTENV -/* GPT */ - -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - /* * Supported Odroid boards: X3, U3 * TODO: Add Odroid X support diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 360815bc03ee0344bae7a20316b2b8aff64bbada..15646297423ec3e8c146c8da597bdff5a0423b45 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -16,11 +16,6 @@ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - /* DFU */ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 @@ -33,9 +28,6 @@ #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ -#undef CONFIG_EXYNOS_TMU - #define CONFIG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 158773acedb997c854bfa034e7e1895592976537..2cd42e5a1dc49bc231d1707763580c657cb69d77 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -28,9 +28,6 @@ #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K /* NAND: SPL falcon mode configs */ -#if defined(CONFIG_SPL_OS_BOOT) -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -#endif /* CONFIG_SPL_OS_BOOT */ #endif /* CONFIG_MTD_RAW_NAND */ /* Enable Multi Bus support for I2C */ @@ -65,7 +62,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, rootfs, rootfs) \ func(NAND, nand, 0) #else /* !CONFIG_MTD_RAW_NAND */ @@ -87,8 +84,6 @@ "bootenv=uEnv.txt\0" \ "bootfile=zImage\0" \ "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ "usbtty=cdc_acm\0" \ "mpurate=auto\0" \ "buddy=none\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index eeb9ef8c741a7060aa5ef76a4e8ea77c3fdd019b..2683d4c7ea45a659e74af9b16bdbd9a626aa07e6 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -32,10 +32,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K -/* NAND: SPL falcon mode configs */ -#if defined(CONFIG_SPL_OS_BOOT) -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -#endif /* CONFIG_SPL_OS_BOOT */ #endif /* CONFIG_MTD_RAW_NAND */ #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ @@ -60,7 +56,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, rootfs, rootfs) \ func(NAND, nand, 0) #else /* !CONFIG_MTD_RAW_NAND */ @@ -80,16 +76,12 @@ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_high=0xffffffff\0" \ "console=ttyO0,115200n8\0" \ "bootdir=/boot\0" \ "bootenv=uEnv.txt\0" \ "bootfile=zImage\0" \ "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ "optargs=\0" \ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \ "nandrootfstype=ubifs rootwait\0" \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index c1ef040ce360099184549dc82a36bde768f8d836..97f47ea5b710fd0a3fa12e3bee32dd3cf9976f4c 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -28,8 +28,6 @@ #define GPIO_IGEP00X0_BOARD_DETECTION 28 #define GPIO_IGEP00X0_REVISION_DETECTION 129 -#ifndef CONFIG_SPL_BUILD - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ @@ -67,10 +65,7 @@ MEM_LAYOUT_SETTINGS \ BOOTENV -#endif - /* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index d3839eb1229301482f859041a24cb12fc1b3bb1c..38dc7ea88f7b545a98e56ff7a027d3a3a9f6c14b 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -35,8 +35,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcrootfstype=ext4 rootwait\0" \ @@ -87,7 +85,6 @@ "nfsroot=${nfsrootpath} " \ "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \ "nfsrootpath=/opt/nfs-exports/omap\0" \ - "autoload=no\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "loadfdt=mmc rescan; " \ "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ @@ -154,16 +151,8 @@ #endif #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE 0x4000000 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -/* Defines for SPL */ - -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 75e84c35ee064393ec9d6b1ac5f6733fd3794c39..cce5556fe266d13a6b9196cfe191d784bd5baff3 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -40,9 +40,6 @@ #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 -/* USB UHH support options */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - /* Enabled commands */ /* USB Networking options */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 0d69316862da8a28f8fd42d254e3c0d52d903a53..c644768ae7d716afced4fd79a998d63032076b76 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -28,9 +28,6 @@ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ -#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE -#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 - /* memtest start addr */ /* memtest will be run on 16MB */ @@ -102,8 +99,6 @@ /* * I2C Configuration */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 /* @@ -139,14 +134,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ - -/* - * USB Configs - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 /* * Linux Information @@ -174,17 +161,9 @@ /* SD/MMC */ /* defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_STACK 0x8001ff00 -#define CONFIG_SPL_MAX_FOOTPRINT 32768 -#define CONFIG_SPL_PAD_TO 32768 /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) #include diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 75b48f880affe8edd87e5e7440184f57694fab44..3ff8187b5df73698f8c48134e4343500ebde4bdf 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -15,22 +15,6 @@ /* Environment options */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) -#define CONFIG_SYS_BOOTM_LEN SZ_256M - -#ifdef CONFIG_SPL -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x82000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000 -#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin" -#define CONFIG_SPL_GD_ADDR 0x85000000 -#endif /* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 1f2887105fff5cad93fe3b34daffe6a45276c275..3e551e13aa67f880e3a2d68eb35540bb847f077f 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -21,158 +21,16 @@ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* USB */ #ifdef CONFIG_USB_EHCI_MX6 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* LCD */ -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_DM_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif -/* Environment is stored in the eMMC boot partition */ - -#define CONFIG_ENV_VERSION 100 -#define ACFG_CONSOLE_DEV ttymxc0 -#define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_ROOTPATH "/tftpboot/opos6ul-root" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "board_name=opos6ul\0" \ - "fdt_addr=0x88000000\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_name=opos6uldev\0" \ - "initrd_high=0xffffffff\0" \ - "ip_dyn=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "kernelimg=opos6ul-linux.bin\0" \ - "splashpos=0,0\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; " \ - "fi; " \ - "if itest ${flash_env_version} != ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; " \ - "env default flash_reset_env; " \ - "else exit; fi; \0" \ - "flash_reset_env=env default -f -a && saveenv && " \ - "echo Environment variables erased!\0" \ - "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ - "flash_uboot_spl=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x2 ${sz}; then " \ - "echo Flashing of U-boot SPL succeed; " \ - "else echo Flashing of U-boot SPL failed; " \ - "fi; " \ - "fi;\0" \ - "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ - "flash_uboot_img=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x8a ${sz}; then " \ - "echo Flashing of U-boot image succeed; " \ - "else echo Flashing of U-boot image failed; " \ - "fi; " \ - "fi;\0" \ - "update_uboot=run download_uboot_spl flash_uboot_spl " \ - "download_uboot_img flash_uboot_img\0" \ - "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ - "flash_kernel=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ - "echo kernel update succeed; " \ - "else echo kernel update failed; " \ - "fi;\0" \ - "update_kernel=run download_kernel flash_kernel\0" \ - "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ - "flash_dtb=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ - "echo dtb update succeed; " \ - "else echo dtb update in failed; " \ - "fi;\0" \ - "update_dtb=run download_dtb flash_dtb\0" \ - "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ - "flash_rootfs=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ - "echo Flashing of rootfs image succeed; " \ - "else echo Flashing of rootfs image failed; " \ - "fi; " \ - "fi;\0" \ - "update_rootfs=run download_rootfs flash_rootfs\0" \ - "flash_failsafe=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ - "echo Flashing of rootfs image in failsafe partition succeed; " \ - "else echo Flashing of rootfs image in failsafe partition failed; " \ - "fi; " \ - "fi;\0" \ - "update_failsafe=run download_rootfs flash_failsafe\0" \ - "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ - "flash_userdata=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ - "echo Flashing of user_data image succeed; " \ - "else echo Flashing of user_data image failed; " \ - "fi; " \ - "fi;\0" \ - "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ - "erase_userdata=" \ - "if mmc dev 0 0; then " \ - "echo Erasing eMMC User Data partition, no way out...; " \ - "mw ${loadaddr} 0 0x200000; " \ - "mmc write ${loadaddr} 0 0x1000; " \ - "mmc write ${loadaddr} 0x800 0x1000; " \ - "mmc write ${loadaddr} 0x40800 0x1000; " \ - "mmc write ${loadaddr} 0x440800 0x1000; " \ - "fi;" \ - "mmc rescan\0" \ - "update_all=run update_rootfs update_uboot\0" \ - "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ - "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "emmcboot=run initargs; run addmmcargs; " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" \ - "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ - "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "nfsboot=run initargs; run addnfsargs addipargs; " \ - "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ - "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" - #endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index c4f5997c3dec3294451b31974189700341e463b6..36aaa7c14fb3c5295c4f99f49cefd515d308bc80 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -10,10 +10,6 @@ #include -/* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ -#define CONFIG_ORIGEN 1 /* working with ORIGEN*/ - /* ORIGEN has 4 bank of DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE @@ -48,8 +44,4 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 - #endif /* __CONFIG_H */ diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index fabbb01e0c800fe5a7c5df033dfbdd2fe6040f28..b0233b96b06dc2d76bf16d07bf718810d0b664e9 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -20,11 +20,7 @@ * image to the top of SDRAM. After relocation u-boot moves the stack to the * proper place. */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) /* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h new file mode 100644 index 0000000000000000000000000000000000000000..13e4fdb4fdf6fef02eb8820d1bd1bce306f46133 --- /dev/null +++ b/include/configs/p1_p2_bootsrc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + * Copyright 2022 Pali Rohár + */ + +#include + +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#endif + +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 + +#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) + +#ifdef __SW_NOR_BANK_LO +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_LO_CMD(var, ...) "" +#endif + +#ifdef __SW_NOR_BANK_UP +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_UP_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NOR +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)) +#else +#define RST_NOR_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SPI +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) +#else +#define RST_SPI_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SD +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)) +#else +#define RST_SD_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NAND +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) +#else +#define RST_NAND_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_PCIE +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)) +#else +#define RST_PCIE_CMD(var, ...) "" +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f6ecf2a7a8b89f147f418602924c830b2a8a9772..a0d583040cde84e69910f1f3198832f363661699 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -77,90 +77,41 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #elif defined(CONFIG_SPIFLASH) -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 4096 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#else -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif /* not CONFIG_TPL_BUILD */ - -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - -#define CONFIG_LBA48 - #define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_L2_CACHE -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) @@ -181,7 +132,6 @@ #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 @@ -215,7 +165,6 @@ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 - * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable @@ -310,9 +259,7 @@ /* Size of used area in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -324,14 +271,6 @@ #endif /* CPLD config size: 1Mb */ -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" @@ -365,31 +304,15 @@ #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) -#else -#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) -#endif #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) #else #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) #endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -402,7 +325,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -417,8 +340,6 @@ #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } #endif -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - /* * I2C2 EEPROM */ @@ -462,8 +383,6 @@ #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -490,15 +409,10 @@ /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #endif -#elif defined(CONFIG_SYS_RAMBOOT) -#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ @@ -507,17 +421,6 @@ /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -533,7 +436,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration @@ -542,31 +444,7 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif +#include "p1_p2_bootsrc.h" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -593,13 +471,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -__stringify(__NOR_RST_CMD)"\0" \ -__stringify(__SPI_RST_CMD)"\0" \ -__stringify(__SD_RST_CMD)"\0" \ -__stringify(__NAND_RST_CMD)"\0" \ -__stringify(__PCIE_RST_CMD)"\0" +MAP_NOR_LO_CMD(map_lowernorbank) \ +MAP_NOR_UP_CMD(map_uppernorbank) \ +RST_NOR_CMD(norboot) \ +RST_SPI_CMD(spiboot) \ +RST_SD_CMD(sdboot) \ +RST_NAND_CMD(nandboot) \ +RST_PCIE_CMD(pciboot) \ +"" #define CONFIG_USB_FAT_BOOT \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 31b7d07a24cde6519787948445468678262401a6..6e593da936cddf98e12f87dd0f18d476ce0c6531 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -41,25 +41,16 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -71,7 +62,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 068fc7db347fc01f2e8cc11ca3a065f41eaacff7..ae81b8e214e23c2209653a715e6ab8393e225f35 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -43,20 +43,13 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 79b69dfe175a9cfd0165550ae53f829f47600f53..a8cfec96595999e1bbeb2ad01baba443f8733274 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -33,7 +33,6 @@ /* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ PCM052_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -50,7 +49,6 @@ "nfs_root=/path/to/nfs/root\0" \ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootargs_base=setenv bootargs rw " \ " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ "console=ttyLP1,115200n8\0" \ @@ -126,11 +124,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #endif diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 4d4185b466872f91663dbbac29d5a0e1d0400d86..cff71df1c9620444f17e28d31d9f91069d3233f8 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #define ENV_MMC \ "mmcdev=0\0" \ @@ -42,8 +37,6 @@ "mmcboot=run mmcloadfit;run mmcargs;bootm ${loadaddr}\0" #define ENV_NAND \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:root ubi.mtd=rootfs\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs root=${nandroot} " \ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 7ab6a896040f708f7a42c29855fdb73ed7c28dd2..ed3201aa3c42e7379c7b232e88367c0851bb0cf5 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -32,7 +32,6 @@ #define CONSOLE_DEV "ttyO5" #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=am335x-pdu001.dtb\0" \ @@ -49,7 +48,6 @@ "reset;" \ "fi;" \ "\0" -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 UART0_BASE diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index ba82aaf6537143a6d9a42bd5888e031edce069b9..7a8d3c63d445e079b34df524d7f488b10bb2b7fe 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -21,14 +21,6 @@ #include #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif #define CONFIG_POWER_TPS65090_EC diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 16fb2f3a0e304acbb4e8d15061e8216bc914f8f9..2c749ac2143dc1ae840d59425b5ae0609ffa80dd 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -21,7 +21,6 @@ #include #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index af6f7e14dfde195fe3acd82e2fab4770d43706d2..f69d8adb91cac51a3b7826f0672357a4f197522f 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -16,8 +16,6 @@ #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ @@ -97,10 +95,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif #endif /* !CONFIG_MTD_RAW_NAND */ /* CPU */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 46fadd56106adbd91b13570acf136f0a6e1752cd..049d1d74345d62558e1b56e0f939f7e94292cf92 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,23 +11,14 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -72,10 +63,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -83,12 +70,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index eb92c423392abf8bc1e49e0e44be00d9bf0346d1..df1716106fe1214f0f075f7a4c6948f80c8b8418 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,21 +10,11 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x98FC00 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 @@ -72,10 +62,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -83,12 +69,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - #endif /* __PHYCORE_IMX8MP_H */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index ef3b0f73d6260f6fa4434eff70f6aae30f1322fc..0a07c9c29c18ec0e67fc7705d1ad7b533d6ff5a9 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -23,12 +23,9 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_ADDR \ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x88000000 -#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) #define CONFIG_SYS_MONITOR_LEN (192 << 10) @@ -41,7 +38,6 @@ /*------------------------------------------------------------ * Console Configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /*-------------------------------------------------- * USB Configuration diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index c288908046ac8588f14bc65da2c8b8b65e542b86..df4dc4d496c6c44e68b7eb257ded8651ea3842f2 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -14,13 +14,8 @@ #ifdef CONFIG_SPL_OS_BOOT /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #define CONFIG_MXC_UART_BASE UART1_BASE @@ -109,11 +104,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ /* Ethernet Configuration */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 1f111ea3064f8bbeec8e3b6ca7f37ddef9ef60f8..2ac48c40c96e2b851c7313e97ef49e78806ab1be 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -16,13 +16,8 @@ #ifdef CONFIG_SPL_OS_BOOT /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif /* Network support */ @@ -35,10 +30,8 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS @@ -109,11 +102,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 06fd78f9da604030f7bbca5d1f7dc47ff286579c..7fbf2c3f55fb26e34e9b6eedba034decdeae4ff4 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -14,13 +14,8 @@ #ifdef CONFIG_SPL_OS_BOOT /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR @@ -110,11 +105,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* PMIC */ #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 @@ -126,9 +116,7 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 1dc7d3525908bc3d44232bfa9c380e3577d0d843..d1cc1b9d63fb08ed4f41137fb0bb6b5b5ae7aee0 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -9,22 +9,15 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ @@ -74,10 +67,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -86,16 +75,7 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_BOOTM_LEN SZ_128M - #endif diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h index d478b19917dfbda956f980f46d9c0c2841305977..241dc39be00846b894923990491830e373c045aa 100644 --- a/include/configs/pinebook-pro-rk3399.h +++ b/include/configs/pinebook-pro-rk3399.h @@ -16,7 +16,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 1db82793970381517e600172594288a43fb6b8b9..7374514698f9ebe1a8c29633a99f34891633608e 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -152,17 +152,9 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -179,7 +171,5 @@ "" #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ - GENERATED_GBL_DATA_SIZE) #endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 143e9f542accbe4dcf0fc85d190d6d368866abac..7a6d817926c7450997ab6eefcf8627a56af7f211 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -175,17 +175,9 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -202,7 +194,5 @@ "" #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ - GENERATED_GBL_DATA_SIZE) #endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index b858aaa1ccd9393838b6cbd3fe77d3398df1a9d5..69f3d0658784fd2f1083654fd20a747c2245629f 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -23,9 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x70000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -46,22 +43,11 @@ #endif /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 #define CONFIG_SYS_MONITOR_LEN 0x80000 #ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x70000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 #define CONFIG_SYS_NAND_ECCSIZE 256 diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index cb221501e269bbee10dd2ebe1435118f79cbb533..085732214e50a663cfb83e0548484ad1e4228584 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -19,9 +19,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ - "32M(rootfs),-(data)\0"\ - "mtdids=nand0=orion_nand\0"\ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index 3365ebe3d2faeba1efb04a709c68098737fc0eb5..7fff78b7b5d68a4d8f1158c1f173596a6ddfa0d0 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -26,8 +26,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ "dtb_file=/boot/dts/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\ - "mtdids=nand0=orion_nand\0"\ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; load usb 0:1 0x00800000 /boot/uImage; " \ "load usb 0:1 0x01100000 /boot/uInitrd; " \ @@ -39,10 +37,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* - * Support large disk for SATA and USB - */ -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 - #endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index c21b063c0591eabb9740033f5e3d6d530b06dae6..f1c259f4760b690cf84a8c1df08f35ca78ec6b57 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -11,12 +11,8 @@ #define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) #define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE) /* Default environemnt variables */ #define CONFIG_SERVERIP 192.168.0.1 diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index cdd6cdb58dd9bcc1eeb67321a7fd1b4d8d26e3e1..2e206542f8dbdb5a6309df703b526b384e187153 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -12,17 +12,13 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* SIZE of malloc pool */ -#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) /*BOOT*/ -#define CONFIG_SYS_BOOTM_LEN 0x3c00000 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 222a14bc8f8e5def95f33864c32f3c4788a1dc90..c58105597e47f78c0f1d14c4708e0903e470e9bb 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -16,13 +16,10 @@ /* DRAM banks */ /* SYS */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_INIT_SP_ADDR 0x200000 /* ATF bl33.bin load address (must match) */ /* USB configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /***************************************************************************** * Initial environment variables @@ -32,9 +29,7 @@ func(USB, usb, 0) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) -#ifndef CONFIG_SPL_BUILD #include -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "loader_mmc_blknum=0x0\0" \ @@ -49,8 +44,4 @@ "ramdisk_addr_r=0x32400000\0" \ BOOTENV -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 - #endif /* _POPLAR_H_ */ diff --git a/include/configs/porter.h b/include/configs/porter.h index bf380ddf05b030c1d8a85c576b774701be2ba514..88fa65e0ffc1bb0ba30cf190c1fcd64b28551231 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -12,10 +12,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -39,7 +38,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __PORTER_H */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 1d526a738027612ff699f811e789d85c0e7de3ca..90f548cc6c137936257f415dfb8a7b4c85e61b51 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -8,9 +8,6 @@ #ifndef __PRESIDIO_ASIC_H #define __PRESIDIO_ASIC_H -#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SYS_BOOTM_LEN 0x00c00000 - /* Generic Timer Definitions */ #define CONFIG_SYS_TIMER_RATE 25000000 #define CONFIG_SYS_TIMER_COUNTER 0xf4321008 @@ -42,10 +39,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define KSEG1_ATU_XLAT(x) (x) @@ -61,7 +54,6 @@ #define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c /* max command args */ -#define CONFIG_SYS_MAXARGS 64 #define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" /* nand driver parameters */ diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index a7f5e9116552fb873c3329456dc2a0264894dc9b..49d1878ebdd7f6247fd44d5fb0f0778ef03879b2 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,31 +8,18 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_NS16550_MEM32 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00400000 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x4000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -50,5 +37,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7272470d12e6232bbebf3692ef65e580952ddae0..4f24b13f500edd90c46ea6ee74960669d5ef0544 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -30,10 +30,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ -#define CONFIG_FACTORYSET - -#ifndef CONFIG_SPL_BUILD - /* Use common default */ /* Default env settings */ @@ -69,9 +65,4 @@ "bootm ${kloadaddr}\0" \ "" -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ - #endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 550e26f3f18fafc5de48dbb43338905b377e834f..e9f756b13edbb238a2afb08b4e934820212b0205 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -/* The DTB generated by QEMU is placed at start of RAM, stay away from there */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ EFI_GUID(0xf885b085, 0x99f8, 0x45af, 0x84, 0x7d, \ @@ -79,8 +74,6 @@ "ramdisk_addr_r=0x44000000\0" \ BOOTENV -#define CONFIG_SYS_CBSIZE 512 - #define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 136a2dfa716a0632cf7fcd17adaed3b5a54e872a..31e94df84df7eb88df2e53bb175ad23276fe7cf3 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -9,12 +9,6 @@ #ifndef __QEMU_PPCE500_H #define __QEMU_PPCE500_H -#define CONFIG_SYS_MPC85XX_NO_RESETVEC - -#define CONFIG_SYS_RAMBOOT - -#define CONFIG_ENABLE_36BIT_PHYS - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ @@ -29,10 +23,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #endif -/* Virtual address range for PCI region maps */ -#define CONFIG_SYS_PCI_MAP_START 0x80000000 -#define CONFIG_SYS_PCI_MAP_END 0xe0000000 - /* Virtual address to a temporary map if we need it (max 128MB) */ #define CONFIG_SYS_TMPVIRT 0xe8000000 @@ -56,14 +46,10 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_LBA48 - /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -83,7 +69,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index f462895fb5fdea332725f0cd2e2427b9b434f691..d81e5d6c8620df031b6adcdb9f95ee2ed6992ee0 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,20 +8,7 @@ #include -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#endif - #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 @@ -32,7 +19,6 @@ /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ @@ -61,6 +47,5 @@ "pxefile_addr_r=0x8c200000\0" \ "ramdisk_addr_r=0x8c300000\0" \ BOOTENV -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index e9dbd54517fb2121ff5410be55c2c2b0d448cf49..ba843e35a4081e0de199b568aea2462eca8a013e 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -34,6 +34,4 @@ * - AHCI controller is supported for QEMU '-M q35' target */ -#define CONFIG_SPL_BOARD_LOAD_IMAGE - #endif /* __CONFIG_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 54674094e83bc7e22a7f51f96fc6542eaa58b863..409d5af0241df1c90626175885d49d33f6ca9b98 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x8C000000 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_PBSIZE 256 - /* Address of u-boot image in Flash */ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) @@ -27,9 +25,4 @@ */ #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ -/* - * SuperH PCI Bridge Configration - */ -#define CONFIG_SH7751_PCI - #endif /* __CONFIG_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 8e20a448d2a79ea3800023955ce0b0d73ae197aa..49cd11c17b4499e39f74df8465ee62763d87a48a 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -37,13 +37,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ @@ -55,8 +48,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 9bc244349807cf989106aa68766c211e90b04f94..2e5421169046278e1b386a44057b953296a27498 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,16 +10,11 @@ #include -#ifdef CONFIG_SPL -#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" -#endif - #ifndef CONFIG_PINCTRL_PFC #define CONFIG_SH_GPIO_PFC #endif /* console */ -#define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 64743382eda1beb7fe40afcdf66c9c20a2542257..9efda3eeea93d983558c3ff3913a6bbec74656ac 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -11,12 +11,6 @@ #include -#ifdef CONFIG_SPL -#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif" -#endif - -#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K - /* boot option */ /* Generic Interrupt Controller Definitions */ @@ -24,16 +18,12 @@ #define GICC_BASE 0xF1020000 /* console */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 /* MEMORY */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define DRAM_RSV_SIZE 0x08000000 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) @@ -42,22 +32,10 @@ #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* ENV setting */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" -/* SPL support */ -#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965) -#define CONFIG_SPL_BSS_START_ADDR 0xe633f000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 -#else -#define CONFIG_SPL_BSS_START_ADDR 0xe631f000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 -#endif -#define CONFIG_SPL_STACK 0xe6304000 -#define CONFIG_SPL_MAX_SIZE 0x7000 - #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index f4f6bcab5edadbea361c1a768a681de77b0f291a..6616396777a03646c557ed7fab7295dd13d10cfb 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,19 +8,12 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SPL_STACK 0x10081fff - #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -38,6 +31,5 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index be7d644e1e5a4469122c806228da5a7fc44bd887..9297184bded8b8f43494b42c49f1bdb43376f422 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -9,22 +9,12 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_INIT_SP_ADDR 0x78000000 - #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SPL_MAX_SIZE 0x32000 - -#define CONFIG_SPL_STACK 0x1008FFFF - #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -42,6 +32,4 @@ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 8f04e9de5a3f0f47eb41d20a13d84518810864b8..12d4bc65d7e41f6e0ecf32f38f8e16cfc868cc85 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -8,27 +8,15 @@ #include "rockchip-common.h" -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* RAW SD card / eMMC locations. */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#ifndef CONFIG_SPL_BUILD - /* usb mass storage */ #define ENV_MEM_LAYOUT_SETTINGS \ @@ -46,5 +34,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 5c4dfa61e05ab3850d87dc266ab812914f384b7e..6fe1b2d9a2e0da3571dbf77dc8c0c33213480431 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -9,25 +9,14 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - -#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM -/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ -#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 - #define CONFIG_IRAM_BASE 0x10080000 /* spl size 32kb sram - 2kb bootrom */ -#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) - -#define CONFIG_SPL_STACK 0x10087fff #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 -#ifndef CONFIG_SPL_BUILD /* usb otg */ /* usb host support */ @@ -51,6 +40,4 @@ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index f66a7d23be36bd663530e60e448610f1e943bd0c..4fb86b69a8e9ffe39b64cc20fcdd49c352e7d22e 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,22 +8,14 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 -#define CONFIG_SPL_MAX_SIZE 0x100000 - #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -41,6 +33,5 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 075623f342ac3a57d7d90550a67fd1fa09026505..f4b3481115b3bf79cedef9f2c2bf77fc77758705 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,33 +9,18 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ - -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 -#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM -/* Bootrom will load u-boot binary to 0x0 once return from SPL */ -#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SPL_STACK 0xff718000 - #define CONFIG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ -/* FAT sd card locations. */ -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 #define CONFIG_SYS_MONITOR_LEN (600 * 1024) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ @@ -55,6 +40,5 @@ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 44a3e7adf206149d06ef3e53104356a337c6087b..200b34b35baefa02a83897e5fa4220f1b8618cf5 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,27 +8,14 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x00400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_IRAM_BASE 0xfff80000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00800000 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -44,5 +31,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 2b8d77c47ed6e18b68db71def71a0523967c1984..1e214e4ebe15b019ab20b8e4b28e11d363f433a0 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,22 +10,10 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_BSS_START_ADDR 0x2000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* FAT sd card locations. */ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -41,9 +29,3 @@ BOOTENV #endif - -/* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 2f71ce72df8c6045a6c5933922e2946faf279b51..37e0c1d936c36d17c57e60c2f8108e0c7f900090 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -13,20 +13,9 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_SYS_CBSIZE 1024 #define CONFIG_IRAM_BASE 0xff8c0000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 - -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_BSS_START_ADDR 0x400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 -#define CONFIG_SPL_STACK 0x00188000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -42,5 +31,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 8e137376661bdbb3d51b60c41136c568faf12e8f..2f9aee58197b97b503f0f96ef7ce0e3aa7f8ad2a 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,27 +8,13 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_IRAM_BASE 0xff8c0000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 - #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_BSS_START_ADDR 0x00400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #else -#define CONFIG_SPL_STACK 0xff8effff -#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 /* BSS setup */ -#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* MMC/SD IP block */ #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index e9947ea492380be0326efd971fa129baac4e3c4d..15e815234020b12bfc4c928b551b4b9b88cfe04a 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -8,23 +8,11 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_IRAM_BASE 0xfdcc0000 -#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 - -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x4000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "pxefile_addr_r=0x00e00000\0" \ @@ -39,6 +27,5 @@ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index 2edad710284f46458ab9a9c3b2a339b8d0d6e415..6099d2fa55a69edb4f8146c7af89017401c9b98f 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -14,7 +14,4 @@ #include #define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 0c08776ae26877f3aa96f18624de68aa738929ad..4c964cc377087a002f11770bc088ac470d832571 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_NS16550_MEM32 /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ -#define CONFIG_SPL_PAD_TO 8355840 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h index 903e9df527c1fc777af9eecd9b5d8cfb0710913d..9195b9b99e41299eda0e45c46dbfb78c7dbf3aef 100644 --- a/include/configs/rockpro64_rk3399.h +++ b/include/configs/rockpro64_rk3399.h @@ -14,7 +14,4 @@ #include #define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 7a5f0851b53e8a8bfd5488b8db963d54a7491977..4f5025d0da58103c5511b0e587f283be4c8f35c0 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -32,13 +32,6 @@ * the VC uses. */ #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#endif /* Devices */ /* LCD */ @@ -60,7 +53,6 @@ #endif /* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Environment */ diff --git a/include/configs/rut.h b/include/configs/rut.h index b30b12af52c3f238f0cc860b029624adf83719e6..ac48372b6c0ba2272636912075f535766b1671f4 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -21,13 +21,9 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ -#define CONFIG_FACTORYSET - /* Watchdog */ #define WATCHDOG_TRIGGER_GPIO 14 -#ifndef CONFIG_SPL_BUILD - /* Use common default */ /* Default env settings */ @@ -61,10 +57,4 @@ "bootm ${kloadaddr}\0" \ "" -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif - -#endif /* CONFIG_SPL_BUILD */ - #endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index d0f70b04e750d24d0f9b0c17788193118c2f5991..83c3167f38dcd7a3ab64edd401f347adf99dde72 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,22 +10,15 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) /* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "fdt_addr_r=0x61f00000\0" \ @@ -38,4 +31,5 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ BOOTENV + #endif diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 882d19afbf693d6c091a62d743ca3b572c947e89..43593572d963a16ecf20f43f8ec48d5042aabf51 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -18,7 +18,6 @@ /*----------------------------------------------------------------------- * System memory Configuration */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MEM_SIZE 0x40000000 #define CONFIG_SYS_SDRAM_BASE 0x71000000 @@ -77,16 +76,6 @@ */ /* board_init_f->init_sequence, call arch_cpu_init */ -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*----------------------------------------------------------------------- * serial console configuration */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 3b4347dd00bd5fb0d22f7c19932ebd964ec3c69e..712a47a495691ffb783920ab4aac4ed30172e26c 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -10,11 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC110 1 /* which is in a S5PC110 */ - #include #include /* get chip and board defs */ @@ -26,9 +21,6 @@ /* MMC */ #define SDHCI_MAX_HOSTS 4 -/* PWM */ -#define CONFIG_PWM 1 - /* USB Composite download gadget - g_dnl */ #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -121,8 +113,6 @@ "opts=always_resume=1\0" \ "dfu_alt_info=" CONFIG_DFU_ALT "\0" -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ - /* Goni has 3 banks of DRAM, but swap the bank */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ @@ -136,12 +126,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xB0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index ae56c66e15cd9eb98372410da712e3c30cf84d0a..137537d65f6581882bcbf66e75b89c6ec1343f45 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -11,8 +11,6 @@ #include -#define CONFIG_TIZEN /* TIZEN lib */ - /* Keep L2 Cache Disabled */ /* Universal has 2 banks of DRAM */ @@ -21,9 +19,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ #define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT @@ -80,7 +75,6 @@ "verify=n\0" \ "rootfstype=ext4\0" \ "console=console=ttySAC1,115200n8\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "mbrparts=" MBRPARTS_DEFAULT \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ @@ -93,12 +87,8 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); void universal_spi_sda(int bit); diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index eb00e2b004bc222ff9a2f4460fc6f8d8c14f7425..4b0f20e89b7cc455c3cb77ea7c7d85f0a510e40a 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -16,7 +16,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 2708711a4ebc2291d83543a62efd87117545340e..afb1e3d0f105d1537e76aa01e9758a565cb970ed 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -20,12 +20,4 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ - GENERATED_GBL_DATA_SIZE) -#endif - #endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index c965fcb4e8f9a9a3e1296ac97169e912d3b05ed1..b9b56d9f1a046ac0a86aac0e9e9587aaa0110e3d 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -26,10 +26,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ - GENERATED_GBL_DATA_SIZE) - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index b9144584e3ed8f333f2f5fd86c0413b2a9cc6723..0eecb561508ede715696f319841de349e9f36868 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -14,24 +14,8 @@ #undef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index e611e7b51047bfe7006573452db26d1da0e80123..178a6ad4eed529011b1d817701644dce67895d6a 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -19,24 +19,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index c3a5c2ae323b7452738049ca51e8d35634c3e921..b18377be66bfda919860e3be7de7a9893e0ca52a 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -18,13 +18,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ #define FAT_ENV_INTERFACE "mmc" @@ -34,16 +27,7 @@ #endif /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 1ffe35bd875716d679d71688bf3ef08a40e14c55..3b91e83683a6c9fab80cc897e50a6c1eb72f6ad3 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -19,9 +19,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - /* NAND Flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index cab6ae506984d10a39bca6eddaf7f95006087255..bbd72979b56ec47d7a0c4a58944074481947bae2 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -11,24 +11,8 @@ #include "at91-sama5_common.h" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 68bbe8f29c84dfbcfc1c01b8adddaecff05abbfd..fad65cb112343f9668a681da889d4a66a995f1ee 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -27,13 +27,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x318000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -44,42 +37,12 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* size of u-boot.bin to load */ #define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - /* Falcon boot support on raw MMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) /* U-Boot proper stored by default at 0x200 (256 KiB) */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x22000000 - -/* Falcon boot support on FAT on MMC */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" - -/* Falcon boot support on raw NAND */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x1a0000 #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 3be2c83fce0fce700f86f390b548f20071d92a39..7bc3f91e77a80967ebe216cb186b2ac1c4255b9a 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -38,13 +38,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x318000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* SerialFlash */ /* NAND flash */ @@ -57,27 +50,8 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif - /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index e0e0bc6beb7c057a6fff0d38d86032a1c58f7f21..d5cd45ca5c3a75b528baf4f4abaf4298c4d11096 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -33,16 +26,7 @@ #endif /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 2549d4c1a19add690965b8493d6f30f0075eaf10..411ed29ab3cbbfd9a144c4c5a8d187d38dfb319c 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -33,16 +26,7 @@ #endif /* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - #endif diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index bca7166cb9bcc501196579536a4e70b5ec816dcf..3f905bf2d77d48d476027c20176677ea70272da7 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -11,17 +11,8 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ - GENERATED_GBL_DATA_SIZE) -#endif - #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 7b6db46ee173ddbff1245a9e244b88d187b22d94..5168e2fa353121d05e71f95fa48e10bbe0010238 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,14 +6,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifndef CONFIG_SPL_BUILD #define CONFIG_IO_TRACE -#endif #define CONFIG_MALLOC_F_ADDR 0x0010000 -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - /* GUIDs for capsule updatable firmware images */ #define SANDBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x09d7cf52, 0x0720, 0x4710, 0x91, 0xd1, \ diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index 835f05d63e249ac06298862e8ce5318cc8d9befb..af5fe27e68bd04902f6a1462c9c99213b2e756e5 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -22,10 +22,5 @@ "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" /* Size of malloc() pool */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 #endif diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 58345e4e1be7a9c513c76083da4979c1bf1b7164..19701ccce22e3c7b7fb5e1b5b889606b69f685be 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -27,10 +27,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* - * Support large disk for SATA and USB - */ -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 08c4d52d658f673aee2567e13eef4eab6c666c74..d2d4296eed6232dc32a4f807a3c55d88ecdd8c73 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -17,24 +17,13 @@ /* commands to include */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_ROOTPATH "/opt/eldk" -#endif - -#define CONFIG_SYS_AUTOLOAD "yes" /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 32 - /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * memtest works on 8 MB in DRAM after skipping 32MB from @@ -45,11 +34,8 @@ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_SERIAL @@ -61,13 +47,6 @@ /* I2C Configuration */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ @@ -92,24 +71,18 @@ * header. That is 0x800FFFC0--0x80100000 should not be used for any * other needs. */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD - /* USB DRACO ID as default */ #define CONFIG_USBD_HS /* USB Device Firmware Update support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif /* CONFIG_SPL_BUILD */ - /* * Default to using SPI for environment, etc. We have multiple copies * of SPL as the ROM will check these locations. @@ -237,7 +210,7 @@ "nand_active_ubi_vol=rootfs_a\0" \ "nand_active_ubi_vol_A=rootfs_a\0" \ "nand_active_ubi_vol_B=rootfs_b\0" \ - "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_root_fs_type=ubifs rootwait\0" \ "nand_src_addr=0x280000\0" \ "nand_src_addr_A=0x280000\0" \ "nand_src_addr_B=0x780000\0" \ @@ -314,7 +287,7 @@ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ - "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_root_fs_type=ubifs rootwait\0" \ "nand_args=run bootargs_defaults;" \ "mtdparts default;" \ "setenv ${partitionset_active} true;" \ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 96e2eb67988179e1b901f8ed3177900575f6023e..2e5592cf94d5ab2ee52b1c431042707f195e2a5b 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -11,24 +11,7 @@ #include -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x85000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ - GENERATED_GBL_DATA_SIZE) - -#endif - #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 @@ -39,7 +22,6 @@ /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(SF, sf, 0) \ @@ -76,6 +58,5 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV \ BOOTENV_SF -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index fa734a66be7932558167a60d101e47f84025d6e6..9923f3d9c34407d4ee6e9ea0e833595ddc644a99 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -11,30 +11,12 @@ #include -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x85000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ - GENERATED_GBL_DATA_SIZE) - -#endif - #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ @@ -68,7 +50,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/silk.h b/include/configs/silk.h index 574ba228d8a1fc92a9a9517c49224ef5abcb7df7..58613effaf476ce31d9849572e22e4bb603f890c 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -12,10 +12,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -39,7 +38,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __SILK_H */ diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 1cc2992c804565d8407d47090003e22071831226..7159fc35d52b6408443fc588e409c651bb7f8346 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,9 +8,6 @@ #include -/* Start just below the second bank so we don't clobber it during reloc */ -#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE SZ_8M diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index e4e15f92d1bef85112a44a0b9d5eb8942d12cc56..1a3ac817fbfc3cd7156ed851b8e2dc699a771582 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -41,12 +41,6 @@ /* misc settings */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 32 - -/* setting board specific options */ -#define CONFIG_SYS_AUTOLOAD "yes" - /* * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. @@ -72,31 +66,14 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#if !defined(CONFIG_SPL_BUILD) -/* USB configuration */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* USB DFU support */ #define CONFIG_USB_GADGET_AT91 /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif /* General Boot Parameter */ -#define CONFIG_SYS_CBSIZE 512 - -/* - * The NAND Flash partitions: - */ -#define CONFIG_ENV_RANGE (SZ_512K) /* * Predefined environment variables. @@ -106,32 +83,18 @@ \ "basicargs=console=ttyS0,115200\0" \ \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x301000 -#else /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, * leaving the correct space for initial global data structure above that * address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) -#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SZ_4K) - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -150,7 +113,4 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10483f0e -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif /* __CONFIG_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 1ea3b650cd26835b471fb7115511fc5170472b95..c6d2b23197d105feb1f99293ed67dd81dca14382 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -12,7 +12,4 @@ #include #include -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index f26995d5c1c917e9837b641d32b64219c41dea99..12c2e1f6159ac31cc0a526f0fed246e769b75fcb 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -12,16 +12,9 @@ #include #include -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* USB */ -#define CONFIG_USB_XHCI_EXYNOS /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 8eea45450b5c5dab1a913795d0517998ccb39be0..1395b8dfe38b438663a9e85a226ef3bd42295dda 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -11,14 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC100 1 /* which is in a S5PC100 */ - #include /* get chip and board defs */ /* input clock of PLL: SMDKC100 has 12MHz input clock */ @@ -32,9 +24,6 @@ * select serial console configuration */ -/* PWM */ -#define CONFIG_PWM 1 - #define COMMON_BOOT "console=ttySAC0,115200n8" \ " mem=128M " \ " " CONFIG_MTDPARTS_DEFAULT @@ -77,7 +66,6 @@ " console=ttySAC0,115200n8 mem=128M" \ " initrd=0x33000000,8M ramdisk=8192\0" \ "rootfstype=cramfs\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "meminfo=mem=128M\0" \ "nfsroot=/nfsroot/arm\0" \ "bootblock=5\0" \ @@ -87,7 +75,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ @@ -99,26 +86,12 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#endif - /*----------------------------------------------------------------------- * Boot configuration */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xE7100000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - /* * Ethernet Contoller driver */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 9ff05fcca7895b66de4f46bb011aa92819d1efe7..0b1f0c5f54ca8fa83fd0dc286e9479f09c8c4449 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -10,11 +10,7 @@ #include "exynos4-common.h" -#undef CONFIG_USB_GADGET_DWC2_OTG_PHY - /* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ - #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ @@ -44,10 +40,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_ENV_SROM_BANK 1 diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index a7f775660421ae8bf096b9db35ee7f538d80e418..681c831747bacfd5ac7dc122669580f123373b10 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -42,9 +42,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index f7ee9dbac3508905b413418c651432a5621738ae..7adb349f9a54c1b4547054c755de406987d8ba6d 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -23,8 +23,8 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Mem test settings */ @@ -37,15 +37,6 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* GPIOs and IO expander */ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 0e3567f535b4efbc5cbf6cb35ac24e6f4b07d2df..59bba7d143e28642a96beea16b38b4701213d83a 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -23,8 +23,8 @@ /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* Mem test settings */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index ca3da9547cb41932c35d2d719a912e07e5176434..0187fca5f0d95da379070836a14b8f7b56b3b006 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -16,7 +16,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 #define V_NS16550_CLK 48000000 #define V_OSCK 26000000 @@ -34,8 +33,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /* * I2C @@ -51,18 +48,6 @@ * SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_CBSIZE 512 - /* * Serial */ diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index c20d54a3c5b8520fccac7a65e70e2f8c878a1981..f712928d3c86163136887dd924b667a7cbdc5262 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -32,7 +32,6 @@ */ /* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 88fd8ae44cc9a3ccfddb322bb30335d170a79ae3..261ae56c1dcec074d2e8ee02b5afd6f56fcf0234 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -9,7 +9,6 @@ #include #include -#define CONFIG_HUSH_INIT_VAR /* Eternal oscillator */ #define CONFIG_SYS_TIMER_RATE 40000000 @@ -24,8 +23,6 @@ */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - /* Environment settings */ /* @@ -67,8 +64,6 @@ "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ "userload=ubi part nand.ubi &&" \ "ubi check rootfs$bootnum &&" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 5ecd1e6399b4fe60969b15fc85fa0a4c33ca164f..4a7da76e51e611b840adf4114e959d0aa343aaa4 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -14,18 +14,11 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE -#define CONFIG_SPL_PAD_TO 0x10000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SPL_PAD_TO 0x40000 /* SPL memory allocation configuration, this is for FAT implementation */ -#ifndef CONFIG_SYS_SPL_MALLOC_SIZE -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 -#endif #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) #endif /* @@ -37,10 +30,6 @@ #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE))) -#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR -#else -#define CONFIG_SPL_STACK \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) #endif /* @@ -48,22 +37,13 @@ * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage * in U-Boot pre-reloc is higher than in SPL. */ -#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR -#else -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK -#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ /* * Cache @@ -71,20 +51,6 @@ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -/* - * Ethernet on SoC (EMAC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_DW_ALTDESCRIPTOR -#endif - -/* - * FPGA Driver - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA_COUNT 1 -#endif - /* * L4 OSC1 Timer 0 */ @@ -100,7 +66,6 @@ /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 /* @@ -162,16 +127,6 @@ * 0xFFEz_zzzz ...... Malloc area (grows up to top) * 0xFFE3_FFFF ...... End of SRAM (top) */ -#ifndef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE -#endif - -/* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_MMC -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif -#endif /* SPL QSPI boot support */ diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index 468a35d4ff9b243a83faba4a346259e638500deb..ad271791206d546d4a0ef8109040c028f7d61658 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -16,9 +16,4 @@ /* The rest of the configuration is shared */ #include -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - #endif /* __CONFIG_SOCFPGA_IS1_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 3447b8f17c29b6a44337f826bfb75a13d932d3a8..06198ddd82a31265b1c33c3f9fd54af768c2fdd3 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -20,49 +20,19 @@ /* * U-Boot console configurations */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* * U-Boot run time memory configurations */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ - + CONFIG_SYS_INIT_RAM_SIZE \ - - SOC64_HANDOFF_SIZE) -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ - + 0x100000) -#endif -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) /* * U-Boot environment configurations */ -/* - * QSPI support - */ - #ifdef CONFIG_CADENCE_QSPI -/* Enable it if you want to use dual-stacked mode */ -/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ - -/* Flash device info */ - -#ifndef CONFIG_SPL_BUILD -#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" -#endif /* CONFIG_SPL_BUILD */ - -#endif /* CONFIG_CADENCE_QSPI */ - /* * Environment variable */ @@ -118,15 +88,9 @@ * Flash configurations */ -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_DW_ALTDESCRIPTOR -#endif /* CONFIG_CMD_NET */ - /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); @@ -157,21 +121,5 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) * */ -#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ - - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ - - CONFIG_SYS_SPL_MALLOC_SIZE) - -/* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_LOAD_FIT -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -#else -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 62c1bc7408a6c486d1b710ed4e47cd11c0e8454e..432144cb40ce0170f8ab6f0eef9ce97ba14a3406 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -18,11 +18,6 @@ /* Enable SPI NOR flash reset, needed for SPI booting */ #define CONFIG_SPI_N25Q256A_RESET -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* Environment setting for SPI flash */ /* The rest of the configuration is shared */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index c333c931ab7aebfb39a73e5913708857f2965734..70d9f3607a677bd9ab62cfe3373960d901f06f0e 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -11,7 +11,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ /* Booting Linux */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" diff --git a/include/configs/socrates.h b/include/configs/socrates.h index daba8278c6a32fa35619a79cec495e2297fa0bc4..5dc8d8559882f88286b5bf2f3315a7b24a22573c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -22,7 +22,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 /* * sysclk for MPC85xx @@ -103,8 +102,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ @@ -120,15 +118,11 @@ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - /* * General PCI * Memory space is mapped 1-1. */ -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ @@ -228,11 +222,4 @@ /* pass open firmware flat tree */ -/* USB support */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index d4761296c7505ca4401459dbd367b1165ece448a..eeee587bafd558323a7c20607445cf67b166b0ce 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,7 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC @@ -62,19 +61,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 96e759d99cabcd7e1a4f751d36053200aa1f364d..71b25c23b13c77c4ca90b0750bfc510579ab389d 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -13,8 +13,6 @@ * low-level initialization and rely on configuration provided by the Samsung * bootloader. New images are loaded at the same address for compatibility. */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* FIXME: This should be loaded from device tree... */ #define CONFIG_SYS_L2_PL310 diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 3e6feae1fa39f7054e3c52e71d8eb0874ed62729..b1a011bacb22abf4d38f5ca3fd88a009a427a3d1 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -24,8 +24,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -#define CONFIG_SYS_BOOTM_LEN SZ_16M - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ @@ -42,17 +40,7 @@ /* Extra Commands */ -#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN - \ - CONFIG_SYS_GBL_DATA_SIZE) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - /* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 /* NET Configs */ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 21bab5aafd5441e5c2ea895add1391e422ab42a7..18c9e5bfb6eb1743471146e8d541bdc6863a553f 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - /* * Configuration of the external SDRAM memory */ @@ -19,8 +17,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 4c421b9596f2bf5726f17c46cb75880576158636..6849477beafbf00d5ba786cd6903dacb2d2f09c6 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - /* * Configuration of the external SDRAM memory */ @@ -24,8 +22,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index e91f8da280d597e779ef85df7c17edf57923f7b4..2d8b2d27c9254dfde88ff1840e5897dab808d487 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - /* * Configuration of the external SDRAM memory */ @@ -24,8 +22,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index cc3d4b4449deb488c31f9412d0fc06cdc4adcb9d..df05ee4892a50b34eecfb4b47798a30a29d8137a 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x20050000 /* * Configuration of the external SDRAM memory @@ -21,13 +20,8 @@ #define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) -#define CONFIG_DW_ALTDESCRIPTOR - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_SYS_CBSIZE 1024 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -41,21 +35,10 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_SPL_LEN 0x00008000 #define CONFIG_SYS_UBOOT_START 0x080083FD #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_SPL_LEN) -#define CONFIG_SPL_PAD_TO 0x8000 - -/* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x1C0000) -#endif -/* For SPL ends */ + CONFIG_SPL_PAD_TO) /* For splashcreen */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index c43b0d82853fb9e718ff76e22d4868c7bd0bc7ac..f959fcf26f3eaf31b9c31bddeb6e3b939fcaa510 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -14,12 +14,9 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_16M #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_SYS_MAXARGS 16 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index d838449452a0955fcd1f6709088cb17927261986..c8688e9ca7b5b464bcb48d9c20585d04f1d50fa1 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -14,12 +14,9 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_16M #define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_SYS_MAXARGS 16 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index db17939a8c809a9219d823fd7bbb242eafce7b9d..f7fa8c51d8e9b4172cdf57df78902434cee9c23a 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -14,12 +14,9 @@ #define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) #define CONFIG_SYS_FLASH_BASE 0x90000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_SYS_MAXARGS 16 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h new file mode 100644 index 0000000000000000000000000000000000000000..3ca65ea2a37b5a92d1e55f4ef0f26e08aaae72a7 --- /dev/null +++ b/include/configs/stm32mp13_common.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP13x CPU + */ + +#ifndef __CONFIG_STM32MP13_COMMMON_H +#define __CONFIG_STM32MP13_COMMMON_H +#include +#include + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ SZ_256M + +/* Extend size of kernel image for uncompression */ + +/*MMC SD*/ +#define CONFIG_SYS_MMC_MAX_DEVICE 2 + +/* NAND support */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/*****************************************************************************/ +#ifdef CONFIG_DISTRO_DEFAULTS +/*****************************************************************************/ + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) +#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1) +#else +#define BOOT_TARGET_MMC0(func) +#define BOOT_TARGET_MMC1(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_MMC0(func) + +/* + * default bootcmd for stm32mp13: + * for mmc boot (eMMC, SD card), distro boot on the same mmc device + */ +#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#define STM32MP_EXTRA \ + "env_check=if env info -p -d -q; then env save; fi\0" \ + "boot_net_usb_start=true\0" + +#ifndef STM32MP_BOARD_EXTRA_ENV +#define STM32MP_BOARD_EXTRA_ENV +#endif + +#include + +/* + * memory layout for 32M uncompressed/compressed kernel, + * 1M fdt, 1M script, 1M pxe and 1M for overlay + * and the ramdisk at the end. + */ +#define __KERNEL_ADDR_R __stringify(0xc2000000) +#define __FDT_ADDR_R __stringify(0xc4000000) +#define __SCRIPT_ADDR_R __stringify(0xc4100000) +#define __PXEFILE_ADDR_R __stringify(0xc4200000) +#define __FDTOVERLAY_ADDR_R __stringify(0xc4300000) +#define __RAMDISK_ADDR_R __stringify(0xc4400000) + +#define STM32MP_MEM_LAYOUT \ + "kernel_addr_r=" __KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" __FDT_ADDR_R "\0" \ + "scriptaddr=" __SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \ + "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ + "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + STM32MP_MEM_LAYOUT \ + STM32MP_BOOTCMD \ + BOOTENV \ + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV + +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + +#endif /* __CONFIG_STM32MP13_COMMMON_H */ diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h new file mode 100644 index 0000000000000000000000000000000000000000..ec64b12f7ab965c5a4e47396e24ec74fef988fc7 --- /dev/null +++ b/include/configs/stm32mp13_st_common.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STMicroelectronics STM32MP13x boards + */ + +#ifndef __CONFIG_STM32MP13_ST_COMMON_H__ +#define __CONFIG_STM32MP13_ST_COMMON_H__ + +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" \ + "console=ttySTM0\0" + +#include + +#endif diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 6b40cdb01779f69d9a4f761bd2534a9e246f001c..c5412ffeb3104b0d305ccb7ca43873043104490c 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -14,12 +14,6 @@ * Configuration of the external SRAM memory used by U-Boot */ #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* - * Console I/O buffer size - */ -#define CONFIG_SYS_CBSIZE SZ_1K /* * For booting Linux, use the first 256 MB of memory, since this is @@ -28,20 +22,7 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_256M /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M - -/* SPL support */ -#ifdef CONFIG_SPL -/* SPL use DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x01D00000 - -/* Restrict SPL to fit within SYSRAM */ -#define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE) -#define CONFIG_SPL_MAX_FOOTPRINT (STM32_SYSRAM_END - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ - STM32_SYSRAM_SIZE) -#endif /* #ifdef CONFIG_SPL */ + /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 @@ -51,7 +32,6 @@ /* Ethernet need */ #ifdef CONFIG_DWC_ETH_QOS #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_SYS_AUTOLOAD "no" #endif /*****************************************************************************/ @@ -77,7 +57,7 @@ #endif #ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0) +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) #else #define BOOT_TARGET_UBIFS(func) #endif @@ -97,7 +77,7 @@ BOOT_TARGET_PXE(func) /* - * default bootcmd for stm32mp1: + * default bootcmd for stm32mp15: * for serial/usb: execute the stm32prog command * for mmc boot (eMMC, SD card), distro boot on the same mmc device * for nand or spi-nand boot, distro boot with ubifs on UBI partition diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index bb95480eeb26de6380ddd329a3f6003e1e32b489..910d7ef107b574d1af4ab925f7e896e0b49ad9d8 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -33,6 +33,4 @@ #include -#define CONFIG_SPL_TARGET "u-boot.itb" - #endif diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 3c0ffb8f56fe8fa901d01d77155a1426f3df2dab..37b216e6e9f03b77c58d14953df1dbaa00756a6f 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -2,7 +2,7 @@ /* * Copyright (C) 2021, STMicroelectronics - All Rights Reserved * - * Configuration settings for the STMicroelectonics STM32MP15x boards + * Configuration settings for the STMicroelectronics STM32MP15x boards */ #ifndef __CONFIG_STM32MP15_ST_COMMON_H__ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 72f07e1c1c212c0728d7acdfe33371801d42e651..d8a334868f311dd1ffa08fc6cbb26c827989c2b9 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -41,17 +41,8 @@ #define CONFIG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK #define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MBAR 0xFC000000 @@ -62,9 +53,8 @@ /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ +#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) /* @@ -81,7 +71,6 @@ #define CONFIG_SERIAL_BOOT #endif -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) @@ -117,12 +106,4 @@ #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 12) -#ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif #endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h index bcc6fcd36b30d02ea350ad3e58d57d9e16c2afe4..f49e88cb17cbc17e08c8f463ac09abd26015d27d 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -13,10 +13,9 @@ #include "rcar-gen2-common.h" -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 #define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 @@ -43,7 +42,5 @@ "bootm_size=0x10000000\0" /* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 #endif /* __STOUT_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 137672909bebd6474e6ed136fc3fa37d7e3be284..567aa1ffe4331bb97d37d4d7b6d778dae047db35 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -14,20 +14,11 @@ #define PHYS_SDRAM_1_SIZE 0x00198000 /* user interface */ -#define CONFIG_SYS_CBSIZE 1024 /* MISC */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* U-Boot Load Address */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* GMAC related configs */ - -#define CONFIG_DW_ALTDESCRIPTOR /* Misc configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 068340aa96499ef917b953141ed3ff504e0cd856..0f0ef4f64bbfe3fe7a5bd0b8c7a7628d35068402 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -15,10 +15,6 @@ #include #include -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) -#endif - /* Serial & console */ #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ @@ -49,20 +45,15 @@ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 #elif defined(CONFIG_MACH_SUNIV) #define SDRAM_OFFSET(x) 0x8##x #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SPL_BSS_START_ADDR 0x81f80000 #else #define SDRAM_OFFSET(x) 0x4##x #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* V3s do not have enough memory to place code at 0x4a000000 */ -#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 #endif -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ - /* * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * slightly bigger. Note that it is possible to map the first 32 KiB of the @@ -77,18 +68,9 @@ /* FIXME: this may be larger on some SoCs */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -#ifdef CONFIG_AHCI -#define CONFIG_SYS_64BIT_LBA -#endif - #ifdef CONFIG_NAND_SUNXI #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SYS_MAX_NAND_DEVICE 8 @@ -102,8 +84,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ /* standalone support */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR @@ -117,7 +97,6 @@ * autoconf.mk. */ #if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ #ifdef CONFIG_ARM64 /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ #define LOW_LEVEL_SRAM_STACK 0x00054000 @@ -126,33 +105,17 @@ #endif /* !CONFIG_ARM64 */ #elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 #ifdef CONFIG_MACH_SUN50I_H616 -#define CONFIG_SPL_MAX_SIZE 0xbfa0 /* 48 KiB */ #define LOW_LEVEL_SRAM_STACK 0x58000 #else -#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ /* end of SRAM A2 on H6 for now */ #define LOW_LEVEL_SRAM_STACK 0x00118000 #endif #else -#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #endif -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#ifndef CONFIG_MACH_SUN50I_H616 -#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ -#endif - /* Ethernet support */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_ARM64 /* * Boards seem to come with at least 512MB of DRAM. @@ -345,20 +308,6 @@ "stderr=serial\0" #endif -#ifdef CONFIG_MTDIDS_DEFAULT -#define SUNXI_MTDIDS_DEFAULT \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" -#else -#define SUNXI_MTDIDS_DEFAULT -#endif - -#ifdef CONFIG_MTDPARTS_DEFAULT -#define SUNXI_MTDPARTS_DEFAULT \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define SUNXI_MTDPARTS_DEFAULT -#endif - #define PARTS_DEFAULT \ "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ @@ -390,16 +339,10 @@ DFU_ALT_INFO_RAM \ "fdtfile=" FDTFILE "\0" \ "console=ttyS0,115200\0" \ - SUNXI_MTDIDS_DEFAULT \ - SUNXI_MTDPARTS_DEFAULT \ "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ BOOTCMD_SUNXI_COMPAT \ BOOTENV -#else /* ifndef CONFIG_SPL_BUILD */ -#define CONFIG_EXTRA_ENV_SETTINGS -#endif - #endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 5686a5b9104ee89c9788b29d84d5dc7af0085a73..63d897d090af24edad171a5f2eb9708478585c5a 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -22,7 +22,6 @@ /* * Boot info */ -#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ /* * Hardware drivers support @@ -40,10 +39,6 @@ #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 128 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ @@ -65,7 +60,6 @@ 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30) /* Distro boot settings */ -#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) #else @@ -97,9 +91,6 @@ BOOT_TARGET_DEVICE_NVME(func) \ #include -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x9fe00000\0" \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 77d80bfc9813009604e10ac0939b447550e9258b..4758e23f55724c7ca690646976de15c555f780d6 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -49,8 +49,8 @@ * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -63,16 +63,7 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif -/* USB */ #if defined(CONFIG_BOARD_TAURUS) -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* USB DFU support */ #define CONFIG_USB_GADGET_AT91 @@ -84,13 +75,8 @@ /* SPI EEPROM */ #define TAURUS_SPI_MASK (1 << 4) -#if defined(CONFIG_SPL_BUILD) -/* SPL related */ -#endif - /* bootstrap in spi flash , u-boot + env + linux in nandflash */ -#ifndef CONFIG_SPL_BUILD #if defined(CONFIG_BOARD_AXM) #define CONFIG_EXTRA_ENV_SETTINGS \ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ @@ -139,21 +125,10 @@ "stdout=serial\0" \ "upgrade_available=0\0" #endif -#endif /* #ifndef CONFIG_SPL_BUILD */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (31 * SZ_512) -#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512) #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -172,7 +147,4 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10193F05 -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - #endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 09766fea27a300d87aab10afac5d927d06121483..16bdc39b750ebb1863f432617b7685b1ab360d3d 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -16,11 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_32M - /* * UART configuration */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b7a94812f3548475be75e64e6a5bef52546e2212..c93df00d58dcde766ed1c7372e739dc31ca08d3a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -17,38 +17,20 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_BOOTMAPSZ 0x10000000 -/* Serial console */ -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif -/* SATA */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA -#endif - /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #ifdef CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USBD_HS diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 755a41fef7e2f1200112f0921f94029cd2a6afd1..c8f9d7cb175c267cb78076015923e8e209884316 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#ifndef CONFIG_SPL_BUILD - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -26,9 +24,6 @@ func(DHCP, dhcp, na) #endif #include -#else -#define BOOTENV -#endif #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 99b7bd07aa0f54aaac715921e3a2976698024084..159ba093f2999615fede1926a7c709d12d7ee015 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -35,17 +35,6 @@ */ #define CONFIG_SYS_MMC_MAX_DEVICE 4 -/* - * Increasing the size of the IO buffer as default nfsargs size is more - * than 256 and so it is not possible to edit it - */ -#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - #ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" #else @@ -65,16 +54,8 @@ #ifndef CONFIG_ARM64 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#endif -#ifndef CONFIG_ARM64 /* Defines for SPL */ -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 #endif #endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 09737211803b2210c6c6e518265a0db66f2034fe..87ec1f5a99d63e53ee900ab3a1f3c2657708e6b0 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -54,10 +54,5 @@ "ramdisk_addr_r=0x83100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index df688dabd1ab15c3a84cba6e9e24b00b15fdc12a..0485fea6ccb88af97f56a678c918788786473c25 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -56,13 +56,5 @@ "ramdisk_addr_r=0x83100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU #endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index fac8692728576da5f632c350a5fc4721992a9861..71867bb6baac5c124fae1110311fb95d74f2121d 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -55,8 +55,6 @@ "ramdisk_addr_r=0x03100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 -#define CONFIG_SPL_STACK 0x000ffffc /* Align LCD to 1MB boundary */ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE @@ -71,12 +69,4 @@ #define TEGRA_LP0_VEC #endif -/* - * This parameter affects a TXFILLTUNING field that controls how much data is - * sent to the latency fifo before it is sent to the wire. Without this - * parameter, the default (2) causes occasional Data Buffer Errors in OUT - * packets depending on the buffer address and size. - */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - #endif /* _TEGRA20_COMMON_H_ */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 3ba12bec0eedc8cb701ee958a1a9ec8a9c37aa06..7f361d874af8ad7bc78b96bad72a88c6bfc4e41b 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,10 +46,4 @@ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83420000\0" -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU - #endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index b878b1a9e699c4272325f340548472a4acc1a326..04fcf11ed82d12ee2e327f9b417be2b62cda9de8 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -51,10 +51,5 @@ "ramdisk_addr_r=0x83100000\0" /* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index fdf048b27b3c40d5499145bef02e6ba4e7c6f474..655fcb0011b0f51ba78c2ed6e5961cb4b0f6db42 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -29,7 +29,6 @@ #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ @@ -40,12 +39,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SATA support */ -#define CONFIG_LBA48 - -/* FPGA programming support */ -#define CONFIG_FPGA_STRATIX_V - /* * Bootcounter */ @@ -73,17 +66,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_SDRAM_SIZE SZ_2G diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 3b120073fef0d7b5c5058212c38f48d405202e1c..696306e46592d3329ee39438532e24038dd5c495 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -30,13 +30,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ @@ -48,8 +41,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_THUBAN_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 3537ba30e1f597bd029b7a94b1762710fd44f5f7..cf2efdbe230b04b52b712a8f3c976b25e9ccb91d 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -6,16 +6,11 @@ #ifndef __THUNDERX_88XX_H__ #define __THUNDERX_88XX_H__ -#define CONFIG_THUNDERX - -#define CONFIG_SYS_64BIT - #define MEM_BASE 0x00500000 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) /* SMP Spin Table Definitions */ #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) @@ -47,9 +42,6 @@ /* Do not preserve environment */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ #define PLL_REF_CLK 50000000 /* 50 MHz */ #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 95434aa5169b0026bb82541fd55fb9f274e74c21..97166e010f7d2256fa236e7d65d7fa1bb2dec622 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -62,7 +62,6 @@ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 /** * Physical Memory Map @@ -71,14 +70,11 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) /** * Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x4802E000 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_SERIAL @@ -89,13 +85,6 @@ /* CPU */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 @@ -105,8 +94,6 @@ * header. That is 0x800FFFC0--0x80800000 should not be used for any * other needs. */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index c2dfdebcd5b6a9ba5bed923459178b8a7f0d8bd8..1aca83a9bcebe776d06b691ce0275ebe13278eb3 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -13,9 +13,7 @@ #include #define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + DEFAULT_LINUX_BOOT_ENV /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ @@ -28,7 +26,6 @@ * Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x4802E000 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* * NS16550 Configuration @@ -65,7 +62,5 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) #endif diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index f8bd5558e56af2213ff9fc48ad02cc2f0e1ce9fb..5d5df6b10191907d49a20c3799844f868057e38e 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -32,8 +32,6 @@ * supports X-MODEM loading via UART, and we leverage this and then use * Y-MODEM to load u-boot.img, when booted over UART. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) /* Enable the watchdog inside of SPL */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 7483bc821d31b0cd72c119fb52d411e7e73b09d8..2d1f0372ae359127969cafe3095f691ea852fef1 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -66,14 +66,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -#endif - -/* Timer information. */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - /* If DM_I2C, enable non-DM I2C support */ /* @@ -88,14 +80,7 @@ /* As stated above, the following choices are optional. */ -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * When we have SPI, NOR or NAND flash we expect to be making use of * mtdparts, both for ease of use in U-Boot and for passing information @@ -128,34 +113,11 @@ * of the BSS area. We suggest that the stack be placed at 32MiB after the * start of DRAM to allow room for all of the above (handled in Kconfig). */ -#ifndef CONFIG_SPL_BSS_START_ADDR -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#endif -#ifndef CONFIG_SYS_SPL_MALLOC_START -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M -#endif -#ifndef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#endif - - -/* FAT sd card locations. */ -#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif #ifdef CONFIG_SPL_OS_BOOT /* FAT */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" /* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ #endif /* General parts of the framework, required. */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 57f013cbf846dd422f9a615e42ca68c59b64a73e..29a6038f8985985e959ee269b16d402140ad6c2e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -12,13 +12,10 @@ /* U-Boot Build Configuration */ /* SoC Configuration */ -#define CONFIG_SPL_TARGET "u-boot-spi.gph" /* Memory Configuration */ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ - GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_SYS_MALLOC_F_LEN #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN @@ -27,22 +24,10 @@ #endif /* SPL SPI Loader Configuration */ -#define CONFIG_SPL_PAD_TO 65536 -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) #define KEYSTONE_SPL_STACK_SIZE (8 * 1024) -#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ - CONFIG_SYS_SPL_MALLOC_SIZE + \ - SPL_MALLOC_F_SIZE + \ - KEYSTONE_SPL_STACK_SIZE - 4) /* SRAM scratch space entries */ -#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 +#define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc #define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) @@ -74,14 +59,6 @@ #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -/* I2C Configuration */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ - /* EEPROM definitions */ /* NAND Configuration */ @@ -180,7 +157,7 @@ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait " \ KERNEL_MTD_PARTS \ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ @@ -199,9 +176,7 @@ "args_ramfs=setenv bootargs ${bootargs} " \ "rdinit=/sbin/init rw root=/dev/ram0 " \ "initrd=0x808080000,80M\0" \ - "no_post=1\0" \ - "mtdparts=mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + "no_post=1\0" /* Now for the remaining common defines */ #include diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3d7cb175faa6b2892da19c8c9b2490b31639e64b..725a5a62f5252d069128d6707f1af4b5611a291e 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -55,8 +55,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* SPL */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (64 << 20)) #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_BASE 0x30000000 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index b5ccfdcc6d46623147e2aa08613dacf4f6b83455..3d78972bfebb3c9e3dee7a9f69c7014015c817e2 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -23,17 +23,6 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - #include /* @@ -47,9 +36,7 @@ #endif /* TWL6030 */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6030_POWER 1 -#endif /* * Environment setup @@ -113,8 +100,6 @@ * SPL is overlapped with public stack and breaking non HS devices to boot. * So moving TEXT_BASE down to non-HS limit. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) #ifdef CONFIG_SPL_BUILD /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 714a1c55c7fb2e04cbd65ef22addcd72e9da0b8a..24bbf9e7c2c6c20f03ba639d130209607add6871 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -19,19 +19,6 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#define CONFIG_PALMAS_POWER - #include #include @@ -305,7 +292,4 @@ */ #endif -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) - #endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index f859656b396cabfe571d5960af1b8a06ba5e84a9..83abaeddf125703f7902b183c917100b3baf242d 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -16,11 +16,6 @@ /* Fixup settings */ -/* SPL settings */ -#undef CONFIG_SPL_MAX_FOOTPRINT -#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - /* Setup proper boot sequences for Miami boards */ #if defined(CONFIG_USB_HOST) diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index 0324b1e1b2170613d4e62cfe4cea88abcbcebfba..4fb3d731c67ab53bb8275dc2e18447a6082d8bc8 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -10,9 +10,6 @@ #define __TOTAL_COMPUTE_H /* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) #define UART0_BASE 0x7ff80000 @@ -46,16 +43,10 @@ * Else boot FIT image. */ -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #define CONFIG_SYS_FLASH_BASE 0x0C000000 /* 256 x 256KiB sectors */ #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define FLASH_MAX_SECTOR_SIZE 0x00040000 diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 21c351a816e6626899bee1de26c391579c36c867..f5466fd5092daf89101f25b2458c99a19ff24d9e 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -9,14 +9,10 @@ #define CONFIG_SYS_MHZ 280 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - #define CONFIG_SYS_SDRAM_BASE 0xa0000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) /* * Serial Port @@ -27,14 +23,6 @@ * Command */ /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* USB, USB storage, USB ethernet */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN /* * Diagnostics diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index e0cd1ec25182e131dadf2e272f05e253feb2b2c0..a782e3d02bdbca2ffe47313ed5b3ee6aa15e3f01 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -52,9 +52,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - #if defined(CONFIG_TQMA6X_MMC_BOOT) @@ -286,11 +283,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * All the defines above are for the TQMa6 SoM * diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 90db96599c1ba59e3842f8e9afd04e8121ca40f7..999130600ccb4cd44c74db76819ade186acb0fe5 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -24,9 +24,6 @@ /* LED */ -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* I2C */ #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 910fc150b18b08075cc807476d5437054260a251..53f5a6996bd77a6c6a365e913806c58d43b78edc 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -11,10 +11,6 @@ #include -#define CONFIG_TRATS - -#define CONFIG_TIZEN /* TIZEN lib */ - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -25,9 +21,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" @@ -130,13 +123,9 @@ "fdtaddr=40800000\0" \ /* Falcon mode definitions */ -#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 /* GPT */ -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -160,8 +149,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 3e121bc6909a5179f29e2481b73defcbb778f75c..b7449dab8bdb4d5364ccd50841378b38653d3a07 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -12,8 +12,6 @@ #include -#define CONFIG_TIZEN /* TIZEN lib */ - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -24,9 +22,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" @@ -121,9 +116,6 @@ /* GPT */ -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -147,8 +139,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 6640ee495d256f3bfb1bcdce2a899f8786d81a87..401627a47a2f83971026694066602dba11a71a83 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,11 +8,7 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H -#define CONFIG_SYS_BOOTM_LEN (64 << 20) #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 32 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ @@ -21,8 +17,6 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -#define CONFIG_USB_MAX_CONTROLLER_COUNT 6 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(NVME, nvme, 0) \ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 8119340b112f9d8acf5d462e685fdcbca3ec932b..9013d9a6932589463be989e081bf129ac49b781d 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -26,23 +26,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -/* SPL related MMC defines */ -# ifdef CONFIG_SPL_BUILD -# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -# endif -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 4bddc0eca30eab4c1e60526629d7110789d88eca..03e5c04af6ee17b5877e31f43eb42e9a5a65da57 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -14,9 +14,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -/* SATA Configs */ -#define CONFIG_LBA48 - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -58,11 +55,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #endif /* __CONFIG_H * */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 3a7cb050b1073691d76bef244d824e416a457273..e30b6cc82d8be61edb579971f869b9e1b6b7e093 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -63,11 +63,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* PMIC */ #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 14ea40bee3edd79f4e88105a2b13812be65a198b..578873295fb9d0db036849139cbbdb5689eb49a5 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -16,7 +16,6 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index f813f88cdd7a0d8e4fb8e874683d2f2cb2e9446e..15ae0844c1a7ab86d5a2864da01bc2af8ddcf779 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_UNIPHIER_H__ #define __CONFIG_UNIPHIER_H__ -#ifndef CONFIG_SPL_BUILD #include #ifdef CONFIG_CMD_MMC @@ -20,7 +19,7 @@ #endif #ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0) +#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) #else #define BOOT_TARGET_DEVICE_UBIFS(func) #endif @@ -35,16 +34,9 @@ BOOT_TARGET_DEVICE_MMC(func) \ BOOT_TARGET_DEVICE_UBIFS(func) \ BOOT_TARGET_DEVICE_USB(func) -#else -#define BOOTENV -#endif #define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - #if !defined(CONFIG_ARM64) /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 @@ -62,8 +54,6 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) - #if defined(CONFIG_ARM64) /* ARM Trusted Firmware */ #define BOOT_IMAGES \ @@ -177,19 +167,9 @@ #define CONFIG_SYS_BOOTMAPSZ 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) - /* only for SPL */ -#define CONFIG_SPL_STACK (0x00100000) /* subtract sizeof(struct image_header) */ #define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - -#define CONFIG_SPL_PAD_TO 0x20000 - #endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 2b6078a1cc9a71c4ecb7c33f432b009c4cd954fd..e0dde1cc83658ebc7a9b769dcac5d4ab370d5ac8 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -28,8 +28,8 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -43,18 +43,7 @@ #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* bootstrap + u-boot + env + linux in dataflash on CS0 */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 0faa656bc63afb2b927f5d6577f265ff587bbf08..2632d56cb1c291ad7f9a8835845edcdfbbb8e85b 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -15,7 +15,6 @@ /* U-Boot environment */ /* U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 512 /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE @@ -66,9 +65,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 88c3061db632dea70b12ee6de689f69c5a11fbc9..78a62a8b028cff8a5f1b82b8b3d5cb199fcd440b 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -32,18 +32,7 @@ #error Unknown DDR size - please add! #endif -#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) -#define VCOREIII_DEFAULT_MTD_ENV \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" -#else -#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - #define CONFIG_EXTRA_ENV_SETTINGS \ - VCOREIII_DEFAULT_MTD_ENV \ "loadaddr=0x81000000\0" \ "spi_image_off=0x00100000\0" \ "console=ttyS0,115200\0" \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 558b78115dfdf225c49702dd668a1347bc4eb76d..5b5fce9bda177d72e66f9b1fbcca4a4a1f235fe9 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,24 +9,14 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ @@ -36,15 +26,11 @@ "scriptaddr=0x46000000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -68,10 +54,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #if defined(CONFIG_ENV_IS_IN_MMC) /* Environment in eMMC, before config block at the end of 1st "boot sector" */ @@ -83,22 +65,10 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - /* ENET */ #define CONFIG_FEC_MXC_PHYADDR 7 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 52fa2be3ab185d598992a6d9820f57acaf4c26f0..fca40beba18a00decfb9ee9576c1130ce0673cf8 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,23 +9,16 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 @@ -47,15 +40,11 @@ "scriptaddr=0x46000000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include -#else -#define BOOTENV -#endif #if defined(CONFIG_TDX_EASY_INSTALLER) # define BOOT_SCRIPT "boot-tezi.scr" @@ -85,12 +74,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -99,14 +82,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #endif /* __VERDIN_IMX8MP_H */ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 0632b367cad88e00b929c8f8657fd628f953684f..3705313aec064a56619af2d9da412cc96d1ea7d1 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -11,14 +11,10 @@ /* Link Definitions */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) #else /* ATF loads u-boot here for BASE_FVP model */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - /* CS register bases for the original memory map. */ #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP #define V2M_DRAM_BASE 0x00000000 @@ -263,10 +259,6 @@ EXTRA_ENV_NAMES \ BOOTENV -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_SYS_FLASH_BASE 0x08000000 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ @@ -280,13 +272,6 @@ /* Store environment at top of flash */ #endif -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define FLASH_MAX_SECTOR_SIZE 0x00040000 diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 599caaca17dc996f8764202017ab86e15b61166e..ff7307f09044230f25b7b7017a5a3a6b8f9d161f 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -139,10 +139,6 @@ /* additions for new relocation code */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET /* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ @@ -197,7 +193,4 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ CONFIG_SYS_FLASH_BASE1 } -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - #endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index ec9049e1b3d8222781dea100f6e57b038e452b46..32d9df0a00ce5dc6b1d5e22b55c0c9fa11a01cd2 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -26,7 +26,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ -#define CONFIG_SYS_SPD_BUS_NUM 0 /* * We do have 128MB of memory on the Vybrid Tower board. Leave the last @@ -130,13 +129,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - #endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 74eccfa2e64412150317d8e7751d56c193d2acb9..a157296761841a8cd466ea8015cbefa96aed9a4b 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -27,9 +27,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x4000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - /* MMC */ #ifdef CONFIG_CMD_MMC diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index e7d4fd16cc7c5b303000780b01609489fe83394d..6eb022f26c5f6298cdd1bc766d9b02888570dc98 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -31,11 +31,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR @@ -46,14 +41,10 @@ /* Network */ #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 7e3d589e3fdea9c17099f39a1b1c15d67cd804f5..6a7a0832c9533aea04e350d1fa5ff46e7363446e 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -17,10 +17,6 @@ /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80010000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -33,11 +29,6 @@ /* RAM */ -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - /* Environment settings */ #endif //__VOCORE2_CONFIG_H__ diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h index a51b169c618b908afd2266901bc0cc2130acb8a6..e8c1013a71a35e7e862388e237941b0de16c4ca8 100644 --- a/include/configs/vyasa-rk3288.h +++ b/include/configs/vyasa-rk3288.h @@ -22,13 +22,8 @@ #ifndef CONFIG_TPL_BUILD /* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x0ffe5000 /* Falcon Mode - MMC support: args@16MB kernel@17MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8000 /* 16MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) #endif #endif diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index d44b4a0750f453b357f3efd4e559244e9de38fdc..899b8ca470e242ab64b524572b9050b6cca7d95b 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -14,14 +14,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -/* SATA Configs */ - -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -103,11 +95,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment organization */ #endif /* __CONFIG_H * */ diff --git a/include/configs/warp.h b/include/configs/warp.h index 8bdda377088fdcc633a06bc7f9d5c4dac6fc0c28..7cb9743fddb3a561d7242850579c9654da1d404e 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -29,20 +29,13 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* VDD voltage 1.65 - 1.95 */ #define CONFIG_SYS_SD_VOLTAGE 0x00000080 /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ #endif #define CONFIG_USBD_HS diff --git a/include/configs/warp7.h b/include/configs/warp7.h index b3c9f14c8f4e3e1b2170c777e25f70761af923c4..c00ca4a111724fd057bcf56b27bb990094c0884d 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -89,11 +89,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* environment organization */ #define CONFIG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 332453759791e4300796ee3d92147a152f8fd6e0..8d1eee2fcac801466e0d765e5b165ec10ec80727 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -19,16 +19,11 @@ #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - - GENERATED_GBL_DATA_SIZE) - #define CONFIG_RTC_DS1374 /* * U-Boot General Configurations */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * NAND chip timings for FIXME: which one? @@ -65,11 +60,9 @@ /* SPL will be executed at offset 0 */ /* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 /* Use the framework and generic lib */ /* SPL will use serial */ /* SPL will load U-Boot from NAND offset 0x40000 */ -#define CONFIG_SPL_PAD_TO 0x20000 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/x530.h b/include/configs/x530.h index 67ff01db90416f8832c490a1a95578bcd09e1ba4..cb126837b9ca3e5ec955c89a191841e4ebec0fd8 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -47,11 +47,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ #include @@ -64,20 +59,4 @@ #define CONFIG_UBI_PART user #define CONFIG_UBIFS_VOLUME user -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - (CONFIG_SPL_TEXT_BASE - 0x40000000)) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - #endif /* _CONFIG_X530_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b45d2bbd62663f738765cc0ff829a5541dea610a..4109af7d8511bcc28299283e1f4171f4a9a022c4 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -12,18 +12,6 @@ #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index a22f97042f7e2c341943554ae140f1fe12e574ee..42b2cb2fc85a230e6a610e1522b8b1c0d0d042f9 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -14,14 +14,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* SATA AHCI storage */ -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#endif /* Generic TPM interfaced through LPC bus */ #define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 @@ -40,7 +32,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /*----------------------------------------------------------------------- * CPU Features @@ -52,11 +43,6 @@ * Environment configuration */ -/*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE - /*----------------------------------------------------------------------- * USB configuration */ diff --git a/include/configs/xea.h b/include/configs/xea.h index 01942eaf2ba5cd37c5a9e0a2024693a15e71fb82..19ccf633c404fa51ea8489be8a666d75ebf28129 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -15,17 +15,11 @@ #include /* SPL */ -#define CONFIG_SPL_STACK 0x20000 - -#define CONFIG_SYS_SPL_ARGS_ADDR 0x44000000 #define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M #define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K #define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (SZ_512K / 0x200) -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200) - /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 408c7b5dd695ef25ee36a65fd174a6f63e5d9779..364dae0cd9340105dfd82180688fc1b6abf8bf51 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -13,13 +13,6 @@ #undef CONFIG_SYS_SDRAM_BASE -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index b78c2429489a58f12c32189bf1a855bfe989e4d0..971bd69dec8d4f07c9c23197276f7c914f757516 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -14,8 +14,6 @@ #define GICD_BASE 0xF9000000 #define GICR_BASE 0xF9080000 -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - /* Serial setup */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } @@ -27,11 +25,7 @@ /* Miscellaneous configurable options */ -/* Monitor Command Prompt */ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -43,8 +37,6 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ "fdt_size_r=0x400000\0" \ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index a94ab1fd2074c7c2664263e827886efe193eac50..e1f95de3c34fb083c3949ecc1c957d5c1421932f 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -17,7 +17,4 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - #endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h index 8572b8b3d2dc3bb753290b25c5335c949b95c3f6..e2f2df293540ce9c743ca3992facf5eb0329b75c 100644 --- a/include/configs/xilinx_versal_mini_qspi.h +++ b/include/configs/xilinx_versal_mini_qspi.h @@ -12,7 +12,4 @@ #include -#undef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) - #endif /* __CONFIG_VERSAL_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f25d796a1e723829005d04b2bc22b48e29dd70a1..f72f3e644768005a628078f48bc2f4ebc7213b71 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -14,8 +14,6 @@ #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - /* Serial setup */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } @@ -39,31 +37,23 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF -#ifndef CONFIG_SPL_BUILD # define PARTS_DEFAULT \ "partitions=uuid_disk=${uuid_gpt_disk};" \ "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \ "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0" #endif -#endif #if !defined(PARTS_DEFAULT) # define PARTS_DEFAULT #endif -/* Monitor Command Prompt */ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM) # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ "fdt_size_r=0x400000\0" \ @@ -205,13 +195,6 @@ "dfu_bufsiz=0x1000\0" #endif -#define CONFIG_SPL_STACK 0xfffffffc -#define CONFIG_SPL_MAX_SIZE 0x40000 - -/* Just random location in OCM */ -#define CONFIG_SPL_BSS_START_ADDR 0x0 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) # define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 # define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 @@ -219,28 +202,8 @@ #endif /* u-boot is like dtb */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 /* ATF is my kernel image */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" - -/* MMC support */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ -# if defined(CONFIG_SPL_LOAD_FIT) -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -# define CONFIG_SPL_HASH -# define CONFIG_ENV_MAX_ENTRIES 10 -#endif - -#define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index baef561c0b5d228f9375afb6ada6caf819b65e57..1c0ab25c64401ab452cca717d527ceeb4fabd041 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -16,9 +16,5 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_INIT_SP_ADDR - -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 #endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h index 57c40d61020414edd1ae90b3ec9b64407719a1e1..f423ddd08ec5e0c0ff68eb9127d5a270094a8c26 100644 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ b/include/configs/xilinx_zynqmp_mini_emmc.h @@ -12,6 +12,4 @@ #include -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 782e69616821af27234df61e51c1e5bef3a7a3b2..d2c0e91b32e0815e3c98ebc1e84f61944b167912 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -14,6 +14,5 @@ #define CONFIG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h index 3091bae051181a85cffb00de52f33d387e963ae2..5bea1c9908c7b67526e64fdfaeee51ed1f81bde2 100644 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ b/include/configs/xilinx_zynqmp_mini_qspi.h @@ -12,6 +12,4 @@ #include -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) - #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 3ec99e062df5f8ca319e285dc783e65798d8522e..b6bc402a7e979210d02c4f12335b99fc69087c60 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -15,15 +15,9 @@ /* Boot configuration */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index bd39b328a67688cd7ce35b2c0d0569ddffb5dd76..0e43b373649aaaf25209800ea3d5df1a21409f28 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -28,18 +28,11 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* Environment is in stored in the eMMC boot partition */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 92e5b436a32766681c85fb1b4b3e12d53f22e498..f1ea47654671f187e842ae8bc30a170ed4e5eb3b 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -16,12 +16,6 @@ * differences. */ -/*=====================*/ -/* Board and Processor */ -/*=====================*/ - -#define CONFIG_XTFPGA - /*===================*/ /* RAM Layout */ /*===================*/ @@ -62,9 +56,6 @@ # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ #endif -/* Linux boot param area in RAM (used only when booting linux) */ -#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) - /* Memory test is destructive so default must not overlap vectors or U-Boot*/ /* Load address for stand-alone applications. @@ -98,10 +89,6 @@ /*==============================*/ /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /*==============================*/ /* U-Boot autoboot configuration */ /*==============================*/ @@ -177,7 +164,6 @@ /* Flash & Environment */ /*=====================*/ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #ifdef CONFIG_XTFPGA_LX60 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bd88b59f24222084fbe1b6f0d3ac7528c04af9b9..1fdde90654f259e6e5c5437faa62cd56146b5d6e 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -199,36 +199,18 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ #define CONFIG_SYS_MMC_MAX_DEVICE 1 -/* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - /* Address in RAM where the parameters must be copied by SPL. */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 - -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" /* Not using MMC raw mode - just for compilation purpose */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI @@ -241,21 +223,13 @@ /* SP location before relocation, must use scratch RAM */ /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ -#define CONFIG_SPL_MAX_SIZE 0x30000 /* On the top of OCM space */ -#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000 /* * SPL stack position - and stack goes down * 0xfffffe00 is used for putting wfi loop. * Set it up as limit for now. */ -#define CONFIG_SPL_STACK 0xfffffe00 - -/* BSS setup */ -#define CONFIG_SPL_BSS_START_ADDR 0x100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 #endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 7eafdfd9a6536251dbab7b6c8480180c1d7a3879..cb982c2e74f6f9deeef3ad0fd5d32d4c72faf981 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -14,17 +14,9 @@ /* Undef unneeded configs */ #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_CBSIZE 1024 - #undef CONFIG_SYS_INIT_RAM_ADDR #undef CONFIG_SYS_INIT_RAM_SIZE #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#undef CONFIG_SPL_BSS_START_ADDR -#undef CONFIG_SPL_BSS_MAX_SIZE -#define CONFIG_SPL_BSS_START_ADDR 0x20000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 #endif /* __CONFIG_ZYNQ_CSE_H */ diff --git a/include/dm/device.h b/include/dm/device.h index 5bdb10653f8e3725f55e6692da301f5171bf1ff1..12c6ba37ff37070ee5b2a0e05a6b0e972722419f 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -11,6 +11,7 @@ #define _DM_DEVICE_H #include +#include #include #include #include @@ -546,6 +547,30 @@ void *dev_get_parent_priv(const struct udevice *dev); */ void *dev_get_uclass_priv(const struct udevice *dev); +/** + * dev_get_attach_ptr() - Get the value of an attached pointed tag + * + * The tag is assumed to hold a pointer, if it exists + * + * @dev: Device to look at + * @tag: Tag to access + * @return value of tag, or NULL if there is no tag of this type + */ +void *dev_get_attach_ptr(const struct udevice *dev, enum dm_tag_t tag); + +/** + * dev_get_attach_size() - Get the size of an attached tag + * + * Core tags have an automatic-allocation mechanism where the allocated size is + * defined by the device, parent or uclass. This returns the size associated + * with a particular tag + * + * @dev: Device to look at + * @tag: Tag to access + * @return size of auto-allocated data, 0 if none + */ +int dev_get_attach_size(const struct udevice *dev, enum dm_tag_t tag); + /** * dev_get_parent() - Get the parent of a device * diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 2c4d72d77f56b4e13d37acc3eba48819a93ed49d..bb60433124b64686185681d913ced06c6f76f0bb 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1181,6 +1181,33 @@ int ofnode_write_string(ofnode node, const char *propname, const char *value); */ int ofnode_set_enabled(ofnode node, bool value); +/** + * ofnode_get_phy_node() - Get PHY node for a MAC (if not fixed-link) + * + * This function parses PHY handle from the Ethernet controller's ofnode + * (trying all possible PHY handle property names), and returns the PHY ofnode. + * + * Before this is used, ofnode_phy_is_fixed_link() should be checked first, and + * if the result to that is true, this function should not be called. + * + * @eth_node: ofnode belonging to the Ethernet controller + * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode + */ +ofnode ofnode_get_phy_node(ofnode eth_node); + +/** + * ofnode_read_phy_mode() - Read PHY connection type from a MAC node + * + * This function parses the "phy-mode" / "phy-connection-type" property and + * returns the corresponding PHY interface type. + * + * @mac_node: ofnode containing the property + * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on + * error + */ +phy_interface_t ofnode_read_phy_mode(ofnode mac_node); + +#if CONFIG_IS_ENABLED(DM) /** * ofnode_conf_read_bool() - Read a boolean value from the U-Boot config * @@ -1218,30 +1245,21 @@ int ofnode_conf_read_int(const char *prop_name, int default_val); */ const char *ofnode_conf_read_str(const char *prop_name); -/** - * ofnode_get_phy_node() - Get PHY node for a MAC (if not fixed-link) - * - * This function parses PHY handle from the Ethernet controller's ofnode - * (trying all possible PHY handle property names), and returns the PHY ofnode. - * - * Before this is used, ofnode_phy_is_fixed_link() should be checked first, and - * if the result to that is true, this function should not be called. - * - * @eth_node: ofnode belonging to the Ethernet controller - * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode - */ -ofnode ofnode_get_phy_node(ofnode eth_node); +#else /* CONFIG_DM */ +static inline bool ofnode_conf_read_bool(const char *prop_name) +{ + return false; +} -/** - * ofnode_read_phy_mode() - Read PHY connection type from a MAC node - * - * This function parses the "phy-mode" / "phy-connection-type" property and - * returns the corresponding PHY interface type. - * - * @mac_node: ofnode containing the property - * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on - * error - */ -phy_interface_t ofnode_read_phy_mode(ofnode mac_node); +static inline int ofnode_conf_read_int(const char *prop_name, int default_val) +{ + return default_val; +} + +static inline const char *ofnode_conf_read_str(const char *prop_name) +{ + return NULL; +} +#endif /* CONFIG_DM */ #endif diff --git a/include/dm/platform_data/pxa_mmc_gen.h b/include/dm/platform_data/pxa_mmc_gen.h deleted file mode 100644 index d15c1551f4687571baf22af9786524f61ff8e1e9..0000000000000000000000000000000000000000 --- a/include/dm/platform_data/pxa_mmc_gen.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Marcel Ziswiler - */ - -#ifndef __PXA_MMC_GEN_H -#define __PXA_MMC_GEN_H - -#include - -/* - * struct pxa_mmc_plat - information about a PXA MMC controller - * - * @base: MMC controller base register address - */ -struct pxa_mmc_plat { - struct mmc_config cfg; - struct mmc mmc; - struct pxa_mmc_regs *base; -}; - -#endif /* __PXA_MMC_GEN_H */ diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h deleted file mode 100644 index 0d7dc4c462db8af5388081efafa24e0a2cc89070..0000000000000000000000000000000000000000 --- a/include/dm/platform_data/serial_pxa.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Marcel Ziswiler - */ - -#ifndef __SERIAL_PXA_H -#define __SERIAL_PXA_H - -/* - * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can - * easily handle enabling of clock. - */ -#ifdef CONFIG_CPU_MONAHANS -#define UART_CLK_BASE CKENA_21_BTUART -#define UART_CLK_REG CKENA -#define BTUART_INDEX 0 -#define FFUART_INDEX 1 -#define STUART_INDEX 2 -#elif CONFIG_CPU_PXA25X -#define UART_CLK_BASE BIT(4) /* HWUART */ -#define UART_CLK_REG CKEN -#define HWUART_INDEX 0 -#define STUART_INDEX 1 -#define FFUART_INDEX 2 -#define BTUART_INDEX 3 -#else /* PXA27x */ -#define UART_CLK_BASE CKEN5_STUART -#define UART_CLK_REG CKEN -#define STUART_INDEX 0 -#define FFUART_INDEX 1 -#define BTUART_INDEX 2 -#endif - -/* - * Only PXA250 has HWUART, to avoid poluting the code with more macros, - * artificially introduce this. - */ -#ifndef CONFIG_CPU_PXA25X -#define HWUART_INDEX 0xff -#endif - -/* - * struct pxa_serial_plat - information about a PXA port - * - * @base: Uart port base register address - * @port: Uart port index, for cpu with pinmux for uart / gpio - * baudrtatre: Uart port baudrate - */ -struct pxa_serial_plat { - struct pxa_uart_regs *base; - int port; - int baudrate; -}; - -#endif /* __SERIAL_PXA_H */ diff --git a/include/dm/root.h b/include/dm/root.h index e888fb993c01baf898c8ab7e57b73a8a8c09722a..b2f30a842f515d70982ec8af7599a86d12002176 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -9,11 +9,49 @@ #ifndef _DM_ROOT_H_ #define _DM_ROOT_H_ +#include + struct udevice; /* Head of the uclass list if CONFIG_OF_PLATDATA_INST is enabled */ extern struct list_head uclass_head; +/** + * struct dm_stats - Information about driver model memory usage + * + * @total_size: All data + * @dev_count: Number of devices + * @dev_size: Size of all devices (just the struct udevice) + * @dev_name_size: Bytes used by device names + * @uc_count: Number of uclasses + * @uc_size: Size of all uclasses (just the struct uclass) + * @tag_count: Number of tags + * @tag_size: Bytes used by all tags + * @uc_attach_count: Number of uclasses with attached data (priv) + * @uc_attach_size: Total size of that attached data + * @attach_count_total: Total number of attached data items for all udevices and + * uclasses + * @attach_size_total: Total number of bytes of attached data + * @attach_count: Number of devices with attached, for each type + * @attach_size: Total number of bytes of attached data, for each type + */ +struct dm_stats { + int total_size; + int dev_count; + int dev_size; + int dev_name_size; + int uc_count; + int uc_size; + int tag_count; + int tag_size; + int uc_attach_count; + int uc_attach_size; + int attach_count_total; + int attach_size_total; + int attach_count[DM_TAG_ATTACH_COUNT]; + int attach_size[DM_TAG_ATTACH_COUNT]; +}; + /** * dm_root() - Return pointer to the top of the driver tree * @@ -141,4 +179,11 @@ static inline int dm_remove_devices_flags(uint flags) { return 0; } */ void dm_get_stats(int *device_countp, int *uclass_countp); +/** + * dm_get_mem() - Get stats on memory usage in driver model + * + * @stats: Place to put the information + */ +void dm_get_mem(struct dm_stats *stats); + #endif diff --git a/include/dm/tag.h b/include/dm/tag.h index 54fc31eb1539d00ed82d424876130a2ba267447b..745088ffcff464ea73931d140292bb1fa423fca0 100644 --- a/include/dm/tag.h +++ b/include/dm/tag.h @@ -10,11 +10,23 @@ #include #include +struct dm_stats; struct udevice; enum dm_tag_t { + /* Types of core tags that can be attached to devices */ + DM_TAG_PLAT, + DM_TAG_PARENT_PLAT, + DM_TAG_UC_PLAT, + + DM_TAG_PRIV, + DM_TAG_PARENT_PRIV, + DM_TAG_UC_PRIV, + DM_TAG_DRIVER_DATA, + DM_TAG_ATTACH_COUNT, + /* EFI_LOADER */ - DM_TAG_EFI = 0, + DM_TAG_EFI = DM_TAG_ATTACH_COUNT, DM_TAG_COUNT, }; @@ -107,4 +119,22 @@ int dev_tag_del(struct udevice *dev, enum dm_tag_t tag); */ int dev_tag_del_all(struct udevice *dev); +/** + * dev_tag_collect_stats() - Collect information on driver model performance + * + * This collects information on how driver model is performing. For now it only + * includes memory usage + * + * @stats: Place to put the collected information + */ +void dev_tag_collect_stats(struct dm_stats *stats); + +/** + * tag_get_name() - Get the name of a tag + * + * @tag: Tag to look up, which must be valid + * Returns: Name of tag + */ +const char *tag_get_name(enum dm_tag_t tag); + #endif /* _DM_TAG_H */ diff --git a/include/dm/test.h b/include/dm/test.h index 4919064cc02e9ebe8ca40db5bdbb52558699c9cb..b5937509212b54567c1a8428c3d80a9ad3ee73ae 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -92,6 +92,13 @@ struct dm_test_uclass_priv { int total_add; }; +/** + * struct dm_test_uclass_plat - private plat data for test uclass + */ +struct dm_test_uclass_plat { + char dummy[32]; +}; + /** * struct dm_test_parent_data - parent's information on each child * diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 3ba69ad9a084ab5d362d2334fdd9dd0fc00a8472..a432e438716736aa595997ad268ca4cd34a2acfe 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -56,6 +56,7 @@ enum uclass_id { UCLASS_ETH, /* Ethernet device */ UCLASS_ETH_PHY, /* Ethernet PHY device */ UCLASS_FIRMWARE, /* Firmware */ + UCLASS_FUZZING_ENGINE, /* Fuzzing engine */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_HASH, /* Hash device */ diff --git a/include/dm/util.h b/include/dm/util.h index 4428f045b72d161875dd89bd4f3b270d45a89704..e10c6060ce000b5c1c1269b415a2fd69a0e635e7 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -6,6 +6,8 @@ #ifndef __DM_UTIL_H #define __DM_UTIL_H +struct dm_stats; + #if CONFIG_IS_ENABLED(DM_WARN) #define dm_warn(fmt...) log(LOGC_DM, LOGL_WARNING, ##fmt) #else @@ -25,7 +27,7 @@ struct list_head; int list_count_items(struct list_head *head); /* Dump out a tree of all devices */ -void dm_dump_all(void); +void dm_dump_tree(void); /* Dump out a list of uclasses and their devices */ void dm_dump_uclass(void); @@ -48,6 +50,13 @@ void dm_dump_driver_compat(void); /* Dump out a list of drivers with static platform data */ void dm_dump_static_driver_info(void); +/** + * dm_dump_mem() - Dump stats on memory usage in driver model + * + * @mem: Stats to dump + */ +void dm_dump_mem(struct dm_stats *stats); + #if CONFIG_IS_ENABLED(OF_PLATDATA_INST) && CONFIG_IS_ENABLED(READ_ONLY) void *dm_priv_to_rw(void *priv); #else diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 63e038e36ca3c88f15b0557501ac0647339829f6..a5204ab91d3ec63d01eeeef33961533cd7048ccf 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -41,4 +41,7 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif diff --git a/include/dt-bindings/sound/microchip,pdmc.h b/include/dt-bindings/sound/microchip,pdmc.h new file mode 100644 index 0000000000000000000000000000000000000000..96cde94ce74f1e02e6971c7f5eaf7e7982df10ec --- /dev/null +++ b/include/dt-bindings/sound/microchip,pdmc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__ +#define __DT_BINDINGS_MICROCHIP_PDMC_H__ + +/* PDM microphone's pin placement */ +#define MCHP_PDMC_DS0 0 +#define MCHP_PDMC_DS1 1 + +/* PDM microphone clock edge sampling */ +#define MCHP_PDMC_CLK_POSITIVE 0 +#define MCHP_PDMC_CLK_NEGATIVE 1 + +#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 11930fbea8389cbe20a56eb4cf39ed65f83cfb72..5b41985244e2d26ea1bbb18f75d79f2f2136dafa 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -591,6 +591,8 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void efi_save_gd(void); /* Call this to relocate the runtime section to an address space */ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); +/* Call this to get image parameters */ +void efi_get_image_parameters(void **img_addr, size_t *img_size); /* Add a new object to the object list. */ void efi_add_handle(efi_handle_t obj); /* Create handle */ diff --git a/include/elf.h b/include/elf.h index b04e746d6176bd37abc30fe775d4dcf97742e886..aeda159f0c01ae706b16b1c7428f8ab17a0a9937 100644 --- a/include/elf.h +++ b/include/elf.h @@ -188,14 +188,14 @@ typedef struct { #define EM_NDR1 57 /* Denso NDR1 microprocessor */ #define EM_STARCORE 58 /* Motorola Start*Core processor */ #define EM_ME16 59 /* Toyota ME16 processor */ -#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ #define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ #define EM_X86_64 62 /* AMD x86-64 */ #define EM_PDSP 63 /* Sony DSP Processor */ /* RESERVED 64,65 for future use */ #define EM_FX66 66 /* Siemens FX66 microcontroller */ #define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_ST7 68 /* STMicroelectronics ST7 8 bit mc */ #define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ #define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ #define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ diff --git a/include/env_default.h b/include/env_default.h index 7004a6fef29ba3db99909efe719b3aa567351818..4e461c815a79331cad0b1092474061b578142a4c 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -59,8 +59,8 @@ const char default_environment[] = { #ifdef CONFIG_SERVERIP "serverip=" __stringify(CONFIG_SERVERIP) "\0" #endif -#ifdef CONFIG_SYS_AUTOLOAD - "autoload=" CONFIG_SYS_AUTOLOAD "\0" +#ifdef CONFIG_SYS_DISABLE_AUTOLOAD + "autoload=0\0" #endif #ifdef CONFIG_PREBOOT "preboot=" CONFIG_PREBOOT "\0" @@ -108,10 +108,13 @@ const char default_environment[] = { #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" #endif +#ifdef CONFIG_MTDIDS_DEFAULT + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" +#endif +#ifdef CONFIG_MTDPARTS_DEFAULT + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#endif #ifdef CONFIG_EXTRA_ENV_TEXT -# ifdef CONFIG_EXTRA_ENV_SETTINGS -# error "Your board uses a text-file environment, so must not define CONFIG_EXTRA_ENV_SETTINGS" -# endif /* This is created in the Makefile */ CONFIG_EXTRA_ENV_TEXT #endif diff --git a/include/environment/ti/nand.h b/include/environment/ti/nand.h index 11dcefcc41caddd65596b806dcb7e8fb265fcda5..7d00afa2b10f565f59a7e065123a272b929e8c6a 100644 --- a/include/environment/ti/nand.h +++ b/include/environment/ti/nand.h @@ -14,7 +14,7 @@ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ diff --git a/include/event.h b/include/event.h index 62e72a7bd3163cb52841cbe8d7dcd849bc349938..c00c4fb68dcdf83f08ab6754a8d73ccca3504ffd 100644 --- a/include/event.h +++ b/include/event.h @@ -144,7 +144,16 @@ int event_register(const char *id, enum event_t type, event_handler_t func, /** event_show_spy_list( - Show a list of event spies */ void event_show_spy_list(void); -#if CONFIG_IS_ENABLED(EVENT) +/** + * event_manual_reloc() - Relocate event handler pointers + * + * Relocate event handler pointers for all static event spies. It is called + * during the generic board init sequence, after relocation. + * + * Return: 0 if OK + */ +int event_manual_reloc(void); + /** * event_notify() - notify spies about an event * @@ -159,6 +168,7 @@ void event_show_spy_list(void); */ int event_notify(enum event_t type, void *data, int size); +#if CONFIG_IS_ENABLED(EVENT) /** * event_notify_null() - notify spies about an event * @@ -169,11 +179,6 @@ int event_notify(enum event_t type, void *data, int size); */ int event_notify_null(enum event_t type); #else -static inline int event_notify(enum event_t type, void *data, int size) -{ - return 0; -} - static inline int event_notify_null(enum event_t type) { return 0; diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index fb838db0b53f1fbf87d0016da5bcb0bf2b2d7bfd..3092a0ea62a04a2c56bf55a54ad52886c86f274b 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -23,8 +23,6 @@ #define sec_mon_in16(a) in_be16(a) #define sec_mon_clrbits32 clrbits_be32 #define sec_mon_setbits32 setbits_be32 -#else -#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined #endif struct ccsr_sec_mon_regs { diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 613814d9057cd5c5690f0f3b1fca9d9e733fc720..e7674c1bff2a2d40786ea16556ebbb8682db8e48 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -24,8 +24,6 @@ #define sfp_in32(a) in_be32(a) #define sfp_out32(a, v) out_be32(a, v) #define sfp_in16(a) in_be16(a) -#else -#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined #endif /* Number of SRKH registers */ diff --git a/include/fuzzing_engine.h b/include/fuzzing_engine.h new file mode 100644 index 0000000000000000000000000000000000000000..357346e93dfef1e51dbfc1289768d2964d7b5f97 --- /dev/null +++ b/include/fuzzing_engine.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#ifndef __FUZZING_ENGINE_H +#define __FUZZING_ENGINE_H + +struct udevice; + +/** + * dm_fuzzing_engine_get_input() - get an input from the fuzzing engine device + * + * The function will return a pointer to the input data and the size of the + * data pointed to. The pointer will remain valid until the next invocation of + * this function. + * + * @dev: fuzzing engine device + * @data: output pointer to input data + * @size output size of input data + * Return: 0 if OK, -ve on error + */ +int dm_fuzzing_engine_get_input(struct udevice *dev, + const uint8_t **data, + size_t *size); + +/** + * struct dm_fuzzing_engine_ops - operations for the fuzzing engine uclass + * + * This contains the functions implemented by a fuzzing engine device. + */ +struct dm_fuzzing_engine_ops { + /** + * @get_input() - get an input + * + * The function will return a pointer to the input data and the size of + * the data pointed to. The pointer will remain valid until the next + * invocation of this function. + * + * @get_input.dev: fuzzing engine device + * @get_input.data: output pointer to input data + * @get_input.size output size of input data + * @get_input.Return: 0 if OK, -ve on error + */ + int (*get_input)(struct udevice *dev, + const uint8_t **data, + size_t *size); +}; + +#endif /* __FUZZING_ENGINE_H */ diff --git a/include/i2c.h b/include/i2c.h index 22add0b5282ff658b0a45acb463f5ebae2265d9b..e0ee94e550467cf716e9e56424fd470898da548f 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -647,9 +647,6 @@ void i2c_early_init_f(void); #if !defined(CONFIG_SYS_RTC_BUS_NUM) #define CONFIG_SYS_RTC_BUS_NUM 0 #endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif struct i2c_adapter { void (*init)(struct i2c_adapter *adap, int speed, diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index 3ad565684fe40f3f345872005221bd1016352764..32dcb03497309681f44f0c1e8aa740a2d15a35db 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -6,6 +6,8 @@ #ifndef __I2C_EEPROM #define __I2C_EEPROM +struct udevice; + struct i2c_eeprom_ops { int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size); int (*write)(struct udevice *dev, int offset, const uint8_t *buf, @@ -20,6 +22,7 @@ struct i2c_eeprom { unsigned long size; }; +#if CONFIG_IS_ENABLED(I2C_EEPROM) /* * i2c_eeprom_read() - read bytes from an I2C EEPROM chip * @@ -42,7 +45,8 @@ int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size); * * Return: 0 on success, -ve on failure */ -int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size); +int i2c_eeprom_write(struct udevice *dev, int offset, const uint8_t *buf, + int size); /* * i2c_eeprom_size() - get size of I2C EEPROM chip @@ -53,4 +57,25 @@ int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size); */ int i2c_eeprom_size(struct udevice *dev); +#else /* !I2C_EEPROM */ + +static inline int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, + int size) +{ + return -ENOSYS; +} + +static inline int i2c_eeprom_write(struct udevice *dev, int offset, + const uint8_t *buf, int size) +{ + return -ENOSYS; +} + +static inline int i2c_eeprom_size(struct udevice *dev) +{ + return -ENOSYS; +} + +#endif /* I2C_EEPROM */ + #endif diff --git a/include/ide.h b/include/ide.h index 2994b7a76226baed2d819c45a6e6d554afc66f60..426cef4e39e094c6cb618326f8050e8a125ff269 100644 --- a/include/ide.h +++ b/include/ide.h @@ -33,10 +33,6 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer); #endif -#ifdef CONFIG_IDE_PREINIT -int ide_preinit(void); -#endif - #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev); #endif diff --git a/include/k3-clk.h b/include/k3-clk.h index 31292b59f20cfd5b737e2527d5c53390e8f4c596..371f077c4476dfc287fdce139a2647994923264d 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -174,6 +174,7 @@ struct ti_k3_clk_platdata { extern const struct ti_k3_clk_platdata j721e_clk_platdata; extern const struct ti_k3_clk_platdata j7200_clk_platdata; extern const struct ti_k3_clk_platdata j721s2_clk_platdata; +extern const struct ti_k3_clk_platdata am62x_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index b46b8c3aabc7fc01101ede479f45d829a4338928..87e873b9cedb9343f83b35040762ba8d0520ebb7 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -78,6 +78,7 @@ struct ti_k3_pd_platdata { extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata; extern const struct ti_k3_pd_platdata j721s2_pd_platdata; +extern const struct ti_k3_pd_platdata am62x_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); diff --git a/include/lcd.h b/include/lcd.h index 51a79317bbadabe48d2f57af98a47a6432e85425..4f180692781183d85a1cc40db8d671af98dc58ea 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -40,10 +40,7 @@ ulong lcd_setmem(ulong addr); */ void lcd_set_flush_dcache(int flush); -#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ - defined CONFIG_CPU_MONAHANS -#include -#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) +#if defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) #include #elif defined(CONFIG_EXYNOS_FB) #include diff --git a/include/linker_lists.h b/include/linker_lists.h index 0575164ce4c8723c73cd3e699e1febbc0e1dc158..d3da9d44e8530b8bb17743e57a537da027af3ffc 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -70,7 +70,7 @@ #define ll_entry_declare(_type, _name, _list) \ _type _u_boot_list_2_##_list##_2_##_name __aligned(4) \ __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_2_"#_name) + __section("__u_boot_list_2_"#_list"_2_"#_name) /** * ll_entry_declare_list() - Declare a list of link-generated array entries @@ -93,7 +93,7 @@ #define ll_entry_declare_list(_type, _name, _list) \ _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \ __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_2_"#_name) + __section("__u_boot_list_2_"#_list"_2_"#_name) /* * We need a 0-byte-size type for iterator symbols, and the compiler @@ -110,7 +110,7 @@ * @_list: Name of the list in which this entry is placed * * This function returns ``(_type *)`` pointer to the very first entry of a - * linker-generated array placed into subsection of .u_boot_list section + * linker-generated array placed into subsection of __u_boot_list section * specified by _list argument. * * Since this macro defines an array start symbol, its leftmost index @@ -126,7 +126,7 @@ ({ \ static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \ __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_1"); \ + __section("__u_boot_list_2_"#_list"_1"); \ (_type *)&start; \ }) @@ -137,7 +137,7 @@ * (with underscores instead of dots) * * This function returns ``(_type *)`` pointer after the very last entry of - * a linker-generated array placed into subsection of .u_boot_list + * a linker-generated array placed into subsection of __u_boot_list * section specified by _list argument. * * Since this macro defines an array end symbol, its leftmost index @@ -152,7 +152,7 @@ #define ll_entry_end(_type, _list) \ ({ \ static char end[0] __aligned(4) __attribute__((unused)) \ - __section(".u_boot_list_2_"#_list"_3"); \ + __section("__u_boot_list_2_"#_list"_3"); \ (_type *)&end; \ }) /** @@ -161,7 +161,7 @@ * @_list: Name of the list of which the number of elements is computed * * This function returns the number of elements of a linker-generated array - * placed into subsection of .u_boot_list section specified by _list + * placed into subsection of __u_boot_list section specified by _list * argument. The result is of an unsigned int type. * * Example: @@ -246,7 +246,7 @@ #define ll_start(_type) \ ({ \ static char start[0] __aligned(4) __attribute__((unused)) \ - __section(".u_boot_list_1"); \ + __section("__u_boot_list_1"); \ (_type *)&start; \ }) @@ -269,7 +269,7 @@ #define ll_end(_type) \ ({ \ static char end[0] __aligned(4) __attribute__((unused)) \ - __section(".u_boot_list_3"); \ + __section("__u_boot_list_3"); \ (_type *)&end; \ }) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 7f2be2339475ec56c71bb2ad52f5535a0f19ad6a..e1d09884a1c534b515581d501347742ebca39e22 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -51,6 +51,10 @@ #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ +#define ARM_SMCCC_ARCH_FEATURES 0x80000001 + +#define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) + #ifndef __ASSEMBLY__ #include @@ -79,6 +83,22 @@ struct arm_smccc_quirk { } state; }; +/** + * struct arm_smccc_feature - Driver registration data for discoverable feature + * @driver_name: name of the driver relate to the SMCCC feature + * @is_supported: callback to test if SMCCC feature is supported + */ +struct arm_smccc_feature { + const char *driver_name; + bool (*is_supported)(void (*invoke_fn)(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_res *res)); +}; + +#define ARM_SMCCC_FEATURE_DRIVER(__name) \ + ll_entry_declare(struct arm_smccc_feature, __name, arm_smccc_feature) + /** * __arm_smccc_smc() - make SMC calls * @a0-a7: arguments passed in registers 0 to 7 diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h index 6079f9e260de1fc7a2ab223772a052c8043a3a24..1d8a067f17ef4d1905d0cf591c2ea861a796bf0d 100644 --- a/include/linux/mtd/fsmc_nand.h +++ b/include/linux/mtd/fsmc_nand.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #ifndef __FSMC_NAND_H__ diff --git a/include/linux/psci.h b/include/linux/psci.h index c78c1079a826ee338e9d82a59246b3d1aac0e432..03e418634325dd56b4db54737a7e74f2bc93869f 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -11,6 +11,8 @@ #ifndef _UAPI_LINUX_PSCI_H #define _UAPI_LINUX_PSCI_H +#include + /* * PSCI v0.1 interface * @@ -115,6 +117,18 @@ #define PSCI_RET_DISABLED -8 #define PSCI_RET_INVALID_ADDRESS -9 +/** + * struct psci_plat_data - PSCI driver platform data + * @method: Selected invocation conduit + */ +struct psci_plat_data { + void (*invoke_fn)(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct arm_smccc_res *res); +}; + #ifdef CONFIG_ARM_PSCI_FW unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3); diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 1367149c4ba7b8d54e5e27a580b80839e00da6f8..40979f72fc683d308b5744a5125a22479f6e3eca 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -53,21 +53,4 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -#endif - -#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB3_ADDR} #endif /* _ASM_ARCH_XHCI_FSL_H_ */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 2c69a60de63ff060c75895d288d878b3a1b3d8e8..053b68a10a4a61b50f0d3f30b37b4929bb01d9e1 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,7 +26,7 @@ * Define default values for some CCSR macros to make header files cleaner* * * To completely disable CCSR relocation in a board header file, define - * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS * to a value that is the same as CONFIG_SYS_CCSRBAR. */ @@ -35,7 +35,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." #endif -#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH #undef CONFIG_SYS_CCSRBAR_PHYS_LOW #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 diff --git a/include/nvmem.h b/include/nvmem.h new file mode 100644 index 0000000000000000000000000000000000000000..822e698bdd484a21861e7c9cdc2a218b7ecb520d --- /dev/null +++ b/include/nvmem.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Sean Anderson + */ + +#ifndef NVMEM_H +#define NVMEM_H + +/** + * DOC: Design + * + * The NVMEM subsystem is a "meta-uclass" in that it abstracts over several + * different uclasses all with read/write APIs. One approach to implementing + * this could be to add a new sub-device for each nvmem-style device of + * UCLASS_NVMEM. This subsystem has taken the approach of using the existing + * access methods (i2c_eeprom_write, misc_write, etc.) directly. This has the + * advantage of not requiring an extra device/driver, saving on binary size and + * runtime memory usage. On the other hand, it is not idiomatic. Similar + * efforts should generally use a new uclass. + */ + +/** + * struct nvmem_cell - One datum within non-volatile memory + * @nvmem: The backing storage device + * @offset: The offset of the cell from the start of @nvmem + * @size: The size of the cell, in bytes + */ +struct nvmem_cell { + struct udevice *nvmem; + unsigned int offset; + size_t size; +}; + +struct udevice; + +#if CONFIG_IS_ENABLED(NVMEM) + +/** + * nvmem_cell_read() - Read the value of an nvmem cell + * @cell: The nvmem cell to read + * @buf: The buffer to read into + * @size: The size of @buf + * + * Return: + * * 0 on success + * * -EINVAL if @buf is not the same size as @cell. + * * -ENOSYS if CONFIG_NVMEM is disabled + * * A negative error if there was a problem reading the underlying storage + */ +int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size); + +/** + * nvmem_cell_write() - Write a value to an nvmem cell + * @cell: The nvmem cell to write + * @buf: The buffer to write from + * @size: The size of @buf + * + * Return: + * * 0 on success + * * -EINVAL if @buf is not the same size as @cell + * * -ENOSYS if @cell is read-only, or if CONFIG_NVMEM is disabled + * * A negative error if there was a problem writing the underlying storage + */ +int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, size_t size); + +/** + * nvmem_cell_get_by_index() - Get an nvmem cell from a given device and index + * @dev: The device that uses the nvmem cell + * @index: The index of the cell in nvmem-cells + * @cell: The cell to initialize + * + * Look up the nvmem cell referenced by the phandle at @index in nvmem-cells in + * @dev. + * + * Return: + * * 0 on success + * * -EINVAL if the regs property is missing, empty, or undersized + * * -ENODEV if the nvmem device is missing or unimplemented + * * -ENOSYS if CONFIG_NVMEM is disabled + * * A negative error if there was a problem reading nvmem-cells or getting the + * device + */ +int nvmem_cell_get_by_index(struct udevice *dev, int index, + struct nvmem_cell *cell); + +/** + * nvmem_cell_get_by_name() - Get an nvmem cell from a given device and name + * @dev: The device that uses the nvmem cell + * @name: The name of the nvmem cell + * @cell: The cell to initialize + * + * Look up the nvmem cell referenced by @name in the nvmem-cell-names property + * of @dev. + * + * Return: + * * 0 on success + * * -EINVAL if the regs property is missing, empty, or undersized + * * -ENODEV if the nvmem device is missing or unimplemented + * * -ENODATA if @name is not in nvmem-cell-names + * * -ENOSYS if CONFIG_NVMEM is disabled + * * A negative error if there was a problem reading nvmem-cell-names, + * nvmem-cells, or getting the device + */ +int nvmem_cell_get_by_name(struct udevice *dev, const char *name, + struct nvmem_cell *cell); + +#else /* CONFIG_NVMEM */ + +static inline int nvmem_cell_read(struct nvmem_cell *cell, void *buf, int size) +{ + return -ENOSYS; +} + +static inline int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, + int size) +{ + return -ENOSYS; +} + +static inline int nvmem_cell_get_by_index(struct udevice *dev, int index, + struct nvmem_cell *cell) +{ + return -ENOSYS; +} + +static inline int nvmem_cell_get_by_name(struct udevice *dev, const char *name, + struct nvmem_cell *cell) +{ + return -ENOSYS; +} + +#endif /* CONFIG_NVMEM */ + +#endif /* NVMEM_H */ diff --git a/include/os.h b/include/os.h index 10e198cf503e978be0bab4adc44502d3bfdd4c30..148178787bc238bceae9d9c710f00d48945b924d 100644 --- a/include/os.h +++ b/include/os.h @@ -16,6 +16,13 @@ struct rtc_time; struct sandbox_state; +/** + * os_printf() - print directly to OS console + * + * @format: format string + */ +int os_printf(const char *format, ...); + /** * Access to the OS read() system call * diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h index b8c895bbabb166efaaff0bc425a92507cdce91cc..500c8ea7174dc29a0ab0972c1e7533853c61437f 100644 --- a/include/power/fg_battery_cell_params.h +++ b/include/power/fg_battery_cell_params.h @@ -7,7 +7,7 @@ #ifndef __FG_BATTERY_CELL_PARAMS_H_ #define __FG_BATTERY_CELL_PARAMS_H_ -#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS) +#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS) /* Cell characteristics - Exynos4 TRATS development board */ /* Shall be written to addr 0x80h */ diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h index d3567df326cfb9a212ac01beb0efd391a97cdef4..201b1df762e39618b8ee2ff34f5395a0364f0951 100644 --- a/include/power/stpmic1.h +++ b/include/power/stpmic1.h @@ -23,12 +23,9 @@ /* BUCKS_MRST_CR */ #define STPMIC1_MRST_BUCK(buck) BIT(buck) -#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \ - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)) /* LDOS_MRST_CR */ #define STPMIC1_MRST_LDO(ldo) BIT(ldo) -#define STPMIC1_MRST_LDO_DEBUG 0 /* BUCKx_MAIN_CR (x=1...4) */ #define STPMIC1_BUCK_ENA BIT(0) diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h deleted file mode 100644 index 11a22abca6dcd3591a05229ccc54512872e39f9e..0000000000000000000000000000000000000000 --- a/include/pxa_lcd.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pxa_lcd.h - PXA LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _PXA_LCD_H_ -#define _PXA_LCD_H_ - -/* - * PXA LCD DMA descriptor - */ -struct pxafb_dma_descriptor { - u_long fdadr; /* Frame descriptor address register */ - u_long fsadr; /* Frame source address register */ - u_long fidr; /* Frame ID register */ - u_long ldcmd; /* Command register */ -}; - -/* - * PXA LCD info - */ -struct pxafb_info { - /* Misc registers */ - u_long reg_lccr3; - u_long reg_lccr2; - u_long reg_lccr1; - u_long reg_lccr0; - u_long fdadr0; - u_long fdadr1; - - /* DMA descriptors */ - struct pxafb_dma_descriptor *dmadesc_fblow; - struct pxafb_dma_descriptor *dmadesc_fbhigh; - struct pxafb_dma_descriptor *dmadesc_palette; - - u_long screen; /* physical address of frame buffer */ - u_long palette; /* physical address of palette memory */ - u_int palette_size; -}; - -/* - * LCD controller stucture for PXA CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_hpw; /* Horz sync pulse width */ - u_char vl_blw; /* Wait before of line */ - u_char vl_elw; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_bfw; /* Wait before of frame */ - u_char vl_efw; /* Wait end of frame */ - - /* PXA LCD controller params */ - struct pxafb_info pxa; -} vidinfo_t; - -#endif diff --git a/include/regmap.h b/include/regmap.h index 8216de015dd88125d090fef91ea67c7f93b19fa0..e81a3602aea5e34e4debf0398374850e830004f5 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -460,7 +460,7 @@ struct reg_field { struct regmap_field; /** - * REG_FIELD() - A convenient way to initialize a 'struct reg_feild'. + * REG_FIELD() - A convenient way to initialize a 'struct reg_field'. * * @_reg: Offset of the register within the regmap bank * @_lsb: lsb of the register field. @@ -519,9 +519,9 @@ void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field); int regmap_field_write(struct regmap_field *field, unsigned int val); /** - * regmap_read() - Read a 32-bit value from a regmap + * regmap_field_read() - Read a 32-bit value from a regmap * - * @field: Regmap field to write to + * @field: Regmap field to read from * @valp: Pointer to the buffer to receive the data read from the regmap * field * diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index a501d1b48255011316a4f3698b9156f61322335b..b1c93532c0eac440fd187e0aac6618663a680aba 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -7,18 +7,29 @@ struct udevice; struct scmi_msg; +struct scmi_channel; /** * struct scmi_transport_ops - The functions that a SCMI transport layer must implement. */ struct scmi_agent_ops { + /* + * of_get_channel - Get SCMI channel from SCMI agent device tree node + * + * @dev: SCMI protocol device using the transport + * @channel: Output reference to SCMI channel upon success + * Return 0 upon success and a negative errno on failure + */ + int (*of_get_channel)(struct udevice *dev, struct scmi_channel **channel); + /* * process_msg - Request transport to get the SCMI message processed * - * @agent: Agent using the transport + * @dev: SCMI protocol device using the transport * @msg: SCMI message to be transmitted */ - int (*process_msg)(struct udevice *dev, struct scmi_msg *msg); + int (*process_msg)(struct udevice *dev, struct scmi_channel *channel, + struct scmi_msg *msg); }; #endif /* _SCMI_TRANSPORT_UCLASS_H */ diff --git a/include/scmi_agent.h b/include/scmi_agent.h index 18bcd48a9d4300be31561dc5a83ca884c92e24bc..ee6286366df7883f6bb8c41281dbce772e00ab62 100644 --- a/include/scmi_agent.h +++ b/include/scmi_agent.h @@ -13,6 +13,7 @@ #include struct udevice; +struct scmi_channel; /* * struct scmi_msg - Context of a SCMI message sent and the response received @@ -44,6 +45,15 @@ struct scmi_msg { .out_msg_sz = sizeof(_out_array), \ } +/** + * devm_scmi_of_get_channel() - Get SCMI channel handle from SCMI agent DT node + * + * @dev: Device requesting a channel + * @channel: Output reference to the SCMI channel upon success + * @return 0 on success and a negative errno on failure + */ +int devm_scmi_of_get_channel(struct udevice *dev, struct scmi_channel **channel); + /** * devm_scmi_process_msg() - Send and process an SCMI message * @@ -52,10 +62,12 @@ struct scmi_msg { * On return, scmi_msg::out_msg_sz stores the response payload size. * * @dev: SCMI device + * @channel: Communication channel for the device * @msg: Message structure reference * Return: 0 on success and a negative errno on failure */ -int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg); +int devm_scmi_process_msg(struct udevice *dev, struct scmi_channel *channel, + struct scmi_msg *msg); /** * scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code diff --git a/include/spl.h b/include/spl.h index 83ac583e0b492ea8cad81c962889aa5024dc1169..aac6648f94694a994bbdccd525f17d814947d01d 100644 --- a/include/spl.h +++ b/include/spl.h @@ -288,6 +288,8 @@ binman_sym_extern(ulong, u_boot_any, image_pos); binman_sym_extern(ulong, u_boot_any, size); binman_sym_extern(ulong, u_boot_spl, image_pos); binman_sym_extern(ulong, u_boot_spl, size); +binman_sym_extern(ulong, u_boot_vpl, image_pos); +binman_sym_extern(ulong, u_boot_vpl, size); /** * spl_get_image_pos() - get the image position of the next phase @@ -377,6 +379,22 @@ int spl_load_imx_container(struct spl_image_info *spl_image, void preloader_console_init(void); u32 spl_boot_device(void); +/** + * spl_spi_boot_bus() - Lookup function for the SPI boot bus source. + * + * This function returns the SF bus to load from. + * If not overridden, it is weakly defined in common/spl/spl_spi.c. + */ +u32 spl_spi_boot_bus(void); + +/** + * spl_spi_boot_cs() - Lookup function for the SPI boot CS source. + * + * This function returns the SF CS to load from. + * If not overridden, it is weakly defined in common/spl/spl_spi.c. + */ +u32 spl_spi_boot_cs(void); + /** * spl_mmc_boot_mode() - Lookup function for the mode of an MMC boot source. * @boot_device: ID of the device which the MMC driver wants to read diff --git a/include/system-constants.h b/include/system-constants.h new file mode 100644 index 0000000000000000000000000000000000000000..83b41b384f39a134d79192743754cd2dc3f96d73 --- /dev/null +++ b/include/system-constants.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SYSTEM_CONSTANTS_H__ +#define __SYSTEM_CONSTANTS_H__ + +/* + * The most common case for our initial stack pointer address is to + * say that we have defined a static intiial ram address location and + * size and from that we subtract the generated global data size. + */ +#ifdef CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR +#define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR +#else +#ifdef CONFIG_MIPS +#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#else +#define SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#endif +#endif + +/* + * Typically, we have the SPL malloc pool at the end of the BSS area. + */ +#ifdef CONFIG_HAS_CUSTOM_SPL_MALLOC_START +#define SYS_SPL_MALLOC_START CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR +#else +#define SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#endif + +#endif diff --git a/include/test/fuzz.h b/include/test/fuzz.h new file mode 100644 index 0000000000000000000000000000000000000000..d4c57540eb3a616a1063b404e919944bc341c62e --- /dev/null +++ b/include/test/fuzz.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#ifndef __TEST_FUZZ_H +#define __TEST_FUZZ_H + +#include +#include + +/** + * struct fuzz_test - Information about a fuzz test + * + * @name: Name of fuzz test + * @func: Function to call to perform fuzz test on an input + * @flags: Flags indicate pre-conditions for fuzz test + */ +struct fuzz_test { + const char *name; + int (*func)(const uint8_t * data, size_t size); + int flags; +}; + +/** + * FUZZ_TEST() - register a fuzz test + * + * The fuzz test function must return 0 as other values are reserved for future + * use. + * + * @_name: the name of the fuzz test function + * @_flags: an integer field that can be evaluated by the fuzzer + * implementation + */ +#define FUZZ_TEST(_name, _flags) \ + ll_entry_declare(struct fuzz_test, _name, fuzz_tests) = { \ + .name = #_name, \ + .func = _name, \ + .flags = _flags, \ + } + +/** Get the start of the list of fuzz tests */ +#define FUZZ_TEST_START() \ + ll_entry_start(struct fuzz_test, fuzz_tests) + +/** Get the number of elements in the list of fuzz tests */ +#define FUZZ_TEST_COUNT() \ + ll_entry_count(struct fuzz_test, fuzz_tests) + +#endif /* __TEST_FUZZ_H */ diff --git a/include/test/suites.h b/include/test/suites.h index ee6858a802a55bec71ba74af2f185ebff6195681..ddb8827fdb15e93f99c3b3c182a25a7f0fcecf1d 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -39,6 +39,7 @@ int do_ut_compression(struct cmd_tbl *cmdtp, int flag, int argc, int do_ut_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_lib(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_log(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); int do_ut_mem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index 283f103293628c9c25ca6764a43253718a0ee695..09fee594d263fa94e1060cf113f9e603b521b99d 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -30,7 +30,7 @@ extern const uint8_t sha1_der_prefix[]; typedef struct { unsigned long total[2]; /*!< number of bytes processed */ - unsigned long state[5]; /*!< intermediate digest state */ + uint32_t state[5]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ } sha1_context; diff --git a/include/usb/designware_udc.h b/include/usb/designware_udc.h index f874e5c35cc2d1f21c064cbf6689700a6a4ede1f..f716f07dd0419ea0df5ed35094cfbe74cbd5b8ab 100644 --- a/include/usb/designware_udc.h +++ b/include/usb/designware_udc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ #ifndef __DW_UDC_H diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 2cdb3146e8630709cf1dad9a4f14cc54232f77c5..bc980934585cc403fd45d6fbad283e8c103f3611 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -146,21 +146,6 @@ #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 -#if defined(CONFIG_MPC83xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR -#else -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif -#elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif - /* * Increasing TX FIFO threshold value from 2 to 4 decreases * data burst rate with which data packets are posted from the TX diff --git a/include/usb/pxa27x_udc.h b/include/usb/pxa27x_udc.h deleted file mode 100644 index 07d14821c31d2a7cafe023ca869aab4caba897b8..0000000000000000000000000000000000000000 --- a/include/usb/pxa27x_udc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA27x register declarations and HCD data structures - * - * Copyright (C) 2007 Rodolfo Giometti - * Copyright (C) 2007 Eurotech S.p.A. - */ - - -#ifndef __PXA270X_UDC_H__ -#define __PXA270X_UDC_H__ - -#include - -/* Endpoint 0 states */ -#define EP0_IDLE 0 -#define EP0_IN_DATA 1 -#define EP0_OUT_DATA 2 -#define EP0_XFER_COMPLETE 3 - - -/* Endpoint parameters */ -#define MAX_ENDPOINTS 4 - -#define EP0_MAX_PACKET_SIZE 16 - -#define UDC_OUT_ENDPOINT 0x02 -#define UDC_IN_ENDPOINT 0x01 -#define UDC_INT_ENDPOINT 0x05 - -#endif diff --git a/include/virtio_ring.h b/include/virtio_ring.h index 6fc0593b14b7b36f02d588270247097b1d288fd6..c77c212cffd3d5e2d2cc9a3a689a528c10a0aed3 100644 --- a/include/virtio_ring.h +++ b/include/virtio_ring.h @@ -55,6 +55,16 @@ struct vring_desc { __virtio16 next; }; +/* Shadow of struct vring_desc in guest byte order. */ +struct vring_desc_shadow { + u64 addr; + u32 len; + u16 flags; + u16 next; + /* Metadata about the descriptor. */ + bool chain_head; +}; + struct vring_avail { __virtio16 flags; __virtio16 idx; @@ -89,6 +99,7 @@ struct vring { * @index: the zero-based ordinal number for this queue * @num_free: number of elements we expect to be able to fit * @vring: actual memory layout for this queue + * @vring_desc_shadow: guest-only copy of descriptors * @event: host publishes avail event idx * @free_head: head of free buffer list * @num_added: number we've added since last sync @@ -102,6 +113,7 @@ struct virtqueue { unsigned int index; unsigned int num_free; struct vring vring; + struct vring_desc_shadow *vring_desc_shadow; bool event; unsigned int free_head; unsigned int num_added; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 76ec2141ff6a80fc73965718a294ee349f5035dc..6c4fd9a6c5f261968eccefb25107e9b0b154ad3e 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -160,6 +160,12 @@ enum dll_reset_type { PM_DLL_RESET_PULSE = 2, }; +enum ospi_mux_select_type { + PM_OSPI_MUX_SEL_DMA, + PM_OSPI_MUX_SEL_LINEAR, + PM_OSPI_MUX_GET_MODE, +}; + enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, @@ -427,6 +433,9 @@ enum pm_gem_config_type { #define ZYNQMP_PM_VERSION_INVALID ~0 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PMIO_NODE_ID_BASE 0x1410801B + +#define PMIO_NODE_ID_BASE 0x1410801B /* * Return payload size diff --git a/lib/Kconfig b/lib/Kconfig index acc0ac081a4421a430b204c73c2260557a135c87..7dd777b56a7921175d69223d50a05704f53fb3e5 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -239,6 +239,7 @@ config GENERATE_ACPI_TABLE config SPL_TINY_MEMSET bool "Use a very small memset() in SPL" + depends on SPL help The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get @@ -248,6 +249,7 @@ config SPL_TINY_MEMSET config TPL_TINY_MEMSET bool "Use a very small memset() in TPL" + depends on TPL help The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get @@ -556,6 +558,7 @@ config MD5 config SPL_MD5 bool "Support MD5 algorithm in SPL" + depends on SPL help This option enables MD5 support in SPL. MD5 is an algorithm designed in 1991 that produces a 16-byte digest (or checksum) from its input @@ -642,6 +645,7 @@ config ZSTD config SPL_LZ4 bool "Enable LZ4 decompression support in SPL" + depends on SPL help This enables support for the LZ4 decompression algorithm in SPL. LZ4 is a lossless data compression algorithm that is focused on @@ -650,6 +654,7 @@ config SPL_LZ4 config SPL_LZMA bool "Enable LZMA decompression support for SPL build" + depends on SPL help This enables support for LZMA compression algorithm for SPL boot. @@ -661,6 +666,7 @@ config VPL_LZMA config SPL_LZO bool "Enable LZO decompression support in SPL" + depends on SPL help This enables support for LZO compression algorithm in the SPL. @@ -677,6 +683,7 @@ config SPL_ZLIB config SPL_ZSTD bool "Enable Zstandard decompression support in SPL" + depends on SPL select XXHASH help This enables Zstandard decompression library in the SPL. @@ -749,7 +756,7 @@ config SPL_OF_LIBFDT config SPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on SPL_OF_LIBFDT || FIT + depends on SPL_OF_LIBFDT || (FIT && SPL) default 0xff help Use this to change the assumptions made by libfdt in SPL about the @@ -771,7 +778,7 @@ config TPL_OF_LIBFDT config TPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on TPL_OF_LIBFDT || FIT + depends on TPL_OF_LIBFDT || (FIT && TPL) default 0xff help Use this to change the assumptions made by libfdt in TPL about the @@ -782,6 +789,7 @@ config TPL_OF_LIBFDT_ASSUME_MASK config VPL_OF_LIBFDT bool "Enable the FDT library for VPL" + depends on VPL default y if VPL_OF_CONTROL && !VPL_OF_PLATDATA help This enables the FDT library (libfdt). It provides functions for @@ -792,7 +800,7 @@ config VPL_OF_LIBFDT config VPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on VPL_OF_LIBFDT || FIT + depends on VPL_OF_LIBFDT || (FIT && VPL) default 0xff help Use this to change the assumptions made by libfdt in SPL about the @@ -958,11 +966,4 @@ config LMB_RESERVED_REGIONS Define the number of supported reserved regions in the library logical memory blocks. -config PHANDLE_CHECK_SEQ - bool "Enable phandle check while getting sequence number" - help - When there are multiple device tree nodes with same name, - enable this config option to distinguish them using - phandles in fdtdec_get_alias_seq() function. - endmenu diff --git a/lib/Makefile b/lib/Makefile index d9b1811f7506382abaafda81202705fa038bde5e..e3deb1528794f484bd3ec4d0d17ecbf634f1d881 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_EFI_LOADER) += efi_loader/ obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest/ obj-$(CONFIG_LZMA) += lzma/ obj-$(CONFIG_BZIP2) += bzip2/ -obj-$(CONFIG_TIZEN) += tizen/ obj-$(CONFIG_FIT) += libfdt/ obj-$(CONFIG_OF_LIVE) += of_live.o obj-$(CONFIG_CMD_DHRYSTONE) += dhry/ diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig index c3f563b2e17423f4e8bc660c358fd29fd0961756..6e0656ad1c568dbfd34b32091e4de42aa9cb8468 100644 --- a/lib/crypto/Kconfig +++ b/lib/crypto/Kconfig @@ -28,7 +28,7 @@ config ASYMMETRIC_PUBLIC_KEY_SUBTYPE config SPL_ASYMMETRIC_PUBLIC_KEY_SUBTYPE bool "Asymmetric public-key crypto algorithm subtype within SPL" - depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE + depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE && SPL help This option provides support for asymmetric public key type handling in the SPL. If signature generation and/or verification are to be used, @@ -48,7 +48,7 @@ config RSA_PUBLIC_KEY_PARSER config SPL_RSA_PUBLIC_KEY_PARSER bool "RSA public key parser within SPL" - depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE + depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE && SPL select SPL_ASN1_DECODER select ASN1_COMPILER select SPL_OID_REGISTRY diff --git a/lib/ecdsa/Kconfig b/lib/ecdsa/Kconfig index a95c4ff581f04f518d298b432103de2d03982768..5c3d67d8144b48860154cac84fe8aa38e0df2547 100644 --- a/lib/ecdsa/Kconfig +++ b/lib/ecdsa/Kconfig @@ -17,6 +17,7 @@ config ECDSA_VERIFY config SPL_ECDSA_VERIFY bool "Enable ECDSA verification support in SPL" + depends on SPL help Allow ECDSA signatures to be recognized and verified in SPL. diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 171661b8972728f0babebf8a6de25e62cc4019ab..2493d7432613d368793838fc9585990e09d15659 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -1158,6 +1158,8 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, { struct blk_desc *desc = NULL; struct disk_partition fs_partition; + size_t image_size; + void *image_addr; int part = 0; char *filename; char *s; @@ -1173,6 +1175,13 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, } else if (!strcmp(dev, "Uart")) { if (device) *device = efi_dp_from_uart(); + } else if (!strcmp(dev, "Mem")) { + efi_get_image_parameters(&image_addr, &image_size); + + if (device) + *device = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, + (uintptr_t)image_addr, + image_size); } else { part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition, 1); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index e20f6aad9c2f1fa6f75594b25ef00ba110b19c67..ffa78f97ca0ad93ea7f0a86c376a163f61a6560b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -516,11 +516,8 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int offset, * Adding an extra check to distinguish DT nodes with * same name */ - if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) { - if (fdt_get_phandle(blob, offset) != - fdt_get_phandle(blob, fdt_path_offset(blob, prop))) - continue; - } + if (offset != fdt_path_offset(blob, prop)) + continue; val = trailing_strtol(name); if (val != -1) { diff --git a/lib/hashtable.c b/lib/hashtable.c index ff5ff7263949f532d7792deb70677df7ab3f65a7..90c8465611e9b7de752ea9432bab90e4cb2175a9 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -35,13 +35,6 @@ # include #endif -#ifndef CONFIG_ENV_MIN_ENTRIES /* minimum number of entries */ -#define CONFIG_ENV_MIN_ENTRIES 64 -#endif -#ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */ -#define CONFIG_ENV_MAX_ENTRIES 512 -#endif - #define USED_FREE 0 #define USED_DELETED -1 diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index b773f17c261e2938728fd0967ee97f3b9b5ebdfb..9033384e60a3355504ba5c8a1ea3abaf37a9e601 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -18,6 +18,7 @@ if RSA config SPL_RSA bool "Use RSA Library within SPL" + depends on SPL config SPL_RSA_VERIFY bool diff --git a/lib/sha1.c b/lib/sha1.c index 8154e1e1350026c07271e08d6ef2864cc29e0fd6..e5e42bc9fe38d0a2b58335c67acdd54821e902d1 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -25,6 +25,8 @@ #include #include +#include + const uint8_t sha1_der_prefix[SHA1_DER_LEN] = { 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14 @@ -65,7 +67,7 @@ void sha1_starts (sha1_context * ctx) ctx->state[4] = 0xC3D2E1F0; } -static void sha1_process(sha1_context *ctx, const unsigned char data[64]) +static void __maybe_unused sha1_process_one(sha1_context *ctx, const unsigned char data[64]) { unsigned long temp, W[16], A, B, C, D, E; @@ -219,6 +221,18 @@ static void sha1_process(sha1_context *ctx, const unsigned char data[64]) ctx->state[4] += E; } +__weak void sha1_process(sha1_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + while (blocks--) { + sha1_process_one(ctx, data); + data += 64; + } +} + /* * SHA-1 process buffer */ @@ -242,17 +256,15 @@ void sha1_update(sha1_context *ctx, const unsigned char *input, if (left && ilen >= fill) { memcpy ((void *) (ctx->buffer + left), (void *) input, fill); - sha1_process (ctx, ctx->buffer); + sha1_process(ctx, ctx->buffer, 1); input += fill; ilen -= fill; left = 0; } - while (ilen >= 64) { - sha1_process (ctx, input); - input += 64; - ilen -= 64; - } + sha1_process(ctx, input, ilen / 64); + input += ilen / 64 * 64; + ilen = ilen % 64; if (ilen > 0) { memcpy ((void *) (ctx->buffer + left), (void *) input, ilen); diff --git a/lib/sha256.c b/lib/sha256.c index c1fe93de012dc8006abd14e7c95c5f6c4852c58c..50b0b511834fb840075f327b3e97b771a853cc2c 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -14,6 +14,8 @@ #include #include +#include + const uint8_t sha256_der_prefix[SHA256_DER_LEN] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, @@ -55,7 +57,7 @@ void sha256_starts(sha256_context * ctx) ctx->state[7] = 0x5BE0CD19; } -static void sha256_process(sha256_context *ctx, const uint8_t data[64]) +static void sha256_process_one(sha256_context *ctx, const uint8_t data[64]) { uint32_t temp1, temp2; uint32_t W[64]; @@ -186,6 +188,18 @@ static void sha256_process(sha256_context *ctx, const uint8_t data[64]) ctx->state[7] += H; } +__weak void sha256_process(sha256_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + while (blocks--) { + sha256_process_one(ctx, data); + data += 64; + } +} + void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length) { uint32_t left, fill; @@ -204,17 +218,15 @@ void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length) if (left && length >= fill) { memcpy((void *) (ctx->buffer + left), (void *) input, fill); - sha256_process(ctx, ctx->buffer); + sha256_process(ctx, ctx->buffer, 1); length -= fill; input += fill; left = 0; } - while (length >= 64) { - sha256_process(ctx, input); - length -= 64; - input += 64; - } + sha256_process(ctx, input, length / 64); + input += length / 64 * 64; + length = length % 64; if (length) memcpy((void *) (ctx->buffer + left), (void *) input, length); diff --git a/lib/tizen/Makefile b/lib/tizen/Makefile deleted file mode 100644 index 3651ea21fbe528f40f9c5a4609fbce6523b5b11f..0000000000000000000000000000000000000000 --- a/lib/tizen/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 Samsung Electronics -# Donghwa Lee - -obj-$(CONFIG_TIZEN) += tizen.o diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c deleted file mode 100644 index 916b2597569cc205ef5a39329f3e6417b3f85c15..0000000000000000000000000000000000000000 --- a/lib/tizen/tizen.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - */ - -#include -#include -#include - -#include "tizen_logo_16bpp.h" -#include "tizen_logo_16bpp_gzip.h" - -#ifdef CONFIG_LCD -void get_tizen_logo_info(vidinfo_t *vid) -{ - switch (vid->vl_bpix) { - case 4: - vid->logo_width = TIZEN_LOGO_16BPP_WIDTH; - vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT; - vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET; - vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET; -#if defined(CONFIG_VIDEO_BMP_GZIP) - vid->logo_addr = (ulong)tizen_logo_16bpp_gzip; -#else - vid->logo_addr = (ulong)tizen_logo_16bpp; -#endif - break; - default: - vid->logo_addr = 0; - break; - } -} -#endif diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h deleted file mode 100644 index 12e86269c451f794030c38984a6698ae86d4afe2..0000000000000000000000000000000000000000 --- a/lib/tizen/tizen_logo_16bpp.h +++ /dev/null @@ -1,7934 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Samsung Electronics - * Przemyslaw Marczak - */ - -#ifndef __TIZEN_LOGO_16BPP__ -#define __TIZEN_LOGO_16BPP__ - -#define TIZEN_LOGO_16BPP_WIDTH 452 -#define TIZEN_LOGO_16BPP_HEIGHT 140 - -/* Center align offsets for word "TIZEN" */ -#define TIZEN_LOGO_16BPP_X_OFFSET (16) -#define TIZEN_LOGO_16BPP_Y_OFFSET (-20) - -/* Format: BMP RGB565 16BPP 452x140 */ -unsigned char tizen_logo_16bpp[] = { -0x42,0x4d,0xa6,0xee,0x01,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, -0x00,0x00,0xc4,0x01,0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, -0x00,0x00,0x60,0xee,0x01,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x21,0x08,0x86,0x31,0x65,0x29,0x41,0x08,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x20,0x00,0x20,0x08,0x20,0x00, -0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x08,0x20,0x00,0x20,0x00,0x20,0x00, -0x20,0x00,0x21,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0x34,0xa5,0xb6,0xb5, -0x96,0xb5,0x34,0xa5,0xd2,0x94,0xef,0x7b,0xeb,0x5a,0x08,0x42,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x61,0x08, -0x6e,0x6b,0x71,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x51,0x8c,0x71,0x8c, -0x71,0x8c,0x71,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c, -0x71,0x8c,0x51,0x8c,0x8a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x42, -0x10,0x84,0xb2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,0xb2,0x94, -0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xd2,0x94, -0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94, -0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xd2,0x94,0xd2,0x94, -0xb2,0x94,0xd2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,0xd2,0x94,0xd2,0x9c,0xd2,0x94, -0xb2,0x94,0xd2,0x94,0xb2,0x9c,0xd2,0x94,0xd2,0x94,0xd2,0x94,0xb3,0x94,0xd2,0x94, -0xb3,0x94,0xd2,0x94,0xb3,0x94,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c, -0x92,0x94,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe3,0x18,0x30,0x84, -0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5, -0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5, -0x14,0xa5,0x14,0x9d,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0x9d, -0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0x9d, -0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x34,0xa5, -0x30,0x84,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x10,0x84,0x34,0xa5, -0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, -0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, -0x30,0x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xe7,0x39,0x14,0xa5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x75,0xad,0x13,0x9d,0x72,0x94,0x8e,0x73,0x8a,0x52,0xa6,0x31, -0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xb2,0x94,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0x14,0xa5,0x14,0xa5,0xf3,0x9c, -0x2c,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x92,0x94,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xab,0x5a, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xef,0x7b,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0xc7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xd3,0x9c,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x51,0x8c,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x30,0x84,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xf7,0xbd,0x51,0x8c,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0x92,0x94,0x14,0xa5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0x55,0xa5,0xd3,0x9c,0x30,0x84,0x2c,0x63, -0x28,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xc3,0x18,0x55,0xad,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x8a,0x52,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xd7,0xb5,0xf7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x96,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5, -0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5, -0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5, -0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd7,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd7,0xbd,0x54,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xd7,0xbd,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0x55,0xad,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84, -0xf3,0x9c,0xf3,0x9c,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x91,0x94,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0xd6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x21,0x08,0x54,0xad,0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xb7,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xb6,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xb6,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd7,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xb5, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x54,0xad,0x41,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x21,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x4d,0x6b,0x14,0xa5,0xd3,0x9c,0xf3,0x9c,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4d,0x6b,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5, -0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb7,0xb5,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd, -0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xb5,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x4a,0x14,0xa5,0xf3,0x9c, -0xd2,0x94,0xd3,0x9c,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0xb6,0xb5,0x30,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08, -0x55,0xad,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5, -0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5, -0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0x55,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x45,0x29,0xf3,0x9c,0x13,0x9d,0xd3,0x9c,0xd2,0x94,0xd3,0x9c,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xb7,0xb5,0xd6,0xbd,0xb6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5, -0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5, -0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x71,0x8c,0x34,0xa5,0xf3,0x9c,0xd3,0x9c, -0xb2,0x94,0xd2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x61,0x08,0x55,0xad, -0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b, -0x55,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xd2,0x94,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5, -0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5, -0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd, -0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x34,0xa5,0xd7,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xeb,0x5a,0x54,0xad,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x9c, -0xb2,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xf3,0x9c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5, -0xd6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x75,0xad,0xd7,0xbd, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd7,0xb5,0xd7,0xb5, -0xd6,0xbd,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5, -0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0x34,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0x55,0xad,0x82,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x34,0xa5,0x54,0xa5, -0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8a,0x52,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xef,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x8e,0x73,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5, -0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5, -0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd7,0xbd,0x75,0xad,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x54,0xa5,0xd7,0xbd,0xd6,0xb5, -0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x82,0x10,0xf3,0x9c,0x55,0xad,0x34,0xa5,0x14,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x94, -0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xca,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5, -0xd6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x75,0xad,0xd7,0xbd,0xb6,0xb5, -0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5, -0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x75,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0x34,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0x75,0xad,0x55,0xad,0x34,0xa5, -0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd2,0x9c,0xb2,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0x13,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0x0f,0x7c,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xae,0x73,0xf7,0xbd,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd, -0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0x75,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x34,0xa5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5, -0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd7,0xb5,0xb6,0xb5, -0xd7,0xbd,0x75,0xad,0xc3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b, -0x96,0xb5,0x55,0xad,0x55,0xa5,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd2,0x94, -0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xf3,0x9c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0x75,0xad,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x75,0xad,0xa2,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5, -0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xbd,0x76,0xad,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x69,0x4a,0x76,0xad,0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5, -0x14,0xa5,0xf3,0x9c,0xf3,0x9c,0xb2,0x94,0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xd6,0xb5,0x0f,0x7c,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x73, -0xf7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0x75,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0x75,0xad,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x34,0xa5,0x96,0xad, -0x75,0xad,0x55,0xad,0x35,0xad,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94, -0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x14,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x52,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xc3,0x18,0x75,0xad,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x75,0xad,0xa3,0x18,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0x34,0xad,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xb2,0x94,0xb6,0xb5,0x76,0xad,0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5, -0x34,0xa5,0xf3,0x9c,0xf3,0x9c,0xd2,0x94,0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5, -0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x10,0x7c,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd, -0xb7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0x17,0xbe,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x54,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x54,0xa5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xd7,0xbd,0x75,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0xb6,0xb5,0x96,0xb5,0x75,0xad, -0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xd2,0x94, -0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x34,0xa5,0x20,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0xb6,0xb5,0xb6,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xf0,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf7,0xbd,0xd2,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xd2,0x9c,0xf7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x14,0x9d,0x62,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x66,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb6,0xb5,0xab,0x5a,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5, -0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xef,0x83,0xf7,0xbd, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xb5,0x96,0xb5, -0xf3,0x9c,0x2c,0x63,0x2c,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b, -0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b, -0x4d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b, -0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b, -0x2d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x0c,0x63, -0x8a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x75,0xad,0x0c,0x63,0xcb,0x5a,0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,0xeb,0x5a, -0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,0xcb,0x5a,0xeb,0x5a,0xaa,0x52,0x6a,0x4a, -0x8a,0x52,0x69,0x52,0x8a,0x4a,0x8a,0x52,0x6a,0x4a,0x8a,0x52,0x8a,0x52,0x8a,0x52, -0x8a,0x52,0x6a,0x52,0x89,0x4a,0x8a,0x52,0x8a,0x52,0x6a,0x4a,0x8a,0x52,0x89,0x52, -0x6a,0x52,0x6a,0x52,0x8a,0x52,0x6a,0x52,0x89,0x52,0x89,0x4a,0x8a,0x52,0x89,0x4a, -0x8a,0x4a,0x8a,0x52,0x8a,0x52,0x89,0x52,0x8a,0x4a,0x8a,0x4a,0x8a,0x52,0x69,0x4a, -0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd, -0xd7,0xbd,0x95,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0x95,0xad,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad, -0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xd3,0x9c,0xb2,0x94, -0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x34,0xa5,0x20,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x52,0xb6,0xb5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x39,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x92,0x94,0xd6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x76,0xb5,0x76,0xad,0x95,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad, -0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x8a,0x52,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x45,0x29,0xb6,0xb5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x14,0xa5,0xd7,0xbd, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5, -0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xb2,0x94,0xb2,0x94,0x92,0x94,0x96,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb7,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xd6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5, -0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xbd,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08, -0xf3,0x9c,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x75,0xad,0x95,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad, -0x55,0xad,0x55,0xad,0x49,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xb5, -0xd7,0xbd,0x96,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x51,0x8c,0xd7,0xbd,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xb5, -0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x14,0xa5,0x13,0x9d,0xd3,0x9c,0xd2,0x94, -0x92,0x94,0x92,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x34,0xa5,0x20,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb6,0xb5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xf7,0xbd,0xd2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x18,0x34,0xa5,0xb6,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xb5,0x96,0xb5,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x54,0xa5,0xc7,0x39, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5, -0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x9c,0x92,0x94,0x92,0x94,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5, -0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5, -0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x86,0x29,0x55,0xad,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad, -0x76,0xb5,0x95,0xb5,0x76,0xb5,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad, -0x55,0xad,0x55,0xad,0x75,0xad,0x14,0xa5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x42, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad, -0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x14,0xa5,0x13,0x9d,0xd3,0x9c,0xd2,0x94, -0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x34,0xa5,0x20,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x75,0xad, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xb5,0x75,0xb5, -0x95,0xad,0x75,0xb5,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x76,0xad, -0xf3,0x9c,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xc3,0x18,0x55,0xad,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5, -0x34,0xa5,0x14,0x9d,0xf3,0x9c,0xb2,0x9c,0x92,0x94,0x92,0x94,0x96,0xb5,0xd7,0xbd, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xd6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0xd6,0xb5, -0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd7,0xb5,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x52,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x76,0xb5,0x95,0xb5,0x96,0xad,0x76,0xad,0x76,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x92,0x94,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0xf7,0xbd, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xb5, -0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,0x34,0xa5,0x13,0x9d,0xd3,0x9c,0xd2,0x94, -0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0x34,0xa5,0x20,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x0c,0x63,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x95,0xb5,0x96,0xb5,0x96,0xad,0x75,0xb5,0x76,0xad,0x96,0xb5, -0x75,0xad,0x75,0xb5,0x95,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x96,0xb5,0x51,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xcf,0x7b,0xf7,0xbd,0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x54,0xa5, -0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x94,0x92,0x94,0x92,0x94,0x96,0xb5,0xd7,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd7,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xd6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xd6,0xb5, -0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xb7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0xd3,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x6b,0xb6,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xad,0x96,0xb5,0x96,0xb5,0x76,0xad,0x95,0xb5,0x75,0xb5,0x75,0xb5, -0x96,0xb5,0x95,0xb5,0x75,0xad,0x75,0xad,0x75,0xb5,0x75,0xad,0x96,0xb5,0xcf,0x7b, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0xd7,0xb5,0xd7,0xbd,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad, -0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd2,0x94, -0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x34,0xa5,0x41,0x08, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5, -0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5, -0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xef,0x7b,0xd6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29, -0x95,0xad,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x54,0xa5, -0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0x92,0x94,0xb2,0x94,0x96,0xb5,0xd6,0xbd, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xab,0x5a,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0xd7,0xbd, -0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd, -0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c, -0xd7,0xbd,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0xab,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5, -0x75,0xad,0x75,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x9c, -0xb2,0x94,0xb2,0x94,0x96,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x55,0xad,0x82,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb6,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x28,0x42,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0xf7,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x54,0xad, -0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xb2,0x94,0x96,0xb5,0xd7,0xbd, -0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0xf7,0xbd, -0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x41,0x08,0x13,0x9d,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x75,0xad,0xa7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xec,0x62,0xd7,0xbd,0xb6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xad, -0x75,0xad,0x75,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0xa5,0xf3,0x9c,0xd3,0x9c, -0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb7,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x54,0xa5,0xd7,0xbd, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0x55,0xad, -0x25,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x96,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x75,0xad,0x55,0xad,0x55,0xad, -0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0x92,0x94,0x96,0xb5,0xd7,0xbd, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0xf7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0x75,0xad,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x14,0xa5,0x62,0x10,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08, -0x14,0xa5,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd2,0x94, -0xb2,0x94,0x91,0x8c,0x76,0xad,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xd7,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0x55,0xad,0xa2,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x4a, -0xb6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5, -0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5, -0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xab,0x5a,0x34,0xa5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xeb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0xf7,0xbd, -0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x51,0x8c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x95,0xb5,0x4d,0x6b,0x0c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63, -0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63, -0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63, -0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63, -0x2c,0x63,0x2c,0x63,0x2c,0x63,0x6d,0x6b,0x6e,0x73,0x8e,0x73,0x4d,0x6b,0xe7,0x39, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4d,0x6b,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xf3,0x9c, -0x2d,0x6b,0x00,0x00,0x34,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5, -0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0x55,0xad,0x82,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x2d,0x6b,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x18,0xc6, -0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe, -0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xbe,0x17,0xc6,0x18,0xc6,0x18,0xc6, -0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x17,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0xf7,0xbd,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x28,0x42,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xad,0x75,0xad,0x55,0xad,0x55,0xad, -0x34,0xa5,0x14,0xa5,0x14,0x9d,0x30,0x84,0x00,0x00,0x00,0x00,0x54,0xa5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5, -0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x7b,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0x34,0xa5,0xb6,0xb5,0x96,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd7,0xbd,0xb7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x75,0xb5,0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5,0x14,0xa5,0xd3,0x9c,0x45,0x29, -0x00,0x00,0x21,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0x55,0xad,0xa2,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xaa,0x52,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x55,0xad,0x41,0x08,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x71,0x8c,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,0x75,0xad,0x55,0xad,0x55,0xa5, -0x34,0xa5,0x14,0xa5,0x8a,0x52,0x00,0x00,0x00,0x00,0x21,0x08,0x54,0xa5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x0c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x92,0x94,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd6,0xb5,0x28,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x96,0xb5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x55,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x9d,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xb6,0xb5,0x65,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0x96,0xb5,0x95,0xad,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x76,0xb5,0x75,0xad,0x55,0xad,0x55,0xa5,0x55,0xad,0xae,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x20,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x96,0xb5,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x55,0xad,0x21,0x08,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x4a,0x75,0xad, -0x75,0xad,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x75,0xb5,0x75,0xad,0x55,0xad,0x55,0xad, -0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x54,0xa5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xb7,0xbd, -0xd6,0xb5,0xd7,0xbd,0x75,0xad,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x0c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xaf,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x82,0x10,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x55,0xad,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x55,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xb6,0xb5,0x66,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0x14,0xa5,0x75,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x76,0xb5,0x75,0xad,0x55,0xad,0x34,0xa5,0x66,0x31,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x20,0x08,0x35,0xa5,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd, -0xb7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0x76,0xad,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x17,0xbe,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x75,0xad, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0x14,0xa5,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xc5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x75,0xad,0x82,0x10,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x71,0x94,0x75,0xad,0x55,0xad, -0x75,0xad,0x75,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,0x75,0xad,0x75,0xad,0xcb,0x5a, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x55,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0x95,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x96,0xb5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x76,0xb5,0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xc5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd6,0xb5,0x66,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8e,0x73,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x95,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5, -0x96,0xad,0x96,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x21,0x08,0x55,0xad,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x49,0x4a,0xd6,0xb5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0x30,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd6,0xb5,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0x34,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad, -0x75,0xad,0x75,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0xd3,0x9c,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0x95,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xeb,0x5a,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xae,0x73, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xf3,0x9c, -0x34,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x95,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0x55,0xad,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x4d,0x6b,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x04,0x21,0xb6,0xb5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0x86,0x31,0x00,0x00, -0x00,0x00,0x20,0x00,0x71,0x8c,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad, -0x75,0xad,0x76,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xeb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xce,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0x89,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0x96,0xb5,0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xc5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xc7,0x39,0x00,0x00,0x00,0x00,0x8e,0x73,0xf3,0x9c,0xf3,0x9c, -0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0x10,0x84, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0x17,0xbe,0xd3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x84,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0xe8,0x41,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xc6,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x17,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xa7,0x39,0x00,0x00, -0xaa,0x52,0xd3,0x9c,0xf3,0x9c,0xf3,0xa4,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad, -0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5, -0xb6,0xb5,0xd7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x92,0x94,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0x75,0xad,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0x96,0xb5,0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x65,0x29,0x45,0x29,0x92,0x94,0xd2,0x9c,0xd3,0x9c,0x13,0x9d, -0x14,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0x96,0xb5,0x86,0x31,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf3,0x9c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0xf7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xf7,0xbd,0x34,0xa5, -0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe, -0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0x89,0x4a,0xef,0x83, -0xb2,0x94,0xd2,0x94,0xf3,0x9c,0x13,0x9d,0x34,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad, -0x75,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xec,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa2,0x10,0x34,0xa5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5, -0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xc5,0xf7,0xbd,0x18,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe, -0x18,0xbe,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf8,0xc5,0x17,0xbe, -0xf8,0xbd,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe, -0xf8,0xc5,0x17,0xbe,0x17,0xc6,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0x18,0xbe,0x17,0xbe,0x17,0xc6,0xf7,0xbd,0xf8,0xbd,0xf7,0xbd,0xf7,0xbd,0x38,0xc6, -0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xc6,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x51,0x8c,0x71,0x8c,0x92,0x94,0xd2,0x94,0xf3,0x9c,0x13,0x9d, -0x14,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x29, -0x55,0xad,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xb6,0xb5,0xd7,0xb5, -0xf7,0xbd,0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,0x17,0xbe,0x17,0xc6,0xf7,0xbd,0xf8,0xbd, -0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0x18,0xbe,0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0xf8,0xbd, -0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6, -0x17,0xbe,0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x17,0xbe,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x55,0xad,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x51,0x8c, -0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad, -0x75,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x14,0xa5, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x25,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf8,0xc5,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x75,0xad,0xd7,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf7,0xbd,0xef,0x7b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6, -0x17,0xbe,0xf7,0xbd,0x18,0xbe,0x17,0xbe,0x17,0xc6,0xf7,0xbd,0x18,0xbe,0x17,0xbe, -0x17,0xbe,0x17,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0xf8,0xbd,0x17,0xbe, -0x18,0xc6,0x96,0xb5,0x28,0x42,0xa6,0x31,0xc7,0x39,0xa7,0x39,0xc7,0x39,0xc7,0x39, -0xa6,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29, -0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29, -0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29, -0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x31,0x66,0x31,0x65,0x29,0x65,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,0x92,0x94,0xd3,0x9c,0xf3,0x9c,0x13,0xa5, -0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x76,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0x96,0xb5,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x6b,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x92,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x49,0x4a,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6, -0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0xf8,0xc5, -0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x75,0xad,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c, -0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad, -0x95,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xec,0x62,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xaa,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xbe, -0xf8,0xc5,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xbe,0x17,0xbe, -0x17,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0xf7,0xc5,0x17,0xbe, -0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5, -0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x30,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x92,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x63,0x96,0xb5,0x96,0xb5,0x76,0xb5,0x96,0xad, -0x96,0xb5,0x95,0xb5,0x96,0xad,0x76,0xb5,0x96,0xad,0x76,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x28,0x42,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x75,0xad,0x41,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd2,0x94,0x71,0x8c, -0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad, -0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8e,0x73,0x95,0xb5,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x76,0xad,0x75,0xad,0x76,0xad,0x95,0xad,0x76,0xb5,0x95,0xad, -0x96,0xb5,0x55,0xad,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6, -0xf8,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xc6,0xf8,0xc5,0x18,0xbe,0x17,0xbe,0x17,0xc6, -0xf7,0xbd,0x18,0xbe,0x18,0xc6,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5, -0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb6,0xb5, -0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0x75,0xad,0x55,0xad, -0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad, -0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x14,0xa5,0x04,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x17,0xbe, -0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x17,0xc6,0x18,0xbe,0x17,0xc6, -0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x75,0xad,0x41,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd2,0x94,0x71,0x8c, -0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad, -0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xeb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x4d,0x6b,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd7,0xb5, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x10,0x84,0x55,0xad,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, -0x34,0xa5,0x34,0xa5,0x34,0xa5,0x54,0xa5,0x34,0xa5,0x54,0xa5,0x54,0xa5,0x54,0xa5, -0x35,0xad,0x54,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad, -0x75,0xad,0x75,0xad,0x96,0xb5,0xd2,0x94,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6, -0x18,0xc6,0x18,0xbe,0x17,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd3,0x9c,0x71,0x8c,0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5, -0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x17,0xc6,0x10,0x84,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x13,0x9d,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x65,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0xf8,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x92,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c, -0x34,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5, -0x34,0xa5,0x14,0xa5,0x34,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, -0x34,0xa5,0x34,0xa5,0x54,0xa5,0x54,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x76,0xb5, -0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xd2,0x9c,0x71,0x94, -0xd2,0x94,0xd3,0x9c,0x13,0x9d,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x76,0xad, -0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0x17,0xbe,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xa5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x08,0x71,0x8c,0x14,0xa5,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0xf3,0xa4,0x13,0x9d,0xf3,0x9c,0x13,0x9d, -0x14,0xa5,0x14,0x9d,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x14,0xa5,0x34,0xa5, -0x34,0xa5,0x34,0xa5,0x34,0xa5,0x54,0xa5,0x75,0xad,0xef,0x7b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe, -0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe, -0x18,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd3,0x9c,0x91,0x8c,0xb2,0x94,0xf3,0x9c,0xf3,0x9c,0x14,0xa5, -0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb7,0xbd,0xd6,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x66,0x31,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0x96,0xb5,0x65,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xe3,0x18,0x72,0x94,0xf3,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c, -0xf3,0x9c,0xd3,0x9c,0xf3,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, -0x54,0xa5,0x55,0xad,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xf3,0x9c,0x38,0xc6,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xd3,0x9c,0x92,0x94, -0xd2,0x94,0xf3,0x9c,0x13,0x9d,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xeb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x72,0x94,0xb2,0x94, -0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94, -0xb2,0x94,0xb2,0x94,0xb3,0x94,0xd2,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xf3,0x9c,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x55,0xad,0xcb,0x5a, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe, -0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xd3,0x9c,0x92,0x94,0xb3,0x94,0xf3,0x9c,0x14,0xa5,0x34,0xa5, -0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xd7,0xb5,0xd6,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0x96,0xb5,0x45,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xa6,0x31,0x71,0x8c,0x92,0x94,0x71,0x94,0x71,0x8c,0x72,0x94, -0x91,0x8c,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94, -0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x9c,0xd3,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c, -0x13,0x9d,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x28,0x42,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xa3,0x18,0xb6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x76,0xb5,0x41,0x08,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x13,0x9d,0x38,0xc6,0x18,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xf3,0x9c,0x92,0x94, -0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xb5, -0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xf7,0xbd,0x13,0x9d,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd6,0xb5,0xd7,0xb5,0x96,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8e,0x73,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe7,0x39, -0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c, -0x51,0x8c,0x51,0x8c,0x71,0x8c,0x71,0x8c,0x71,0x8c,0x92,0x94,0x92,0x94,0x92,0x94, -0x92,0x94,0xb2,0x94,0xd2,0x94,0xd2,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,0x14,0xa5, -0x14,0xa5,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x18,0xc6,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0x18,0xbe,0xf3,0x9c,0x92,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5, -0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd7,0xbd,0x96,0xb5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0x10,0x84,0x10,0x84,0x10,0x84, -0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x30,0x84,0x30,0x84, -0x30,0x84,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x71,0x8c,0x92,0x94,0x92,0x94, -0xb2,0x94,0xd2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0xd3,0x9c,0x24,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xa3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xf3,0x9c,0x38,0xc6,0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xc6, -0x17,0xbe,0x17,0xc6,0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xc6,0xf3,0x9c,0x92,0x94, -0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5, -0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xcb,0x5a,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x6d,0x6b,0xf7,0xbd,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x6d,0x6b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x45,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29, -0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29, -0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x31,0x65,0x29,0x66,0x31,0x65,0x29, -0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29, -0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29, -0x45,0x29,0x8d,0x6b,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x72,0x8c,0x71,0x8c, -0x72,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94, -0xb2,0x94,0xd2,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0x14,0xa5,0x34,0xa5, -0x34,0xa5,0x75,0xad,0xd3,0x9c,0xc3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0xb6,0xb5,0x69,0x4a,0xe7,0x39,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42, -0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42, -0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42, -0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42, -0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42, -0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42, -0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x18,0xc6,0x17,0xbe, -0xf8,0xc5,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0x18,0xc6,0xf3,0x9c,0x92,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5, -0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xf7,0xbd, -0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0x08,0x42,0xe8,0x41,0xe8,0x41, -0xe8,0x41,0xe8,0x41,0xe8,0x41,0xe8,0x41,0x08,0x42,0xe8,0x41,0x08,0x42,0xe8,0x41, -0x08,0x42,0xe8,0x41,0x08,0x42,0xe8,0x41,0x08,0x42,0x08,0x42,0x08,0x42,0xe8,0x41, -0x08,0x42,0x08,0x42,0x08,0x42,0xc7,0x39,0x30,0x84,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0x51,0x8c,0x29,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a, -0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a, -0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a, -0x49,0x4a,0xc3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x14,0xa5,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x2c,0x63, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0xf7,0xbd,0x2c,0x63,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0x9d,0x38,0xc6,0x17,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0xf8,0xbd, -0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf8,0xbd,0xf7,0xbd,0xf8,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xf3,0x9c,0xb2,0x94, -0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5, -0x96,0xb5,0xb6,0xb5,0xd7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x92,0x94, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x96,0xb5,0xe7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd3,0x9c, -0x38,0xc6,0x18,0xc6,0x18,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe, -0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x38,0xc6,0x8a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe, -0x38,0xc6,0xd7,0xb5,0xe3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x38,0xc6,0x17,0xc6, -0x18,0xbe,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0x18,0xc6,0x17,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0x18,0xc6,0xf3,0x9c,0xb2,0x94,0xf3,0x9c,0x13,0x9d,0x34,0xa5,0x54,0xa5, -0x55,0xad,0x75,0xad,0x76,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x75,0xad,0x45,0x29, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x6d,0x6b,0xf7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xbd, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x18,0xc6,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x18,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x21,0x00,0x75,0xad,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6, -0x17,0xc6,0xf8,0xbd,0x18,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xf4,0x9c,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe, -0x18,0xc6,0xf8,0xbd,0x18,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf8,0xc5, -0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x13,0x9d,0xb2,0x94, -0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5, -0xb6,0xb5,0xb6,0xb5,0xaa,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x14,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad, -0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf8,0xc5,0x17,0xbe, -0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6, -0x18,0xbe,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x38,0xc6,0x2c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe, -0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x38,0xc6,0x18,0xbe, -0x17,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xc5,0x17,0xbe, -0xf7,0xc5,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0xf7,0xbd,0x18,0xc6,0x14,0xa5,0xd2,0x94,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xa5, -0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xd6,0xb5,0xaf,0x73,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0xa4,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x86,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x18,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x18,0xc6,0x17,0xbe,0x17,0xbe,0x18,0xc6, -0x18,0xbe,0x17,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xc6,0x17,0xbe,0x18,0xbe,0x18,0xc6, -0x17,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x55,0xad,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x13,0xa5,0x38,0xc6,0x18,0xc6,0x17,0xbe,0x17,0xc6,0x18,0xbe,0x18,0xbe, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe, -0x18,0xbe,0xf8,0xbd,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6,0x14,0xa5,0xd3,0x9c, -0x13,0x9d,0x14,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0xb6,0xb5, -0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5, -0xb7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad, -0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6, -0x18,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x38,0xc6,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x9d,0x38,0xc6,0x18,0xbe, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6, -0xf8,0xbd,0x17,0xbe,0x17,0xc6,0x17,0xc6,0xf8,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe, -0xf8,0xc5,0x18,0xbe,0x14,0xa5,0xd3,0x9c,0x13,0x9d,0x34,0xa5,0x34,0xa5,0x55,0xad, -0x75,0xad,0x75,0xad,0x96,0xb5,0x55,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0x9c,0x17,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x86,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x18,0xc6,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x38,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x14,0xa5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x17,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xbe,0x18,0xc6,0x34,0xa5,0xd3,0x9c, -0x14,0xa5,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x95,0xb5,0x96,0xb5,0x8a,0x52, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xb7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5, -0x96,0xb5,0x96,0xb5,0x75,0xad,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5, -0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad, -0x18,0xc6,0x18,0xbe,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6, -0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd3,0x9c,0x38,0xc6,0x18,0xc6, -0x18,0xc6,0x17,0xbe,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x18,0xbe, -0x17,0xbe,0x18,0xc6,0x34,0xa5,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad, -0x75,0xad,0xb6,0xb5,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad,0x75,0xad,0x86,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xc5,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x38,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x38,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xb2,0x94,0x38,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x17,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6, -0x18,0xbe,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x54,0xa5,0xf3,0x9c, -0x34,0xa5,0x54,0xa5,0x55,0xad,0x55,0xad,0x96,0xb5,0x92,0x94,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5, -0x95,0xb5,0x75,0xad,0x75,0xad,0x66,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x14,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe, -0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0xeb,0x5a, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0x38,0xc6,0x17,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xbe, -0x18,0xbe,0x18,0xc6,0x54,0xad,0x13,0xa5,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad, -0x34,0xa5,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xb5,0x75,0xad,0x75,0xad,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xc5,0x17,0xbe,0xf7,0xc5,0x38,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x38,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6, -0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x38,0xc6,0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xb3,0x9c,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x54,0xad,0x14,0xa5, -0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x49,0x4a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5, -0x75,0xad,0x75,0xad,0x75,0xad,0xa7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd, -0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5, -0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5, -0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x14,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x42,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0xcb,0x5a,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd2,0x94,0x38,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x17,0xbe, -0x18,0xc6,0x18,0xc6,0x55,0xad,0x34,0xa5,0x54,0xa5,0x55,0xad,0x96,0xb5,0x6d,0x6b, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xb7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5, -0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x18,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x8a,0x52,0x18,0xc6,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0xf8,0xbd,0x38,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x41,0x08,0x76,0xad,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xd2,0x9c,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x75,0xad,0x34,0xa5, -0x55,0xad,0x76,0xb5,0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xad,0x75,0xad, -0x75,0xad,0x55,0xad,0x55,0xad,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xf7,0xbd, -0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd, -0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x14,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x52,0x18,0xc6, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe, -0x17,0xc6,0x17,0xbe,0x38,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad, -0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0xcb,0x5a,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0x38,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xbe, -0x18,0xc6,0x18,0xc6,0x75,0xad,0x34,0xa5,0x75,0xad,0x14,0xa5,0xe3,0x18,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5, -0x96,0xb5,0x96,0xb5,0x76,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0xa6,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5,0xd7,0xb5, -0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x18,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x8a,0x52,0x18,0xc6,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xc5,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf8,0xc5, -0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x38,0xc6,0xb2,0x94, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x41,0x08,0x76,0xad,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6, -0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xc3,0x18,0xd6,0xb5,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x0c,0x63,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x96,0xad,0x55,0xad, -0x75,0xad,0x29,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x18,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xad,0x75,0xad, -0x55,0xad,0x55,0xad,0x55,0xad,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xf7,0xbd, -0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd, -0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x34,0xa5,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x4a,0x38,0xc6, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd, -0x17,0xbe,0xf7,0xbd,0x17,0xc6,0xf7,0xbd,0xf7,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xbe, -0xf8,0xc5,0x17,0xbe,0x38,0xc6,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x96,0xb5, -0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,0xcb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xd6,0xb5,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x8c,0x18,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x96,0xb5,0x75,0xad,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xd3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xb6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0x96,0xb5,0x95,0xb5,0x75,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x86,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x50,0x84,0xf7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd, -0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0x18,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x65,0x29,0xf7,0xbd,0x18,0xc6,0xf8,0xc5,0x17,0xbe,0x17,0xc6, -0x17,0xbe,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x17,0xbe, -0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x58,0xc6,0xcf,0x7b, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x59,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, -0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,0x58,0xce,0x71,0x8c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x34,0xa5,0x59,0xce,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x58,0xc6,0x38,0xc6,0x58,0xc6,0x38,0xc6,0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x59,0xc6,0xb6,0xb5,0x82,0x10,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x0c,0x63,0x30,0x84,0xf3,0x9c,0x75,0xad, -0xf7,0xbd,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6, -0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xb6,0xb5,0x51,0x8c, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x63,0x18,0xc6, -0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,0x75,0xad, -0x75,0xad,0x75,0xad,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x6b,0xf7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf8,0xbd,0x17,0xbe, -0xf7,0xc5,0x17,0xbe,0x17,0xc6,0x17,0xbe,0x17,0xc6,0x38,0xc6,0x10,0x84,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x73, -0xd7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x17,0xbe, -0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xc6, -0x18,0xc6,0xf7,0xbd,0xf3,0x9c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29, -0x35,0xad,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, -0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe, -0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd, -0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, -0xd7,0xbd,0x76,0xad,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x54,0xa5, -0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5, -0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5, -0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5, -0x54,0xa5,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x29,0x4a,0x8e,0x73,0x71,0x8c, -0x34,0xa5,0x96,0xb5,0x17,0xbe,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6, -0x18,0xc6,0x38,0xc6,0x55,0xad,0xa2,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, -0x34,0xa5,0x34,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x13,0x9d,0xf3,0x9c,0xf3,0x9c, -0xf3,0x9c,0xd3,0x9c,0xd3,0x9c,0xb2,0x94,0xb2,0x94,0xef,0x7b,0x04,0x21,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad, -0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad, -0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad, -0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad, -0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad, -0x75,0xad,0x31,0x8c,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xc7,0x39,0xc7,0x39,0xc7,0x39, -0xc7,0x39,0xc7,0x39,0xa7,0x39,0xc7,0x39,0xc7,0x39,0xc7,0x39,0xa7,0x39,0xc7,0x39, -0xc7,0x39,0xc7,0x39,0xa7,0x39,0xc7,0x39,0xc7,0x39,0x86,0x31,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0x66,0x31,0x66,0x31, -0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31, -0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31, -0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31, -0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31, -0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x45,0x29,0x24,0x21,0x24,0x21,0x24,0x21, -0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21, -0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x24,0x21,0x24,0x21,0x24,0x21, -0x24,0x21,0x24,0x29,0x24,0x21,0xe3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18, -0xc3,0x18,0xc3,0x18,0x61,0x08,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x86,0x31,0xaa,0x52, -0xef,0x7b,0xd3,0x9c,0x75,0xad,0xd6,0xb5,0xf7,0xbd,0xb6,0xb5,0x8a,0x52,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0x00,0xc6,0x00,0xc5,0x00,0xc6,0x00, -0xc5,0x00,0x85,0x00,0x84,0x00,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x41,0x08,0xa2,0x10,0x82,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10, -0x82,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10, -0xa2,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10, -0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10, -0xa3,0x10,0xa2,0x10,0xa2,0x18,0xa3,0x10,0x82,0x10,0x21,0x08,0x21,0x08,0x20,0x08, -0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08, -0x21,0x08,0x21,0x08,0x21,0x08,0x20,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08, -0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08, -0x21,0x08,0x21,0x08,0x21,0x08,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21, -0x66,0x31,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xd6,0x33,0x99,0x44,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x44,0x98,0x4c,0x99,0x54, -0x78,0x54,0xb5,0x3b,0x6f,0x1a,0x28,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, -0x69,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x12,0x99,0x44,0x99,0x44,0x99,0x44, -0x99,0x44,0x79,0x44,0x99,0x44,0xda,0x4c,0x1b,0x5d,0x3c,0x65,0xfb,0x4c,0x79,0x34, -0xb5,0x23,0xcb,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x23,0x79,0x3c,0xc6,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x12,0x23,0xb9,0x44,0x79,0x44,0x79,0x44,0x78,0x44,0x79,0x44,0x78,0x44, -0x99,0x4c,0xfa,0x5c,0x1b,0x65,0xfb,0x54,0x9a,0x3c,0x59,0x24,0xd1,0x22,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x0a,0x79,0x3c, -0x79,0x3c,0x4e,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xf6,0x33,0x99,0x44, -0x78,0x44,0x79,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x99,0x44,0xda,0x54,0x1b,0x5d, -0xfb,0x54,0x9a,0x3c,0x59,0x24,0x72,0x3b,0x20,0x08,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xa6,0x00,0x37,0x34,0x79,0x3c,0x79,0x3c,0xb5,0x2b,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x07,0x01,0x58,0x44,0x79,0x44,0x78,0x44,0x78,0x44,0x78,0x44, -0x58,0x44,0x58,0x3c,0x78,0x44,0xb9,0x4c,0x1b,0x5d,0x1b,0x5d,0xba,0x44,0x79,0x2c, -0xb2,0x5b,0xa1,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x95,0x2b,0x79,0x3c,0x58,0x3c, -0x79,0x3c,0x58,0x3c,0xc6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x12, -0x99,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x3c,0x58,0x44, -0x99,0x4c,0xfa,0x5c,0x1b,0x5d,0xba,0x44,0x78,0x4c,0xf0,0x7b,0x24,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xb0,0x1a,0x79,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x99,0x3c,0x6f,0x12,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x23,0x99,0x44,0x58,0x44,0x78,0x44, -0x58,0x44,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x79,0x44,0xda,0x54,0x1b,0x5d, -0xda,0x4c,0xd5,0x84,0x50,0x8c,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x01,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, -0x58,0x3c,0x79,0x3c,0xb5,0x2b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x01,0x00,0xd6,0x33,0x79,0x44,0x58,0x44,0x58,0x44,0x58,0x44,0x58,0x3c,0x58,0x3c, -0x58,0x3c,0x58,0x3c,0x79,0x44,0xda,0x54,0x1b,0x5d,0x18,0x85,0x13,0xa5,0x71,0x8c, -0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x00,0xf6,0x33, -0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x79,0x3c,0x58,0x34,0xa6,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x01,0x37,0x3c,0x58,0x44, -0x58,0x44,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x44, -0xba,0x4c,0x59,0x8d,0x96,0xb5,0x14,0xa5,0x92,0x94,0xeb,0x5a,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x33,0x23,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, -0x58,0x3c,0x58,0x3c,0x58,0x34,0xed,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x2d,0x12,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x3c,0x58,0x3c, -0x58,0x3c,0x58,0x44,0x58,0x3c,0x58,0x3c,0x79,0x34,0x59,0x85,0x58,0xce,0xd6,0xb5, -0x34,0xa5,0xb2,0x94,0x6d,0x6b,0x20,0x00,0x00,0x00,0x2e,0x12,0x58,0x3c,0x58,0x3c, -0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x58,0x34,0x38,0x2c,0xf2,0x12, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8f,0x1a, -0x74,0x2b,0x94,0x2b,0xb5,0x33,0xb5,0x33,0xd5,0x33,0xd6,0x33,0xf6,0x33,0xf6,0x33, -0xd6,0x23,0xf7,0x7c,0x9a,0xd6,0x59,0xce,0xd7,0xbd,0x55,0xad,0xd3,0x9c,0xae,0x73, -0xa8,0x21,0xf7,0x33,0x38,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, -0x58,0x3c,0x38,0x34,0xf7,0x23,0x74,0x1b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00, -0x01,0x00,0x02,0x00,0x23,0x00,0x23,0x00,0x01,0x00,0xec,0x5a,0xba,0xd6,0x9a,0xd6, -0x79,0xce,0xf7,0xbd,0x75,0xad,0xd3,0x9c,0x51,0x84,0x36,0x4c,0x38,0x34,0x58,0x3c, -0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x17,0x2c,0xf7,0x1b,0x95,0x23, -0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0xec,0x5a, -0x30,0x84,0x8e,0x73,0x20,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xe7,0x39,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x99,0xce,0x18,0xc6,0x96,0xb5, -0xd2,0x9c,0xd4,0x43,0x38,0x34,0x38,0x3c,0x38,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, -0x58,0x34,0x17,0x24,0xd6,0x1b,0xb5,0x23,0x85,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x69,0x4a,0x0f,0x7c,0x71,0x8c,0xd3,0x9c,0x55,0xad,0xb2,0x94,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xba,0xd6,0x9a,0xd6, -0x9a,0xd6,0x9a,0xd6,0x99,0xd6,0x59,0xce,0x0f,0x84,0xcc,0x01,0x58,0x3c,0x38,0x3c, -0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x37,0x2c,0xf6,0x23,0xb5,0x13,0x53,0x23, -0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xae,0x73,0x51,0x8c,0xb2,0x94,0x14,0xa5, -0x75,0xad,0xf7,0xbd,0x79,0xce,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xe7,0x39,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x38,0xc6, -0xc3,0x18,0x24,0x00,0x17,0x34,0x58,0x34,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x34, -0x17,0x2c,0xd6,0x1b,0x95,0x13,0xd0,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x29,0x6d,0x6b,0x51,0x8c, -0x92,0x94,0xf3,0x9c,0x55,0xad,0xd6,0xb5,0x38,0xc6,0x79,0xce,0x9a,0xd6,0xba,0xd6, -0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x9a,0xd6,0x9a,0xd6, -0x99,0xd6,0x9a,0xd6,0x9a,0xd6,0x8a,0x52,0x00,0x00,0x00,0x00,0x74,0x23,0x58,0x3c, -0x58,0x3c,0x58,0x3c,0x58,0x3c,0x38,0x34,0xf7,0x23,0xd6,0x13,0x94,0x1b,0xa9,0x21, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0x10, -0xeb,0x5a,0x30,0x84,0x71,0x94,0xd3,0x9c,0x34,0xa5,0x96,0xb5,0xf7,0xbd,0x79,0xce, -0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x79,0xce,0xa6,0x31,0x00,0x00,0x00,0x00, -0x00,0x00,0xc7,0x39,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x51,0x8c,0x00,0x00, -0x00,0x00,0x00,0x00,0x0d,0x12,0x58,0x3c,0x58,0x34,0x58,0x3c,0x58,0x3c,0x37,0x2c, -0xd6,0x0b,0x95,0x03,0xd2,0x5b,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x08,0x8a,0x4a,0x11,0x74,0x72,0x84,0xb3,0x8c,0x14,0x9d,0x75,0xb5, -0xf7,0xbd,0x58,0xce,0x99,0xce,0x9a,0xd6,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6, -0xba,0xd6,0xd7,0xbd,0x41,0x08,0x00,0x00,0x00,0x00,0x86,0x31,0x79,0xce,0x9a,0xd6, -0xba,0xd6,0x96,0xb5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x85,0x00,0x17,0x34, -0x58,0x3c,0x58,0x34,0x38,0x24,0xd7,0x03,0x16,0x3c,0xb5,0x84,0x6d,0x6b,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x22,0x15,0x4c,0x78,0x4c,0xb9,0x4c, -0xfa,0x54,0xfa,0x64,0xf9,0x64,0x39,0x85,0xd9,0xad,0x39,0xc6,0xba,0xd6,0xda,0xd6, -0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x9a,0xd6,0xda,0xd6,0xd3,0x9c,0x00,0x00, -0x00,0x00,0x86,0x31,0x79,0xce,0xba,0xd6,0x59,0xce,0x65,0x29,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x13,0x58,0x2c,0x78,0x4c,0xf8,0x74,0x78,0x95, -0xb7,0xb5,0x54,0xad,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa5,0x00,0xb5,0x33, -0x79,0x2c,0x9a,0x2c,0xdb,0x44,0xfb,0x54,0xfb,0x54,0xda,0x54,0xda,0x4c,0xba,0x4c, -0x99,0x44,0xc8,0x21,0xe8,0x41,0x92,0x94,0xd7,0xbd,0x9a,0xd6,0xda,0xd6,0xba,0xd6, -0xba,0xd6,0x9a,0xd6,0xba,0xd6,0x2c,0x63,0x00,0x00,0xe4,0x20,0xf7,0xbd,0xba,0xd6, -0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x91,0x5b, -0xb9,0x9d,0x59,0xbe,0x9a,0xd6,0x59,0xce,0xd7,0xbd,0x10,0x84,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x85,0x00,0xf7,0x2b,0x9a,0x2c,0xba,0x44,0xfb,0x54,0xfb,0x5c,0xfa,0x54, -0xda,0x54,0xda,0x54,0xba,0x54,0xda,0x54,0xf6,0x3b,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xa7,0x39,0xcf,0x7b,0x96,0xb5,0x59,0xce,0xba,0xd6,0xdb,0xde,0x96,0xb5, -0x00,0x00,0x00,0x00,0xe3,0x18,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x29,0x4a,0x92,0x94,0xf7,0xbd,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x79,0xce,0x18,0xbe, -0x75,0xad,0xe7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb5,0x2b,0xbb,0x3c,0xdb,0x4c, -0x1b,0x5d,0xfb,0x5c,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54, -0x8e,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x45,0x29,0x4d,0x6b,0x34,0xa5,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x08,0x42,0x92,0x94,0xf7,0xbd,0xba,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6, -0x9a,0xd6,0x9a,0xd6,0x59,0xce,0xf7,0xbd,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8f,0x1a,0xfb,0x4c,0x1b,0x5d,0x1b,0x5d,0xfa,0x5c,0xfa,0x54,0xda,0x54,0xda,0x54, -0xda,0x54,0xda,0x54,0xda,0x54,0x99,0x4c,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x9a,0xd6,0xba,0xd6,0xba,0xd6, -0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x99,0xce,0x38,0xc6,0xb6,0xb5, -0xab,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x22,0x00,0xb9,0x54,0x3b,0x5d,0x1b,0x5d,0xfa,0x54, -0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xb5,0x3b, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x45,0x29,0x38,0xc6,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6, -0x9a,0xd6,0x79,0xce,0xf7,0xbd,0x14,0xa5,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x22, -0x3c,0x5d,0x1b,0x5d,0xfa,0x54,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54, -0xda,0x54,0xda,0x54,0xda,0x54,0x0b,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xae,0x73,0xb6,0xb5,0x79,0xce,0x8e,0x73, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x20,0xeb,0x5a,0x34,0xa5, -0x38,0xc6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0x58,0xc6,0xb6,0xb5,0x8d,0x6b, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x37,0x4c,0x1b,0x5d,0xfb,0x54,0xfa,0x54,0xda,0x54, -0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0x78,0x4c,0x02,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0x30,0x84,0xd7,0xb5,0x9a,0xd6, -0xda,0xd6,0xba,0xd6,0xdb,0xde,0x75,0xad,0x00,0x00,0x00,0x00,0x8a,0x52,0x8e,0x73, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xaa,0x52,0xf3,0x9c,0x18,0xc6, -0x9a,0xd6,0x38,0xc6,0x55,0xad,0x24,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x01,0xfb,0x5c, -0xfb,0x5c,0xfb,0x54,0xfb,0x54,0xfa,0x54,0xfa,0x54,0xfa,0x54,0xda,0x54,0xfa,0x54, -0xfb,0x54,0xba,0x54,0xaf,0x22,0x00,0x00,0x00,0x00,0x49,0x4a,0x92,0x94,0x38,0xc6, -0xba,0xd6,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0xba,0xd6,0x79,0xce,0x86,0x31, -0x00,0x00,0x45,0x29,0x9a,0xd6,0xdb,0xde,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x08,0x42,0x10,0x7c,0x32,0x74,0x01,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x10,0x2b,0x1b,0x5d,0xfb,0x5c,0xfb,0x5c,0xfb,0x5c,0xfb,0x5c, -0x1b,0x55,0xfb,0x54,0x98,0x4c,0xb5,0x3b,0x4d,0x1a,0xc5,0x00,0x00,0x00,0x00,0x00, -0x10,0x84,0xf7,0xbd,0xba,0xd6,0xfb,0xde,0xdb,0xde,0xba,0xd6,0x9a,0xd6,0x9a,0xd6, -0xba,0xd6,0xba,0xd6,0x6d,0x6b,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6, -0xba,0xd6,0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x45,0x00,0x54,0x23,0x58,0x34,0xf6,0x33,0xf2,0x22,0x69,0x01,0x02,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x57,0x4c,0x1b,0x5d, -0x1b,0x5d,0x1b,0x5d,0xfb,0x5c,0x58,0x4c,0x53,0x33,0xea,0x11,0x43,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0x96,0xb5,0x59,0xce,0xdb,0xde, -0xdb,0xde,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xdb,0xd6,0x34,0xa5,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0x79,0xce,0xba,0xd6,0xba,0xd6,0x58,0xc6,0x45,0x29,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x4e,0x12,0x38,0x3c,0x99,0x44,0x79,0x44,0x99,0x44, -0x99,0x44,0x99,0x44,0x17,0x3c,0x12,0x23,0x89,0x01,0x02,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x26,0x01,0x1b,0x5d,0xda,0x54,0x16,0x44,0xef,0x2a,0x47,0x09,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xaa,0x52,0x75,0xad,0x38,0xc6,0xda,0xd6,0xfb,0xde,0xba,0xd6,0xba,0xd6,0xba,0xd6, -0x18,0xc6,0xe3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6, -0x9a,0xd6,0xba,0xd6,0xb6,0xb5,0x00,0x00,0x00,0x00,0x85,0x00,0x74,0x2b,0x99,0x44, -0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x99,0x44,0xba,0x44, -0xb9,0x44,0x17,0x3c,0x12,0x23,0x89,0x01,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xea,0x11,0xc5,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0x54,0xa5,0xf7,0xbd,0xba,0xd6, -0xfb,0xde,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0x79,0xce,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xda,0xd6,0x92,0x94, -0xab,0x01,0x37,0x3c,0x99,0x44,0x78,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44, -0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x9a,0x44,0xba,0x44,0xba,0x44, -0x38,0x3c,0x53,0x23,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x41,0x08,0xb2,0x94,0xd7,0xb5,0x79,0xce,0xfb,0xde,0xdb,0xde,0xda,0xde,0x10,0x84, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6, -0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x59,0x85,0x79,0x34,0x79,0x44,0x79,0x44, -0x99,0x44,0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44, -0x99,0x44,0x99,0x44,0x99,0x44,0x9a,0x44,0xda,0x44,0x79,0x44,0x07,0x01,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0x96,0xb5,0x59,0xce, -0xdb,0xde,0xfb,0xde,0x3a,0xbe,0xc9,0x19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0x79,0xce,0xda,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6, -0x9a,0xce,0xf9,0x6c,0x59,0x34,0x79,0x44,0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44, -0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0xba,0x44,0xba,0x44, -0xb5,0x2b,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x2c,0x63,0x75,0xad,0x18,0xc6,0xda,0xde,0xdb,0xd6,0x3a,0x75,0x99,0x44, -0x6d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0xba,0xd6,0x1c,0xe7, -0xfb,0xde,0xfb,0xde,0xfb,0xde,0xdb,0xde,0xfb,0xde,0x7a,0xc6,0x98,0x4c,0x38,0x2c, -0x58,0x34,0x58,0x34,0x58,0x34,0x79,0x3c,0x79,0x3c,0x79,0x3c,0x79,0x3c,0x79,0x3c, -0x99,0x3c,0x9a,0x44,0x79,0x44,0xb0,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe7,0x39,0x55,0xad,0xf7,0xbd, -0xba,0xd6,0xda,0x9d,0xba,0x44,0xda,0x54,0xda,0x54,0x73,0x33,0x02,0x00,0x00,0x00, -0x00,0x00,0x65,0x29,0xda,0xde,0x1c,0xe7,0x1b,0xdf,0x1c,0xe7,0x1b,0xdf,0x1c,0xdf, -0x1c,0xe7,0x3c,0xe7,0x1a,0xb6,0xd6,0x13,0xd6,0x13,0xf6,0x23,0xf7,0x23,0x17,0x24, -0x17,0x24,0x17,0x24,0x17,0x24,0x38,0x2c,0x38,0x2c,0xb5,0x23,0x28,0x01,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xa3,0x18,0xf3,0x9c,0xd7,0xbd,0xd9,0xa5,0xba,0x4c,0xda,0x4c,0xda,0x54, -0xda,0x54,0xda,0x54,0x37,0x44,0x07,0x01,0x00,0x00,0xa7,0x39,0x59,0xce,0x79,0xce, -0x99,0xce,0x9a,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0xdb,0xde,0xfb,0xde,0x58,0x95, -0x74,0x03,0x95,0x03,0x95,0x1b,0x95,0x1b,0xb5,0x1b,0xb5,0x1b,0xd6,0x1b,0xd6,0x1b, -0x6f,0x0a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0x96,0xad, -0x98,0x54,0x99,0x3c,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0x99,0x4c, -0x48,0x01,0x00,0x00,0x0c,0x63,0x8e,0x73,0x30,0x84,0x92,0x94,0xf3,0x9c,0x34,0xa5, -0x75,0xad,0xb6,0xb5,0x18,0xbe,0x58,0xc6,0x16,0x95,0x93,0x3b,0x33,0x0b,0x53,0x13, -0x53,0x13,0x73,0x1b,0xd0,0x1a,0xe7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x8d,0x73,0xf6,0x8c,0x17,0x0c,0x99,0x44,0xda,0x54,0xda,0x54, -0xda,0x54,0xda,0x54,0xda,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0xe4,0x20,0x86,0x31,0x08,0x42, -0xeb,0x5a,0xcc,0x52,0x4c,0x32,0x4d,0x1a,0x0c,0x1a,0xe6,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x52,0x55,0x64, -0xf7,0x03,0x79,0x3c,0xda,0x4c,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xfa,0x54, -0xaf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x45,0x29,0xf5,0x4b,0xf7,0x03,0x58,0x34,0xda,0x4c,0xda,0x54, -0xda,0x54,0xda,0x54,0xfa,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x52,0x33, -0xd6,0x0b,0x38,0x2c,0xba,0x4c,0xfa,0x54,0xfa,0x54,0xfa,0x54,0xda,0x54,0xfb,0x54, -0xaf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xd0,0x2a,0xd6,0x13,0x18,0x24,0x99,0x44,0xfb,0x54, -0xfb,0x54,0xfb,0x54,0xfa,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89,0x11, -0xd6,0x23,0x17,0x1c,0x79,0x3c,0xfa,0x54,0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x55, -0x8e,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb0,0x22,0x18,0x1c,0x79,0x34,0xda,0x54, -0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x5d,0x8d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x12,0x1b,0x59,0x2c,0xda,0x4c,0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x55, -0x8d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd1,0x1a,0xda,0x4c, -0x1b,0x55,0xfb,0x5c,0xfb,0x54,0x1b,0x5d,0x6c,0x1a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x1a,0xda,0x54,0x1b,0x5d,0xfb,0x54,0x1b,0x5d, -0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x67,0x09,0x78,0x4c,0x3c,0x5d,0x1c,0x5d,0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x73,0x33,0x3c,0x5d, -0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00}; -#endif diff --git a/lib/tizen/tizen_logo_16bpp_gzip.h b/lib/tizen/tizen_logo_16bpp_gzip.h deleted file mode 100644 index d8526f88a949128e43ef97e4b4db3e7809ca6f29..0000000000000000000000000000000000000000 --- a/lib/tizen/tizen_logo_16bpp_gzip.h +++ /dev/null @@ -1,647 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Samsung Electronics - * Przemyslaw Marczak - */ - -#ifndef __TIZEN_LOGO_16BPP_GZIP__ -#define __TIZEN_LOGO_16BPP_GZIP__ - -/* Format: GZIP: BMP RGB565 16BPP 452x140 */ -unsigned char tizen_logo_16bpp_gzip[] = { -0x1f,0x8b,0x08,0x08,0xd9,0x76,0x29,0x53,0x00,0x03,0x74,0x69,0x7a,0x65,0x6e,0x5f, -0x6c,0x6f,0x67,0x6f,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9d,0x6f,0x6c,0x1b,0x67,0x7e, -0xe7,0xa9,0x4d,0x80,0x65,0xbb,0x2e,0x56,0xb1,0xd8,0x25,0xcf,0x0a,0x70,0x52,0xa4, -0x2d,0xc2,0x5a,0x39,0x58,0x35,0xf7,0x42,0x35,0x7a,0x63,0xd5,0x6a,0x1b,0x9d,0x5c, -0xd4,0x0a,0x85,0xca,0xde,0x35,0x70,0x1b,0xc7,0x29,0xbc,0xaa,0xbb,0x50,0x14,0x0a, -0xd6,0x79,0xdf,0x9c,0x2b,0x07,0x88,0xa1,0xb8,0x88,0x4a,0x11,0x2b,0x83,0x7a,0x71, -0xc9,0xd2,0x6e,0x1d,0x4c,0x76,0xa1,0x60,0x28,0x44,0xc5,0xe8,0x8d,0x6b,0xba,0xbd, -0x14,0xca,0x56,0xba,0x0e,0x51,0x05,0x70,0x0b,0x24,0xa8,0x83,0x7a,0xef,0x5c,0x54, -0x77,0x61,0x6a,0xbf,0xb9,0x79,0xe6,0x99,0xe7,0x79,0x7e,0xf3,0x87,0x9c,0x67,0x86, -0xc3,0x7f,0xca,0xf3,0x7d,0x30,0x1a,0x92,0xe2,0x9f,0x21,0x39,0x1f,0x7e,0x7f,0xcf, -0xbf,0xdf,0x33,0x72,0xe2,0xc6,0xff,0xe9,0x08,0x21,0xfd,0xb6,0xb6,0x25,0xb5,0xed, -0xaf,0xb4,0xab,0x8b,0xda,0xbe,0x23,0xd4,0x19,0x7a,0x42,0xdb,0xff,0x57,0xed,0xff, -0x1d,0xfa,0x75,0xa0,0x2f,0x43,0xa1,0x7f,0xfa,0x7a,0x28,0xf4,0x1f,0x43,0x42,0x42, -0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x5f,0x3d,0xf5,0x86,0xdf,0x18,0x3c,0x17,0x3f, -0x16,0x6e,0xf6,0x71,0x08,0x09,0xb5,0x8a,0x7a,0xc3,0x3d,0xa1,0x1e,0xb4,0x91,0x42, -0x2f,0xf7,0x6a,0x5b,0x3d,0x74,0x6b,0x22,0x91,0x2f,0xc8,0x59,0x39,0x91,0xdf,0xce, -0x3c,0xbc,0xf4,0xe0,0x74,0x78,0xe4,0xc9,0xde,0xba,0xbc,0x50,0xcb,0xab,0xa7,0x6e, -0xcf,0xfc,0xfd,0xf0,0x1f,0x4f,0xcf,0x2c,0x9e,0xd4,0xcb,0x8c,0xbe,0xcd,0x2c,0xce, -0xd0,0x6b,0x27,0x8d,0x6b,0x57,0x27,0xfc,0x3e,0xff,0xb3,0x23,0x9d,0x0b,0x6b,0x99, -0xb5,0xcc,0xb6,0xb1,0x59,0xcb,0x76,0x95,0x6b,0xe8,0xfa,0x36,0x78,0xac,0x76,0x2d, -0x67,0x5c,0xce,0x6d,0xeb,0xff,0xfb,0x80,0x6e,0x7b,0x39,0x52,0x96,0x32,0xe1,0x11, -0xde,0xa3,0xfb,0x34,0x76,0x64,0x81,0x3d,0x92,0xbf,0x44,0xf2,0x55,0xcb,0x6a,0x85, -0xcb,0x0e,0xd7,0x13,0xf9,0x23,0x0b,0x2f,0x77,0xf2,0x1d,0x6d,0x6f,0xb8,0x73,0x21, -0x91,0x77,0x2b,0x47,0x16,0x79,0x9f,0x8f,0x4f,0xf7,0x87,0x22,0x1a,0x85,0xb8,0xa8, -0x5a,0x41,0xfb,0xb4,0xd4,0xb5,0xfa,0x5a,0xe6,0xda,0xec,0xd5,0x89,0x1b,0x83,0xef, -0x04,0xfa,0x6a,0xcd,0x54,0x78,0x64,0x2d,0xe3,0xf6,0xad,0xef,0xe5,0x06,0xa6,0xeb, -0xf1,0xda,0x4b,0x99,0x92,0xa2,0xca,0x25,0xb9,0xa4,0xa0,0x0d,0x7d,0xce,0xf8,0x92, -0x7e,0xab,0xa2,0x2a,0x25,0xa3,0xbc,0x77,0xda,0xcf,0xb3,0x3f,0xbc,0x84,0x9f,0x8b, -0xb7,0x94,0xc1,0x9e,0x6f,0x2b,0x3b,0xdc,0x56,0x90,0xef,0x0e,0xf1,0x1d,0xdf,0x4e, -0xce,0xe9,0xf1,0x7c,0x5b,0x50,0xa5,0xac,0x9c,0x5c,0xe4,0x3b,0xda,0x23,0x0b,0xf0, -0x75,0xf5,0xef,0xc7,0xf8,0x74,0xf5,0xef,0x49,0xff,0xbe,0x54,0x0f,0xcf,0xc7,0xa3, -0xdb,0xb1,0xa5,0x0c,0xe3,0x10,0x16,0xd5,0xa0,0x72,0x32,0xbf,0x93,0x3b,0xb2,0x30, -0x70,0xf6,0x59,0xee,0x5f,0xbf,0xd6,0xd4,0xed,0xd8,0xa4,0xe4,0xf4,0x3e,0xed,0xc5, -0xbf,0x2b,0x55,0xd2,0xb9,0x41,0xbe,0x57,0x2e,0x29,0x4b,0x19,0xef,0xcf,0x3e,0x70, -0xb6,0xa4,0xb0,0x6f,0xad,0x60,0xfc,0x96,0xb2,0xcb,0xf0,0x36,0xf2,0xbd,0xaa,0xf4, -0xfb,0x55,0x4d,0xb7,0xb2,0xfb,0x94,0xd0,0x5f,0x05,0xef,0xf5,0x5f,0x0e,0x6d,0x2b, -0x68,0xdb,0xba,0x76,0x7d,0x5d,0xbf,0xbd,0xac,0xbc,0x3f,0xcb,0x73,0x7c,0xa3,0xf1, -0x2c,0xfd,0xed,0xc1,0xdb,0x3a,0xd9,0xcb,0x78,0xa3,0xcf,0x4d,0x36,0x19,0x5f,0x2f, -0x81,0x6d,0x5d,0x66,0x8f,0x55,0xe1,0xfd,0x8c,0xe3,0xc6,0xc7,0x8b,0xf6,0xf6,0xf7, -0x58,0xd0,0x1f,0x9b,0xca,0xf3,0x7d,0x9e,0x89,0x3c,0x7a,0x1d,0xf8,0x99,0x39,0x7f, -0x57,0x93,0x52,0x70,0x8e,0xd8,0xa9,0xc7,0x0b,0xd9,0x0a,0xaf,0x95,0xa5,0xdf,0x27, -0xfa,0xfb,0xb6,0x8f,0x73,0xa4,0x75,0xf4,0xe2,0x18,0x7a,0x3f,0xee,0x45,0x95,0x3b, -0x17,0x82,0x7e,0xed,0x1b,0x9c,0x1c,0xaa,0xca,0x9a,0xe7,0xcf,0xb8,0x37,0x9c,0x92, -0x54,0xa5,0x60,0xfa,0xa6,0xcc,0x44,0x15,0xc0,0xf5,0x02,0xbd,0x8e,0xcf,0x5a,0x72, -0x26,0xaf,0x93,0x47,0x29,0x6c,0x4f,0xa8,0xa0,0x44,0x2a,0x2a,0xf5,0xf3,0x92,0xee, -0x08,0x1f,0x5f,0xe2,0x39,0xc2,0x73,0xf1,0x02,0x79,0x1c,0xfa,0xab,0x3f,0x5b,0x89, -0xdd,0xa2,0x58,0x63,0x03,0xc3,0x7d,0x0c,0xdf,0xa1,0xf1,0x83,0xce,0x52,0xc1,0xb8, -0xbd,0x80,0x9f,0x49,0xbf,0x5f,0x41,0x66,0xc7,0x49,0x7e,0x25,0x54,0x40,0xb8,0x4e, -0x39,0xe2,0x50,0xe2,0x69,0x01,0xe9,0xd5,0x39,0x2c,0x58,0x3e,0x2f,0xfb,0x86,0x38, -0x0c,0x2a,0x56,0x3c,0x31,0x1d,0xd1,0xdc,0xae,0x32,0x87,0xd6,0x5f,0x00,0xbe,0xdf, -0xbf,0xd6,0x14,0x2f,0x87,0x85,0x26,0x72,0x58,0xf2,0xc1,0xe1,0x89,0x69,0x78,0xd6, -0x58,0xb8,0x06,0x1b,0xe4,0x52,0x2f,0xc6,0x99,0x5b,0x50,0x0a,0x94,0x34,0xea,0x75, -0xc6,0x46,0x3c,0x09,0xfa,0x55,0x81,0x9e,0xe5,0xde,0x38,0x34,0xe2,0x6f,0xd9,0x20, -0x8f,0xb2,0x57,0x32,0x6e,0x03,0xa4,0x1a,0x2c,0xaa,0xc6,0x2b,0x31,0x12,0xf5,0x7b, -0x62,0x5f,0x54,0x0a,0x32,0x38,0x46,0xe2,0xd9,0x32,0xfb,0xf5,0x20,0xbf,0x40,0xeb, -0x94,0x61,0x3e,0x6e,0x7a,0x28,0x87,0x4e,0xf4,0x81,0xef,0x4a,0x9e,0x94,0x2e,0x07, -0xc2,0xe1,0xf9,0x31,0x54,0x1f,0xda,0xce,0xec,0x70,0x71,0x88,0xee,0xb3,0x97,0x0b, -0xe2,0x75,0x9b,0x23,0x7e,0x0e,0x8f,0xb4,0x11,0x87,0xc7,0xc2,0x93,0x12,0x8e,0xa2, -0x2a,0x9c,0x39,0xc4,0x27,0x88,0xaf,0x81,0xdb,0x69,0xf4,0xa7,0x9f,0xdf,0xd4,0xf3, -0x0c,0xa7,0x61,0x6c,0x58,0x58,0x91,0x49,0x6d,0xc9,0x23,0x87,0xc4,0xf9,0x14,0xfc, -0xec,0xd8,0x05,0x55,0x40,0x3a,0x7d,0x0d,0x52,0x13,0x23,0xff,0x97,0x49,0xbd,0x8c, -0x1d,0x19,0x39,0x06,0x7a,0x8c,0x94,0x57,0xf2,0x78,0x95,0x1e,0xad,0xf1,0x1e,0x3d, -0x73,0x68,0xfd,0x35,0x2b,0xc0,0xcf,0x4f,0xe7,0x30,0x08,0x3f,0x1c,0x8d,0xef,0xe5, -0xba,0x56,0x77,0xb8,0x39,0x2c,0x7c,0x65,0x38,0x6c,0x27,0x3f,0xbc,0x30,0x6d,0xae, -0xcb,0xa8,0xc0,0xf3,0xac,0xd1,0x28,0xa8,0x05,0x5a,0x3c,0x4f,0x05,0x5e,0x42,0x23, -0x52,0x19,0x47,0x7f,0xb8,0x2e,0xe6,0xc4,0xa6,0xc7,0xb8,0x14,0x50,0xa3,0x2a,0x86, -0x37,0xca,0x46,0x9c,0x6a,0x6e,0xbf,0xa2,0x7c,0x12,0x9e,0xf0,0xfd,0x08,0x6d,0xc6, -0xa3,0x21,0xcb,0x20,0x8a,0x55,0x8d,0xcf,0x83,0x44,0xa9,0x2a,0x8d,0xaa,0xf9,0xfc, -0x8b,0x70,0xc8,0x3e,0x45,0xf3,0x67,0x48,0x2e,0xab,0x9c,0xcf,0xe7,0xa6,0x99,0xc5, -0x84,0xe6,0x86,0x3b,0x39,0xd4,0x3e,0x2d,0x38,0x6c,0x4f,0x0e,0xbf,0x8f,0xdc,0xd0, -0xc6,0x20,0xdb,0xb3,0x96,0x0d,0xd8,0x1a,0x42,0xda,0x33,0x8c,0xf3,0x96,0x9e,0xfb, -0xcc,0x8b,0x54,0x7a,0x4e,0x97,0x98,0x6b,0x11,0xa7,0xa1,0x35,0x3b,0x9f,0x1c,0x12, -0x16,0xc1,0x56,0xa2,0x64,0x99,0xdc,0x10,0xb4,0x23,0xc3,0xc7,0xc1,0xa3,0x31,0xdc, -0x19,0xd7,0x39,0x49,0x24,0xab,0x50,0x07,0x35,0xf6,0xf8,0x79,0xbc,0xf9,0xa1,0xf9, -0x73,0x34,0xd7,0xb8,0x75,0x3f,0x0c,0x84,0xc3,0x8f,0x2f,0x4d,0xea,0xad,0xf4,0x82, -0xc3,0xd6,0xe2,0x70,0xdb,0x13,0x87,0xd7,0x66,0xcb,0x0a,0xf4,0x3a,0xab,0x17,0x92, -0x36,0x46,0xd8,0x4e,0x49,0xfc,0xae,0x24,0x97,0x40,0xc4,0xa7,0x12,0xc6,0x98,0xc3, -0x18,0x11,0xa1,0xca,0xce,0x65,0xc3,0xa1,0x08,0x45,0x5e,0x39,0x84,0x54,0xa9,0x80, -0x2c,0x6b,0x31,0x51,0xc8,0xda,0x70,0xd8,0xaf,0x00,0xe5,0x0e,0x1e,0x11,0xf5,0x4e, -0x56,0x97,0x34,0x7e,0x61,0x0c,0x36,0x3d,0xf9,0x21,0x63,0x0f,0xfe,0xba,0xc1,0x88, -0x3f,0x08,0x3f,0x7c,0x70,0x3a,0x25,0x25,0xf2,0x5d,0xab,0x98,0xc3,0x35,0x4e,0x0e, -0xd5,0x7d,0xcf,0x61,0xa1,0xc9,0xed,0xa5,0xde,0xfc,0xf0,0x72,0x67,0x5a,0x22,0x67, -0x0c,0xa5,0x4d,0x86,0xed,0x85,0x98,0x34,0xdc,0xd2,0xcf,0xda,0x32,0x48,0xdb,0x24, -0x3b,0x63,0x59,0x1d,0x50,0xa5,0x64,0x98,0x48,0x01,0xad,0x2a,0xcc,0xb7,0x6a,0xf4, -0x43,0x1b,0x7f,0xe6,0xdb,0x19,0x67,0x96,0x63,0x00,0xcf,0xa5,0x5a,0x8f,0x55,0x29, -0xd9,0x8e,0xd5,0xb8,0xcd,0x63,0xfd,0xd0,0xda,0x43,0xa2,0x7f,0x3b,0xa6,0x68,0xa3, -0xf6,0x76,0x9a,0xbb,0x43,0x89,0x7c,0x2a,0x9f,0xa0,0x7e,0xc8,0xcb,0x61,0x7b,0xfb, -0xe1,0xd5,0x09,0x5e,0x3f,0x7c,0xc8,0x75,0x76,0x79,0x51,0x7d,0x38,0xbc,0x36,0x8b, -0xb9,0x2a,0x18,0xd4,0x19,0xf1,0x92,0x51,0xff,0xb3,0xb6,0x1d,0xae,0xb3,0x5e,0x68, -0x76,0xb6,0xb3,0x56,0x0d,0xd0,0x3e,0x69,0x44,0x9e,0x84,0x4f,0xd9,0x74,0xe6,0x03, -0x42,0xfc,0x70,0x68,0x25,0xc6,0xec,0xc7,0x16,0x12,0x65,0x48,0x3d,0xb8,0x6e,0xa5, -0xd3,0x46,0xa1,0x29,0xa6,0xa6,0x71,0x6c,0x9a,0x93,0xc3,0x54,0xbe,0x04,0xe8,0x5b, -0x97,0x59,0xc4,0x51,0x00,0xfb,0x5a,0xe3,0xd2,0xcb,0x9d,0x7b,0xb9,0x49,0x09,0x51, -0xa8,0xfb,0x61,0x66,0xe9,0x2b,0xc2,0xe1,0xff,0x3c,0x5d,0x9d,0xc3,0x42,0x93,0xfc, -0x10,0x7e,0xbb,0x5e,0xe2,0x52,0xec,0x86,0x05,0xe3,0x3c,0x83,0x3d,0xdb,0xb4,0x35, -0x12,0x9e,0xa5,0xe4,0xfc,0x04,0x8e,0xc7,0x28,0xb3,0xb5,0x40,0x5a,0xcf,0x6c,0x0b, -0x45,0x35,0xfb,0x61,0x1d,0x8a,0xaa,0x98,0x7f,0x25,0xec,0x85,0x97,0x43,0xe2,0x87, -0x24,0x82,0xa0,0xd1,0xbc,0x4c,0xda,0x9c,0x09,0x87,0xb5,0xb4,0x97,0x9e,0x5c,0x4c, -0x4b,0x88,0x43,0x1c,0x97,0x6e,0x7b,0x8a,0x4b,0xbb,0x56,0xfd,0xbf,0x6e,0xb3,0xf5, -0x5e,0x55,0x0e,0x0b,0x74,0x5f,0x90,0xbf,0xf9,0xa3,0xa0,0x5f,0xdb,0xdd,0x0f,0xb1, -0xab,0x79,0xe1,0xf0,0x7d,0xad,0x6e,0xb8,0x0e,0xbc,0x8f,0x9c,0x39,0x46,0x5b,0xa1, -0xa2,0xd2,0x68,0xd4,0x54,0x2f,0x93,0xa9,0x5b,0xb0,0x33,0xd7,0x4a,0x1a,0x69,0x3d, -0x91,0xab,0xd0,0xd9,0x0a,0x1c,0x5a,0xa2,0x5b,0xeb,0x31,0x93,0xf7,0x46,0xae,0xa7, -0xf9,0xea,0x87,0x61,0x5c,0x3f,0xa4,0x7d,0xaa,0xa0,0x5f,0x15,0xb7,0x2d,0x17,0xf4, -0x31,0x3b,0xe8,0xf9,0x6e,0xc7,0x78,0xbf,0x2d,0xab,0x2e,0x4c,0x67,0xb5,0xb8,0x76, -0x32,0x4f,0x39,0xf4,0xe0,0x87,0xed,0x5d,0x3f,0x74,0xe2,0xb0,0x60,0xdb,0x50,0x69, -0x8e,0x1f,0xe2,0xdf,0x58,0xde,0xb8,0xf4,0x76,0x0c,0xd7,0x0d,0x8d,0xd6,0x4d,0x19, -0xb4,0x62,0xd0,0x36,0xff,0x12,0xad,0xf1,0x39,0xd6,0xc5,0xc8,0x59,0xea,0xe0,0x2b, -0x7c,0xa5,0xe9,0x1c,0x7a,0x2c,0x5e,0xe2,0x52,0xd6,0xe2,0xca,0xfa,0x38,0x69,0x0b, -0x17,0xee,0xc9,0x51,0xe6,0x24,0xbf,0xf3,0x21,0xce,0x8f,0xcd,0x49,0xc8,0x0d,0x53, -0x12,0xae,0x1d,0xee,0x69,0x6e,0xc8,0xcf,0x61,0x49,0xd9,0x6f,0x1c,0x5a,0xbd,0x30, -0xab,0x73,0xd1,0x68,0x3f,0x54,0x65,0x56,0xe7,0xe0,0xe5,0x10,0xb9,0x21,0x1b,0x73, -0x09,0xfb,0xcc,0x20,0x49,0x74,0x0c,0x8b,0x51,0xfb,0x2b,0x99,0xfa,0xba,0x2d,0xf1, -0xa9,0x29,0xaa,0xe3,0xa1,0xb1,0xe5,0x39,0x84,0xad,0x35,0x32,0xaf,0x1f,0xf6,0x62, -0x0e,0xe9,0xc8,0x1f,0x93,0x27,0x1a,0xf1,0x07,0xfe,0x0c,0xd3,0xd2,0x67,0x3d,0x7c, -0xdf,0x96,0x59,0x4f,0xf6,0x26,0xf2,0x59,0x9d,0xc3,0xef,0x48,0xac,0x95,0xc6,0x4b, -0xfd,0x30,0xc2,0x39,0x52,0xb6,0x15,0xf5,0x9e,0xa5,0x9d,0xc6,0xd9,0x0b,0xeb,0xe7, -0x87,0xc4,0xf7,0xac,0x7b,0xf3,0x2f,0xdd,0x0e,0xd7,0x2f,0x1d,0x71,0x43,0x58,0xd7, -0xb3,0x78,0x9b,0xd9,0x03,0x2d,0x67,0xa4,0x63,0x3b,0xa3,0xe7,0x52,0x56,0xf8,0x5a, -0xb4,0x5a,0xc3,0x0f,0xcb,0x1a,0x37,0xef,0x72,0xc4,0x91,0x5a,0xfd,0x50,0x2a,0xd1, -0x7e,0x49,0xf6,0x39,0x19,0x7d,0x22,0x60,0xdc,0xcf,0x9c,0xec,0xcf,0x0f,0xd7,0x32, -0x05,0x99,0xf9,0x61,0x42,0xf7,0x43,0x2f,0x71,0x69,0x41,0x4e,0xe4,0x7b,0xfc,0xbc, -0x70,0x4b,0xc8,0xd9,0x0f,0x9d,0x48,0xec,0x0c,0xdc,0x0f,0x6f,0x52,0x3f,0x84,0xf4, -0x59,0x2f,0xf3,0xd7,0x0f,0x51,0xbf,0xe1,0x3a,0xec,0x83,0x07,0xa3,0xd1,0x60,0xed, -0xcf,0x5c,0x3f,0x82,0x6d,0x8f,0x41,0x94,0xe8,0xe6,0x09,0xae,0x39,0x62,0x88,0xc3, -0x72,0x0b,0x70,0xc8,0x37,0xdf,0xa2,0x37,0x4c,0xfc,0x90,0x7d,0x7a,0x60,0x94,0x9c, -0xc2,0xc6,0xab,0xa6,0x7d,0xc5,0xa5,0x1f,0x5f,0x42,0xe7,0x5a,0xda,0x14,0x97,0xee, -0x78,0xac,0x1f,0xb6,0x3b,0x87,0x05,0x1b,0x7d,0x05,0x8b,0x17,0xa2,0x77,0xf9,0xaf, -0x75,0xe9,0xb7,0x70,0xf2,0x3f,0xeb,0x58,0x8d,0xb2,0xb2,0xcd,0xe5,0x87,0xdb,0xb9, -0x32,0xed,0x4f,0xb0,0xf5,0xb3,0x55,0x39,0x13,0x83,0x2c,0xd1,0xcd,0xc8,0xea,0xcb, -0x5c,0x19,0x1c,0x5e,0xe5,0xf6,0xc3,0x60,0x8f,0xd0,0x5c,0x0a,0x32,0xef,0xdc,0xce, -0x44,0xbe,0x6c,0xf9,0x4c,0x61,0x9c,0x41,0x3f,0x73,0x5f,0x7e,0xf8,0x91,0xe1,0x06, -0x69,0x19,0x71,0x38,0x69,0x8a,0x4b,0x97,0x32,0x59,0xc7,0xb3,0xc4,0x56,0x94,0x76, -0xe7,0xd0,0xdd,0x0b,0x11,0x1b,0x7c,0xb5,0x1e,0x2f,0xba,0x31,0xe8,0x14,0x95,0xb2, -0x8d,0x5c,0xe2,0xf5,0xc3,0x87,0x7f,0x52,0xb6,0xcd,0xb1,0xa8,0xd6,0x27,0x33,0xa7, -0x6d,0x7b,0xb9,0x81,0xb3,0x03,0xd3,0x27,0xa6,0x9f,0xab,0xb0,0x9d,0x70,0xd8,0x57, -0xba,0xed,0xc4,0xf4,0x81,0xb3,0xfc,0xb3,0x34,0xf9,0xfc,0x10,0xc5,0x8d,0x07,0xce, -0x7e,0x74,0xfa,0x81,0xa5,0xa0,0x5b,0x6e,0x4d,0xfc,0x60,0xec,0xea,0xc4,0xf9,0x89, -0xab,0xda,0x5f,0x74,0x09,0x97,0x1f,0x4c,0xbc,0xa9,0x5f,0x46,0xb7,0xbc,0xa9,0x5d, -0xfb,0x01,0xbe,0x4d,0xbf,0x55,0xdb,0xf4,0xff,0xbd,0x89,0x1e,0x83,0x1e,0x3b,0xd6, -0xcf,0xcd,0x8c,0xc1,0xa1,0x62,0x89,0x1e,0x64,0x3a,0xc6,0xdd,0x88,0x4c,0x97,0x3d, -0xfb,0xe1,0x8d,0xc1,0x65,0xc9,0xe0,0x50,0x22,0x1c,0xa2,0xf6,0x52,0x8f,0x1c,0xb6, -0xb5,0x1f,0x7e,0x34,0x41,0xbc,0xcf,0x4a,0x9e,0xd5,0xa3,0xea,0xc0,0xe1,0x90,0x99, -0x3a,0x73,0x44,0x4a,0x7a,0xe1,0xd1,0xb9,0xc8,0x57,0x3f,0x44,0xf3,0xfb,0x55,0x13, -0x67,0x73,0xd2,0xb2,0x94,0x06,0x65,0xd2,0xf8,0x9e,0x61,0x09,0x7e,0x7e,0x33,0x9f, -0x46,0x39,0x39,0x4c,0xb4,0x48,0xeb,0x03,0xf3,0x43,0xd3,0xe8,0x02,0xd9,0xda,0xf7, -0x9a,0xf5,0xe8,0x87,0xc7,0xc2,0x11,0x7d,0xe4,0xaa,0xfe,0x8d,0x99,0x38,0xdc,0xd3, -0x7b,0x0f,0x97,0xf4,0xb8,0xd4,0x9d,0xc4,0xf5,0x36,0xf7,0x43,0xd5,0xb1,0x75,0xc6, -0x4a,0xa4,0xca,0xd9,0x0a,0xe8,0x45,0xb8,0x7e,0xc8,0x3e,0x61,0xf3,0xa8,0x61,0x83, -0x45,0xc5,0x4b,0x3f,0xfe,0xb1,0xf0,0x5e,0xce,0xec,0x81,0x69,0x0b,0x89,0x8c,0x46, -0x46,0xe4,0x8b,0x63,0x41,0xbf,0x33,0x1e,0x3d,0xd9,0x9b,0x6d,0x2b,0x0e,0x23,0x79, -0x76,0xb4,0xd6,0x96,0x2d,0x32,0xfb,0x0a,0xed,0xb3,0x1e,0xfd,0xf0,0xe4,0x22,0xa1, -0x30,0x2b,0x2f,0x83,0xb8,0x14,0xcf,0x7a,0x5a,0x32,0x38,0x74,0x2f,0xed,0x5d,0x3f, -0xfc,0xe8,0x34,0xf4,0xc3,0x6a,0xef,0xb2,0x5e,0x71,0x29,0x8b,0x41,0x01,0x83,0xa6, -0x11,0x68,0x65,0x0f,0xfd,0xf8,0x9f,0xc5,0x70,0x76,0xaf,0x2c,0xfd,0x66,0x71,0xb4, -0x63,0x2f,0x84,0xc4,0xb4,0x94,0xca,0xf3,0x66,0x94,0x09,0x52,0x98,0xc3,0xb2,0xe2, -0x96,0x8b,0xa6,0x55,0x38,0x4c,0x00,0x0e,0x61,0xad,0xd0,0x5a,0xbc,0xf9,0xe1,0x05, -0x3a,0x5f,0x9b,0xfc,0x6e,0x42,0x3f,0xdc,0xc9,0x79,0xe0,0xb0,0xcd,0xfd,0xb0,0xba, -0x0f,0x32,0xd7,0xaf,0x83,0x1f,0x0e,0x59,0x3d,0x90,0x5d,0x26,0x7d,0x52,0x38,0x32, -0xe5,0x8d,0x4b,0x91,0xde,0x88,0x4f,0x4a,0x94,0x44,0x69,0x4e,0x23,0x71,0xce,0x95, -0xc4,0x48,0x7e,0x34,0x1e,0xf4,0xbb,0x73,0x53,0xbb,0xf9,0xa1,0x89,0x43,0xa7,0x51, -0xef,0xc6,0x75,0x2f,0x1c,0x3e,0x3b,0x42,0xe2,0x21,0xf2,0x7d,0xd9,0xfd,0x90,0xb4, -0x97,0xba,0x45,0xa6,0xed,0xee,0x87,0xaa,0xab,0x17,0xa2,0x52,0xaa,0x93,0x1f,0xda, -0x0b,0xf4,0x42,0x3c,0x62,0x9b,0xbf,0x7e,0x88,0x15,0x1e,0x49,0x4b,0xd0,0x13,0xd3, -0x5a,0xd1,0xa2,0xd3,0x0a,0x34,0xa2,0x32,0x27,0xed,0xe5,0x1a,0x9d,0x81,0xaf,0xdd, -0xfc,0x30,0x62,0xf7,0x43,0x4b,0x51,0x3d,0xfa,0x21,0xca,0x51,0xc6,0xe6,0xf8,0x5b, -0xeb,0x87,0x11,0x54,0x3f,0x34,0xfc,0xb0,0x04,0xe6,0xb1,0x15,0x4c,0xfb,0xfd,0xe3, -0x87,0x2a,0x47,0x54,0x5a,0x9f,0xb8,0xf4,0xe6,0x20,0x1b,0xf3,0xa2,0xca,0x6c,0x4e, -0x04,0x99,0x49,0x63,0xf4,0x04,0x7a,0xe6,0x10,0xcd,0x22,0xc9,0xb2,0xdf,0x58,0x19, -0x79,0xa2,0xe6,0x8c,0xd2,0x5c,0x45,0x0e,0xd3,0x52,0x56,0xf6,0x93,0x13,0xae,0x16, -0x11,0x3f,0xac,0xbe,0xb5,0x0e,0x87,0x0e,0x71,0xa9,0xd9,0x0b,0x8d,0x1e,0x7e,0x7e, -0x0e,0xd7,0x32,0x6c,0x9e,0x28,0xeb,0xb7,0xd0,0x7b,0x10,0x8d,0xf6,0xd2,0x6d,0x4b, -0x7b,0x69,0x65,0x0a,0xd1,0xd9,0xd3,0xce,0x1c,0x62,0x3f,0x74,0x2f,0xa5,0x3a,0xc4, -0xa5,0x37,0x06,0xc9,0xa8,0xe3,0x02,0xd8,0xc8,0xa8,0x6b,0x95,0xfc,0xc6,0xfa,0xe0, -0x30,0x14,0x3a,0x70,0x16,0x44,0x3b,0xa0,0xae,0xa8,0x45,0x3e,0xda,0xaf,0xae,0x5e, -0x67,0x94,0x97,0x2d,0x24,0x9e,0x0c,0x7c,0xc4,0x50,0x35,0x3d,0xd9,0x5b,0x90,0x79, -0x7a,0xf8,0x5a,0x9e,0x43,0x9f,0xf5,0xc3,0x8f,0x2f,0x95,0xf5,0x39,0xa0,0x25,0x53, -0x64,0x8a,0xfd,0x90,0xce,0x3f,0x34,0x38,0x24,0x23,0xf5,0x59,0x5f,0x96,0xfd,0xac, -0x2d,0xed,0x0b,0x3f,0x74,0x2b,0x75,0x69,0x2f,0x1d,0x22,0xb3,0x93,0x58,0xdf,0x7d, -0x09,0x90,0xb8,0x6e,0xfc,0xca,0x6a,0x1c,0xfa,0xf0,0xaa,0x6b,0xd3,0x15,0x7a,0x0f, -0x25,0x1c,0x01,0x2d,0xeb,0xf1,0x2a,0x6e,0xa3,0x4b,0xeb,0x51,0x6b,0xb6,0x0e,0x9e, -0x5f,0x59,0x24,0x2e,0xb5,0xfa,0x5f,0xdb,0xf9,0xa1,0xc5,0x1b,0xf9,0x38,0xbc,0x35, -0x51,0x02,0xd1,0x26,0xe5,0xd0,0xd2,0x6f,0xc1,0xfc,0x90,0xdd,0xaf,0x12,0x89,0x88, -0xc3,0xf6,0x5d,0x03,0x03,0xb7,0x97,0x36,0x87,0x43,0xec,0x87,0xa4,0x55,0xc6,0x9a, -0x7f,0x8c,0xd5,0xfd,0xfd,0xf8,0x21,0xd2,0xc3,0x4b,0xaa,0xcd,0x13,0xdd,0x0a,0xdf, -0x98,0xb4,0x20,0xc4,0x38,0xdc,0x4f,0x7e,0x58,0xe6,0xe2,0x70,0x34,0xbe,0x2c,0x91, -0x59,0x54,0xeb,0x0e,0xed,0xa5,0x6c,0x3e,0x3e,0x6e,0xa7,0x51,0x8d,0xd9,0xc7,0xac, -0x3f,0xab,0x60,0x21,0xb3,0x10,0x58,0x86,0xaa,0xe6,0xe8,0xbd,0x26,0x72,0x78,0x77, -0xa8,0xa4,0x90,0xb9,0xf1,0xfa,0xa7,0x4b,0x32,0x31,0x19,0x3c,0x92,0x99,0x72,0x5e, -0xfa,0x2d,0xcc,0x82,0x7d,0x53,0xbc,0xc5,0x5f,0x0e,0x7f,0xef,0xda,0x9f,0x1c,0xf2, -0xf9,0xe1,0x5e,0xae,0x44,0x5b,0xe1,0xa0,0x23,0x2e,0x1b,0xf5,0x43,0xd6,0x6f,0xb1, -0x46,0x39,0x84,0xfe,0xa7,0x82,0x3d,0xbb,0xdc,0xce,0x1c,0x6a,0x7e,0x58,0x31,0xdf, -0xae,0xd9,0xf5,0x83,0xe7,0x30,0x3c,0x52,0x06,0xf5,0x7b,0xcb,0xdc,0x5b,0x30,0x6e, -0xc3,0xaf,0x1f,0x22,0xad,0x65,0x2a,0xe5,0x13,0xce,0x56,0xdc,0x1a,0xb3,0x56,0x02, -0x1f,0x87,0xd1,0xcd,0x76,0xe3,0xb0,0x20,0x9f,0x73,0xe9,0x03,0xea,0x5c,0x28,0x93, -0x3c,0x40,0xfa,0x77,0xec,0xe0,0x87,0x92,0x39,0x3f,0x0d,0x9d,0xe7,0xa8,0xc7,0x4d, -0xe6,0xe8,0x94,0xd5,0x68,0x82,0xcb,0x24,0xde,0x78,0x35,0xb3,0x9d,0xe6,0xf3,0x63, -0x65,0x45,0xa5,0x7d,0x84,0xd0,0x0d,0xcd,0x33,0x77,0xfd,0xd5,0x0f,0xb1,0x8e,0x85, -0xbb,0x56,0x2b,0x67,0xf6,0x76,0x2e,0x69,0xe9,0x66,0x03,0xfa,0xf5,0xf7,0xab,0x1f, -0xba,0x71,0xf8,0x8b,0x97,0xf5,0xef,0x83,0xcd,0xda,0x00,0xbf,0x8c,0x59,0x09,0xf8, -0x61,0x9e,0xf5,0xe3,0xab,0x8a,0xd5,0xfb,0xec,0xfe,0x18,0x4c,0xc6,0xc6,0x66,0xe9, -0xa3,0xd3,0xeb,0x7c,0x1c,0xd6,0xa1,0x0d,0x43,0xf7,0x43,0x3d,0x1e,0x65,0xe3,0xf5, -0xa1,0x3b,0xb2,0x3a,0x87,0x7f,0x3f,0x44,0xe7,0x7b,0x2a,0x0f,0xbf,0x6d,0xf7,0x82, -0x6a,0x1a,0xdf,0xae,0xfb,0x1a,0x7b,0xfd,0xfb,0xd2,0x0f,0xcb,0x2e,0x1c,0xde,0x1d, -0xca,0x1a,0xd4,0xd0,0xb9,0xda,0xa6,0x1e,0x44,0x36,0xd2,0x9b,0xcd,0xb8,0x30,0xfc, -0xd0,0xe8,0xd5,0x2a,0x80,0x36,0x56,0xc2,0x60,0xc1,0xf0,0xc3,0x76,0xe6,0xb0,0xb9, -0x7e,0x68,0xd4,0x11,0x2a,0xcf,0xdc,0xad,0xa1,0x9d,0x86,0xe8,0xc6,0x60,0x5a,0x32, -0xaf,0xcd,0xe0,0x48,0x9f,0xe9,0xdd,0x46,0xf2,0xc1,0xae,0xe3,0x67,0x17,0x5f,0xbf, -0x45,0xbb,0x71,0x58,0xdd,0x0f,0xf5,0x31,0xdd,0xc6,0xef,0x3a,0xf1,0x42,0xc6,0x14, -0xe3,0x90,0xb4,0xd3,0xa0,0xf5,0x26,0xdf,0x5e,0x9c,0x93,0xf0,0x4c,0x63,0xdc,0xcb, -0x51,0xa0,0xbd,0x18,0x05,0xd3,0x5f,0x35,0xa0,0x8c,0xfe,0xcd,0xd1,0x47,0xa7,0x4b, -0x4d,0xe3,0x10,0xd7,0x0f,0x4b,0xf6,0xb9,0xf0,0x81,0xfa,0x21,0x52,0x7c,0xac,0x40, -0xda,0x61,0x61,0xcf,0x88,0xac,0x82,0xd7,0x53,0x69,0x24,0x8c,0x57,0x8b,0xa9,0xf5, -0x35,0xdd,0xd4,0x9e,0x1c,0x5a,0x37,0x6f,0x7e,0x88,0xdb,0xcd,0x90,0xa7,0xb1,0x56, -0x80,0x6a,0x1c,0x22,0x3f,0x7c,0xef,0xb4,0x9e,0x29,0x8e,0x66,0x2f,0x21,0x59,0x4f, -0xd6,0x49,0x1d,0x13,0xd4,0x0f,0xdb,0xd7,0x0f,0x1f,0x34,0xdb,0x0f,0xe9,0x0a,0x2d, -0xd6,0x99,0xbb,0xac,0xcd,0x26,0x08,0x26,0xde,0x3b,0xcd,0xbe,0x77,0xab,0xdf,0x96, -0x40,0xae,0x79,0x7a,0x8b,0x12,0xec,0x8a,0x9a,0x76,0xf1,0xd6,0x0f,0x97,0x65,0x34, -0xaf,0x71,0xa0,0xa6,0x72,0x61,0xfa,0x8f,0x67,0xaf,0xcd,0x9e,0x98,0xbe,0x5f,0x43, -0xbd,0x17,0x71,0x58,0x89,0x3e,0x3e,0x3f,0x3c,0x31,0xcd,0x62,0x8f,0x12,0xc8,0x57, -0x59,0x99,0xc3,0xbd,0xdc,0x73,0xd3,0x21,0x96,0xb1,0x11,0x52,0x08,0x47,0x42,0xe2, -0x7d,0x5b,0x73,0x38,0x70,0xb6,0xb9,0x7e,0xc8,0x97,0x79,0x29,0x08,0x6f,0x7a,0x6e, -0x9a,0x2f,0xae,0x82,0xaf,0x1b,0x7c,0xee,0x64,0x26,0xde,0xf1,0x34,0x65,0x25,0x56, -0x8c,0x15,0xa3,0xda,0x16,0xdb,0x44,0x7b,0x54,0x62,0x9b,0x64,0x8f,0x2e,0x19,0xff, -0xdf,0x8c,0x19,0x1b,0xbe,0x45,0xbf,0xb6,0x19,0x2b,0xd2,0x47,0x6b,0xa5,0xac,0x1c, -0x38,0xeb,0xf7,0x78,0x9d,0xfd,0xb0,0x4c,0x3f,0x2b,0x37,0x3f,0x7c,0x76,0x24,0x4b, -0x29,0x5c,0x67,0x9f,0x32,0xed,0x1b,0xc4,0x1c,0x2e,0x83,0xfa,0x61,0x64,0x15,0xaf, -0x31,0x06,0x33,0x72,0xc0,0xac,0x96,0x2c,0x1b,0xd8,0x7a,0xdb,0xfb,0x61,0xb3,0x39, -0x04,0x3e,0x58,0x31,0x8b,0x45,0x50,0x31,0xe2,0x4f,0x2f,0x79,0x27,0xb1,0x7e,0xfd, -0xfa,0xbc,0x7e,0x18,0x64,0x89,0x6e,0x4e,0x4a,0x7e,0x8f,0x37,0x02,0xfc,0xd0,0x4a, -0x21,0xfc,0xc4,0x9c,0x39,0xbc,0x6d,0xcc,0x47,0x03,0x7e,0xa8,0x90,0x98,0x07,0xf6, -0xe4,0xe3,0xcc,0x18,0xb8,0xdf,0x62,0x27,0x87,0x66,0xc1,0x90,0x4c,0x71,0xec,0x3c, -0x61,0x6b,0x54,0x92,0x3a,0x26,0xae,0x67,0xb6,0x73,0xfd,0x10,0xae,0x5e,0xdd,0xb4, -0xfa,0x61,0x43,0xfc,0x10,0xc9,0xbc,0xc6,0x3b,0xcf,0x2b,0x97,0x95,0x5b,0x75,0x9a, -0xaf,0xdf,0xaf,0xf9,0x61,0x74,0xb3,0xd1,0x24,0x4e,0x72,0xad,0xfe,0xeb,0xa4,0x48, -0xde,0x7c,0xb4,0x25,0xb0,0x87,0x9b,0x33,0x87,0x33,0x8b,0xb8,0x7f,0x10,0x9f,0x4d, -0xeb,0x96,0xfc,0xe2,0xe4,0x2c,0xa3,0x33,0x81,0xf5,0xb8,0x14,0x67,0x4a,0x60,0x19, -0xaa,0x48,0x46,0x76,0x32,0xd2,0x83,0x8c,0xc1,0x22,0x44,0xb6,0xb3,0x1f,0x1e,0xe0, -0xe7,0x30,0xf0,0x55,0x8f,0x0d,0x0e,0xad,0xf3,0xba,0xeb,0xc8,0x21,0xca,0x9c,0xe1, -0x95,0x44,0xb5,0x4e,0xfd,0xfa,0x7c,0xfd,0x16,0xc1,0x73,0xd8,0xeb,0x97,0xc3,0x55, -0x48,0xa0,0xf3,0x66,0x70,0x38,0x68,0x7d,0x2c,0xca,0xd3,0xbd,0x2c,0x65,0xe9,0xd9, -0x04,0xfd,0x50,0xa5,0xa3,0x4c,0xf1,0xdc,0x18,0xcc,0xe1,0xa4,0x44,0x56,0xd9,0xee, -0x21,0x71,0x29,0x65,0xd0,0xc8,0xc2,0x67,0x59,0x97,0xb2,0xbd,0xfb,0xf1,0xf9,0xfd, -0xf0,0xa7,0xfb,0xc0,0x0f,0x91,0xf6,0x72,0x5e,0x49,0xcc,0xca,0x37,0x6c,0x67,0x56, -0xed,0xea,0xe7,0xae,0x1f,0x06,0x57,0x50,0x5c,0xea,0x9b,0xc3,0x7c,0xe5,0xe7,0x85, -0x34,0xda,0xfd,0xf0,0xfc,0x18,0x9e,0xcf,0xc2,0xfc,0xd0,0xfa,0x19,0xb3,0x1a,0x22, -0xc9,0xd8,0xc6,0x66,0xa1,0x19,0x7e,0x08,0x1f,0x43,0xf3,0x3e,0x93,0x99,0x39,0xeb, -0x35,0x65,0x30,0x6e,0x05,0xf1,0xfb,0xe1,0x4f,0xeb,0xe5,0x87,0x0d,0xe6,0xf0,0x72, -0x27,0x6f,0x4f,0x18,0x7b,0xfd,0xc9,0x3a,0x7c,0xc3,0x4f,0x36,0x29,0x2e,0xf5,0xcf, -0xa1,0xd3,0xd1,0x96,0x2c,0x24,0x22,0x0e,0x5f,0x35,0x71,0xd8,0xdf,0x1b,0xc9,0xeb, -0x1c,0x42,0x3f,0x24,0xfc,0x19,0x54,0x59,0xfd,0x30,0x91,0x7f,0x95,0xfe,0xf2,0xf5, -0x84,0xbf,0xa3,0x7f,0x5f,0xa6,0x7e,0x65,0x99,0xf4,0x35,0xad,0x83,0xf6,0x1b,0xff, -0x19,0xfd,0x9b,0xaf,0x6a,0x7e,0xa8,0x9a,0x39,0x6c,0x9a,0x1f,0x46,0x37,0x83,0xed, -0xcb,0xeb,0xef,0x4d,0x4b,0x5e,0x49,0x8c,0x04,0x3e,0xa7,0x46,0x6f,0x2f,0xbd,0xd3, -0x68,0x0e,0xf9,0xb2,0xe8,0x3b,0xc9,0x99,0x43,0x7b,0xb1,0xfa,0xe1,0x4c,0x06,0x67, -0x20,0x49,0x03,0x0e,0x2d,0xf5,0x0f,0x7a,0x3b,0x19,0xe9,0xfd,0x11,0x18,0x6b,0xdf, -0x1b,0x9e,0x34,0x7e,0x37,0x55,0xab,0x8f,0x9a,0xfb,0xbc,0x7c,0x64,0x6c,0x6c,0x1d, -0x0d,0x9c,0x55,0x5d,0xfc,0x50,0x35,0xe2,0xf9,0xf7,0xf7,0x89,0x1f,0x22,0xa1,0xd1, -0x55,0x5e,0x49,0xf4,0xb6,0x36,0xb8,0xbb,0x9a,0xe3,0x87,0x73,0xf2,0xbb,0xbe,0x39, -0x74,0xfb,0xd5,0x28,0xe9,0x7f,0x55,0xf9,0x55,0x10,0xc5,0x5f,0x9b,0x9d,0x34,0x72, -0x00,0x2d,0x83,0x79,0xae,0xd6,0x4f,0x97,0x71,0x98,0xb5,0xcd,0x02,0xd5,0x38,0x94, -0x88,0x1f,0x9a,0x0b,0x5b,0xcf,0xd1,0xf0,0x43,0x9f,0x19,0xfd,0x5b,0x41,0x95,0xfc, -0x50,0x05,0x5b,0xb3,0xfd,0xb0,0x1e,0x63,0x5b,0x5e,0x1c,0x53,0x3d,0x93,0x78,0x24, -0xd0,0xf9,0xfa,0xa8,0x7e,0xf8,0xe5,0x9d,0xc6,0x92,0x18,0xdb,0xcc,0xca,0x3c,0xab, -0x59,0x38,0x89,0xd7,0x0f,0x55,0xe0,0x87,0xb7,0x26,0xd0,0x88,0x6d,0xcc,0x61,0x1a, -0x72,0x68,0x62,0x0a,0xb5,0xb6,0x50,0x0e,0x65,0xfb,0x77,0x6d,0xcd,0x50,0x45,0xd7, -0xd8,0x80,0xb3,0x74,0xe4,0x76,0xf7,0xc3,0x6a,0xf5,0x43,0x16,0x99,0xee,0x2f,0x3f, -0x44,0x7a,0x70,0xba,0xa4,0x78,0x25,0x31,0xc8,0xcf,0xa0,0x19,0xfd,0x16,0xd1,0x9a, -0x38,0xe4,0x7b,0x0d,0xc6,0xe1,0xb9,0xf8,0x5e,0x8e,0x71,0x08,0xfd,0xd0,0xea,0x6d, -0xec,0x3c,0x9b,0x94,0xde,0xb0,0xb5,0x89,0x45,0x4c,0x99,0xc4,0x1d,0x56,0x87,0xad, -0x71,0x85,0x9b,0x56,0x90,0x5b,0x7b,0xa9,0x4a,0x3f,0xb7,0xc6,0xfb,0x61,0x99,0x6e, -0xf5,0x19,0xeb,0x79,0x62,0xba,0xec,0x89,0x44,0x74,0x6f,0xff,0xe3,0x51,0xac,0x62, -0x71,0x29,0xfa,0x5b,0x69,0x83,0xff,0x37,0x13,0x55,0x8d,0xb6,0x4a,0xff,0x89,0x15, -0x6b,0xe1,0x30,0xc6,0xf5,0xab,0x51,0x52,0x30,0x49,0x3d,0xa1,0x99,0xc5,0x48,0x3e, -0x42,0x39,0x9c,0xb3,0xf5,0xe2,0x3b,0x91,0xf8,0xc0,0x61,0x16,0xb6,0x53,0xbb,0x9a, -0xea,0xb0,0xf7,0x9a,0x49,0xbc,0x95,0x54,0x99,0x43,0x15,0xec,0xd1,0x27,0xb7,0xd5, -0x24,0x3f,0x44,0xdf,0x6d,0xbd,0x56,0x98,0xfc,0xd8,0xe3,0x08,0x1b,0x74,0xef,0x37, -0x03,0xea,0xd7,0x77,0xf2,0x43,0x2b,0x81,0xd5,0xa8,0xf2,0xe3,0xa5,0xba,0x1f,0xd6, -0xad,0x7e,0x48,0x0a,0xce,0xca,0x7c,0x6d,0x16,0x8d,0x0f,0x65,0x1c,0x92,0xf6,0x52, -0xd5,0xda,0x4a,0x43,0x29,0x54,0x15,0xe7,0xb5,0xfd,0xec,0x19,0x1b,0x4d,0xbe,0x48, -0xe7,0xa9,0xee,0x37,0x3f,0xc4,0xe4,0xa9,0xa6,0x4b,0x65,0xe5,0x5a,0x43,0x39,0x2c, -0x83,0x2d,0xe8,0xf6,0x52,0xa8,0xdf,0xf7,0x3c,0xc2,0xa6,0x20,0x7f,0x7e,0x2c,0x88, -0x57,0xd6,0x39,0x2c,0x22,0x36,0x98,0x2b,0xb2,0x3d,0xb9,0xd5,0x8d,0x40,0xab,0x6f, -0x56,0xa7,0xb5,0x36,0x3f,0x44,0x47,0xcb,0x53,0xd0,0x2c,0xea,0x5b,0x13,0x3b,0x1a, -0x85,0x7b,0x3f,0x01,0x1c,0x56,0xf1,0x43,0x55,0xaf,0xf9,0x54,0xfa,0xb5,0x0d,0x36, -0x43,0x55,0x6b,0xaa,0xba,0x1f,0xaa,0xa0,0x9d,0xa6,0x91,0x1c,0x96,0x4d,0x5b,0xfd, -0xfc,0x10,0xc9,0x75,0x84,0x8d,0x6c,0x3d,0xb6,0xb4,0xe4,0x96,0xf9,0x81,0x47,0xc4, -0x0f,0x2b,0x79,0x9f,0x9b,0x0f,0x56,0x8b,0x56,0x2b,0x91,0x59,0x9b,0x1f,0xf2,0x3a, -0xf0,0xb9,0xf8,0x68,0x7c,0x29,0xb3,0x9d,0xdb,0xc9,0x75,0xad,0x46,0xf2,0xa9,0x3c, -0xe9,0xb5,0x20,0x1c,0xda,0x57,0x44,0x47,0xed,0x9d,0x59,0xd9,0x5e,0x33,0xc4,0xaa, -0xce,0x21,0x6d,0xb5,0xd9,0x17,0x1c,0xc2,0x28,0xd4,0x3a,0x57,0x16,0x7d,0x4a,0x8d, -0xf0,0xc3,0xb2,0x6d,0x23,0x67,0x4f,0x7d,0x57,0x3e,0x47,0x23,0x6c,0x54,0xf8,0xad, -0x42,0xfa,0xc0,0x08,0x74,0x32,0x26,0x12,0xe5,0xaa,0xf0,0x7b,0x36,0x33,0x21,0x0e, -0x63,0x45,0xe4,0x7b,0x66,0xef,0xc3,0x7c,0x91,0x5b,0x19,0x51,0xe6,0x4b,0xec,0x51, -0xe4,0xbe,0xec,0x39,0x9c,0xa2,0xdb,0x40,0xfc,0x90,0xb3,0x7e,0xf8,0xe6,0xd8,0xc3, -0x3f,0x59,0xcb,0x6c,0x67,0xf6,0x34,0x0e,0x71,0x3b,0x0d,0xec,0x3d,0x54,0x6d,0x14, -0xe2,0xf2,0x8b,0x97,0x2b,0xbd,0x72,0xd0,0x99,0x53,0x5b,0x51,0x66,0x3f,0x54,0x4d, -0x44,0xaa,0x32,0x6c,0xa7,0x69,0x94,0x1f,0xda,0x49,0xac,0x37,0x87,0xef,0x74,0x26, -0xf2,0x24,0x77,0x18,0x9c,0x61,0xba,0x2e,0x93,0x39,0xe0,0xe6,0xb9,0x6f,0xfe,0x32, -0x1b,0x5b,0x45,0x38,0x34,0x93,0x67,0xa6,0xcf,0x28,0x77,0x50,0x8f,0x03,0xbe,0x1d, -0xed,0x71,0x6f,0x07,0xde,0x7f,0x69,0xec,0xd1,0x33,0xe9,0xd7,0xb5,0x2d,0x8a,0x9e, -0xf5,0x0e,0x7e,0x2e,0x74,0x7f,0x14,0x4f,0x7e,0xa9,0x3f,0x53,0xb2,0xe8,0x7f,0x56, -0x31,0x7f,0x5c,0x7a,0x72,0x71,0x66,0x71,0xc9,0xe0,0xd0,0xee,0x87,0x4e,0x1c,0x96, -0x2b,0xd4,0x0c,0xb1,0x78,0x39,0xdc,0x2f,0xf5,0x43,0xd5,0x46,0x23,0x99,0x6d,0x59, -0xaa,0x9b,0x1f,0x3a,0x7b,0x60,0xc9,0xf4,0xbd,0x46,0x37,0x83,0xee,0x43,0xb7,0xea, -0xdb,0x71,0xbc,0xd2,0x02,0xac,0x19,0xc3,0x4c,0x44,0x2a,0xfc,0x6c,0xd0,0x4a,0x70, -0x1a,0x89,0x33,0x35,0xce,0x12,0xa6,0x7e,0xa8,0x53,0x82,0xc8,0x31,0x68,0xbb,0x43, -0xae,0x1b,0x54,0x12,0xca,0x14,0xbc,0xb7,0xff,0x66,0x95,0xe9,0x65,0xf2,0xd7,0xb9, -0xa0,0x51,0x6d,0xfe,0x57,0xb6,0xe2,0x6d,0x2f,0x45,0x23,0x1e,0x4e,0x2e,0xae,0x65, -0x76,0x8c,0x56,0x1a,0xb3,0x1f,0x3a,0xb5,0x95,0xa2,0xd1,0x4a,0xd5,0x5e,0x99,0xdf, -0x0f,0xbf,0xdd,0xf0,0xd5,0x82,0x82,0x12,0xe3,0x10,0xb6,0xcb,0x80,0xcb,0xd4,0x27, -0xea,0xc1,0x21,0x39,0xab,0xec,0x34,0x42,0x12,0xbf,0xbc,0x53,0xff,0xb5,0x27,0xee, -0x0e,0xa5,0x25,0xbe,0x99,0x98,0xa4,0xd4,0x3a,0x4b,0x98,0xf9,0x21,0xf1,0xac,0xd8, -0x26,0xf3,0x30,0x42,0x23,0x8a,0x24,0x9f,0x1d,0xb9,0x31,0x78,0x77,0xe8,0xe6,0xd0, -0x5d,0xad,0xdc,0x18,0x3c,0x17,0x7f,0xd5,0xfb,0x36,0x88,0xf6,0xb5,0xd5,0x6a,0x35, -0x0e,0x39,0xfd,0x70,0x2d,0x83,0xfc,0x10,0x71,0xd8,0xa5,0x51,0x88,0xfd,0x70,0x4e, -0x66,0x7e,0x68,0xa5,0xb0,0x72,0xcd,0x10,0x2b,0xb8,0x8c,0x8d,0xad,0xab,0x81,0xe9, -0x12,0xc8,0x6a,0x4f,0x09,0x04,0xd1,0x18,0x1e,0x53,0x5b,0x1f,0x3f,0x44,0x67,0xa1, -0x13,0x79,0xe6,0x12,0xdb,0x6c,0xc4,0x1a,0x30,0x2f,0x8e,0x65,0x3d,0x71,0x88,0xda, -0xae,0x6a,0x99,0x25,0x4c,0x39,0x04,0x51,0x25,0x2a,0x24,0xd2,0xd4,0xa3,0x4d,0xed, -0x3f,0x69,0xdf,0x33,0x77,0x83,0x95,0x37,0x0e,0x99,0x1f,0x9a,0x7b,0xf1,0x09,0x85, -0xf0,0x3b,0xaf,0x5c,0x33,0xc4,0xfa,0x4a,0x70,0xe8,0x50,0x3f,0x54,0xc1,0x65,0xe2, -0x89,0xf5,0x6b,0xa7,0x71,0x27,0xb1,0x31,0x1c,0xa2,0x1c,0x36,0xbc,0x39,0xbf,0xd9, -0xcc,0x72,0xff,0xb3,0x84,0x75,0x0e,0x71,0x5d,0x8f,0x52,0x87,0xeb,0x76,0xa4,0xde, -0x87,0x09,0x4d,0xfb,0x9e,0x21,0x11,0xac,0xfc,0x72,0x88,0xfd,0x30,0x6b,0xf3,0x43, -0x12,0x47,0xbb,0x8f,0x16,0xe4,0xe0,0x50,0xde,0x3f,0x1c,0xb2,0x98,0x14,0x64,0xba, -0x97,0x4b,0xc6,0x0c,0xaf,0xfa,0xf9,0xa1,0x7b,0x69,0x14,0x87,0xa1,0xd0,0x73,0x67, -0xf1,0xdc,0x1b,0xd4,0xe7,0xac,0xaf,0xd5,0x86,0xb7,0xaa,0x3c,0xfa,0x9d,0x25,0xdc, -0xdf,0xab,0xca,0x46,0x46,0x99,0x22,0xc9,0x3b,0x13,0x65,0xd7,0x8d,0x08,0x15,0x71, -0xd8,0x1a,0xab,0xa7,0xec,0xe5,0x78,0x39,0xdc,0x76,0xf0,0x43,0x6b,0x2b,0x0d,0xb9, -0x6f,0xf5,0x9a,0x21,0x16,0xc9,0x50,0xb5,0xff,0xfd,0xd0,0xdc,0x46,0x6a,0xac,0xfa, -0xc2,0x5a,0x2c,0xea,0xec,0x87,0x6e,0x25,0x5a,0x6c,0xdc,0xda,0x84,0xd7,0x66,0x97, -0xab,0xac,0x57,0x4a,0x56,0x2d,0x45,0xdb,0x32,0x5a,0x6b,0x58,0x3b,0xbf,0x26,0x25, -0x7f,0xb3,0x84,0x71,0x5c,0x6a,0xb4,0x75,0x6a,0x7b,0x56,0x4b,0x04,0xad,0x32,0xc5, -0xd6,0xf1,0x43,0x7e,0x0e,0x9d,0xe2,0x52,0xd8,0x7b,0x58,0xa2,0x24,0x16,0x5c,0x6a, -0x86,0x58,0x5f,0xa5,0xb8,0xd4,0x58,0x7b,0x47,0x06,0x59,0xee,0xe9,0x1a,0x84,0xf8, -0x53,0x6b,0xa2,0x1f,0x36,0x90,0x43,0x34,0xd6,0x0d,0xcf,0x08,0x67,0x25,0x6d,0xb9, -0x6c,0x5d,0xc1,0x34,0x92,0xf7,0xd3,0x5e,0x8e,0xfd,0xd0,0xc8,0xbe,0xb6,0x49,0x73, -0xaa,0x6d,0x46,0x8b,0xe6,0x1c,0x6c,0xad,0xe7,0x87,0xce,0x7d,0x93,0x95,0xfd,0xd0, -0xdc,0x6b,0xc1,0x28,0x2c,0x2b,0x4e,0xa3,0x49,0xed,0x72,0xca,0x50,0xb5,0xdf,0x38, -0x3c,0x31,0xcd,0x56,0xdd,0x21,0x5e,0xb8,0x6e,0x78,0x60,0x41,0x61,0x79,0x77,0xeb, -0xd7,0x6f,0xd1,0x6a,0x1c,0xa2,0x75,0x50,0xf0,0x0a,0x0b,0xac,0xa4,0xf4,0x0d,0x95, -0xef,0x48,0x29,0x0b,0xa3,0xe8,0x1c,0xdb,0xce,0x78,0x67,0x05,0xfb,0x21,0x26,0x0f, -0x70,0x08,0x32,0x24,0xe2,0xeb,0xad,0xe4,0x87,0x7c,0xbf,0x9b,0x3b,0xb9,0xaa,0x71, -0xa9,0x41,0x62,0xb4,0x58,0xad,0xcf,0x10,0xaa,0x6b,0xb5,0x1a,0x7d,0xac,0x64,0xdb, -0x98,0xc3,0x6b,0xb3,0x6c,0x1d,0x3a,0x90,0xeb,0x1a,0xac,0x3e,0x50,0x4f,0x3f,0xfc, -0x92,0x8b,0xc3,0x46,0xc6,0xa5,0x58,0x27,0x17,0xf5,0xfc,0x99,0xa0,0x24,0xe8,0x06, -0xe9,0x24,0x4c,0xce,0xc9,0xde,0x7b,0x13,0x8d,0xfa,0x21,0xa1,0xcf,0x20,0x8f,0xee, -0x8d,0xdb,0x93,0x2d,0xe6,0x87,0x6e,0x5e,0x88,0xfe,0xb7,0x9d,0x9b,0xc9,0x6c,0x67, -0x76,0xf4,0xd1,0x34,0x46,0xaf,0x85,0xad,0x7e,0x18,0xdd,0xe4,0xa9,0x19,0x62,0x75, -0xd1,0x19,0x57,0x95,0x3d,0x11,0x9d,0xaf,0xed,0xec,0x87,0xd7,0x66,0xcb,0x0a,0x71, -0x43,0x98,0x03,0xcb,0xe0,0xd0,0x88,0xe6,0xeb,0x55,0x3f,0xe4,0x8d,0x4b,0xeb,0xdd, -0x8f,0x6f,0xd5,0xcb,0x61,0x34,0x67,0x07,0xcd,0x17,0xc0,0xa5,0x6b,0x75,0xef,0x27, -0x68,0x3d,0x3e,0x34,0x3e,0x24,0xb2,0x0a,0xc9,0x24,0x44,0xa6,0x25,0xaf,0xbd,0x89, -0x26,0x0e,0x37,0x0d,0x02,0x89,0x0f,0x92,0xc8,0xb4,0xc5,0xe2,0xd2,0x6a,0x23,0xca, -0xa1,0x1f,0xbe,0xad,0xf9,0xe1,0x9e,0x63,0x5c,0x8a,0x33,0x26,0xea,0x59,0x6c,0xb8, -0x6b,0xd5,0x11,0xae,0x8c,0xfe,0xaa,0xdc,0xfe,0x7e,0xa8,0x52,0x3f,0x34,0xd6,0x5f, -0x32,0x65,0xf7,0x55,0xeb,0x57,0x3f,0xe4,0xaa,0xf9,0x37,0x3a,0x2e,0x45,0xfa,0x34, -0xf6,0x5a,0x06,0xad,0xaf,0x40,0xca,0x1e,0xdd,0x20,0x9d,0x11,0xca,0x22,0xfa,0xdd, -0xf7,0xd6,0x9b,0xc8,0x38,0x8c,0x3a,0x44,0xa3,0xb1,0x16,0xf4,0xc3,0x64,0x11,0x8e, -0x68,0x85,0x7b,0x46,0x27,0xda,0xd0,0x6a,0x69,0x64,0x74,0xa9,0xb9,0xd7,0x82,0xb5, -0x96,0xf2,0xd5,0x0c,0xb1,0xcc,0x23,0x5b,0x2b,0xd3,0x98,0x95,0x47,0xdb,0x98,0xc3, -0x32,0x75,0xbf,0x75,0x92,0x13,0xcb,0xb4,0xfa,0x40,0x2b,0xb4,0xd3,0x34,0xda,0x0f, -0x91,0x46,0xe3,0xaf,0x65,0xd6,0x1c,0xcb,0x07,0xfa,0x5c,0x82,0x1d,0x4a,0x25,0xa1, -0x71,0xd2,0x94,0xdf,0xc8,0x4d,0x4f,0x92,0xfa,0x21,0x28,0x84,0x46,0xe8,0x93,0xad, -0x55,0x3f,0x34,0x8f,0x26,0x87,0xf4,0xb1,0xdb,0x11,0x87,0x1f,0x64,0x4c,0xbd,0x87, -0x60,0xee,0x21,0xea,0x03,0xf3,0x16,0x3b,0x90,0x4c,0x00,0x2e,0x7e,0xb8,0x1f,0x38, -0xc4,0x99,0x76,0x2c,0x63,0x70,0x41,0xde,0xd6,0x3a,0x71,0xc8,0xd7,0x12,0xde,0x0c, -0x3f,0x44,0xba,0x31,0x88,0xc6,0x67,0xcd,0x64,0x66,0x16,0x5f,0xcb,0xbc,0xbd,0x88, -0x56,0xc4,0x64,0xc5,0x60,0x92,0xd2,0x88,0xbc,0x11,0xb1,0xc8,0xdf,0x9b,0xf8,0x6e, -0xcc,0xce,0xa1,0xbd,0x24,0x8b,0x73,0x72,0x6b,0xf8,0x61,0xd7,0x6a,0xb2,0x18,0xdb, -0x64,0xf3,0x3d,0x18,0x83,0x66,0x4f,0x8c,0x15,0xf7,0x72,0x4b,0x0e,0xbd,0xf8,0xa4, -0x67,0xac,0xac,0x74,0xad,0x7a,0x7b,0x65,0xfb,0x4c,0x0f,0x33,0x89,0xaa,0x91,0xdb, -0xbb,0xbd,0xe3,0xd2,0xb2,0x02,0xe6,0x35,0x5b,0x7a,0x2b,0x58,0x69,0x6e,0x5c,0xda, -0x0c,0x3f,0x44,0xba,0x3f,0x74,0x72,0xd1,0x5e,0x66,0xf4,0xc2,0x88,0xdc,0xd6,0xfd, -0x91,0x38,0x23,0x6f,0x6f,0xe2,0x6d,0x8d,0xc3,0xa4,0x0b,0x85,0xd1,0x16,0x8a,0x4b, -0xbb,0x56,0x2b,0xff,0x6a,0xc2,0x99,0x56,0xb1,0x4d,0xc8,0xa1,0xad,0xf7,0xd0,0x87, -0x6b,0x39,0x65,0xc6,0xb1,0x7a,0x21,0x6e,0xed,0xaf,0x47,0xbe,0xe7,0xc6,0x08,0x73, -0x08,0xdc,0x0f,0xae,0x00,0x22,0xd7,0x9b,0x43,0x5e,0x3f,0x6c,0x16,0x87,0x68,0x6d, -0xb8,0xce,0x05,0x6b,0x39,0xa2,0x17,0xc6,0x24,0xa1,0x11,0x9f,0x7b,0x3b,0xb9,0x7e, -0xae,0xde,0xc4,0x77,0x39,0x38,0xc4,0xf5,0xc3,0x7a,0xbf,0x47,0x3e,0xa1,0xfa,0x21, -0x19,0x07,0x8b,0xe7,0x89,0xe0,0xd1,0xe8,0x66,0x67,0x44,0xb7,0x57,0xe6,0x10,0x9d, -0x49,0x5e,0x62,0x77,0x2c,0xe7,0x11,0x75,0x66,0x0a,0x71,0x69,0x5f,0x0e,0x2f,0x4c, -0x97,0x95,0x75,0xa3,0x5d,0x94,0xac,0xdf,0x41,0xdd,0x1e,0xac,0x15,0x58,0x56,0x2e, -0x04,0xbe,0xf2,0x51,0x7d,0xda,0x69,0x46,0xe3,0x78,0x6e,0xc1,0xb9,0xea,0xfb,0x41, -0x97,0xff,0x1b,0xfb,0xd1,0xf8,0x5b,0xd3,0x84,0xb8,0xd7,0xd0,0x66,0x8d,0x4c,0xa9, -0x17,0x92,0xc8,0x34,0x2d,0xed,0xe4,0x6e,0x73,0xcc,0xb5,0xe5,0xf1,0x43,0x54,0x0a, -0xf2,0xf9,0xb1,0xfb,0x43,0xe1,0x91,0xfa,0x14,0x7e,0x6f,0x42,0x7e,0x18,0xa5,0xe3, -0x61,0x9d,0xf3,0x77,0xe8,0x7e,0x68,0xe1,0x10,0xb6,0x96,0x96,0x7d,0xad,0x56,0x64, -0xf5,0x43,0x4b,0x54,0x2a,0xb3,0x79,0x32,0xad,0xc3,0xe1,0xcd,0xc1,0xf0,0xc8,0xe7, -0xc7,0x58,0x41,0xd7,0xcc,0x1b,0x2a,0x64,0x7f,0x77,0xe8,0xc8,0x02,0x65,0x8e,0xf6, -0x1b,0x3a,0x15,0x34,0xbb,0x33,0x3e,0x76,0x9e,0xbb,0xbc,0x38,0xe6,0x7e,0x2e,0x06, -0xef,0x87,0xa3,0xf1,0x48,0xbe,0x64,0xfb,0xc6,0xec,0x97,0xfd,0x14,0x77,0x62,0x98, -0x87,0x0d,0x70,0x64,0x75,0xe3,0xe5,0x10,0x3d,0x5f,0xfd,0x4a,0x59,0xe1,0x39,0x56, -0xa4,0x88,0x56,0x3f,0x34,0x46,0x1c,0x98,0xe6,0x84,0xa0,0x3e,0xe0,0x2f,0x41,0x6b, -0x0d,0xe2,0xd0,0x79,0x34,0x4d,0xc9,0xe7,0xec,0x69,0xe7,0x8c,0x8d,0xd0,0x0f,0xd5, -0x96,0xe2,0xb0,0x37,0xbc,0x94,0x71,0xa6,0x88,0xd1,0x04,0x37,0xe3,0xdd,0xe0,0x19, -0x4e,0xb0,0x8d,0xb4,0xc2,0x63,0x79,0x8b,0x3e,0x42,0xb9,0x98,0x95,0xdd,0x56,0x9f, -0x0d,0xbe,0x7e,0xb8,0xa3,0xc7,0x4e,0x74,0x1e,0x9f,0xfd,0x9c,0x26,0x6b,0x75,0xd6, -0xb5,0x24,0x8b,0x57,0x39,0x66,0x61,0xf0,0x73,0x18,0x70,0xd9,0x04,0xed,0xb2,0x9b, -0xc9,0x62,0x49,0xfe,0x94,0x2b,0x53,0x46,0x97,0xce,0x21,0xcc,0x07,0x80,0x3f,0x63, -0x63,0xbe,0x24,0x6d,0xaf,0xc1,0x1c,0xc2,0x5e,0x0b,0x32,0xf7,0x30,0x2d,0xf9,0x6b, -0xcf,0x74,0xca,0xc8,0x01,0xce,0x4c,0x3a,0x3a,0xba,0x3e,0xeb,0x01,0x79,0x17,0x8a, -0x31,0xcd,0x33,0x98,0xe8,0x25,0x32,0x7f,0x82,0xd6,0xfb,0x4c,0xde,0x57,0xc5,0x07, -0xf9,0xa9,0xb6,0x92,0x1a,0x2b,0xba,0xfd,0xfa,0xb9,0xf9,0x21,0xad,0xf9,0x73,0x72, -0xd8,0x1b,0x4a,0x4b,0xe8,0x4c,0x33,0x46,0x4e,0x2b,0xe6,0xf5,0x70,0x0d,0x2e,0x2d, -0x7d,0x74,0xa4,0xf7,0x3c,0x48,0x0a,0xf9,0x6a,0x74,0x4d,0xe3,0xd0,0x56,0x6e,0x72, -0xcd,0xd1,0xff,0xbf,0x39,0x70,0xb4,0xda,0x27,0x86,0x3f,0x5f,0x90,0xa1,0x83,0x64, -0xe2,0x28,0x76,0xad,0xae,0x65,0x9c,0x32,0x26,0xfa,0x9d,0x23,0x56,0xad,0x7e,0x68, -0x5e,0xd7,0x9b,0x67,0xd4,0x78,0xfd,0x85,0x62,0x4c,0x38,0x6f,0xb0,0x00,0xfe,0x92, -0x31,0xa4,0x34,0xdf,0x0a,0x58,0x0f,0xde,0xb2,0x26,0x6f,0x60,0x44,0xba,0x8d,0x5c, -0x0a,0xba,0x7e,0xd8,0x1b,0x46,0x1c,0xda,0xf3,0xb7,0xc4,0xa8,0x0f,0x1a,0x63,0xa8, -0xe1,0x6a,0xd5,0x9b,0xf0,0xdc,0x82,0x7b,0x6b,0x8f,0x3a,0x3f,0x87,0x7c,0x91,0x5e, -0xb3,0x39,0x64,0xef,0x9e,0x2f,0x57,0x06,0xee,0xb7,0x88,0x92,0xc7,0x19,0x19,0x3b, -0xca,0x60,0xfe,0x24,0x76,0xc4,0x58,0x31,0x92,0xdf,0x26,0x1c,0xd2,0x5e,0x0b,0x55, -0xf6,0xbf,0x5e,0xd8,0xde,0x4f,0xcc,0x7e,0x58,0x62,0x7e,0x28,0xc3,0x5c,0xe0,0xad, -0xc4,0x21,0x98,0xbd,0x0b,0x7c,0x91,0xe4,0x99,0xa1,0x23,0xd6,0x4c,0x3e,0x68,0x5a, -0xd1,0x2a,0x10,0x2f,0xe4,0xe5,0xd0,0xbd,0x7e,0xe8,0xc5,0x0f,0x8f,0x19,0x1c,0x46, -0x8d,0x55,0xe2,0xf1,0x38,0x15,0x3c,0x8b,0x2f,0x0a,0xb9,0xb2,0xf4,0x94,0xfb,0x25, -0xce,0x99,0x42,0xde,0x95,0xaf,0x9b,0xcd,0x21,0x2b,0x7c,0x7e,0xd8,0x95,0x47,0x47, -0x1b,0xc5,0xbf,0x63,0xa6,0xdf,0x2a,0x7c,0x0b,0x9b,0xb9,0x8c,0xda,0x8c,0x71,0xab, -0x15,0xcb,0x4c,0x53,0x4b,0x8b,0xb7,0x7d,0xc6,0x15,0x23,0x91,0xd5,0x0d,0xb3,0x2d, -0xc5,0x21,0x9c,0x5b,0x4f,0x58,0x2c,0xc9,0x30,0xff,0x18,0x6b,0x03,0x55,0x4d,0x11, -0x69,0xed,0x34,0x5a,0x09,0x72,0xcb,0x0d,0xe6,0xee,0x87,0xa4,0xc6,0xc1,0x19,0x97, -0xea,0x1c,0x12,0xb2,0xa2,0xa0,0x36,0x68,0x8c,0xdb,0xa4,0xfc,0x59,0xc9,0x0b,0x8e, -0xc4,0x64,0x91,0x37,0xf3,0x7e,0xeb,0x70,0xc8,0xe7,0x87,0x11,0xdd,0x0f,0xd9,0x27, -0x86,0x0b,0xa2,0x8f,0xee,0xf5,0xba,0x63,0x6c,0x13,0x73,0x08,0x33,0x44,0x4d,0xd6, -0xb4,0x02,0xcc,0x5e,0xce,0x7e,0x9e,0x90,0x33,0x50,0x05,0x2b,0xd4,0xb4,0x12,0x87, -0x30,0x2a,0x55,0x69,0x9e,0x99,0x02,0xec,0x9f,0x37,0x66,0xd8,0x7b,0x8f,0x3e,0x79, -0xe8,0x83,0xd1,0xa4,0x57,0x3f,0xb4,0x8f,0x94,0xc2,0x97,0x92,0x9e,0xfc,0x90,0x9c, -0x25,0x76,0xc2,0xa2,0x01,0x7b,0x9f,0x13,0x85,0xfc,0xbd,0x7d,0x98,0xc3,0xa4,0xfe, -0xa8,0xca,0x5b,0xac,0xca,0x3e,0xa8,0xc2,0xe7,0x87,0x91,0x3c,0x79,0x5d,0x36,0x1f, -0x24,0x6a,0x27,0x53,0xbb,0x9e,0xd0,0x38,0x64,0x63,0x69,0x50,0x66,0x1a,0x9e,0x76, -0xab,0xca,0x72,0xf2,0x43,0x7c,0x26,0xaf,0xcb,0x90,0xc2,0xb4,0xc3,0x1a,0x35,0xcd, -0x10,0xab,0x1f,0x5a,0x32,0x00,0xd2,0x91,0xdc,0x25,0xd6,0x52,0x83,0x59,0xb4,0x66, -0xc9,0x0d,0x90,0x46,0x1e,0x3f,0x74,0x8a,0x4b,0xed,0x39,0xad,0xbd,0xfa,0x61,0xd4, -0xdc,0x3e,0x53,0xa4,0x75,0x1a,0x47,0x3a,0x83,0xe5,0x90,0x7f,0x1d,0x1a,0xe2,0x87, -0x56,0xaa,0x82,0xa6,0xcc,0xbd,0xf0,0xf9,0xa1,0xd1,0x16,0x8d,0x7b,0xf0,0x49,0x9c, -0x01,0x3e,0x5f,0xec,0x85,0x98,0x43,0xd8,0x4a,0x53,0x90,0x6b,0x1d,0x01,0xa2,0x71, -0xb8,0x69,0xa7,0x50,0x35,0xad,0x5f,0x8a,0x56,0x4e,0x6c,0x25,0x0e,0x59,0xbd,0x90, -0x44,0xa2,0x05,0x1a,0x8d,0xd2,0x88,0x5a,0x61,0xe3,0x46,0xbd,0x12,0xe8,0xee,0x83, -0xb4,0xdc,0xf1,0xe2,0x87,0xf6,0x75,0x8e,0x58,0x56,0x5d,0x2f,0x7e,0x98,0x2c,0x56, -0xf0,0xc0,0x3a,0xf5,0x56,0x24,0xc1,0xde,0xdb,0xd8,0x17,0x3e,0x3f,0xf4,0xb2,0xc1, -0xe3,0x09,0x9e,0xc3,0xb5,0x4c,0xd2,0xf8,0x1c,0x69,0xeb,0x33,0x6c,0xd9,0x02,0xfd, -0x44,0xa9,0x3c,0x5a,0x6f,0x2d,0xa5,0x73,0x98,0x95,0x6b,0x1f,0x1b,0x5c,0xc9,0x0f, -0x61,0x0b,0x0d,0xce,0x66,0xc2,0x3f,0x97,0xaa,0x9e,0x82,0xf5,0x43,0xd5,0xa8,0x17, -0x92,0x96,0x98,0x75,0x05,0xf6,0x12,0x92,0xb5,0x72,0xaa,0xf5,0x17,0xfa,0x8f,0x48, -0x09,0x59,0xfe,0xda,0x69,0xac,0x63,0x35,0x3c,0xd7,0x0f,0x8b,0xf5,0x25,0xaf,0x32, -0x91,0xc9,0xa2,0x97,0xd9,0x3c,0xd0,0x0f,0x9b,0x49,0xa1,0x17,0x0e,0x4d,0x71,0x84, -0x29,0xca,0xa7,0xbd,0x42,0xda,0x3e,0x25,0xb1,0xbc,0xa5,0x89,0xfc,0x67,0x3d,0xfc, -0x9f,0x89,0xb3,0xac,0x1c,0x92,0xa8,0x14,0xb6,0xd0,0xcc,0xe9,0x1c,0xb6,0x46,0xff, -0x21,0xe6,0x90,0xd0,0x47,0x33,0x00,0xd3,0x76,0x18,0x15,0x8e,0x1f,0xf5,0x4d,0x1f, -0x97,0x17,0x22,0x8a,0x5c,0x73,0xb8,0xdb,0x39,0x84,0x2b,0x1f,0xe9,0x7f,0xf5,0x56, -0x71,0xcf,0x7e,0x58,0xa7,0x7a,0x60,0x75,0x12,0xf8,0x5b,0x4a,0xb1,0x88,0x1f,0xfa, -0x2d,0x31,0xb0,0xf7,0x4f,0x29,0xba,0x8d,0xaf,0x7e,0xf8,0x41,0xce,0xe9,0xf1,0x3a, -0x83,0x80,0xc5,0xa8,0xce,0x21,0x6b,0x2b,0x7d,0x71,0xcc,0xcb,0x67,0xe2,0x2c,0x33, -0x87,0x2c,0x2a,0x55,0x4d,0x75,0x43,0x54,0xf8,0xde,0x49,0xbd,0xc5,0xe2,0x52,0x53, -0xc6,0x27,0xdc,0x5a,0xa3,0x10,0x2e,0x55,0x9f,0xfd,0x84,0x5e,0x49,0x74,0xf7,0xc3, -0x67,0x47,0x2a,0x65,0x1e,0x82,0xeb,0xa6,0xf8,0xf1,0xc3,0x46,0x8c,0x9b,0x81,0x67, -0x37,0xde,0xbc,0x8d,0x60,0x66,0x1c,0xc6,0x1c,0xc8,0x0a,0x26,0x62,0xe5,0x2b,0x7c, -0x7e,0xb8,0x9d,0x01,0xcf,0xb8,0x69,0xa7,0xcf,0xe8,0x23,0xd2,0xf6,0x28,0xbb,0x0f, -0x72,0xc3,0xac,0x1c,0xcc,0x98,0x64,0x27,0x0e,0x4b,0xa6,0xfe,0x8a,0x65,0x23,0x7f, -0x57,0xeb,0xf8,0x21,0x6b,0x1f,0x45,0xe4,0xad,0xd3,0xf6,0x18,0x3f,0xe3,0x65,0xfc, -0x7b,0x21,0x2a,0x31,0x57,0x3f,0xbc,0x3a,0x01,0x33,0x0f,0x59,0x57,0x37,0xa2,0xb9, -0xad,0x3d,0xd4,0x0f,0xe7,0x24,0xfe,0xb3,0xcf,0x2b,0x65,0x95,0x7d,0x10,0xef,0xbd, -0xb9,0x61,0xed,0x7e,0x18,0x9c,0x47,0xf2,0xb9,0xc8,0x76,0x45,0x3f,0x24,0x64,0x92, -0x82,0xa2,0x51,0x7f,0x39,0x7b,0x9c,0xe5,0xec,0x87,0xa0,0x8d,0x46,0xf7,0x42,0x54, -0x1b,0x6d,0x15,0x0e,0xcb,0x4a,0x01,0xf8,0xa0,0x8d,0x40,0x3a,0x86,0xc6,0x3a,0xab, -0x29,0x68,0x2f,0xc4,0x71,0xa9,0x9b,0x1f,0x22,0x0e,0xa1,0x0f,0xc2,0xb5,0x8f,0xe8, -0xa5,0xa2,0xe7,0x7e,0x8b,0x00,0x7d,0x90,0x8f,0x46,0x5c,0xbc,0xce,0xe7,0x09,0x96, -0xc3,0x98,0xc3,0xbe,0x3a,0x7d,0xac,0x78,0x6a,0xa7,0x71,0x2c,0xe6,0x96,0x1b,0xc4, -0x61,0x5a,0x8b,0x4d,0xf9,0xc6,0xad,0xba,0xcb,0x89,0xc3,0x75,0x45,0x35,0xd5,0x0d, -0x27,0x5b,0x8a,0x43,0xd2,0x22,0x53,0xa2,0x99,0x66,0x68,0x3d,0xb0,0xa6,0x7a,0xa1, -0x9f,0xc2,0xe7,0x87,0x96,0xf9,0xdc,0x77,0x30,0x8f,0x64,0x76,0x0d,0xee,0xa1,0x6a, -0x94,0x1f,0x56,0x27,0x2d,0xe6,0x78,0xfe,0xe3,0x32,0xe5,0xd9,0x0d,0x11,0x87,0x6a, -0xe0,0x7e,0xc8,0x4b,0xac,0x79,0xe3,0xe3,0xf0,0xc0,0x59,0xde,0xcf,0x36,0xab,0xc7, -0x88,0xf1,0x00,0x6a,0x86,0x58,0xe6,0x19,0xc8,0xe4,0x7c,0xb6,0x46,0xa5,0xad,0xc4, -0x61,0x59,0xff,0x9d,0x20,0x19,0x10,0x0b,0x8c,0x29,0xb9,0x64,0xce,0xfe,0xe4,0x3b, -0x32,0xe5,0x2f,0xee,0xed,0x34,0xe7,0xc7,0x92,0xa0,0x7e,0x08,0xfc,0x10,0xdd,0x0a, -0x56,0x5f,0x49,0x16,0xb7,0x39,0x39,0xcc,0x06,0x30,0x42,0x05,0x7a,0x06,0x2f,0x91, -0x53,0x9e,0xdd,0xb0,0x91,0x1c,0x56,0x7a,0x2f,0xe4,0x7d,0xf0,0xae,0xc5,0x76,0x64, -0x31,0x06,0x9e,0xb3,0x0a,0x87,0x9a,0x3f,0xd5,0xb2,0x02,0x8f,0x55,0x3b,0x36,0x3f, -0xd4,0xa2,0x52,0xc5,0xdc,0x63,0x81,0x39,0x6c,0x8d,0xfe,0x43,0xb4,0xd6,0x3b,0x9d, -0x53,0xa1,0xd4,0x36,0x9f,0xa2,0x36,0x2f,0xe4,0xf3,0xc3,0x73,0x71,0x74,0x2f,0xb2, -0x72,0x26,0x5c,0xe3,0x01,0xcc,0x8d,0xd0,0xb6,0xa9,0x22,0xef,0xec,0xd1,0xbd,0xdc, -0xa9,0x8a,0x14,0xd5,0xab,0x4c,0x15,0xa7,0xb6,0xfc,0xd5,0x84,0x12,0xf9,0x53,0x5b, -0xf6,0x67,0x63,0xfb,0x29,0xcb,0x75,0xa7,0xfb,0xd5,0x5a,0x4e,0x15,0x0b,0xf2,0x65, -0xee,0xb5,0x8d,0xdf,0x18,0x3c,0x70,0xf6,0xc8,0xc2,0x5e,0x2e,0x2d,0xa1,0x5e,0xdd, -0x4a,0x4c,0x16,0xe4,0x93,0x01,0xd5,0x0c,0xb1,0x0e,0x9c,0x45,0xcf,0x8a,0xe3,0x5e, -0x13,0x8d,0x26,0x12,0xd3,0x52,0x73,0xb2,0x18,0xd9,0xf5,0xdc,0x74,0x99,0x9b,0xae, -0x5a,0x08,0xb3,0xe6,0xaf,0x24,0x6d,0x9b,0x74,0xf5,0x4c,0x7d,0xcc,0x45,0x92,0x23, -0x5f,0xf3,0xfb,0xb3,0x25,0x90,0x51,0x01,0xae,0xb6,0xc9,0xc6,0x6b,0x94,0x95,0xbd, -0xdc,0xcb,0x9c,0x67,0xca,0xb9,0xf8,0x77,0xa4,0x5a,0xdf,0x97,0x75,0x83,0x9f,0x9b, -0xd3,0x67,0x39,0x27,0xf9,0x1d,0x2f,0xf2,0xc6,0x60,0x2a,0x5f,0x02,0xdf,0x84,0x79, -0x54,0x22,0x2c,0xaa,0x65,0x5f,0x70,0xb9,0x1f,0x5f,0x41,0x31,0x5d,0x2a,0x1f,0xf6, -0xb5,0x4e,0xce,0x68,0x3c,0x3e,0x76,0x6d,0x76,0x66,0x31,0x91,0xcf,0xca,0x28,0x62, -0x81,0xde,0x3b,0x29,0xbd,0x13,0x50,0xcd,0x90,0xe8,0xc2,0x34,0xcc,0xdf,0x8c,0xf3, -0xc7,0xa2,0x7c,0xb2,0x7b,0x39,0x9c,0xdb,0x12,0xe5,0x45,0x78,0x78,0xa9,0x75,0x56, -0x03,0x46,0x19,0xe1,0xc9,0x1a,0x0c,0x64,0x1d,0x06,0xeb,0x7a,0x0c,0x4e,0x6b,0x34, -0x38,0x95,0x49,0xd7,0x92,0xb6,0x5c,0x32,0x3f,0xf7,0xe0,0x62,0x0f,0xc7,0x11,0xf7, -0xf7,0xde,0x1d,0x22,0xe5,0xa6,0xe3,0xde,0x6b,0xac,0x81,0xf2,0x59,0xf8,0x58,0xa9, -0xb3,0xc2,0x36,0x1a,0xef,0xef,0xad,0x5e,0xfc,0x7c,0x4f,0x4c,0x4f,0xb2,0x67,0xd2, -0x5e,0xe9,0xd3,0xd8,0xed,0x06,0x96,0xef,0x87,0x83,0xc8,0x40,0x75,0xb9,0xf3,0x8d, -0xc1,0x5b,0x13,0x0f,0x2f,0xed,0x68,0x2e,0x89,0xb2,0xb1,0x15,0x6a,0x1c,0x4d,0x1a, -0xac,0x5e,0x09,0x15,0x43,0x77,0xf4,0xed,0x4a,0x68,0x21,0xf4,0x5b,0x0d,0x7b,0xdd, -0x63,0xe1,0x77,0x3a,0x2f,0x77,0xda,0xb7,0x77,0x1c,0xf6,0x4e,0xe5,0x5d,0xf4,0x37, -0xf6,0xae,0x76,0x9f,0xde,0x70,0x6f,0xb8,0x27,0xdc,0xeb,0x58,0x2a,0xdd,0x4e,0x4a, -0x6b,0x64,0x18,0x13,0x6a,0xb4,0x9e,0xec,0x7d,0x75,0xf0,0xfb,0x2d,0xf5,0xdd,0xab, -0x47,0x57,0x8e,0x5f,0xd4,0xca,0x94,0x56,0x7e,0x3c,0xbe,0x92,0xba,0x98,0x92,0x5f, -0xf8,0xe1,0xa1,0x67,0x3b,0xf8,0x1e,0xdd,0x11,0x3a,0xcf,0x79,0x4f,0x21,0x21,0xa1, -0xca,0x7a,0xee,0xe0,0xca,0x71,0x5c,0xe6,0xb5,0x6d,0x77,0xbc,0xfb,0xcc,0xf0,0xb9, -0xc7,0xe3,0xf3,0x09,0xb9,0xef,0xa3,0xa7,0xdc,0x1f,0x7d,0xb0,0x6f,0x7e,0xb8,0x58, -0xff,0x83,0x14,0x12,0xda,0xf7,0x3a,0xd8,0xf7,0xa1,0xc6,0xe0,0xbc,0xe6,0x89,0x68, -0x5b,0x19,0x7f,0xf4,0xbd,0xee,0x73,0x8f,0x53,0xd7,0x87,0x4f,0xf5,0xff,0xdd,0x33, -0xd5,0x1f,0xf9,0x2b,0xbf,0x3c,0x3f,0x3c,0x3f,0xfc,0x7b,0x07,0x1b,0x73,0x9c,0x42, -0x42,0xfb,0x59,0x1d,0xa1,0x2f,0xf4,0xd8,0x74,0x5e,0x8f,0x4f,0x2f,0x22,0x57,0x4c, -0x75,0x9f,0xc1,0x24,0xbe,0xf6,0x42,0x4f,0xc5,0x28,0xfa,0x46,0xe8,0xf9,0x04,0xe2, -0x50,0x3e,0xdc,0xc8,0xa3,0x15,0x12,0xda,0xaf,0xfa,0x7a,0xc7,0x14,0xa5,0x50,0xab, -0x27,0x0e,0x5f,0x3c,0xfe,0xa1,0x16,0x9f,0x76,0x9f,0xd9,0x38,0x3e,0x3f,0xb0,0xf6, -0xdd,0xff,0x51,0xa1,0x6d,0x77,0xf9,0xf0,0xfc,0xf0,0xd4,0x30,0xda,0x44,0x64,0x2a, -0x24,0x14,0x84,0x50,0x2d,0xf1,0x22,0x20,0x71,0x0a,0xc7,0xa7,0x1a,0x89,0x17,0xc7, -0xff,0xf5,0x52,0xbf,0x43,0x36,0xc7,0x9f,0x1d,0x42,0x04,0x6a,0xcc,0x0e,0xaf,0x0c, -0xff,0x50,0x44,0xa6,0x42,0x42,0x81,0xe8,0x60,0xdf,0x8a,0x46,0xa0,0x41,0xa1,0x5e, -0xe6,0xf5,0xf8,0x74,0x77,0xfc,0xef,0x17,0x7e,0x7f,0xd1,0x3a,0xa2,0xe8,0x6a,0x07, -0xb9,0xd7,0x94,0x88,0x4c,0x85,0x84,0x02,0x53,0x47,0x48,0x3d,0x3a,0xaf,0xf7,0x5e, -0x58,0x49,0x8c,0x5d,0xe9,0xca,0xcf,0x2c,0x9e,0x07,0xa3,0x61,0x8f,0x6b,0x35,0x4a, -0x72,0x9f,0x8b,0x28,0x32,0x4d,0xdc,0x68,0xde,0x81,0x0b,0x09,0xed,0x2b,0x7d,0xbd, -0xe3,0xf9,0x61,0x48,0xa1,0x4e,0xd9,0xf1,0x8d,0xf1,0x53,0x6f,0x65,0xe5,0x48,0x7e, -0x29,0xc3,0x72,0x29,0x1c,0xed,0x83,0xf7,0xd1,0x4a,0xe2,0x7f,0x8b,0x5e,0x44,0x21, -0xa1,0x80,0xf4,0xdc,0xc1,0x8b,0x30,0x32,0xd5,0xf7,0xf3,0x89,0x53,0x57,0xa6,0xb6, -0x54,0x39,0x91,0x5f,0xcb,0x5c,0x98,0xee,0xd1,0xee,0xf5,0x9f,0x0e,0x9a,0x48,0xd5, -0x28,0x4c,0x0e,0xfc,0x9b,0xa8,0x21,0x0a,0x09,0x05,0xa6,0x3f,0x3d,0xf4,0xfa,0xe1, -0xcc,0x61,0xf9,0xa8,0x7c,0xf4,0xef,0x8f,0xaa,0x47,0xbf,0xd0,0x8a,0xda,0x57,0xfe, -0xd1,0x75,0xf5,0xd4,0x56,0x49,0x99,0x94,0x76,0x72,0xef,0xcf,0xfe,0x79,0x6f,0xf9, -0x68,0xd2,0xe4,0x86,0xc9,0x44,0xb9,0xef,0xf5,0xee,0x66,0x1f,0xb9,0x90,0xd0,0x7e, -0x12,0x99,0x5b,0xd2,0x11,0xfa,0x5a,0xa8,0x4f,0x2b,0x1d,0xa1,0x5f,0x9c,0xde,0x50, -0xaf,0xab,0xf3,0x5b,0x65,0x05,0xad,0x98,0x77,0x72,0xe1,0x3f,0x8f,0x27,0x13,0x90, -0xc3,0xe8,0x40,0xb9,0x7b,0xb9,0xef,0x95,0xe6,0x1e,0xb6,0x90,0xd0,0xbe,0xd1,0xe5, -0xce,0x5f,0x9c,0x3e,0xb2,0x70,0x6d,0xd6,0xdc,0x77,0x7f,0x7f,0x08,0x71,0x78,0x5d, -0x5d,0xd9,0x42,0x33,0x27,0xb7,0x73,0xff,0xeb,0xb7,0x92,0x89,0xe4,0x30,0xf5,0xc4, -0x44,0xb4,0x5f,0xed,0x96,0xfb,0xae,0x34,0xeb,0xa0,0x85,0x84,0xf6,0x95,0xce,0x8f, -0x7d,0xf3,0x47,0x33,0x8b,0x3b,0xb9,0x49,0xc9,0x9c,0xdd,0x21,0x3c,0x82,0x39,0xd4, -0x48,0xd4,0xe2,0xd3,0x6f,0x2e,0xfc,0x6d,0xc7,0x14,0xa3,0x70,0xf8,0xf9,0x81,0x2f, -0xfa,0xe4,0xae,0x97,0xfa,0x1a,0x37,0x53,0x43,0x48,0x68,0xbf,0xea,0xe6,0xd0,0xfb, -0xb3,0x27,0x17,0xd7,0x32,0x91,0x3c,0x9a,0xc1,0x3c,0xbf,0x05,0xf3,0x3b,0x10,0x3f, -0xbc,0xae,0x6e,0xa8,0xc9,0xe2,0xed,0x58,0x7f,0x28,0x9a,0x98,0x4a,0x50,0x37,0x1c, -0x50,0xbb,0x97,0xbb,0x7e,0xee,0x32,0x12,0x55,0x48,0x48,0xa8,0xba,0xbe,0x1d,0xbf, -0x30,0x7d,0x72,0x71,0x29,0xb3,0xa7,0x39,0x21,0xca,0x44,0x32,0xbf,0x85,0x88,0x63, -0xeb,0x1f,0xdc,0x1d,0xc2,0x5e,0x88,0xfe,0xe2,0x99,0x93,0xaf,0xf7,0xc1,0x36,0x1a, -0xb5,0x2b,0xd3,0xfd,0x17,0x2d,0x33,0xc3,0x58,0x48,0xa8,0xfd,0xf4,0xdf,0x3b,0x1f, -0x68,0x35,0xc2,0x99,0xcc,0x4e,0x0e,0xe5,0x0d,0x40,0x4e,0x48,0x9c,0x6f,0x7e,0x8b, -0xe4,0x94,0xc2,0x1c,0xa2,0xdb,0x48,0x36,0x8f,0x5f,0x41,0x3d,0x17,0x09,0x1c,0x95, -0xaa,0xdf,0x58,0x7e,0x62,0xfb,0xbb,0x62,0x3e,0xad,0x90,0x90,0x4f,0x85,0xaf,0x8e, -0x3d,0xf5,0xfa,0x6b,0x0b,0x1f,0x2c,0x46,0x56,0xd3,0x1a,0x83,0x53,0x5b,0x2b,0xba, -0x13,0x12,0xea,0x4a,0x0a,0xa6,0xeb,0x8d,0x41,0xec,0x90,0x59,0x99,0x3c,0xf0,0x0a, -0x8a,0x4c,0x51,0xbf,0x61,0x7f,0xe9,0x89,0x6f,0x0d,0xcb,0x0b,0xc1,0x64,0x43,0x16, -0x12,0xfa,0xea,0x69,0xe0,0x99,0x5f,0x1d,0xbf,0x38,0xfe,0xe1,0xf8,0xa3,0xd4,0xa3, -0x57,0xfe,0xfd,0x95,0xa1,0x2b,0xff,0x20,0x0d,0x15,0x37,0xd4,0x5d,0x83,0x43,0xf4, -0x77,0x57,0xc5,0xeb,0xc6,0x23,0x0e,0x37,0xd4,0x53,0x5b,0xe7,0xc0,0x68,0xef,0xae, -0xae,0xa9,0x81,0x8b,0xe3,0x5f,0xbe,0x7e,0x71,0x79,0x5d,0x4e,0x49,0xb5,0xe6,0x3e, -0x11,0x12,0xfa,0x2a,0x2a,0x1f,0x92,0x8f,0xce,0x0f,0x5c,0x1f,0xf8,0xe4,0xf8,0xe3, -0xd4,0xe3,0xd4,0x6e,0x6a,0x77,0x7c,0x63,0x7c,0xe5,0xf8,0x5f,0xf7,0x7e,0x7e,0x6c, -0x29,0x53,0x52,0xae,0xeb,0x34,0x6e,0xe8,0x34,0xa2,0x15,0xd4,0x3f,0xeb,0x29,0x2b, -0xb0,0xbe,0x88,0xf4,0xf6,0x77,0x3f,0x5c,0x3d,0xb5,0x89,0xfb,0xf7,0xdd,0xb3,0x9d, -0x09,0x09,0x09,0x59,0x75,0x25,0x54,0x3e,0x7c,0x7d,0x60,0x03,0x31,0xf8,0xbd,0x47, -0x88,0xc2,0xd4,0x86,0xb6,0x7d,0xf1,0x02,0xf9,0xff,0xcd,0xa1,0x8f,0x2f,0x65,0xe5, -0x53,0x9a,0x07,0x7e,0x72,0x0f,0xc7,0xa2,0x9f,0xc6,0xd8,0x7c,0x8b,0xf8,0xd8,0x52, -0xa6,0xac,0xe0,0xd8,0x75,0x7e,0x2b,0xb6,0x99,0x96,0xee,0xb7,0xc4,0xda,0x35,0x42, -0x42,0xed,0x25,0xf9,0xf0,0x5f,0x0e,0x7f,0x32,0xde,0x7d,0x86,0x50,0x88,0xcb,0xb5, -0x43,0xe6,0x7b,0x8d,0xc6,0x4f,0x4c,0x27,0x4c,0x39,0x23,0xc3,0x23,0x88,0xc0,0x0d, -0xc3,0x2b,0x51,0x39,0xb5,0x55,0x56,0x5a,0x25,0x27,0xaa,0x90,0x50,0x3b,0xe9,0x4f, -0x0f,0x3d,0xd6,0xe7,0xda,0x3f,0x32,0x51,0xb8,0x32,0xee,0x92,0xd2,0x5a,0xab,0x25, -0x5e,0x07,0x04,0xe2,0xf1,0x35,0xc9,0x62,0x41,0x7e,0xcf,0x73,0x9e,0x76,0x21,0xa1, -0xaf,0xba,0x9e,0x09,0x7d,0x98,0x7a,0x01,0x51,0x98,0x82,0x14,0xee,0xa6,0xe4,0x17, -0x9c,0xee,0x0d,0xdb,0x5f,0x46,0xe3,0xc9,0xe2,0xae,0x89,0x44,0x34,0xe2,0x34,0x92, -0x6f,0xad,0x2c,0x90,0x42,0x42,0xed,0x20,0xe9,0x99,0x61,0x07,0x0a,0x77,0x53,0xdf, -0xb0,0xcc,0x5b,0xba,0x31,0xf8,0xfe,0x6c,0x41,0x9e,0xdf,0x82,0x99,0xd8,0x3f,0xeb, -0x79,0x70,0x3a,0x91,0x4f,0x16,0x49,0x64,0x3a,0xa5,0xb9,0xe1,0x5b,0xa2,0xc7,0x42, -0x48,0xc8,0xb3,0x9e,0x47,0xf5,0x42,0x9d,0x42,0x48,0xe2,0xc5,0xf1,0xaf,0xd1,0x7b, -0x7c,0x7e,0xec,0xc8,0x42,0x49,0xc6,0x6d,0xa6,0x9f,0xdc,0x4b,0xeb,0xab,0x74,0x5d, -0x9d,0x60,0x3c,0xde,0x8e,0xdd,0x9a,0x40,0xeb,0xbc,0x5d,0x57,0xd1,0xfa,0x00,0x4e, -0x99,0x6b,0x84,0x84,0x84,0xaa,0xe9,0xd7,0x3a,0x1e,0x7f,0x4f,0x2b,0x29,0x44,0xe2, -0x23,0x83,0xc6,0xc7,0xa9,0x8d,0xd4,0x4f,0xf5,0xd1,0xa1,0x2f,0x8e,0x2d,0x65,0x92, -0x46,0x1f,0xe2,0x86,0x31,0xa6,0x06,0xad,0xd9,0x30,0x1a,0xbf,0xae,0x11,0x69,0xee, -0x9d,0xb8,0xdc,0x19,0x1e,0xe9,0xfc,0xd1,0x6f,0xbc,0x2e,0xa6,0xe1,0x0b,0x09,0x79, -0x55,0xe7,0x61,0xd4,0x4a,0x8a,0x4b,0xf7,0xe4,0xe3,0xd4,0x8f,0xc7,0xe5,0x17,0x4e, -0x1c,0xba,0x83,0xff,0xb7,0x80,0xda,0x42,0x1f,0xdf,0xfb,0xe4,0x1e,0xe9,0xc9,0xdf, -0x50,0xf1,0x38,0x99,0x57,0xf5,0x7e,0xfc,0x0d,0xf5,0xbc,0x69,0xbd,0xc6,0xd1,0x50, -0xaa,0x6f,0x2a,0xf1,0xc5,0xd1,0x7f,0x7b,0xe6,0x7c,0xc7,0xd7,0x1c,0x5e,0x4b,0x48, -0x48,0xc8,0x59,0x7f,0xa0,0xb7,0x94,0x22,0x16,0xa7,0xc6,0x5f,0x3a,0xfa,0x2f,0x4f, -0xc1,0xb9,0x4a,0xb8,0xcf,0xf0,0x13,0xca,0xe1,0x27,0x2a,0x59,0x15,0xf0,0x5c,0x1c, -0x73,0x38,0x55,0x1c,0xa5,0x51,0xe8,0xef,0x1d,0x4c,0x0e,0xe3,0x4c,0xfc,0xa8,0x44, -0x87,0x0f,0xf6,0xbd,0x29,0x68,0x14,0x12,0xe2,0xd0,0xaf,0x75,0x74,0x9f,0xd9,0x4d, -0x7d,0xeb,0xf8,0xc3,0x5f,0xff,0x9d,0x5f,0xb2,0xff,0xf7,0xd6,0x44,0x5a,0x42,0x2d, -0xa2,0x8f,0xef,0xe1,0x76,0x98,0x58,0x91,0xac,0x1a,0x8e,0xfd,0x10,0x39,0x64,0x41, -0xef,0xd5,0xbf,0x12,0x7a,0xfd,0xf0,0x8a,0x9e,0x89,0x9f,0x94,0x95,0xe3,0x1b,0xc7, -0x3f,0x14,0x34,0x0a,0x09,0x71,0xa8,0x23,0xf4,0x2f,0x4f,0xdd,0xa9,0xf8,0xdf,0x73, -0xf1,0x54,0x1e,0x47,0xa6,0xb8,0x7e,0xc8,0xa2,0x50,0xec,0x87,0xd7,0xf5,0x11,0xa7, -0x4b,0x99,0xf7,0x3a,0x9e,0x1f,0xc6,0x59,0xf8,0x19,0x85,0xb8,0x5c,0xd7,0x68,0xdc, -0x38,0x9e,0x1c,0x7e,0xa9,0x4f,0x0c,0x74,0x13,0x12,0xf2,0xa7,0x63,0xe1,0xb5,0x4c, -0x49,0x9e,0xdf,0x42,0x35,0xc4,0x5d,0x53,0xab,0x0c,0xf1,0x43,0x5c,0x6b,0x3c,0x75, -0x65,0x3e,0x81,0xe9,0x63,0x04,0xae,0x00,0x16,0x77,0xb5,0xdb,0xbf,0x2e,0x9a,0x6f, -0x84,0x84,0x7c,0xaa,0x73,0x01,0xd7,0x10,0x1f,0xdf,0xfb,0xcd,0xcd,0xbf,0xf9,0x0f, -0xec,0x76,0xe4,0x87,0xd8,0x23,0xf5,0x76,0xd4,0xad,0x7f,0xff,0xa3,0x53,0x89,0x79, -0x47,0x0a,0x91,0x1f,0xca,0x87,0xdd,0x46,0xe6,0x08,0x09,0x09,0x55,0xd6,0xc0,0xd9, -0xb4,0x14,0x2b,0xee,0xde,0xfb,0x44,0xfd,0xcd,0xf4,0xca,0xf1,0x0b,0x74,0xbc,0xe9, -0x68,0x7c,0x43,0x7d,0xfa,0xfe,0xe3,0x7b,0xa8,0x20,0x4a,0xff,0x5b,0xf1,0xc7,0xe3, -0xc9,0x81,0x29,0x94,0x1b,0x43,0x5f,0xef,0x09,0x97,0x95,0xe1,0xeb,0x1a,0x9b,0x3f, -0x3b,0x54,0xed,0x15,0x84,0x84,0x84,0xdc,0x74,0x7f,0x68,0x52,0x42,0x35,0xc4,0xdd, -0xd5,0x8d,0xe3,0xa8,0x77,0x7f,0xf6,0x28,0x6e,0x73,0x39,0x17,0xdf,0xbd,0xf7,0xf4, -0xfd,0xee,0x7f,0xd4,0x37,0xed,0xef,0xf0,0xfd,0x43,0x05,0xb5,0x4b,0xed,0xfa,0xa2, -0xaf,0xdc,0x17,0xed,0xc7,0x25,0x39,0x90,0x1c,0x90,0xfb,0x78,0x57,0x11,0x16,0x12, -0x12,0xaa,0xa4,0x77,0x63,0x7b,0xb9,0x92,0xf2,0x0f,0xf9,0x8d,0xf1,0xdd,0x71,0x3c, -0xce,0xe6,0x79,0xbd,0xa6,0x77,0x73,0xe8,0xd4,0xd6,0xbc,0x31,0x57,0x7f,0x43,0x1f, -0x65,0xf3,0xf8,0xde,0xd4,0xf2,0xeb,0x4f,0x2c,0x3f,0xb1,0xdc,0xbd,0xdc,0x2d,0x6b, -0x45,0xd5,0xca,0x0f,0x7f,0xb9,0xd9,0xc7,0x2f,0x24,0xb4,0x3f,0x74,0x72,0x31,0x2b, -0xfd,0x38,0xb5,0x32,0x0c,0xe7,0x61,0xfc,0xae,0x46,0xe2,0x81,0xb3,0xd7,0x66,0x8f, -0x2c,0xa0,0x4c,0x52,0x89,0x7c,0x5a,0x2a,0xc8,0xb1,0xcd,0xa9,0xe2,0xb7,0x96,0xff, -0xec,0x85,0xa3,0xdf,0x78,0xa9,0xeb,0xa5,0xae,0xd9,0xee,0x9f,0x1f,0xba,0xdf,0xec, -0x43,0x17,0x12,0xda,0x37,0x7a,0x6b,0xf6,0x8b,0xc5,0xe8,0x81,0x95,0xe3,0x8c,0xc3, -0xc7,0xa9,0x8f,0x2d,0x19,0x11,0x8f,0x85,0x3f,0xeb,0x79,0x63,0x30,0x3c,0xf2,0xe0, -0xf4,0xdf,0x4e,0x8c,0xff,0xc6,0x89,0x43,0x07,0x0e,0xfd,0x73,0x73,0x0e,0x56,0x48, -0x68,0x9f,0xea,0xfc,0xc4,0xe4,0x2b,0xe5,0x27,0xe6,0x87,0x77,0xc7,0xc9,0x28,0xf0, -0x47,0xc6,0xd8,0x53,0x21,0x21,0xa1,0x46,0x69,0x34,0xfe,0xff,0xfe,0x4b,0xf9,0x89, -0xa9,0x04,0xa9,0x1f,0x3e,0x72,0xf0,0x43,0x21,0x21,0xa1,0xfa,0xea,0x58,0x78,0xe2, -0xa8,0xfa,0x8d,0xe4,0xc0,0xc6,0x38,0x99,0x8f,0xf1,0x58,0xf8,0xa1,0x90,0x50,0xc3, -0xf5,0xf3,0x5f,0x57,0xbb,0x62,0xfd,0x2b,0x7a,0x1e,0xb7,0xc7,0xc2,0x0f,0x85,0x84, -0x9a,0xa2,0x37,0x9f,0x52,0xfb,0xa2,0x4f,0xcf,0x0f,0x3f,0x4a,0x61,0x12,0xbb,0x27, -0xaf,0x09,0x0e,0x85,0x84,0x1a,0xae,0x9f,0x3d,0x13,0x7b,0x7a,0x3e,0xb1,0x4b,0x38, -0x3c,0xf3,0x96,0x18,0x21,0x23,0x24,0xd4,0x04,0x1d,0xec,0x3e,0x35,0xb0,0x3b,0x4e, -0xfc,0x50,0x70,0x28,0x24,0xd4,0x1c,0xfd,0xdd,0xa1,0xdd,0xf1,0xee,0x49,0x94,0x41, -0xa3,0xfb,0xcc,0x1f,0x09,0x0e,0x85,0x84,0x9a,0xa4,0x0b,0x87,0x76,0x53,0x28,0xa3, -0x54,0xf7,0x99,0xc3,0x82,0x43,0x21,0xa1,0xa6,0xe9,0x0f,0x7f,0xe9,0xe2,0xf8,0xf0, -0x99,0xa7,0x05,0x87,0x42,0x42,0x4d,0x55,0x47,0x68,0xf6,0xe8,0xb0,0xe0,0x50,0x48, -0xa8,0xed,0xf5,0xff,0x01,0xd1,0x0a,0xff,0xc9,0xa6,0xee,0x01,0x00}; -#endif diff --git a/lib/zlib/deflate.c b/lib/zlib/deflate.c index 63473359e456ee1460a6a445020bc9f4100833d3..4549f4dc12a0030e74d99c77b3f6d9b885342ff0 100644 --- a/lib/zlib/deflate.c +++ b/lib/zlib/deflate.c @@ -223,11 +223,6 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits, memLevel, strategy, int wrap = 1; static const char my_version[] = ZLIB_VERSION; - ushf *overlay; - /* We overlay pending_buf and d_buf+l_buf. This works since the average - * output size for (length,distance) codes is <= 24 bits. - */ - if (version == Z_NULL || version[0] != my_version[0] || stream_size != sizeof(z_stream)) { return Z_VERSION_ERROR; @@ -287,9 +282,47 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits, memLevel, strategy, s->lit_bufsize = 1 << (memLevel + 6); /* 16K elements by default */ - overlay = (ushf *) ZALLOC(strm, s->lit_bufsize, sizeof(ush)+2); - s->pending_buf = (uchf *) overlay; - s->pending_buf_size = (ulg)s->lit_bufsize * (sizeof(ush)+2L); + /* We overlay pending_buf and sym_buf. This works since the average size + * for length/distance pairs over any compressed block is assured to be 31 + * bits or less. + * + * Analysis: The longest fixed codes are a length code of 8 bits plus 5 + * extra bits, for lengths 131 to 257. The longest fixed distance codes are + * 5 bits plus 13 extra bits, for distances 16385 to 32768. The longest + * possible fixed-codes length/distance pair is then 31 bits total. + * + * sym_buf starts one-fourth of the way into pending_buf. So there are + * three bytes in sym_buf for every four bytes in pending_buf. Each symbol + * in sym_buf is three bytes -- two for the distance and one for the + * literal/length. As each symbol is consumed, the pointer to the next + * sym_buf value to read moves forward three bytes. From that symbol, up to + * 31 bits are written to pending_buf. The closest the written pending_buf + * bits gets to the next sym_buf symbol to read is just before the last + * code is written. At that time, 31*(n-2) bits have been written, just + * after 24*(n-2) bits have been consumed from sym_buf. sym_buf starts at + * 8*n bits into pending_buf. (Note that the symbol buffer fills when n-1 + * symbols are written.) The closest the writing gets to what is unread is + * then n+14 bits. Here n is lit_bufsize, which is 16384 by default, and + * can range from 128 to 32768. + * + * Therefore, at a minimum, there are 142 bits of space between what is + * written and what is read in the overlain buffers, so the symbols cannot + * be overwritten by the compressed data. That space is actually 139 bits, + * due to the three-bit fixed-code block header. + * + * That covers the case where either Z_FIXED is specified, forcing fixed + * codes, or when the use of fixed codes is chosen, because that choice + * results in a smaller compressed block than dynamic codes. That latter + * condition then assures that the above analysis also covers all dynamic + * blocks. A dynamic-code block will only be chosen to be emitted if it has + * fewer bits than a fixed-code block would for the same set of symbols. + * Therefore its average symbol length is assured to be less than 31. So + * the compressed data for a dynamic block also cannot overwrite the + * symbols from which it is being constructed. + */ + + s->pending_buf = (uchf *) ZALLOC(strm, s->lit_bufsize, 4); + s->pending_buf_size = (ulg)s->lit_bufsize * 4; if (s->window == Z_NULL || s->prev == Z_NULL || s->head == Z_NULL || s->pending_buf == Z_NULL) { @@ -298,8 +331,12 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits, memLevel, strategy, deflateEnd (strm); return Z_MEM_ERROR; } - s->d_buf = overlay + s->lit_bufsize/sizeof(ush); - s->l_buf = s->pending_buf + (1+sizeof(ush))*s->lit_bufsize; + s->sym_buf = s->pending_buf + s->lit_bufsize; + s->sym_end = (s->lit_bufsize - 1) * 3; + /* We avoid equality with lit_bufsize*3 because of wraparound at 64K + * on 16 bit machines and because stored blocks are restricted to + * 64K-1 bytes. + */ s->level = level; s->strategy = strategy; @@ -935,7 +972,6 @@ int ZEXPORT deflateCopy (dest, source) #else deflate_state *ds; deflate_state *ss; - ushf *overlay; if (source == Z_NULL || dest == Z_NULL || source->state == Z_NULL) { @@ -955,8 +991,7 @@ int ZEXPORT deflateCopy (dest, source) ds->window = (Bytef *) ZALLOC(dest, ds->w_size, 2*sizeof(Byte)); ds->prev = (Posf *) ZALLOC(dest, ds->w_size, sizeof(Pos)); ds->head = (Posf *) ZALLOC(dest, ds->hash_size, sizeof(Pos)); - overlay = (ushf *) ZALLOC(dest, ds->lit_bufsize, sizeof(ush)+2); - ds->pending_buf = (uchf *) overlay; + ds->pending_buf = (uchf *) ZALLOC(dest, ds->lit_bufsize, 4); if (ds->window == Z_NULL || ds->prev == Z_NULL || ds->head == Z_NULL || ds->pending_buf == Z_NULL) { @@ -970,8 +1005,7 @@ int ZEXPORT deflateCopy (dest, source) zmemcpy(ds->pending_buf, ss->pending_buf, (uInt)ds->pending_buf_size); ds->pending_out = ds->pending_buf + (ss->pending_out - ss->pending_buf); - ds->d_buf = overlay + ds->lit_bufsize/sizeof(ush); - ds->l_buf = ds->pending_buf + (1+sizeof(ush))*ds->lit_bufsize; + ds->sym_buf = ds->pending_buf + ds->lit_bufsize; ds->l_desc.dyn_tree = ds->dyn_ltree; ds->d_desc.dyn_tree = ds->dyn_dtree; diff --git a/lib/zlib/deflate.h b/lib/zlib/deflate.h index cbf0d1ea5d966e572c4d3ae24d334c1ff1789169..4c53b94af0b01df421b50e67ed529998278be980 100644 --- a/lib/zlib/deflate.h +++ b/lib/zlib/deflate.h @@ -211,7 +211,7 @@ typedef struct internal_state { /* Depth of each subtree used as tie breaker for trees of equal frequency */ - uchf *l_buf; /* buffer for literals or lengths */ + uchf *sym_buf; /* buffer for distances and literals/lengths */ uInt lit_bufsize; /* Size of match buffer for literals/lengths. There are 4 reasons for @@ -233,13 +233,8 @@ typedef struct internal_state { * - I can't count above 4 */ - uInt last_lit; /* running index in l_buf */ - - ushf *d_buf; - /* Buffer for distances. To simplify the code, d_buf and l_buf have - * the same number of elements. To use different lengths, an extra flag - * array would be necessary. - */ + uInt sym_next; /* running index in sym_buf */ + uInt sym_end; /* symbol table full when sym_next reaches this */ ulg opt_len; /* bit length of current block with optimal trees */ ulg static_len; /* bit length of current block with static trees */ @@ -318,20 +313,22 @@ void ZLIB_INTERNAL _tr_stored_block OF((deflate_state *s, charf *buf, # define _tr_tally_lit(s, c, flush) \ { uch cc = (c); \ - s->d_buf[s->last_lit] = 0; \ - s->l_buf[s->last_lit++] = cc; \ + s->sym_buf[s->sym_next++] = 0; \ + s->sym_buf[s->sym_next++] = 0; \ + s->sym_buf[s->sym_next++] = cc; \ s->dyn_ltree[cc].Freq++; \ - flush = (s->last_lit == s->lit_bufsize-1); \ + flush = (s->sym_next == s->sym_end); \ } # define _tr_tally_dist(s, distance, length, flush) \ { uch len = (length); \ ush dist = (distance); \ - s->d_buf[s->last_lit] = dist; \ - s->l_buf[s->last_lit++] = len; \ + s->sym_buf[s->sym_next++] = dist; \ + s->sym_buf[s->sym_next++] = dist >> 8; \ + s->sym_buf[s->sym_next++] = len; \ dist--; \ s->dyn_ltree[_length_code[len]+LITERALS+1].Freq++; \ s->dyn_dtree[d_code(dist)].Freq++; \ - flush = (s->last_lit == s->lit_bufsize-1); \ + flush = (s->sym_next == s->sym_end); \ } #else # define _tr_tally_lit(s, c, flush) flush = _tr_tally(s, 0, c) diff --git a/lib/zlib/trees.c b/lib/zlib/trees.c index 700c62f6d7b9974a1e326edef6577481d3f73dde..970bc5dbc64e2caefcae4ad4adc2d370381b71a9 100644 --- a/lib/zlib/trees.c +++ b/lib/zlib/trees.c @@ -425,7 +425,7 @@ local void init_block(s) s->dyn_ltree[END_BLOCK].Freq = 1; s->opt_len = s->static_len = 0L; - s->last_lit = s->matches = 0; + s->sym_next = s->matches = 0; } #define SMALLEST 1 @@ -962,7 +962,7 @@ void ZLIB_INTERNAL _tr_flush_block(s, buf, stored_len, last) Tracev((stderr, "\nopt %lu(%lu) stat %lu(%lu) stored %lu lit %u ", opt_lenb, s->opt_len, static_lenb, s->static_len, stored_len, - s->last_lit)); + s->sym_next / 3)); if (static_lenb <= opt_lenb) opt_lenb = static_lenb; @@ -1029,8 +1029,9 @@ int ZLIB_INTERNAL _tr_tally (s, dist, lc) unsigned dist; /* distance of matched string */ unsigned lc; /* match length-MIN_MATCH or unmatched char (if dist==0) */ { - s->d_buf[s->last_lit] = (ush)dist; - s->l_buf[s->last_lit++] = (uch)lc; + s->sym_buf[s->sym_next++] = dist; + s->sym_buf[s->sym_next++] = dist >> 8; + s->sym_buf[s->sym_next++] = lc; if (dist == 0) { /* lc is the unmatched char */ s->dyn_ltree[lc].Freq++; @@ -1045,30 +1046,7 @@ int ZLIB_INTERNAL _tr_tally (s, dist, lc) s->dyn_ltree[_length_code[lc]+LITERALS+1].Freq++; s->dyn_dtree[d_code(dist)].Freq++; } - -#ifdef TRUNCATE_BLOCK - /* Try to guess if it is profitable to stop the current block here */ - if ((s->last_lit & 0x1fff) == 0 && s->level > 2) { - /* Compute an upper bound for the compressed length */ - ulg out_length = (ulg)s->last_lit*8L; - ulg in_length = (ulg)((long)s->strstart - s->block_start); - int dcode; - for (dcode = 0; dcode < D_CODES; dcode++) { - out_length += (ulg)s->dyn_dtree[dcode].Freq * - (5L+extra_dbits[dcode]); - } - out_length >>= 3; - Tracev((stderr,"\nlast_lit %u, in %ld, out ~%ld(%ld%%) ", - s->last_lit, in_length, out_length, - 100L - out_length*100L/in_length)); - if (s->matches < s->last_lit/2 && out_length < in_length/2) return 1; - } -#endif - return (s->last_lit == s->lit_bufsize-1); - /* We avoid equality with lit_bufsize because of wraparound at 64K - * on 16 bit machines and because stored blocks are restricted to - * 64K-1 bytes. - */ + return (s->sym_next == s->sym_end); } /* =========================================================================== @@ -1081,13 +1059,14 @@ local void compress_block(s, ltree, dtree) { unsigned dist; /* distance of matched string */ int lc; /* match length or unmatched char (if dist == 0) */ - unsigned lx = 0; /* running index in l_buf */ + unsigned sx = 0; /* running index in sym_buf */ unsigned code; /* the code to send */ int extra; /* number of extra bits to send */ - if (s->last_lit != 0) do { - dist = s->d_buf[lx]; - lc = s->l_buf[lx++]; + if (s->sym_next != 0) do { + dist = s->sym_buf[sx++] & 0xff; + dist += (unsigned)(s->sym_buf[sx++] & 0xff) << 8; + lc = s->sym_buf[sx++]; if (dist == 0) { send_code(s, lc, ltree); /* send a literal byte */ Tracecv(isgraph(lc), (stderr," '%c' ", lc)); @@ -1112,11 +1091,10 @@ local void compress_block(s, ltree, dtree) } } /* literal or match pair ? */ - /* Check that the overlay between pending_buf and d_buf+l_buf is ok: */ - Assert((uInt)(s->pending) < s->lit_bufsize + 2*lx, - "pendingBuf overflow"); + /* Check that the overlay between pending_buf and sym_buf is ok: */ + Assert(s->pending < s->lit_bufsize + sx, "pendingBuf overflow"); - } while (lx < s->last_lit); + } while (sx < s->sym_next); send_code(s, END_BLOCK, ltree); s->last_eob_len = ltree[END_BLOCK].Len; diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c index 9ff55a02fb23c8a7cadeaa77e974019723d2e65e..3bf4351c847d3db13688a1e73f4bba0713f58dd8 100644 --- a/net/dsa-uclass.c +++ b/net/dsa-uclass.c @@ -477,8 +477,10 @@ static int dsa_pre_probe(struct udevice *dev) return -ENODEV; } - uclass_find_device_by_ofnode(UCLASS_ETH, pdata->master_node, - &priv->master_dev); + err = uclass_get_device_by_ofnode(UCLASS_ETH, pdata->master_node, + &priv->master_dev); + if (err) + return err; /* Simulate a probing event for the CPU port */ if (ops->port_probe) { diff --git a/net/eth-uclass.c b/net/eth-uclass.c index bcefc54ded891df8e3adb3e808059c3f484a5fd2..0f6b45b002c0be52ad15cd08c064d960ed475dd1 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -507,17 +508,21 @@ static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN]) { #if CONFIG_IS_ENABLED(OF_CONTROL) const uint8_t *p; + struct nvmem_cell mac_cell; p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN); if (!p) p = dev_read_u8_array_ptr(dev, "local-mac-address", ARP_HLEN); - if (!p) - return false; + if (p) { + memcpy(mac, p, ARP_HLEN); + return true; + } - memcpy(mac, p, ARP_HLEN); + if (nvmem_cell_get_by_name(dev, "mac-address", &mac_cell)) + return false; - return true; + return !nvmem_cell_read(&mac_cell, mac, ARP_HLEN); #else return false; #endif diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 3db2550085a1b45a338b837a35ee879a6090539d..c0a5bb9addc58171fd5d6fc146917b5acfdcddf0 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -567,6 +567,11 @@ cmd_xzmisc = (cat $(filter-out FORCE,$^) | \ # Additional commands for U-Boot # +# bin2c +# --------------------------------------------------------------------------- +quiet_cmd_bin2c = BIN2C $@ + cmd_bin2c = $(objtree)/scripts/bin2c $2 < $< > $@ + # mkimage # --------------------------------------------------------------------------- MKIMAGEOUTPUT ?= /dev/null diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index f047d4e09415738333e457dc2e7c26148d0196d8..1cfb8115e3100825da35b150dbf089829579376a 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -194,7 +194,7 @@ LDPPFLAGS += \ # Turn various CONFIG symbols into IMAGE symbols for easy reuse of # the scripts between SPL, TPL and VPL. -ifneq ($(CONFIG_$(SPL_TPL_)MAX_SIZE),) +ifneq ($(CONFIG_$(SPL_TPL_)MAX_SIZE),0x0) LDPPFLAGS += -DIMAGE_MAX_SIZE=$(CONFIG_$(SPL_TPL_)MAX_SIZE) endif ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),) @@ -253,7 +253,7 @@ endif INPUTS-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).sym -ifdef CONFIG_SAMSUNG +ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),) INPUTS-y += $(obj)/$(BOARD)-spl.bin endif @@ -367,8 +367,8 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) &: $(obj)/$(SPL_BIN).dtb @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata) $(call if_changed,dtoc) -ifdef CONFIG_SAMSUNG -ifdef CONFIG_VAR_SIZE_SPL +ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),) +ifeq ($(CONFIG_EXYNOS5420),y) VAR_SIZE_PARAM = --vs else VAR_SIZE_PARAM = diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c61df4fb1c9b1e946aef5ac4e5ca018ac43293c7..efc2f3bcf71ee2db4cf65e8ba5f9b4333dbab721 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,18 +1,6 @@ CONFIG_ARM_GIC_BASE_ADDRESS CONFIG_AUTO_ZRELADDR CONFIG_BOARDDIR -CONFIG_BOOTSCRIPT_ADDR -CONFIG_BOOTSCRIPT_COPY_RAM -CONFIG_BOOTSCRIPT_HDR_ADDR -CONFIG_BS_ADDR_DEVICE -CONFIG_BS_ADDR_RAM -CONFIG_BS_COPY_CMD -CONFIG_BS_COPY_ENV -CONFIG_BS_HDR_ADDR_DEVICE -CONFIG_BS_HDR_ADDR_RAM -CONFIG_BS_HDR_SIZE -CONFIG_BS_SIZE -CONFIG_CHAIN_BOOT_CMD CONFIG_DEFAULT CONFIG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC @@ -24,30 +12,9 @@ CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_DEBUG CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT -CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR -CONFIG_DSP_CLUSTER_START -CONFIG_DWC_AHSATA_BASE_ADDR -CONFIG_DWC_AHSATA_PORT_ID -CONFIG_DW_ALTDESCRIPTOR -CONFIG_DW_GMAC_DEFAULT_DMA_PBL -CONFIG_DW_WDT_BASE CONFIG_DW_WDT_CLOCK_KHZ -CONFIG_E1000_NO_NVM -CONFIG_EFLASH_PROTSECTORS -CONFIG_EHCI_DESC_BIG_ENDIAN -CONFIG_EHCI_HCD_INIT_AFTER_RESET -CONFIG_EHCI_MMIO_BIG_ENDIAN -CONFIG_EHCI_MXS_PORT0 -CONFIG_EHCI_MXS_PORT1 -CONFIG_EMU -CONFIG_ENABLE_36BIT_PHYS -CONFIG_ENABLE_MMU CONFIG_ENV_FLAGS_LIST_STATIC CONFIG_ENV_IS_EMBEDDED -CONFIG_ENV_MAX_ENTRIES -CONFIG_ENV_MIN_ENTRIES -CONFIG_ENV_RANGE -CONFIG_ENV_REFLASH CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS CONFIG_ENV_SETTINGS_NAND_V1 CONFIG_ENV_SETTINGS_NAND_V2 @@ -55,39 +22,15 @@ CONFIG_ENV_SETTINGS_V1 CONFIG_ENV_SETTINGS_V2 CONFIG_ENV_SROM_BANK CONFIG_ENV_TOTAL_SIZE -CONFIG_ENV_VERSION -CONFIG_ESBC_ADDR_64BIT -CONFIG_ESBC_HDR_LS -CONFIG_ESDHC_DETECT_QUIRK -CONFIG_ESDHC_HC_BLK_ADDR -CONFIG_ESPRESSO7420 CONFIG_ET1100_BASE CONFIG_ETHBASE -CONFIG_EXTRA_CLOCK -CONFIG_EXTRA_ENV CONFIG_EXTRA_ENV_SETTINGS -CONFIG_EXTRA_ENV_SETTINGS_COMMON -CONFIG_EXYNOS4 -CONFIG_EXYNOS4210 -CONFIG_EXYNOS5 -CONFIG_EXYNOS5250 -CONFIG_EXYNOS5420 -CONFIG_EXYNOS5_DT -CONFIG_EXYNOS_ACE_SHA -CONFIG_EXYNOS_DP -CONFIG_EXYNOS_FB -CONFIG_EXYNOS_MIPI_DSIM -CONFIG_EXYNOS_RELOCATE_CODE_BASE -CONFIG_EXYNOS_SPL -CONFIG_EXYNOS_TMU -CONFIG_FACTORYSET CONFIG_FB_ADDR CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FEC_ENET_DEV CONFIG_FEC_FIXED_SPEED CONFIG_FEC_MXC_PHYADDR -CONFIG_FIXED_SDHCI_ALIGNED_BUFFER CONFIG_FLASH_BR_PRELIM CONFIG_FLASH_CFI_LEGACY CONFIG_FLASH_OR_PRELIM @@ -96,15 +39,12 @@ CONFIG_FLASH_SHOW_PROGRESS CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FM_PLAT_CLK_DIV -CONFIG_FPGA_COUNT -CONFIG_FPGA_STRATIX_V CONFIG_FSL_CADMUS CONFIG_FSL_CORENET CONFIG_FSL_CPLD CONFIG_FSL_DEVICE_DISABLE CONFIG_FSL_DSPI1 CONFIG_FSL_ESDHC_PIN_MUX -CONFIG_FSL_FIXED_MMC_LOCATION CONFIG_FSL_FM_10GEC_REGULAR_NOTATION CONFIG_FSL_IIM CONFIG_FSL_ISBC_KEY_EXT @@ -116,7 +56,6 @@ CONFIG_FSL_PMIC_BUS CONFIG_FSL_PMIC_CLK CONFIG_FSL_PMIC_CS CONFIG_FSL_PMIC_MODE -CONFIG_FSL_SATA_V2 CONFIG_FSL_SDHC_V2_3 CONFIG_FSL_SERDES CONFIG_FSL_SERDES1 @@ -132,10 +71,7 @@ CONFIG_G_DNL_THOR_PRODUCT_NUM CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_UMS_VENDOR_NUM -CONFIG_HAS_FSL_DR_USB -CONFIG_HAS_FSL_MPH_USB CONFIG_HDMI_ENCODER_I2C_ADDR -CONFIG_HETROGENOUS_CLUSTERS CONFIG_HIDE_LOGO_VERSION CONFIG_HIKEY_GPIO CONFIG_HOSTNAME @@ -282,7 +218,6 @@ CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP CONFIG_HSMMC2_8BIT -CONFIG_HUSH_INIT_VAR CONFIG_HWCONFIG CONFIG_HW_ENV_SETTINGS CONFIG_I2C_ENV_EEPROM_BUS @@ -293,7 +228,6 @@ CONFIG_I2C_MVTWSI_BASE0 CONFIG_I2C_MVTWSI_BASE1 CONFIG_I2C_RTC_ADDR CONFIG_ICS307_REFCLK_HZ -CONFIG_IDE_PREINIT CONFIG_IMX CONFIG_IMX6_PWM_PER_CLK CONFIG_IMX_HDMI @@ -307,12 +241,7 @@ CONFIG_IPADDR CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE -CONFIG_IRAM_STACK CONFIG_IRAM_TOP -CONFIG_KEY_REVOCATION -CONFIG_KIRKWOOD_EGIGA_INIT -CONFIG_KIRKWOOD_PCIE_INIT -CONFIG_KIRKWOOD_RGMII_PAD_1V8 CONFIG_KM_BOARD_EXTRA_ENV CONFIG_KM_DEF_ARCH CONFIG_KM_DEF_BOOT_ARGS_CPU @@ -324,7 +253,6 @@ CONFIG_KM_DEF_ENV_CONSTANTS CONFIG_KM_DEF_ENV_CPU CONFIG_KM_DEF_ENV_FLASH_BOOT CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI -CONFIG_KM_DISABLE_PCIE CONFIG_KM_ECC_MODE CONFIG_KM_NEW_ENV CONFIG_KM_ROOTFSSIZE @@ -345,8 +273,6 @@ CONFIG_KSNET_SERDES_SGMII2_BASE CONFIG_KSNET_SERDES_SGMII_BASE CONFIG_L1_INIT_RAM CONFIG_L2_CACHE -CONFIG_LAYERSCAPE_NS_ACCESS -CONFIG_LBA48 CONFIG_LCD_ALIGNMENT CONFIG_LCD_MENU CONFIG_LD9040 @@ -421,35 +347,11 @@ CONFIG_NORBOOT CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN -CONFIG_ORIGEN CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_PALMAS_POWER CONFIG_PCA953X -CONFIG_PCI1 -CONFIG_PCI2 -CONFIG_PCIE1 -CONFIG_PCIE2 -CONFIG_PCIE3 -CONFIG_PCIE4 -CONFIG_PCIE_IMX CONFIG_PCIE_IMX_PERST_GPIO CONFIG_PCIE_IMX_POWER_GPIO -CONFIG_PCI_CLK_FREQ -CONFIG_PCI_CONFIG_HOST_BRIDGE -CONFIG_PCI_GT64120 -CONFIG_PCI_IO_BUS -CONFIG_PCI_IO_PHYS -CONFIG_PCI_IO_SIZE -CONFIG_PCI_MEM_BUS -CONFIG_PCI_MEM_PHYS -CONFIG_PCI_MEM_SIZE -CONFIG_PCI_MSC01 -CONFIG_PCI_OHCI -CONFIG_PCI_PREF_BUS -CONFIG_PCI_PREF_PHYS -CONFIG_PCI_PREF_SIZE -CONFIG_PCI_SCAN_SHOW CONFIG_PEN_ADDR_BIG_ENDIAN CONFIG_PHY_BASE_ADR CONFIG_PHY_ET1011C_TX_CLK_FIX @@ -459,8 +361,6 @@ CONFIG_PHY_IRAM_BASE CONFIG_PL011_CLOCK CONFIG_PL01x_PORTS CONFIG_PM -CONFIG_PMC_BR_PRELIM -CONFIG_PMC_OR_PRELIM CONFIG_PME_PLAT_CLK_DIV CONFIG_POST CONFIG_POSTBOOTMENU @@ -480,20 +380,15 @@ CONFIG_POWER_TPS62362 CONFIG_POWER_TPS65090_EC CONFIG_POWER_TPS65218 CONFIG_POWER_TPS65910 -CONFIG_PPC_CLUSTER_START CONFIG_PPC_SPINTABLE_COMPATIBLE CONFIG_PRAM CONFIG_PSRAM_SCFG -CONFIG_PWM -CONFIG_PXA_VGA CONFIG_QBMAN_CLK_DIV -CONFIG_RAMBOOT_NAND CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RAMDISK_ADDR CONFIG_RD_LVL CONFIG_RESET_VECTOR_ADDRESS -CONFIG_RESTORE_FLASH CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_ROOTPATH CONFIG_RTC_DS1337 @@ -505,34 +400,23 @@ CONFIG_RTC_MC13XXX CONFIG_RTC_MCFRRTC CONFIG_RTC_MXS CONFIG_RTC_PT7C4338 -CONFIG_S5P -CONFIG_S5PC100 -CONFIG_S5PC110 -CONFIG_S5P_PA_SYSRAM CONFIG_SAMA5D3_LCD_BASE -CONFIG_SAMSUNG -CONFIG_SAMSUNG_ONENAND CONFIG_SANDBOX_ARCH CONFIG_SANDBOX_SDL CONFIG_SANDBOX_SPI_MAX_BUS CONFIG_SANDBOX_SPI_MAX_CS CONFIG_SAR2_REG CONFIG_SAR_REG -CONFIG_SATA1 -CONFIG_SATA2 CONFIG_SCIF_A CONFIG_SCSI_DEV_LIST CONFIG_SC_TIMER_CLK CONFIG_SDRAM_OFFSET_FOR_RT -CONFIG_SECBOOT CONFIG_SERIAL_BOOT CONFIG_SERIAL_SOFTWARE_FIFO CONFIG_SERVERIP CONFIG_SETUP_INITRD_TAG -CONFIG_SET_BOOTARGS CONFIG_SET_DFU_ALT_BUF_LEN CONFIG_SH73A0 -CONFIG_SH7751_PCI CONFIG_SH_ETHER_ALIGNE_SIZE CONFIG_SH_ETHER_BASE_ADDR CONFIG_SH_ETHER_CACHE_INVALIDATE @@ -562,43 +446,6 @@ CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET -CONFIG_SPL_BOARD_LOAD_IMAGE -CONFIG_SPL_BOOTROM_SAVE -CONFIG_SPL_BOOT_DEVICE -CONFIG_SPL_BSS_MAX_SIZE -CONFIG_SPL_BSS_START_ADDR -CONFIG_SPL_CMT -CONFIG_SPL_CMT_DEBUG -CONFIG_SPL_COMMON_INIT_DDR -CONFIG_SPL_FLUSH_IMAGE -CONFIG_SPL_FS_LOAD_ARGS_NAME -CONFIG_SPL_FS_LOAD_KERNEL_NAME -CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -CONFIG_SPL_GD_ADDR -CONFIG_SPL_INIT_MINIMAL -CONFIG_SPL_MAX_FOOTPRINT -CONFIG_SPL_MAX_SIZE -CONFIG_SPL_NAND_INIT -CONFIG_SPL_NAND_MINIMAL -CONFIG_SPL_NAND_RAW_ONLY -CONFIG_SPL_NAND_SOFTECC -CONFIG_SPL_PAD_TO -CONFIG_SPL_PBL_PAD -CONFIG_SPL_RELOC_MALLOC_ADDR -CONFIG_SPL_RELOC_MALLOC_SIZE -CONFIG_SPL_RELOC_STACK -CONFIG_SPL_RELOC_TEXT_BASE -CONFIG_SPL_SATA_BOOT_DEVICE -CONFIG_SPL_SIZE -CONFIG_SPL_SKIP_RELOCATE -CONFIG_SPL_SPI_FLASH_MINIMAL -CONFIG_SPL_STACK -CONFIG_SPL_STACK_ADDR -CONFIG_SPL_STACK_SIZE -CONFIG_SPL_START_S_PATH -CONFIG_SPL_TARGET -CONFIG_SRAM_BASE -CONFIG_SRAM_SIZE CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET @@ -614,9 +461,6 @@ CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE CONFIG_STACKBASE CONFIG_STANDALONE_LOAD_ADDR CONFIG_STD_DEVICES_SETTINGS -CONFIG_SYS_64BIT -CONFIG_SYS_64BIT_LBA -CONFIG_SYS_83XX_DDR_USES_CS0 CONFIG_SYS_AMASK0 CONFIG_SYS_AMASK1 CONFIG_SYS_AMASK1_FINAL @@ -630,13 +474,7 @@ CONFIG_SYS_AT91_MAIN_CLOCK CONFIG_SYS_AT91_PLLA CONFIG_SYS_AT91_PLLB CONFIG_SYS_AT91_SLOW_CLOCK -CONFIG_SYS_AUTOLOAD -CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -CONFIG_SYS_AUXCORE_BOOTDATA -CONFIG_SYS_BARGSIZE CONFIG_SYS_BAUDRATE_TABLE -CONFIG_SYS_BFTIC3_BASE -CONFIG_SYS_BFTIC3_SIZE CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_CENA_SIZE CONFIG_SYS_BMAN_CINH_BASE @@ -648,32 +486,21 @@ CONFIG_SYS_BMAN_NUM_PORTALS CONFIG_SYS_BMAN_SP_CENA_SIZE CONFIG_SYS_BMAN_SP_CINH_SIZE CONFIG_SYS_BMAN_SWP_ISDR_REG -CONFIG_SYS_BOOK3E_HV -CONFIG_SYS_BOOTCOUNT_BE -CONFIG_SYS_BOOTCOUNT_LE CONFIG_SYS_BOOTMAPSZ -CONFIG_SYS_BOOTM_LEN -CONFIG_SYS_BOOTPARAMS_LEN CONFIG_SYS_BOOT_BLOCK -CONFIG_SYS_BOOT_RAMDISK_HIGH CONFIG_SYS_CACHE_ACR0 CONFIG_SYS_CACHE_ACR1 CONFIG_SYS_CACHE_ACR2 CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR -CONFIG_SYS_CACHE_STASHING -CONFIG_SYS_CBSIZE CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_CCSRBAR_PHYS_LOW -CONFIG_SYS_CCSR_DO_NOT_RELOCATE -CONFIG_SYS_CFI_FLASH_STATUS_POLL CONFIG_SYS_CLK CONFIG_SYS_CLKTL_CBCDR CONFIG_SYS_CORE_SRAM CONFIG_SYS_CORE_SRAM_SIZE -CONFIG_SYS_CPC_REINIT_F CONFIG_SYS_CPLD_AMASK CONFIG_SYS_CPLD_BASE CONFIG_SYS_CPLD_BASE_PHYS @@ -685,9 +512,6 @@ CONFIG_SYS_CPLD_FTIM1 CONFIG_SYS_CPLD_FTIM2 CONFIG_SYS_CPLD_FTIM3 CONFIG_SYS_CPLD_SIZE -CONFIG_SYS_CPRI -CONFIG_SYS_CPRI_CLK -CONFIG_SYS_CPUSPEED CONFIG_SYS_CPU_CLK CONFIG_SYS_CS0_BASE CONFIG_SYS_CS0_CTRL @@ -696,7 +520,6 @@ CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_CS0_MASK -CONFIG_SYS_CS0_SIZE CONFIG_SYS_CS1_BASE CONFIG_SYS_CS1_CTRL CONFIG_SYS_CS1_FTIM0 @@ -765,19 +588,11 @@ CONFIG_SYS_DA850_DDR2_SDTIMR2 CONFIG_SYS_DA850_PLL0_PLLM CONFIG_SYS_DA850_PLL1_PLLM CONFIG_SYS_DA850_SYSCFG_SUSPSRC -CONFIG_SYS_DAVINCI_I2C_SLAVE -CONFIG_SYS_DAVINCI_I2C_SLAVE1 -CONFIG_SYS_DAVINCI_I2C_SLAVE2 -CONFIG_SYS_DAVINCI_I2C_SPEED -CONFIG_SYS_DAVINCI_I2C_SPEED1 -CONFIG_SYS_DAVINCI_I2C_SPEED2 CONFIG_SYS_DCACHE_INV CONFIG_SYS_DCSRBAR CONFIG_SYS_DCSRBAR_PHYS -CONFIG_SYS_DCSR_COP_CCP_ADDR CONFIG_SYS_DCSR_DCFG_ADDR CONFIG_SYS_DCSR_DCFG_OFFSET -CONFIG_SYS_DCU_ADDR CONFIG_SYS_DDRCDR CONFIG_SYS_DDRCDR_VALUE CONFIG_SYS_DDRUA @@ -800,7 +615,6 @@ CONFIG_SYS_DDR_CS0_CONFIG_2 CONFIG_SYS_DDR_CS1_BNDS CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG_2 -CONFIG_SYS_DDR_DATA_INIT CONFIG_SYS_DDR_INIT_ADDR CONFIG_SYS_DDR_INIT_EXT_ADDR CONFIG_SYS_DDR_INTERVAL @@ -815,7 +629,6 @@ CONFIG_SYS_DDR_MODE_2 CONFIG_SYS_DDR_MODE_2_667 CONFIG_SYS_DDR_MODE_2_800 CONFIG_SYS_DDR_MODE_CONTROL -CONFIG_SYS_DDR_RAW_TIMING CONFIG_SYS_DDR_RCW_1 CONFIG_SYS_DDR_RCW_2 CONFIG_SYS_DDR_SDRAM_BASE @@ -845,10 +658,8 @@ CONFIG_SYS_DDR_ZQ_CONTROL CONFIG_SYS_DEBUG CONFIG_SYS_DEBUG_SERVER_FW_ADDR CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DIALOG_PMIC_I2C_ADDR CONFIG_SYS_DIRECT_FLASH_TFTP -CONFIG_SYS_DISCOVER_PHY CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME @@ -863,16 +674,12 @@ CONFIG_SYS_DV_NOR_BOOT_CFG CONFIG_SYS_EEPROM_BUS_NUM CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE CONFIG_SYS_EEPROM_WREN -CONFIG_SYS_EHCI_USB1_ADDR -CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS CONFIG_SYS_ENET_BD_BASE CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_ETHOC_BASE CONFIG_SYS_ETHOC_BUFFER_ADDR -CONFIG_SYS_ETVPE_CLK CONFIG_SYS_EXCEPTION_VECTORS_HIGH CONFIG_SYS_FAST_CLK -CONFIG_SYS_FDT_BASE CONFIG_SYS_FDT_PAD CONFIG_SYS_FECI2C CONFIG_SYS_FEC_BUF_USE_SRAM @@ -889,7 +696,6 @@ CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE_PHYS_EARLY CONFIG_SYS_FLASH_BR_PRELIM CONFIG_SYS_FLASH_CFI_NONBLOCK -CONFIG_SYS_FLASH_CFI_WIDTH CONFIG_SYS_FLASH_CHECKSUM CONFIG_SYS_FLASH_EMPTY_INFO CONFIG_SYS_FLASH_ERASE_TOUT @@ -977,19 +783,15 @@ CONFIG_SYS_FSL_CORENET_SERDES_ADDR CONFIG_SYS_FSL_CORENET_SERDES_OFFSET CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY CONFIG_SYS_FSL_CORES_PER_CLUSTER -CONFIG_SYS_FSL_CPC CONFIG_SYS_FSL_CPC_ADDR CONFIG_SYS_FSL_CPC_OFFSET CONFIG_SYS_FSL_CSU_ADDR -CONFIG_SYS_FSL_DCFG_ADDR CONFIG_SYS_FSL_DCSR_DDR2_ADDR CONFIG_SYS_FSL_DCSR_DDR3_ADDR -CONFIG_SYS_FSL_DCSR_DDR4_ADDR CONFIG_SYS_FSL_DCSR_DDR_ADDR CONFIG_SYS_FSL_DDR2_ADDR CONFIG_SYS_FSL_DDR3_ADDR CONFIG_SYS_FSL_DDR_ADDR -CONFIG_SYS_FSL_DDR_EMU CONFIG_SYS_FSL_DDR_INTLV_256B CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY @@ -1031,7 +833,6 @@ CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET -CONFIG_SYS_FSL_FMAN_ADDR CONFIG_SYS_FSL_GUTS_ADDR CONFIG_SYS_FSL_IFC_BE CONFIG_SYS_FSL_IFC_LE @@ -1048,7 +849,6 @@ CONFIG_SYS_FSL_OCRAM_SIZE CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS CONFIG_SYS_FSL_PAMU_OFFSET CONFIG_SYS_FSL_PCIE_COMPAT -CONFIG_SYS_FSL_PCI_VER_3_X CONFIG_SYS_FSL_PEX_LUT_BE CONFIG_SYS_FSL_PEX_LUT_LE CONFIG_SYS_FSL_PMIC_I2C_ADDR @@ -1073,16 +873,9 @@ CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SEC_ADDR CONFIG_SYS_FSL_SEC_IDX_OFFSET -CONFIG_SYS_FSL_SEC_MON_BE -CONFIG_SYS_FSL_SEC_MON_LE CONFIG_SYS_FSL_SEC_OFFSET CONFIG_SYS_FSL_SERDES CONFIG_SYS_FSL_SERDES_ADDR -CONFIG_SYS_FSL_SFP_BE -CONFIG_SYS_FSL_SFP_LE -CONFIG_SYS_FSL_SFP_VER_3_0 -CONFIG_SYS_FSL_SFP_VER_3_2 -CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SINGLE_SOURCE_CLK CONFIG_SYS_FSL_SRDS_3 CONFIG_SYS_FSL_SRDS_4 @@ -1094,7 +887,6 @@ CONFIG_SYS_FSL_SRIO_MAX_PORTS CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM CONFIG_SYS_FSL_SRIO_OB_WIN_NUM CONFIG_SYS_FSL_SRIO_OFFSET -CONFIG_SYS_FSL_SRK_LE CONFIG_SYS_FSL_TBCLK_DIV CONFIG_SYS_FSL_TIMER_ADDR CONFIG_SYS_FSL_USB1_PHY_ENABLE @@ -1106,9 +898,6 @@ CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_FSL_WRIOP1_ADDR CONFIG_SYS_FSL_WRIOP1_MDIO1 CONFIG_SYS_FSL_WRIOP1_MDIO2 -CONFIG_SYS_GBL_DATA_OFFSET -CONFIG_SYS_GBL_DATA_SIZE -CONFIG_SYS_GIC400_ADDR CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR @@ -1167,7 +956,6 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_CTRL CONFIG_SYS_INIT_RAM_LOCK CONFIG_SYS_INIT_RAM_SIZE -CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_INTERLAKEN CONFIG_SYS_INT_FLASH_BASE @@ -1202,7 +990,6 @@ CONFIG_SYS_LOADS_BAUD_CHANGE CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LPAE_SDRAM_BASE -CONFIG_SYS_LS1_DDR_BLOCK1_SIZE CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS CONFIG_SYS_LS_MC_DPC_MAX_LENGTH @@ -1213,14 +1000,10 @@ CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET CONFIG_SYS_M41T11_BASE_YEAR CONFIG_SYS_MAIN_PWR_ON -CONFIG_SYS_MALLOC_SIMPLE CONFIG_SYS_MAMR -CONFIG_SYS_MAPLE -CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_MASTER_CLOCK CONFIG_SYS_MATRIX_EBI0CSA_VAL CONFIG_SYS_MATRIX_EBICSA_VAL -CONFIG_SYS_MAXARGS CONFIG_SYS_MAX_FLASH_SECT CONFIG_SYS_MAX_I2C_BUS CONFIG_SYS_MAX_NAND_CHIPS @@ -1232,9 +1015,7 @@ CONFIG_SYS_MCKR CONFIG_SYS_MCKR1_VAL CONFIG_SYS_MCKR2_VAL CONFIG_SYS_MCKR_CSS -CONFIG_SYS_MDCNFG_VAL CONFIG_SYS_MDIO1_OFFSET -CONFIG_SYS_MDREFR_VAL CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE CONFIG_SYS_MEMORY_SIZE @@ -1243,8 +1024,6 @@ CONFIG_SYS_MEM_SIZE CONFIG_SYS_MFD CONFIG_SYS_MHZ CONFIG_SYS_MIPS_TIMER_FREQ -CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR -CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS CONFIG_SYS_MMC_CD_PIN CONFIG_SYS_MMC_CLK_OD CONFIG_SYS_MMC_MAX_BLK_COUNT @@ -1260,9 +1039,6 @@ CONFIG_SYS_MPC83xx_DMA_ADDR CONFIG_SYS_MPC83xx_DMA_OFFSET CONFIG_SYS_MPC83xx_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_OFFSET -CONFIG_SYS_MPC83xx_USB1_ADDR -CONFIG_SYS_MPC83xx_USB1_OFFSET -CONFIG_SYS_MPC85XX_NO_RESETVEC CONFIG_SYS_MPC85xx_DMA CONFIG_SYS_MPC85xx_DMA1_OFFSET CONFIG_SYS_MPC85xx_DMA2_OFFSET @@ -1364,7 +1140,6 @@ CONFIG_SYS_NAND_PAGE_4K CONFIG_SYS_NAND_READY_PIN CONFIG_SYS_NAND_REGS_BASE CONFIG_SYS_NAND_SIZE -CONFIG_SYS_NAND_SPL_KERNEL_OFFS CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_NAND_U_BOOT_RELOC_SP CONFIG_SYS_NAND_U_BOOT_SIZE @@ -1406,7 +1181,6 @@ CONFIG_SYS_NUM_I2C_BUSES CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_OBIR -CONFIG_SYS_OHCI_SWAP_REG_ACCESS CONFIG_SYS_OMAP_ABE_SYSCK CONFIG_SYS_ONENAND_BASE CONFIG_SYS_ONENAND_BLOCK_SIZE @@ -1426,7 +1200,6 @@ CONFIG_SYS_PBDAT CONFIG_SYS_PBDDR CONFIG_SYS_PBI_FLASH_BASE CONFIG_SYS_PBI_FLASH_WINDOW -CONFIG_SYS_PBSIZE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR @@ -1445,31 +1218,21 @@ CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCIE CONFIG_SYS_PCIE1_ADDR -CONFIG_SYS_PCIE1_BASE CONFIG_SYS_PCIE1_CFG_BASE CONFIG_SYS_PCIE1_CFG_SIZE -CONFIG_SYS_PCIE1_IO_BASE CONFIG_SYS_PCIE1_IO_PHYS -CONFIG_SYS_PCIE1_IO_SIZE CONFIG_SYS_PCIE1_IO_VIRT -CONFIG_SYS_PCIE1_MEM_BASE CONFIG_SYS_PCIE1_MEM_PHYS -CONFIG_SYS_PCIE1_MEM_SIZE CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_PHYS_ADDR CONFIG_SYS_PCIE1_PHYS_BASE CONFIG_SYS_PCIE1_VIRT_ADDR CONFIG_SYS_PCIE2_ADDR -CONFIG_SYS_PCIE2_BASE CONFIG_SYS_PCIE2_CFG_BASE CONFIG_SYS_PCIE2_CFG_SIZE -CONFIG_SYS_PCIE2_IO_BASE CONFIG_SYS_PCIE2_IO_PHYS -CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE2_IO_VIRT -CONFIG_SYS_PCIE2_MEM_BASE CONFIG_SYS_PCIE2_MEM_PHYS -CONFIG_SYS_PCIE2_MEM_SIZE CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_PHYS_ADDR CONFIG_SYS_PCIE2_PHYS_BASE @@ -1489,20 +1252,6 @@ CONFIG_SYS_PCIE4_MEM_PHYS CONFIG_SYS_PCIE4_MEM_VIRT CONFIG_SYS_PCIE4_PHYS_ADDR CONFIG_SYS_PCIE_MMAP_SIZE -CONFIG_SYS_PCI_IO_BASE -CONFIG_SYS_PCI_IO_PHYS -CONFIG_SYS_PCI_IO_SIZE -CONFIG_SYS_PCI_MAP_END -CONFIG_SYS_PCI_MAP_START -CONFIG_SYS_PCI_MEM_BASE -CONFIG_SYS_PCI_MEM_PHYS -CONFIG_SYS_PCI_MEM_SIZE -CONFIG_SYS_PCI_MMIO_BASE -CONFIG_SYS_PCI_MMIO_PHYS -CONFIG_SYS_PCI_MMIO_SIZE -CONFIG_SYS_PCI_SLV_MEM_BUS -CONFIG_SYS_PCI_SLV_MEM_LOCAL -CONFIG_SYS_PCI_SLV_MEM_SIZE CONFIG_SYS_PDCNT CONFIG_SYS_PEHLPAR CONFIG_SYS_PIOC_PDR_VAL @@ -1519,12 +1268,9 @@ CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_PMAN -CONFIG_SYS_PMC_BASE -CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PME_CLK CONFIG_SYS_POST_MEMORY CONFIG_SYS_POST_MEM_REGIONS -CONFIG_SYS_PTV CONFIG_SYS_PUAPAR CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_CENA_SIZE @@ -1539,7 +1285,6 @@ CONFIG_SYS_QMAN_SP_CINH_SIZE CONFIG_SYS_QMAN_SWP_ISDR_REG CONFIG_SYS_QRIO_BASE CONFIG_SYS_QRIO_BASE_PHYS -CONFIG_SYS_RAMBOOT CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE @@ -1553,12 +1298,6 @@ CONFIG_SYS_RTC_BUS_NUM CONFIG_SYS_RTC_CNT CONFIG_SYS_RTC_SETUP CONFIG_SYS_SATA -CONFIG_SYS_SATA1 -CONFIG_SYS_SATA1_FLAGS -CONFIG_SYS_SATA1_OFFSET -CONFIG_SYS_SATA2 -CONFIG_SYS_SATA2_FLAGS -CONFIG_SYS_SATA2_OFFSET CONFIG_SYS_SATA_FAT_BOOT_PARTITION CONFIG_SYS_SBFHDR_DATA_OFFSET CONFIG_SYS_SBFHDR_SIZE @@ -1631,7 +1370,6 @@ CONFIG_SYS_SMC0_CYCLE0_VAL CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL -CONFIG_SYS_SPD_BUS_NUM CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE CONFIG_SYS_SPI_BASE @@ -1643,9 +1381,6 @@ CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_SYS_SPI_KERNEL_OFFS CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE -CONFIG_SYS_SPL_ARGS_ADDR -CONFIG_SYS_SPL_LEN -CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_SPR CONFIG_SYS_SRIO @@ -1671,8 +1406,6 @@ CONFIG_SYS_TIMER_COUNTS_DOWN CONFIG_SYS_TIMER_RATE CONFIG_SYS_TMPVIRT CONFIG_SYS_TSEC1_OFFSET -CONFIG_SYS_TSEC2_OFFSET -CONFIG_SYS_TSEC3_OFFSET CONFIG_SYS_TX_ETH_BUFFER CONFIG_SYS_UART2_ALT3_GPIO CONFIG_SYS_UART_PORT @@ -1686,15 +1419,7 @@ CONFIG_SYS_UEC2_PHY_ADDR CONFIG_SYS_UEC2_RX_CLK CONFIG_SYS_UEC2_TX_CLK CONFIG_SYS_UEC2_UCC_NUM -CONFIG_SYS_ULB_CLK -CONFIG_SYS_UNIFY_CACHE -CONFIG_SYS_USB_FAT_BOOT_PARTITION -CONFIG_SYS_USB_OHCI_BOARD_INIT -CONFIG_SYS_USB_OHCI_CPU_INIT -CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS CONFIG_SYS_USB_OHCI_REGS_BASE -CONFIG_SYS_USB_OHCI_SLOT_NAME -CONFIG_SYS_USE_NAND CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT @@ -1726,7 +1451,6 @@ CONFIG_TEGRA_BOARD_STRING CONFIG_TEGRA_CLOCK_SCALING CONFIG_TEGRA_ENABLE_UARTA CONFIG_TEGRA_ENABLE_UARTD -CONFIG_TEGRA_GPU CONFIG_TEGRA_LP0 CONFIG_TEGRA_PMU CONFIG_TEGRA_SLINK_CTRLS @@ -1738,13 +1462,9 @@ CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 CONFIG_TESTPIN_MASK CONFIG_TESTPIN_REG CONFIG_THOR_RESET_OFF -CONFIG_THUNDERX -CONFIG_TIZEN CONFIG_TMU_TIMER -CONFIG_TPL_PAD_TO CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER -CONFIG_TRATS CONFIG_TSEC CONFIG_TSEC1 CONFIG_TSEC1_NAME @@ -1775,24 +1495,13 @@ CONFIG_USBD_PRODUCTID_GSERIAL CONFIG_USBD_PRODUCT_NAME CONFIG_USBD_VENDORID CONFIG_USBNET_DEV_ADDR -CONFIG_USB_ATMEL -CONFIG_USB_ATMEL_CLK_SEL_PLLB -CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_BOOTING CONFIG_USB_DEVICE -CONFIG_USB_EHCI_EXYNOS -CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_EXT2_BOOT CONFIG_USB_FAT_BOOT CONFIG_USB_GADGET_AT91 -CONFIG_USB_GADGET_DWC2_OTG_PHY CONFIG_USB_ISP1301_I2C_ADDR -CONFIG_USB_MAX_CONTROLLER_COUNT -CONFIG_USB_OHCI_LPC32XX -CONFIG_USB_OHCI_NEW CONFIG_USB_TTY -CONFIG_USB_XHCI_EXYNOS -CONFIG_USE_ONENAND_BOARD_INIT CONFIG_U_BOOT_HDR_SIZE CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM @@ -1807,4 +1516,3 @@ CONFIG_X86EMU_RAW_IO CONFIG_X86_MRC_ADDR CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR -CONFIG_XTFPGA diff --git a/test/Kconfig b/test/Kconfig index 7f3447ae5acd1271ffee6881fbd15d3e4ab9b05c..9b283a57ba938161bc738d421d539e3d47dc16b4 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -8,6 +8,7 @@ menuconfig UNIT_TEST config SPL_UNIT_TEST bool "Unit tests in SPL" + depends on SPL # We need to be able to unbind devices for tests to work select SPL_DM_DEVICE_REMOVE help diff --git a/test/Makefile b/test/Makefile index abd605a4351e038b46be0f3485d8e74216e3bd45..1dfd5677440d734c00f1e82224778e6be6ec9b50 100644 --- a/test/Makefile +++ b/test/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o obj-$(CONFIG_$(SPL_)UT_COMPRESSION) += compression.o obj-y += dm/ +obj-$(CONFIG_FUZZ) += fuzz/ obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o obj-$(CONFIG_UT_TIME) += time_ut.o diff --git a/test/bootm.c b/test/bootm.c index 8528982ae116cdc6dcf2fc3656d4df05a7563058..7d03e1e0c6802cd866586c472b97c9d06c7d64d0 100644 --- a/test/bootm.c +++ b/test/bootm.c @@ -83,12 +83,12 @@ static int bootm_test_silent(struct unit_test_state *uts) ut_assertok(env_set("silent_linux", "yes")); ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SILENT)); - ut_asserteq_str("console=", buf); + ut_asserteq_str("console=ttynull", buf); /* Empty buffer should still add the string */ *buf = '\0'; ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SILENT)); - ut_asserteq_str("console=", buf); + ut_asserteq_str("console=ttynull", buf); /* Check nothing happens when do_silent is false */ *buf = '\0'; @@ -97,21 +97,21 @@ static int bootm_test_silent(struct unit_test_state *uts) /* Not enough space */ *buf = '\0'; - ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, 8, BOOTM_CL_SILENT)); + ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, 15, BOOTM_CL_SILENT)); /* Just enough space */ *buf = '\0'; - ut_assertok(bootm_process_cmdline(buf, 9, BOOTM_CL_SILENT)); + ut_assertok(bootm_process_cmdline(buf, 16, BOOTM_CL_SILENT)); /* add at end */ strcpy(buf, "something"); ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SILENT)); - ut_asserteq_str("something console=", buf); + ut_asserteq_str("something console=ttynull", buf); /* change at start */ strcpy(buf, CONSOLE_STR " something"); ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SILENT)); - ut_asserteq_str("console= something", buf); + ut_asserteq_str("console=ttynull something", buf); return 0; } @@ -210,12 +210,12 @@ static int bootm_test_subst_var(struct unit_test_state *uts) { env_set("bootargs", NULL); ut_assertok(bootm_process_cmdline_env(BOOTM_CL_SILENT)); - ut_asserteq_str("console=", env_get("bootargs")); + ut_asserteq_str("console=ttynull", env_get("bootargs")); ut_assertok(env_set("var", "abc")); ut_assertok(env_set("bootargs", "some${var}thing")); ut_assertok(bootm_process_cmdline_env(BOOTM_CL_SILENT)); - ut_asserteq_str("some${var}thing console=", env_get("bootargs")); + ut_asserteq_str("some${var}thing console=ttynull", env_get("bootargs")); return 0; } @@ -227,12 +227,12 @@ static int bootm_test_subst_both(struct unit_test_state *uts) ut_assertok(env_set("silent_linux", "yes")); env_set("bootargs", NULL); ut_assertok(bootm_process_cmdline_env(BOOTM_CL_ALL)); - ut_asserteq_str("console=", env_get("bootargs")); + ut_asserteq_str("console=ttynull", env_get("bootargs")); ut_assertok(env_set("bootargs", "some${var}thing " CONSOLE_STR)); ut_assertok(env_set("var", "1234567890")); ut_assertok(bootm_process_cmdline_env(BOOTM_CL_ALL)); - ut_asserteq_str("some1234567890thing console=", env_get("bootargs")); + ut_asserteq_str("some1234567890thing console=ttynull", env_get("bootargs")); return 0; } diff --git a/test/cmd/Makefile b/test/cmd/Makefile index a59adb1e6d60dd59c97bf1b45de625d3e3a3543f..4b2d7df0d2ef92deae9412467e2c1a69b70c8db1 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o endif obj-y += mem.o obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o +obj-$(CONFIG_CMD_LOADM) += loadm.o obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o obj-$(CONFIG_CMD_PINMUX) += pinmux.o obj-$(CONFIG_CMD_PWM) += pwm.o diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c new file mode 100644 index 0000000000000000000000000000000000000000..41e005ac59236407c3accaacf832e3513a2d9df8 --- /dev/null +++ b/test/cmd/loadm.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for loadm command + * + * Copyright 2022 ARM Limited + * Copyright 2022 Linaro + * + * Authors: + * Rui Miguel Silva + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BUF_SIZE 0x100 + +#define LOADM_TEST(_name, _flags) UNIT_TEST(_name, _flags, loadm_test) + +static int loadm_test_params(struct unit_test_state *uts) +{ + ut_assertok(console_record_reset_enable()); + run_command("loadm", 0); + ut_assert_nextline("loadm - load binary blob from source address to destination address"); + + ut_assertok(console_record_reset_enable()); + run_command("loadm 0x12345678", 0); + ut_assert_nextline("loadm - load binary blob from source address to destination address"); + + ut_assertok(console_record_reset_enable()); + run_command("loadm 0x12345678 0x12345678", 0); + ut_assert_nextline("loadm - load binary blob from source address to destination address"); + + ut_assertok(console_record_reset_enable()); + run_command("loadm 0x12345678 0x12345678 0", 0); + ut_assert_nextline("loadm: can not load zero bytes"); + + return 0; +} +LOADM_TEST(loadm_test_params, UT_TESTF_CONSOLE_REC); + +static int loadm_test_load (struct unit_test_state *uts) +{ + char *buf; + + buf = map_sysmem(0, BUF_SIZE); + memset(buf, '\0', BUF_SIZE); + memset(buf, 0xaa, BUF_SIZE / 2); + + ut_assertok(console_record_reset_enable()); + run_command("loadm 0x0 0x80 0x80", 0); + ut_assert_nextline("loaded bin to memory: size: 128"); + + unmap_sysmem(buf); + + return 0; +} +LOADM_TEST(loadm_test_load, UT_TESTF_CONSOLE_REC); + +int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(loadm_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(loadm_test); + + return cmd_ut_category("loadm", "loadm_test_", tests, n_ents, argc, + argv); +} diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 67a13ee32b8b8917b60cf04f2bd9b0b356485e22..d70b72678aedbbbb19796817aa7af1aa3a27dfb8 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -74,6 +74,9 @@ static struct cmd_tbl cmd_ut_sub[] = { #ifdef CONFIG_CMD_ADDRMAP U_BOOT_CMD_MKENT(addrmap, CONFIG_SYS_MAXARGS, 1, do_ut_addrmap, "", ""), #endif +#ifdef CONFIG_CMD_LOADM + U_BOOT_CMD_MKENT(loadm, CONFIG_SYS_MAXARGS, 1, do_ut_loadm, "", ""), +#endif }; static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc, @@ -155,6 +158,9 @@ static char ut_help_text[] = #endif #ifdef CONFIG_CMD_ADDRMAP "ut addrmap - Very basic test of addrmap command\n" +#endif +#ifdef CONFIG_CMD_LOADM + "ut loadm [test-name]- test of parameters and load memory blob\n" #endif ; #endif /* CONFIG_SYS_LONGHELP */ diff --git a/test/dm/Makefile b/test/dm/Makefile index f0a7c97e3d17e8a76038fb182ea96d312d33413b..52fe178a828d5ae3f637a53d17af921089e63794 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -18,9 +18,13 @@ obj-$(CONFIG_UT_DM) += core.o obj-$(CONFIG_UT_DM) += read.o obj-$(CONFIG_UT_DM) += phys2bus.o ifneq ($(CONFIG_SANDBOX),) -obj-$(CONFIG_ACPIGEN) += acpi.o -obj-$(CONFIG_ACPIGEN) += acpigen.o -obj-$(CONFIG_ACPIGEN) += acpi_dp.o +ifeq ($(CONFIG_ACPIGEN),y) +obj-y += acpi.o +obj-y += acpigen.o +obj-y += acpi_dp.o +obj-(CONFIG_DM_GPIO) += gpio.o +obj-y += irq.o +endif obj-$(CONFIG_ADC) += adc.o obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_AXI) += axi.o @@ -43,11 +47,9 @@ ifneq ($(CONFIG_EFI_PARTITION),) obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o endif obj-$(CONFIG_FIRMWARE) += firmware.o -obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_SOUND) += i2s.o -obj-y += irq.o obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o obj-$(CONFIG_IOMMU) += iommu.o obj-$(CONFIG_LED) += led.o @@ -107,7 +109,11 @@ obj-$(CONFIG_TEE) += tee.o obj-$(CONFIG_TIMER) += timer.o obj-$(CONFIG_DM_USB) += usb.o obj-$(CONFIG_DM_VIDEO) += video.o -obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o +ifeq ($(CONFIG_VIRTIO_SANDBOX),y) +obj-y += virtio.o +obj-$(CONFIG_VIRTIO_RNG) += virtio_device.o +obj-$(CONFIG_VIRTIO_RNG) += virtio_rng.o +endif ifeq ($(CONFIG_WDT_GPIO)$(CONFIG_WDT_SANDBOX),yy) obj-y += wdt.o endif diff --git a/test/dm/core.c b/test/dm/core.c index ebd504427d13bfddae4f17b88c215015fa1bac32..fd4d7569728000645dba206b716b8bb83b5d2bee 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -1275,3 +1275,94 @@ static int dm_test_uclass_find_device(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_uclass_find_device, UT_TESTF_SCAN_FDT); + +/* Test getting information about tags attached to devices */ +static int dm_test_dev_get_attach(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_TEST_FDT, &dev)); + ut_asserteq_str("a-test", dev->name); + + ut_assertnonnull(dev_get_attach_ptr(dev, DM_TAG_PLAT)); + ut_assertnonnull(dev_get_attach_ptr(dev, DM_TAG_PRIV)); + ut_assertnull(dev_get_attach_ptr(dev, DM_TAG_UC_PRIV)); + ut_assertnull(dev_get_attach_ptr(dev, DM_TAG_UC_PLAT)); + ut_assertnull(dev_get_attach_ptr(dev, DM_TAG_PARENT_PLAT)); + ut_assertnull(dev_get_attach_ptr(dev, DM_TAG_PARENT_PRIV)); + + ut_asserteq(sizeof(struct dm_test_pdata), + dev_get_attach_size(dev, DM_TAG_PLAT)); + ut_asserteq(sizeof(struct dm_test_priv), + dev_get_attach_size(dev, DM_TAG_PRIV)); + ut_asserteq(0, dev_get_attach_size(dev, DM_TAG_UC_PRIV)); + ut_asserteq(0, dev_get_attach_size(dev, DM_TAG_UC_PLAT)); + ut_asserteq(0, dev_get_attach_size(dev, DM_TAG_PARENT_PLAT)); + ut_asserteq(0, dev_get_attach_size(dev, DM_TAG_PARENT_PRIV)); + + return 0; +} +DM_TEST(dm_test_dev_get_attach, UT_TESTF_SCAN_FDT); + +/* Test getting information about tags attached to bus devices */ +static int dm_test_dev_get_attach_bus(struct unit_test_state *uts) +{ + struct udevice *dev, *child; + + ut_assertok(uclass_first_device_err(UCLASS_TEST_BUS, &dev)); + ut_asserteq_str("some-bus", dev->name); + + ut_assertnonnull(dev_get_attach_ptr(dev, DM_TAG_PLAT)); + ut_assertnonnull(dev_get_attach_ptr(dev, DM_TAG_PRIV)); + ut_assertnonnull(dev_get_attach_ptr(dev, DM_TAG_UC_PRIV)); + ut_assertnonnull(dev_get_attach_ptr(dev, DM_TAG_UC_PLAT)); + ut_assertnull(dev_get_attach_ptr(dev, DM_TAG_PARENT_PLAT)); + ut_assertnull(dev_get_attach_ptr(dev, DM_TAG_PARENT_PRIV)); + + ut_asserteq(sizeof(struct dm_test_pdata), + dev_get_attach_size(dev, DM_TAG_PLAT)); + ut_asserteq(sizeof(struct dm_test_priv), + dev_get_attach_size(dev, DM_TAG_PRIV)); + ut_asserteq(sizeof(struct dm_test_uclass_priv), + dev_get_attach_size(dev, DM_TAG_UC_PRIV)); + ut_asserteq(sizeof(struct dm_test_uclass_plat), + dev_get_attach_size(dev, DM_TAG_UC_PLAT)); + ut_asserteq(0, dev_get_attach_size(dev, DM_TAG_PARENT_PLAT)); + ut_asserteq(0, dev_get_attach_size(dev, DM_TAG_PARENT_PRIV)); + + /* Now try the child of the bus */ + ut_assertok(device_first_child_err(dev, &child)); + ut_asserteq_str("c-test@5", child->name); + + ut_assertnonnull(dev_get_attach_ptr(child, DM_TAG_PLAT)); + ut_assertnonnull(dev_get_attach_ptr(child, DM_TAG_PRIV)); + ut_assertnull(dev_get_attach_ptr(child, DM_TAG_UC_PRIV)); + ut_assertnull(dev_get_attach_ptr(child, DM_TAG_UC_PLAT)); + ut_assertnonnull(dev_get_attach_ptr(child, DM_TAG_PARENT_PLAT)); + ut_assertnonnull(dev_get_attach_ptr(child, DM_TAG_PARENT_PRIV)); + + ut_asserteq(sizeof(struct dm_test_pdata), + dev_get_attach_size(child, DM_TAG_PLAT)); + ut_asserteq(sizeof(struct dm_test_priv), + dev_get_attach_size(child, DM_TAG_PRIV)); + ut_asserteq(0, dev_get_attach_size(child, DM_TAG_UC_PRIV)); + ut_asserteq(0, dev_get_attach_size(child, DM_TAG_UC_PLAT)); + ut_asserteq(sizeof(struct dm_test_parent_plat), + dev_get_attach_size(child, DM_TAG_PARENT_PLAT)); + ut_asserteq(sizeof(struct dm_test_parent_data), + dev_get_attach_size(child, DM_TAG_PARENT_PRIV)); + + return 0; +} +DM_TEST(dm_test_dev_get_attach_bus, UT_TESTF_SCAN_FDT); + +/* Test getting information about tags attached to bus devices */ +static int dm_test_dev_get_mem(struct unit_test_state *uts) +{ + struct dm_stats stats; + + dm_get_mem(&stats); + + return 0; +} +DM_TEST(dm_test_dev_get_mem, UT_TESTF_SCAN_FDT); diff --git a/test/dm/eth.c b/test/dm/eth.c index e4ee695610646871e1ae48c91c05338f7e40fdd6..5437f9ea4a07492cbb79cbc1f38d7e6fca99b630 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -147,6 +147,35 @@ static int dm_test_eth_act(struct unit_test_state *uts) } DM_TEST(dm_test_eth_act, UT_TESTF_SCAN_FDT); +/* Ensure that all addresses are loaded properly */ +static int dm_test_ethaddr(struct unit_test_state *uts) +{ + static const char *const addr[] = { + "02:00:11:22:33:44", + "02:00:11:22:33:48", /* dsa slave */ + "02:00:11:22:33:45", + "02:00:11:22:33:48", /* dsa master */ + "02:00:11:22:33:46", + "02:00:11:22:33:47", + "02:00:11:22:33:48", /* dsa slave */ + "02:00:11:22:33:49", + }; + int i; + + for (i = 0; i < ARRAY_SIZE(addr); i++) { + char addrname[10]; + + if (i) + snprintf(addrname, sizeof(addrname), "eth%daddr", i + 1); + else + strcpy(addrname, "ethaddr"); + ut_asserteq_str(addr[i], env_get(addrname)); + } + + return 0; +} +DM_TEST(dm_test_ethaddr, UT_TESTF_SCAN_FDT); + /* The asserts include a return on fail; cleanup in the caller */ static int _dm_test_eth_rotate1(struct unit_test_state *uts) { diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index e1de066226cb39bcd3931cdd47e5d76212cb1160..f9e817475959a74b8afb11bff259cb6a28a06792 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -184,7 +184,7 @@ static int dm_test_alias_highest_id(struct unit_test_state *uts) int ret; ret = dev_read_alias_highest_id("ethernet"); - ut_asserteq(5, ret); + ut_asserteq(8, ret); ret = dev_read_alias_highest_id("gpio"); ut_asserteq(3, ret); diff --git a/test/dm/virtio.c b/test/dm/virtio.c index 9a7e658ccebcefc83cbb2382d0ea65c1aa75c587..3e108cdc35d0485f9dd0d501f1e803355a86b298 100644 --- a/test/dm/virtio.c +++ b/test/dm/virtio.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -15,78 +14,6 @@ #include #include -/* Basic test of the virtio uclass */ -static int dm_test_virtio_base(struct unit_test_state *uts) -{ - struct udevice *bus, *dev; - u8 status; - - /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); - ut_assertnonnull(bus); - - /* check the child virtio-blk device is bound */ - ut_assertok(device_find_first_child(bus, &dev)); - ut_assertnonnull(dev); - ut_assertok(strcmp(dev->name, "virtio-blk#0")); - - /* check driver status */ - ut_assertok(virtio_get_status(dev, &status)); - ut_asserteq(VIRTIO_CONFIG_S_ACKNOWLEDGE, status); - - return 0; -} -DM_TEST(dm_test_virtio_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); - -/* Test all of the virtio uclass ops */ -static int dm_test_virtio_all_ops(struct unit_test_state *uts) -{ - struct udevice *bus, *dev; - struct virtio_dev_priv *uc_priv; - uint offset = 0, len = 0, nvqs = 1; - void *buffer = NULL; - u8 status; - u32 counter; - u64 features; - struct virtqueue *vqs[2]; - - /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); - ut_assertnonnull(bus); - - /* check the child virtio-blk device is bound */ - ut_assertok(device_find_first_child(bus, &dev)); - ut_assertnonnull(dev); - - /* - * fake the virtio device probe by filling in uc_priv->vdev - * which is used by virtio_find_vqs/virtio_del_vqs. - */ - uc_priv = dev_get_uclass_priv(bus); - ut_assertnonnull(uc_priv); - uc_priv->vdev = dev; - - /* test virtio_xxx APIs */ - ut_assertok(virtio_get_config(dev, offset, buffer, len)); - ut_assertok(virtio_set_config(dev, offset, buffer, len)); - ut_asserteq(-ENOSYS, virtio_generation(dev, &counter)); - ut_assertok(virtio_set_status(dev, VIRTIO_CONFIG_S_DRIVER_OK)); - ut_assertok(virtio_get_status(dev, &status)); - ut_asserteq(VIRTIO_CONFIG_S_DRIVER_OK, status); - ut_assertok(virtio_reset(dev)); - ut_assertok(virtio_get_status(dev, &status)); - ut_asserteq(0, status); - ut_assertok(virtio_get_features(dev, &features)); - ut_asserteq(VIRTIO_F_VERSION_1, features); - ut_assertok(virtio_set_features(dev)); - ut_assertok(virtio_find_vqs(dev, nvqs, vqs)); - ut_assertok(virtio_del_vqs(dev)); - ut_assertok(virtio_notify(dev, vqs[0])); - - return 0; -} -DM_TEST(dm_test_virtio_all_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); - /* Test of the virtio driver that does not have required driver ops */ static int dm_test_virtio_missing_ops(struct unit_test_state *uts) { @@ -104,29 +31,3 @@ static int dm_test_virtio_missing_ops(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_virtio_missing_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); - -/* Test removal of virtio device driver */ -static int dm_test_virtio_remove(struct unit_test_state *uts) -{ - struct udevice *bus, *dev; - - /* check probe success */ - ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); - ut_assertnonnull(bus); - - /* check the child virtio-blk device is bound */ - ut_assertok(device_find_first_child(bus, &dev)); - ut_assertnonnull(dev); - - /* set driver status to VIRTIO_CONFIG_S_DRIVER_OK */ - ut_assertok(virtio_set_status(dev, VIRTIO_CONFIG_S_DRIVER_OK)); - - /* check the device can be successfully removed */ - dev_or_flags(dev, DM_FLAG_ACTIVATED); - ut_asserteq(-EKEYREJECTED, device_remove(bus, DM_REMOVE_ACTIVE_ALL)); - - ut_asserteq(false, device_active(dev)); - - return 0; -} -DM_TEST(dm_test_virtio_remove, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c new file mode 100644 index 0000000000000000000000000000000000000000..d0195e6bf096fb352eba4d04109bd65bedb77b28 --- /dev/null +++ b/test/dm/virtio_device.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Basic test of the virtio uclass */ +static int dm_test_virtio_base(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + u8 status; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertnonnull(bus); + + /* check the child virtio-rng device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + ut_assertnonnull(dev); + ut_asserteq_str("virtio-rng#0", dev->name); + + /* check driver status */ + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(VIRTIO_CONFIG_S_ACKNOWLEDGE, status); + + /* probe the virtio-rng driver */ + ut_assertok(device_probe(dev)); + + /* check the device was reset and the driver picked up the device */ + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(VIRTIO_CONFIG_S_DRIVER | + VIRTIO_CONFIG_S_DRIVER_OK | + VIRTIO_CONFIG_S_FEATURES_OK, status); + + return 0; +} +DM_TEST(dm_test_virtio_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* Test all of the virtio uclass ops */ +static int dm_test_virtio_all_ops(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + struct virtio_dev_priv *uc_priv; + uint offset = 0, len = 0, nvqs = 1; + void *buffer = NULL; + u8 status; + u32 counter; + u64 features; + struct virtqueue *vqs[2]; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertnonnull(bus); + + /* check the child virtio-rng device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + ut_assertnonnull(dev); + + /* + * fake the virtio device probe by filling in uc_priv->vdev + * which is used by virtio_find_vqs/virtio_del_vqs. + */ + uc_priv = dev_get_uclass_priv(bus); + ut_assertnonnull(uc_priv); + uc_priv->vdev = dev; + + /* test virtio_xxx APIs */ + ut_assertok(virtio_get_config(dev, offset, buffer, len)); + ut_assertok(virtio_set_config(dev, offset, buffer, len)); + ut_asserteq(-ENOSYS, virtio_generation(dev, &counter)); + ut_assertok(virtio_set_status(dev, VIRTIO_CONFIG_S_DRIVER_OK)); + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(VIRTIO_CONFIG_S_DRIVER_OK, status); + ut_assertok(virtio_reset(dev)); + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(0, status); + ut_assertok(virtio_get_features(dev, &features)); + ut_asserteq_64(BIT_ULL(VIRTIO_F_VERSION_1), features); + ut_assertok(virtio_set_features(dev)); + ut_assertok(virtio_find_vqs(dev, nvqs, vqs)); + ut_assertok(virtio_notify(dev, vqs[0])); + ut_assertok(virtio_del_vqs(dev)); + + return 0; +} +DM_TEST(dm_test_virtio_all_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* Test removal of virtio device driver */ +static int dm_test_virtio_remove(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertnonnull(bus); + + /* check the child virtio-rng device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + ut_assertnonnull(dev); + + /* set driver status to VIRTIO_CONFIG_S_DRIVER_OK */ + ut_assertok(virtio_set_status(dev, VIRTIO_CONFIG_S_DRIVER_OK)); + + /* check the device can be successfully removed */ + dev_or_flags(dev, DM_FLAG_ACTIVATED); + ut_asserteq(-EKEYREJECTED, device_remove(bus, DM_REMOVE_ACTIVE_ALL)); + + ut_asserteq(false, device_active(dev)); + + return 0; +} +DM_TEST(dm_test_virtio_remove, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* Test all of the virtio ring */ +static int dm_test_virtio_ring(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + struct virtio_dev_priv *uc_priv; + struct virtqueue *vq; + struct virtio_sg sg[2]; + struct virtio_sg *sgs[2]; + unsigned int len; + u8 buffer[2][32]; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertnonnull(bus); + + /* check the child virtio-blk device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + ut_assertnonnull(dev); + + /* + * fake the virtio device probe by filling in uc_priv->vdev + * which is used by virtio_find_vqs/virtio_del_vqs. + */ + uc_priv = dev_get_uclass_priv(bus); + ut_assertnonnull(uc_priv); + uc_priv->vdev = dev; + + /* prepare the scatter-gather buffer */ + sg[0].addr = buffer[0]; + sg[0].length = sizeof(buffer[0]); + sg[1].addr = buffer[1]; + sg[1].length = sizeof(buffer[1]); + sgs[0] = &sg[0]; + sgs[1] = &sg[1]; + + /* read a buffer and report written size from device */ + ut_assertok(virtio_find_vqs(dev, 1, &vq)); + ut_assertok(virtqueue_add(vq, sgs, 0, 1)); + vq->vring.used->idx = 1; + vq->vring.used->ring[0].id = 0; + vq->vring.used->ring[0].len = 0x53355885; + ut_asserteq_ptr(buffer, virtqueue_get_buf(vq, &len)); + ut_asserteq(0x53355885, len); + ut_assertok(virtio_del_vqs(dev)); + + /* rejects used descriptors that aren't a chain head */ + ut_assertok(virtio_find_vqs(dev, 1, &vq)); + ut_assertok(virtqueue_add(vq, sgs, 0, 2)); + vq->vring.used->idx = 1; + vq->vring.used->ring[0].id = 1; + vq->vring.used->ring[0].len = 0x53355885; + ut_assertnull(virtqueue_get_buf(vq, &len)); + ut_assertok(virtio_del_vqs(dev)); + + /* device changes to descriptor are ignored */ + ut_assertok(virtio_find_vqs(dev, 1, &vq)); + ut_assertok(virtqueue_add(vq, sgs, 0, 1)); + vq->vring.desc[0].addr = cpu_to_virtio64(dev, 0xbadbad11); + vq->vring.desc[0].len = cpu_to_virtio32(dev, 0x11badbad); + vq->vring.desc[0].flags = cpu_to_virtio16(dev, VRING_DESC_F_NEXT); + vq->vring.desc[0].next = cpu_to_virtio16(dev, U16_MAX); + vq->vring.used->idx = 1; + vq->vring.used->ring[0].id = 0; + vq->vring.used->ring[0].len = 6; + ut_asserteq_ptr(buffer, virtqueue_get_buf(vq, &len)); + ut_asserteq(6, len); + ut_assertok(virtio_del_vqs(dev)); + + return 0; +} +DM_TEST(dm_test_virtio_ring, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c new file mode 100644 index 0000000000000000000000000000000000000000..ff5646b4e11331cb3f6a26baaf0606a9ea11c278 --- /dev/null +++ b/test/dm/virtio_rng.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* This is a brittle means of getting access to the virtqueue */ +struct virtio_rng_priv { + struct virtqueue *rng_vq; +}; + +/* Test the virtio-rng driver validates the used size */ +static int dm_test_virtio_rng_check_len(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + struct virtio_rng_priv *priv; + u8 buffer[16]; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + ut_assertnonnull(bus); + + /* check the child virtio-rng device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + ut_assertnonnull(dev); + + /* probe the virtio-rng driver */ + ut_assertok(device_probe(dev)); + + /* simulate the device returning the buffer with too much data */ + priv = dev_get_priv(dev); + priv->rng_vq->vring.used->idx = 1; + priv->rng_vq->vring.used->ring[0].id = 0; + priv->rng_vq->vring.used->ring[0].len = U32_MAX; + + /* check the driver gracefully handles the error */ + ut_asserteq(-EIO, dm_rng_read(dev, buffer, sizeof(buffer))); + + return 0; +} +DM_TEST(dm_test_virtio_rng_check_len, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/test/fuzz/Makefile b/test/fuzz/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..663b79ce80be49c8790f8be3288c0b13ca8c7590 --- /dev/null +++ b/test/fuzz/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2022 Google, Inc. +# Written by Andrew Scull +# + +obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_fuzz.o +obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c new file mode 100644 index 0000000000000000000000000000000000000000..0cc01dc199ca764e00af9b295542c0945dff6d4b --- /dev/null +++ b/test/fuzz/cmd_fuzz.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#include +#include +#include +#include +#include + +static struct fuzz_test *find_fuzz_test(const char *name) +{ + struct fuzz_test *fuzzer = FUZZ_TEST_START(); + size_t count = FUZZ_TEST_COUNT(); + size_t i; + + for (i = 0; i < count; ++i) { + if (strcmp(name, fuzzer->name) == 0) + return fuzzer; + ++fuzzer; + } + + return NULL; +} + +static struct udevice *find_fuzzing_engine(void) +{ + struct udevice *dev; + + if (uclass_first_device(UCLASS_FUZZING_ENGINE, &dev)) + return NULL; + + return dev; +} + +static int do_fuzz(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct fuzz_test *fuzzer; + struct udevice *dev; + + if (argc != 2) + return CMD_RET_USAGE; + + fuzzer = find_fuzz_test(argv[1]); + if (!fuzzer) { + printf("Could not find fuzzer: %s\n", argv[1]); + return 1; + } + + dev = find_fuzzing_engine(); + if (!dev) { + puts("No fuzzing engine available\n"); + return 1; + } + + while (1) { + const uint8_t *data; + size_t size; + + if (dm_fuzzing_engine_get_input(dev, &data, &size)) { + puts("Fuzzing engine failed\n"); + return 1; + } + + fuzzer->func(data, size); + } + + return 1; +} + +#ifdef CONFIG_SYS_LONGHELP +static char fuzz_help_text[] = + "[fuzz-test-name] - execute the named fuzz test\n" + ; +#endif /* CONFIG_SYS_LONGHELP */ + +U_BOOT_CMD( + fuzz, CONFIG_SYS_MAXARGS, 1, do_fuzz, + "fuzz tests", fuzz_help_text +); diff --git a/test/fuzz/virtio.c b/test/fuzz/virtio.c new file mode 100644 index 0000000000000000000000000000000000000000..e5363d5638e49a9ddab12b72b36cb70167d84065 --- /dev/null +++ b/test/fuzz/virtio.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2022 Google, Inc. + * Written by Andrew Scull + */ + +#include +#include +#include +#include +#include + +static int fuzz_vring(const uint8_t *data, size_t size) +{ + struct udevice *bus, *dev; + struct virtio_dev_priv *uc_priv; + struct virtqueue *vq; + struct virtio_sg sg[2]; + struct virtio_sg *sgs[2]; + unsigned int len; + u8 buffer[2][32]; + + /* hackily hardcode vring sizes */ + size_t num = 4; + size_t desc_size = (sizeof(struct vring_desc) * num); + size_t avail_size = (3 + num) * sizeof(u16); + size_t used_size = (3 * sizeof(u16)) + (sizeof(struct vring_used_elem) * num); + + if (size < (desc_size + avail_size + used_size)) + return 0; + + /* check probe success */ + if (uclass_first_device(UCLASS_VIRTIO, &bus) || !bus) + panic("Could not find virtio bus\n"); + + /* check the child virtio-rng device is bound */ + if (device_find_first_child(bus, &dev) || !dev) + panic("Could not find virtio device\n"); + + /* + * fake the virtio device probe by filling in uc_priv->vdev + * which is used by virtio_find_vqs/virtio_del_vqs. + */ + uc_priv = dev_get_uclass_priv(bus); + uc_priv->vdev = dev; + + /* prepare the scatter-gather buffer */ + sg[0].addr = buffer[0]; + sg[0].length = sizeof(buffer[0]); + sg[1].addr = buffer[1]; + sg[1].length = sizeof(buffer[1]); + sgs[0] = &sg[0]; + sgs[1] = &sg[1]; + + if (virtio_find_vqs(dev, 1, &vq)) + panic("Could not find vqs\n"); + if (virtqueue_add(vq, sgs, 0, 1)) + panic("Could not add to virtqueue\n"); + /* Simulate device writing to vring */ + memcpy(vq->vring.desc, data, desc_size); + memcpy(vq->vring.avail, data + desc_size, avail_size); + memcpy(vq->vring.used, data + desc_size + avail_size, used_size); + /* Make sure there is a response */ + if (vq->vring.used->idx == 0) + vq->vring.used->idx = 1; + virtqueue_get_buf(vq, &len); + if (virtio_del_vqs(dev)) + panic("Could not delete vqs\n"); + + return 0; +} +FUZZ_TEST(fuzz_vring, 0); diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py index 8ad277da190b2d85ded09f9adcb0fb8217541ba9..d7e6626d45f1a6e21a3f26c3f14859346d5f0213 100644 --- a/test/py/tests/test_bind.py +++ b/test/py/tests/test_bind.py @@ -1,186 +1,191 @@ # SPDX-License-Identifier: GPL-2.0 # Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. -import os.path -import pytest +""" Test for bind command """ + import re +import pytest def in_tree(response, name, uclass, drv, depth, last_child): - lines = [x.strip() for x in response.splitlines()] - leaf = '' - if depth != 0: - leaf = ' ' + ' ' * (depth - 1) ; - if not last_child: - leaf = leaf + r'\|' - else: - leaf = leaf + '`' - - leaf = leaf + '-- ' + name - line = (r' *{:10.10} *[0-9]* \[ [ +] \] {:20.20} [` |]{}$' - .format(uclass, drv, leaf)) - prog = re.compile(line) - for l in lines: - if prog.match(l): - return True - return False + lines = [x.strip() for x in response.splitlines()] + leaf = '' + if depth != 0: + leaf = ' ' + ' ' * (depth - 1) + if not last_child: + leaf = leaf + r'\|' + else: + leaf = leaf + '`' + + leaf = leaf + '-- ' + name + line = (r' *{:10.10} *[0-9]* \[ [ +] \] {:20.20} [` |]{}$' + .format(uclass, drv, leaf)) + prog = re.compile(line) + for l in lines: + if prog.match(l): + return True + return False @pytest.mark.buildconfigspec('cmd_bind') def test_bind_unbind_with_node(u_boot_console): - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) - assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) - - #bind usb_ether driver (which has no compatible) to usb@1 node. - ##New entry usb_ether should appear in the dm tree - response = u_boot_console.run_command('bind /usb@1 usb_ether') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True) - - #Unbind child #1. No error expected and all devices should be there except for bind-test-child1 - response = u_boot_console.run_command('unbind /bind-test/bind-test-child1') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) - assert 'bind-test-child1' not in tree - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) - - #bind child #1. No error expected and all devices should be there - response = u_boot_console.run_command('bind /bind-test/bind-test-child1 phy_sandbox') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) - assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True) - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, False) - - #Unbind child #2. No error expected and all devices should be there except for bind-test-child2 - response = u_boot_console.run_command('unbind /bind-test/bind-test-child2') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) - assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True) - assert 'bind-test-child2' not in tree - - - #Bind child #2. No error expected and all devices should be there - response = u_boot_console.run_command('bind /bind-test/bind-test-child2 simple_bus') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) - assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) - - #Unbind parent. No error expected. All devices should be removed and unbound - response = u_boot_console.run_command('unbind /bind-test') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert 'bind-test' not in tree - assert 'bind-test-child1' not in tree - assert 'bind-test-child2' not in tree - - #try binding invalid node with valid driver - response = u_boot_console.run_command('bind /not-a-valid-node simple_bus') - assert response != '' - tree = u_boot_console.run_command('dm tree') - assert 'not-a-valid-node' not in tree - - #try binding valid node with invalid driver - response = u_boot_console.run_command('bind /bind-test not_a_driver') - assert response != '' - tree = u_boot_console.run_command('dm tree') - assert 'bind-test' not in tree - - #bind /bind-test. Device should come up as well as its children - response = u_boot_console.run_command('bind /bind-test simple_bus') - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) - assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) - - response = u_boot_console.run_command('unbind /bind-test') - assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) + assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + + #bind usb_ether driver (which has no compatible) to usb@1 node. + ##New entry usb_ether should appear in the dm tree + response = u_boot_console.run_command('bind /usb@1 usb_ether') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True) + + #Unbind child #1. No error expected and all devices should be there except for bind-test-child1 + response = u_boot_console.run_command('unbind /bind-test/bind-test-child1') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) + assert 'bind-test-child1' not in tree + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + + #bind child #1. No error expected and all devices should be there + response = u_boot_console.run_command('bind /bind-test/bind-test-child1 phy_sandbox') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) + assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True) + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, False) + + #Unbind child #2. No error expected and all devices should be there except for bind-test-child2 + response = u_boot_console.run_command('unbind /bind-test/bind-test-child2') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) + assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True) + assert 'bind-test-child2' not in tree + + + #Bind child #2. No error expected and all devices should be there + response = u_boot_console.run_command('bind /bind-test/bind-test-child2 simple_bus') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) + assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + + #Unbind parent. No error expected. All devices should be removed and unbound + response = u_boot_console.run_command('unbind /bind-test') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert 'bind-test' not in tree + assert 'bind-test-child1' not in tree + assert 'bind-test-child2' not in tree + + #try binding invalid node with valid driver + response = u_boot_console.run_command('bind /not-a-valid-node simple_bus') + assert response != '' + tree = u_boot_console.run_command('dm tree') + assert 'not-a-valid-node' not in tree + + #try binding valid node with invalid driver + response = u_boot_console.run_command('bind /bind-test not_a_driver') + assert response != '' + tree = u_boot_console.run_command('dm tree') + assert 'bind-test' not in tree + + #bind /bind-test. Device should come up as well as its children + response = u_boot_console.run_command('bind /bind-test simple_bus') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True) + assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + + response = u_boot_console.run_command('unbind /bind-test') + assert response == '' def get_next_line(tree, name): - treelines = [x.strip() for x in tree.splitlines() if x.strip()] - child_line = '' - for idx, line in enumerate(treelines): - if ('-- ' + name) in line: - try: - child_line = treelines[idx+1] - except: - pass - break - return child_line + treelines = [x.strip() for x in tree.splitlines() if x.strip()] + child_line = '' + for idx, line in enumerate(treelines): + if '-- ' + name in line: + try: + child_line = treelines[idx+1] + except: + pass + break + return child_line @pytest.mark.buildconfigspec('cmd_bind') def test_bind_unbind_with_uclass(u_boot_console): - #bind /bind-test - response = u_boot_console.run_command('bind /bind-test simple_bus') - assert response == '' - - #make sure bind-test-child2 is there and get its uclass/index pair - tree = u_boot_console.run_command('dm tree') - child2_line = [x.strip() for x in tree.splitlines() if '-- bind-test-child2' in x] - assert len(child2_line) == 1 - - child2_uclass = child2_line[0].split()[0] - child2_index = int(child2_line[0].split()[1]) - - #bind simple_bus as a child of bind-test-child2 - response = u_boot_console.run_command('bind {} {} simple_bus'.format(child2_uclass, child2_index)) - - #check that the child is there and its uclass/index pair is right - tree = u_boot_console.run_command('dm tree') - - child_of_child2_line = get_next_line(tree, 'bind-test-child2') - assert child_of_child2_line - child_of_child2_index = int(child_of_child2_line.split()[1]) - assert in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True) - assert child_of_child2_index == child2_index + 1 - - #unbind the child and check it has been removed - response = u_boot_console.run_command('unbind simple_bus {}'.format(child_of_child2_index)) - assert response == '' - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) - assert not in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True) - child_of_child2_line = get_next_line(tree, 'bind-test-child2') - assert child_of_child2_line == '' - - #bind simple_bus as a child of bind-test-child2 - response = u_boot_console.run_command('bind {} {} simple_bus'.format(child2_uclass, child2_index)) - - #check that the child is there and its uclass/index pair is right - tree = u_boot_console.run_command('dm tree') - treelines = [x.strip() for x in tree.splitlines() if x.strip()] - - child_of_child2_line = get_next_line(tree, 'bind-test-child2') - assert child_of_child2_line - child_of_child2_index = int(child_of_child2_line.split()[1]) - assert in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True) - assert child_of_child2_index == child2_index + 1 - - #unbind the child and check it has been removed - response = u_boot_console.run_command('unbind {} {} simple_bus'.format(child2_uclass, child2_index)) - assert response == '' - - tree = u_boot_console.run_command('dm tree') - assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) - - child_of_child2_line = get_next_line(tree, 'bind-test-child2') - assert child_of_child2_line == '' - - #unbind the child again and check it doesn't change the tree - tree_old = u_boot_console.run_command('dm tree') - response = u_boot_console.run_command('unbind {} {} simple_bus'.format(child2_uclass, child2_index)) - tree_new = u_boot_console.run_command('dm tree') - - assert response == '' - assert tree_old == tree_new - - response = u_boot_console.run_command('unbind /bind-test') - assert response == '' + #bind /bind-test + response = u_boot_console.run_command('bind /bind-test simple_bus') + assert response == '' + + #make sure bind-test-child2 is there and get its uclass/index pair + tree = u_boot_console.run_command('dm tree') + child2_line = [x.strip() for x in tree.splitlines() if '-- bind-test-child2' in x] + assert len(child2_line) == 1 + + child2_uclass = child2_line[0].split()[0] + child2_index = int(child2_line[0].split()[1]) + + #bind simple_bus as a child of bind-test-child2 + response = u_boot_console.run_command( + 'bind {} {} simple_bus'.format(child2_uclass, child2_index)) + + #check that the child is there and its uclass/index pair is right + tree = u_boot_console.run_command('dm tree') + + child_of_child2_line = get_next_line(tree, 'bind-test-child2') + assert child_of_child2_line + child_of_child2_index = int(child_of_child2_line.split()[1]) + assert in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True) + assert child_of_child2_index == child2_index + 1 + + #unbind the child and check it has been removed + response = u_boot_console.run_command('unbind simple_bus {}'.format(child_of_child2_index)) + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + assert not in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True) + child_of_child2_line = get_next_line(tree, 'bind-test-child2') + assert child_of_child2_line == '' + + #bind simple_bus as a child of bind-test-child2 + response = u_boot_console.run_command( + 'bind {} {} simple_bus'.format(child2_uclass, child2_index)) + + #check that the child is there and its uclass/index pair is right + tree = u_boot_console.run_command('dm tree') + treelines = [x.strip() for x in tree.splitlines() if x.strip()] + + child_of_child2_line = get_next_line(tree, 'bind-test-child2') + assert child_of_child2_line + child_of_child2_index = int(child_of_child2_line.split()[1]) + assert in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True) + assert child_of_child2_index == child2_index + 1 + + #unbind the child and check it has been removed + response = u_boot_console.run_command( + 'unbind {} {} simple_bus'.format(child2_uclass, child2_index)) + assert response == '' + + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + + child_of_child2_line = get_next_line(tree, 'bind-test-child2') + assert child_of_child2_line == '' + + #unbind the child again and check it doesn't change the tree + tree_old = u_boot_console.run_command('dm tree') + response = u_boot_console.run_command( + 'unbind {} {} simple_bus'.format(child2_uclass, child2_index)) + tree_new = u_boot_console.run_command('dm tree') + + assert response == '' + assert tree_old == tree_new + + response = u_boot_console.run_command('unbind /bind-test') + assert response == '' diff --git a/test/py/tests/test_stackprotector.py b/test/py/tests/test_stackprotector.py index b009437e5e05b08a9d35360cf0aca9f85ed2ff6a..b87392c54ff88be8997715135acb601c65f9ee7b 100644 --- a/test/py/tests/test_stackprotector.py +++ b/test/py/tests/test_stackprotector.py @@ -5,6 +5,7 @@ import pytest import signal @pytest.mark.buildconfigspec('cmd_stackprotector_test') +@pytest.mark.notbuildconfigspec('asan') def test_stackprotector(u_boot_console): """Test that the stackprotector function works.""" diff --git a/tools/binman/elf.py b/tools/binman/elf.py index afa05e58fdd85e947e621fbd3b9d18b78d452f04..6d440ddf21df663841b413fccf617f7de8bf1cec 100644 --- a/tools/binman/elf.py +++ b/tools/binman/elf.py @@ -25,6 +25,9 @@ try: except: # pragma: no cover ELF_TOOLS = False +# BSYM in little endian, keep in sync with include/binman_sym.h +BINMAN_SYM_MAGIC_VALUE = 0x4d595342 + # Information about an EFL symbol: # section (str): Name of the section containing this symbol # address (int): Address of the symbol (its value) @@ -223,9 +226,12 @@ def LookupAndWriteSymbols(elf_fname, entry, section): raise ValueError('%s has size %d: only 4 and 8 are supported' % (msg, sym.size)) - # Look up the symbol in our entry tables. - value = section.GetImage().LookupImageSymbol(name, sym.weak, msg, - base.address) + if name == '_binman_sym_magic': + value = BINMAN_SYM_MAGIC_VALUE + else: + # Look up the symbol in our entry tables. + value = section.GetImage().LookupImageSymbol(name, sym.weak, + msg, base.address) if value is None: value = -1 pack_string = pack_string.lower() diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py index 02bc108374925165676e933719f7bf6ba6e62c50..5a51c64cfee32812bf1a94d5b43050a725a9c119 100644 --- a/tools/binman/elf_test.py +++ b/tools/binman/elf_test.py @@ -127,7 +127,7 @@ class TestElf(unittest.TestCase): elf_fname = self.ElfTestFile('u_boot_binman_syms') with self.assertRaises(ValueError) as e: elf.LookupAndWriteSymbols(elf_fname, entry, section) - self.assertIn('entry_path has offset 4 (size 8) but the contents size ' + self.assertIn('entry_path has offset 8 (size 8) but the contents size ' 'is a', str(e.exception)) def testMissingImageStart(self): @@ -161,18 +161,20 @@ class TestElf(unittest.TestCase): This should produce -1 values for all thress symbols, taking up the first 16 bytes of the image. """ - entry = FakeEntry(24) + entry = FakeEntry(28) section = FakeSection(sym_value=None) elf_fname = self.ElfTestFile('u_boot_binman_syms') elf.LookupAndWriteSymbols(elf_fname, entry, section) - self.assertEqual(tools.get_bytes(255, 20) + tools.get_bytes(ord('a'), 4), - entry.data) + expected = (struct.pack('; + offset = <28>; }; }; }; diff --git a/tools/binman/test/024_sorted.dts b/tools/binman/test/024_sorted.dts index b79d9adf68271db3ee7d50e79af675adab09c283..b54f9b14191d8d27ee269883ab26ebc9443eee0e 100644 --- a/tools/binman/test/024_sorted.dts +++ b/tools/binman/test/024_sorted.dts @@ -7,7 +7,7 @@ binman { sort-by-offset; u-boot { - offset = <26>; + offset = <30>; }; u-boot-spl { diff --git a/tools/binman/test/028_pack_4gb_outside.dts b/tools/binman/test/028_pack_4gb_outside.dts index 11a1f6059e263c8f1db70ad36e34ef456c89eed3..b6ad7fb56a534efcb1a22d46975d43cfcb92d37f 100644 --- a/tools/binman/test/028_pack_4gb_outside.dts +++ b/tools/binman/test/028_pack_4gb_outside.dts @@ -13,7 +13,7 @@ }; u-boot-spl { - offset = <0xffffffe7>; + offset = <0xffffffe3>; }; }; }; diff --git a/tools/binman/test/029_x86_rom.dts b/tools/binman/test/029_x86_rom.dts index 88aa007bbae19586402cdb2bab04eb6e56147d0b..ad8f9d6e1bdd35ebba7681a9963fd055fc08186a 100644 --- a/tools/binman/test/029_x86_rom.dts +++ b/tools/binman/test/029_x86_rom.dts @@ -7,13 +7,13 @@ binman { sort-by-offset; end-at-4gb; - size = <32>; + size = <36>; u-boot { - offset = <0xffffffe0>; + offset = <0xffffffdc>; }; u-boot-spl { - offset = <0xffffffe7>; + offset = <0xffffffe3>; }; }; }; diff --git a/tools/binman/test/053_symbols.dts b/tools/binman/test/053_symbols.dts index 2965809276480848744b0387ce36f69903453637..b28f34a72faafdd52dc6790c43af9678fd9b036b 100644 --- a/tools/binman/test/053_symbols.dts +++ b/tools/binman/test/053_symbols.dts @@ -10,7 +10,7 @@ }; u-boot { - offset = <0x18>; + offset = <0x1c>; }; u-boot-spl2 { diff --git a/tools/binman/test/149_symbols_tpl.dts b/tools/binman/test/149_symbols_tpl.dts index 0a4ab3f1fabdd321b5fa49cc4071686678efe153..4e649c45978d49c0629c2cf5a6f76561488b7891 100644 --- a/tools/binman/test/149_symbols_tpl.dts +++ b/tools/binman/test/149_symbols_tpl.dts @@ -11,12 +11,12 @@ }; u-boot-spl2 { - offset = <0x1c>; + offset = <0x20>; type = "u-boot-spl"; }; u-boot { - offset = <0x34>; + offset = <0x3c>; }; section { diff --git a/tools/binman/test/155_symbols_tpl_x86.dts b/tools/binman/test/155_symbols_tpl_x86.dts index 9d7dc51b3d9b68c4fa78b2ad21c7215f9e50827f..e1ce33e67fbc7f180efaeca39f3d1b57518afc6a 100644 --- a/tools/binman/test/155_symbols_tpl_x86.dts +++ b/tools/binman/test/155_symbols_tpl_x86.dts @@ -14,12 +14,12 @@ }; u-boot-spl2 { - offset = <0xffffff1c>; + offset = <0xffffff20>; type = "u-boot-spl"; }; u-boot { - offset = <0xffffff34>; + offset = <0xffffff3c>; }; section { diff --git a/tools/binman/test/187_symbols_sub.dts b/tools/binman/test/187_symbols_sub.dts index 54511a737112eb903a1a6acc88e9e4c280ba1e87..3ab62d37215261de90f7cdbac39da1b2fad23e5c 100644 --- a/tools/binman/test/187_symbols_sub.dts +++ b/tools/binman/test/187_symbols_sub.dts @@ -11,7 +11,7 @@ }; u-boot { - offset = <24>; + offset = <28>; }; }; diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile index 57057e2d588fd7db0573c2edd2e5807e748661b4..bea8567c9b45c0e3763d2dce6bbaf7947440304d 100644 --- a/tools/binman/test/Makefile +++ b/tools/binman/test/Makefile @@ -21,7 +21,7 @@ CC = $(CROSS_COMPILE)gcc OBJCOPY = $(CROSS_COMPILE)objcopy VPATH := $(SRC) -CFLAGS := -march=i386 -m32 -nostdlib -I $(SRC)../../../include \ +CFLAGS := -march=i386 -m32 -nostdlib -I $(SRC)../../../include -I $(SRC) \ -Wl,--no-dynamic-linker LDS_UCODE := -T $(SRC)u_boot_ucode_ptr.lds diff --git a/tools/binman/test/generated/autoconf.h b/tools/binman/test/generated/autoconf.h new file mode 100644 index 0000000000000000000000000000000000000000..6a23039f46991d199e3ac7b7b5013cebfcb884fb --- /dev/null +++ b/tools/binman/test/generated/autoconf.h @@ -0,0 +1,3 @@ +#define CONFIG_BINMAN 1 +#define CONFIG_SPL_BUILD 1 +#define CONFIG_SPL_BINMAN_SYMBOLS 1 diff --git a/tools/binman/test/u_boot_binman_syms.c b/tools/binman/test/u_boot_binman_syms.c index 37fc339ce84bfb5792e0672188e196bca36af8ce..ed761246aec751030b5b7d6ebfa4ba5427cd5460 100644 --- a/tools/binman/test/u_boot_binman_syms.c +++ b/tools/binman/test/u_boot_binman_syms.c @@ -5,9 +5,13 @@ * Simple program to create some binman symbols. This is used by binman tests. */ -#define CONFIG_BINMAN +typedef unsigned long ulong; + +#include #include +DECLARE_BINMAN_MAGIC_SYM; + binman_sym_declare(unsigned long, u_boot_spl_any, offset); binman_sym_declare(unsigned long long, u_boot_spl2, offset); binman_sym_declare(unsigned long, u_boot_any, image_pos); diff --git a/tools/binman/test/u_boot_binman_syms_size.c b/tools/binman/test/u_boot_binman_syms_size.c index 7224bc1863c75b4e51d30ba3f73841d7fad28659..fa41b3d9a332cf6be1e2922f8b39b12c0defaf57 100644 --- a/tools/binman/test/u_boot_binman_syms_size.c +++ b/tools/binman/test/u_boot_binman_syms_size.c @@ -5,7 +5,11 @@ * Simple program to create some binman symbols. This is used by binman tests. */ -#define CONFIG_BINMAN +typedef unsigned long ulong; + +#include #include +DECLARE_BINMAN_MAGIC_SYM; + binman_sym_declare(char, u_boot_spl, pos); diff --git a/tools/buildman/main.py b/tools/buildman/main.py index 3b6af240802d9a80c7663da5b0f6461b2937e3aa..67c560c48d37be0ed74e1f4515c7df58f062725c 100755 --- a/tools/buildman/main.py +++ b/tools/buildman/main.py @@ -11,7 +11,6 @@ import multiprocessing import os import re import sys -import unittest # Bring in the patman libraries our_path = os.path.dirname(os.path.realpath(__file__)) @@ -34,19 +33,18 @@ def RunTests(skip_net_tests, verboose, args): from buildman import test import doctest - result = unittest.TestResult() test_name = args and args[0] or None if skip_net_tests: test.use_network = False # Run the entry tests first ,since these need to be the first to import the # 'entry' module. - test_util.run_test_suites( - result, False, verboose, False, None, test_name, [], + result = test_util.run_test_suites( + 'buildman', False, verboose, False, None, test_name, [], [test.TestBuild, func_test.TestFunctional, 'buildman.toolchain', 'patman.gitutil']) - return test_util.report_result('buildman', test_name, result) + return (0 if result.wasSuccessful() else 1) options, args = cmdline.ParseArgs() diff --git a/tools/concurrencytest/concurrencytest.py b/tools/concurrencytest/concurrencytest.py index 5e88b94f41561f887dbf9e58fc8e36c83881bd17..1c4f03f37e5bd7f9eb399867d711600097d1ae18 100644 --- a/tools/concurrencytest/concurrencytest.py +++ b/tools/concurrencytest/concurrencytest.py @@ -31,6 +31,7 @@ from subunit import ProtocolTestCase, TestProtocolClient from subunit.test_results import AutoTimingTestResultDecorator from testtools import ConcurrentTestSuite, iterate_tests +from testtools.content import TracebackContent, text_content _all__ = [ @@ -43,11 +44,81 @@ _all__ = [ CPU_COUNT = cpu_count() -def fork_for_tests(concurrency_num=CPU_COUNT): +class BufferingTestProtocolClient(TestProtocolClient): + """A TestProtocolClient which can buffer the test outputs + + This class captures the stdout and stderr output streams of the + tests as it runs them, and includes the output texts in the subunit + stream as additional details. + + Args: + stream: A file-like object to write a subunit stream to + buffer (bool): True to capture test stdout/stderr outputs and + include them in the test details + """ + def __init__(self, stream, buffer=True): + super().__init__(stream) + self.buffer = buffer + + def _addOutcome(self, outcome, test, error=None, details=None, + error_permitted=True): + """Report a test outcome to the subunit stream + + The parent class uses this function as a common implementation + for various methods that report successes, errors, failures, etc. + + This version automatically upgrades the error tracebacks to the + new 'details' format by wrapping them in a Content object, so + that we can include the captured test output in the test result + details. + + Args: + outcome: A string describing the outcome - used as the + event name in the subunit stream. + test: The test case whose outcome is to be reported + error: Standard unittest positional argument form - an + exc_info tuple. + details: New Testing-in-python drafted API; a dict from + string to subunit.Content objects. + error_permitted: If True then one and only one of error or + details must be supplied. If False then error must not + be supplied and details is still optional. + """ + if details is None: + details = {} + + # Parent will raise an exception if error_permitted is False but + # error is not None. We want that exception in that case, so + # don't touch error when error_permitted is explicitly False. + if error_permitted and error is not None: + # Parent class prefers error over details + details['traceback'] = TracebackContent(error, test) + error_permitted = False + error = None + + if self.buffer: + stdout = sys.stdout.getvalue() + if stdout: + details['stdout'] = text_content(stdout) + + stderr = sys.stderr.getvalue() + if stderr: + details['stderr'] = text_content(stderr) + + return super()._addOutcome(outcome, test, error=error, + details=details, error_permitted=error_permitted) + + +def fork_for_tests(concurrency_num=CPU_COUNT, buffer=False): """Implementation of `make_tests` used to construct `ConcurrentTestSuite`. :param concurrency_num: number of processes to use. """ + if buffer: + test_protocol_client_class = BufferingTestProtocolClient + else: + test_protocol_client_class = TestProtocolClient + def do_fork(suite): """Take suite and start up multiple runners by forking (Unix only). @@ -76,7 +147,7 @@ def fork_for_tests(concurrency_num=CPU_COUNT): # child actually gets keystrokes for pdb etc). sys.stdin.close() subunit_result = AutoTimingTestResultDecorator( - TestProtocolClient(stream) + test_protocol_client_class(stream) ) process_suite.run(subunit_result) except: @@ -93,7 +164,13 @@ def fork_for_tests(concurrency_num=CPU_COUNT): else: os.close(c2pwrite) stream = os.fdopen(c2pread, 'rb') - test = ProtocolTestCase(stream) + # If we don't pass the second argument here, it defaults + # to sys.stdout.buffer down the line. But if we don't + # pass it *now*, it may be resolved after sys.stdout is + # replaced with a StringIO (to capture tests' outputs) + # which doesn't have a buffer attribute and can end up + # occasionally causing a 'broken-runner' error. + test = ProtocolTestCase(stream, sys.stdout.buffer) result.append(test) return result return do_fork diff --git a/tools/dtoc/main.py b/tools/dtoc/main.py index fac9db9c786f1554d9f51af63debe78e57c8d285..5508759d4d5658d8d9c5cf2a406f4b2263b877c6 100755 --- a/tools/dtoc/main.py +++ b/tools/dtoc/main.py @@ -24,7 +24,6 @@ see doc/driver-model/of-plat.rst from argparse import ArgumentParser import os import sys -import unittest # Bring in the patman libraries our_path = os.path.dirname(os.path.realpath(__file__)) @@ -49,18 +48,18 @@ def run_tests(processes, args): from dtoc import test_src_scan from dtoc import test_dtoc - result = unittest.TestResult() sys.argv = [sys.argv[0]] test_name = args.files and args.files[0] or None test_dtoc.setup() - test_util.run_test_suites( - result, debug=True, verbosity=1, test_preserve_dirs=False, + result = test_util.run_test_suites( + toolname='dtoc', debug=True, verbosity=1, test_preserve_dirs=False, processes=processes, test_name=test_name, toolpath=[], class_and_module_list=[test_dtoc.TestDtoc,test_src_scan.TestSrcScan]) - return test_util.report_result('binman', test_name, result) + return (0 if result.wasSuccessful() else 1) + def RunTestCoverage(): """Run the tests and check that we get 100% coverage""" diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py index c81bcc9c32f16535c01721068e7d93f4980550ea..879ca2ab2bfc9b00780f2ee2069c45548d555b3a 100755 --- a/tools/dtoc/test_dtoc.py +++ b/tools/dtoc/test_dtoc.py @@ -616,8 +616,11 @@ struct dm_test_pdata __attribute__ ((section (".priv_data"))) u8 _denx_u_boot_test_bus_priv_some_bus[sizeof(struct dm_test_priv)] \t__attribute__ ((section (".priv_data"))); #include -u8 _denx_u_boot_test_bus_ucplat_some_bus[sizeof(struct dm_test_uclass_priv)] +u8 _denx_u_boot_test_bus_ucplat_some_bus[sizeof(struct dm_test_uclass_plat)] \t__attribute__ ((section (".priv_data"))); +#include +u8 _denx_u_boot_test_bus_uc_priv_some_bus[sizeof(struct dm_test_uclass_priv)] + __attribute__ ((section (".priv_data"))); #include DM_DEVICE_INST(some_bus) = { @@ -628,6 +631,7 @@ DM_DEVICE_INST(some_bus) = { \t.driver_data\t= DM_TEST_TYPE_FIRST, \t.priv_\t\t= _denx_u_boot_test_bus_priv_some_bus, \t.uclass\t\t= DM_UCLASS_REF(testbus), +\t.uclass_priv_ = _denx_u_boot_test_bus_uc_priv_some_bus, \t.uclass_node\t= { \t\t.prev = &DM_UCLASS_REF(testbus)->dev_head, \t\t.next = &DM_UCLASS_REF(testbus)->dev_head, diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index 914ed6aed59f30d2a8ea8541fb6ed019e46fc2bf..3baf4437cdd3b40ebd5bf84be5d289dd40c27340 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -780,25 +780,17 @@ def RunTests(args): Args: args: List of positional args provided to fdt. This can hold a test name to execute (as in 'fdt -t testFdt', for example) + + Returns: + Return code, 0 on success """ - result = unittest.TestResult() - sys.argv = [sys.argv[0]] test_name = args and args[0] or None - for module in (TestFdt, TestNode, TestProp, TestFdtUtil): - if test_name: - try: - suite = unittest.TestLoader().loadTestsFromName(test_name, module) - except AttributeError: - continue - else: - suite = unittest.TestLoader().loadTestsFromTestCase(module) - suite.run(result) - - print(result) - for _, err in result.errors: - print(err) - for _, err in result.failures: - print(err) + result = test_util.run_test_suites( + 'test_fdt', False, False, False, None, test_name, None, + [TestFdt, TestNode, TestProp, TestFdtUtil]) + + return (0 if result.wasSuccessful() else 1) + if __name__ != '__main__': sys.exit(1) @@ -816,6 +808,7 @@ parser.add_option('-T', '--test-coverage', action='store_true', # Run our meagre tests if options.test: - RunTests(args) + ret_code = RunTests(args) + sys.exit(ret_code) elif options.test_coverage: RunTestCoverage() diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 31afef6f3b1780f01defecce0626fdcdb0898061..908a162202d55d189a57877d610af87f3b108da5 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1713,6 +1713,67 @@ static int check_device_config(int dev) return rc; } +static int find_nvmem_device(void) +{ + const char *path = "/sys/bus/nvmem/devices"; + struct dirent *dent; + char *nvmem = NULL; + char comp[256]; + char buf[32]; + int bytes; + DIR *dir; + + dir = opendir(path); + if (!dir) { + return -EIO; + } + + while (!nvmem && (dent = readdir(dir))) { + FILE *fp; + + if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) { + continue; + } + + bytes = snprintf(comp, sizeof(comp), "%s/%s/of_node/compatible", path, dent->d_name); + if (bytes < 0 || bytes == sizeof(comp)) { + continue; + } + + fp = fopen(comp, "r"); + if (!fp) { + continue; + } + + fread(buf, sizeof(buf), 1, fp); + + if (!strcmp(buf, "u-boot,env")) { + bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name); + if (bytes < 0) { + nvmem = NULL; + } + } + + fclose(fp); + } + + closedir(dir); + + if (nvmem) { + struct stat s; + + stat(nvmem, &s); + + DEVNAME(0) = nvmem; + DEVOFFSET(0) = 0; + ENVSIZE(0) = s.st_size; + + return 0; + } + + return -ENOENT; +} + static int parse_config(struct env_opts *opts) { int rc; @@ -1723,9 +1784,12 @@ static int parse_config(struct env_opts *opts) #if defined(CONFIG_FILE) /* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */ if (get_config(opts->config_file)) { - fprintf(stderr, "Cannot parse config file '%s': %m\n", - opts->config_file); - return -1; + if (find_nvmem_device()) { + fprintf(stderr, "Cannot parse config file '%s': %m\n", + opts->config_file); + fprintf(stderr, "Failed to find NVMEM device\n"); + return -1; + } } #else DEVNAME(0) = DEVICE1_NAME; diff --git a/tools/fit_image.c b/tools/fit_image.c index 1884a2eb0b95114254342ffad2fdaa1d1b6a391e..979f2411ee0e897138ff2d46d8f3befb5ab480da 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -199,15 +199,36 @@ static void get_basename(char *str, int size, const char *fname) } /** - * add_crc_node() - Add a hash node to request a CRC checksum for an image + * add_hash_node() - Add a hash or signature node * + * @params: Image parameters * @fdt: Device tree to add to (in sequential-write mode) + * + * If there is a key name hint, try to sign the images. Otherwise, just add a + * CRC. + * + * Return: 0 on success, or -1 on failure */ -static void add_crc_node(void *fdt) +static int add_hash_node(struct image_tool_params *params, void *fdt) { - fdt_begin_node(fdt, "hash-1"); - fdt_property_string(fdt, FIT_ALGO_PROP, "crc32"); + if (params->keyname) { + if (!params->algo_name) { + fprintf(stderr, + "%s: Algorithm name must be specified\n", + params->cmdname); + return -1; + } + + fdt_begin_node(fdt, "signature-1"); + fdt_property_string(fdt, FIT_ALGO_PROP, params->algo_name); + fdt_property_string(fdt, FIT_KEY_HINT, params->keyname); + } else { + fdt_begin_node(fdt, "hash-1"); + fdt_property_string(fdt, FIT_ALGO_PROP, "crc32"); + } + fdt_end_node(fdt); + return 0; } /** @@ -248,7 +269,9 @@ static int fit_write_images(struct image_tool_params *params, char *fdt) ret = fdt_property_file(params, fdt, FIT_DATA_PROP, params->datafile); if (ret) return ret; - add_crc_node(fdt); + ret = add_hash_node(params, fdt); + if (ret) + return ret; fdt_end_node(fdt); /* Now the device tree files if available */ @@ -271,7 +294,9 @@ static int fit_write_images(struct image_tool_params *params, char *fdt) genimg_get_arch_short_name(params->arch)); fdt_property_string(fdt, FIT_COMP_PROP, genimg_get_comp_short_name(IH_COMP_NONE)); - add_crc_node(fdt); + ret = add_hash_node(params, fdt); + if (ret) + return ret; fdt_end_node(fdt); } @@ -289,7 +314,9 @@ static int fit_write_images(struct image_tool_params *params, char *fdt) params->fit_ramdisk); if (ret) return ret; - add_crc_node(fdt); + ret = add_hash_node(params, fdt); + if (ret) + return ret; fdt_end_node(fdt); } diff --git a/tools/imagetool.h b/tools/imagetool.h index 05dd94d108474842b88eb8a38a2db9a03d13fc33..ca7c2e48ba914441758a69536a548e3d539b7d20 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -71,6 +71,7 @@ struct image_tool_params { const char *keydir; /* Directory holding private keys */ const char *keydest; /* Destination .dtb for public key */ const char *keyfile; /* Filename of private or public key */ + const char *keyname; /* Key name "hint" */ const char *comment; /* Comment to add to signature node */ /* Algorithm name to use for hashing/signing or NULL to use the one * specified in the its */ diff --git a/tools/mips-relocs.c b/tools/mips-relocs.c index 625258085b608b17a54342db5ee90affd89f0ca0..5db610f5c77bb098c81f37d8a4ac59f6c6e42493 100644 --- a/tools/mips-relocs.c +++ b/tools/mips-relocs.c @@ -312,7 +312,7 @@ int main(int argc, char *argv[]) goto out_free_relocs; } - rel_pfx = is_64 ? ".rela." : ".rel."; + rel_pfx = is_64 ? ".rela" : ".rel"; for (i = 0; i < ehdr_field(e_shnum); i++) { sh_type = shdr_field(i, sh_type); @@ -321,10 +321,11 @@ int main(int argc, char *argv[]) sh_name = shstr(shdr_field(i, sh_name)); if (strncmp(sh_name, rel_pfx, strlen(rel_pfx))) { - if (strcmp(sh_name, ".rel") && strcmp(sh_name, ".rel.dyn")) - fprintf(stderr, "WARNING: Unexpected reloc section name '%s'\n", sh_name); + fprintf(stderr, "WARNING: Unexpected reloc section name '%s'\n", sh_name); continue; } + if (!strcmp(sh_name, ".rel") || !strcmp(sh_name, ".rel.dyn")) + continue; /* * Skip reloc sections which either don't correspond to another @@ -334,7 +335,7 @@ int main(int argc, char *argv[]) */ skip = true; for (j = 0; j < ehdr_field(e_shnum); j++) { - if (strcmp(&sh_name[strlen(rel_pfx) - 1], shstr(shdr_field(j, sh_name)))) + if (strcmp(&sh_name[strlen(rel_pfx)], shstr(shdr_field(j, sh_name)))) continue; skip = !(shdr_field(j, sh_flags) & SHF_ALLOC); diff --git a/tools/mkimage.c b/tools/mkimage.c index 5c6a60e85136074d98b8ad5046bb7715a2b7b1ab..0e1198b411325a685e60116e445fbe0158cd0d08 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -119,6 +119,7 @@ static void usage(const char *msg) "Signing / verified boot options: [-k keydir] [-K dtb] [ -c ] [-p addr] [-r] [-N engine]\n" " -k => set directory containing private keys\n" " -K => write public keys to this .dtb file\n" + " -g => set key name hint\n" " -G => use this signing key (in lieu of -k)\n" " -c => add comment in signature node\n" " -F => re-sign existing FIT image\n" @@ -163,7 +164,7 @@ static void process_args(int argc, char **argv) int opt; while ((opt = getopt(argc, argv, - "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:ln:N:p:o:O:rR:qstT:vVx")) != -1) { + "a:A:b:B:c:C:d:D:e:Ef:Fg:G:k:i:K:ln:N:p:o:O:rR:qstT:vVx")) != -1) { switch (opt) { case 'a': params.addr = strtoull(optarg, &ptr, 16); @@ -239,6 +240,8 @@ static void process_args(int argc, char **argv) params.type = IH_TYPE_FLATDT; params.fflag = 1; break; + case 'g': + params.keyname = optarg; case 'G': params.keyfile = optarg; break; diff --git a/tools/patman/main.py b/tools/patman/main.py index 2a2ac4570931f21768fb9a4c7f24a09762ddca99..66d4806c8d8ffffb627e2cfff2e2bdb2bb6d4c4f 100755 --- a/tools/patman/main.py +++ b/tools/patman/main.py @@ -12,7 +12,6 @@ import re import shutil import sys import traceback -import unittest if __name__ == "__main__": # Allow 'from patman import xxx to work' @@ -134,13 +133,12 @@ if args.cmd == 'test': import doctest from patman import func_test - result = unittest.TestResult() - test_util.run_test_suites( - result, False, False, False, None, None, None, + result = test_util.run_test_suites( + 'patman', False, False, False, None, None, None, [test_checkpatch.TestPatch, func_test.TestFunctional, 'gitutil', 'settings', 'terminal']) - sys.exit(test_util.report_result('patman', args.testname, result)) + sys.exit(0 if result.wasSuccessful() else 1) # Process commits, produce patches files, check them, email them elif args.cmd == 'send': diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 7c2b5c196c0621696d5715ab7d24602b6920467e..4c847fe88fd4cacd7df36915715f11c7822f089b 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -246,8 +246,10 @@ def _UpdateDefaults(main_parser, config): # Collect the defaults from each parser defaults = {} + parser_defaults = [] for parser in parsers: pdefs = parser.parse_known_args()[0] + parser_defaults.append(pdefs) defaults.update(vars(pdefs)) # Go through the settings and collect defaults @@ -264,8 +266,11 @@ def _UpdateDefaults(main_parser, config): else: print("WARNING: Unknown setting %s" % name) - # Set all the defaults (this propagates through all subparsers) + # Set all the defaults and manually propagate them to subparsers main_parser.set_defaults(**defaults) + for parser, pdefs in zip(parsers, parser_defaults): + parser.set_defaults(**{ k: v for k, v in defaults.items() + if k in pdefs }) def _ReadAliasFile(fname): """Read in the U-Boot git alias file if it exists. diff --git a/tools/patman/test_util.py b/tools/patman/test_util.py index c60eb3628e23e522ea9d90dbf84be7242b68032d..c27e0b39e5fa2a29802599d84677d690952a3656 100644 --- a/tools/patman/test_util.py +++ b/tools/patman/test_util.py @@ -15,6 +15,7 @@ from patman import command from io import StringIO +buffer_outputs = True use_concurrent = True try: from concurrencytest.concurrencytest import ConcurrentTestSuite @@ -102,49 +103,85 @@ def capture_sys_output(): sys.stdout, sys.stderr = old_out, old_err -def report_result(toolname:str, test_name: str, result: unittest.TestResult): - """Report the results from a suite of tests +class FullTextTestResult(unittest.TextTestResult): + """A test result class that can print extended text results to a stream + + This is meant to be used by a TestRunner as a result class. Like + TextTestResult, this prints out the names of tests as they are run, + errors as they occur, and a summary of the results at the end of the + test run. Beyond those, this prints information about skipped tests, + expected failures and unexpected successes. Args: - toolname: Name of the tool that ran the tests - test_name: Name of test that was run, or None for all - result: A unittest.TestResult object containing the results + stream: A file-like object to write results to + descriptions (bool): True to print descriptions with test names + verbosity (int): Detail of printed output per test as they run + Test stdout and stderr always get printed when buffering + them is disabled by the test runner. In addition to that, + 0: Print nothing + 1: Print a dot per test + 2: Print test names + 3: Print test names, and buffered outputs for failing tests """ - # Remove errors which just indicate a missing test. Since Python v3.5 If an - # ImportError or AttributeError occurs while traversing name then a - # synthetic test that raises that error when run will be returned. These - # errors are included in the errors accumulated by result.errors. - if test_name: - errors = [] - - for test, err in result.errors: - if ("has no attribute '%s'" % test_name) not in err: - errors.append((test, err)) - result.testsRun -= 1 - result.errors = errors - - print(result) - for test, err in result.errors: - print(test.id(), err) - for test, err in result.failures: - print(err, result.failures) - if result.skipped: - print('%d %s test%s SKIPPED:' % (len(result.skipped), toolname, - 's' if len(result.skipped) > 1 else '')) - for skip_info in result.skipped: - print('%s: %s' % (skip_info[0], skip_info[1])) - if result.errors or result.failures: - print('%s tests FAILED' % toolname) - return 1 - return 0 - - -def run_test_suites(result, debug, verbosity, test_preserve_dirs, processes, + def __init__(self, stream, descriptions, verbosity): + self.verbosity = verbosity + super().__init__(stream, descriptions, verbosity) + + def printErrors(self): + "Called by TestRunner after test run to summarize the tests" + # The parent class doesn't keep unexpected successes in the same + # format as the rest. Adapt it to what printErrorList expects. + unexpected_successes = [ + (test, 'Test was expected to fail, but succeeded.\n') + for test in self.unexpectedSuccesses + ] + + super().printErrors() # FAIL and ERROR + self.printErrorList('SKIP', self.skipped) + self.printErrorList('XFAIL', self.expectedFailures) + self.printErrorList('XPASS', unexpected_successes) + + def addError(self, test, err): + """Called when an error has occurred.""" + super().addError(test, err) + self._mirrorOutput &= self.verbosity >= 3 + + def addFailure(self, test, err): + """Called when a test has failed.""" + super().addFailure(test, err) + self._mirrorOutput &= self.verbosity >= 3 + + def addSubTest(self, test, subtest, err): + """Called at the end of a subtest.""" + super().addSubTest(test, subtest, err) + self._mirrorOutput &= self.verbosity >= 3 + + def addSuccess(self, test): + """Called when a test has completed successfully""" + super().addSuccess(test) + # Don't print stdout/stderr for successful tests + self._mirrorOutput = False + + def addSkip(self, test, reason): + """Called when a test is skipped.""" + # Add empty line to keep spacing consistent with other results + if not reason.endswith('\n'): + reason += '\n' + super().addSkip(test, reason) + self._mirrorOutput &= self.verbosity >= 3 + + def addExpectedFailure(self, test, err): + """Called when an expected failure/error occurred.""" + super().addExpectedFailure(test, err) + self._mirrorOutput &= self.verbosity >= 3 + + +def run_test_suites(toolname, debug, verbosity, test_preserve_dirs, processes, test_name, toolpath, class_and_module_list): """Run a series of test suites and collect the results Args: - result: A unittest.TestResult object to add the results to + toolname: Name of the tool that ran the tests debug: True to enable debugging, which shows a full stack trace on error verbosity: Verbosity level to use (0-4) test_preserve_dirs: True to preserve the input directory used by tests @@ -158,11 +195,6 @@ def run_test_suites(result, debug, verbosity, test_preserve_dirs, processes, class_and_module_list: List of test classes (type class) and module names (type str) to run """ - for module in class_and_module_list: - if isinstance(module, str) and (not test_name or test_name == module): - suite = doctest.DocTestSuite(module) - suite.run(result) - sys.argv = [sys.argv[0]] if debug: sys.argv.append('-D') @@ -174,6 +206,22 @@ def run_test_suites(result, debug, verbosity, test_preserve_dirs, processes, suite = unittest.TestSuite() loader = unittest.TestLoader() + runner = unittest.TextTestRunner( + stream=sys.stdout, + verbosity=(1 if verbosity is None else verbosity), + buffer=buffer_outputs, + resultclass=FullTextTestResult, + ) + + if use_concurrent and processes != 1: + suite = ConcurrentTestSuite(suite, + fork_for_tests(processes or multiprocessing.cpu_count(), + buffer=buffer_outputs)) + + for module in class_and_module_list: + if isinstance(module, str) and (not test_name or test_name == module): + suite.addTests(doctest.DocTestSuite(module)) + for module in class_and_module_list: if isinstance(module, str): continue @@ -184,15 +232,17 @@ def run_test_suites(result, debug, verbosity, test_preserve_dirs, processes, preserve_outdirs=test_preserve_dirs and test_name is not None, toolpath=toolpath, verbosity=verbosity) if test_name: - try: + # Since Python v3.5 If an ImportError or AttributeError occurs + # while traversing a name then a synthetic test that raises that + # error when run will be returned. Check that the requested test + # exists, otherwise these errors are included in the results. + if test_name in loader.getTestCaseNames(module): suite.addTests(loader.loadTestsFromName(test_name, module)) - except AttributeError: - continue else: suite.addTests(loader.loadTestsFromTestCase(module)) - if use_concurrent and processes != 1: - concurrent_suite = ConcurrentTestSuite(suite, - fork_for_tests(processes or multiprocessing.cpu_count())) - concurrent_suite.run(result) - else: - suite.run(result) + + print(f" Running {toolname} tests ".center(70, "=")) + result = runner.run(suite) + print() + + return result diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index f0bc548617a43e8f53d56e2d112c3b635abd35b7..090fb1acb20c2234b65487f268f7c20b28371d00 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -20,6 +20,10 @@ #define R_AARCH64_RELATIVE 1027 #endif +static int ei_class; + +static uint64_t rela_start, rela_end, text_base, dyn_start; + static const bool debug_en; static void debug(const char *fmt, ...) @@ -52,58 +56,310 @@ static bool supported_rela(Elf64_Rela *rela) } } -static bool read_num(const char *str, uint64_t *num) +static int decode_elf64(FILE *felf, char **argv) { - char *endptr; - *num = strtoull(str, &endptr, 16); - return str[0] && !endptr[0]; + size_t size; + Elf64_Ehdr header; + uint64_t section_header_base, section_header_size, sh_offset, sh_size; + Elf64_Shdr *sh_table; /* Elf symbol table */ + int ret, i, machine; + char *sh_str; + + debug("64bit version\n"); + + /* Make sure we are at start */ + rewind(felf); + + size = fread(&header, 1, sizeof(header), felf); + if (size != sizeof(header)) { + fclose(felf); + return 25; + } + + machine = header.e_machine; + debug("Machine\t%d\n", machine); + + if (machine != EM_AARCH64) { + fprintf(stderr, "%s: Not supported machine type\n", argv[0]); + return 30; + } + + text_base = header.e_entry; + section_header_base = header.e_shoff; + section_header_size = header.e_shentsize * header.e_shnum; + + sh_table = malloc(section_header_size); + if (!sh_table) { + fprintf(stderr, "%s: Cannot allocate space for section header\n", + argv[0]); + fclose(felf); + return 26; + } + + ret = fseek(felf, section_header_base, SEEK_SET); + if (ret) { + fprintf(stderr, "%s: Can't set pointer to section header: %x/%lx\n", + argv[0], ret, section_header_base); + free(sh_table); + fclose(felf); + return 26; + } + + size = fread(sh_table, 1, section_header_size, felf); + if (size != section_header_size) { + fprintf(stderr, "%s: Can't read section header: %lx/%lx\n", + argv[0], size, section_header_size); + free(sh_table); + fclose(felf); + return 27; + } + + sh_size = sh_table[header.e_shstrndx].sh_size; + debug("e_shstrndx\t0x%08x\n", header.e_shstrndx); + debug("sh_size\t\t0x%08lx\n", sh_size); + + sh_str = malloc(sh_size); + if (!sh_str) { + fprintf(stderr, "malloc failed\n"); + free(sh_table); + fclose(felf); + return 28; + } + + /* + * Specifies the byte offset from the beginning of the file + * to the first byte in the section. + */ + sh_offset = sh_table[header.e_shstrndx].sh_offset; + + debug("sh_offset\t0x%08x\n", header.e_shnum); + + ret = fseek(felf, sh_offset, SEEK_SET); + if (ret) { + fprintf(stderr, "Setting up sh_offset failed\n"); + free(sh_str); + free(sh_table); + fclose(felf); + return 29; + } + + size = fread(sh_str, 1, sh_size, felf); + if (size != sh_size) { + fprintf(stderr, "%s: Can't read section: %lx/%lx\n", + argv[0], size, sh_size); + free(sh_str); + free(sh_table); + fclose(felf); + return 30; + } + + for (i = 0; i < header.e_shnum; i++) { + /* fprintf(stderr, "%s\n", sh_str + sh_table[i].sh_name); Debug only */ + if (!strcmp(".rela.dyn", (sh_str + sh_table[i].sh_name))) { + debug("Found section\t\".rela_dyn\"\n"); + debug(" at addr\t0x%08x\n", + (unsigned int)sh_table[i].sh_addr); + debug(" at offset\t0x%08x\n", + (unsigned int)sh_table[i].sh_offset); + debug(" of size\t0x%08x\n", + (unsigned int)sh_table[i].sh_size); + rela_start = sh_table[i].sh_addr; + rela_end = rela_start + sh_table[i].sh_size; + break; + } + } + + /* Clean up */ + free(sh_str); + free(sh_table); + fclose(felf); + + debug("text_base\t0x%08lx\n", text_base); + debug("rela_start\t0x%08lx\n", rela_start); + debug("rela_end\t0x%08lx\n", rela_end); + + if (!rela_start) + return 1; + + return 0; } -int main(int argc, char **argv) +static int decode_elf32(FILE *felf, char **argv) { - FILE *f; - int i, num; - uint64_t rela_start, rela_end, text_base, file_size; + size_t size; + Elf32_Ehdr header; + uint64_t section_header_base, section_header_size, sh_offset, sh_size; + Elf32_Shdr *sh_table; /* Elf symbol table */ + int ret, i, machine; + char *sh_str; - if (argc != 5) { - fprintf(stderr, "Statically apply ELF rela relocations\n"); - fprintf(stderr, "Usage: %s " \ - " \n", argv[0]); - fprintf(stderr, "All numbers in hex.\n"); - return 1; + debug("32bit version\n"); + + /* Make sure we are at start */ + rewind(felf); + + size = fread(&header, 1, sizeof(header), felf); + if (size != sizeof(header)) { + fclose(felf); + return 25; } - f = fopen(argv[1], "r+b"); - if (!f) { + machine = header.e_machine; + debug("Machine %d\n", machine); + + if (machine != EM_MICROBLAZE) { + fprintf(stderr, "%s: Not supported machine type\n", argv[0]); + return 30; + } + + text_base = header.e_entry; + section_header_base = header.e_shoff; + + debug("Section header base %x\n", section_header_base); + + section_header_size = header.e_shentsize * header.e_shnum; + + debug("Section header size %d\n", section_header_size); + + sh_table = malloc(section_header_size); + if (!sh_table) { + fprintf(stderr, "%s: Cannot allocate space for section header\n", + argv[0]); + fclose(felf); + return 26; + } + + ret = fseek(felf, section_header_base, SEEK_SET); + if (ret) { + fprintf(stderr, "%s: Can't set pointer to section header: %x/%lx\n", + argv[0], ret, section_header_base); + free(sh_table); + fclose(felf); + return 26; + } + + size = fread(sh_table, 1, section_header_size, felf); + if (size != section_header_size) { + fprintf(stderr, "%s: Can't read section header: %lx/%lx\n", + argv[0], size, section_header_size); + free(sh_table); + fclose(felf); + return 27; + } + + sh_size = sh_table[header.e_shstrndx].sh_size; + debug("e_shstrndx %x, sh_size %lx\n", header.e_shstrndx, sh_size); + + sh_str = malloc(sh_size); + if (!sh_str) { + fprintf(stderr, "malloc failed\n"); + free(sh_table); + fclose(felf); + return 28; + } + + /* + * Specifies the byte offset from the beginning of the file + * to the first byte in the section. + */ + sh_offset = sh_table[header.e_shstrndx].sh_offset; + + debug("sh_offset %x\n", header.e_shnum); + + ret = fseek(felf, sh_offset, SEEK_SET); + if (ret) { + fprintf(stderr, "Setting up sh_offset failed\n"); + free(sh_str); + free(sh_table); + fclose(felf); + return 29; + } + + size = fread(sh_str, 1, sh_size, felf); + if (size != sh_size) { + fprintf(stderr, "%s: Can't read section: %lx/%lx\n", + argv[0], size, sh_size); + free(sh_str); + free(sh_table); + fclose(felf); + return 30; + } + + for (i = 0; i < header.e_shnum; i++) { + debug("%s\n", sh_str + sh_table[i].sh_name); + if (!strcmp(".rela.dyn", (sh_str + sh_table[i].sh_name))) { + debug("Found section\t\".rela_dyn\"\n"); + debug(" at addr\t0x%08x\n", (unsigned int)sh_table[i].sh_addr); + debug(" at offset\t0x%08x\n", (unsigned int)sh_table[i].sh_offset); + debug(" of size\t0x%08x\n", (unsigned int)sh_table[i].sh_size); + rela_start = sh_table[i].sh_addr; + rela_end = rela_start + sh_table[i].sh_size; + } + if (!strcmp(".dynsym", (sh_str + sh_table[i].sh_name))) { + debug("Found section\t\".dynsym\"\n"); + debug(" at addr\t0x%08x\n", (unsigned int)sh_table[i].sh_addr); + debug(" at offset\t0x%08x\n", (unsigned int)sh_table[i].sh_offset); + debug(" of size\t0x%08x\n", (unsigned int)sh_table[i].sh_size); + dyn_start = sh_table[i].sh_addr; + } + } + + /* Clean up */ + free(sh_str); + free(sh_table); + fclose(felf); + + debug("text_base\t0x%08lx\n", text_base); + debug("rela_start\t0x%08lx\n", rela_start); + debug("rela_end\t0x%08lx\n", rela_end); + debug("dyn_start\t0x%08lx\n", dyn_start); + + if (!rela_start) + return 1; + + return 0; +} + +static int decode_elf(char **argv) +{ + FILE *felf; + size_t size; + unsigned char e_ident[EI_NIDENT]; + + felf = fopen(argv[2], "r+b"); + if (!felf) { fprintf(stderr, "%s: Cannot open %s: %s\n", - argv[0], argv[1], strerror(errno)); + argv[0], argv[5], strerror(errno)); return 2; } - if (!read_num(argv[2], &text_base) || - !read_num(argv[3], &rela_start) || - !read_num(argv[4], &rela_end)) { - fprintf(stderr, "%s: bad number\n", argv[0]); - return 3; + size = fread(e_ident, 1, EI_NIDENT, felf); + if (size != EI_NIDENT) { + fclose(felf); + return 25; } - if (rela_start > rela_end || rela_start < text_base) { - fprintf(stderr, "%s: bad rela bounds\n", argv[0]); - return 3; + /* Check if this is really ELF file */ + if (e_ident[0] != 0x7f && + e_ident[1] != 'E' && + e_ident[2] != 'L' && + e_ident[3] != 'F') { + fclose(felf); + return 1; } - rela_start -= text_base; - rela_end -= text_base; + ei_class = e_ident[4]; + debug("EI_CLASS(1=32bit, 2=64bit) %d\n", ei_class); - fseek(f, 0, SEEK_END); - file_size = ftell(f); - rewind(f); + if (ei_class == 2) + return decode_elf64(felf, argv); - if (rela_end > file_size) { - // Most likely compiler inserted some section that didn't get - // objcopy-ed into the final binary - rela_end = file_size; - } + return decode_elf32(felf, argv); +} + +static int rela_elf64(char **argv, FILE *f) +{ + int i, num; if ((rela_end - rela_start) % sizeof(Elf64_Rela)) { fprintf(stderr, "%s: rela size isn't a multiple of Elf64_Rela\n", argv[0]); @@ -161,11 +417,228 @@ int main(int argc, char **argv) } } + return 0; +} + +static bool supported_rela32(Elf32_Rela *rela, uint32_t *type) +{ + uint32_t mask = 0xffULL; /* would be different on 32-bit */ + *type = rela->r_info & mask; + + debug("Type:\t"); + + switch (*type) { + case R_MICROBLAZE_32: + debug("R_MICROBLAZE_32\n"); + return true; + case R_MICROBLAZE_GLOB_DAT: + debug("R_MICROBLAZE_GLOB_DAT\n"); + return true; + case R_MICROBLAZE_NONE: + debug("R_MICROBLAZE_NONE - ignoring - do nothing\n"); + return false; + case R_MICROBLAZE_REL: + debug("R_MICROBLAZE_REL\n"); + return true; + default: + fprintf(stderr, "warning: unsupported relocation type %" + PRIu32 " at %" PRIx32 "\n", *type, rela->r_offset); + + return false; + } +} + +static int rela_elf32(char **argv, FILE *f) +{ + int i, num, index; + uint32_t value, type; + + if ((rela_end - rela_start) % sizeof(Elf32_Rela)) { + fprintf(stderr, "%s: rela size isn't a multiple of Elf32_Rela\n", argv[0]); + return 3; + } + + num = (rela_end - rela_start) / sizeof(Elf32_Rela); + + debug("Number of entries: %u\n", num); + + for (i = 0; i < num; i++) { + Elf32_Rela rela, swrela; + Elf32_Sym symbols; + uint32_t pos = rela_start + sizeof(Elf32_Rela) * i; + uint32_t addr, pos_dyn; + + debug("\nPossition:\t%d/0x%x\n", i, pos); + + if (fseek(f, pos, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" PRIx32 + " failed: %s\n", + argv[0], argv[1], pos, strerror(errno)); + } + + if (fread(&rela, sizeof(rela), 1, f) != 1) { + fprintf(stderr, "%s: %s: read rela failed at %" + PRIx32 "\n", + argv[0], argv[1], pos); + return 4; + } + + debug("Rela:\toffset:\t%" PRIx32 " r_info:\t%" + PRIu32 " r_addend:\t%" PRIx32 "\n", + rela.r_offset, rela.r_info, rela.r_addend); + + swrela.r_offset = cpu_to_le32(rela.r_offset); + swrela.r_info = cpu_to_le32(rela.r_info); + swrela.r_addend = cpu_to_le32(rela.r_addend); + + debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%" + PRIu32 " r_addend:\t%" PRIx32 "\n", + swrela.r_offset, swrela.r_info, swrela.r_addend); + + if (!supported_rela32(&swrela, &type)) + continue; + + if (swrela.r_offset < text_base) { + fprintf(stderr, "%s: %s: bad rela at %" PRIx32 "\n", + argv[0], argv[1], pos); + return 4; + } + + addr = swrela.r_offset - text_base; + + debug("Addr:\t0x%" PRIx32 "\n", addr); + + switch (type) { + case R_MICROBLAZE_REL: + if (fseek(f, addr, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" + PRIx32 " failed: %s\n", + argv[0], argv[1], addr, strerror(errno)); + return 5; + } + + debug("Write addend\n"); + + if (fwrite(&rela.r_addend, sizeof(rela.r_addend), 1, f) != 1) { + fprintf(stderr, "%s: %s: write failed at %" PRIx32 "\n", + argv[0], argv[1], addr); + return 4; + } + break; + case R_MICROBLAZE_32: + case R_MICROBLAZE_GLOB_DAT: + /* global symbols read it and add reloc offset */ + index = swrela.r_info >> 8; + pos_dyn = dyn_start + sizeof(Elf32_Sym) * index; + + debug("Index:\t%d\n", index); + debug("Pos_dyn:\t0x%x\n", pos_dyn); + + if (fseek(f, pos_dyn, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" + PRIx32 " failed: %s\n", + argv[0], argv[1], pos_dyn, strerror(errno)); + return 5; + } + + if (fread(&symbols, sizeof(symbols), 1, f) != 1) { + fprintf(stderr, "%s: %s: read symbols failed at %" + PRIx32 "\n", + argv[0], argv[1], pos_dyn); + return 4; + } + + debug("Symbol description:\n"); + debug(" st_name:\t0x%x\n", symbols.st_name); + debug(" st_value:\t0x%x\n", symbols.st_value); + debug(" st_size:\t0x%x\n", symbols.st_size); + + value = swrela.r_addend + symbols.st_value; + + debug("Value:\t0x%x\n", value); + + if (fseek(f, addr, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" + PRIx32 " failed: %s\n", + argv[0], argv[1], addr, strerror(errno)); + return 5; + } + + if (fwrite(&value, sizeof(rela.r_addend), 1, f) != 1) { + fprintf(stderr, "%s: %s: write failed at %" PRIx32 "\n", + argv[0], argv[1], addr); + return 4; + } + + break; + case R_MICROBLAZE_NONE: + debug("R_MICROBLAZE_NONE - skip\n"); + break; + default: + fprintf(stderr, "warning: unsupported relocation type %" + PRIu32 " at %" PRIx32 "\n", + type, rela.r_offset); + } + } + + return 0; +} + +int main(int argc, char **argv) +{ + FILE *f; + int ret; + uint64_t file_size; + + if (argc != 3) { + fprintf(stderr, "Statically apply ELF rela relocations\n"); + fprintf(stderr, "Usage: %s \n", + argv[0]); + return 1; + } + + ret = decode_elf(argv); + if (ret) { + fprintf(stderr, "ELF decoding failed\n"); + return ret; + } + + if (rela_start > rela_end || rela_start < text_base) { + fprintf(stderr, "%s: bad rela bounds\n", argv[0]); + return 3; + } + + rela_start -= text_base; + rela_end -= text_base; + dyn_start -= text_base; + + f = fopen(argv[1], "r+b"); + if (!f) { + fprintf(stderr, "%s: Cannot open %s: %s\n", + argv[0], argv[1], strerror(errno)); + return 2; + } + + fseek(f, 0, SEEK_END); + file_size = ftell(f); + rewind(f); + + if (rela_end > file_size) { + // Most likely compiler inserted some section that didn't get + // objcopy-ed into the final binary + rela_end = file_size; + } + + if (ei_class == 2) + ret = rela_elf64(argv, f); + else + ret = rela_elf32(argv, f); + if (fclose(f) < 0) { fprintf(stderr, "%s: %s: close failed: %s\n", argv[0], argv[1], strerror(errno)); return 4; } - return 0; + return ret; } diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 4ee418f07eac9013016a7e5d294b49046e32a694..16c622f6ce7ffd8615eea62eb77494b20093ba36 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -2,6 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2018 Michal Simek # Copyright (C) 2019 Luca Ceresoli +# Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG +# Stefan Herbrechtsmeier usage() { @@ -119,7 +121,7 @@ tr "\n" "\r" <${OUT} >${TMP} # | | ==> |while (e)| # | } | | ; | # | | -sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP} +sed -i -r 's| \{\r+(\t*)\}\r\r|\r\1\t;\r|g' ${TMP} # Remove empty line between variable declaration sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP} @@ -141,7 +143,30 @@ sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP} # if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...) sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP} +# Move helper functions below header includes +TARGET="#include " +START="static int serdes_rst_seq" +END="static int serdes_enb_coarse_saturation" + +sed -i -e "s|\(${TARGET}\r\r\)\(.*\)\(${START}(.*\)\(${END}(\)|\1\3\2\4|g" \ + ${TMP} + # Convert back newlines tr "\r" "\n" <${TMP} >${OUT} +# Remove unnecessary settings +# - Low level UART +SETTINGS_TO_REMOVE="0xFF000000 +0xFF000004 +0xFF000018 +0xFF000034 +0xFF010000 +0xFF010004 +0xFF010018 +0xFF010034 +" +for i in $SETTINGS_TO_REMOVE; do +sed -i "/^\tpsu_mask_write($i,.*$/d" ${OUT} +done + rm ${TMP}