diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index c572818e7c12a9a4aadafd0748b8c484e625704b..53f86f5184c57df3e45c990791fc9f1533ed5108 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 macos_vm: macOS-10.15 - ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021 + ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -195,6 +195,9 @@ jobs: evb_ast2500: TEST_PY_BD: "evb-ast2500" TEST_PY_ID: "--id qemu" + vexpress_ca9x4: + TEST_PY_BD: "vexpress_ca9x4" + TEST_PY_ID: "--id qemu" integratorcp_cm926ejs: TEST_PY_BD: "integratorcp_cm926ejs" TEST_PY_ID: "--id qemu" @@ -254,6 +257,12 @@ jobs: r2dplus_tulip: TEST_PY_BD: "r2dplus" TEST_PY_ID: "--id tulip_qemu" + sifive_unleashed_sdcard: + TEST_PY_BD: "sifive_unleashed" + TEST_PY_ID: "--id sdcard_qemu" + sifive_unleashed_spi-nor: + TEST_PY_BD: "sifive_unleashed" + TEST_PY_ID: "--id spi-nor_qemu" xilinx_zynq_virt: TEST_PY_BD: "xilinx_zynq_virt" TEST_PY_ID: "--id qemu" @@ -289,7 +298,7 @@ jobs: wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then + if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi @@ -302,6 +311,18 @@ jobs: cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi + # create sdcard / spi-nor images for sifive unleashed using genimage + if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then + mkdir -p root; + cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .; + cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .; + rm -rf tmp; + genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg; + cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/; + rm -rf tmp; + genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg; + cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/; + fi virtualenv -p /usr/bin/python3 /tmp/venv . /tmp/venv/bin/activate pip install -r test/py/requirements.txt diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index aff479eea1af8371a89a72cc5430b05b8b323923..5a3e2f0ceb8562bb5a2ddeb345188ce8c69275f8 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://source.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021 +image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021 # We run some tests in different order, to catch some failures quicker. stages: @@ -23,7 +23,7 @@ stages: wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then + - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi @@ -40,6 +40,18 @@ stages: - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi + # create sdcard / spi-nor images for sifive unleashed using genimage + - if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then + mkdir -p root; + cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .; + cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .; + rm -rf tmp; + genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg; + cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/; + rm -rf tmp; + genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg; + cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/; + fi - virtualenv -p /usr/bin/python3 /tmp/venv - . /tmp/venv/bin/activate - pip install -r test/py/requirements.txt @@ -204,6 +216,12 @@ sandbox_flattree test.py: TEST_PY_BD: "sandbox_flattree" <<: *buildman_and_testpy_dfn +vexpress_ca9x4 test.py: + variables: + TEST_PY_BD: "vexpress_ca9x4" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + integratorcp_cm926ejs test.py: variables: TEST_PY_BD: "integratorcp_cm926ejs" @@ -317,6 +335,18 @@ r2dplus_tulip test.py: TEST_PY_ID: "--id tulip_qemu" <<: *buildman_and_testpy_dfn +sifive_unleashed_sdcard test.py: + variables: + TEST_PY_BD: "sifive_unleashed" + TEST_PY_ID: "--id sdcard_qemu" + <<: *buildman_and_testpy_dfn + +sifive_unleashed_spi-nor test.py: + variables: + TEST_PY_BD: "sifive_unleashed" + TEST_PY_ID: "--id spi-nor_qemu" + <<: *buildman_and_testpy_dfn + xilinx_zynq_virt test.py: variables: TEST_PY_BD: "xilinx_zynq_virt" diff --git a/.mailmap b/.mailmap index b09fc321bd6174de80106775196876e1ff5c2fe1..93533d96b5425a55adef187a5804cfef6f881c5c 100644 --- a/.mailmap +++ b/.mailmap @@ -29,6 +29,7 @@ Jagan Teki Jagan Teki Jagan Teki Jagan Teki +Jernej Skrabec Igor Opaniuk Igor Opaniuk Markus Klotzbuecher diff --git a/Kconfig b/Kconfig index a6c42b902f7d5249179f1c6807f60adbad0bfae3..931a22806e4ea54c0255319a18f2426e94dc067d 100644 --- a/Kconfig +++ b/Kconfig @@ -83,7 +83,6 @@ config CC_OPTIMIZE_FOR_SIZE config OPTIMIZE_INLINING bool "Allow compiler to uninline functions marked 'inline' in full U-Boot" - default n help This option determines if U-Boot forces gcc to inline the functions developers have marked 'inline'. Doing so takes away freedom from gcc to @@ -93,7 +92,6 @@ config OPTIMIZE_INLINING config SPL_OPTIMIZE_INLINING bool "Allow compiler to uninline functions marked 'inline' in SPL" depends on SPL - default n help This option determines if U-Boot forces gcc to inline the functions developers have marked 'inline'. Doing so takes away freedom from gcc to @@ -106,7 +104,6 @@ config ARCH_SUPPORTS_LTO config LTO bool "Enable Link Time Optimizations" depends on ARCH_SUPPORTS_LTO - default n help This option enables Link Time Optimization (LTO), a mechanism which allows the compiler to optimize between different compilation units. @@ -127,7 +124,6 @@ config LTO config TPL_OPTIMIZE_INLINING bool "Allow compiler to uninline functions marked 'inline' in TPL" depends on TPL - default n help This option determines if U-Boot forces gcc to inline the functions developers have marked 'inline'. Doing so takes away freedom from gcc to @@ -249,8 +245,11 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" - depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP - default 0x2000000 if ARCH_ROCKCHIP + default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON + default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S + default 0x200000 if ARCH_BMIPS || X86 + default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S + default 0x400000 help This defines memory to be allocated for Dynamic allocation TODO: Use for other architectures @@ -307,7 +306,6 @@ if EXPERT config SYS_MALLOC_DEFAULT_TO_INIT bool "Default malloc to init while reserving the memory for it" - default n help It may happen that one needs to move the dynamic allocation from one to another memory range, eg. when moving the malloc @@ -389,6 +387,20 @@ config SYS_LDSCRIPT Path within the source tree to the linker script to use for the main U-Boot binary. +config SYS_LOAD_ADDR + hex "Address in memory to use by default" + default 0x01000000 if ARCH_SOCFPGA + default 0x02000000 if PPC || X86 + default 0x22000000 if MACH_SUN9I + default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I + default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3 + default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) + default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) + default 0x80800000 if ARCH_MX7 + default 0x90000000 if FSL_LSCH2 || FSL_LSCH3 + help + Address in memory to use as the default safe load address. + config ERR_PTR_OFFSET hex default 0x0 @@ -423,7 +435,6 @@ config SYS_HAS_SRAM default y if TARGET_PIC32MZDASK default y if TARGET_DEVKIT8000 default y if TARGET_TRICORDER - default n help Enable this to allow support for the on board SRAM. SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. diff --git a/Licenses/lgpl-2.0.txt b/Licenses/lgpl-2.0.txt index 5bc8fb2c8f757e34a0d8f4644f589d57609e213f..12735e6c21959f1c5db16aac184480f94697ef7f 100644 --- a/Licenses/lgpl-2.0.txt +++ b/Licenses/lgpl-2.0.txt @@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based on the Library (independent of the use of the Library in a tool for writing it). Whether that is true depends on what the Library does and what the program that uses the Library does. - + 1. You may copy and distribute verbatim copies of the Library's complete source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an diff --git a/MAINTAINERS b/MAINTAINERS index 5370b550648eac728c3408f8e73269204fef79ba..31b49c0a95f0420e2944d64c9044412d8d4a0a8a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -312,6 +312,7 @@ F: arch/arm/mach-at91/ F: board/atmel/ F: drivers/cpu/at91_cpu.c F: drivers/misc/microchip_flexcom.c +F: include/dt-bindings/mfd/atmel-flexcom.h F: drivers/timer/mchp-pit64b-timer.c ARM NEXELL S5P4418 @@ -525,7 +526,12 @@ R: Linus Walleij S: Maintained F: arch/arm/dts/ste-* F: arch/arm/mach-u8500/ +F: drivers/gpio/nmk_gpio.c +F: drivers/phy/phy-ab8500-usb.c +F: drivers/power/pmic/ab8500.c F: drivers/timer/nomadik-mtu-timer.c +F: drivers/usb/musb-new/ux500.c +F: drivers/video/mcde_simple.c ARM UNIPHIER S: Orphan (Since 2020-09) @@ -769,6 +775,16 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git F: drivers/i2c/ +KWBIMAGE / KWBOOT TOOLS +M: Pali Rohár +M: Marek Behún +M: Stefan Roese +S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git +F: doc/README.kwbimage +F: doc/kwboot.1 +F: tools/kwb* + LOGGING M: Simon Glass S: Maintained diff --git a/Makefile b/Makefile index 20c1aa3f58a5aa673240e5ecd6137f3a7a963e71..d8241aa79c88c0bbd75d96e2f7f71a69fee95e96 100644 --- a/Makefile +++ b/Makefile @@ -327,14 +327,14 @@ os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \ $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \ - $(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) + $(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) # Snow Leopards build environment has no longer restrictions as described above HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") KBUILD_HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") -# macOS Mojave (10.14.X) +# macOS Mojave (10.14.X) # Undefined symbols for architecture x86_64: "_PyArg_ParseTuple" KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "") endif @@ -813,23 +813,9 @@ libs-y += fs/ libs-y += net/ libs-y += disk/ libs-y += drivers/ -libs-y += drivers/dma/ -libs-y += drivers/gpio/ -libs-y += drivers/net/ -libs-y += drivers/net/phy/ -libs-y += drivers/power/ \ - drivers/power/domain/ \ - drivers/power/fuel_gauge/ \ - drivers/power/mfd/ \ - drivers/power/pmic/ \ - drivers/power/battery/ \ - drivers/power/regulator/ -libs-y += drivers/spi/ -libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/ -libs-y += drivers/serial/ libs-y += drivers/usb/cdns3/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/common/ @@ -1306,10 +1292,6 @@ u-boot.ldr: u-boot # Use 'make BINMAN_VERBOSE=3' to set vebosity level default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE)) -# Tell binman whether we have a devicetree for SPL and TPL -have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL)) -have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL)) - quiet_cmd_binman = BINMAN $@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ --toolpath $(objtree)/tools \ @@ -1323,7 +1305,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ -a scp-path=$(SCP) \ -a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \ -a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \ - -a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \ + -a spl-dtb=$(CONFIG_SPL_OF_REAL) \ + -a tpl-dtb=$(CONFIG_SPL_OF_REAL) \ $(BINMAN_$(@F)) OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex @@ -1756,7 +1739,7 @@ endif # May be overridden by arch/$(ARCH)/config.mk ifdef CONFIG_LTO quiet_cmd_u-boot__ ?= LTO $@ - cmd_u-boot__ ?= \ + cmd_u-boot__ ?= \ $(CC) -nostdlib -nostartfiles \ $(LTO_FINAL_LDFLAGS) $(c_flags) \ $(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \ diff --git a/README b/README index a3f81e4aed02576c6d38ae495e4791b160de562c..9a81de300b266544fcad17c7f67bd40a10f9cfb2 100644 --- a/README +++ b/README @@ -300,7 +300,6 @@ board_init_r(): - loads U-Boot or (in falcon mode) Linux - Configuration Options: ---------------------- @@ -465,10 +464,6 @@ The following options need to be configured: Board config to use DDR3L. It can be enabled for SoCs with DDR3L controllers. - CONFIG_SYS_FSL_DDR4 - Board config to use DDR4. It can be enabled for SoCs with - DDR4 controllers. - CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian @@ -481,15 +476,6 @@ The following options need to be configured: CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). - CONFIG_SYS_FSL_PBL_PBI - It enables addition of RCW (Power on reset configuration) in built image. - Please refer doc/README.pblimage for more details - - CONFIG_SYS_FSL_PBL_RCW - It adds PBI(pre-boot instructions) commands in u-boot build image. - PBI commands can be used to configure SoC before it starts the execution. - Please refer doc/README.pblimage for more details - CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian @@ -599,16 +585,6 @@ The following options need to be configured: crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. - CONFIG_MACH_TYPE [relevant for ARM only][mandatory] - - This setting is mandatory for all boards that have only one - machine type and must be used to specify the machine type - number as it appears in the ARM machine registry - (see https://www.arm.linux.org.uk/developer/machines/). - Only boards that have multiple machine types supported - in a single configuration file and the machine type is - runtime discoverable, do not have to use this setting. - - vxWorks boot parameters: bootvx constructs a valid bootline using the following @@ -671,11 +647,6 @@ The following options need to be configured: time on others. This setting #define's the initial value of the "loads_echo" environment variable. -- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined) - CONFIG_KGDB_BAUDRATE - Select one of the baudrates listed in - CONFIG_SYS_BAUDRATE_TABLE, see below. - - Removal of commands If no commands are needed to boot, you can disable CONFIG_CMDLINE to remove them. In this case, the command line @@ -879,17 +850,6 @@ The following options need to be configured: Support for National dp8382[01] gigabit chips. - NETWORK Support (other): - - CONFIG_DRIVER_AT91EMAC - Support for AT91RM9200 EMAC. - - CONFIG_RMII - Define this to use reduced MII inteface - - CONFIG_DRIVER_AT91EMAC_QUIET - If this defined, the driver is quiet. - The driver doen't show link status messages. - CONFIG_CALXEDA_XGMAC Support for the Calxeda XGMAC device @@ -1461,129 +1421,7 @@ The following options need to be configured: In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined with a list of GPIO LEDs that have inverted polarity. -- I2C Support: CONFIG_SYS_I2C_LEGACY - - Note: This is deprecated in favour of driver model. Use - CONFIG_DM_I2C instead. - - This enable the legacy i2c subsystem, and will allow you to use - i2c commands at the u-boot command line (as long as you set - CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE - for defining speed and slave address - - activate second bus with I2C_SOFT_DECLARATIONS2 define - CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2 - for defining speed and slave address - - activate third bus with I2C_SOFT_DECLARATIONS3 define - CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3 - for defining speed and slave address - - activate fourth bus with I2C_SOFT_DECLARATIONS4 define - CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4 - for defining speed and slave address - - - drivers/i2c/fsl_i2c.c: - - activate i2c driver with CONFIG_SYS_I2C_FSL - define CONFIG_SYS_FSL_I2C_OFFSET for setting the register - offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and - CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first - bus. - - If your board supports a second fsl i2c bus, define - CONFIG_SYS_FSL_I2C2_OFFSET for the register offset - CONFIG_SYS_FSL_I2C2_SPEED for the speed and - CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the - second bus. - - - drivers/i2c/tegra_i2c.c: - - activate this driver with CONFIG_SYS_I2C_TEGRA - - This driver adds 4 i2c buses with a fix speed from - 100000 and the slave addr 0! - - - drivers/i2c/ppc4xx_i2c.c - - activate this driver with CONFIG_SYS_I2C_PPC4XX - - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0 - - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1 - - - drivers/i2c/i2c_mxc.c - - activate this driver with CONFIG_SYS_I2C_MXC - - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 - - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE - - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED - - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE - If those defines are not set, default value is 100000 - for speed, and 0 for slave. - - - drivers/i2c/rcar_i2c.c: - - activate this driver with CONFIG_SYS_I2C_RCAR - - This driver adds 4 i2c buses - - - drivers/i2c/sh_i2c.c: - - activate this driver with CONFIG_SYS_I2C_SH - - This driver adds from 2 to 5 i2c buses - - - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 - - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 - - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 - - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 - - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 - - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 - - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 - - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 - - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 - - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 - - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses - - - drivers/i2c/omap24xx_i2c.c - - activate this driver with CONFIG_SYS_I2C_OMAP24XX - - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 - - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 - - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 - - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 - - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 - - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 - - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 - - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 - - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 - - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 - - - drivers/i2c/s3c24x0_i2c.c: - - activate this driver with CONFIG_SYS_I2C_S3C24X0 - - This driver adds i2c buses (11 for Exynos5250, Exynos5420 - 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung) - with a fix speed from 100000 and the slave addr 0! - - - drivers/i2c/ihs_i2c.c - - activate this driver with CONFIG_SYS_I2C_IHS - - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0 - - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0 - - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0 - - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1 - - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1 - - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1 - - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2 - - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2 - - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2 - - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 - - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 - - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 - - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL - - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1 - - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1 - - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1 - - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1 - - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1 - - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1 - - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1 - - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1 - - additional defines: - +- I2C Support: CONFIG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. @@ -2873,22 +2711,6 @@ Low Level (hardware related) configuration options: This only takes effect if the memory commands are activated globally (CONFIG_CMD_MEMORY). -- CONFIG_SKIP_LOWLEVEL_INIT - [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain - low level initializations (like setting up the memory - controller) are omitted and/or U-Boot does not - relocate itself into RAM. - - Normally this variable MUST NOT be defined. The only - exception is when U-Boot is loaded (to RAM) by some - other boot loader or by a debugger which performs - these initializations itself. - -- CONFIG_SKIP_LOWLEVEL_INIT_ONLY - [ARM926EJ-S only] This allows just the call to lowlevel_init() - to be skipped. The normal CP15 init (such as enabling the - instruction cache) is still performed. - - CONFIG_SPL_BUILD Set when the currently-running compilation is for an artifact that will end up in the SPL (as opposed to the TPL or U-Boot diff --git a/api/Kconfig b/api/Kconfig index 16731d3b4b31d15b50b4d14beea66fbc07233cc4..382aa4ad3f02cb82aa777216854cb3d9cdf78925 100644 --- a/api/Kconfig +++ b/api/Kconfig @@ -2,7 +2,6 @@ menu "API" config API bool "Enable U-Boot API" - default n help This option enables the U-Boot API. See api/README for more information. diff --git a/arch/Kconfig b/arch/Kconfig index 8f8daadcf92b561d6b3a4a41c8555ae27c701a21..3e2cc84ab2c45d33f456b9e5ac12bc791219c805 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -7,6 +7,27 @@ config HAVE_ARCH_IOREMAP config NEEDS_MANUAL_RELOC bool +config SYS_CACHE_SHIFT_4 + bool + +config SYS_CACHE_SHIFT_5 + bool + +config SYS_CACHE_SHIFT_6 + bool + +config SYS_CACHE_SHIFT_7 + bool + +config SYS_CACHELINE_SIZE + int + default 128 if SYS_CACHE_SHIFT_7 + default 64 if SYS_CACHE_SHIFT_6 + default 32 if SYS_CACHE_SHIFT_5 + default 16 if SYS_CACHE_SHIFT_4 + # Fall-back for MIPS + default 32 if MIPS + config LINKER_LIST_ALIGN int default 32 if SANDBOX @@ -29,6 +50,7 @@ config ARC select DM select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL + select SYS_CACHE_SHIFT_7 select TIMER config ARM @@ -44,6 +66,7 @@ config M68K select NEEDS_MANUAL_RELOC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD + select SYS_CACHE_SHIFT_4 select SUPPORT_OF_CONTROL config MICROBLAZE @@ -97,7 +120,7 @@ config RISCV imply SPL_OF_CONTROL imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_TIMER config SANDBOX @@ -122,6 +145,7 @@ config SANDBOX select SPI select SUPPORT_OF_CONTROL select SYSRESET_CMD_POWEROFF + select SYS_CACHE_SHIFT_4 select IRQ select SUPPORT_EXTENSION_SCAN imply BITREVERSE @@ -187,6 +211,7 @@ config X86 select OF_CONTROL select PCI select SUPPORT_OF_CONTROL + select SYS_CACHE_SHIFT_6 select TIMER select USE_PRIVATE_LIBGCC select X86_TSC_TIMER @@ -233,9 +258,9 @@ config X86 imply SPL_PINCTRL imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_SPI_FLASH_SUPPORT - imply SPL_SPI_SUPPORT + imply SPL_SPI imply SPL_OF_CONTROL imply SPL_TIMER imply SPL_REGMAP @@ -247,7 +272,7 @@ config X86 imply TPL_PINCTRL imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_OF_CONTROL imply TPL_TIMER imply TPL_REGMAP @@ -325,6 +350,63 @@ config SYS_DISABLE_DCACHE_OPS Note that, its up to the individual architectures to implement this functionality. +config SKIP_LOWLEVEL_INIT + bool "Skip the calls to certain low level initialization functions" + depends on ARM || NDS32 || MIPS || RISCV + help + If enabled, then certain low level initializations (like setting up + the memory controller) are omitted and/or U-Boot does not relocate + itself into RAM. + Normally this variable MUST NOT be defined. The only exception is + when U-Boot is loaded (to RAM) by some other boot loader or by a + debugger which performs these initializations itself. + +config SPL_SKIP_LOWLEVEL_INIT + bool "Skip the calls to certain low level initialization functions" + depends on SPL && (ARM || NDS32 || MIPS || RISCV) + help + If enabled, then certain low level initializations (like setting up + the memory controller) are omitted and/or U-Boot does not relocate + itself into RAM. + Normally this variable MUST NOT be defined. The only exception is + when U-Boot is loaded (to RAM) by some other boot loader or by a + debugger which performs these initializations itself. + +config TPL_SKIP_LOWLEVEL_INIT + bool "Skip the calls to certain low level initialization functions" + depends on SPL && ARM + help + If enabled, then certain low level initializations (like setting up + the memory controller) are omitted and/or U-Boot does not relocate + itself into RAM. + Normally this variable MUST NOT be defined. The only exception is + when U-Boot is loaded (to RAM) by some other boot loader or by a + debugger which performs these initializations itself. + +config SKIP_LOWLEVEL_INIT_ONLY + bool "Skip the call to lowlevel_init during early boot ONLY" + depends on ARM + help + This allows just the call to lowlevel_init() to be skipped. The + normal CP15 init (such as enabling the instruction cache) is still + performed. + +config SPL_SKIP_LOWLEVEL_INIT_ONLY + bool "Skip the call to lowlevel_init during early boot ONLY" + depends on SPL && ARM + help + This allows just the call to lowlevel_init() to be skipped. The + normal CP15 init (such as enabling the instruction cache) is still + performed. + +config TPL_SKIP_LOWLEVEL_INIT_ONLY + bool "Skip the call to lowlevel_init during early boot ONLY" + depends on TPL && ARM + help + This allows just the call to lowlevel_init() to be skipped. The + normal CP15 init (such as enabling the instruction cache) is still + performed. + source "arch/arc/Kconfig" source "arch/arm/Kconfig" source "arch/m68k/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 6ff201fa81678fab7d0bd70eb4663073dc347520..1a7c525cdb96f0ce8a501e0d5aad13c570a625bf 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -104,13 +104,11 @@ endchoice config CPU_BIG_ENDIAN bool "Enable Big Endian Mode" - default n help Build kernel for Big Endian Mode of ARC CPU config SYS_ICACHE_OFF bool "Do not enable icache" - default n help Do not enable instruction cache in U-Boot. @@ -123,7 +121,6 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" - default n help Do not enable data cache in U-Boot. @@ -136,14 +133,12 @@ config SPL_SYS_DCACHE_OFF menuconfig ARC_DBG bool "ARC debugging" - default n if ARC_DBG config ARC_DBG_IOC_ENABLE bool "Enable IO coherency unit" depends on CPU_ARCHS38 - default n help Enable IO coherency unit to debug problems with caches and DMA peripherals. diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index ab61846b5ab9983cebc1f0bfdc3fe4e88b24ff12..a48e1aec6889e0d2578085a67c295aca5ac06054 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -16,9 +16,6 @@ */ #define ARCH_DMA_MINALIGN 128 -/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */ -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN - #if defined(ARC_MMU_ABSENT) #define CONFIG_ARC_MMU_VER 0 #elif defined(CONFIG_ARC_MMU_V2) diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 8a8d394a5f0cb745ebd6821c9e9a1873bd7d0635..41408c2b4607bf179a533d430a371fb8e9896f0b 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -8,42 +8,12 @@ #include #include #include -#include #include #include #include DECLARE_GLOBAL_DATA_PTR; -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - ulong sp; - - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); -} - static int cleanup_before_linux(void) { disable_interrupts(); diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index f807cd83d6b548783b8fcae1732669fd6b6d5dea..4c696cb53a48732857df40954140bdeb05f37d94 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -820,3 +821,16 @@ void sync_n_cleanup_cache_all(void) __ic_entire_invalidate(); } + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/arc/lib/libgcc2.h b/arch/arc/lib/libgcc2.h index 9c3ce99892784b982d7678d82a5354c3ca665ad9..95eb9b05241b02a601a3c011562fb90049080509 100644 --- a/arch/arc/lib/libgcc2.h +++ b/arch/arc/lib/libgcc2.h @@ -35,7 +35,7 @@ typedef int HItype __attribute__ ((mode (HI))); typedef unsigned int UHItype __attribute__ ((mode (HI))); #if MIN_UNITS_PER_WORD > 1 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */ -typedef int SItype __attribute__ ((mode (SI))); +typedef int SItype __attribute__ ((mode (SI))); typedef unsigned int USItype __attribute__ ((mode (SI))); #if __SIZEOF_LONG_LONG__ > 4 /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5bd3284cd1cc565777cddbdcf3a43d69a51b4ae..ebb19272708d18506fb9d8d7e5094e016ce51856 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -9,9 +9,19 @@ config ARM64 select PHYS_64BIT select SYS_CACHE_SHIFT_6 -if ARM64 +config ARM64_CRC32 + bool "Enable support for CRC32 instruction" + depends on ARM64 + default y + help + ARMv8 implements dedicated crc32 instruction for crc32 calculation. + This is faster than software crc32 calculation. This instruction may + not be present on all ARMv8.0, but is always present on ARMv8.1 and + newer. + config POSITION_INDEPENDENT bool "Generate position-independent pre-relocation code" + depends on ARM64 || CPU_V7A help U-Boot expects to be linked to a specific hard-coded address, and to be loaded to and run from that address. This option lifts that @@ -22,6 +32,7 @@ config POSITION_INDEPENDENT config INIT_SP_RELATIVE bool "Specify the early stack pointer relative to the .bss section" + depends on ARM64 default n if ARCH_QEMU default y if POSITION_INDEPENDENT help @@ -37,6 +48,7 @@ config INIT_SP_RELATIVE config SYS_INIT_SP_BSS_OFFSET int "Early stack offset from the .bss base address" + depends on ARM64 depends on INIT_SP_RELATIVE default 524288 help @@ -46,6 +58,7 @@ config SYS_INIT_SP_BSS_OFFSET do not overlap any appended DTB. config LINUX_KERNEL_IMAGE_HEADER + depends on ARM64 bool help Place a Linux kernel image header at the start of the U-Boot binary. @@ -54,14 +67,18 @@ config LINUX_KERNEL_IMAGE_HEADER image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but which isn't part of the binary. -if LINUX_KERNEL_IMAGE_HEADER config LNX_KRNL_IMG_TEXT_OFFSET_BASE + depends on LINUX_KERNEL_IMAGE_HEADER hex help The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the TEXT_OFFSET value written to the Linux kernel image header. -endif -endif + +config GICV2 + bool + +config GICV3 + bool config GIC_V3_ITS bool "ARM GICV3 ITS" @@ -104,7 +121,6 @@ config THUMB2_KERNEL config SYS_ICACHE_OFF bool "Do not enable icache" - default n help Do not enable instruction cache in U-Boot. @@ -117,7 +133,6 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" - default n help Do not enable data cache in U-Boot. @@ -332,21 +347,6 @@ config SYS_ARM_ARCH default 4 if CPU_SA1100 default 8 if ARM64 -config SYS_CACHE_SHIFT_5 - bool - -config SYS_CACHE_SHIFT_6 - bool - -config SYS_CACHE_SHIFT_7 - bool - -config SYS_CACHELINE_SIZE - int - default 128 if SYS_CACHE_SHIFT_7 - default 64 if SYS_CACHE_SHIFT_6 - default 32 if SYS_CACHE_SHIFT_5 - choice prompt "Select the ARM data write cache policy" default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ @@ -452,12 +452,11 @@ config ENABLE_ARM_SOC_BOOT0_HOOK config ARM_CORTEX_CPU_IS_UP bool - default n config USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy" - default y - depends on !ARM64 + default y if !ARM64 + depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400)) help Enable the generation of an optimized version of memcpy. Such an implementation may be faster under some conditions @@ -466,7 +465,7 @@ config USE_ARCH_MEMCPY config SPL_USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy for SPL" default y if USE_ARCH_MEMCPY - depends on !ARM64 && SPL + depends on SPL help Enable the generation of an optimized version of memcpy. Such an implementation may be faster under some conditions @@ -475,16 +474,43 @@ config SPL_USE_ARCH_MEMCPY config TPL_USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy for TPL" default y if USE_ARCH_MEMCPY - depends on !ARM64 && TPL + depends on TPL help Enable the generation of an optimized version of memcpy. Such an implementation may be faster under some conditions but may increase the binary size. +config USE_ARCH_MEMMOVE + bool "Use an assembly optimized implementation of memmove" if !ARM64 + default USE_ARCH_MEMCPY if ARM64 + depends on ARM64 + help + Enable the generation of an optimized version of memmove. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config SPL_USE_ARCH_MEMMOVE + bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64 + default SPL_USE_ARCH_MEMCPY if ARM64 + depends on SPL && ARM64 + help + Enable the generation of an optimized version of memmove. + Such an implementation may be faster under some conditions + but may increase the binary size. + +config TPL_USE_ARCH_MEMMOVE + bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64 + default TPL_USE_ARCH_MEMCPY if ARM64 + depends on TPL && ARM64 + help + Enable the generation of an optimized version of memmove. + Such an implementation may be faster under some conditions + but may increase the binary size. + config USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset" - default y - depends on !ARM64 + default y if !ARM64 + depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400)) help Enable the generation of an optimized version of memset. Such an implementation may be faster under some conditions @@ -493,7 +519,7 @@ config USE_ARCH_MEMSET config SPL_USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset for SPL" default y if USE_ARCH_MEMSET - depends on !ARM64 && SPL + depends on SPL help Enable the generation of an optimized version of memset. Such an implementation may be faster under some conditions @@ -502,7 +528,7 @@ config SPL_USE_ARCH_MEMSET config TPL_USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset for TPL" default y if USE_ARCH_MEMSET - depends on !ARM64 && TPL + depends on TPL help Enable the generation of an optimized version of memset. Such an implementation may be faster under some conditions @@ -525,11 +551,6 @@ config ARCH_AT91 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL -config TARGET_ASPENITE - bool "Support aspenite" - select CPU_ARM926EJS - select GPIO_EXTRA_HEADER - config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS @@ -579,11 +600,6 @@ config TARGET_STV0991 select SPI_FLASH imply CMD_DM -config TARGET_FLEA3 - bool "Support flea3" - select CPU_ARM1136 - select GPIO_EXTRA_HEADER - config ARCH_BCM283X bool "Broadcom BCM283X family" select DM @@ -626,6 +642,11 @@ config ARCH_BCMSTB This enables support for Broadcom ARM-based set-top box chipsets, including the 7445 family of chips. +config TARGET_VEXPRESS_CA9X4 + bool "Support vexpress_ca9x4" + select CPU_V7A + select PL011_SERIAL + config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A @@ -723,6 +744,7 @@ config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF select CPU_V7A + select DDR_SPD select GPIO_EXTRA_HEADER select SUPPORT_SPL select SYS_ARCH_TIMER @@ -787,6 +809,7 @@ config ARCH_IMX8 select ARM64 select DM select GPIO_EXTRA_HEADER + select MACH_IMX select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK @@ -794,9 +817,11 @@ config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select SYS_I2C_MXC select DM select SUPPORT_SPL imply CMD_DM @@ -805,6 +830,7 @@ config ARCH_IMX8ULP bool "NXP i.MX8ULP platform" select ARM64 select DM + select MACH_IMX select OF_CONTROL select SUPPORT_SPL select GPIO_EXTRA_HEADER @@ -816,6 +842,7 @@ config ARCH_IMXRT select DM select DM_SERIAL select GPIO_EXTRA_HEADER + select MACH_IMX select SUPPORT_SPL imply CMD_DM @@ -823,31 +850,29 @@ config ARCH_MX23 bool "NXP i.MX23 family" select CPU_ARM926EJS select GPIO_EXTRA_HEADER + select MACH_IMX select PL011_SERIAL select SUPPORT_SPL -config ARCH_MX25 - bool "NXP MX25" - select CPU_ARM926EJS - select GPIO_EXTRA_HEADER - imply MXC_GPIO - config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS select GPIO_EXTRA_HEADER select PL011_SERIAL + select MACH_IMX select SUPPORT_SPL config ARCH_MX31 bool "NXP i.MX31 family" select CPU_ARM1136 select GPIO_EXTRA_HEADER + select MACH_IMX config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -860,6 +885,7 @@ config ARCH_MX7 select ARCH_MISC_INIT select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -871,6 +897,7 @@ config ARCH_MX6 bool "Freescale MX6" select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -887,6 +914,7 @@ config ARCH_MX5 select BOARD_EARLY_INIT_F select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX imply MXC_GPIO config ARCH_NEXELL @@ -952,6 +980,7 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GICV2 select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL @@ -962,7 +991,7 @@ config ARCH_SOCFPGA select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG select SUPPORT_SPL @@ -982,11 +1011,11 @@ config ARCH_SOCFPGA imply SPL_DM_SPI imply SPL_DM_SPI_FLASH imply SPL_LIBDISK_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT - imply SPL_SPI_SUPPORT + imply SPL_SPI imply L2X0_CACHE config ARCH_SUNXI @@ -1032,9 +1061,9 @@ config ARCH_SUNXI imply SPL_GPIO imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT if MMC + imply SPL_MMC if MMC imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply USB_GADGET config ARCH_U8500 @@ -1044,14 +1073,22 @@ config ARCH_U8500 select DM_GPIO select DM_MMC if MMC select DM_SERIAL + select DM_USB_GADGET if DM_USB select OF_CONTROL select SYSRESET select TIMER + imply AB8500_USB_PHY imply ARM_PL180_MMCI + imply CLK + imply DM_PMIC imply DM_RTC + imply NOMADIK_GPIO imply NOMADIK_MTU_TIMER + imply PHY imply PL01X_SERIAL + imply PMIC_AB8500 imply RTC_PL031 + imply SYS_THUMB_BUILD imply SYSRESET_SYSCON config ARCH_VERSAL @@ -1062,6 +1099,7 @@ config ARCH_VERSAL select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GICV3 select GPIO_EXTRA_HEADER select OF_CONTROL select SOC_DEVICE @@ -1072,6 +1110,7 @@ config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS imply MTD_RAW_NAND @@ -1131,6 +1170,7 @@ config ARCH_ZYNQMP select DM_SPI if SPI select DM_SPI_FLASH if DM_SPI select FIRMWARE + select GICV2 select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_BOARD_INIT if SPL @@ -1880,6 +1920,7 @@ config TARGET_DURIAN config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 + select GICV2 config TARGET_XENGUEST_ARM64 bool "Xen guest ARM64" @@ -1891,13 +1932,56 @@ config TARGET_XENGUEST_ARM64 select SSCANF endchoice +config SUPPORT_PASSING_ATAGS + bool "Support pre-devicetree ATAG-based booting" + depends on !ARM64 + imply SETUP_MEMORY_TAGS + help + Support for booting older Linux kernels, using ATAGs rather than + passing a devicetree. This is option is rarely used, and the + semantics are defined at + https://www.kernel.org/doc/Documentation/arm/Booting at section 4a. + +config SETUP_MEMORY_TAGS + bool "Pass memory size information via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config CMDLINE_TAG + bool "Pass Linux kernel cmdline via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config INITRD_TAG + bool "Pass initrd starting point and size via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config REVISION_TAG + bool "Pass system revision via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config SERIAL_TAG + bool "Pass system serial number via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config STATIC_MACH_TYPE + bool "Statically define the Machine ID number" + help + When booting via ATAGs, enable this option if we know the correct + machine ID number to use at compile time. Some systems will be + passed the number dynamically by whatever loads U-Boot. + +config MACH_TYPE + int "Machine ID number" + depends on STATIC_MACH_TYPE + help + When booting via ATAGs, the machine type must be passed as a number. + For the full list see https://www.arm.linux.org.uk/developer/machines + config ARCH_SUPPORT_TFABOOT bool config TFABOOT bool "Support for booting from TF-A" depends on ARCH_SUPPORT_TFABOOT - default n help Some platforms support the setup of secure registers (for instance for CPU errata handling) or provide secure services like PSCI. @@ -1966,8 +2050,6 @@ source "arch/arm/mach-octeontx2/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" -source "arch/arm/mach-imx/mx2/Kconfig" - source "arch/arm/mach-imx/mx3/Kconfig" source "arch/arm/mach-imx/mx5/Kconfig" @@ -2048,10 +2130,9 @@ source "board/armltd/total_compute/Kconfig" source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" -source "board/CarMediaLab/flea3/Kconfig" -source "board/Marvell/aspenite/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" +source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcm963158/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c68e598a675b96647abd36f0a2a07bbb17868df6..6c9a00c5a481e01e80765ce9897966c655e029c5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,7 +18,11 @@ arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7)) arch-$(CONFIG_CPU_V7M) =-march=armv7-m arch-$(CONFIG_CPU_V7R) =-march=armv7-r +ifeq ($(CONFIG_ARM64_CRC32),y) +arch-$(CONFIG_ARM64) =-march=armv8-a+crc +else arch-$(CONFIG_ARM64) =-march=armv8-a +endif # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH @@ -107,7 +111,7 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) libs-y += arch/arm/mach-imx/ endif else diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 16c63e12667ebccbf3b891c67e4f9b005cecb7ca..b107b1af27ac07571144532eda80fb86c9b223c1 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -25,6 +25,7 @@ endif PLATFORM_RELFLAGS += -fno-common -ffixed-r9 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ + $(call cc-option,-mgeneral-regs-only) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) # LLVM support @@ -158,7 +159,8 @@ ifdef CONFIG_EFI_LOADER OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel endif -ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_MACH_IMX +ifneq ($(CONFIG_IMX_CONFIG),"") ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD INPUTS-y += SPL @@ -174,6 +176,7 @@ ifneq ($(CONFIG_VF610),) INPUTS-y += u-boot.vyb endif endif +endif EFI_LDS := elf_arm_efi.lds EFI_CRT0 := crt0_arm_efi.o diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile index 24c33861cbfa9dac39ba739eb6d68ddba9b8ed3b..68d686a5dc775b90d73ab0d1fbe24c23f0cc0e6c 100644 --- a/arch/arm/cpu/arm1136/Makefile +++ b/arch/arm/cpu/arm1136/Makefile @@ -7,4 +7,3 @@ extra-y = start.o obj-y += ../arm11/ obj-$(CONFIG_MX31) += mx31/ -obj-$(CONFIG_MX35) += mx35/ diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile deleted file mode 100644 index 36568f99e1befc447feae9b690f685e5a8c22673..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm1136/mx35/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y += generic.o -obj-y += timer.o -obj-y += mx35_sdram.o -obj-y += relocate.o diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c deleted file mode 100644 index cbf76ab4feec57bed2b6ef576a4c5751668d7da5..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_FSL_ESDHC_IMX -#include -#endif -#include -#include - -#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) -#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) -#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) -#define CLK_CODE_PATH(c) ((c) & 0xFF) - -#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) - -#ifdef CONFIG_FSL_ESDHC_IMX -DECLARE_GLOBAL_DATA_PTR; -#endif - -static int g_clk_mux_auto[8] = { - CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, - CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, -}; - -static int g_clk_mux_consumer[16] = { - CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, - -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), - CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, - -1, -1, CLK_CODE(4, 2, 0), -1, -}; - -static int hsp_div_table[3][16] = { - {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, - {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, - {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, -}; - -u32 get_cpu_rev(void) -{ - int reg; - struct iim_regs *iim = - (struct iim_regs *)IIM_BASE_ADDR; - reg = readl(&iim->iim_srev); - if (!reg) { - reg = readw(ROMPATCH_REV); - reg <<= 4; - } else { - reg += CHIP_REV_1_0; - } - - return 0x35000 + (reg & 0xFF); -} - -static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) -{ - int *pclk_mux; - if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { - pclk_mux = g_clk_mux_consumer + - ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> - MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); - } else { - pclk_mux = g_clk_mux_auto + - ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> - MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); - } - - if ((*pclk_mux) == -1) - return -1; - - if (fi && fd) { - if (!CLK_CODE_PATH(*pclk_mux)) { - *fi = *fd = 1; - return CLK_CODE_ARM(*pclk_mux); - } - if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { - *fi = 3; - *fd = 4; - } else { - *fi = 2; - *fd = 3; - } - } - return CLK_CODE_ARM(*pclk_mux); -} - -static int get_ahb_div(u32 pdr0) -{ - int *pclk_mux; - - pclk_mux = g_clk_mux_consumer + - ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> - MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); - - if ((*pclk_mux) == -1) - return -1; - - return CLK_CODE_AHB(*pclk_mux); -} - -static u32 decode_pll(u32 reg, u32 infreq) -{ - u32 mfi = (reg >> 10) & 0xf; - s32 mfn = reg & 0x3ff; - u32 mfd = (reg >> 16) & 0x3ff; - u32 pd = (reg >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - mfn = mfn >= 512 ? mfn - 1024 : mfn; - mfd += 1; - pd += 1; - - return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), - mfd * pd); -} - -static u32 get_mcu_main_clk(void) -{ - u32 arm_div = 0, fi = 0, fd = 0; - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); - fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); - return fi / (arm_div * fd); -} - -static u32 get_ipg_clk(void) -{ - u32 freq = get_mcu_main_clk(); - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - u32 pdr0 = readl(&ccm->pdr0); - - return freq / (get_ahb_div(pdr0) * 2); -} - -static u32 get_ipg_per_clk(void) -{ - u32 freq = get_mcu_main_clk(); - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - u32 pdr0 = readl(&ccm->pdr0); - u32 pdr4 = readl(&ccm->pdr4); - u32 div; - if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; - } else { - div = CCM_GET_DIVIDER(pdr0, - MXC_CCM_PDR0_PER_PODF_MASK, - MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - div *= get_ahb_div(pdr0); - } - return freq / div; -} - -u32 imx_get_uartclk(void) -{ - u32 freq; - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - u32 pdr4 = readl(&ccm->pdr4); - - if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) - freq = get_mcu_main_clk(); - else - freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); - freq /= CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; - return freq; -} - -unsigned int mxc_get_main_clock(enum mxc_main_clock clk) -{ - u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_podf; - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - u32 reg = readl(&ccm->pdr0); - u32 reg4 = readl(&ccm->pdr4); - - reg |= 0x1; - - switch (clk) { - case CPU_CLK: - ret_val = get_mcu_main_clk(); - break; - case AHB_CLK: - ret_val = get_mcu_main_clk(); - break; - case HSP_CLK: - if (reg & CLKMODE_CONSUMER) { - hsp_podf = (reg >> 20) & 0x3; - pll = get_mcu_main_clk(); - hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; - if (hsp_podf > 0) { - ret_val = pll / hsp_podf; - } else { - puts("mismatch HSP with ARM clock setting\n"); - ret_val = 0; - } - } else { - ret_val = get_mcu_main_clk(); - } - break; - case IPG_CLK: - ret_val = get_ipg_clk(); - break; - case IPG_PER_CLK: - ret_val = get_ipg_per_clk(); - break; - case NFC_CLK: - nfc_pdf = (reg4 >> 28) & 0xF; - pll = get_mcu_main_clk(); - /* AHB/nfc_pdf */ - ret_val = pll / (nfc_pdf + 1); - break; - case USB_CLK: - usb_podf = (reg4 >> 22) & 0x3F; - if (reg4 & 0x200) - pll = get_mcu_main_clk(); - else - pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); - - ret_val = pll / (usb_podf + 1); - break; - default: - printf("Unknown clock: %d\n", clk); - break; - } - - return ret_val; -} -unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) -{ - u32 ret_val = 0, pdf, pre_pdf, clk_sel; - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - u32 mpdr2 = readl(&ccm->pdr2); - u32 mpdr3 = readl(&ccm->pdr3); - u32 mpdr4 = readl(&ccm->pdr4); - - switch (clk) { - case UART1_BAUD: - case UART2_BAUD: - case UART3_BAUD: - clk_sel = mpdr3 & (1 << 14); - pdf = (mpdr4 >> 10) & 0x3F; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); - break; - case SSI1_BAUD: - pre_pdf = (mpdr2 >> 24) & 0x7; - pdf = mpdr2 & 0x3F; - clk_sel = mpdr2 & (1 << 6); - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case SSI2_BAUD: - pre_pdf = (mpdr2 >> 27) & 0x7; - pdf = (mpdr2 >> 8) & 0x3F; - clk_sel = mpdr2 & (1 << 6); - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case CSI_BAUD: - clk_sel = mpdr2 & (1 << 7); - pdf = (mpdr2 >> 16) & 0x3F; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); - break; - case MSHC_CLK: - pre_pdf = readl(&ccm->pdr1); - clk_sel = (pre_pdf & 0x80); - pdf = (pre_pdf >> 22) & 0x3F; - pre_pdf = (pre_pdf >> 28) & 0x7; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case ESDHC1_CLK: - clk_sel = mpdr3 & 0x40; - pdf = mpdr3 & 0x3F; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); - break; - case ESDHC2_CLK: - clk_sel = mpdr3 & 0x40; - pdf = (mpdr3 >> 8) & 0x3F; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); - break; - case ESDHC3_CLK: - clk_sel = mpdr3 & 0x40; - pdf = (mpdr3 >> 16) & 0x3F; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); - break; - case SPDIF_CLK: - clk_sel = mpdr3 & 0x400000; - pre_pdf = (mpdr3 >> 29) & 0x7; - pdf = (mpdr3 >> 23) & 0x3F; - ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / - ((pre_pdf + 1) * (pdf + 1)); - break; - default: - printf("%s(): This clock: %d not supported yet\n", - __func__, clk); - break; - } - - return ret_val; -} - -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return get_mcu_main_clk(); - case MXC_AHB_CLK: - break; - case MXC_IPG_CLK: - return get_ipg_clk(); - case MXC_IPG_PERCLK: - case MXC_I2C_CLK: - return get_ipg_per_clk(); - case MXC_UART_CLK: - return imx_get_uartclk(); - case MXC_ESDHC1_CLK: - return mxc_get_peri_clock(ESDHC1_CLK); - case MXC_ESDHC2_CLK: - return mxc_get_peri_clock(ESDHC2_CLK); - case MXC_ESDHC3_CLK: - return mxc_get_peri_clock(ESDHC3_CLK); - case MXC_USB_CLK: - return mxc_get_main_clock(USB_CLK); - case MXC_FEC_CLK: - return get_ipg_clk(); - case MXC_CSPI_CLK: - return get_ipg_clk(); - } - return -1; -} - -#ifdef CONFIG_FEC_MXC -/* - * The MX35 has no fuse for MAC, return a NULL MAC - */ -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - memset(mac, 0, 6); -} - -u32 imx_get_fecclk(void) -{ - return mxc_get_clock(MXC_IPG_CLK); -} -#endif - -int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u32 cpufreq = get_mcu_main_clk(); - printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); - printf("ipg clock : %dHz\n", get_ipg_clk()); - printf("ipg per clock : %dHz\n", get_ipg_per_clk()); - printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); - - return 0; -} - -U_BOOT_CMD( - clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, - "display clocks", - "" -); - -#if defined(CONFIG_DISPLAY_CPUINFO) -static char *get_reset_cause(void) -{ - /* read RCSR register from CCM module */ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - u32 cause = readl(&ccm->rcsr) & 0x0F; - - switch (cause) { - case 0x0000: - return "POR"; - case 0x0002: - return "JTAG"; - case 0x0004: - return "RST"; - case 0x0008: - return "WDOG"; - default: - return "unknown reset"; - } -} - -int print_cpuinfo(void) -{ - u32 srev = get_cpu_rev(); - - printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n", - (srev & 0xF0) >> 4, (srev & 0x0F), - get_mcu_main_clk() / 1000000); - - printf("Reset cause: %s\n", get_reset_cause()); - - return 0; -} -#endif - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -#ifdef CONFIG_FSL_ESDHC_IMX -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(struct bd_info *bis) -{ - return fsl_esdhc_mmc_init(bis); -} -#endif - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC_IMX -#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR - gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR - gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); -#else - gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); -#endif -#endif - return 0; -} - -#define RCSR_MEM_CTL_WEIM 0 -#define RCSR_MEM_CTL_NAND 1 -#define RCSR_MEM_CTL_ATA 2 -#define RCSR_MEM_CTL_EXPANSION 3 -#define RCSR_MEM_TYPE_NOR 0 -#define RCSR_MEM_TYPE_ONENAND 2 -#define RCSR_MEM_TYPE_SD 0 -#define RCSR_MEM_TYPE_I2C 2 -#define RCSR_MEM_TYPE_SPI 3 - -u32 spl_boot_device(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - u32 rcsr = readl(&ccm->rcsr); - u32 mem_type, mem_ctl; - - /* In external mode, no boot device is returned */ - if ((rcsr >> 10) & 0x03) - return BOOT_DEVICE_NONE; - - mem_ctl = (rcsr >> 25) & 0x03; - mem_type = (rcsr >> 23) & 0x03; - - switch (mem_ctl) { - case RCSR_MEM_CTL_WEIM: - switch (mem_type) { - case RCSR_MEM_TYPE_NOR: - return BOOT_DEVICE_NOR; - case RCSR_MEM_TYPE_ONENAND: - return BOOT_DEVICE_ONENAND; - default: - return BOOT_DEVICE_NONE; - } - case RCSR_MEM_CTL_NAND: - return BOOT_DEVICE_NAND; - case RCSR_MEM_CTL_EXPANSION: - switch (mem_type) { - case RCSR_MEM_TYPE_SD: - return BOOT_DEVICE_MMC1; - case RCSR_MEM_TYPE_I2C: - return BOOT_DEVICE_I2C; - case RCSR_MEM_TYPE_SPI: - return BOOT_DEVICE_SPI; - default: - return BOOT_DEVICE_NONE; - } - } - - return BOOT_DEVICE_NONE; -} diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c deleted file mode 100644 index f120e84dc346c6c8558a3ae2cfc24cc8e8a1f415..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012, Stefano Babic - */ - -#include -#include -#include -#include -#include - -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_PRECHARGE 0x00000400 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 - -enum { - SMODE_NORMAL = 0, - SMODE_PRECHARGE, - SMODE_AUTO_REFRESH, - SMODE_LOAD_REG, - SMODE_MANUAL_REFRESH -}; - -#define set_mode(x, en, m) (x | (en << 31) | (m << 28)) - -static inline void dram_wait(unsigned int count) -{ - volatile unsigned int wait = count; - - while (wait--) - ; - -} - -void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, - u32 row, u32 col, u32 dsize, u32 refresh) -{ - struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; - u32 *cfg_reg, *ctl_reg; - u32 val; - u32 ctlval; - - switch (start_address) { - case CSD0_BASE_ADDR: - cfg_reg = &esdc->esdcfg0; - ctl_reg = &esdc->esdctl0; - break; - case CSD1_BASE_ADDR: - cfg_reg = &esdc->esdcfg1; - ctl_reg = &esdc->esdctl1; - break; - default: - return; - } - - /* The MX35 supports 11 up to 14 rows */ - if (row < 11 || row > 14 || col < 8 || col > 10) - return; - ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16); - - /* Initialize MISC register for DDR2 */ - val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST | - ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN; - writel(val, &esdc->esdmisc); - val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST); - writel(val, &esdc->esdmisc); - - /* - * according to DDR2 specs, wait a while before - * the PRECHARGE_ALL command - */ - dram_wait(0x20000); - - /* Load DDR2 config and timing */ - writel(ddr2_config, cfg_reg); - - /* Precharge ALL */ - writel(set_mode(ctlval, 1, SMODE_PRECHARGE), - ctl_reg); - writel(0xda, start_address + ESDCTL_PRECHARGE); - - /* Load mode */ - writel(set_mode(ctlval, 1, SMODE_LOAD_REG), - ctl_reg); - writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ - writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ - writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ - writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ - - /* Precharge ALL */ - writel(set_mode(ctlval, 1, SMODE_PRECHARGE), - ctl_reg); - writel(0xda, start_address + ESDCTL_PRECHARGE); - - /* Set mode auto refresh : at least two refresh are required */ - writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH), - ctl_reg); - writel(0xda, start_address); - writel(0xda, start_address); - - writel(set_mode(ctlval, 1, SMODE_LOAD_REG), - ctl_reg); - writeb(0xda, start_address + ESDCTL_DDR2_MR); - writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); - - /* OCD mode exit */ - writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ - - /* Set normal mode */ - writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh, - ctl_reg); - - dram_wait(0x20000); - - /* Do not set delay lines, only for MDDR */ -} diff --git a/arch/arm/cpu/arm1136/mx35/relocate.S b/arch/arm/cpu/arm1136/mx35/relocate.S deleted file mode 100644 index e41e5a5726002eaac68fa0a6857f88b95f4a0a6f..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm1136/mx35/relocate.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - i.MX35-specific vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD - */ - -#include - -/* - * The i.MX35 SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM, so let's avoid relocating the vectors. - */ - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c deleted file mode 100644 index f2541c398d89c4a6455aac8986efd7b355dd9d41..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1<<15) /* Software reset */ -#define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ -#define GPTCR_TEN (1) /* Timer enable */ - -/* - * nothing really to do with interrupts, just starts up a counter. - * The 32KHz 32-bit timer overruns in 134217 seconds - */ -int timer_init(void) -{ - int i; - struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; - - /* setup GP Timer 1 */ - writel(GPTCR_SWR, &gpt->ctrl); - - writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); - - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); /* prescaler = 1 */ - /* Freerun Mode, 32KHz input */ - writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, - &gpt->ctrl); - writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); - - return 0; -} diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index da7278e59fa7d801f319669a2ec092e095372dba..4bc27f637366c9878db1a433291fc8b5dd9de76f 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -39,7 +39,7 @@ reset: msr cpsr,r0 /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -62,7 +62,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -81,7 +81,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Jump to board specific initialization... The Mask ROM will have already initialized * basic memory. Go here to bump up clock rate and handle wake up conditions. @@ -91,4 +91,4 @@ cpu_init_crit: mov lr, ip /* restore link */ #endif mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index ecb4e44fd8d4df2b3ecdfcd8727f7e854332fd2d..9ad1f031429cc9e1ac192b381e4c05e67639123d 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -37,8 +37,8 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif @@ -62,8 +62,8 @@ c_runtime_cpu_setup: ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) cpu_init_crit: mov ip, lr @@ -76,4 +76,4 @@ cpu_init_crit: mov lr, ip mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e2b5f2bff4a91c88dd714fbf5fce97128810143f..cba4a1f0358f50992146ed93f2fb4e80cfe45aa6 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -35,25 +35,11 @@ reset: orr r0, r0, #0xd3 msr cpsr, r0 -#if defined(CONFIG_AT91RM9200DK) - /* - * relocate exception table - */ - ldr r0, =_start - ldr r1, =0x0 - mov r2, #16 -copyex: - subs r2, r2, #1 - ldr r3, [r0], #4 - str r3, [r1], #4 - bne copyex -#endif - /* * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -78,7 +64,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -97,7 +83,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will @@ -109,4 +95,4 @@ cpu_init_crit: mov lr, ip #endif mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 98aafe805a225248968d4dc0d240570584dae25e..b901b7c5c9073d962d84e49a982dd69c32b0233a 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -12,8 +12,6 @@ extra-y := endif endif -obj-$(CONFIG_ARMADA100) += armada100/ -obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile deleted file mode 100644 index 77ac0e2624ab97dc7a498557e68b6b42d86f58cd..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/armada100/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar - -obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c deleted file mode 100644 index 96726b3144ecfccb9154435a8f5181024b62b165..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/armada100/cpu.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#include -#include -#include -#include -#include - -#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) -#define SET_MRVL_ID (1<<8) -#define L2C_RAM_SEL (1<<4) - -int arch_cpu_init(void) -{ - u32 val; - struct armd1cpu_registers *cpuregs = - (struct armd1cpu_registers *) ARMD1_CPU_BASE; - - struct armd1apb1_registers *apb1clkres = - (struct armd1apb1_registers *) ARMD1_APBC1_BASE; - - struct armd1mpmu_registers *mpmu = - (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; - - /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */ - val = readl(&cpuregs->cpu_conf); - val = val | SET_MRVL_ID; - writel(val, &cpuregs->cpu_conf); - - /* Enable Clocks for all hardware units */ - writel(0xFFFFFFFF, &mpmu->acgr); - - /* Turn on AIB and AIB-APB Functional clock */ - writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib); - - /* ensure L2 cache is not mapped as SRAM */ - val = readl(&cpuregs->cpu_conf); - val = val & ~(L2C_RAM_SEL); - writel(val, &cpuregs->cpu_conf); - - /* Enable GPIO clock */ - writel(APBC_APBCLK, &apb1clkres->gpio); - -#ifdef CONFIG_I2C_MV - /* Enable general I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); - writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); - - /* Enable power I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); - writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); -#endif - - /* - * Enable Functional and APB clock at 14.7456MHz - * for configured UART console - */ -#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE) - writel(UARTCLK14745KHZ, &apb1clkres->uart3); -#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE) - writel(UARTCLK14745KHZ, &apb1clkres->uart2); -#else - writel(UARTCLK14745KHZ, &apb1clkres->uart1); -#endif - icache_enable(); - - return 0; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 id; - struct armd1cpu_registers *cpuregs = - (struct armd1cpu_registers *) ARMD1_CPU_BASE; - - id = readl(&cpuregs->chip_id); - printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); - return 0; -} -#endif - -#ifdef CONFIG_I2C_MV -void i2c_clk_enable(void) -{ -} -#endif diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c deleted file mode 100644 index c97b5b1940a5eafd6a787e642ad6352480eb951f..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/armada100/dram.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar , - * Contributor: Mahavir Jain - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * ARMADA100 DRAM controller supports upto 8 banks - * for chip select 0 and 1 - */ - -/* - * DDR Memory Control Registers - * Refer Datasheet Appendix A.17 - */ -struct armd1ddr_map_registers { - u32 cs; /* Memory Address Map Register -CS */ - u32 pad[3]; -}; - -struct armd1ddr_registers { - u8 pad[0x100 - 0x000]; - struct armd1ddr_map_registers mmap[2]; -}; - -/* - * armd1_sdram_base - reads SDRAM Base Address Register - */ -u32 armd1_sdram_base(int chip_sel) -{ - struct armd1ddr_registers *ddr_regs = - (struct armd1ddr_registers *)ARMD1_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; - return result; -} - -/* - * armd1_sdram_size - reads SDRAM size - */ -u32 armd1_sdram_size(int chip_sel) -{ - struct armd1ddr_registers *ddr_regs = - (struct armd1ddr_registers *)ARMD1_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs); - result = (result >> 16) & 0xF; - if (result < 0x7) { - printf("Unknown DRAM Size\n"); - return -1; - } else { - return ((0x8 << (result - 0x7)) * 1024 * 1024); - } -} - -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = armd1_sdram_base(i); - gd->bd->bi_dram[i].size = armd1_sdram_size(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -int dram_init_banksize(void) -{ - dram_init(); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c deleted file mode 100644 index 6d77ad3b6da65f335432a3653d01a8f4d2623167..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Timer registers - * Refer Section A.6 in Datasheet - */ -struct armd1tmr_registers { - u32 clk_ctrl; /* Timer clk control reg */ - u32 match[9]; /* Timer match registers */ - u32 count[3]; /* Timer count registers */ - u32 status[3]; - u32 ie[3]; - u32 preload[3]; /* Timer preload value */ - u32 preload_ctrl[3]; - u32 wdt_match_en; - u32 wdt_match_r; - u32 wdt_val; - u32 wdt_sts; - u32 icr[3]; - u32 wdt_icr; - u32 cer; /* Timer count enable reg */ - u32 cmr; - u32 ilr[3]; - u32 wcr; - u32 wfar; - u32 wsar; - u32 cvwr; -}; - -#define TIMER 0 /* Use TIMER 0 */ -/* Each timer has 3 match registers */ -#define MATCH_CMP(x) ((3 * TIMER) + x) -#define TIMER_LOAD_VAL 0xffffffff -#define COUNT_RD_REQ 0x1 - -DECLARE_GLOBAL_DATA_PTR; -/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ - -/* For preventing risk of instability in reading counter value, - * first set read request to register cvwr and then read same - * register after it captures counter value. - */ -ulong read_timer(void) -{ - struct armd1tmr_registers *armd1timers = - (struct armd1tmr_registers *) ARMD1_TIMER_BASE; - volatile int loop=100; - - writel(COUNT_RD_REQ, &armd1timers->cvwr); - while (loop--); - return(readl(&armd1timers->cvwr)); -} - -static ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (now >= gd->arch.tbl) { - /* normal mode */ - gd->arch.tbu += now - gd->arch.tbl; - } else { - /* we have an overflow ... */ - gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; - } - gd->arch.tbl = now; - - return gd->arch.tbu; -} - -ulong get_timer(ulong base) -{ - return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - - base); -} - -void __udelay(unsigned long usec) -{ - ulong delayticks; - ulong endtime; - - delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); - endtime = get_timer_masked() + delayticks; - - while (get_timer_masked() < endtime); -} - -/* - * init the Timer - */ -int timer_init(void) -{ - struct armd1apb1_registers *apb1clkres = - (struct armd1apb1_registers *) ARMD1_APBC1_BASE; - struct armd1tmr_registers *armd1timers = - (struct armd1tmr_registers *) ARMD1_TIMER_BASE; - - /* Enable Timer clock at 3.25 MHZ */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); - - /* load value into timer */ - writel(0x0, &armd1timers->clk_ctrl); - /* Use Timer 0 Match Resiger 0 */ - writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]); - /* Preload value is 0 */ - writel(0x0, &armd1timers->preload[TIMER]); - /* Enable match comparator 0 for Timer 0 */ - writel(0x1, &armd1timers->preload_ctrl[TIMER]); - - /* Enable timer 0 */ - writel(0x1, &armd1timers->cer); - /* init the gd->arch.tbu and gd->arch.tbl value */ - gd->arch.tbl = read_timer(); - gd->arch.tbu = 0; - - return 0; -} - -#define MPMU_APRR_WDTR (1<<4) -#define TMR_WFAR 0xbaba /* WDT Register First key */ -#define TMP_WSAR 0xeb10 /* WDT Register Second key */ - -/* - * This function uses internal Watchdog Timer - * based reset mechanism. - * Steps to write watchdog registers (protected access) - * 1. Write key value to TMR_WFAR reg. - * 2. Write key value to TMP_WSAR reg. - * 3. Perform write operation. - */ -void reset_cpu(void) -{ - struct armd1mpmu_registers *mpmu = - (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; - struct armd1tmr_registers *armd1timers = - (struct armd1tmr_registers *) ARMD1_TIMER_BASE; - u32 val; - - /* negate hardware reset to the WDT after system reset */ - val = readl(&mpmu->aprr); - val = val | MPMU_APRR_WDTR; - writel(val, &mpmu->aprr); - - /* reset/enable WDT clock */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr); - readl(&mpmu->wdtpcr); - writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); - readl(&mpmu->wdtpcr); - - /* clear previous WDT status */ - writel(TMR_WFAR, &armd1timers->wfar); - writel(TMP_WSAR, &armd1timers->wsar); - writel(0, &armd1timers->wdt_sts); - - /* set match counter */ - writel(TMR_WFAR, &armd1timers->wfar); - writel(TMP_WSAR, &armd1timers->wsar); - writel(0xf, &armd1timers->wdt_match_r); - - /* enable WDT reset */ - writel(TMR_WFAR, &armd1timers->wfar); - writel(TMP_WSAR, &armd1timers->wsar); - writel(0x3, &armd1timers->wdt_match_en); - - while(1); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index acab9bccc01ad44e8e5150790ff3a7f38af54054..95963d2665f45543083acd47c750e4dec6d46e34 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -89,4 +89,3 @@ void enable_caches(void) dcache_enable(); #endif } - diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c deleted file mode 100644 index 9cd60abcccbd4a47f9666ad92f71ad7fc813011b..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * Based on mx27/generic.c: - * Copyright (c) 2008 Eric Jarrige - * Copyright (c) 2009 Ilya Yanok - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_FSL_ESDHC_IMX -#include - -DECLARE_GLOBAL_DATA_PTR; -#endif - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) -{ - unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) - & CCM_PLL_MFI_MASK; - int mfn = (pll >> CCM_PLL_MFN_SHIFT) - & CCM_PLL_MFN_MASK; - unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) - & CCM_PLL_MFD_MASK; - unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) - & CCM_PLL_PD_MASK; - - mfi = mfi <= 5 ? 5 : mfi; - mfn = mfn >= 512 ? mfn - 1024 : mfn; - mfd += 1; - pd += 1; - - return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn), - mfd * pd); -} - -static ulong imx_get_mpllclk(void) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = MXC_HCLK; - - return imx_decode_pll(readl(&ccm->mpctl), fref); -} - -static ulong imx_get_upllclk(void) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = MXC_HCLK; - - return imx_decode_pll(readl(&ccm->upctl), fref); -} - -static ulong imx_get_armclk(void) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong cctl = readl(&ccm->cctl); - ulong fref = imx_get_mpllclk(); - ulong div; - - if (cctl & CCM_CCTL_ARM_SRC) - fref = lldiv((u64) fref * 3, 4); - - div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) - & CCM_CCTL_ARM_DIV_MASK) + 1; - - return fref / div; -} - -static ulong imx_get_ahbclk(void) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong cctl = readl(&ccm->cctl); - ulong fref = imx_get_armclk(); - ulong div; - - div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) - & CCM_CCTL_AHB_DIV_MASK) + 1; - - return fref / div; -} - -static ulong imx_get_ipgclk(void) -{ - return imx_get_ahbclk() / 2; -} - -static ulong imx_get_perclk(int clk) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() : - imx_get_ahbclk(); - ulong div; - - div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); - div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; - - return fref / div; -} - -int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk(); - ulong div = (fref + freq - 1) / freq; - - if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK) - return -EINVAL; - - clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)], - CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk), - div << CCM_PERCLK_SHIFT(clk)); - if (from_upll) - setbits_le32(&ccm->mcr, 1 << clk); - else - clrbits_le32(&ccm->mcr, 1 << clk); - return 0; -} - -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - if (clk >= MXC_CLK_NUM) - return -1; - switch (clk) { - case MXC_ARM_CLK: - return imx_get_armclk(); - case MXC_AHB_CLK: - return imx_get_ahbclk(); - case MXC_IPG_CLK: - case MXC_CSPI_CLK: - case MXC_FEC_CLK: - return imx_get_ipgclk(); - default: - return imx_get_perclk(clk); - } -} - -u32 get_cpu_rev(void) -{ - u32 srev; - u32 system_rev = 0x25000; - - /* read SREV register from IIM module */ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - srev = readl(&iim->iim_srev); - - switch (srev) { - case 0x00: - system_rev |= CHIP_REV_1_0; - break; - case 0x01: - system_rev |= CHIP_REV_1_1; - break; - case 0x02: - system_rev |= CHIP_REV_1_2; - break; - default: - system_rev |= 0x8000; - break; - } - - return system_rev; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -static char *get_reset_cause(void) -{ - /* read RCSR register from CCM module */ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - u32 cause = readl(&ccm->rcsr) & 0x0f; - - if (cause == 0) - return "POR"; - else if (cause == 1) - return "RST"; - else if ((cause & 2) == 2) - return "WDOG"; - else if ((cause & 4) == 4) - return "SW RESET"; - else if ((cause & 8) == 8) - return "JTAG"; - else - return "unknown reset"; - -} - -int print_cpuinfo(void) -{ - char buf[32]; - u32 cpurev = get_cpu_rev(); - - printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", - (cpurev & 0xF0) >> 4, (cpurev & 0x0F), - ((cpurev & 0x8000) ? " unknown" : ""), - strmhz(buf, imx_get_armclk())); - printf("Reset cause: %s\n", get_reset_cause()); - return 0; -} -#endif - -#if defined(CONFIG_FEC_MXC) -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong val; - - val = readl(&ccm->cgr0); - val |= (1 << 23); - writel(val, &ccm->cgr0); - return fecmxc_initialize(bis); -} -#endif - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC_IMX -#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE - gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); -#else - gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); -#endif -#endif - return 0; -} - -#ifdef CONFIG_FSL_ESDHC_IMX -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(struct bd_info *bis) -{ - return fsl_esdhc_mmc_init(bis); -} -#endif - -#ifdef CONFIG_FEC_MXC -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - int i; - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank *bank = &iim->bank[0]; - struct fuse_bank0_regs *fuse = - (struct fuse_bank0_regs *)bank->fuse_regs; - - for (i = 0; i < 6; i++) - mac[i] = readl(&fuse->mac_addr[i]) & 0xff; -} -#endif /* CONFIG_FEC_MXC */ diff --git a/arch/arm/cpu/arm926ejs/mx25/relocate.S b/arch/arm/cpu/arm926ejs/mx25/relocate.S deleted file mode 100644 index 709e35c81838fea2e5802daebaffc0e62d8696d5..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/mx25/relocate.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - i.MX25-specific vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD - */ - -#include - -/* - * The i.MX25 SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM, so let's avoid relocating the vectors. - */ - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c deleted file mode 100644 index 7844a99c164019194f79202b2c564a5682632557..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/mx25/reset.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - */ - -#include -#include -#include -#include - -/* - * Reset the cpu by setting up the watchdog timer and let it time out - */ -void reset_cpu(void) -{ - struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; - /* Disable watchdog and set Time-Out field to 0 */ - writew(0, ®s->wcr); - - /* Write Service Sequence */ - writew(WSR_UNLOCK1, ®s->wsr); - writew(WSR_UNLOCK2, ®s->wsr); - - /* Enable watchdog */ - writew(WCR_WDE, ®s->wcr); - - while (1) ; -} diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c deleted file mode 100644 index 4b726d5c73f06547aa6b1f19814547b967cb4396..0000000000000000000000000000000000000000 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * Add support for MX25 - */ - -#include -#include -#include -#include -#include - -/* nothing really to do with interrupts, just starts up a counter. */ -/* The 32KHz 32-bit timer overruns in 134217 seconds */ -int timer_init(void) -{ - int i; - struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - - /* setup GP Timer 1 */ - writel(GPT_CTRL_SWR, &gpt->ctrl); - - writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1); - - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); /* prescaler = 1 */ - /* Freerun Mode, 32KHz input */ - writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, - &gpt->ctrl); - writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 0a8985b90a938fb8df8f5ea130e75aa74d5548df..763d79e8036a41a0f157ce11f534d33dd19d5d01 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; static gd_t gdata __section(".data"); -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL static struct bd_info bdata __section(".data"); #endif @@ -108,7 +108,7 @@ static void mxs_spl_fixup_vectors(void) static void mxs_spl_console_init(void) { -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL gd->bd = &bdata; gd->baudrate = CONFIG_BAUDRATE; serial_init(); diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index ff592ba81017ec731c1691a0174d7488b3e2b8ec..0afcc47aad7d4d522d6f50c14a166bb3a950e511 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -46,7 +46,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -69,7 +69,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush D cache before disabling it @@ -100,7 +100,7 @@ flush_dcache: #endif mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Go setup Memory and board specific bits prior to relocation. */ @@ -109,4 +109,4 @@ flush_dcache: mov lr, r4 /* restore link */ #endif mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 0ec340b1a6e975dd6ad8836900f6e1297092cd58..2d5186774a76e903dfe2d3c78ea06afec1cb989f 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -45,7 +45,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -70,7 +70,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -89,7 +89,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Go setup Memory and board specific bits prior to relocation. */ diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0e83e394d52b8203a85ca47c202fa4080fc0fd73..bfbd85ae64ef74b2b645ec84facbc2f139cc8e8a 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 747059b56a52965ccd2d49e7e22ee5ad43f9cb1b..f919d02db428cadc96801c0568e90f2b85e2c3aa 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -20,6 +20,7 @@ config ARCH_LS1021A select SYS_FSL_SEC_LE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES + select SYS_I2C_MXC imply CMD_PCI imply SCSI imply SCSI_AHCI diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 940995ef5af1fc91bcaab59a3d16c6d71c75be85..984ae8b87bd6c3cbcc5049a59ec29adb35c14bfd 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -42,8 +42,8 @@ void get_sys_info(struct sys_info *sys_info) unsigned long sysclk = CONFIG_SYS_CLK_FREQ; sys_info->freq_systembus = sysclk; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #else sys_info->freq_ddrbus = sysclk; #endif diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index 308536c3362f25338eb4296b93412ea2a8b30d65..a19496862359aa1a1d8b8209e02a268ccdec5037 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -8,7 +8,7 @@ u32 spl_boot_device(void) { -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif return BOOT_DEVICE_NAND; diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c index a328b2bc0e83987a039e07abca5df8a0cf86bca7..f313fe4b84c37cc9bcb8bbf1b1f8780e6389ff68 100644 --- a/arch/arm/cpu/armv7/psci-common.c +++ b/arch/arm/cpu/armv7/psci-common.c @@ -43,4 +43,3 @@ u32 __secure psci_get_context_id(int cpu) { return psci_context_id[cpu]; } - diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index dcb4195d7b48bc790ac696b2db47faf9cc72cc17..698e15b8e184da24ff61ba82862086521ade16c0 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -39,6 +39,42 @@ reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_POSITION_INDEPENDENT + /* + * Fix .rela.dyn relocations. This allows U-Boot to loaded to and + * executed at a different address than it was linked at. + */ +pie_fixup: + adr r0, reset /* r0 <- Runtime value of reset label */ + ldr r1, =reset /* r1 <- Linked value of reset label */ + subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */ + beq pie_fixup_done + + adr r0, pie_fixup + ldr r1, _rel_dyn_start_ofs + add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */ + ldr r1, _rel_dyn_end_ofs + add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */ + +pie_fix_loop: + ldr r0, [r2] /* r0 <- Link location */ + ldr r1, [r2, #4] /* r1 <- fixup */ + cmp r1, #23 /* relative fixup? */ + bne pie_skip_reloc + + /* relative fix: increase location by offset */ + add r0, r4 + ldr r1, [r0] + add r1, r4 + str r1, [r0] + str r0, [r2] + add r2, #8 +pie_skip_reloc: + cmp r2, r3 + blo pie_fix_loop +pie_fixup_done: +#endif + #ifdef CONFIG_ARMV7_LPAE /* * check for Hypervisor support @@ -80,11 +116,11 @@ switch_to_hypervisor_ret: #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #ifdef CONFIG_CPU_V7A bl cpu_init_cp15 #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif #endif @@ -320,8 +356,8 @@ skip_errata_801819: mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /************************************************************************* * * CPU_init_critical registers @@ -340,3 +376,10 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif + +#if CONFIG_POSITION_INDEPENDENT +_rel_dyn_start_ofs: + .word __rel_dyn_start - pie_fixup +_rel_dyn_end_ofs: + .word __rel_dyn_end - pie_fixup +#endif diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index b7a10a8e34e6120f09b2c77c3f55471e0eeb09af..0a3fdfa4716e348fa2de14ff4c76e3afa055ea80 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -3,7 +3,6 @@ if ARM64 config ARMV8_SPL_EXCEPTION_VECTORS bool "Install crash dump exception vectors" depends on SPL - default n help The default exception vector table is only used for the crash dump, but still takes quite a lot of space in the image size. @@ -128,7 +127,6 @@ config PSCI_RESET config ARMV8_PSCI bool "Enable PSCI support" if EXPERT - default n help PSCI is Power State Coordination Interface defined by ARM. The PSCI in U-boot provides a general framework and each platform @@ -156,7 +154,6 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER config ARMV8_EA_EL3_FIRST bool "External aborts and SError interrupt exception are taken in EL3" - default n help Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index e04907dd8c0bec90708c98f58934315b56707c0f..d1cee23437da1422b304b0bd2c31302448eb1dd0 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -27,13 +27,11 @@ ENTRY(__asm_dcache_level) msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ - and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ + ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ + ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ add x2, x2, #4 /* x2 <- log2(cache line size) */ - mov x3, #0x3ff - and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ clz w5, w3 /* bit position of #ways */ - mov x4, #0x7fff - and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ /* x12 <- cache level << 1 */ /* x2 <- line length offset */ /* x3 <- number of cache ways - 1 */ @@ -72,8 +70,7 @@ ENTRY(__asm_dcache_all) mov x1, x0 dsb sy mrs x10, clidr_el1 /* read clidr_el1 */ - lsr x11, x10, #24 - and x11, x11, #0x7 /* x11 <- loc */ + ubfx x11, x10, #24, #3 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr mov x0, #0 /* start flush at cache level 0 */ @@ -83,8 +80,7 @@ ENTRY(__asm_dcache_all) /* x15 <- return address */ loop_level: - lsl x12, x0, #1 - add x12, x12, x0 /* x0 <- tripled cache level */ + add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */ lsr x12, x10, x12 and x12, x12, #7 /* x12 <- cache type */ cmp x12, #2 @@ -131,8 +127,7 @@ ENDPROC(__asm_invalidate_dcache_all) .pushsection .text.__asm_flush_dcache_range, "ax" ENTRY(__asm_flush_dcache_range) mrs x3, ctr_el0 - lsr x3, x3, #16 - and x3, x3, #0xf + ubfx x3, x3, #16, #4 mov x2, #4 lsl x2, x2, x3 /* cache line size */ @@ -158,7 +153,7 @@ ENDPROC(__asm_flush_dcache_range) .pushsection .text.__asm_invalidate_dcache_range, "ax" ENTRY(__asm_invalidate_dcache_range) mrs x3, ctr_el0 - ubfm x3, x3, #16, #19 + ubfx x3, x3, #16, #4 mov x2, #4 lsl x2, x2, x3 /* cache line size */ diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index 7def44ad1d31782a3b16295957e55b5eaec99409..5266515f145ef1b77e75d50f73b555b4fd2efb1c 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -64,18 +64,18 @@ ENTRY(return_to_fel) /* AArch32 code to restore the state from fel_stash and return back to FEL. */ back_in_32: - .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address - .word 0xe5901008 // ldr r1, [r0, #8] - .word 0xe129f001 // msr CPSR_fc, r1 + .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address + .word 0xe5901008 // ldr r1, [r0, #8] + .word 0xe129f001 // msr CPSR_fc, r1 .word 0xf57ff06f // isb - .word 0xe590d000 // ldr sp, [r0] - .word 0xe590e004 // ldr lr, [r0, #4] - .word 0xe5901010 // ldr r1, [r0, #16] - .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR - .word 0xe590100c // ldr r1, [r0, #12] - .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR + .word 0xe590d000 // ldr sp, [r0] + .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901010 // ldr r1, [r0, #16] + .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR + .word 0xe590100c // ldr r1, [r0, #12] + .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR .word 0xf57ff06f // isb - .word 0xe12fff1e // bx lr ; return to FEL + .word 0xe12fff1e // bx lr ; return to FEL fel_stash_addr: .word 0x00000000 // receives fel_stash addr, by AA64 code above ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9cef363fbaabd3e7fb7651313ace7f73c72fa6cd..1e166c73e40a02b216fbb65ac4114cf1f40f4ee0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -4,6 +4,8 @@ config ARCH_LS1012A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH2 + select GICV2 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE @@ -25,6 +27,7 @@ config ARCH_LS1028A select ARMV8_SET_SMPEN select FSL_LAYERSCAPE select FSL_LSCH3 + select GICV3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 select SYS_FSL_SRDS_1 @@ -58,7 +61,9 @@ config ARCH_LS1043A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH2 + select GICV2 select HAS_FSL_XHCI_USB if USB_HOST + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -84,13 +89,16 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C imply CMD_PCI + imply ID_EEPROM config ARCH_LS1046A bool select ARMV8_SET_SMPEN select FSL_LAYERSCAPE select FSL_LSCH2 + select GICV2 select HAS_FSL_XHCI_USB if USB_HOST + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -117,8 +125,10 @@ config ARCH_LS1046A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + imply ID_EEPROM imply SCSI imply SCSI_AHCI + imply SPL_SYS_I2C_LEGACY config ARCH_LS1088A bool @@ -126,6 +136,8 @@ config ARCH_LS1088A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH3 + select GICV3 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -158,7 +170,9 @@ config ARCH_LS1088A select SYS_I2C_MXC_I2C3 if !TFABOOT select SYS_I2C_MXC_I2C4 if !TFABOOT select RESV_RAM if GIC_V3_ITS + imply ID_EEPROM imply SCSI + imply SPL_SYS_I2C_LEGACY imply PANIC_HANG config ARCH_LS2080A @@ -170,6 +184,8 @@ config ARCH_LS2080A select ARM_ERRATA_833471 select FSL_LAYERSCAPE select FSL_LSCH3 + select GICV3 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -210,12 +226,15 @@ config ARCH_LS2080A select SYS_I2C_MXC_I2C4 if !TFABOOT select RESV_RAM if GIC_V3_ITS imply DISTRO_DEFAULTS + imply ID_EEPROM imply PANIC_HANG + imply SPL_SYS_I2C_LEGACY config ARCH_LX2162A bool select ARMV8_SET_SMPEN select FSL_LSCH3 + select GICV3 select NXP_LSCH3_2 select SYS_HAS_SERDES select SYS_FSL_SRDS_1 @@ -242,11 +261,13 @@ config ARCH_LX2162A imply PANIC_HANG imply SCSI imply SCSI_AHCI + imply SPL_SYS_I2C_LEGACY config ARCH_LX2160A bool select ARMV8_SET_SMPEN select FSL_LSCH3 + select GICV3 select HAS_FSL_XHCI_USB if USB_HOST select NXP_LSCH3_2 select SYS_HAS_SERDES @@ -272,12 +293,15 @@ config ARCH_LX2160A select SYS_I2C_MXC select RESV_RAM if GIC_V3_ITS imply DISTRO_DEFAULTS + imply ID_EEPROM imply PANIC_HANG imply SCSI imply SCSI_AHCI + imply SPL_SYS_I2C_LEGACY config FSL_LSCH2 bool + select SKIP_LOWLEVEL_INIT select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 @@ -429,7 +453,6 @@ config QSPI_AHB_INIT config FSPI_AHB_EN_4BYTE bool "Enable 4-byte Fast Read command for AHB mode" - default n help The default setting for FlexSPI AHB bus just supports 3-byte addressing. But some FlexSPI flash sizes are up to 64MBytes. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d0103fc8811e6b80412569615560483641f593a4..1a359d060e82e53f78d788704832fdd6e968e1d2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1147,7 +1147,7 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_SYS_FSL_HAS_RGMII /* some dpmacs in armv8a based freescale layerscape SOCs can be - * configured via both serdes(sgmii, xfi, xlaui etc) bits and via + * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 6c98d99d0ccea0fabe6321d86a91bcec3fc9d09a..9119d60ffb31c72682c492eab9dbc38032e08e99 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -42,22 +42,22 @@ Flash Layout pre-silicon platforms (simulator and emulator): ------------------------- - | FIT Image | + | FIT Image | | (linux + DTB + RFS) | ------------------------- ----> 0x0120_0000 - | Debug Server FW | + | Debug Server FW | ------------------------- ----> 0x00C0_0000 - | AIOP FW | + | AIOP FW | ------------------------- ----> 0x0070_0000 - | MC FW | + | MC FW | ------------------------- ----> 0x006C_0000 - | MC DPL Blob | + | MC DPL Blob | ------------------------- ----> 0x0020_0000 - | BootLoader + Env| + | BootLoader + Env| ------------------------- ----> 0x0000_1000 - | PBI | + | PBI | ------------------------- ----> 0x0000_0080 - | RCW | + | RCW | ------------------------- ----> 0x0000_0000 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) @@ -70,45 +70,45 @@ Flash Layout ----------------------------------------- ----> 0x5_8790_0000 | | FIT Image (linux + DTB + RFS) (40M) | | ----------------------------------------- ----> 0x5_8510_0000 | - | PHY firmware (2M) | | + | PHY firmware (2M) | | ----------------------------------------- ----> 0x5_84F0_0000 | 64K | Debug Server FW (2M) | | Alt ----------------------------------------- ----> 0x5_84D0_0000 | Bank | AIOP FW (4M) | | ----------------------------------------- ----> 0x5_8490_0000 (vbank4) - | MC DPC Blob (1M) | | + | MC DPC Blob (1M) | | ----------------------------------------- ----> 0x5_8480_0000 | | MC DPL Blob (1M) | | ----------------------------------------- ----> 0x5_8470_0000 | - | MC FW (4M) | | + | MC FW (4M) | | ----------------------------------------- ----> 0x5_8430_0000 | - | BootLoader Environment (1M) | | + | BootLoader Environment (1M) | | ----------------------------------------- ----> 0x5_8420_0000 | | BootLoader (1M) | | ----------------------------------------- ----> 0x5_8410_0000 | - | RCW and PBI (1M) | | + | RCW and PBI (1M) | | ----------------------------------------- ----> 0x5_8400_0000 --- | .. Unused .. (7M) | | ----------------------------------------- ----> 0x5_8390_0000 | | FIT Image (linux + DTB + RFS) (40M) | | ----------------------------------------- ----> 0x5_8110_0000 | - | PHY firmware (2M) | | + | PHY firmware (2M) | | ----------------------------------------- ----> 0x5_80F0_0000 | 64K | Debug Server FW (2M) | | Bank ----------------------------------------- ----> 0x5_80D0_0000 | | AIOP FW (4M) | | ----------------------------------------- ----> 0x5_8090_0000 (vbank0) - | MC DPC Blob (1M) | | + | MC DPC Blob (1M) | | ----------------------------------------- ----> 0x5_8080_0000 | | MC DPL Blob (1M) | | ----------------------------------------- ----> 0x5_8070_0000 | - | MC FW (4M) | | + | MC FW (4M) | | ----------------------------------------- ----> 0x5_8030_0000 | - | BootLoader Environment (1M) | | + | BootLoader Environment (1M) | | ----------------------------------------- ----> 0x5_8020_0000 | | BootLoader (1M) | | ----------------------------------------- ----> 0x5_8010_0000 | - | RCW and PBI (1M) | | + | RCW and PBI (1M) | | ----------------------------------------- ----> 0x5_8000_0000 --- 128-MB NOR flash layout for QDS and RDB boards diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index f33d05d0539fbff50631e9dbf9fb272beff62146..f2efd4cc1d704f075bebef3f1f1bea3b8b888723 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features: - Hardware buffer management for buffer allocation and de-allocation (BMan) - Cryptography acceleration (SEC) - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface + - Up to 1 x 10GBase-R supporting 10G interface - Up to 1 x QSGMII - Up to 4 x SGMII supporting 1000Mbps - Up to 2 x SGMII supporting 2500Mbps @@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features: - Two PLLs per four-lane SerDes - Support for 10G operation - Ethernet interfaces by FMan - - Up to 2 x XFI supporting 10G interface (MAC 9, 10) + - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10) - Up to 1 x QSGMII (MAC 5, 6, 10, 1) - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) @@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features: Single WRIOP tile supporting 130Gbps using 18 MACs Support for 10G-SXGMII (aka USXGMII). Support for SGMII (and 1000Base-KX) - Support for XFI (and 10GBase-KR) + Support for 10GBase-R (and 10GBase-KR) Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). Support for XLAUI (and 40GBase-KR4) for 40G. Support for two RGMII parallel interfaces. @@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features: Ethernet interfaces Support for 10G-SXGMII (aka USXGMII). Support for SGMII (and 1000Base-KX) - Support for XFI (and 10GBase-KR) + Support for 10GBase-R (and 10GBase-KR) Support for CAUI2 (50G) and 25G-AUI(25G). Support for XLAUI (and 40GBase-KR4) for 40G. Support for two RGMII parallel interfaces. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 63d34e1ec039a1cd639fc8bed6f22e624d5c1360..3f97c8aee4abf462f1eba775e493388eeccb69c5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -61,8 +61,8 @@ void get_sys_info(struct sys_info *sys_info) #endif cluster_clk = CONFIG_CLUSTER_CLK_FREQ; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #else sys_info->freq_ddrbus = sysclk; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 25a1c36d2ac02ae49543a9e0e76f10a41cb9c430..6f50cbad2ba94ac6ee2f3bb3df6225c69e71d051 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -78,10 +78,10 @@ void get_sys_info(struct sys_info *sys_info) void *offset; sys_info->freq_systembus = sysclk; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus2 = get_board_ddr_clk(); #endif #else sys_info->freq_ddrbus = sysclk; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d8803738f105860b7ecca683af5b64ff3159bae7..3aa1a9c3e5ccb861450d244ec90369ab3e037df8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -250,7 +250,7 @@ ENTRY(lowlevel_init) * b. We use only Region0 whose NSAID write/read is EN * * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just - * placeholders. + * placeholders. */ .macro tzasc_prog, xreg @@ -259,7 +259,7 @@ ENTRY(lowlevel_init) mov x16, #0x10000 mul x14, \xreg, x16 add x14, x14,x12 - mov x1, #0x8 + mov x1, #0x8 add x1, x1, x14 ldr w0, [x1] /* Filter 0 Gate Keeper Register */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 280afbbf98f761e9d847fc140bcf5f79b8a07705..26f8a49826927d1904761c0aca97f891c42d8cdb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; /* - * LS1044A/1048A support only one XFI port + * LS1044A/1048A support only one 10GBase-R port * Disable MAC1 for LS1044A/1048A */ if (serdes == FSL_SRDS_1 && lane == 2) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 42a096854629164ac583185960e463160783cfd5..41f3e95019b7daa9a06ab7c9bbf859b34f1a5ad9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -329,7 +329,7 @@ static void erratum_rcw_src(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) u8 __iomem *ptr; #ifdef I2C1_BASE_ADDR ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index 363ded03e603c8461b81eb38fb8e344e1b4ffc2f..d6bd1884599c43f35d15b6fbb686ba7f2cf6ec6c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -93,7 +93,7 @@ __secondary_boot_func: 4: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 switch_el x7, _dead_loop, 0f, _dead_loop -0: armv8_switch_to_el1_m x4, x6, x7 +0: armv8_switch_to_el1_m x4, x6, x7, x9 #else switch_el x7, 0f, _dead_loop, _dead_loop 0: armv8_switch_to_el2_m x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1d5e34445296f6c0a1d44cb4d1787744796c448b..68111b6eff8cfdddf325af3f9b8c5f5938c79446 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif #ifdef CONFIG_SPL_NAND_SUPPORT @@ -88,7 +88,7 @@ void board_init_f(ulong dummy) preloader_console_init(); spl_set_bd(); -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) #ifdef CONFIG_SPL_I2C i2c_init_all(); #endif diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c b/arch/arm/cpu/armv8/hisilicon/pinmux.c index 5183e00a44cb14ee635294c89194d0a69280fbc0..e14057c0a47c372675967a7414513e9be1d63446 100644 --- a/arch/arm/cpu/armv8/hisilicon/pinmux.c +++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c @@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral) return 0; } - - diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index a31af4ffc8943af6aea86f24babcbcf8eeb3b1ae..9dbdff3a4fceaba29a62f8c79db031fac97435af 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -40,7 +40,7 @@ ENTRY(armv8_switch_to_el1) * now, jump to the address saved in x4. */ br x4 -1: armv8_switch_to_el1_m x4, x5, x6 +1: armv8_switch_to_el1_m x4, x5, x6, x7 ENDPROC(armv8_switch_to_el1) .popsection diff --git a/arch/arm/cpu/armv8/xen/hypercall.S b/arch/arm/cpu/armv8/xen/hypercall.S index 731256b34e2451179d8d7d1b684896bad89ea46b..e69ed408dc659de4142fa0519637d5c49a87e944 100644 --- a/arch/arm/cpu/armv8/xen/hypercall.S +++ b/arch/arm/cpu/armv8/xen/hypercall.S @@ -76,4 +76,3 @@ HYPERCALL2(sched_op); HYPERCALL2(event_channel_op); HYPERCALL2(hvm_op); HYPERCALL2(memory_op); - diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 575abac09c27cd4f920a662c95a66c867dfab60a..896e05f1fda48d9b256791ff13f25dc101fd9f44 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -45,7 +45,7 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -92,7 +92,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) cpu_init_crit: /* * flush v4 I/D caches @@ -111,7 +111,7 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */ /* * Enable MMU to use DCache as DRAM. diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 8eb005309e0fd281e5b5e6368f39c65940830f7d..2f84f20575c98b3361a1108d260d32dbbda347b9 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -39,7 +39,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -95,7 +95,7 @@ cpu_init_crit: ldr r1, cpuspeed str r1, [r0, #PPCR] -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fc16a57e60b03a416cce637465339bdce83bf5af..9438bf735aad414a1e0fc1b2f88a2d5a4e4d9d47 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -929,7 +929,7 @@ endif dtb-$(CONFIG_RZA1) += \ r7s72100-gr-peach-u-boot.dtb -dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ +dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb \ @@ -1090,7 +1090,14 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcom-picoitx.dtb \ stm32mp15xx-dhcor-avenger96.dtb -dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb +dtb-$(CONFIG_SOC_K3_AM6) += \ + k3-am654-base-board.dtb \ + k3-am654-r5-base-board.dtb \ + k3-am65-iot2050-spl.dtb \ + k3-am6528-iot2050-basic.dtb \ + k3-am6528-iot2050-basic-pg2.dtb \ + k3-am6548-iot2050-advanced.dtb \ + k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-r5-common-proc-board.dtb \ k3-j7200-common-proc-board.dtb \ @@ -1120,6 +1127,8 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \ dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb +dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb + dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index ac0f08b7ea8892645aac8eb83c0d43e105a4edbf..f121f547e6d47bb5e3118a41cdb4b790c50d140b 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -474,21 +474,25 @@ wdt1: watchdog@1e785000 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785000 0x40>; + status = "disabled"; }; wdt2: watchdog@1e785040 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785040 0x40>; + status = "disabled"; }; wdt3: watchdog@1e785080 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785080 0x40>; + status = "disabled"; }; wdt4: watchdog@1e7850C0 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e7850C0 0x40>; + status = "disabled"; }; lpc: lpc@1e789000 { diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts index ee851a1befcd28adea445324baa6a965be698738..efd1a5d197b77b96a751d176cac2d2a15de1be96 100644 --- a/arch/arm/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -68,7 +68,7 @@ }; ahb { - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <&pioA 42 0>; pinctrl-names = "default"; @@ -76,7 +76,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; diff --git a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi index 347fa813e989f2c5606d1c35a3906a38b75776e5..b45de978c2e81df02325bb8fb6ec306204707b76 100644 --- a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi +++ b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi @@ -13,11 +13,15 @@ }; }; -&sdmmc0 { +&pinctrl_mikrobus1_uart { u-boot,dm-pre-reloc; }; -&uart0 { /* mikrobus1 uart */ +&pinctrl_qspi1_sck_cs_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_qspi1_dat_default { u-boot,dm-pre-reloc; }; @@ -25,6 +29,19 @@ u-boot,dm-pre-reloc; }; -&pinctrl_mikrobus1_uart { +&qspi1 { u-boot,dm-pre-reloc; + + flash@0 { + u-boot,dm-pre-reloc; + }; }; + +&sdmmc0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { /* mikrobus1 uart */ + u-boot,dm-pre-reloc; +}; + diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index f81fa601714bc94c5b54a6f9da3da51aedb91665..44522197ff67ebc72b68df8be4a011b23cda5dff 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT /* * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board - * SAMA5D2 Industrial Connectivity Board + * SAMA5D2 Industrial Connectivity Platform * * Copyright (c) 2018, Microchip Technology Inc. * 2018, Eugen Hristev @@ -33,10 +33,19 @@ }; apb { - uart0: serial@f801c000 { /* mikrobus1 uart */ + + qspi1: spi@f0024000 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_uart>; + pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>; status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <83000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; }; macb0: ethernet@f8008000 { @@ -46,6 +55,12 @@ status = "okay"; }; + uart0: serial@f801c000 { /* mikrobus1 uart */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + status = "okay"; + }; + i2c1: i2c@fc028000 { dmas = <0>, <0>; pinctrl-names = "default"; @@ -70,6 +85,7 @@ pagesize = <16>; }; }; + pioA: gpio@fc038000 { status = "okay"; pinctrl { @@ -109,6 +125,26 @@ bias-pull-up; }; + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_qspi1_dat_default: qspi1_dat_default { + pinmux = , + , + , + ; + bias-pull-up; + }; + pinctrl_sdmmc0_default: sdmmc0_default { pinmux = , , @@ -119,12 +155,6 @@ ; bias-disable; }; - - pinctrl_mikrobus1_uart: mikrobus1_uart { - pinmux = , - ; - bias-disable; - }; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts index cd3711a02a5b8a4a175cda2c855505e3271cfe0c..f45fb1ef268f7482542ad361775455b9eaeee262 100644 --- a/arch/arm/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts @@ -76,7 +76,7 @@ status = "okay"; }; - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioA PIN_PB12 GPIO_ACTIVE_HIGH @@ -87,7 +87,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index b733c4d4ceeb60c264a61392a169f6331e57d377..34b64a22af4769e4096e0cbe325b1220def453f3 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -12,6 +12,10 @@ stdout-path = &uart1; }; + memory { + reg = <0x20000000 0x20000000>; + }; + onewire_tm: onewire { gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -25,7 +29,7 @@ }; ahb { - usb1: ohci@00400000 { + usb1: ohci@400000 { num-ports = <3>; atmel,vbus-gpio = <&pioA 42 0>; pinctrl-names = "default"; @@ -33,7 +37,7 @@ status = "okay"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi index 23816da8eebadbd699c625ab924451fe816c314e..4063d9a114d39bbf70f54e5900aed059bc2f629f 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 1xxx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi index c6558ae2e07bb7302ea4ad767f037fa93dd016dc..548ab2ba65bc3667a319a8d7ddd12aee32f913e4 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 6xxx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* @@ -14,6 +14,6 @@ &enetc0 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index 5a0f060c16e5dbcae2263cd2ce44a4ef7e3e4635..3991fb793ffbd0a772e50197459b3c49ef1af7f2 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7777 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* @@ -30,25 +30,25 @@ &mscc_felix_port0 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; }; &mscc_felix_port1 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; }; &mscc_felix_port2 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; &mscc_felix_port3 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index 39a83e10c4ce6c2b2a9407a8db83e27e65fa4104..d68c8c2be040102eb998b6f060aebf677be8853f 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7xx7 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ &slot1 { @@ -19,13 +19,13 @@ &mscc_felix_port0 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; &mscc_felix_port3 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi index 7d4702e4ff2b1a74df40cc85aabc5908806f8b90..94b5081d6101be4e3857c1feceb745929a1aa18a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 8xxx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi index 021fe3fbc67a77e3913a8df55775aa52c4a95c29..3b850268e6a94239679aae007c6f15816ec92474 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 9999 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi index b6704d8089a8d30e7b790b55a7149676b11761b0..eb632143e068a518041a83012645128a7dcb1bad 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 9999 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP * */ diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi index 8c10897e565c9dffac8db8c4c55acaae23ef7602..ed86da6b26dfa79077cd78ec7a9efe3732ac17ae 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW x3xx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index 1d800dacef89803bd3757c63a9e2eb1b7074acb3..c9de4ecc434ab22c7f419ec80078af61b27bcaab 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW x5xx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 1fb2cdf0c244ccbf0346345af82e93d85d2e8ce8..7f785507bf1b5d3e31783b2559a74b220a20495c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7777 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ &slot2 { @@ -19,7 +19,7 @@ &mscc_felix_port1 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 2333f74e5ae136580cb42d701213e09548800d21..0fbe7721c813cc6a39da6ff1b6168f874821601c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7777 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ &slot3 { @@ -19,7 +19,7 @@ &mscc_felix_port2 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi index e0a6c04835bf171855ecba7b87d93c4acc7ec0f2..df39cca6961c4cd9e95027ca9c33785e9b537c90 100644 --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi @@ -9,12 +9,12 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi index 65e95300ab56ea0377783afd4e55f2913b83bb95..99f74c2fc4d31bf35b3b4ad0f6ac2a2816ce3fb3 100644 --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi @@ -9,10 +9,10 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi index ccbb5de1eaefda3eb2dea82957b32c038de772d4..72297f48ca657c6472401d1d5c83af5239154566 100644 --- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -9,40 +9,40 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac5 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac6 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac7 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac8 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 179ed19bf2c1b6babf628bc5bdb2d4612ee22b35..9e68c147e607a362255aa85f9ba8acb2a900d956 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -24,49 +24,49 @@ &dpmac1 { status = "okay"; phy-handle = <&mdio1_phy1>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; phy-handle = <&mdio1_phy2>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { status = "okay"; phy-handle = <&mdio1_phy3>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { status = "okay"; phy-handle = <&mdio1_phy4>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac5 { status = "okay"; phy-handle = <&mdio2_phy1>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac6 { status = "okay"; phy-handle = <&mdio2_phy2>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac7 { status = "okay"; phy-handle = <&mdio2_phy3>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac8 { status = "okay"; phy-handle = <&mdio2_phy4>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &emdio1 { diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi index 304afdabc59ee740f6e507f2c8fac1e61036af0e..d1b43aa0020a0acc9036b75246440da2ead5d62a 100644 --- a/arch/arm/dts/fsl-sch-24801.dtsi +++ b/arch/arm/dts/fsl-sch-24801.dtsi @@ -2,7 +2,7 @@ /* * Device tree fragment for RCW SCH-24801 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi index 584f3fa68cdd4875d7a7867bf96edccbcfd9af0b..61245287b96305896d9ec8eab02a150217906980 100644 --- a/arch/arm/dts/fsl-sch-28021.dtsi +++ b/arch/arm/dts/fsl-sch-28021.dtsi @@ -2,7 +2,7 @@ /* * Device tree fragment for RCW SCH-28021 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi index ca437d1782811f95d53735552f0e326e0a332394..28b1bec18a5531d632146e74e79614397a20b41a 100644 --- a/arch/arm/dts/fsl-sch-30841.dtsi +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -2,14 +2,14 @@ /* * Device tree fragment for RCW SCH-30841 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed * together on a single lane or mapped 1:1 to serdes lanes. - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. + * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R. * PHY addresses are 0x00 - 0x03. * On the card the first port is the bottom port (closest to PEX connector). */ diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi index fa0f2cdb10964f6e8933e683ed064c0c14f9529a..bff9e76570b681c4411b6a40c81975c9553f5f88 100644 --- a/arch/arm/dts/fsl-sch-30842.dtsi +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -2,13 +2,13 @@ /* * Device tree fragment for RCW SCH-30842 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* * SCH-30842 is a single port add-on card used with various FSL QDS boards. * It integrates a AQR112 PHY, which supports several protocols - SGMII, - * SGMII-2500, USXGMII, XFI. + * 2500base-x, USXGMII, 10GBase-R. * PHY address is 0x02. */ phy@02 { diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index c5af2ffb8ee146d400276bc714fde953fb0955b0..02c3fdf9cc46ba8b2e77565279de442840b9fdbc 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +37,20 @@ }; }; + main_conf: syscon@43000000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x0 0x43000000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x43000000 0x20000>; + + serdes_ln_ctrl: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -50,12 +75,12 @@ }; }; - dmss: dmss { + dmss: bus@48000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; dma-ranges; - ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; ti,sci-dev-id = <25>; @@ -142,7 +167,7 @@ }; }; - dmsc: dmsc@44043000 { + dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; @@ -156,7 +181,7 @@ #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -197,8 +222,6 @@ main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -210,8 +233,6 @@ main_uart1: serial@2810000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -223,8 +244,6 @@ main_uart2: serial@2820000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -236,8 +255,6 @@ main_uart3: serial@2830000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -249,8 +266,6 @@ main_uart4: serial@2840000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -262,8 +277,6 @@ main_uart5: serial@2850000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -275,8 +288,6 @@ main_uart6: serial@2860000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -381,6 +392,52 @@ clocks = <&k3_clks 145 0>; }; + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + sdhci0: mmc@fa10000 { compatible = "ti,am64-sdhci-8bit"; reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; @@ -451,7 +508,8 @@ ti,mac-only; label = "port1"; phys = <&phy_gmii_sel 1>; - mac-address = [00 00 de ad be ef]; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&main_conf 0x200>; }; cpsw_port2: port@2 { @@ -459,7 +517,7 @@ ti,mac-only; label = "port2"; phys = <&phy_gmii_sel 2>; - mac-address = [00 01 de ad be ef]; + mac-address = [00 00 00 00 00 00]; }; }; @@ -485,30 +543,23 @@ }; }; - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <77 0 IRQ_TYPE_EDGE_RISING>, - <77 1 IRQ_TYPE_EDGE_RISING>, - <77 2 IRQ_TYPE_EDGE_RISING>, - <77 3 IRQ_TYPE_EDGE_RISING>, - <77 4 IRQ_TYPE_EDGE_RISING>, - <77 5 IRQ_TYPE_EDGE_RISING>, - <77 6 IRQ_TYPE_EDGE_RISING>, - <77 7 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 77 0>; - clock-names = "gpio"; + cpts@39000000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x39000000 0x0 0x400>; + reg-names = "cpts"; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 84 0>; + clock-names = "cpts"; + assigned-clocks = <&k3_clks 84 0>; + assigned-clock-parents = <&k3_clks 84 8>; + interrupts = ; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; }; usbss0: cdns-usb@f900000{ - compatible = "ti,am64-usb", "ti,j721e-usb"; + compatible = "ti,am64-usb"; reg = <0x00 0xf900000 0x00 0x100>; power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; @@ -537,69 +588,275 @@ }; }; - main_gpio1: gpio@601000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00601000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <78 0 IRQ_TYPE_EDGE_RISING>, - <78 1 IRQ_TYPE_EDGE_RISING>, - <78 2 IRQ_TYPE_EDGE_RISING>, - <78 3 IRQ_TYPE_EDGE_RISING>, - <78 4 IRQ_TYPE_EDGE_RISING>, - <78 5 IRQ_TYPE_EDGE_RISING>, - <78 6 IRQ_TYPE_EDGE_RISING>, - <78 7 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 78 0>; - clock-names = "gpio"; + tscadc0: tscadc@28001000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x00 0x28001000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 0>; + assigned-clock-parents = <&k3_clks 0 3>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; }; - main_i2c0: i2c@20000000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x0 0x20000000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 102 2>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&k3_clks 75 6>; + assigned-clocks = <&k3_clks 75 6>; + assigned-clock-parents = <&k3_clks 75 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + }; }; - main_i2c1: i2c@20010000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x0 0x20010000 0x0 0x100>; - interrupts = ; + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29030000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster4: mailbox@29040000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29040000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster5: mailbox@29050000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29050000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster6: mailbox@29060000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29060000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster7: mailbox@29070000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29070000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + main_r5fss0: r5fss@78000000 { + compatible = "ti,am64-r5fss"; + ti,cluster-mode = <0>; #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 103 2>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x10000>, + <0x78100000 0x00 0x78100000 0x10000>, + <0x78200000 0x00 0x78200000 0x08000>, + <0x78300000 0x00 0x78300000 0x08000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@78000000 { + compatible = "ti,am64-r5f"; + reg = <0x78000000 0x00010000>, + <0x78100000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am64-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@78200000 { + compatible = "ti,am64-r5f"; + reg = <0x78200000 0x00008000>, + <0x78300000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <122>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 122 1>; + firmware-name = "am64-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; }; - main_i2c2: i2c@20020000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20020000 0x0 0x100>; - interrupts = ; + main_r5fss1: r5fss@78400000 { + compatible = "ti,am64-r5fss"; + ti,cluster-mode = <0>; #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 104 2>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + #size-cells = <1>; + ranges = <0x78400000 0x00 0x78400000 0x10000>, + <0x78500000 0x00 0x78500000 0x10000>, + <0x78600000 0x00 0x78600000 0x08000>, + <0x78700000 0x00 0x78700000 0x08000>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@78400000 { + compatible = "ti,am64-r5f"; + reg = <0x78400000 0x00010000>, + <0x78500000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <123>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 123 1>; + firmware-name = "am64-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@78600000 { + compatible = "ti,am64-r5f"; + reg = <0x78600000 0x00008000>, + <0x78700000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <124>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 124 1>; + firmware-name = "am64-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; }; - main_i2c3: i2c@20030000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20030000 0x0 0x100>; - interrupts = ; + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + + assigned-clocks = <&k3_clks 162 1>; + assigned-clock-parents = <&k3_clks 162 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 162 1>, + <&k3_clks 162 1>, + <&k3_clks 162 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; + + pcie0_rc: pcie@f102000 { + compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + cdns,no-bar-match-nbits = <64>; + vendor-id = <0x104c>; + device-id = <0xb010>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + }; + + pcie0_ep: pcie-ep@f102000 { + compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; clock-names = "fck"; - clocks = <&k3_clks 105 2>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + max-functions = /bits/ 8 <1>; }; }; diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi index 1d2be485a6695085f3cc3906f97c3745369cf476..59cc58f7d0c8791d1fa211da9f480753d20f9fed 100644 --- a/arch/arm/dts/k3-am64-mcu.dtsi +++ b/arch/arm/dts/k3-am64-mcu.dtsi @@ -9,8 +9,6 @@ mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -22,8 +20,6 @@ mcu_uart1: serial@4a10000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -73,4 +69,32 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x4201000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <23>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; }; diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi index 6b2d0803b4f49b381d95ba0b4e5f7e850d8c9cc8..de6805b0c72c1709e8d2d96ca8e75954912f10f9 100644 --- a/arch/arm/dts/k3-am64.dtsi +++ b/arch/arm/dts/k3-am64.dtsi @@ -28,8 +28,6 @@ serial6 = &main_uart4; serial7 = &main_uart5; serial8 = &main_uart6; - i2c0 = &main_i2c0; - i2c1 = &main_i2c1; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; }; diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index 3a505d22c635062b38e13c61126bfd10381c40a1..0307122211889cac9afa8bb1bc6c9d907b60c3a4 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include #include #include @@ -36,6 +38,60 @@ alignment = <0x1000>; no-map; }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; evm_12v0: fixedregulator-evm12v0 { @@ -154,6 +210,15 @@ >; }; + main_spi0_pins_default: main-spi0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ + AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ + AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -207,6 +272,22 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ + AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ + >; + }; }; &main_uart0 { @@ -285,6 +366,11 @@ }; }; +/* mcu_gpio0 is reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + &mcu_i2c0 { status = "disabled"; }; @@ -301,28 +387,16 @@ status = "disabled"; }; -&cpsw3g { +&main_spi0 { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default - &rgmii2_pins_default>; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy3>; -}; - -&cpsw3g_mdio { - cpsw3g_phy0: ethernet-phy@0 { + pinctrl-0 = <&main_spi0_pins_default>; + ti,pindir-d0-out-d1-in; + eeprom@0 { + compatible = "microchip,93lc46b"; reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; + spi-max-frequency = <1000000>; + spi-cs-high; + data-size = <16>; }; }; @@ -355,3 +429,148 @@ pinctrl-names = "default"; pinctrl-0 = <&main_usb0_pins_default>; }; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default + &rgmii1_pins_default + &rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&tscadc0 { + /* ADC is reserved for R5 usage */ + status = "reserved"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mailbox0_cluster2 { + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts index df76c6e0b9ae6d536c383f9327be99ae74f32a64..d3aa2901e6fdaeb2cc400515dde2a3fb71dfc8dd 100644 --- a/arch/arm/dts/k3-am642-sk.dts +++ b/arch/arm/dts/k3-am642-sk.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include #include #include "k3-am642.dtsi" @@ -35,6 +37,93 @@ alignment = <0x1000>; no-map; }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; + }; + + vusb_main: fixed-regulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible = "regulator-fixed"; + regulator-name = "vusb_main5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: fixedregulator-vcc-3v3-sys { + /* output of LP8733xx */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: fixed-regulator-sd { + /* TPS2051BD */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; }; @@ -52,6 +141,12 @@ >; }; + main_usb0_pins_default: main-usb0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -99,6 +194,30 @@ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ >; }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ + AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ + >; + }; +}; + +&mcu_uart0 { + status = "disabled"; +}; + +&mcu_uart1 { + status = "disabled"; }; &main_uart1 { @@ -126,8 +245,51 @@ status = "disabled"; }; +&mcu_i2c0 { + status = "disabled"; +}; + +&mcu_i2c1 { + status = "disabled"; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "RPI_PS_3V3_En", + "RPI_PS_5V0_En", "RPI_HAT_DETECT"; + }; +}; + +&main_i2c3 { + status = "disabled"; +}; + +&mcu_spi0 { + status = "disabled"; +}; + +&mcu_spi1 { + status = "disabled"; +}; + +/* mcu_gpio0 is reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + &sdhci1 { /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; @@ -135,6 +297,33 @@ disable-wp; }; +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "host"; + maximum-speed = "super-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&mdio1_pins_default @@ -147,10 +336,120 @@ phy-handle = <&cpsw3g_phy0>; }; +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + &cpsw3g_mdio { cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&tscadc0 { + status = "disabled"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mailbox0_cluster2 { + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie0_ep { + status = "disabled"; }; diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..69479d7b18e16c124cca72ced485231cb7b882a0 --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2020-2021 + * + * Authors: + * Jan Kiszka + * Chao Zeng + */ + +#include + +/ { + binman { + filename = "flash.bin"; + pad-byte = <0xff>; + size = <0x8c0000>; + + blob-ext@0x000000 { + offset = <0x000000>; + filename = "tiboot3.bin"; + }; + + blob@0x080000 { + offset = <0x080000>; + filename = "tispl.bin"; + }; + + fit@0x280000 { + description = "U-Boot for IOT2050"; + offset = <0x280000>; + images { + u-boot { + description = "U-Boot"; + type = "standalone"; + arch = "arm64"; + os = "u-boot"; + compression = "none"; + load = <0x80800000>; + entry = <0x80800000>; + u-boot-nodtb { + }; + }; + + fdt-iot2050-basic { + description = "k3-am6528-iot2050-basic.dtb"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + blob { + filename = "arch/arm/dts/k3-am6528-iot2050-basic.dtb"; + }; + }; + + fdt-iot2050-basic-pg2 { + description = "k3-am6528-iot2050-basic-pg2.dtb"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + blob { + filename = "arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb"; + }; + }; + + fdt-iot2050-advanced { + description = "k3-am6548-iot2050-advanced.dtb"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + blob { + filename = "arch/arm/dts/k3-am6548-iot2050-advanced.dtb"; + }; + }; + + fdt-iot2050-advanced-pg2 { + description = "k3-am6548-iot2050-advanced-pg2.dtb"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + blob { + filename = "arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb"; + }; + }; + +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + k3-rti-wdt-firmware { + type = "firmware"; + load = <0x82000000>; + arch = "arm"; + compression = "none"; + blob-ext { + filename = CONFIG_WDT_K3_RTI_FW_FILE; + missing-msg = "k3-rti-wdt-firmware"; + }; + }; +#endif + }; + + configurations { + default = "conf-iot2050-basic"; + + conf-iot2050-basic { + description = "iot2050-basic"; + firmware = "u-boot"; + fdt = "fdt-iot2050-basic"; +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + loadables = "k3-rti-wdt-firmware"; +#endif + }; + + conf-iot2050-basic-pg2 { + description = "iot2050-basic-pg2"; + firmware = "u-boot"; + fdt = "fdt-iot2050-basic-pg2"; +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + loadables = "k3-rti-wdt-firmware"; +#endif + }; + + conf-iot2050-advanced { + description = "iot2050-advanced"; + firmware = "u-boot"; + fdt = "fdt-iot2050-advanced"; +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + loadables = "k3-rti-wdt-firmware"; +#endif + }; + + conf-iot2050-advanced-pg2 { + description = "iot2050-advanced-pg2"; + firmware = "u-boot"; + fdt = "fdt-iot2050-advanced-pg2"; +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + loadables = "k3-rti-wdt-firmware"; +#endif + }; + }; + }; + + /* primary env */ + fill@0x680000 { + offset = <0x680000>; + size = <0x020000>; + fill-byte = [00]; + }; + /* secondary env */ + fill@0x6a0000 { + offset = <0x6a0000>; + size = <0x020000>; + fill-byte = [00]; + }; + + /* PG1 sysfw, basic variant */ + blob-ext@0x6c0000 { + offset = <0x6c0000>; + filename = "sysfw.itb"; + }; + /* PG1 sysfw, advanced variant */ + blob-ext@0x740000 { + offset = <0x740000>; + filename = "sysfw.itb_HS"; + }; + /* PG2 sysfw, basic variant */ + blob-ext@0x7c0000 { + offset = <0x7c0000>; + filename = "sysfw_sr2.itb"; + }; + /* PG2 sysfw, advanced variant */ + blob-ext@0x840000 { + offset = <0x840000>; + filename = "sysfw_sr2.itb_HS"; + }; + }; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..51f902fa35a7377af0cf2c1fa2db0ca8495d3486 --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2021 + * + * Authors: + * Jan Kiszka + * + * Common bits of the IOT2050 Basic and Advanced variants, PG1 + */ + +&dss { + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; +}; + +&serdes0 { + status = "disabled"; +}; + +&sdhci1 { + no-1-8-v; +}; + +&tx_pru0_0 { + status = "disabled"; +}; + +&tx_pru0_1 { + status = "disabled"; +}; + +&tx_pru1_0 { + status = "disabled"; +}; + +&tx_pru1_1 { + status = "disabled"; +}; + +&tx_pru2_0 { + status = "disabled"; +}; + +&tx_pru2_1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c25bce7339b7fbd3320d4d2aa4aa41c482710eab --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2021 + * + * Authors: + * Chao Zeng + * Jan Kiszka + * + * Common bits of the IOT2050 Basic and Advanced variants, PG2 + */ + +&main_pmx0 { + cp2102n_reset_pin_default: cp2102n-reset-pin-default { + pinctrl-single,pins = < + /* (AF12) GPIO1_24, used as cp2102 reset */ + AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) + >; + }; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp2102n_reset_pin_default>; + gpio-line-names = + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "CP2102N-RESET"; +}; + +&dss { + /* Workaround needed to get DP clock of 154Mhz */ + assigned-clocks = <&k3_clks 67 0>; +}; + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0_phy { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..88c36fcf438302cd84948854a1ce4679ae3bff40 --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * Common U-Boot bits of the IOT2050 Basic and Advanced variants + */ + +/ { + aliases { + spi0 = &ospi0; + }; + + leds { + u-boot,dm-spl; + status-led-red { + u-boot,dm-spl; + }; + status-led-green { + u-boot,dm-spl; + }; + }; +}; + +&cbass_mcu { + u-boot,dm-spl; +}; + +&cbass_wakeup { + u-boot,dm-spl; +}; + +&cbass_main { + u-boot,dm-spl; + main-navss { + u-boot,dm-spl; + }; +}; + +&wkup_pmx0 { + u-boot,dm-spl; + mcu-fss0-ospi0-pins-default { + u-boot,dm-spl; + }; +}; + +&main_pmx0 { + u-boot,dm-spl; + main-uart1-pins-default { + u-boot,dm-spl; + }; +}; + +&main_uart1 { + u-boot,dm-spl; + current-speed = <115200>; +}; + +&wkup_gpio0 { + u-boot,dm-spl; +}; + +&ospi0 { + u-boot,dm-spl; + flash@0 { + u-boot,dm-spl; + }; +}; + +&secure_proxy_main { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + u-boot,dm-spl; + }; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&fss { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common.dtsi b/arch/arm/dts/k3-am65-iot2050-common.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..65da226847f45b594e9c7c251b298fee5933406b --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common.dtsi @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 + */ + +#include "k3-am654.dtsi" +#include + +/ { + aliases { + spi0 = &mcu_spi0; + mmc0 = &sdhci1; + mmc1 = &sdhci0; + }; + + chosen { + stdout-path = "serial3:115200n8"; + bootargs = "earlycon=ns16550a,mmio32,0x02810000"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: secure-ddr@9e800000 { + reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa0100000 0 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1100000 0 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a2000000 { + reg = <0x00 0xa2000000 0x00 0x00200000>; + alignment = <0x1000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + status-led-red { + gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + + status-led-green { + gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + user-led1-red { + gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; + }; + + user-led1-green { + gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; + }; + + user-led2-red { + gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; + }; + + user-led2-green { + gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; + }; + }; + + dp_refclk: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; +}; + +&wkup_pmx0 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + /* (AC7) WKUP_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) + /* (AD6) WKUP_I2C0_SDA */ + AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) + >; + }; + + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + /* (AD8) MCU_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) + /* (AD7) MCU_I2C0_SDA */ + AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) + >; + }; + + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default { + pinctrl-single,pins = < + /* (R2) WKUP_GPIO0_21 */ + AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) + >; + }; + + push_button_pins_default: push-button-pins-default { + pinctrl-single,pins = < + /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ + AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) + >; + }; + + arduino_uart_pins_default: arduino-uart-pins-default { + pinctrl-single,pins = < + /* (P4) MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) + /* (P5) MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) + >; + }; + + arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default { + pinctrl-single,pins = < + /* (P1) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7) + >; + }; + + arduino_io_oe_pins_default: arduino-io-oe-pins-default { + pinctrl-single,pins = < + /* (N4) WKUP_GPIO0_34 */ + AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) + /* (M2) WKUP_GPIO0_36 */ + AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) + /* (M3) WKUP_GPIO0_37 */ + AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) + /* (M4) WKUP_GPIO0_38 */ + AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) + /* (M1) WKUP_GPIO0_41 */ + AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) + >; + }; + + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + /* (V1) MCU_OSPI0_CLK */ + AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) + /* (U2) MCU_OSPI0_DQS */ + AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) + /* (U4) MCU_OSPI0_D0 */ + AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) + /* (U5) MCU_OSPI0_D1 */ + AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) + /* (R4) MCU_OSPI0_CSn0 */ + AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) + >; + }; + + db9_com_mode_pins_default: db9-com-mode-pins-default { + pinctrl-single,pins = < + /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ + AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) + /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */ + AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7) + /* (AC1) WKUP_GPIO0_7, used as uart0 term */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7) + /* (AC2) WKUP_GPIO0_6, used as uart0 en */ + AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7) + >; + }; + + leds_pins_default: leds-pins-default { + pinctrl-single,pins = < + /* (T2) WKUP_GPIO0_17, used as user led1 red */ + AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) + /* (R3) WKUP_GPIO0_22, used as user led1 green */ + AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7) + /* (R5) WKUP_GPIO0_24, used as status led red */ + AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7) + /* (N2) WKUP_GPIO0_32, used as status led green */ + AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7) + >; + }; + + mcu_spi0_pins_default: mcu-spi0-pins-default { + pinctrl-single,pins = < + /* (Y1) MCU_SPI0_CLK */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) + /* (Y3) MCU_SPI0_D0 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) + /* (Y2) MCU_SPI0_D1 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) + /* (Y4) MCU_SPI0_CS0 */ + AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) + >; + }; + + minipcie_pins_default: minipcie-pins-default { + pinctrl-single,pins = < + /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ + AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) + >; + }; +}; + +&main_pmx0 { + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ + AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ + AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */ + AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */ + >; + }; + + main_i2c3_pins_default: main-i2c3-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ + AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */ + >; + }; + + usb0_pins_default: usb0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; + + usb1_pins_default: usb1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ + >; + }; + + arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */ + >; + }; + + dss_vout1_pins_default: dss-vout1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ + AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ + AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ + AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ + AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ + AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ + AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ + AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ + AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ + AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ + AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ + AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ + AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ + AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ + AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ + AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ + AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ + AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ + AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ + AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ + AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ + AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ + AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ + AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ + AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ + AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ + AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ + AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ + >; + }; + + dp_pins_default: dp-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ + AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ + >; + }; +}; + +&main_pmx1 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ + AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ + AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ + >; + }; + + ecap0_pins_default: ecap0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ + >; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by System firmware */ + status = "reserved"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; +}; + +&main_uart2 { + status = "disabled"; +}; + +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&arduino_uart_pins_default>; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>; + gpio-line-names = + "main_gpio0-base", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "IO4", "", "IO5", "", "", "IO6", "", + "", "", "", "IO7", "", "", "", "", "IO8", "", + "", "IO9"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = < + &arduino_io_d2_to_d3_pins_default + &arduino_i2c_aio_switch_pins_default + &arduino_io_oe_pins_default + &push_button_pins_default + &db9_com_mode_pins_default + >; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", + /* 30..39 */ + "IO1", "IO2", "", "IO3", "IO17-direction", "A5", + "IO16-direction", "IO15-direction", "IO14-direction", "A3", + /* 40..49 */ + "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", + "IO11", + /* 50..51 */ + "IO12", "IO10"; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; + + psu: regulator@60 { + compatible = "ti,tps62363"; + reg = <0x60>; + regulator-name = "tps62363-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + }; + + /* D4200 */ + pcal9535_1: gpio@20 { + compatible = "nxp,pcal9535"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", + "A5-pull", "", "", + "IO14-enable", "IO15-enable", "IO16-enable", + "IO17-enable", "IO18-enable", "IO19-enable"; + }; + + /* D4201 */ + pcal9535_2: gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-direction", "IO1-direction", "IO2-direction", + "IO3-direction", "IO4-direction", "IO5-direction", + "IO6-direction", "IO7-direction", + "IO8-direction", "IO9-direction", "IO10-direction", + "IO11-direction", "IO12-direction", "IO13-direction", + "IO19-direction"; + }; + + /* D4202 */ + pcal9535_3: gpio@25 { + compatible = "nxp,pcal9535"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", + "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", + "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", + "IO12-pull", "IO13-pull"; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + rtc: rtc8564@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom: eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + edp-bridge@f { + compatible = "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&dp_pins_default>; + reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + clock-names = "ref"; + clocks = <&dp_refclk>; + + toshiba,hpd-pin = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; +}; + +&mcu_cpsw { + status = "disabled"; +}; + +&ecap0 { + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins_default>; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; + dr_mode = "host"; +}; + +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; + + #address-cells = <1>; + #size-cells= <0>; + ti,pindir-d0-out-d1-in; +}; + +&tscadc0 { + status = "disabled"; +}; + +&tscadc1 { + adc { + ti,adc-channels = <0 1 2 3 4 5>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <50000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout1_pins_default>; + + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + + dpi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie0_ep { + status = "disabled"; +}; + +&pcie1_rc { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins_default>; + + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + status = "disabled"; +}; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&mcu_r5fss0_core0 { + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +}; + +&mcu_r5fss0_core1 { + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +}; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; + +&icssg2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-spl.dts b/arch/arm/dts/k3-am65-iot2050-spl.dts new file mode 100644 index 0000000000000000000000000000000000000000..4e668fa3e039cd5e925f7ddf8e0dcd91bef13a6d --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-spl.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Jan Kiszka + */ + +/dts-v1/; + +#include "k3-am65-iot2050-common.dtsi" +#include "k3-am65-iot2050-common-u-boot.dtsi" + +/ { + compatible = "siemens,iot2050", "ti,am654"; + model = "Siemens IOT2050"; +}; diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 669484b0dd3b23fb73131d5712f052335a0a6e9c..ba4e5d3e1ed7a6d65f8a605d3a8556fa7f4c7a1d 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -84,8 +84,6 @@ main_uart0: serial@2800000 { compatible = "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -95,8 +93,6 @@ main_uart1: serial@2810000 { compatible = "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; @@ -105,8 +101,6 @@ main_uart2: serial@2820000 { compatible = "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; @@ -256,7 +250,7 @@ #size-cells = <0>; }; - sdhci0: sdhci@4f80000 { + sdhci0: mmc@4f80000 { compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; @@ -271,21 +265,16 @@ ti,otap-del-sel-sdr12 = <0x0>; ti,otap-del-sel-sdr25 = <0x0>; ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-sdr104 = <0x7>; ti,otap-del-sel-ddr50 = <0x5>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; ti,otap-del-sel-hs400 = <0x0>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-mmc-hs = <0x1>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; }; - sdhci1: sdhci@4fa0000 { + sdhci1: mmc@4fa0000 { compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; @@ -302,11 +291,8 @@ ti,otap-del-sel-ddr50 = <0x4>; ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-mmc-hs = <0x1>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; + ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; }; @@ -440,8 +426,9 @@ #phy-cells = <0>; }; - intr_main_gpio: interrupt-controller0 { + intr_main_gpio: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x0 0x00a00000 0x0 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -451,18 +438,19 @@ ti,interrupt-ranges = <0 392 32>; }; - main-navss { + main_navss: bus@30800000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; dma-coherent; dma-ranges; ti,sci-dev-id = <118>; - intr_main_navss: interrupt-controller1 { + intr_main_navss: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; + reg = <0x0 0x310e0000 0x0 0x2000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; @@ -714,6 +702,7 @@ dma-coherent; interrupts = ; msi-map = <0x0 &gic_its 0x0 0x10000>; + device_type = "pci"; }; pcie0_ep: pcie-ep@5500000 { @@ -746,6 +735,7 @@ dma-coherent; interrupts = ; msi-map = <0x0 &gic_its 0x10000 0x10000>; + device_type = "pci"; }; pcie1_ep: pcie-ep@5600000 { @@ -974,18 +964,6 @@ }; }; - icssg0_iep0: iep@2e000 { - compatible = "ti,am654-icss-iep"; - reg = <0x2e000 0x1000>; - clocks = <&icssg0_iepclk_mux>; - }; - - icssg0_iep1: iep@2f000 { - compatible = "ti,am654-icss-iep"; - reg = <0x2f000 0x1000>; - clocks = <&icssg0_iepclk_mux>; - }; - icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1077,7 +1055,6 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; - status = "disabled"; }; }; @@ -1128,18 +1105,6 @@ }; }; - icssg1_iep0: iep@2e000 { - compatible = "ti,am654-icss-iep"; - reg = <0x2e000 0x1000>; - clocks = <&icssg1_iepclk_mux>; - }; - - icssg1_iep1: iep@2f000 { - compatible = "ti,am654-icss-iep"; - reg = <0x2f000 0x1000>; - clocks = <&icssg1_iepclk_mux>; - }; - icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1231,7 +1196,6 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; - status = "disabled"; }; }; @@ -1282,18 +1246,6 @@ }; }; - icssg2_iep0: iep@2e000 { - compatible = "ti,am654-icss-iep"; - reg = <0x2e000 0x1000>; - clocks = <&icssg2_iepclk_mux>; - }; - - icssg2_iep1: iep@2f000 { - compatible = "ti,am654-icss-iep"; - reg = <0x2f000 0x1000>; - clocks = <&icssg2_iepclk_mux>; - }; - icssg2_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1385,8 +1337,6 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; - status = "disabled"; }; }; - }; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index 7454c8cec0cc584658deb99b719622a14f4520c2..c93ff1520a0e2897646aa3d8d031b767bc1ab431 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -23,8 +23,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; @@ -116,11 +114,11 @@ }; }; - mcu-navss { + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; dma-coherent; dma-ranges; @@ -308,4 +306,13 @@ ti,loczrama = <1>; }; }; + + mcu_rti1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x0 0x40610000 0x0 0x100>; + clocks = <&k3_clks 135 0>; + power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; + assigned-clocks = <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 135 4>; + }; }; diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi index ed42f13e7663479bbeefeb87d5d3817fc40782c8..9d21cdf6fce8fa8daef39dfa92cb19ef67bd784c 100644 --- a/arch/arm/dts/k3-am65-wakeup.dtsi +++ b/arch/arm/dts/k3-am65-wakeup.dtsi @@ -6,24 +6,24 @@ */ &cbass_wakeup { - dmsc: dmsc { + dmsc: system-controller@44083000 { compatible = "ti,am654-sci"; ti,host-id = <12>; - #address-cells = <1>; - #size-cells = <1>; - ranges; mbox-names = "rx", "tx"; mboxes= <&secure_proxy_main 11>, <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x44083000 0x1000>; + k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -50,8 +50,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -69,8 +67,9 @@ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; }; - intr_wkup_gpio: interrupt-controller2 { + intr_wkup_gpio: interrupt-controller@42200000 { compatible = "ti,sci-intr"; + reg = <0x42200000 0x200>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi index d84c0bc05023373e7cbebdd41c2c21655be79bb0..a9fc1af03f27f77bf1c78d5295a08415ce8bade4 100644 --- a/arch/arm/dts/k3-am65.dtsi +++ b/arch/arm/dts/k3-am65.dtsi @@ -56,7 +56,7 @@ }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = ; }; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0d215b4d668a1f4d81e2f19bf5564dad3293d11f --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * Common bits of the IOT2050 Basic variant, PG1 and PG2 + */ + +#include "k3-am65-iot2050-common.dtsi" + +#include "k3-am65-iot2050-common-u-boot.dtsi" +#include "k3-am65-iot2050-boot-image.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + cpus { + cpu-map { + /delete-node/ cluster1; + }; + /delete-node/ cpu@100; + /delete-node/ cpu@101; + }; + + /delete-node/ l2-cache1; +}; + +/* eMMC */ +&sdhci0 { + status = "disabled"; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ + AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */ + AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */ + AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */ + AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */ + >; + }; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&mcu_r5fss0 { + /* lock-step mode not supported on Basic boards */ + ti,cluster-mode = <0>; +}; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts b/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts new file mode 100644 index 0000000000000000000000000000000000000000..c62549a4b43679f53b1e5f60be553cb792502a41 --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2 + * 1 GB RAM, no eMMC, main_uart0 on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6528-iot2050-basic-common.dtsi" +#include "k3-am65-iot2050-common-pg2.dtsi" + +/ { + compatible = "siemens,iot2050-basic-pg2", "ti,am654"; + model = "SIMATIC IOT2050 Basic PG2"; +}; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic.dts b/arch/arm/dts/k3-am6528-iot2050-basic.dts new file mode 100644 index 0000000000000000000000000000000000000000..87928ff28214d027672c70b042aeb6b9c5234b09 --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1 + * 1 GB RAM, no eMMC, main_uart0 on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6528-iot2050-basic-common.dtsi" +#include "k3-am65-iot2050-common-pg1.dtsi" + +/ { + compatible = "siemens,iot2050-basic", "ti,am654"; + model = "SIMATIC IOT2050 Basic"; +}; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 7b2cdaf7dcb16bfde8feda3b55ed065a6f008118..cfbcebfa37c1df95ef85bad5b520bf4a93a0100a 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -86,10 +86,36 @@ }; }; - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_io: fixedregulator-vcc3v3io { + /* Output of TPS54334 */ + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&evm_12v0>; + }; + + vdd_mmc1_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc3v3_io>; + gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; }; }; @@ -142,7 +168,7 @@ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ - AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ + AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ >; }; @@ -287,23 +313,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - }; &main_i2c2 { @@ -322,7 +331,7 @@ pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; flash@0{ compatible = "jedec,spi-nor"; @@ -350,10 +359,10 @@ * disable sdhci1 */ &sdhci1 { + vmmc-supply = <&vdd_mmc1_sd>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; - sdhci-caps-mask = <0x7 0x0>; disable-wp; }; @@ -484,9 +493,9 @@ flash@0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; @@ -497,14 +506,6 @@ }; }; -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; @@ -538,3 +539,15 @@ &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; + +&icssg2_mdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi index 0f6df5b34b1784d57e4a0380d904bd049e3a84cc..26567f4167ffe491d6c5d67fba669234c9870c92 100644 --- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi @@ -23,7 +23,7 @@ &cbass_main{ u-boot,dm-spl; - main-navss { + main_navss: bus@30800000 { u-boot,dm-spl; }; }; @@ -31,7 +31,7 @@ &cbass_mcu { u-boot,dm-spl; - mcu-navss { + mcu_navss: bus@28380000 { u-boot,dm-spl; ringacc@2b800000 { diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..816a4cb4a68a4e49c29612078a0bd2c9de8f0ee9 --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * Common bits of the IOT2050 Advanced variant, PG1 and PG2 + */ + +/dts-v1/; + +#include "k3-am65-iot2050-common.dtsi" + +#include "k3-am65-iot2050-common-u-boot.dtsi" +#include "k3-am65-iot2050-boot-image.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; +}; + +&main_pmx0 { + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */ + AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ + >; + }; +}; + +/* eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_uart0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts new file mode 100644 index 0000000000000000000000000000000000000000..f00dc86d01b99a535445f852cc9f2a09f93f2391 --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2 + * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6548-iot2050-advanced-common.dtsi" +#include "k3-am65-iot2050-common-pg2.dtsi" + +/ { + compatible = "siemens,iot2050-advanced-pg2", "ti,am654"; + model = "SIMATIC IOT2050 Advanced PG2"; +}; + +&mcu_r5fss0 { + /* lock-step mode not supported on this board */ + ti,cluster-mode = <0>; +}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced.dts b/arch/arm/dts/k3-am6548-iot2050-advanced.dts new file mode 100644 index 0000000000000000000000000000000000000000..077f165bdc687f2fbf8f373913e808b3a980f639 --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1 + * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6548-iot2050-advanced-common.dtsi" +#include "k3-am65-iot2050-common-pg1.dtsi" + +/ { + compatible = "siemens,iot2050-advanced", "ti,am654"; + model = "SIMATIC IOT2050 Advanced"; +}; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 8a3f1891e22cc7483f4aa733071434102d1f16cd..1544c2e51bdee5cbb8695c7b496837b67013ab19 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -41,7 +41,7 @@ u-boot,dm-spl; }; - mcu-navss{ + mcu_navss: bus@28380000 { u-boot,dm-spl; #address-cells = <2>; #size-cells = <2>; @@ -118,10 +118,6 @@ u-boot,dm-spl; }; -&wkup_i2c0_pins_default { - u-boot,dm-spl; -}; - &wkup_i2c0 { u-boot,dm-spl; }; @@ -165,10 +161,6 @@ u-boot,dm-spl; }; -&wkup_gpio_pins_default { - u-boot,dm-spl; -}; - &mcu_fss0_hpb0_pins_default { u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index f0440cda1a71ecc5c45e3ac11ff78e5feebb68f3..d14f3c18b65fc0da98423015556ff22abc660840 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -17,51 +17,67 @@ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; - aliases { - remoteproc0 = &mcu_r5fss0_core0; - remoteproc1 = &mcu_r5fss0_core1; - remoteproc2 = &main_r5fss0_core0; - remoteproc3 = &main_r5fss0_core1; + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; }; vdd_mmc1: fixedregulator-sd { + /* Output of TPS22918 */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; enable-active-high; + vin-supply = <&vsys_3v3>; gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; }; - vdd_sd_dv: gpio-regulator-vdd-sd-dv { + vdd_sd_dv: gpio-regulator-TLV71033 { + /* Output of TLV71033 */ compatible = "regulator-gpio"; - regulator-name = "vdd_sd_dv"; + regulator-name = "tlv71033"; pinctrl-names = "default"; pinctrl-0 = <&vdd_sd_dv_pins_default>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; + vin-supply = <&vsys_5v0>; gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; }; }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ - >; - }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ @@ -74,7 +90,7 @@ J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; @@ -115,15 +131,15 @@ >; }; - vdd_sd_dv_pins_default: vdd_sd_dv_pins_default { + main_usbss0_pins_default: main-usbss0-pins-default { pinctrl-single,pins = < - J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { pinctrl-single,pins = < - J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; }; }; @@ -178,6 +194,22 @@ status = "disabled"; }; +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; @@ -288,7 +320,7 @@ }; &serdes0 { - serdes0_pcie_link: link@0 { + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -296,7 +328,7 @@ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; }; - serdes0_qsgmii_link: link@1 { + serdes0_qsgmii_link: phy@1 { reg = <2>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -304,3 +336,17 @@ resets = <&serdes_wiz0 3>; }; }; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index e1d43acc8550caf797d24375ced9304394572982..e8a41d09b45f2113b9b191cff29b1e04f4264d0b 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ / { @@ -68,8 +68,9 @@ }; }; - main_gpio_intr: interrupt-controller0 { + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -85,9 +86,12 @@ #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; ti,sci-dev-id = <199>; + dma-coherent; + dma-ranges; - main_navss_intr: interrupt-controller1 { + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; + reg = <0x00 0x310e0000 0x00 0x4000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; @@ -297,8 +301,6 @@ main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -310,8 +312,6 @@ main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -323,8 +323,6 @@ main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -336,8 +334,6 @@ main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -349,8 +345,6 @@ main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -362,8 +356,6 @@ main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -375,8 +367,6 @@ main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -388,8 +378,6 @@ main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -401,8 +389,6 @@ main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -414,8 +400,6 @@ main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -424,53 +408,6 @@ clock-names = "fclk"; }; - main_sdhci0: sdhci@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>; - interrupts = ; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - dma-coherent; - }; - - main_sdhci1: sdhci@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>; - interrupts = ; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - }; - main_i2c0: i2c@2000000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2000000 0x00 0x100>; @@ -548,26 +485,51 @@ power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; }; - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <105 0 IRQ_TYPE_EDGE_RISING>, - <105 1 IRQ_TYPE_EDGE_RISING>, - <105 2 IRQ_TYPE_EDGE_RISING>, - <105 3 IRQ_TYPE_EDGE_RISING>, - <105 4 IRQ_TYPE_EDGE_RISING>, - <105 5 IRQ_TYPE_EDGE_RISING>, - <105 6 IRQ_TYPE_EDGE_RISING>, - <105 7 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; + main_sdhci0: mmc@4f80000 { + compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; + reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,strobe-sel = <0x77>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + dma-coherent; + }; + + main_sdhci1: mmc@4fb0000 { + compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; + reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + dma-coherent; }; serdes_wiz0: wiz@5060000 { @@ -626,6 +588,54 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; @@ -653,12 +663,81 @@ "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; + cdns,phyrst-a-enable; }; }; + main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <145>, <146>, <147>, <148>, + <149>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 0>; + clock-names = "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <154>, <155>, <156>, <157>, + <158>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 0>; + clock-names = "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <163>, <164>, <165>, <166>, + <167>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 109 0>; + clock-names = "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <172>, <173>, <174>, <175>, + <176>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 111 0>; + clock-names = "gpio"; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <0>; + ti,cluster-mode = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5c00000 0x00 0x5c00000 0x20000>, @@ -672,7 +751,7 @@ reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xFF>; + ti,sci-proc-ids = <0x06 0xff>; resets = <&k3_reset 245 1>; firmware-name = "j7200-main-r5f0_0-fw"; ti,atcm-enable = <1>; @@ -687,7 +766,7 @@ reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xFF>; + ti,sci-proc-ids = <0x07 0xff>; resets = <&k3_reset 246 1>; firmware-name = "j7200-main-r5f0_1-fw"; ti,atcm-enable = <1>; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index ac78d4cb685bf43ff07c9aa1714853adf42386a1..1044ec6c4b0d4b10819fd7c04a0224895d22ed7d 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -2,11 +2,11 @@ /* * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { - dmsc: dmsc@44083000 { + dmsc: system-controller@44083000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -23,7 +23,7 @@ #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -73,8 +73,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -86,8 +84,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; @@ -96,8 +92,9 @@ clock-names = "fclk"; }; - wkup_gpio_intr: interrupt-controller2 { + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -107,6 +104,38 @@ ti,interrupt-ranges = <16 960 16>; }; + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <85>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 113 0>; + clock-names = "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <85>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "gpio"; + }; + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; @@ -269,6 +298,23 @@ #size-cells = <1>; mux-controls = <&hbmc_mux 0>; }; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x0 0x47040000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 103 0>; + assigned-clocks = <&k3_clks 103 0>; + assigned-clock-parents = <&k3_clks 103 2>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; }; tscadc0: tscadc@40200000 { diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi index 7b5e9aa0324e16129e4655866c4d50808ec17f47..34724440171a6c90ef3d5554d0ee0ba8f9d5a6ce 100644 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ b/arch/arm/dts/k3-j7200-som-p0.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -25,6 +25,60 @@ alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a4000000 { + reg = <0x00 0xa4000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; }; @@ -46,6 +100,22 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ >; }; + + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ + J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ + >; + }; }; &main_pmx0 { @@ -141,6 +211,30 @@ status = "disabled"; }; +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -157,3 +251,23 @@ "GPIO_LIN_EN", "CAN_STB"; }; }; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi index 66169bcf7c9a408e827dd21ffd51fe1617bd77d7..b7005b8031495e2e9fdff0396a883010eb902cf6 100644 --- a/arch/arm/dts/k3-j7200.dtsi +++ b/arch/arm/dts/k3-j7200.dtsi @@ -114,7 +114,7 @@ }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = ; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 85dbf8d2ac96e1b586e15d0883524b25e404567d..3ca9b5c801f008c120badca09151797e72c8ab42 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -34,7 +34,7 @@ &cbass_main{ u-boot,dm-spl; - main-navss { + main_navss: bus@30000000 { u-boot,dm-spl; }; }; @@ -50,7 +50,7 @@ u-boot,dm-spl; }; - mcu-navss { + mcu_navss: bus@28380000 { u-boot,dm-spl; ringacc@2b800000 { diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index 60764366e22bdb3f2fa9c151152d56441c14e93a..8bd02d9e28ad3ce30004b26de70433685ce4f639 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -9,6 +9,7 @@ #include #include #include +#include / { chosen { @@ -237,7 +238,7 @@ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; @@ -358,7 +359,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -635,8 +636,45 @@ status = "disabled"; }; +&cmn_refclk1 { + clock-frequency = <100000000>; +}; + +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + &serdes0 { - serdes0_pcie_link: link@0 { + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -646,7 +684,10 @@ }; &serdes1 { - serdes1_pcie_link: link@0 { + assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -656,7 +697,10 @@ }; &serdes2 { - serdes2_pcie_link: link@0 { + assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -718,3 +762,11 @@ &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 07b489679ed92b7e0fd62ee53a615073aefbee88..cf3482376c1e619f42a837c3169f4becbbb17176 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -8,6 +8,20 @@ #include #include +/ { + cmn_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cmn_refclk1: clock-cmnrefclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -28,38 +42,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_ctrl: syscon@4070 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4070 0x4070 0x4>; - }; - - pcie1_ctrl: syscon@4074 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4074 0x4074 0x4>; - }; - - pcie2_ctrl: syscon@4078 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4078 0x4078 0x4>; - }; - - pcie3_ctrl: syscon@407c { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x0000407c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x407c 0x407c 0x4>; - }; - serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; @@ -108,8 +90,9 @@ }; }; - main_gpio_intr: interrupt-controller0 { + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -119,18 +102,19 @@ ti,interrupt-ranges = <8 392 56>; }; - main-navss { + main_navss: bus@30000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; dma-coherent; dma-ranges; ti,sci-dev-id = <199>; - main_navss_intr: interrupt-controller1 { + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; + reg = <0x0 0x310e0000 0x0 0x4000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; @@ -368,24 +352,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; - dummy_cmn_refclk: dummy-cmn-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - dummy_cmn_refclk1: dummy-cmn-refclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; @@ -394,21 +366,21 @@ ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; @@ -430,10 +402,13 @@ reg = <0x5000000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, + <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -442,7 +417,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; @@ -451,21 +426,21 @@ ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; @@ -487,10 +462,13 @@ reg = <0x5010000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, + <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -499,7 +477,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; @@ -508,21 +486,21 @@ ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; @@ -544,10 +522,13 @@ reg = <0x5020000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, + <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -556,7 +537,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; @@ -565,21 +546,21 @@ ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; @@ -601,10 +582,13 @@ reg = <0x5030000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, + <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -618,7 +602,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -645,13 +629,12 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 239 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -667,7 +650,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -694,13 +677,12 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -716,7 +698,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -743,13 +725,12 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 241 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -765,7 +746,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; @@ -792,13 +773,12 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 242 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -809,8 +789,6 @@ main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -822,8 +800,6 @@ main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -835,8 +811,6 @@ main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -848,8 +822,6 @@ main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -861,8 +833,6 @@ main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -874,8 +844,6 @@ main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -887,8 +855,6 @@ main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -900,8 +866,6 @@ main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -913,8 +877,6 @@ main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -926,8 +888,6 @@ main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -1068,13 +1028,13 @@ clock-names = "gpio"; }; - main_sdhci0: sdhci@4f80000 { + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; interrupts = ; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; assigned-clocks = <&k3_clks 91 1>; assigned-clock-parents = <&k3_clks 91 2>; bus-width = <8>; @@ -1084,24 +1044,26 @@ ti,otap-del-sel-mmc-hs = <0xf>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-hs400 = <0x0>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; ti,trm-icp = <0x8>; + ti,strobe-sel = <0x77>; dma-coherent; }; - main_sdhci1: sdhci@4fb0000 { + main_sdhci1: mmc@4fb0000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; interrupts = ; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; @@ -1117,17 +1079,17 @@ sdhci-caps-mask = <0x2 0x0>; }; - main_sdhci2: sdhci@4f98000 { + main_sdhci2: mmc@4f98000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; interrupts = ; power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; @@ -1696,4 +1658,286 @@ resets = <&k3_reset 15 1>; firmware-name = "j7-c71_0-fw"; }; + + icssg0: icssg@b000000 { + compatible = "ti,j721e-icssg"; + reg = <0x00 0xb000000 0x00 0x80000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x0b000000 0x100000>; + + icssg0_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + icssg0_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg0_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ + <&k3_clks 119 1>; /* icssg0_iclk */ + assigned-clocks = <&icssg0_coreclk_mux>; + assigned-clock-parents = <&k3_clks 119 1>; + }; + + icssg0_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ + <&icssg0_coreclk_mux>; /* core_clk */ + assigned-clocks = <&icssg0_iepclk_mux>; + assigned-clock-parents = <&icssg0_coreclk_mux>; + }; + }; + }; + + icssg0_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg0_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg0_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru0_0: pru@34000 { + compatible = "ti,j721e-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-pru0_0-fw"; + }; + + rtu0_0: rtu@4000 { + compatible = "ti,j721e-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-rtu0_0-fw"; + }; + + tx_pru0_0: txpru@a000 { + compatible = "ti,j721e-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-txpru0_0-fw"; + }; + + pru0_1: pru@38000 { + compatible = "ti,j721e-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-pru0_1-fw"; + }; + + rtu0_1: rtu@6000 { + compatible = "ti,j721e-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-rtu0_1-fw"; + }; + + tx_pru0_1: txpru@c000 { + compatible = "ti,j721e-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-txpru0_1-fw"; + }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 119 1>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; + }; + + icssg1: icssg@b100000 { + compatible = "ti,j721e-icssg"; + reg = <0x00 0xb100000 0x00 0x80000>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x0b100000 0x100000>; + + icssg1_mem: memories@b100000 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + icssg1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ + <&k3_clks 120 4>; /* icssg1_iclk */ + assigned-clocks = <&icssg1_coreclk_mux>; + assigned-clock-parents = <&k3_clks 120 4>; + }; + + icssg1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ + <&icssg1_coreclk_mux>; /* core_clk */ + assigned-clocks = <&icssg1_iepclk_mux>; + assigned-clock-parents = <&icssg1_coreclk_mux>; + }; + }; + }; + + icssg1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg1_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg1_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru1_0: pru@34000 { + compatible = "ti,j721e-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-pru1_0-fw"; + }; + + rtu1_0: rtu@4000 { + compatible = "ti,j721e-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-rtu1_0-fw"; + }; + + tx_pru1_0: txpru@a000 { + compatible = "ti,j721e-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-txpru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,j721e-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-pru1_1-fw"; + }; + + rtu1_1: rtu@6000 { + compatible = "ti,j721e-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-rtu1_1-fw"; + }; + + tx_pru1_1: txpru@c000 { + compatible = "ti,j721e-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "j7-txpru1_1-fw"; + }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 120 4>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; + }; }; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 8750de7aa61130d0aabf2bf2cf6328a742b85f7f..d2dceda72fe97783b4b4c082673a137c5802e79b 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -6,7 +6,7 @@ */ &cbass_mcu_wakeup { - dmsc: dmsc@44083000 { + dmsc: system-controller@44083000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -23,7 +23,7 @@ #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -73,8 +73,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -86,8 +84,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; @@ -96,8 +92,9 @@ clock-names = "fclk"; }; - wkup_gpio_intr: interrupt-controller2 { + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -179,26 +176,8 @@ #size-cells = <2>; ranges; - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,j721e-hbmc", "ti,am654-hbmc"; - reg = <0x0 0x47034000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - assigned-clocks = <&k3_clks 102 0>; - assigned-clock-rates = <250000000>; - }; - ospi0: spi@47040000 { - compatible = "ti,am654-ospi"; + compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, <0x5 0x00000000 0x1 0x0000000>; interrupts = ; @@ -215,7 +194,7 @@ }; ospi1: spi@47050000 { - compatible = "ti,am654-ospi"; + compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47050000 0x0 0x100>, <0x7 0x00000000 0x1 0x00000000>; interrupts = ; @@ -267,11 +246,11 @@ }; }; - mcu-navss { + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; dma-coherent; dma-ranges; diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index ebc0f5bbc5bca2ce1c0f08d81141a07113340e03..2fee2906183d10b184f7795fe4332288975577a7 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -150,25 +150,6 @@ >; }; - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ - >; - }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ @@ -186,19 +167,6 @@ }; }; -&hbmc { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */ - <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x0 0x0 0x4000000>; - }; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -206,9 +174,9 @@ flash@0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi index 84693fce65206aa7431edff50d4b8264fbba3b23..f0587fde147e6f87ceb98e728c396233a28d4053 100644 --- a/arch/arm/dts/k3-j721e.dtsi +++ b/arch/arm/dts/k3-j721e.dtsi @@ -115,7 +115,7 @@ }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = ; }; @@ -126,7 +126,6 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts index f633074099dc16cf40dd15efe9ff22e3fc284a75..8e0f4eaf684a63fd8c6bba6dce0d5fc51c73ce80 100644 --- a/arch/arm/dts/ls1021a-tsn.dts +++ b/arch/arm/dts/ls1021a-tsn.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2018 NXP Semiconductors +/* Copyright 2016-2018 NXP * Copyright 2019 Vladimir Oltean */ diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 007646fcb43a02e5332b2abd87b729becf3fe7a6..e801331d80a14f85cf8f8c5472b82fb70cca3703 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -50,6 +50,18 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + ARM9260_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 77edd593b41658fa1ec4cac30e072c18a01e5c59..32ffe93b4d9f2ba5e25fbc280e81c748d1b6e8ec 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -7,6 +7,7 @@ * Author: Sandeep Sheriker M */ /dts-v1/; +#include #include "sam9x60.dtsi" / { @@ -57,7 +58,7 @@ }; flx0: flexcom@f801c600 { - atmel,flexcom-mode = <3>; + atmel,flexcom-mode = ; status = "okay"; i2c@600 { diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 6fb2cb25f984ea3300167f5e8698892664106741..d8a125b0735cf3238761a3b205cae3b57abcae68 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -32,7 +32,7 @@ #size-cells = <1>; u-boot,dm-pre-reloc; - usb1: ohci@00400000 { + usb1: ohci@400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; @@ -40,7 +40,7 @@ status = "disabled"; }; - usb2: ehci@00500000 { + usb2: ehci@500000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; clocks = <&utmi>, <&uhphs_clk>; diff --git a/arch/arm/dts/sama7g5-pinfunc.h b/arch/arm/dts/sama7g5-pinfunc.h index 89293e5470b479d7da381d34effd0b18aeb97cda..b5472fa4c9575233b9bb7a240b64b0ac53b497bf 100644 --- a/arch/arm/dts/sama7g5-pinfunc.h +++ b/arch/arm/dts/sama7g5-pinfunc.h @@ -921,4 +921,3 @@ #define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) #define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) #define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) - diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts index 3a4fdd38a59084dc34b927b174d49bded840ce72..1c59a8aaf8fc7690a64479b4ae3e963cb011a4ce 100644 --- a/arch/arm/dts/sama7g5ek.dts +++ b/arch/arm/dts/sama7g5ek.dts @@ -8,6 +8,7 @@ * 2020, Claudiu Beznea */ /dts-v1/; +#include #include "sama7g5.dtsi" #include "sama7g5-pinfunc.h" @@ -64,7 +65,7 @@ }; &flx1 { - atmel,flexcom-mode = <3>; + atmel,flexcom-mode = ; status = "okay"; }; diff --git a/arch/arm/dts/ste-ab8500.dtsi b/arch/arm/dts/ste-ab8500.dtsi index 14d4d8617d759469e8a6f0e51da6ef53aadc3595..dcc4a60c0ce2806332692dd2d624bfcb4e2bad85 100644 --- a/arch/arm/dts/ste-ab8500.dtsi +++ b/arch/arm/dts/ste-ab8500.dtsi @@ -42,15 +42,15 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; gpadc: ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "HW_CONV_END", "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_tvout_reg>; #address-cells = <1>; @@ -122,9 +122,11 @@ ab8500_temp { compatible = "stericsson,abx500-temp"; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ABX500_TEMP_WARM"; io-channels = <&gpadc 0x06>, <&gpadc 0x07>; - io-channel-name = "aux1", "aux2"; + io-channel-names = "aux1", "aux2"; }; ab8500_battery: ab8500_battery { @@ -134,29 +136,77 @@ ab8500_fg { compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "NCONV_ACCU", + "BATT_OVV", + "LOW_BAT_F", + "CC_INT_CALIB", + "CCEOC"; + battery = <&ab8500_battery>; io-channels = <&gpadc 0x08>; - io-channel-name = "main_bat_v"; + io-channel-names = "main_bat_v"; }; ab8500_btemp { compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "BAT_CTRL_INDB", + "BTEMP_LOW", + "BTEMP_HIGH", + "BTEMP_LOW_MEDIUM", + "BTEMP_MEDIUM_HIGH"; + battery = <&ab8500_battery>; io-channels = <&gpadc 0x02>, <&gpadc 0x01>; - io-channel-name = "btemp_ball", + io-channel-names = "btemp_ball", "bat_ctrl"; }; ab8500_charger { - compatible = "stericsson,ab8500-charger"; + compatible = "stericsson,ab8500-charger"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TYPE_LEVEL_HIGH>, + <107 IRQ_TYPE_LEVEL_HIGH>, + <106 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <105 IRQ_TYPE_LEVEL_HIGH>, + <104 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <21 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "MAIN_CH_UNPLUG_DET", + "MAIN_CHARGE_PLUG_DET", + "MAIN_EXT_CH_NOT_OK", + "MAIN_CH_TH_PROT_R", + "MAIN_CH_TH_PROT_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_CH_TH_PROT_R", + "USB_CH_TH_PROT_F", + "USB_CHARGER_NOT_OKR", + "VBUS_OVV", + "CH_WD_EXP", + "VBUS_CH_DROP_END"; battery = <&ab8500_battery>; vddadc-supply = <&ab8500_ldo_tvout_reg>; io-channels = <&gpadc 0x03>, <&gpadc 0x0a>, <&gpadc 0x09>, <&gpadc 0x0b>; - io-channel-name = "main_charger_v", + io-channel-names = "main_charger_v", "main_charger_c", "vbus_v", "usb_charger_c"; @@ -167,15 +217,15 @@ battery = <&ab8500_battery>; }; - ab8500_usb { + ab8500_usb: ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -188,12 +238,13 @@ musb_1v8-supply = <&db8500_vsmps2_reg>; clocks = <&prcmu_clk PRCMU_SYSCLK>; clock-names = "sysclk"; + #phy-cells = <0>; }; ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; @@ -201,7 +252,19 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm { + ab8500-pwm-1 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-pwm-2 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-pwm-3 { compatible = "stericsson,ab8500-pwm"; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; @@ -255,8 +318,8 @@ // supplies to the display/camera ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; /* BUG: If turned off MMC will be affected. */ regulator-always-on; @@ -324,5 +387,10 @@ vana-supply = <&ab8500_ldo_ana_reg>; }; }; + + usb_per5@a03e0000 { + phys = <&ab8500_usb>; + phy-names = "usb"; + }; }; }; diff --git a/arch/arm/dts/ste-ab8505.dtsi b/arch/arm/dts/ste-ab8505.dtsi index c72aa250bf6fe9144389197401bbd2cb5668fbd3..a1197fd37e62419905f8b1e2ab8cb2837b806560 100644 --- a/arch/arm/dts/ste-ab8505.dtsi +++ b/arch/arm/dts/ste-ab8505.dtsi @@ -13,7 +13,8 @@ <&gpadc 0x08>, /* Main battery voltage */ <&gpadc 0x09>, /* VBUS */ <&gpadc 0x0b>, /* Charger current */ - <&gpadc 0x0c>; /* Backup battery voltage */ + <&gpadc 0x0c>, /* Backup battery voltage */ + <&gpadc 0x0d>; /* Die temperature */ }; soc { @@ -38,16 +39,15 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; gpadc: ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_adc_reg>; #address-cells = <1>; #size-cells = <0>; @@ -84,42 +84,93 @@ bk_bat_v: channel@0c { reg = <0x0c>; }; + die_temp: channel@0d { + reg = <0x0d>; + }; usb_id: channel@0e { reg = <0x0e>; }; }; ab8500_battery: ab8500_battery { - status = "disabled"; + stericsson,battery-type = "LIPO"; thermistor-on-batctrl; }; ab8500_fg { status = "disabled"; compatible = "stericsson,ab8500-fg"; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "NCONV_ACCU", + "BATT_OVV", + "LOW_BAT_F", + "CC_INT_CALIB", + "CCEOC"; battery = <&ab8500_battery>; io-channels = <&gpadc 0x08>; - io-channel-name = "main_bat_v"; + io-channel-names = "main_bat_v"; }; ab8500_btemp { status = "disabled"; compatible = "stericsson,ab8500-btemp"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "BAT_CTRL_INDB", + "BTEMP_LOW", + "BTEMP_HIGH", + "BTEMP_LOW_MEDIUM", + "BTEMP_MEDIUM_HIGH"; battery = <&ab8500_battery>; io-channels = <&gpadc 0x02>, <&gpadc 0x01>; - io-channel-name = "btemp_ball", + io-channel-names = "btemp_ball", "bat_ctrl"; }; ab8500_charger { status = "disabled"; compatible = "stericsson,ab8500-charger"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TYPE_LEVEL_HIGH>, + <107 IRQ_TYPE_LEVEL_HIGH>, + <106 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <105 IRQ_TYPE_LEVEL_HIGH>, + <104 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <21 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "MAIN_CH_UNPLUG_DET", + "MAIN_CHARGE_PLUG_DET", + "MAIN_EXT_CH_NOT_OK", + "MAIN_CH_TH_PROT_R", + "MAIN_CH_TH_PROT_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_CH_TH_PROT_R", + "USB_CH_TH_PROT_F", + "USB_CHARGER_NOT_OKR", + "VBUS_OVV", + "CH_WD_EXP", + "VBUS_CH_DROP_END"; battery = <&ab8500_battery>; vddadc-supply = <&ab8500_ldo_adc_reg>; io-channels = <&gpadc 0x09>, <&gpadc 0x0b>; - io-channel-name = "vbus_v", + io-channel-names = "vbus_v", "usb_charger_c"; }; @@ -131,13 +182,13 @@ ab8500_usb: ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -150,12 +201,13 @@ musb_1v8-supply = <&db8500_vsmps2_reg>; clocks = <&prcmu_clk PRCMU_SYSCLK>; clock-names = "sysclk"; + #phy-cells = <0>; }; ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; @@ -271,5 +323,10 @@ vana-supply = <&ab8500_ldo_ana_reg>; }; }; + + usb_per5@a03e0000 { + phys = <&ab8500_usb>; + phy-names = "usb"; + }; }; }; diff --git a/arch/arm/dts/ste-dbx5x0-u-boot.dtsi b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi index 4a99ee5a923faab980d675aab5d9234f8bf6f987..e350175305e9721a4a403c5e8bff8e63a6309042 100644 --- a/arch/arm/dts/ste-dbx5x0-u-boot.dtsi +++ b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi @@ -4,8 +4,14 @@ #include "ste-dbx5x0.dtsi" / { + /* FIXME: Remove this when clk driver is implemented */ + sdmmcclk: sdmmcclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + soc { - /* FIXME: Remove this when clk driver is implemented */ mtu@a03c6000 { clock-frequency = <133000000>; }; @@ -18,6 +24,9 @@ uart@80007000 { clock = <38400000>; }; + mmc@80005000 { + clocks = <&sdmmcclk>; + }; }; reboot { diff --git a/arch/arm/dts/ste-dbx5x0.dtsi b/arch/arm/dts/ste-dbx5x0.dtsi index 6671f74c9f03d939f8d1245a32e3429dc2ab5751..68607e4ad80cb464a1b738ad4cdce82ab6f693d2 100644 --- a/arch/arm/dts/ste-dbx5x0.dtsi +++ b/arch/arm/dts/ste-dbx5x0.dtsi @@ -260,7 +260,7 @@ reg = <0x80150000 0x2000>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xa0412000 0x1000>; interrupts = ; @@ -883,7 +883,7 @@ status = "disabled"; }; - sdi0_per1@80126000 { + mmc@80126000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80126000 0x1000>; interrupts = ; @@ -899,7 +899,7 @@ status = "disabled"; }; - sdi1_per2@80118000 { + mmc@80118000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80118000 0x1000>; interrupts = ; @@ -915,7 +915,7 @@ status = "disabled"; }; - sdi2_per3@80005000 { + mmc@80005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80005000 0x1000>; interrupts = ; @@ -931,7 +931,7 @@ status = "disabled"; }; - sdi3_per2@80119000 { + mmc@80119000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; interrupts = ; @@ -947,7 +947,7 @@ status = "disabled"; }; - sdi4_per2@80114000 { + mmc@80114000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80114000 0x1000>; interrupts = ; @@ -963,7 +963,7 @@ status = "disabled"; }; - sdi5_per3@80008000 { + mmc@80008000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; interrupts = ; diff --git a/arch/arm/dts/ste-ux500-samsung-stemmy.dts b/arch/arm/dts/ste-ux500-samsung-stemmy.dts index 7e7f4c823a9e1df2d9f1f0bff796d155acfb792f..14be86086b225272d9a634fbfa1fe1ac355c4615 100644 --- a/arch/arm/dts/ste-ux500-samsung-stemmy.dts +++ b/arch/arm/dts/ste-ux500-samsung-stemmy.dts @@ -12,9 +12,25 @@ }; soc { + /* eMMC */ + mmc@80005000 { + status = "okay"; + + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + + non-removable; + cap-mmc-highspeed; + }; + /* Debugging console UART */ uart@80007000 { status = "okay"; }; + + mcde@a0350000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/dts/vexpress-v2m.dtsi b/arch/arm/dts/vexpress-v2m.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cc80146d555e85bd47b7f1217d9ed664828c057b --- /dev/null +++ b/arch/arm/dts/vexpress-v2m.dtsi @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + +/ { + smb@4000000 { + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + v2m_sysreg: sysreg@0 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + v2m_led_gpios: gpio@8 { + compatible = "arm,vexpress-sysreg,sys_led"; + reg = <0x008 4>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: gpio@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + reg = <0x048 4>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: gpio@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + reg = <0x04c 4>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + v2m_sysctl: sysctl@1000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@2000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@4000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmc0: mmci@5000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9>, <10>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + v2m_serial0: uart@9000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Both the core tile and the motherboard routes their output + * pads to this transmitter. The motherboard system controller + * can select one of them as input using a mux register in + * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is + * the only platform with this specific set-up. + */ + port@0 { + reg = <0>; + dvi_bridge_in_ct: endpoint { + remote-endpoint = <&clcd_pads_ct>; + }; + }; + port@1 { + reg = <1>; + dvi_bridge_in_mb: endpoint { + remote-endpoint = <&clcd_pads_mb>; + }; + }; + }; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 800x600 16bpp @36MHz works fine */ + max-memory-bandwidth = <54000000>; + memory-region = <&vram>; + + port { + clcd_pads_mb: endpoint { + remote-endpoint = <&dvi_bridge_in_mb>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; + + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + user1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + + user3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + user4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + user5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + user6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + user7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + user8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts new file mode 100644 index 0000000000000000000000000000000000000000..bf00c62bcf6ff8b5368236b0afdbb0c293b967bb --- /dev/null +++ b/arch/arm/dts/vexpress-v2p-ca9.dts @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; +#include "vexpress-v2m.dtsi" + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + mmc0 = &mmc0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A9_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + A9_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + A9_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + A9_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Chipselect 3 is physically at 0x4c000000 */ + vram: vram@4c000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x4c000000 0x00800000>; + no-map; + }; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + interrupts = <0 44 4>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz */ + max-memory-bandwidth = <95000000>; + + port { + clcd_pads_ct: endpoint { + remote-endpoint = <&dvi_bridge_in_ct>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "timclk", "apb_pclk"; + status = "disabled"; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "wdogclk", "apb_pclk"; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1e000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e000620 0x20>; + interrupts = <1 14 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; + + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0: extsaxiclk { + /* ACLK clock to the AXI master port on the test chip */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <30000000 50000000>; + #clock-cells = <0>; + clock-output-names = "extsaxiclk"; + }; + + oscclk1: clcdclk { + /* Reference clock for the CLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <10000000 80000000>; + #clock-cells = <0>; + clock-output-names = "clcdclk"; + }; + + smbclk: oscclk2: tcrefclk { + /* Reference clock for the test chip internal PLLs */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <33000000 100000000>; + #clock-cells = <0>; + clock-output-names = "tcrefclk"; + }; + + volt-vd10 { + /* Test Chip internal logic voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VD10"; + regulator-always-on; + label = "VD10"; + }; + + volt-vd10-s2 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "VD10_S2"; + regulator-always-on; + label = "VD10_S2"; + }; + + volt-vd10-s3 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 2>; + regulator-name = "VD10_S3"; + regulator-always-on; + label = "VD10_S3"; + }; + + volt-vcc1v8 { + /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 3>; + regulator-name = "VCC1V8"; + regulator-always-on; + label = "VCC1V8"; + }; + + volt-ddr2vtt { + /* DDR2 SDRAM VTT termination voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 4>; + regulator-name = "DDR2VTT"; + regulator-always-on; + label = "DDR2VTT"; + }; + + volt-vcc3v3 { + /* Local board supply for miscellaneous logic external to the Test Chip */ + arm,vexpress-sysreg,func = <2 5>; + compatible = "arm,vexpress-volt"; + regulator-name = "VCC3V3"; + regulator-always-on; + label = "VCC3V3"; + }; + + amp-vd10-s2 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "VD10_S2"; + }; + + amp-vd10-s3 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "VD10_S3"; + }; + + power-vd10-s2 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "PVD10_S2"; + }; + + power-vd10-s3 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "PVD10_S3"; + }; + }; + + smb: smb@4000000 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; + + site2: hsb@e0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000000 0x20000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index 94567190746883617da462ecb83f3920556fc974..e079edf30674edb417cdc3dd8ba8d71ad8c8469a 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -424,7 +424,7 @@ #define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 #define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 #define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 #define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 #define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 #define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 7a540b63f47135584710e0c7d0b51b8fde63cc5b..cf28167a7f74966f92f2803c4bf56cf7d238e30e 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -53,7 +53,7 @@ status = "okay"; num-cs = <1>; flash@0 { - compatible = "spansion,s25fl256s", "jedec,spi-nor"; + compatible = "spansion,s25fl256s1", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <30000000>; m25p,fast-read; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index bd0ba557e072748478b3f8ddf3d9def6ea010c24..f229880a70210b6ad5bf386faabe3e2e9cb1f83e 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -24,6 +24,9 @@ i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; + nvmem1 = &eeprom_ebm; + nvmem2 = &eeprom_fmc1; + nvmem3 = &eeprom_fmc2; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -477,6 +480,10 @@ silabs,skip-recall; }; /* and connector J212D */ + eeprom_ebm: eeprom@52 { /* x-ebm module */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x52>; + }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; @@ -484,6 +491,10 @@ reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ + eeprom_fmc1: eeprom@50 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x50>; + }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; @@ -491,6 +502,10 @@ reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ + eeprom_fmc2: eeprom@50 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x50>; + }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 4225a9547c5873fce6c8451a548910997a8c97a2..f32f87acacb6f6981f0ad4a66b15351def4c7fcd 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -140,6 +140,8 @@ nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-0"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; @@ -174,6 +176,8 @@ nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-1"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h index 493be6431167c45db8d23aebca4864edfadf36a0..e423c9d071f9071b69aa03729bca503740e3b730 100644 --- a/arch/arm/include/asm/arch-am33xx/chilisom.h +++ b/arch/arm/include/asm/arch-am33xx/chilisom.h @@ -6,7 +6,7 @@ #ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__ #define __ARCH_ARM_MACH_CHILISOM_SOM_H__ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) void chilisom_enable_pin_mux(void); void chilisom_spl_board_init(void); #endif diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 79081de700b486f43f172d85b536fd3200b6f854..b33e6f7fd1bdafab3b70e8dd7d5f45048bd45131 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -408,7 +408,7 @@ struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ unsigned int resv2[11]; - unsigned int clkselmacclk; /* offset 0x34 */ + unsigned int clkselmacclk; /* offset 0x34 */ }; #endif /* CONFIG_AM43XX */ diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h deleted file mode 100644 index dd21ad3c60552202279971d0df36c54b38d3c8c6..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#ifndef _ASM_ARCH_ARMADA100_H -#define _ASM_ARCH_ARMADA100_H - -#if defined (CONFIG_ARMADA100) - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Fast Ethernet Controller Clock register definition */ -#define FE_CLK_RST 0x1 -#define FE_CLK_ENA 0x8 - -/* SSP2 Clock Control */ -#define SSP2_APBCLK 0x01 -#define SSP2_FNCLK 0x02 - -/* USB Clock/reset control bits */ -#define USB_SPH_AXICLK_EN 0x10 -#define USB_SPH_AXI_RST 0x02 - -/* MPMU Clocks */ -#define APB2_26M_EN (1 << 20) -#define AP_26M (1 << 4) - -/* Register Base Addresses */ -#define ARMD1_DRAM_BASE 0xB0000000 -#define ARMD1_FEC_BASE 0xC0800000 -#define ARMD1_TIMER_BASE 0xD4014000 -#define ARMD1_APBC1_BASE 0xD4015000 -#define ARMD1_APBC2_BASE 0xD4015800 -#define ARMD1_UART1_BASE 0xD4017000 -#define ARMD1_UART2_BASE 0xD4018000 -#define ARMD1_GPIO_BASE 0xD4019000 -#define ARMD1_SSP1_BASE 0xD401B000 -#define ARMD1_SSP2_BASE 0xD401C000 -#define ARMD1_MFPR_BASE 0xD401E000 -#define ARMD1_SSP3_BASE 0xD401F000 -#define ARMD1_SSP4_BASE 0xD4020000 -#define ARMD1_SSP5_BASE 0xD4021000 -#define ARMD1_UART3_BASE 0xD4026000 -#define ARMD1_MPMU_BASE 0xD4050000 -#define ARMD1_USB_HOST_BASE 0xD4209000 -#define ARMD1_APMU_BASE 0xD4282800 -#define ARMD1_CPU_BASE 0xD4282C00 - -#endif /* CONFIG_ARMADA100 */ -#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h deleted file mode 100644 index 2862dd072b96b96862b2a417f5666940228a4a69..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - */ - -/* - * This file should be included in board config header file. - * - * It supports common definitions for Armada100 platform - */ - -#ifndef _ARMD1_CONFIG_H -#define _ARMD1_CONFIG_H - -#include - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE ARMD1_MFPR_BASE -#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ - -#endif /* _ARMD1_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h deleted file mode 100644 index cd5e5051d51d6f4c43aa559e992ad26389b8ba2f..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/cpu.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar , Contributor: Mahavir Jain - */ - -#ifndef _ARMADA100CPU_H -#define _ARMADA100CPU_H - -#include -#include - -/* - * Main Power Management (MPMU) Registers - * Refer Datasheet Appendix A.8 - */ -struct armd1mpmu_registers { - u8 pad0[0x08 - 0x00]; - u32 fccr; /*0x0008*/ - u32 pocr; /*0x000c*/ - u32 posr; /*0x0010*/ - u32 succr; /*0x0014*/ - u8 pad1[0x030 - 0x014 - 4]; - u32 gpcr; /*0x0030*/ - u8 pad2[0x200 - 0x030 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad3[0x1000 - 0x200 - 4]; - u32 apcr; /*0x1000*/ - u32 apsr; /*0x1004*/ - u8 pad4[0x1020 - 0x1004 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ - u32 arsr; /*0x1028*/ -}; - -/* - * Application Subsystem Power Management - * Refer Datasheet Appendix A.9 - */ -struct armd1apmu_registers { - u32 pcr; /* 0x000 */ - u32 ccr; /* 0x004 */ - u32 pad1; - u32 ccsr; /* 0x00C */ - u32 fc_timer; /* 0x010 */ - u32 pad2; - u32 ideal_cfg; /* 0x018 */ - u8 pad3[0x04C - 0x018 - 4]; - u32 lcdcrc; /* 0x04C */ - u32 cciccrc; /* 0x050 */ - u32 sd1crc; /* 0x054 */ - u32 sd2crc; /* 0x058 */ - u32 usbcrc; /* 0x05C */ - u32 nfccrc; /* 0x060 */ - u32 dmacrc; /* 0x064 */ - u32 pad4; - u32 buscrc; /* 0x06C */ - u8 pad5[0x07C - 0x06C - 4]; - u32 wake_clr; /* 0x07C */ - u8 pad6[0x090 - 0x07C - 4]; - u32 core_status; /* 0x090 */ - u32 rfsc; /* 0x094 */ - u32 imr; /* 0x098 */ - u32 irwc; /* 0x09C */ - u32 isr; /* 0x0A0 */ - u8 pad7[0x0B0 - 0x0A0 - 4]; - u32 mhst; /* 0x0B0 */ - u32 msr; /* 0x0B4 */ - u8 pad8[0x0C0 - 0x0B4 - 4]; - u32 msst; /* 0x0C0 */ - u32 pllss; /* 0x0C4 */ - u32 smb; /* 0x0C8 */ - u32 gccrc; /* 0x0CC */ - u8 pad9[0x0D4 - 0x0CC - 4]; - u32 smccrc; /* 0x0D4 */ - u32 pad10; - u32 xdcrc; /* 0x0DC */ - u32 sd3crc; /* 0x0E0 */ - u32 sd4crc; /* 0x0E4 */ - u8 pad11[0x0F0 - 0x0E4 - 4]; - u32 cfcrc; /* 0x0F0 */ - u32 mspcrc; /* 0x0F4 */ - u32 cmucrc; /* 0x0F8 */ - u32 fecrc; /* 0x0FC */ - u32 pciecrc; /* 0x100 */ - u32 epdcrc; /* 0x104 */ -}; - -/* - * APB1 Clock Reset/Control Registers - * Refer Datasheet Appendix A.10 - */ -struct armd1apb1_registers { - u32 uart1; /*0x000*/ - u32 uart2; /*0x004*/ - u32 gpio; /*0x008*/ - u32 pwm1; /*0x00c*/ - u32 pwm2; /*0x010*/ - u32 pwm3; /*0x014*/ - u32 pwm4; /*0x018*/ - u8 pad0[0x028 - 0x018 - 4]; - u32 rtc; /*0x028*/ - u32 twsi0; /*0x02c*/ - u32 kpc; /*0x030*/ - u32 timers; /*0x034*/ - u8 pad1[0x03c - 0x034 - 4]; - u32 aib; /*0x03c*/ - u32 sw_jtag; /*0x040*/ - u32 timer1; /*0x044*/ - u32 onewire; /*0x048*/ - u8 pad2[0x050 - 0x048 - 4]; - u32 asfar; /*0x050 AIB Secure First Access Reg*/ - u32 assar; /*0x054 AIB Secure Second Access Reg*/ - u8 pad3[0x06c - 0x054 - 4]; - u32 twsi1; /*0x06c*/ - u32 uart3; /*0x070*/ - u8 pad4[0x07c - 0x070 - 4]; - u32 timer2; /*0x07C*/ - u8 pad5[0x084 - 0x07c - 4]; - u32 ac97; /*0x084*/ -}; - -/* -* APB2 Clock Reset/Control Registers -* Refer Datasheet Appendix A.11 -*/ -struct armd1apb2_registers { - u32 pad1[0x01C - 0x000]; - u32 ssp1_clkrst; /* 0x01C */ - u32 ssp2_clkrst; /* 0x020 */ - u32 pad2[0x04C - 0x020 - 4]; - u32 ssp3_clkrst; /* 0x04C */ - u32 pad3[0x058 - 0x04C - 4]; - u32 ssp4_clkrst; /* 0x058 */ - u32 ssp5_clkrst; /* 0x05C */ -}; - -/* - * CPU Interface Registers - * Refer Datasheet Appendix A.2 - */ -struct armd1cpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 armd1_sdram_base(int); -u32 armd1_sdram_size(int); - -#endif /* _ARMADA100CPU_H */ diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h deleted file mode 100644 index b85f6a53d98b1338cb90925268fa3efc315402e2..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/gpio.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2010 - * Marvell Semiconductor - */ - -#ifndef _ASM_ARCH_GPIO_H -#define _ASM_ARCH_GPIO_H - -#include -#include - -#define GPIO_HIGH 1 -#define GPIO_LOW 0 - -#define GPIO_TO_REG(gp) (gp >> 5) -#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) -#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) - -static inline void *get_gpio_base(int bank) -{ - const unsigned int offset[4] = {0, 4, 8, 0x100}; - /* gpio register bank offset - refer Appendix A.36 */ - return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); -} - -#endif /* _ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h deleted file mode 100644 index a808ee85745bfc4e7b4d36f779fa2498a56e8f5c..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h - * (C) Copyright 2007 - * Marvell Semiconductor - * 2007-08-21: eric miao - * - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#ifndef __ARMADA100_MFP_H -#define __ARMADA100_MFP_H - -/* - * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART1 */ -#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART3 */ -#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* I2c */ -#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) - -/* Fast Ethernet */ -#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) - -/* SPI */ -#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ - -#define MFP_PIN_MAX 117 - -#endif /* __ARMADA100_MFP_H */ diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h deleted file mode 100644 index 873ba6e91c9d81cf004f97ccf9f595a9b97933b6..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/spi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2010 - * Marvell Semiconductor - */ - -#ifndef __ARMADA100_SPI_H_ -#define __ARMADA100_SPI_H_ - -#include - -#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE -#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) - -/* - * SSP Serial Port Registers - * refer Appendix A.26 - */ -struct ssp_reg { - u32 sscr0; /* SSP Control Register 0 - 0x000 */ - u32 sscr1; /* SSP Control Register 1 - 0x004 */ - u32 sssr; /* SSP Status Register - 0x008 */ - u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ - u32 ssdr; /* SSP Data Register - 0x010 */ - u32 pad1[5]; - u32 ssto; /* SSP Timeout Register - 0x028 */ - u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ - u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ - u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ - u32 sstss; /* SSP Timeslot Status Register - 0x038 */ -}; - -#define DEFAULT_WORD_LEN 8 -#define SSP_FLUSH_NUM 0x2000 -#define RX_THRESH_DEF 8 -#define TX_THRESH_DEF 8 -#define TIMEOUT_DEF 1000 - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity - setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ -#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ - -#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ -#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out - Interrupt enable */ - -#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ -#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF 0x30 /* FRame Format (mask) */ -#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial - Peripheral Interface */ -#define SSCR0_TI (0x1 << 4) /* TI's Synchronous - Serial Protocol (SSP) */ -#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port - Enable */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ - -#endif /* __ARMADA100_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h deleted file mode 100644 index 28147f42acf7515a927914c3157afc730291d4fb..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2009 - * Marvell Semiconductor - */ - -#ifndef __UTMI_ARMADA100__ -#define __UTMI_ARMADA100__ - -#define UTMI_PHY_BASE 0xD4206000 - -/* utmi_ctrl - bits */ -#define INPKT_DELAY_SOF (1 << 28) -#define PLL_PWR_UP 2 -#define PHY_PWR_UP 1 - -/* utmi_pll - bits */ -#define PLL_FBDIV_MASK 0x00000FF0 -#define PLL_FBDIV 4 -#define PLL_REFDIV_MASK 0x0000000F -#define PLL_REFDIV 0 -#define PLL_READY 0x800000 -#define VCOCAL_START (1 << 21) - -#define N_DIVIDER 0xEE -#define M_DIVIDER 0x0B - -/* utmi_tx - bits */ -#define CK60_PHSEL 17 -#define PHSEL_VAL 0x4 -#define RCAL_START (1 << 12) - -/* - * USB PHY registers - * Refer Datasheet Appendix A.21 - */ -struct armd1usb_phy_reg { - u32 utmi_rev; /* USB PHY Revision */ - u32 utmi_ctrl; /* USB PHY Control register */ - u32 utmi_pll; /* PLL register */ - u32 utmi_tx; /* Tx register */ - u32 utmi_rx; /* Rx register */ - u32 utmi_ivref; /* IVREF register */ - u32 utmi_tst_g0; /* Test group 0 register */ - u32 utmi_tst_g1; /* Test group 1 register */ - u32 utmi_tst_g2; /* Test group 2 register */ - u32 utmi_tst_g3; /* Test group 3 register */ - u32 utmi_tst_g4; /* Test group 4 register */ - u32 utmi_tst_g5; /* Test group 5 register */ - u32 utmi_reserve; /* Reserve Register */ - u32 utmi_usb_int; /* USB interuppt register */ - u32 utmi_dbg_ctl; /* Debug control register */ - u32 utmi_otg_addon; /* OTG addon register */ -}; - -int utmi_init(void); - -#endif /* __UTMI_ARMADA100__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 3675ce763d1dd70d69dd8a7e21d29fa74a21370d..733373ecf0b1df3a7d39d19bc4804dc1604493a3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -123,7 +123,6 @@ #elif defined(CONFIG_ARCH_LS1088A) #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_GICV3 #define CONFIG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 @@ -183,10 +182,6 @@ #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define TZPC_BASE 0x02200000 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #define SRDS_MAX_LANES 8 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -239,7 +234,6 @@ #elif defined(CONFIG_ARCH_LS1028A) #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_TZASC_400 diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h index 1cb2c57d31d143cec286cf680de35b10a1abc846..14f7c769b0c863f3567380395f9a59871ab326a4 100644 --- a/arch/arm/include/asm/arch-imxrt/imxrt.h +++ b/arch/arm/include/asm/arch-imxrt/imxrt.h @@ -8,4 +8,3 @@ #define _ASM_ARCH_IMXRT_H #endif /* _ASM_ARCH_IMXRT_H */ - diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h deleted file mode 100644 index 3045b78d08f41e26431ada62b7bc683618658c6f..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems - * - * Modified for mx25 by John Rigby - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#ifdef CONFIG_MX25_HCLK_FREQ -#define MXC_HCLK CONFIG_MX25_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX25_CLK32 -#define MXC_CLK32 CONFIG_MX25_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - /* PER clocks (do not change order) */ - MXC_CSI_CLK, - MXC_EPIT_CLK, - MXC_ESAI_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_GPT_CLK, - MXC_I2C_CLK, - MXC_LCDC_CLK, - MXC_NFC_CLK, - MXC_OWIRE_CLK, - MXC_PWM_CLK, - MXC_SIM1_CLK, - MXC_SIM2_CLK, - MXC_SSI1_CLK, - MXC_SSI2_CLK, - MXC_UART_CLK, - /* Other clocks */ - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_CLK_NUM -}; - -int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx25/gpio.h b/arch/arm/include/asm/arch-mx25/gpio.h deleted file mode 100644 index 1205695ce0548d238feeb3daa6b127fe5f8a97c4..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx25/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, - */ - - -#ifndef __ASM_ARCH_MX25_GPIO_H -#define __ASM_ARCH_MX25_GPIO_H - -#include - -#endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h deleted file mode 100644 index 57809697c1a8c7ad8cd242eb70afaa5f8544edfb..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ /dev/null @@ -1,504 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009, DENX Software Engineering - * Author: John Rigby - * and arch-mx27/imx-regs.h - * Copyright (C) 2007 Pengutronix, - * Sascha Hauer - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 mpctl; /* Core PLL Control */ - u32 upctl; /* USB PLL Control */ - u32 cctl; /* Clock Control */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 pcdr[4]; /* PER Clock Dividers */ - u32 rcsr; /* CCM Status */ - u32 crdr; /* CCM Reset and Debug */ - u32 dcvr0; /* DPTC Comparator Value 0 */ - u32 dcvr1; /* DPTC Comparator Value 1 */ - u32 dcvr2; /* DPTC Comparator Value 2 */ - u32 dcvr3; /* DPTC Comparator Value 3 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ - u32 ltbr1; /* Load Tracking Buffer 1 */ - u32 pcmr0; /* Power Management Control 0 */ - u32 pcmr1; /* Power Management Control 1 */ - u32 pcmr2; /* Power Management Control 2 */ - u32 mcr; /* Miscellaneous Control */ - u32 lpimr0; /* Low Power Interrupt Mask 0 */ - u32 lpimr1; /* Low Power Interrupt Mask 1 */ -}; - -/* Enhanced SDRAM Controller (ESDRAMC) registers */ -struct esdramc_regs { - u32 ctl0; /* control 0 */ - u32 cfg0; /* configuration 0 */ - u32 ctl1; /* control 1 */ - u32 cfg1; /* configuration 1 */ - u32 misc; /* miscellaneous */ - u32 pad[3]; - u32 cdly1; /* Delay Line 1 configuration debug */ - u32 cdly2; /* delay line 2 configuration debug */ - u32 cdly3; /* delay line 3 configuration debug */ - u32 cdly4; /* delay line 4 configuration debug */ - u32 cdly5; /* delay line 5 configuration debug */ - u32 cdlyl; /* delay line cycle length debug */ -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* Watchdog Timer (WDOG) registers */ -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Misc Control */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_25[0xa]; - u32 mac_addr[6]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr5; - u32 fuse23_29[7]; - u32 usr6[2]; -}; - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; -}; -/* LCD controller registers */ -struct lcdc_regs { - u32 lssar; /* Screen Start Address */ - u32 lsr; /* Size */ - u32 lvpwr; /* Virtual Page Width */ - u32 lcpr; /* Cursor Position */ - u32 lcwhb; /* Cursor Width Height and Blink */ - u32 lccmr; /* Color Cursor Mapping */ - u32 lpcr; /* Panel Configuration */ - u32 lhcr; /* Horizontal Configuration */ - u32 lvcr; /* Vertical Configuration */ - u32 lpor; /* Panning Offset */ - u32 lscr; /* Sharp Configuration */ - u32 lpccr; /* PWM Contrast Control */ - u32 ldcr; /* DMA Control */ - u32 lrmcr; /* Refresh Mode Control */ - u32 licr; /* Interrupt Configuration */ - u32 lier; /* Interrupt Enable */ - u32 lisr; /* Interrupt Status */ - u32 res0[3]; - u32 lgwsar; /* Graphic Window Start Address */ - u32 lgwsr; /* Graphic Window Size */ - u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ - u32 lgwpor; /* Graphic Window Panning Offset */ - u32 lgwpr; /* Graphic Window Position */ - u32 lgwcr; /* Graphic Window Control */ - u32 lgwdcr; /* Graphic Window DMA Control */ - u32 res1[5]; - u32 lauscr; /* AUS Mode Control */ - u32 lausccr; /* AUS mode Cursor Control */ - u32 res2[31 + 64*7]; - u32 bglut; /* Background Lookup Table */ - u32 gwlut; /* Graphic Window Lookup Table */ -}; - -/* Wireless External Interface Module Registers */ -struct weim_regs { - u32 cscr0u; /* Chip Select 0 Upper Register */ - u32 cscr0l; /* Chip Select 0 Lower Register */ - u32 cscr0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cscr1u; /* Chip Select 1 Upper Register */ - u32 cscr1l; /* Chip Select 1 Lower Register */ - u32 cscr1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cscr2u; /* Chip Select 2 Upper Register */ - u32 cscr2l; /* Chip Select 2 Lower Register */ - u32 cscr2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cscr3u; /* Chip Select 3 Upper Register */ - u32 cscr3l; /* Chip Select 3 Lower Register */ - u32 cscr3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cscr4u; /* Chip Select 4 Upper Register */ - u32 cscr4l; /* Chip Select 4 Lower Register */ - u32 cscr4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cscr5u; /* Chip Select 5 Upper Register */ - u32 cscr5l; /* Chip Select 5 Lower Register */ - u32 cscr5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 wcr; /* WEIM Configuration Register */ -}; - -/* Multi-Master Memory Interface */ -struct m3if_regs { - u32 ctl; /* Control Register */ - u32 wcfg0; /* Watermark Configuration Register 0 */ - u32 wcfg1; /* Watermark Configuration Register1 */ - u32 wcfg2; /* Watermark Configuration Register2 */ - u32 wcfg3; /* Watermark Configuration Register 3 */ - u32 wcfg4; /* Watermark Configuration Register 4 */ - u32 wcfg5; /* Watermark Configuration Register 5 */ - u32 wcfg6; /* Watermark Configuration Register 6 */ - u32 wcfg7; /* Watermark Configuration Register 7 */ - u32 wcsr; /* Watermark Control and Status Register */ - u32 scfg0; /* Snooping Configuration Register 0 */ - u32 scfg1; /* Snooping Configuration Register 1 */ - u32 scfg2; /* Snooping Configuration Register 2 */ - u32 ssr0; /* Snooping Status Register 0 */ - u32 ssr1; /* Snooping Status Register 1 */ - u32 res0; - u32 mlwe0; /* Master Lock WEIM CS0 Register */ - u32 mlwe1; /* Master Lock WEIM CS1 Register */ - u32 mlwe2; /* Master Lock WEIM CS2 Register */ - u32 mlwe3; /* Master Lock WEIM CS3 Register */ - u32 mlwe4; /* Master Lock WEIM CS4 Register */ - u32 mlwe5; /* Master Lock WEIM CS5 Register */ -}; - -/* Pulse width modulation */ -struct pwm_regs { - u32 cr; /* Control Register */ - u32 sr; /* Status Register */ - u32 ir; /* Interrupt Register */ - u32 sar; /* Sample Register */ - u32 pr; /* Period Register */ - u32 cnr; /* Counter Register */ -}; - -/* Enhanced Periodic Interrupt Timer */ -struct epit_regs { - u32 cr; /* Control register */ - u32 sr; /* Status register */ - u32 lr; /* Load register */ - u32 cmpr; /* Compare register */ - u32 cnr; /* Counter register */ -}; - -#endif - -#define ARCH_MXC - -/* AIPS 1 */ -#define IMX_AIPS1_BASE (0x43F00000) -#define IMX_MAX_BASE (0x43F04000) -#define IMX_CLKCTL_BASE (0x43F08000) -#define IMX_ETB_SLOT4_BASE (0x43F0C000) -#define IMX_ETB_SLOT5_BASE (0x43F10000) -#define IMX_ECT_CTIO_BASE (0x43F18000) -#define I2C1_BASE_ADDR (0x43F80000) -#define I2C3_BASE_ADDR (0x43F84000) -#define IMX_CAN1_BASE (0x43F88000) -#define IMX_CAN2_BASE (0x43F8C000) -#define UART1_BASE (0x43F90000) -#define UART2_BASE (0x43F94000) -#define I2C2_BASE_ADDR (0x43F98000) -#define IMX_OWIRE_BASE (0x43F9C000) -#define IMX_CSPI1_BASE (0x43FA4000) -#define IMX_KPP_BASE (0x43FA8000) -#define IMX_IOPADMUX_BASE (0x43FAC000) -#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE -#define IMX_IOPADCTL_BASE (0x43FAC22C) -#define IMX_IOPADGRPCTL_BASE (0x43FAC418) -#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) -#define IMX_AUDMUX_BASE (0x43FB0000) -#define IMX_ECT_IP1_BASE (0x43FB8000) -#define IMX_ECT_IP2_BASE (0x43FBC000) - -/* SPBA */ -#define IMX_SPBA_BASE (0x50000000) -#define IMX_CSPI3_BASE (0x50004000) -#define UART4_BASE (0x50008000) -#define UART3_BASE (0x5000C000) -#define IMX_CSPI2_BASE (0x50010000) -#define IMX_SSI2_BASE (0x50014000) -#define IMX_ESAI_BASE (0x50018000) -#define IMX_ATA_DMA_BASE (0x50020000) -#define IMX_SIM1_BASE (0x50024000) -#define IMX_SIM2_BASE (0x50028000) -#define UART5_BASE (0x5002C000) -#define IMX_TSC_BASE (0x50030000) -#define IMX_SSI1_BASE (0x50034000) -#define IMX_FEC_BASE (0x50038000) -#define IMX_SPBA_CTRL_BASE (0x5003C000) - -/* AIPS 2 */ -#define IMX_AIPS2_BASE (0x53F00000) -#define IMX_CCM_BASE (0x53F80000) -#define IMX_GPT4_BASE (0x53F84000) -#define IMX_GPT3_BASE (0x53F88000) -#define IMX_GPT2_BASE (0x53F8C000) -#define IMX_GPT1_BASE (0x53F90000) -#define IMX_EPIT1_BASE (0x53F94000) -#define IMX_EPIT2_BASE (0x53F98000) -#define IMX_GPIO4_BASE (0x53F9C000) -#define IMX_PWM2_BASE (0x53FA0000) -#define IMX_GPIO3_BASE (0x53FA4000) -#define IMX_PWM3_BASE (0x53FA8000) -#define IMX_SCC_BASE (0x53FAC000) -#define IMX_SCM_BASE (0x53FAE000) -#define IMX_SMN_BASE (0x53FAF000) -#define IMX_RNGD_BASE (0x53FB0000) -#define IMX_MMC_SDHC1_BASE (0x53FB4000) -#define IMX_MMC_SDHC2_BASE (0x53FB8000) -#define IMX_LCDC_BASE (0x53FBC000) -#define IMX_SLCDC_BASE (0x53FC0000) -#define IMX_PWM4_BASE (0x53FC8000) -#define IMX_GPIO1_BASE (0x53FCC000) -#define IMX_GPIO2_BASE (0x53FD0000) -#define IMX_SDMA_BASE (0x53FD4000) -#define IMX_WDT_BASE (0x53FDC000) -#define WDOG1_BASE_ADDR IMX_WDT_BASE -#define IMX_PWM1_BASE (0x53FE0000) -#define IMX_RTIC_BASE (0x53FEC000) -#define IMX_IIM_BASE (0x53FF0000) -#define IIM_BASE_ADDR IMX_IIM_BASE -#define IMX_USB_BASE (0x53FF4000) -/* - * This is in contradiction to the imx25 reference manual, which says that - * port 1's registers start at 0x53FF4200. The correct base address for - * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well. - */ -#define IMX_USB_PORT_OFFSET 0x400 -#define IMX_CSI_BASE (0x53FF8000) -#define IMX_DRYICE_BASE (0x53FFC000) - -#define IMX_ARM926_ROMPATCH (0x60000000) -#define IMX_ARM926_ASIC (0x68000000) - -/* 128K Internal Static RAM */ -#define IMX_RAM_BASE (0x78000000) -#define IMX_RAM_SIZE (128 * 1024) - -/* SDRAM BANKS */ -#define IMX_SDRAM_BANK0_BASE (0x80000000) -#define IMX_SDRAM_BANK1_BASE (0x90000000) - -#define IMX_WEIM_CS0 (0xA0000000) -#define IMX_WEIM_CS1 (0xA8000000) -#define IMX_WEIM_CS2 (0xB0000000) -#define IMX_WEIM_CS3 (0xB2000000) -#define IMX_WEIM_CS4 (0xB4000000) -#define IMX_ESDRAMC_BASE (0xB8001000) -#define IMX_WEIM_CTRL_BASE (0xB8002000) -#define IMX_M3IF_CTRL_BASE (0xB8003000) -#define IMX_EMI_CTRL_BASE (0xB8004000) - -/* NAND Flash Controller */ -#define IMX_NFC_BASE (0xBB000000) -#define NFC_BASE_ADDR IMX_NFC_BASE - -/* CCM bitfields */ -#define CCM_PLL_MFI_SHIFT 10 -#define CCM_PLL_MFI_MASK 0xf -#define CCM_PLL_MFN_SHIFT 0 -#define CCM_PLL_MFN_MASK 0x3ff -#define CCM_PLL_MFD_SHIFT 16 -#define CCM_PLL_MFD_MASK 0x3ff -#define CCM_PLL_PD_SHIFT 26 -#define CCM_PLL_PD_MASK 0xf -#define CCM_CCTL_ARM_DIV_SHIFT 30 -#define CCM_CCTL_ARM_DIV_MASK 3 -#define CCM_CCTL_AHB_DIV_SHIFT 28 -#define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) -#define CCM_CGR1_GPT1 (1 << 19) -#define CCM_PERCLK_REG(clk) (clk / 4) -#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) -#define CCM_PERCLK_MASK 0x3f -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) -#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) -#define CCM_CRDR_BT_UART_SRC_SHIFT 29 -#define CCM_CRDR_BT_UART_SRC_MASK 7 - -/* ESDRAM Controller register bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -/* GPT bits */ -#define GPT_CTRL_SWR (1 << 15) /* Software reset */ -#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ -#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPT_CTRL_TEN 1 /* Timer enable */ - -/* WDOG enable */ -#define WCR_WDE 0x04 -#define WSR_UNLOCK1 0x5555 -#define WSR_UNLOCK2 0xAAAA - -/* MAX bits */ -#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) - -/* M3IF bits */ -#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) - -/* WEIM bits */ -/* 13 fields of the upper CS control register */ -#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ - (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ - (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -/* Names used in GPIO driver */ -#define GPIO1_BASE_ADDR IMX_GPIO1_BASE -#define GPIO2_BASE_ADDR IMX_GPIO2_BASE -#define GPIO3_BASE_ADDR IMX_GPIO3_BASE -#define GPIO4_BASE_ADDR IMX_GPIO4_BASE - -/* - * CSPI register definitions - */ -#define MXC_SPI_BASE_ADDRESSES \ - IMX_CSPI1_BASE, \ - IMX_CSPI2_BASE, \ - IMX_CSPI3_BASE - -#endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h deleted file mode 100644 index 1ce7a8586f83fe2c46401a52567f6104f4371db3..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx25/iomux-mx25.h +++ /dev/null @@ -1,537 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau - * - * Based on mainline Linux i.MX iomux-mx25.h file: - * Copyright (C) 2009 by Lothar Wassmann - * - * Based on Linux arch/arm/mach-mx25/mx25_pins.h: - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH - */ - -#ifndef __IOMUX_MX25_H__ -#define __IOMUX_MX25_H__ - -#include - -/* Pad control groupings */ -#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP -#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -/* - * The naming convention for the pad modes is MX25_PAD___ - * If or refers to a GPIO, it is named GPIO__ - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL), - - MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL), - MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL), - - MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL), - - MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL), - - MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL), - - MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL), - MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL), - MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL), - MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL), - MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL), - MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE), - MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE), - - MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL), - MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL), - MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL), - - MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL), - - MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL), - - MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL), - - MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL), - - MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL), - - MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL), - - MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE), - MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN), - MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL), - MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL), - MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL), - - /* - * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the SD1_CMD function doesn't enable the input path for - * this pin. - * This might have side effects for other hardware units that are connected to - * that pin and use the respective function as input. - */ - MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL), - MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE), - - MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL), - MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX25_H__ */ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h deleted file mode 100644 index 68bddf49526ed318876986ab935aec31304cc3ae..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx25/macro.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Matthias Weisser - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * Common asm macros for imx25 - */ - -#ifndef __ASM_ARM_ARCH_MACRO_H__ -#define __ASM_ARM_ARCH_MACRO_H__ -#ifdef __ASSEMBLY__ - -#include -#include -#include - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - */ -.macro init_aips mpr=0x77777777 - ldr r0, =IMX_AIPS1_BASE - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =IMX_AIPS2_BASE - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =IMX_MAX_BASE - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 - * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 - * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000001 - */ -.macro init_m3if ctl=0x00000001 - /* M3IF Control Register (M3IFCTL) */ - write32 IMX_M3IF_CTRL_BASE, \ctl -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h deleted file mode 100644 index cb0b53a69f4df6b9ba7aa372f85752126da31025..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#ifdef CONFIG_MX35_HCLK_FREQ -#define MXC_HCLK CONFIG_MX35_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX35_CLK32 -#define MXC_CLK32 CONFIG_MX35_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_USB_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; - -enum mxc_main_clock { - CPU_CLK, - AHB_CLK, - IPG_CLK, - IPG_PER_CLK, - NFC_CLK, - USB_CLK, - HSP_CLK, -}; - -enum mxc_peri_clock { - UART1_BAUD, - UART2_BAUD, - UART3_BAUD, - SSI1_BAUD, - SSI2_BAUD, - CSI_BAUD, - MSHC_CLK, - ESDHC1_CLK, - ESDHC2_CLK, - ESDHC3_CLK, - SPDIF_CLK, - SPI1_CLK, - SPI2_CLK, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h deleted file mode 100644 index fc65a3ad343a4baf934421272c0956d35cc71af6..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ -#define __CPU_ARM1136_MX35_CRM_REGS_H__ - -/* Register bit definitions */ -#define MXC_CCM_CCMR_WFI (1 << 30) -#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) -#define MXC_CCM_CCMR_VSTBY (1 << 28) -#define MXC_CCM_CCMR_WBEN (1 << 27) -#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 -#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) -#define MXC_CCM_CCMR_ROMW_OFFSET 18 -#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 16 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) -#define MXC_CCM_CCMR_LPM_OFFSET 14 -#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) -#define MXC_CCM_CCMR_UPE (1 << 9) -#define MXC_CCM_CCMR_MPE (1 << 3) - -#define MXC_CCM_PDR0_PER_SEL (1 << 26) -#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) -#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 -#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) -#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 -#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) -#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) -#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) -#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 -#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) -#define MXC_CCM_PDR0_AUTO_CON 0x1 - -#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 -#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) -#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 -#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) - -#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 -#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) -#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 -#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 -#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR2_CSI_M_U (1 << 7) -#define MXC_CCM_PDR2_SSI_M_U (1 << 6) -#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 -#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) - -#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 -#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) -#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 -#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) -#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 14) -#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) - -#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 -#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) -#define MXC_CCM_PDR4_USB_M_U (1 << 9) - -/* Bit definitions for RCSR */ -#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) -#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) -#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) -#define MXC_CCM_RCSR_PAGE_512 (0 << 27) -#define MXC_CCM_RCSR_PAGE_2K (1 << 27) -#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) -#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) -#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) -#define MXC_CCM_RCSR_NF16B (1 << 14) -#define MXC_CCM_RCSR_NFC_4K (1 << 9) -#define MXC_CCM_RCSR_NFC_FMS (1 << 8) - -/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ -#define MXC_CCM_PCTL_BRM 0x80000000 -#define MXC_CCM_PCTL_PD_OFFSET 26 -#define MXC_CCM_PCTL_PD_MASK (0xF << 26) -#define MXC_CCM_PCTL_MFD_OFFSET 16 -#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) -#define MXC_CCM_PCTL_MFI_OFFSET 10 -#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) -#define MXC_CCM_PCTL_MFN_OFFSET 0 -#define MXC_CCM_PCTL_MFN_MASK 0x3FF - -/* Bit definitions for Audio clock mux register*/ -#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 -#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) -#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 -#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) -#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 -#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) -#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 -#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) - -/* Bit definitions for Clock gating Register*/ -#define MXC_CCM_CGR_CG_MASK 0x3 -#define MXC_CCM_CGR_CG_OFF 0x0 -#define MXC_CCM_CGR_CG_RUN_ON 0x1 -#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 -#define MXC_CCM_CGR_CG_ON 0x3 - -#define MXC_CCM_CGR0_ASRC_OFFSET 0 -#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) -#define MXC_CCM_CGR0_ATA_OFFSET 2 -#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) -#define MXC_CCM_CGR0_CAN1_OFFSET 6 -#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) -#define MXC_CCM_CGR0_CAN2_OFFSET 8 -#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) -#define MXC_CCM_CGR0_CSPI1_OFFSET 10 -#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) -#define MXC_CCM_CGR0_CSPI2_OFFSET 12 -#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) -#define MXC_CCM_CGR0_ECT_OFFSET 14 -#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) -#define MXC_CCM_CGR0_EDIO_OFFSET 16 -#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) -#define MXC_CCM_CGR0_EMI_OFFSET 18 -#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) -#define MXC_CCM_CGR0_EPIT1_OFFSET 20 -#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) -#define MXC_CCM_CGR0_EPIT2_OFFSET 22 -#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) -#define MXC_CCM_CGR0_ESAI_OFFSET 24 -#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) -#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 -#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) -#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 -#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) -#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 -#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) - -#define MXC_CCM_CGR1_FEC_OFFSET 0 -#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) -#define MXC_CCM_CGR1_GPIO1_OFFSET 2 -#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) -#define MXC_CCM_CGR1_GPIO2_OFFSET 4 -#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) -#define MXC_CCM_CGR1_GPIO3_OFFSET 6 -#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) -#define MXC_CCM_CGR1_GPT_OFFSET 8 -#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) -#define MXC_CCM_CGR1_I2C1_OFFSET 10 -#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) -#define MXC_CCM_CGR1_I2C2_OFFSET 12 -#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) -#define MXC_CCM_CGR1_I2C3_OFFSET 14 -#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) -#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 -#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) -#define MXC_CCM_CGR1_IPU_OFFSET 18 -#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) -#define MXC_CCM_CGR1_KPP_OFFSET 20 -#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) -#define MXC_CCM_CGR1_MLB_OFFSET 22 -#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) -#define MXC_CCM_CGR1_MSHC_OFFSET 24 -#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) -#define MXC_CCM_CGR1_OWIRE_OFFSET 26 -#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) -#define MXC_CCM_CGR1_PWM_OFFSET 28 -#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) -#define MXC_CCM_CGR1_RNGC_OFFSET 30 -#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) - -#define MXC_CCM_CGR2_RTC_OFFSET 0 -#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) -#define MXC_CCM_CGR2_RTIC_OFFSET 2 -#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) -#define MXC_CCM_CGR2_SCC_OFFSET 4 -#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) -#define MXC_CCM_CGR2_SDMA_OFFSET 6 -#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) -#define MXC_CCM_CGR2_SPBA_OFFSET 8 -#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) -#define MXC_CCM_CGR2_SPDIF_OFFSET 10 -#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) -#define MXC_CCM_CGR2_SSI1_OFFSET 12 -#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) -#define MXC_CCM_CGR2_SSI2_OFFSET 14 -#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) -#define MXC_CCM_CGR2_UART1_OFFSET 16 -#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) -#define MXC_CCM_CGR2_UART2_OFFSET 18 -#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) -#define MXC_CCM_CGR2_UART3_OFFSET 20 -#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) -#define MXC_CCM_CGR2_USBOTG_OFFSET 22 -#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) -#define MXC_CCM_CGR2_WDOG_OFFSET 24 -#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) -#define MXC_CCM_CGR2_MAX_OFFSET 26 -#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) -#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) -#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 -#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) - -#define MXC_CCM_CGR3_CSI_OFFSET 0 -#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) -#define MXC_CCM_CGR3_IIM_OFFSET 2 -#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) -#define MXC_CCM_CGR3_GPU2D_OFFSET 4 -#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) - -#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F -#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 -#define MXC_CCM_COSR_CLKOEN (1 << 5) -#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) -#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 -#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) -#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 -#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) -#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 -#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) -#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 -#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) -#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 -#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) -#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) -#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 - -#endif diff --git a/arch/arm/include/asm/arch-mx35/gpio.h b/arch/arm/include/asm/arch-mx35/gpio.h deleted file mode 100644 index b3d36394a99face654daabf1976ef8e6ffbbf784..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, - */ - - -#ifndef __ASM_ARCH_MX35_GPIO_H -#define __ASM_ARCH_MX35_GPIO_H - -#include - -#endif diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h deleted file mode 100644 index 35090047c70364b5fed41c54144ff05b1bd7384a..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2007 Pengutronix, Sascha Hauer - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX35_H -#define __ASM_ARCH_MX35_H - -#define ARCH_MXC - -/* - * IRAM - */ -#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define IRAM_SIZE 0x00020000 /* 128 KB */ - -#define LOW_LEVEL_SRAM_STACK 0x1001E000 - -/* - * AIPS 1 - */ -#define AIPS1_BASE_ADDR 0x43F00000 -#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR -#define MAX_BASE_ADDR 0x43F04000 -#define EVTMON_BASE_ADDR 0x43F08000 -#define CLKCTL_BASE_ADDR 0x43F0C000 -#define I2C1_BASE_ADDR 0x43F80000 -#define I2C3_BASE_ADDR 0x43F84000 -#define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define I2C2_BASE_ADDR 0x43F98000 -#define CSPI1_BASE_ADDR 0x43FA4000 -#define IOMUXC_BASE_ADDR 0x43FAC000 - -/* - * SPBA - */ -#define SPBA_BASE_ADDR 0x50000000 -#define UART3_BASE 0x5000C000 -#define CSPI2_BASE_ADDR 0x50010000 -#define ATA_DMA_BASE_ADDR 0x50020000 -#define FEC_BASE_ADDR 0x50038000 -#define SPBA_CTRL_BASE_ADDR 0x5003C000 - -/* - * AIPS 2 - */ -#define AIPS2_BASE_ADDR 0x53F00000 -#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR -#define CCM_BASE_ADDR 0x53F80000 -#define GPT1_BASE_ADDR 0x53F90000 -#define EPIT1_BASE_ADDR 0x53F94000 -#define EPIT2_BASE_ADDR 0x53F98000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define MMC_SDHC1_BASE_ADDR 0x53FB4000 -#define MMC_SDHC2_BASE_ADDR 0x53FB8000 -#define MMC_SDHC3_BASE_ADDR 0x53FBC000 -#define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define SDMA_BASE_ADDR 0x53FD4000 -#define RTC_BASE_ADDR 0x53FD8000 -#define WDOG1_BASE_ADDR 0x53FDC000 -#define PWM_BASE_ADDR 0x53FE0000 -#define RTIC_BASE_ADDR 0x53FEC000 -#define IIM_BASE_ADDR 0x53FF0000 -#define IMX_USB_BASE 0x53FF4000 -#define IMX_USB_PORT_OFFSET 0x400 - -#define IMX_CCM_BASE CCM_BASE_ADDR - -/* - * ROMPATCH and AVIC - */ -#define ROMPATCH_BASE_ADDR 0x60000000 -#define AVIC_BASE_ADDR 0x68000000 - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define EXT_MEM_CTRL_BASE 0xB8000000 -#define ESDCTL_BASE_ADDR 0xB8001000 -#define WEIM_BASE_ADDR 0xB8002000 -#define WEIM_CTRL_CS0 WEIM_BASE_ADDR -#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) -#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) -#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) -#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) -#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) -#define M3IF_BASE_ADDR 0xB8003000 -#define EMI_BASE_ADDR 0xB8004000 - -#define NFC_BASE_ADDR 0xBB000000 - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE_ADDR 0x70000000 -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 -#define CS0_BASE_ADDR 0xA0000000 -#define CS1_BASE_ADDR 0xA8000000 -#define CS2_BASE_ADDR 0xB0000000 -#define CS3_BASE_ADDR 0xB2000000 -#define CS4_BASE_ADDR 0xB4000000 -#define CS5_BASE_ADDR 0xB6000000 - -/* - * IRQ Controller Register Definitions. - */ -#define AVIC_NIMASK 0x04 -#define AVIC_INTTYPEH 0x18 -#define AVIC_INTTYPEL 0x1C - -/* L210 */ -#define L2CC_BASE_ADDR 0x30000000 -#define L2_CACHE_LINE_SIZE 32 -#define L2_CACHE_CTL_REG 0x100 -#define L2_CACHE_AUX_CTL_REG 0x104 -#define L2_CACHE_SYNC_REG 0x730 -#define L2_CACHE_INV_LINE_REG 0x770 -#define L2_CACHE_INV_WAY_REG 0x77C -#define L2_CACHE_CLEAN_LINE_REG 0x7B0 -#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 -#define L2_CACHE_DBG_CTL_REG 0xF40 - -#define CLKMODE_AUTO 0 -#define CLKMODE_CONSUMER 1 - -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define _PLL_BRM(x) ((x) << 31) -#define _PLL_PD(x) (((x) - 1) << 26) -#define _PLL_MFD(x) (((x) - 1) << 16) -#define _PLL_MFI(x) ((x) << 10) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - -#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) -#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) -#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) - -#define IIM_SREV 0x24 -#define ROMPATCH_REV 0x40 - -#define IPU_CONF IPU_CTRL_BASE_ADDR - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -/* - * CSPI register definitions - */ -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, - -#define GPIO_PORT_NUM 3 -#define GPIO_NUM_PIN 32 - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_2_0 0x20 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 ccmr; /* Control */ - u32 pdr0; /* Post divider 0 */ - u32 pdr1; /* Post divider 1 */ - u32 pdr2; /* Post divider 2 */ - u32 pdr3; /* Post divider 3 */ - u32 pdr4; /* Post divider 4 */ - u32 rcsr; /* CCM Status */ - u32 mpctl; /* Core PLL Control */ - u32 ppctl; /* Peripheral PLL Control */ - u32 acmr; /* Audio clock mux */ - u32 cosr; /* Clock out source */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 cgr3; /* Clock Gating Control 3 */ - u32 reserved; - u32 dcvr0; /* DPTC Comparator 0 */ - u32 dcvr1; /* DPTC Comparator 0 */ - u32 dcvr2; /* DPTC Comparator 0 */ - u32 dcvr3; /* DPTC Comparator 0 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_31[0x10]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr; - u32 fuse23_31[9]; -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -struct esdc_regs { - u32 esdctl0; - u32 esdcfg0; - u32 esdctl1; - u32 esdcfg1; - u32 esdmisc; - u32 reserved[4]; - u32 esdcdly[5]; - u32 esdcdlyl; -}; - -#define ESDC_MISC_RST (1 << 1) -#define ESDC_MISC_MDDR_EN (1 << 2) -#define ESDC_MISC_MDDR_DL_RST (1 << 3) -#define ESDC_MISC_DDR_EN (1 << 8) -#define ESDC_MISC_DDR2_EN (1 << 9) - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; - u32 pad14[63]; - u32 mgpcr5; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; - u32 pad0[6]; - u32 pacr_0_7; - u32 pacr_8_15; - u32 pacr_16_23; - u32 pacr_24_31; - u32 pad1[4]; - u32 opacr_0_7; - u32 opacr_8_15; - u32 opacr_16_23; - u32 opacr_24_31; - u32 opacr_32_39; -}; - -/* - * NFMS bit in RCSR register for pagesize of nandflash - */ -#define NFMS_BIT 8 -#define NFMS_NF_DWIDTH 14 -#define NFMS_NF_PG_SZ 8 - -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) - -#endif - -/* - * Generic timer support - */ -#ifdef CONFIG_MX35_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 -#else -#define CONFIG_SYS_TIMER_RATE 32768 -#endif - -#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) - -#endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/arch/arm/include/asm/arch-mx35/iomux-mx35.h deleted file mode 100644 index f519c69fd4812126bc1617f5e6a9378afe43bb5e..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/iomux-mx35.h +++ /dev/null @@ -1,1259 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau - * - * Based on mainline Linux i.MX iomux-mx35.h file: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH - */ - -#ifndef __IOMUX_MX35_H__ -#define __IOMUX_MX35_H__ - -#include - -/* - * The naming convention for the pad modes is MX35_PAD___ - * If or refers to a GPIO, it is named GPIO_ - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL), - - MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL), - MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL), - MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL), - - MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL), - - MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL), - MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL), - - MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL), - MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL), - MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL), - - MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL), - - MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL), - - MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL), - MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL), - MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL), - MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL), - MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL), - MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL), - MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL), - MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL), - MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL), - MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL), - MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL), - MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL), - - MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL), - MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL), - MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL), - - MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL), - - MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL), - - MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL), - - MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL), - - MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL), - MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL), - MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL), - MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL), - - MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL), - MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL), - MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL), - MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL), - MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL), - - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL), - MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL), - MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL), - MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL), - - MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL), - MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL), - MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL), - - MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL), - - MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL), - MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL), - - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL), - MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL), - - MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL), - MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL), - MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL), - MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL), - MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL), - MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL), - MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL), - MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL), - MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL), - MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL), - MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL), - MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL), - MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL), - MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL), - MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL), - MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL), - MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL), - MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL), - MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL), - MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL), - MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL), - MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL), - MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL), - MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL), - MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL), - MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL), - MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL), - MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL), - MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL), - MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL), - MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL), - MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL), - MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL), - MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL), - MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL), - MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL), - MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL), - - MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL), - - MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL), - - MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL), - MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL), - - MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX35_H__ */ diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S deleted file mode 100644 index 4b1c9f8632a40eb224fa0ce5fafc1b84a3ca93b7..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for - * SDMA to access them. - */ -.macro init_aips mpr=0x77777777, opacr=0x00000000 - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =AIPS2_BASE_ADDR - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] - - /* Did not change the AIPS control registers access type. */ - ldr r1, =\opacr - str r1, [r0, #AIPS_OPACR_0_7] - str r1, [r0, #AIPS_OPACR_8_15] - str r1, [r0, #AIPS_OPACR_16_23] - str r1, [r0, #AIPS_OPACR_24_31] - str r1, [r0, #AIPS_OPACR_32_39] - str r1, [r2, #AIPS_OPACR_0_7] - str r1, [r2, #AIPS_OPACR_8_15] - str r1, [r2, #AIPS_OPACR_16_23] - str r1, [r2, #AIPS_OPACR_24_31] - str r1, [r2, #AIPS_OPACR_32_39] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =MAX_BASE_ADDR - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ - str r1, [r0, #MAX_MGPCR5] /* for M5 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000040 - */ -.macro init_m3if ctl=0x00000040 - /* M3IF Control Register (M3IFCTL) */ - write32 M3IF_BASE_ADDR, \ctl -.endm - -.macro core_init - mrc p15, 0, r1, c1, c0, 0 - - /* Set branch prediction enable */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr p15, 0, r0, c1, c0, 1 - orr r1, r1, #1 << 11 - - /* Set unaligned access enable */ - orr r1, r1, #1 << 22 - - /* Set low int latency enable */ - orr r1, r1, #1 << 21 - - mcr p15, 0, r1, c1, c0, 0 - - mov r0, #0 - - mcr p15, 0, r0, c15, c2, 4 - - mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ - mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ - mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ - - /* Setup the Peripheral Port Memory Remap Register */ - ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ - mcr p15, 0, r0, c15, c2, 4 -.endm diff --git a/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/arch/arm/include/asm/arch-mx35/mmc_host_def.h deleted file mode 100644 index 81c19bb323cfc5b6c000d9d9294692604d18ee06..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/mmc_host_def.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h deleted file mode 100644 index 6e8b84128bc44fa5e7313de7608b44b488dda97e..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-mx35/sys_proto.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef _MX35_SYS_PROTO_H_ -#define _MX35_SYS_PROTO_H_ - -#include - -void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row, - u32 col, u32 dsize, u32 refresh); - -#endif diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 2731b7fb59b0ba7306f50d37c3233619bd7a9b38..f763749b03c48599d58147a9f614eeaa729fe6a5 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -43,7 +43,7 @@ #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) @@ -97,7 +97,7 @@ #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S index 7e61d22ca793cbd068cc7cd70845a79e84771773..4d12c6873b3412bce093029f34099ad2b2813826 100644 --- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S +++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S @@ -7,10 +7,10 @@ #ifdef CONFIG_ROM_UNIFIED_SECTIONS #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 +#define ROM_VERSION_OFFSET 0x80 #else #define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0 -#define ROM_VERSION_OFFSET 0x48 +#define ROM_VERSION_OFFSET 0x48 #endif #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4 #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4 diff --git a/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/arch/arm/include/asm/arch-mx7/mx7_plugin.S index c7a84e8caa11123bce9adfab63a7bb805a32d7ee..b552542e2818c23c228f9def8e19a8a72e818e4d 100644 --- a/arch/arm/include/asm/arch-mx7/mx7_plugin.S +++ b/arch/arm/include/asm/arch-mx7/mx7_plugin.S @@ -6,7 +6,7 @@ #include #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 +#define ROM_VERSION_OFFSET 0x80 #define ROM_API_HWCNFG_SETUP_OFFSET 0x08 plugin_start: diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S index bcc804b58fab7d2585369ff8420e0f46ca06d81f..5089b1d51772ac2bf3ae0e0f87c3019591f526d1 100644 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S +++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S @@ -6,7 +6,7 @@ #include #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 +#define ROM_VERSION_OFFSET 0x80 #define ROM_API_HWCNFG_SETUP_OFFSET 0x08 plugin_start: diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 316c67c62f9d29efe7afe7695130951bea75abc8..ed2a61218552bd88d26addf0adf3cd82712602c7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -126,17 +126,17 @@ enum { /* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2, PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), - PMU_RST_BY_FST_GLB_SRST = 0, - PMU_RST_BY_SND_GLB_SRST = 1, + PMU_RST_BY_FST_GLB_SRST = 0, + PMU_RST_BY_SND_GLB_SRST = 1, PMU_RST_DISABLE = 2, WDT_GLB_SRST_CTRL_SHIFT = 1, WDT_GLB_SRST_CTRL_MASK = BIT(1), - WDT_TRIGGER_SND_GLB_SRST = 0, - WDT_TRIGGER_FST_GLB_SRST = 1, - TSADC_GLB_SRST_CTRL_SHIFT = 0, - TSADC_GLB_SRST_CTRL_MASK = BIT(0), - TSADC_TRIGGER_SND_GLB_SRST = 0, - TSADC_TRIGGER_FST_GLB_SRST = 1, + WDT_TRIGGER_SND_GLB_SRST = 0, + WDT_TRIGGER_FST_GLB_SRST = 1, + TSADC_GLB_SRST_CTRL_SHIFT = 0, + TSADC_GLB_SRST_CTRL_MASK = BIT(0), + TSADC_TRIGGER_SND_GLB_SRST = 0, + TSADC_TRIGGER_FST_GLB_SRST = 1, }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h index 9772321023b3c757736cee439c562897e4b9f5de..e9c7f793391037bcc0d302e10b87bc2e90e71c60 100644 --- a/arch/arm/include/asm/arch-rockchip/f_rockusb.h +++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h @@ -133,4 +133,3 @@ struct f_rockusb { /* init rockusb device, tell rockusb which device you want to read/write*/ void rockusb_dev_init(char *dev_type, int dev_index); #endif /* _F_ROCKUSB_H_ */ - diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h index a1ce81ecadd046a587d2da52ed17178f8188c4fe..e795d81169c38bc5d86317a99e0600406fa66013 100644 --- a/arch/arm/include/asm/arch-stm32/stm32f.h +++ b/arch/arm/include/asm/arch-stm32/stm32f.h @@ -18,4 +18,3 @@ void stm32_flash_latency_cfg(int latency); #endif /* _ASM_ARCH_STM32F_H */ - diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h index 97d28b26f139a4fb525bdf69731f194b1acff94d..98d7cde85bc24f7829f55668aeac5f9fb409b577 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h @@ -12,4 +12,3 @@ extern int stv0991_pinmux_config(enum periph_id); extern int clock_setup(enum periph_clock); #endif - diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 8ba03e5a17f2fcbc002f9f9150e1245a655b78c7..94ab059745e88b69f41207de970a86a1ff6a8372 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -163,13 +163,13 @@ enum { VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), + VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), - VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index a2131ca07c52a62649689c7752d773f1f8adc130..439e43c2d01773dc7a210eac6376f5d17d23fd9c 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -10,11 +10,7 @@ extern void udc_disconnect(void); -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) +#ifdef CONFIG_SUPPORT_PASSING_ATAGS # define BOOTM_ENABLE_TAGS 1 #else # define BOOTM_ENABLE_TAGS 0 @@ -41,9 +37,12 @@ extern void udc_disconnect(void); struct tag_serialnr; #ifdef CONFIG_SERIAL_TAG #define BOOTM_ENABLE_SERIAL_TAG 1 -void get_board_serial(struct tag_serialnr *serialnr); #else #define BOOTM_ENABLE_SERIAL_TAG 0 +#endif +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +void get_board_serial(struct tag_serialnr *serialnr); +#else static inline void get_board_serial(struct tag_serialnr *serialnr) { } diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 32532b3ca47db07a40e25cbaf5717fdbcaa11cec..2713b1d2c55826bf3f8867ede7d633bddbf3e19d 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -267,7 +267,6 @@ #define MACH_TYPE_BMS 259 #define MACH_TYPE_IXCDP1100 260 #define MACH_TYPE_PRPMC1100 261 -#define MACH_TYPE_AT91RM9200DK 262 #define MACH_TYPE_ARMSTICK 263 #define MACH_TYPE_ARMONIE 264 #define MACH_TYPE_MPORT1 265 diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 485310d66086de326810355be02de177ccfe55fa..ec0171e0e6c9aeb1350e5df70285710971fd0113 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -154,7 +154,7 @@ lr .req x30 orr \xreg1, \xreg1, \xreg2 cbz \xreg1, \master_label #else - b \master_label + b \master_label #endif .endm @@ -256,7 +256,7 @@ lr .req x30 * For loading 64-bit OS, x0 is physical address to the FDT blob. * They will be passed to the guest. */ -.macro armv8_switch_to_el1_m, ep, flag, tmp +.macro armv8_switch_to_el1_m, ep, flag, tmp, tmp2 /* Initialize Generic Timers */ mrs \tmp, cnthctl_el2 /* Enable EL1 access to timers */ @@ -306,7 +306,14 @@ lr .req x30 b.eq 1f /* Initialize HCR_EL2 */ - ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) + /* Only disable PAuth traps if PAuth is supported */ + mrs \tmp, id_aa64isar1_el1 + ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \ + ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA) + tst \tmp, \tmp2 + mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) + orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API) + csel \tmp, \tmp2, \tmp, eq msr hcr_el2, \tmp /* Return to the EL1_SP1 mode from EL2 */ diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index 11eaa34fab8cf2ed75ba056408a58f774bbaf492..ead3f2c356438e70f69c9f7b5cdf13077ede532f 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -19,7 +19,11 @@ extern char * strchr(const char * s, int c); #endif extern void * memcpy(void *, const void *, __kernel_size_t); +#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE) +#define __HAVE_ARCH_MEMMOVE +#else #undef __HAVE_ARCH_MEMMOVE +#endif extern void * memmove(void *, const void *, __kernel_size_t); #undef __HAVE_ARCH_MEMCHR diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 8b3a54e64c82ae9ddf4141aaa8f22c034dfc16ac..f75eea16b36c51f4a632b83ee215534efb522618 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -75,10 +75,25 @@ /* * HCR_EL2 bits definitions */ +#define HCR_EL2_API (1 << 41) /* Trap pointer authentication + instructions */ +#define HCR_EL2_APK (1 << 40) /* Trap pointer authentication + key access */ #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ +/* + * ID_AA64ISAR1_EL1 bits definitions + */ +#define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic + code auth algorithm */ +#define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth + algorithm */ +#define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address + auth algorithm */ +#define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */ + /* * ID_AA64PFR0_EL1 bits definitions */ @@ -551,7 +566,6 @@ s32 psci_affinity_info(u32 function_id, u32 target_affinity, u32 psci_migrate_info_type(void); void psci_system_off(void); void psci_system_reset(void); -s32 psci_features(u32 function_id, u32 psci_fid); #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 28842c3b1552811d7fdd561ed5b82c618ca10898..ffaac6840ba774e8b55130e326d765626c7c5eeb 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -12,9 +12,9 @@ #include #include -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 #define MASK_CLE 0x10 #define MASK_ALE 0x08 diff --git a/arch/arm/include/asm/xen.h b/arch/arm/include/asm/xen.h index 8e2ee3d64eafe2eb82f9818362c8d936b317e532..670d5ad4a5b7790ac509fe3657ba014e9a1b1e34 100644 --- a/arch/arm/include/asm/xen.h +++ b/arch/arm/include/asm/xen.h @@ -4,4 +4,3 @@ */ extern unsigned long rom_pointer[]; - diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 7f663327151874e8fe93c557c1d9c095416d2f90..c48e1f622d3c890e79d953bfd26dbbe614380c3b 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -39,8 +39,13 @@ obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif +ifdef CONFIG_ARM64 +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o +else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o +endif obj-$(CONFIG_SEMIHOSTING) += semihosting.o obj-y += bdinfo.o diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 1a306ec4153b8a333fd7ce9a0061e98fc991ba74..22fd541f9a289df7c0339c07734cc9756d5fa4a3 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,7 +15,7 @@ #include #include -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ +#if defined(CONFIG_MX27) \ || defined(CONFIG_MX51) || defined(CONFIG_MX53) #include #endif @@ -35,42 +35,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */ -#if defined(CONFIG_MX25) - /* Clock Control Module */ - DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); - DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); - DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); - - /* Enhanced SDRAM Controller */ - DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); - DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); - DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); -#endif - #if defined(CONFIG_MX27) DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); @@ -97,56 +61,6 @@ int main(void) offsetof(struct system_control_regs, fmcr)); #endif -#if defined(CONFIG_MX35) - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); - DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); - DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); - DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); - DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); - DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); - DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); - DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); - DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); - DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); - DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); - DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); - DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); - DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); - DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); - DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); - DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); - DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); - DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); - DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); -#endif - #if defined(CONFIG_MX51) || defined(CONFIG_MX53) /* Round up to make sure size gives nice stack alignment */ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); diff --git a/arch/arm/lib/asmdefs.h b/arch/arm/lib/asmdefs.h new file mode 100644 index 0000000000000000000000000000000000000000..d307a3a8a25c514338b2ec5d3525745117bec73f --- /dev/null +++ b/arch/arm/lib/asmdefs.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Macros for asm code. + * + * Copyright (c) 2019, Arm Limited. + */ + +#ifndef _ASMDEFS_H +#define _ASMDEFS_H + +#if defined(__aarch64__) + +/* Branch Target Identitication support. */ +#define BTI_C hint 34 +#define BTI_J hint 36 +/* Return address signing support (pac-ret). */ +#define PACIASP hint 25; .cfi_window_save +#define AUTIASP hint 29; .cfi_window_save + +/* GNU_PROPERTY_AARCH64_* macros from elf.h. */ +#define FEATURE_1_AND 0xc0000000 +#define FEATURE_1_BTI 1 +#define FEATURE_1_PAC 2 + +/* Add a NT_GNU_PROPERTY_TYPE_0 note. */ +#define GNU_PROPERTY(type, value) \ + .section .note.gnu.property, "a"; \ + .p2align 3; \ + .word 4; \ + .word 16; \ + .word 5; \ + .asciz "GNU"; \ + .word type; \ + .word 4; \ + .word value; \ + .word 0; \ + .text + +/* If set then the GNU Property Note section will be added to + mark objects to support BTI and PAC-RET. */ +#ifndef WANT_GNU_PROPERTY +#define WANT_GNU_PROPERTY 1 +#endif + +#if WANT_GNU_PROPERTY +/* Add property note with supported features to all asm files. */ +GNU_PROPERTY (FEATURE_1_AND, FEATURE_1_BTI|FEATURE_1_PAC) +#endif + +#define ENTRY_ALIGN(name, alignment) \ + .global name; \ + .type name,%function; \ + .align alignment; \ + name: \ + .cfi_startproc; \ + BTI_C; + +#else + +#define END_FILE + +#define ENTRY_ALIGN(name, alignment) \ + .global name; \ + .type name,%function; \ + .align alignment; \ + name: \ + .cfi_startproc; + +#endif + +#define ENTRY(name) ENTRY_ALIGN(name, 6) + +#define ENTRY_ALIAS(name) \ + .global name; \ + .type name,%function; \ + name: + +#define END(name) \ + .cfi_endproc; \ + .size name, .-name; + +#define L(l) .L ## l + +#ifdef __ILP32__ + /* Sanitize padding bits of pointer arguments as per aapcs64 */ +#define PTR_ARG(n) mov w##n, w##n +#else +#define PTR_ARG(n) +#endif + +#ifdef __ILP32__ + /* Sanitize padding bits of size arguments as per aapcs64 */ +#define SIZE_ARG(n) mov w##n, w##n +#else +#define SIZE_ARG(n) +#endif + +#endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f60ee3a7e6a66aa339c5b91028f795eba27e6dbf..dd6a69315acca4b62bfa5ad976e825bc84d3e913 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -43,50 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - ulong sp, bank_end; - int bank; - - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - sp < gd->bd->bi_dram[bank].start) - continue; - /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; - if (sp > bank_end) - continue; - if (bank_end > gd->ram_top) - bank_end = gd->ram_top - 1; - - lmb_reserve(lmb, sp, bank_end - sp + 1); - break; - } -} - __weak void board_quiesce_devices(void) { } diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S index 2c584095c3c2191525fcabf67c5f2f6da743f00d..c6ea3e3afc9f51526d27ba6b9382e6a8cc71e430 100644 --- a/arch/arm/lib/ccn504.S +++ b/arch/arm/lib/ccn504.S @@ -12,7 +12,7 @@ /************************************************************************* * * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, - * CCI_MN_DVM_DOMAIN_CTL_SET); + * CCI_MN_DVM_DOMAIN_CTL_SET); * * Add fully-coherent masters to DVM domain * @@ -78,4 +78,3 @@ ENTRY(ccn504_set_aux) ret ENDPROC(ccn504_set_aux) - diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 46b6be21a8df8a3acd89568c319f8220b8f80428..956d258c9da476cd10545dac70a45cbe3df8407b 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -130,6 +130,14 @@ ENTRY(_main) ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */ adr lr, here +#if defined(CONFIG_POSITION_INDEPENDENT) + adr r0, _main + ldr r1, _start_ofs + add r0, r1 + ldr r1, =CONFIG_SYS_TEXT_BASE + sub r1, r0 + add lr, r1 +#endif ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 #if defined(CONFIG_CPU_V7M) @@ -180,3 +188,6 @@ here: #endif ENDPROC(_main) + +_start_ofs: + .word _start - _main diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S index 3ef1ce1fff5b750a1e7f543de08dcd25b2294bf9..a83e33721493ed1cb0928cc6d4fc076e73c8e18b 100644 --- a/arch/arm/lib/div64.S +++ b/arch/arm/lib/div64.S @@ -34,12 +34,12 @@ * This is meant to be used by do_div() from include/asm/div64.h only. * * Input parameters: - * xh-xl = dividend (clobbered) - * r4 = divisor (preserved) + * xh-xl = dividend (clobbered) + * r4 = divisor (preserved) * * Output values: - * yh-yl = result - * xh = remainder + * yh-yl = result + * xh = remainder * * Clobbered regs: xl, ip */ @@ -85,7 +85,7 @@ UNWIND(.fnstart) #endif @ The division loop for needed upper bit positions. - @ Break out early if dividend reaches 0. + @ Break out early if dividend reaches 0. 2: cmp xh, yl orrcs yh, yh, ip subscs xh, xh, yl diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S index 0798d098afe8c0509ec2721a901b71f3b157fe73..700eee5fbbe0c4c8db2d533ffe15a7cb7748f83b 100644 --- a/arch/arm/lib/lib1funcs.S +++ b/arch/arm/lib/lib1funcs.S @@ -34,7 +34,7 @@ mov \divisor, \divisor, lsl \result mov \curbit, \curbit, lsl \result mov \result, #0 - + #else @ Initially shift the divisor left 3 bits if possible, @@ -48,7 +48,7 @@ @ Unless the divisor is very big, shift it up in multiples of @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is + @ division loop. Continue shifting until the divisor is @ larger than the dividend. 1: cmp \divisor, #0x10000000 cmplo \divisor, \dividend @@ -135,7 +135,7 @@ @ Unless the divisor is very big, shift it up in multiples of @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is + @ division loop. Continue shifting until the divisor is @ larger than the dividend. 1: cmp \divisor, #0x10000000 cmplo \divisor, \dividend diff --git a/arch/arm/lib/memcpy-arm64.S b/arch/arm/lib/memcpy-arm64.S new file mode 100644 index 0000000000000000000000000000000000000000..507054d847eaa99cf61aa8c25c7afe5183339f87 --- /dev/null +++ b/arch/arm/lib/memcpy-arm64.S @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: MIT */ +/* + * memcpy - copy memory area + * + * Copyright (c) 2012-2020, Arm Limited. + */ + +/* Assumptions: + * + * ARMv8-a, AArch64, unaligned accesses. + * + */ + +#include "asmdefs.h" + +#define dstin x0 +#define src x1 +#define count x2 +#define dst x3 +#define srcend x4 +#define dstend x5 +#define A_l x6 +#define A_lw w6 +#define A_h x7 +#define B_l x8 +#define B_lw w8 +#define B_h x9 +#define C_l x10 +#define C_lw w10 +#define C_h x11 +#define D_l x12 +#define D_h x13 +#define E_l x14 +#define E_h x15 +#define F_l x16 +#define F_h x17 +#define G_l count +#define G_h dst +#define H_l src +#define H_h srcend +#define tmp1 x14 + +/* This implementation handles overlaps and supports both memcpy and memmove + from a single entry point. It uses unaligned accesses and branchless + sequences to keep the code small, simple and improve performance. + + Copies are split into 3 main cases: small copies of up to 32 bytes, medium + copies of up to 128 bytes, and large copies. The overhead of the overlap + check is negligible since it is only required for large copies. + + Large copies use a software pipelined loop processing 64 bytes per iteration. + The destination pointer is 16-byte aligned to minimize unaligned accesses. + The loop tail is handled by always copying 64 bytes from the end. +*/ + +ENTRY_ALIAS (memmove) +ENTRY (memcpy) + PTR_ARG (0) + PTR_ARG (1) + SIZE_ARG (2) + add srcend, src, count + add dstend, dstin, count + cmp count, 128 + b.hi L(copy_long) + cmp count, 32 + b.hi L(copy32_128) + + /* Small copies: 0..32 bytes. */ + cmp count, 16 + b.lo L(copy16) + ldp A_l, A_h, [src] + ldp D_l, D_h, [srcend, -16] + stp A_l, A_h, [dstin] + stp D_l, D_h, [dstend, -16] + ret + + /* Copy 8-15 bytes. */ +L(copy16): + tbz count, 3, L(copy8) + ldr A_l, [src] + ldr A_h, [srcend, -8] + str A_l, [dstin] + str A_h, [dstend, -8] + ret + + .p2align 3 + /* Copy 4-7 bytes. */ +L(copy8): + tbz count, 2, L(copy4) + ldr A_lw, [src] + ldr B_lw, [srcend, -4] + str A_lw, [dstin] + str B_lw, [dstend, -4] + ret + + /* Copy 0..3 bytes using a branchless sequence. */ +L(copy4): + cbz count, L(copy0) + lsr tmp1, count, 1 + ldrb A_lw, [src] + ldrb C_lw, [srcend, -1] + ldrb B_lw, [src, tmp1] + strb A_lw, [dstin] + strb B_lw, [dstin, tmp1] + strb C_lw, [dstend, -1] +L(copy0): + ret + + .p2align 4 + /* Medium copies: 33..128 bytes. */ +L(copy32_128): + ldp A_l, A_h, [src] + ldp B_l, B_h, [src, 16] + ldp C_l, C_h, [srcend, -32] + ldp D_l, D_h, [srcend, -16] + cmp count, 64 + b.hi L(copy128) + stp A_l, A_h, [dstin] + stp B_l, B_h, [dstin, 16] + stp C_l, C_h, [dstend, -32] + stp D_l, D_h, [dstend, -16] + ret + + .p2align 4 + /* Copy 65..128 bytes. */ +L(copy128): + ldp E_l, E_h, [src, 32] + ldp F_l, F_h, [src, 48] + cmp count, 96 + b.ls L(copy96) + ldp G_l, G_h, [srcend, -64] + ldp H_l, H_h, [srcend, -48] + stp G_l, G_h, [dstend, -64] + stp H_l, H_h, [dstend, -48] +L(copy96): + stp A_l, A_h, [dstin] + stp B_l, B_h, [dstin, 16] + stp E_l, E_h, [dstin, 32] + stp F_l, F_h, [dstin, 48] + stp C_l, C_h, [dstend, -32] + stp D_l, D_h, [dstend, -16] + ret + + .p2align 4 + /* Copy more than 128 bytes. */ +L(copy_long): + /* Use backwards copy if there is an overlap. */ + sub tmp1, dstin, src + cbz tmp1, L(copy0) + cmp tmp1, count + b.lo L(copy_long_backwards) + + /* Copy 16 bytes and then align dst to 16-byte alignment. */ + + ldp D_l, D_h, [src] + and tmp1, dstin, 15 + bic dst, dstin, 15 + sub src, src, tmp1 + add count, count, tmp1 /* Count is now 16 too large. */ + ldp A_l, A_h, [src, 16] + stp D_l, D_h, [dstin] + ldp B_l, B_h, [src, 32] + ldp C_l, C_h, [src, 48] + ldp D_l, D_h, [src, 64]! + subs count, count, 128 + 16 /* Test and readjust count. */ + b.ls L(copy64_from_end) + +L(loop64): + stp A_l, A_h, [dst, 16] + ldp A_l, A_h, [src, 16] + stp B_l, B_h, [dst, 32] + ldp B_l, B_h, [src, 32] + stp C_l, C_h, [dst, 48] + ldp C_l, C_h, [src, 48] + stp D_l, D_h, [dst, 64]! + ldp D_l, D_h, [src, 64]! + subs count, count, 64 + b.hi L(loop64) + + /* Write the last iteration and copy 64 bytes from the end. */ +L(copy64_from_end): + ldp E_l, E_h, [srcend, -64] + stp A_l, A_h, [dst, 16] + ldp A_l, A_h, [srcend, -48] + stp B_l, B_h, [dst, 32] + ldp B_l, B_h, [srcend, -32] + stp C_l, C_h, [dst, 48] + ldp C_l, C_h, [srcend, -16] + stp D_l, D_h, [dst, 64] + stp E_l, E_h, [dstend, -64] + stp A_l, A_h, [dstend, -48] + stp B_l, B_h, [dstend, -32] + stp C_l, C_h, [dstend, -16] + ret + + .p2align 4 + + /* Large backwards copy for overlapping copies. + Copy 16 bytes and then align dst to 16-byte alignment. */ +L(copy_long_backwards): + ldp D_l, D_h, [srcend, -16] + and tmp1, dstend, 15 + sub srcend, srcend, tmp1 + sub count, count, tmp1 + ldp A_l, A_h, [srcend, -16] + stp D_l, D_h, [dstend, -16] + ldp B_l, B_h, [srcend, -32] + ldp C_l, C_h, [srcend, -48] + ldp D_l, D_h, [srcend, -64]! + sub dstend, dstend, tmp1 + subs count, count, 128 + b.ls L(copy64_from_start) + +L(loop64_backwards): + stp A_l, A_h, [dstend, -16] + ldp A_l, A_h, [srcend, -16] + stp B_l, B_h, [dstend, -32] + ldp B_l, B_h, [srcend, -32] + stp C_l, C_h, [dstend, -48] + ldp C_l, C_h, [srcend, -48] + stp D_l, D_h, [dstend, -64]! + ldp D_l, D_h, [srcend, -64]! + subs count, count, 64 + b.hi L(loop64_backwards) + + /* Write the last iteration and copy 64 bytes from the start. */ +L(copy64_from_start): + ldp G_l, G_h, [src, 48] + stp A_l, A_h, [dstend, -16] + ldp A_l, A_h, [src, 32] + stp B_l, B_h, [dstend, -32] + ldp B_l, B_h, [src, 16] + stp C_l, C_h, [dstend, -48] + ldp C_l, C_h, [src] + stp D_l, D_h, [dstend, -64] + stp G_l, G_h, [dstin, 48] + stp A_l, A_h, [dstin, 32] + stp B_l, B_h, [dstin, 16] + stp C_l, C_h, [dstin] + ret + +END (memcpy) diff --git a/arch/arm/lib/memset-arm64.S b/arch/arm/lib/memset-arm64.S new file mode 100644 index 0000000000000000000000000000000000000000..ee9f9a96cfe6e26bc3e0e4867a48bac6764d8170 --- /dev/null +++ b/arch/arm/lib/memset-arm64.S @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: MIT */ +/* + * memset - fill memory with a constant byte + * + * Copyright (c) 2012-2021, Arm Limited. + */ + +/* Assumptions: + * + * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses. + * + */ + +#include +#include "asmdefs.h" + +#define dstin x0 +#define val x1 +#define valw w1 +#define count x2 +#define dst x3 +#define dstend x4 +#define zva_val x5 + +ENTRY (memset) + PTR_ARG (0) + SIZE_ARG (2) + + /* + * The optimized memset uses the dc opcode, which causes problems + * when the cache is disabled. Let's check if the cache is disabled + * and use a very simple memset implementation in this case. Otherwise + * jump to the optimized version. + */ + switch_el x6, 3f, 2f, 1f +3: mrs x6, sctlr_el3 + b 0f +2: mrs x6, sctlr_el2 + b 0f +1: mrs x6, sctlr_el1 +0: + tst x6, #CR_C + bne 9f + + /* + * A very "simple" memset implementation without the use of the + * dc opcode. Can be run with caches disabled. + */ + mov x3, #0x0 + cmp count, x3 /* check for zero length */ + beq 8f +4: strb valw, [dstin, x3] + add x3, x3, #0x1 + cmp count, x3 + bne 4b +8: ret +9: + + /* Here the optimized memset version starts */ + dup v0.16B, valw + add dstend, dstin, count + + cmp count, 96 + b.hi L(set_long) + cmp count, 16 + b.hs L(set_medium) + mov val, v0.D[0] + + /* Set 0..15 bytes. */ + tbz count, 3, 1f + str val, [dstin] + str val, [dstend, -8] + ret + .p2align 4 +1: tbz count, 2, 2f + str valw, [dstin] + str valw, [dstend, -4] + ret +2: cbz count, 3f + strb valw, [dstin] + tbz count, 1, 3f + strh valw, [dstend, -2] +3: ret + + /* Set 17..96 bytes. */ +L(set_medium): + str q0, [dstin] + tbnz count, 6, L(set96) + str q0, [dstend, -16] + tbz count, 5, 1f + str q0, [dstin, 16] + str q0, [dstend, -32] +1: ret + + .p2align 4 + /* Set 64..96 bytes. Write 64 bytes from the start and + 32 bytes from the end. */ +L(set96): + str q0, [dstin, 16] + stp q0, q0, [dstin, 32] + stp q0, q0, [dstend, -32] + ret + + .p2align 4 +L(set_long): + and valw, valw, 255 + bic dst, dstin, 15 + str q0, [dstin] + cmp count, 160 + ccmp valw, 0, 0, hs + b.ne L(no_zva) + +#ifndef SKIP_ZVA_CHECK + mrs zva_val, dczid_el0 + and zva_val, zva_val, 31 + cmp zva_val, 4 /* ZVA size is 64 bytes. */ + b.ne L(no_zva) +#endif + str q0, [dst, 16] + stp q0, q0, [dst, 32] + bic dst, dst, 63 + sub count, dstend, dst /* Count is now 64 too large. */ + sub count, count, 128 /* Adjust count and bias for loop. */ + + .p2align 4 +L(zva_loop): + add dst, dst, 64 + dc zva, dst + subs count, count, 64 + b.hi L(zva_loop) + stp q0, q0, [dstend, -64] + stp q0, q0, [dstend, -32] + ret + +L(no_zva): + sub count, dstend, dst /* Count is 16 too large. */ + sub dst, dst, 16 /* Dst is biased by -32. */ + sub count, count, 64 + 16 /* Adjust count and bias for loop. */ +L(no_zva_loop): + stp q0, q0, [dst, 32] + stp q0, q0, [dst, 64]! + subs count, count, 64 + b.hi L(no_zva_loop) + stp q0, q0, [dstend, -64] + stp q0, q0, [dstend, -32] + ret + +END (memset) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index e5f7267be193e09db2db3e7b32ed7a1b93c2f09b..14b7f61c1a4bb4c5b222f1be0b1252f1ab4bdd85 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -78,22 +78,28 @@ ENDPROC(relocate_vectors) */ ENTRY(relocate_code) - ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ - subs r4, r0, r1 /* r4 <- relocation offset */ - beq relocate_done /* skip relocation */ - ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ - + adr r3, relocate_code + ldr r1, _image_copy_start_ofs + add r1, r3 /* r1 <- Run &__image_copy_start */ + subs r4, r0, r1 /* r4 <- Run to copy offset */ + beq relocate_done /* skip relocation */ + ldr r1, _image_copy_start_ofs + add r1, r3 /* r1 <- Run &__image_copy_start */ + ldr r2, _image_copy_end_ofs + add r2, r3 /* r2 <- Run &__image_copy_end */ copy_loop: - ldmia r1!, {r10-r11} /* copy from source address [r1] */ - stmia r0!, {r10-r11} /* copy to target address [r0] */ - cmp r1, r2 /* until source end address [r2] */ + ldmia r1!, {r10-r11} /* copy from source address [r1] */ + stmia r0!, {r10-r11} /* copy to target address [r0] */ + cmp r1, r2 /* until source end address [r2] */ blo copy_loop /* * fix .rel.dyn relocations */ - ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */ - ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */ + ldr r1, _rel_dyn_start_ofs + add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */ + ldr r1, _rel_dyn_end_ofs + add r3, r1, r3 /* r3 <- Run &__rel_dyn_end */ fixloop: ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */ and r1, r1, #0xff @@ -129,3 +135,12 @@ relocate_done: #endif ENDPROC(relocate_code) + +_image_copy_start_ofs: + .word __image_copy_start - relocate_code +_image_copy_end_ofs: + .word __image_copy_end - relocate_code +_rel_dyn_start_ofs: + .word __rel_dyn_start - relocate_code +_rel_dyn_end_ofs: + .word __rel_dyn_end - relocate_code diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index b03e1cfc80c9eabaf3712fce3ddaad693cd81fcf..656084c7e519486bc606db7f29781aab2554580d 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -12,6 +12,7 @@ */ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -33,3 +34,16 @@ int arch_reserve_stacks(void) return 0; } + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 16384); +} diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c90505e5edcb6000363a854fd2753dbf510cbcc7..4448ca1592e21c08511695bf22094fae6b6e53c7 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -298,7 +298,6 @@ endchoice config ATMEL_SFR bool - default n config SYS_SOC default "at91" diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index de99c616ac836581c7b3cdb59da5173ead1dce6d..5e3cce03b7e724355adbd3ff93cb32ffaebf2495 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -10,7 +10,7 @@ #include -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #include #include @@ -148,4 +148,4 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index f5b26659578dd2e857c6915225fea43220b4bae5..246050b67bb106657dcb871be410523ea73a3360 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -11,7 +11,9 @@ obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o clock.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o obj-y += cpu.o -obj-y += reset.o +ifndef CONFIG_$(SPL_TPL_)SYSRESET +obj-y += reset.o +endif ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y) # old non-DM timer driver diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index 9e9d026c3e064e46a36a1bd70abd9c653dd15459..edc20574c31bb03b3e699f6bd533fbb341970e19 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -46,6 +46,8 @@ char *get_cpu_name(void) return "SAMA5D28-CU"; case ARCH_EXID_SAMA5D28CN: return "SAMA5D28-CN"; + case ARCH_EXID_SAMA5D29CN: + return "SAMA5D29-CN"; } } diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c index a58f671f72d979291f2e142e300bb9cb4f68ec83..0b702c7fb76d5451de38f1e1dccd36e6a1858180 100644 --- a/arch/arm/mach-at91/armv7/sama7g5_devices.c +++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c @@ -8,4 +8,3 @@ char *get_cpu_name(void) { return "SAMA7G5"; } - diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index b14222460f3acd74f888774fdcaceaafd5ed6b9b..62108d2bd0a5db43ae42ab539170041efb8d99b8 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -39,4 +39,3 @@ void configure_ddrcfg_input_buffers(bool open) else writel(0, &sfr->ddrcfg); } - diff --git a/arch/arm/mach-at91/include/mach/at91_mc.h b/arch/arm/mach-at91/include/mach/at91_mc.h index 18b0e163c099b135ffc12b8ea1091e572850165e..7cf6cdf3102228e045e251d3ff2c09bc63d9fca3 100644 --- a/arch/arm/mach-at91/include/mach/at91_mc.h +++ b/arch/arm/mach-at91/include/mach/at91_mc.h @@ -16,7 +16,7 @@ #ifndef __ASSEMBLY__ typedef struct at91_ebi { - u32 csa; /* 0x00 Chip Select Assignment Register */ + u32 csa; /* 0x00 Chip Select Assignment Register */ u32 cfgr; /* 0x04 Configuration Register */ u32 reserved[2]; } at91_ebi_t; @@ -28,20 +28,20 @@ typedef struct at91_ebi { #define AT91_EBI_CSA_CS4A 0x0010 typedef struct at91_sdramc { - u32 mr; /* 0x00 SDRAMC Mode Register */ - u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ - u32 cr; /* 0x08 SDRAMC Configuration Register */ - u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ - u32 lpr; /* 0x10 SDRAMC Low Power Register */ - u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ - u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ - u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ - u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ + u32 mr; /* 0x00 SDRAMC Mode Register */ + u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ + u32 cr; /* 0x08 SDRAMC Configuration Register */ + u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ + u32 lpr; /* 0x10 SDRAMC Low Power Register */ + u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ + u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ + u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ + u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ u32 reserved[3]; } at91_sdramc_t; typedef struct at91_smc { - u32 csr[8]; /* 0x00 SDRAMC Mode Register */ + u32 csr[8]; /* 0x00 SDRAMC Mode Register */ } at91_smc_t; #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) @@ -60,7 +60,7 @@ typedef struct at91_smc { #define AT91_SMC_CSR_NWS(x) (x & 0x7F) typedef struct at91_bfc { - u32 mr; /* 0x00 SDRAMC Mode Register */ + u32 mr; /* 0x00 SDRAMC Mode Register */ } at91_bfc_t; typedef struct at91_mc { diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h index ec4658a391775de529b75ff2fbbd84b2e6dcb2b4..f91cec98c935239340c1694e24eb5b1a719f6dbf 100644 --- a/arch/arm/mach-at91/include/mach/at91_st.h +++ b/arch/arm/mach-at91/include/mach/at91_st.h @@ -24,6 +24,6 @@ typedef struct at91_st { #define AT91_ST_WDMR_WDV(x) (x & 0xFFFF) #define AT91_ST_WDMR_RSTEN 0x00010000 -#define AT91_ST_WDMR_EXTEN 0x00020000 +#define AT91_ST_WDMR_EXTEN 0x00020000 #endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index d1b2e01cdd0dccd6abdb0fd91a8da08d10b5920a..9d9462725cde4bd6bcb0fa7f34613257fb86a2a5 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -215,6 +215,7 @@ #define ARCH_EXID_SAMA5D27CN 0x00000021 #define ARCH_EXID_SAMA5D28CU 0x00000010 #define ARCH_EXID_SAMA5D28CN 0x00000020 +#define ARCH_EXID_SAMA5D29CN 0x00000023 #define ARCH_ID_SAMA5D2_SIP 0x8a5c08c2 #define ARCH_EXID_SAMA5D225C_D1M 0x00000053 diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index d0c732539248c066254e9ef30fc58b6284fdeaaf..ea19ec322e81cadadd7f3de98d17381972c4076f 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -136,7 +136,7 @@ void board_init_f(ulong dummy) at91_periph_clk_enable(ATMEL_ID_PIOC); #endif -#if defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_SERIAL) /* init console */ at91_seriald_hw_init(); preloader_console_init(); diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index 345f7fe2b77f0c9f1723514b25fd7f6158ccb1fc..01a8ed2a7b1f84f275303bc182be59200abe85de 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -202,4 +202,3 @@ int bcm2711_notify_vl805_reset(void) return 0; } - diff --git a/arch/arm/mach-davinci/include/mach/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h index 215706e1729669af6e9545eb4229836bf6be037e..99d403cef7ecadd08b3194c94a06b8774345cab2 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx-usb.h +++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h @@ -29,22 +29,22 @@ struct da8xx_usb_regs { dv_reg revision; dv_reg control; - dv_reg status; - dv_reg emulation; - dv_reg mode; - dv_reg autoreq; - dv_reg srpfixtime; - dv_reg teardown; - dv_reg intsrc; - dv_reg intsrc_set; - dv_reg intsrc_clr; - dv_reg intmsk; - dv_reg intmsk_set; - dv_reg intmsk_clr; - dv_reg intsrcmsk; - dv_reg eoi; - dv_reg intvector; - dv_reg grndis_size[4]; + dv_reg status; + dv_reg emulation; + dv_reg mode; + dv_reg autoreq; + dv_reg srpfixtime; + dv_reg teardown; + dv_reg intsrc; + dv_reg intsrc_set; + dv_reg intsrc_clr; + dv_reg intmsk; + dv_reg intmsk_set; + dv_reg intmsk_clr; + dv_reg intsrcmsk; + dv_reg eoi; + dv_reg intvector; + dv_reg grndis_size[4]; }; #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) @@ -68,13 +68,13 @@ struct da8xx_usb_regs { #define CFGCHIP2_OTGMODE (3 << 13) #define CFGCHIP2_NO_OVERRIDE (0 << 13) #define CFGCHIP2_FORCE_HOST (1 << 13) -#define CFGCHIP2_FORCE_DEVICE (2 << 13) +#define CFGCHIP2_FORCE_DEVICE (2 << 13) #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) #define CFGCHIP2_PHYPWRDN (1 << 10) #define CFGCHIP2_OTGPWRDN (1 << 9) -#define CFGCHIP2_DATPOL (1 << 8) +#define CFGCHIP2_DATPOL (1 << 8) #define CFGCHIP2_USB1SUSPENDM (1 << 7) #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 48b11f7a5c82bb3881cb127627669640df9d3ae2..1133a23bdee321b9db8802da1b9b5e391e6ae016 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -23,7 +23,7 @@ struct pinmux_config { /* pin table definition */ struct pinmux_resource { const struct pinmux_config *pins; - const int n_pins; + const int n_pins; }; #define PINMUX_ITEM(item) { \ @@ -35,7 +35,6 @@ struct lpsc_resource { const int lpsc_no; }; -int dvevm_read_mac_address(uint8_t *buf); void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 90b38b7e020eb4a4e5c3d3e239d6f617704bde15..73fdd1f243292246da66064766fa8bc2a75ce5d9 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -41,33 +41,6 @@ int dram_init_banksize(void) #endif #ifdef CONFIG_DRIVER_TI_EMAC -/* - * Read ethernet MAC address from EEPROM for DVEVM compatible boards. - * Returns 1 if found, 0 otherwise. - */ -int dvevm_read_mac_address(uint8_t *buf) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) - goto i2cerr; - - /* Check that MAC address is valid. */ - if (!is_valid_ethaddr(buf)) - goto err; - - return 1; /* Found */ - -i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", - CONFIG_SYS_I2C_EEPROM_ADDR); -err: -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ - - return 0; -} - /* * Set the mii mode as MII or RMII */ diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index d0d7a814713abc23036b4baaceb52e503ea410af..54aff78894a58b390bbc710fb0bc16d2597feb71 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -51,7 +51,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NAND; #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case DAVINCI_SD_OR_MMC_BOOT: case DAVINCI_MMC_ONLY_BOOT: return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 0b4276c0362858885713da30773309163a708530..7df0e176179d37b5b85e125dbb776112f17b5c86 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -141,7 +141,7 @@ if ARCH_EXYNOS7 choice prompt "EXYNOS7 board select" -config TARGET_ESPRESSO7420 +config TARGET_ESPRESSO7420 bool "ESPRESSO7420 board" select ARM64 select ARMV8_MULTIENTRY diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 97d6ca8fc2a09b94418dd05d62e05ba4886639b5..2645a8ff492491e381fdf9fdcb204f8efe6546cb 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -218,7 +218,7 @@ int do_lowlevel_init(void) if (actions & DO_CLOCKS) { system_clock_init(); #ifdef CONFIG_DEBUG_UART -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ !defined(CONFIG_SPL_BUILD) exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); debug_uart_init(); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 653463ab461fdf804d24e86e4b27f5d3da45029d..dd4f027f36d042ba4fc8bba2b4471a26bd8ab238 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,8 +1,13 @@ +config MACH_IMX + bool + config HAS_CAAM bool config IMX_CONFIG - string + string "DCD script to use" + depends on MACH_IMX + default "arch/arm/mach-imx/spl_sd.cfg" config ROM_UNIFIED_SECTIONS bool diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0ef269563da2b109094a8312581ebd47deb84500..63e28c635e3655c8eaef973d6a46bbbbb596818d 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) -obj-y += cpu.o +obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o @@ -43,7 +43,7 @@ ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) -obj-y += cache.o init.o +obj-y += cache.o init.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o ifneq ($(CONFIG_SPL_BUILD),y) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 68b30bcfc592d0dc11676c6c1e67cfd203500fdc..0e76786482214797221a458b961ba10684e42d32 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -73,7 +73,7 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, return -ENOMEM; } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC if (dev_type == MMC_DEV) { unsigned long count = 0; struct mmc *mmc = (struct mmc *)dev; @@ -213,7 +213,7 @@ unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash) } #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) { diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 02db322f51af4006922b330ffa6790999cb5c13e..ee5cc479039bc523bc292cb871c9bedd09d476cf 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -172,7 +172,7 @@ enum boot_device get_boot_device(void) return boot_dev; } -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define FUSE_UNIQUE_ID_WORD0 16 #define FUSE_UNIQUE_ID_WORD1 17 void get_board_serial(struct tag_serialnr *serialnr) @@ -201,7 +201,7 @@ void get_board_serial(struct tag_serialnr *serialnr) serialnr->low = val1; serialnr->high = val2; } -#endif /*CONFIG_SERIAL_TAG*/ +#endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/ #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 1c33acc7dd6e4a864095d169b478c6db795f0c59..bba6323f96fa163cdb8193f791edd4a1ccc92a54 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -405,7 +405,7 @@ int dram_init(void) return 0; } -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG void get_board_serial(struct tag_serialnr *serialnr) { u32 uid[4]; diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index d82efa7f8f0a34da5b5e4e0266e791549cf01698..09a758ff6e893286ae388b2450fc0a0529e0d962 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -77,33 +77,3 @@ int mxs_reset_block(struct mxs_register_32 *reg) return 0; } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void board_lmb_reserve(struct lmb *lmb) -{ - ulong sp, bank_end; - int bank; - - sp = get_sp(); - debug("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 16K to be safe */ - sp -= 4096 << 2; - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (sp < gd->bd->bi_dram[bank].start) - continue; - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size; - if (sp >= bank_end) - continue; - lmb_reserve(lmb, sp, bank_end - sp); - break; - } -} diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig deleted file mode 100644 index fad5dcc940aa6cc63e14f52d2960624ec58128a0..0000000000000000000000000000000000000000 --- a/arch/arm/mach-imx/mx2/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if ARCH_MX25 - -config MX25 - bool - default y - select SYS_FSL_ERRATUM_ESDHC_A001 -choice - prompt "MX25 board select" - optional - -config TARGET_ZMX25 - bool "Support zmx25" - select BOARD_LATE_INIT - select CPU_ARM926EJS - -endchoice - -config SYS_SOC - default "mx25" - -source "board/syteco/zmx25/Kconfig" - -endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 515c3020faa1b80b6a42ae088efa212a269a5d7d..ee73006ae810a06a6de045b0c30061dc558abbb8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -102,7 +102,6 @@ config MX6_OCRAM_256KB config MX6_DDRCAL bool "Include dynamic DDR calibration routines" depends on SPL - default n help Say "Y" if your board uses dynamic (per-boot) DDR calibration. If unsure, say N. @@ -305,12 +304,12 @@ config TARGET_MX6DL_MAMOJ select SPL_LIBCOMMON_SUPPORT if SPL select SPL_LIBDISK_SUPPORT if SPL select SPL_LIBGENERIC_SUPPORT if SPL - select SPL_MMC_SUPPORT if SPL + select SPL_MMC if SPL select SPL_OF_CONTROL if SPL select SPL_OF_LIBFDT if SPL select SPL_PINCTRL if SPL select SPL_SEPARATE_BSS if SPL - select SPL_SERIAL_SUPPORT if SPL + select SPL_SERIAL if SPL select SPL_USB_GADGET if SPL select SPL_USB_HOST if SPL select SPL_USB_SDP_SUPPORT if SPL diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index adedc011648ffa0658856d1c1c020835ac3c949f..059e65879c5cccefd714545aa063deef35248efb 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -91,6 +91,7 @@ config TARGET_COLIBRI_IMX7 select DM select DM_SERIAL select DM_THERMAL + select MX7D imply CMD_DM endchoice diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index fda25ba66a365f6c858ea771a8d8322d4a72645d..21690072e15d3225a4b9b92dcccbc37347c94cbc 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -224,7 +225,7 @@ const struct rproc_att hostmap[] = { }; #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) /* enable all periherial can be accessed in nosec mode */ static void init_csu(void) { @@ -337,10 +338,19 @@ int arch_cpu_init(void) int arch_misc_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + struct tag_serialnr serialnr; + char serial_string[0x20]; + if (is_mx7d()) env_set("soc", "imx7d"); else env_set("soc", "imx7s"); + + /* Set serial# standard environment variable based on OTP settings */ + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "0x%08x%08x", + serialnr.low, serialnr.high); + env_set("serial#", serial_string); #endif #ifdef CONFIG_FSL_CAAM @@ -351,7 +361,7 @@ int arch_misc_init(void) } #endif -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* * OCOTP_TESTER * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 @@ -435,4 +445,3 @@ void reset_misc(void) #endif #endif } - diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 9f48ffda414a80be81d768de5494347fd357ec00..b2026a3758a5d921849550e982e3437e3f47ed8d 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -39,9 +39,6 @@ choice prompt "MX28 board select" optional -config TARGET_BG0900 - bool "Support bg0900" - config TARGET_MX28EVK bool "Support mx28evk" select BOARD_EARLY_INIT_F @@ -56,6 +53,5 @@ config SYS_SOC source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" -source "board/ppcag/bg0900/Kconfig" endif diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 36033d611c9f0c0dd7b3ca40e828055a40256ca3..c2845241d9dcb50571d02ded72ba1373b31107fb 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -199,7 +199,7 @@ int g_dnl_get_board_bcd_device_number(int gcnum) } #endif -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ u32 spl_mmc_boot_mode(const u32 boot_device) { diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 6dfed365d295b2d69075bb2ea54e1bd126505ccf..7c02e199a38c69c8009559c9beebaa8a1766904a 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index fa8d134b42f09522111017819d36e8ee1ae9e881..526f5f8b76c2c221a34f2a5ba7b8f76994b46c3f 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -168,4 +168,5 @@ config K3_DM_FW source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/j721e/Kconfig" +source "board/siemens/iot2050/Kconfig" endif diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index d213e06afbb1c345ba7c3efec7960b27e41675c2..9ce576186c75f37b00a99d5aa5d49b5e7811a90e 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -370,7 +370,7 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, /* Load combined System Controller firmware and config data image */ switch (bootdev.boot_device) { -#if CONFIG_IS_ENABLED(MMC_SUPPORT) +#if CONFIG_IS_ENABLED(MMC) case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index e06eba5aea1fb25c27528559326f1514855ef607..94e6fe1f228527850daa14898105cf969aa87f4c 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -6,6 +6,7 @@ choice config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" + select SOC_K2HK select SPL_BOARD_INIT if SPL select CMD_DDR3 imply DM_I2C @@ -14,6 +15,7 @@ config TARGET_K2HK_EVM config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" + select SOC_K2E select SPL_BOARD_INIT if SPL select CMD_DDR3 imply DM_I2C @@ -22,6 +24,7 @@ config TARGET_K2E_EVM config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" + select SOC_K2L select SPL_BOARD_INIT if SPL select CMD_DDR3 imply DM_I2C @@ -31,6 +34,7 @@ config TARGET_K2L_EVM config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" select BOARD_LATE_INIT + select SOC_K2G select SPL_BOARD_INIT if SPL select TI_I2C_BOARD_DETECT select CMD_DDR3 @@ -40,6 +44,18 @@ config TARGET_K2G_EVM endchoice +config SOC_K2E + bool + +config SOC_K2G + bool + +config SOC_K2HK + bool + +config SOC_K2L + bool + config SYS_SOC default "keystone" diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 0c5dc6a7395196d910eec9e99b4e96bf848bfdaa..98a8f058df4a3eb7e2b3c65e502d1f7bd0160cef 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -148,8 +148,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 #define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) -#define KS2_UART0_BASE 0x02530c00 -#define KS2_UART1_BASE 0x02531000 +#define KS2_UART0_BASE 0x02530c00 +#define KS2_UART1_BASE 0x02531000 /* Boot Config */ #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 @@ -210,7 +210,7 @@ typedef volatile unsigned int *dv_reg_p; #endif /* AEMIF */ -#define KS2_AEMIF_CNTRL_BASE 0x21000a00 +#define KS2_AEMIF_CNTRL_BASE 0x21000a00 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE /* Flag from ks2_debug options to check if DSPs need to stay ON */ diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 3953aa9b9b519e8442e093978813ca47a5b307b7..e9571298a8245718625351cfc956cfce1243991c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -278,4 +278,3 @@ int cpu_eth_init(struct bd_info *bis) return 0; } #endif - diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index a4b5630c46f624fce7a17bb03f9101b126904dce..9002e26d75f240b2fc6a6d307689f28995c9758e 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -91,18 +91,6 @@ #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE #endif /* CONFIG_IDE */ -/* - * I2C related stuff - */ -#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI -#endif -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - /* Use common timer */ #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index e067604d9b394a711498cb18314d79eef168620c..f79a5c62cd3a89324dd35acdc69119c4c1c7c581 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -8,7 +8,6 @@ config SYS_VENDOR config MT8512 bool "MediaTek MT8512 SoC" - default n choice prompt "MediaTek board select" @@ -80,12 +79,40 @@ config TARGET_MT8518 endchoice -source "board/mediatek/mt7622/Kconfig" -source "board/mediatek/mt7623/Kconfig" -source "board/mediatek/mt7629/Kconfig" -source "board/mediatek/mt8183/Kconfig" -source "board/mediatek/mt8512/Kconfig" -source "board/mediatek/mt8516/Kconfig" -source "board/mediatek/mt8518/Kconfig" +config SYS_BOARD + string "Board name" + default "mt7622" if TARGET_MT7622 + default "mt7623" if TARGET_MT7623 + default "mt7629" if TARGET_MT7629 + default "mt8183" if TARGET_MT8183 + default "mt8512" if TARGET_MT8512 + default "mt8516" if TARGET_MT8516 + default "mt8518" if TARGET_MT8518 + default "" + help + This option contains information about board name. + Based on this option board// will + be used. + +config SYS_CONFIG_NAME + string "Board configuration name" + default "mt7622" if TARGET_MT7622 + default "mt7623" if TARGET_MT7623 + default "mt7629" if TARGET_MT7629 + default "mt8183" if TARGET_MT8183 + default "mt8512" if TARGET_MT8512 + default "mt8516" if TARGET_MT8516 + default "mt8518" if TARGET_MT8518 + default "" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. + +config MTK_BROM_HEADER_INFO + string + default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 + default "lk=1" if TARGET_MT7623 endif diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index 927175c5a319822834ee26c80dc2ec79364f73e0..d3cda94617e1a7925d7cad17224d2330d429da88 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -31,9 +31,9 @@ void board_init_f(ulong dummy) u32 spl_boot_device(void) { -#if defined(CONFIG_SPL_SPI_SUPPORT) +#if defined(CONFIG_SPL_SPI) return BOOT_DEVICE_SPI; -#elif defined(CONFIG_SPL_MMC_SUPPORT) +#elif defined(CONFIG_SPL_MMC) return BOOT_DEVICE_MMC1; #elif defined(CONFIG_SPL_NAND_SUPPORT) return BOOT_DEVICE_NAND; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 89737a37ad9e2db419ca27a8ac940233b5c0219a..087643725e85261eeccf4799ab0b19baf409a4b8 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -2,7 +2,6 @@ if ARCH_MVEBU config HAVE_MVEBU_EFUSE bool - default n config ARMADA_32BIT bool @@ -184,6 +183,33 @@ config TARGET_CRS3XX_98DX3236 endchoice +choice + prompt "DDR bus width" + default DDR_64BIT + depends on ARMADA_XP + +config DDR_64BIT + bool "64bit bus width" + +config DDR_32BIT + bool "32bit bus width" + +endchoice + +config DDR_LOG_LEVEL + int "DDR training code log level" + depends on ARMADA_XP + default 0 + range 0 3 + help + Amount of information provided on error while running the DDR + training code. At level 0, provides an error code in a case of + failure, RL, WL errors and other algorithm failure. At level 1, + provides the D-Unit setup (SPD/Static configuration). At level 2, + provides the windows margin as a results of DQS centeralization. + At level 3, rovides the windows margin of each DQ as a results of + DQS centeralization. + config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "helios4" if TARGET_HELIOS4 @@ -256,7 +282,7 @@ config MVEBU_SPL_BOOT_DEVICE_SPI imply SPL_DM_SPI imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI_LOAD - imply SPL_SPI_SUPPORT + imply SPL_SPI select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_MMC @@ -267,12 +293,12 @@ config MVEBU_SPL_BOOT_DEVICE_MMC imply SPL_DM_MMC imply SPL_GPIO imply SPL_LIBDISK_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_SATA bool "SATA" - imply SPL_SATA_SUPPORT + imply SPL_SATA imply SPL_LIBDISK_SUPPORT select SPL_BOOTROM_SUPPORT @@ -284,14 +310,12 @@ endchoice config MVEBU_EFUSE bool "Enable eFuse support" - default n depends on HAVE_MVEBU_EFUSE help Enable support for reading and writing eFuses on mvebu SoCs. config MVEBU_EFUSE_FAKE bool "Fake eFuse access (dry run)" - default n depends on MVEBU_EFUSE help This enables a "dry run" mode where eFuses are not really programmed. diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 02a5b880152e304a3ab584bb24dfee00ca87c2f7..6ecd394a533d56266e208e4a5e7f84929e35d81b 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -27,10 +27,6 @@ #define CONFIG_SYS_L2_PL310 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#endif - /* * By default the generated mvebu kwbimage.cfg is used * If for some board, different configuration file need to be used, @@ -63,8 +59,6 @@ #ifndef CONFIG_SYS_I2C_SOFT #define CONFIG_I2C_MVTWSI #endif -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 #endif /* Use common timer */ diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 3b41c7d49b729a23d75785a6e535136b4dcdbae8..bb7d24b4b7ba586bcd7420085d85c1fc3ce0fa10 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -14,8 +14,6 @@ #include "sys_env_lib.h" #include "ctrl_pex.h" - - /* * serdes_seq_db - holds all serdes sequences, their size and the * relevant index in the data array initialized in serdes_seq_init diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 8d6d4902f69cef866b5faf244953f6b12b67971f..b798c797cc2737b407e031d0cabcf64e07ab80d5 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -17,7 +17,8 @@ #include #include -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC_SUPPORT) || defined(CONFIG_SPL_SATA_SUPPORT) +#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \ + defined(CONFIG_SPL_SATA) /* * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must @@ -39,7 +40,7 @@ * and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET need to point to the * kwbimage main header. */ -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported #endif @@ -56,7 +57,7 @@ * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper. */ -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA #if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1 #error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1 #endif @@ -92,7 +93,7 @@ struct kwbimage_main_hdr_v1 { uint8_t checksum; /* 0x1F */ } __packed; -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC u32 spl_mmc_boot_mode(const u32 boot_device) { return MMCSD_MODE_RAW; @@ -121,10 +122,10 @@ int spl_parse_board_header(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT mhdr->blockid != IBR_HDR_SPI_ID && #endif -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA mhdr->blockid != IBR_HDR_SATA_ID && #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC mhdr->blockid != IBR_HDR_SDIO_ID && #endif 1 @@ -135,7 +136,7 @@ int spl_parse_board_header(struct spl_image_info *spl_image, spl_image->offset = mhdr->srcaddr; -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA /* * For SATA srcaddr is specified in number of sectors. * The main header is must be stored at sector number 1. @@ -152,7 +153,7 @@ int spl_parse_board_header(struct spl_image_info *spl_image, } #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC /* * For SDIO (eMMC) srcaddr is specified in number of sectors. * This expects that sector size is 512 bytes and recalculates @@ -193,11 +194,11 @@ u32 spl_boot_device(void) * If SPL is compiled with chosen boot_device support * then use SPL driver for loading U-Boot proper. */ -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case BOOT_DEVICE_MMC1: return BOOT_DEVICE_MMC1; #endif -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA case BOOT_FROM_SATA: return BOOT_FROM_SATA; #endif diff --git a/arch/arm/mach-octeontx/Makefile b/arch/arm/mach-octeontx/Makefile index 20cb48ad92549ea2c4ea05d3db698c2ac5d5d3d9..8706becd0f30419299f770e4b0770b753f2f46f7 100644 --- a/arch/arm/mach-octeontx/Makefile +++ b/arch/arm/mach-octeontx/Makefile @@ -6,4 +6,3 @@ # */ obj-y += lowlevel_init.o clock.o cpu.o - diff --git a/arch/arm/mach-octeontx2/Makefile b/arch/arm/mach-octeontx2/Makefile index c3192343dd29301e5ffc51513a147bf66b836cfa..b3073a84b149b0712d6e01e6b233c3a3b20a18d8 100644 --- a/arch/arm/mach-octeontx2/Makefile +++ b/arch/arm/mach-octeontx2/Makefile @@ -6,4 +6,3 @@ # */ obj-y += lowlevel_init.o clock.o cpu.o - diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 08639653b795258ca9e3e9796aba9b271fea89c0..263142683b04757dc32c517a9ac174bd41f204c0 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -20,11 +20,11 @@ config OMAP34XX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_OMAP3_ID_NAND imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD imply TWL4030_POWER @@ -42,11 +42,11 @@ config OMAP44XX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SIMPLE imply SPL_NAND_SUPPORT imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD @@ -66,12 +66,12 @@ config OMAP54XX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_AM33XX_BCH imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SYS_I2C_OMAP24XX config TI814X @@ -120,6 +120,7 @@ config AM33XX select SPECIFY_CONSOLE_INDEX imply NAND_OMAP_ELM imply NAND_OMAP_GPMC + imply SKIP_LOWLEVEL_INIT imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SYS_I2C_OMAP24XX diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 4268419b166b6b95155ba89e1514c40875f292e0..1402376915eaf50f801d46d58020c1f828baa52e 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -46,12 +46,12 @@ config TARGET_AM335X_EVM imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_OF_LIBFDT imply SPL_POWER imply SPL_SEPARATE_BSS - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_SYS_MALLOC_SIMPLE imply SPL_WATCHDOG imply SPL_YMODEM_SUPPORT @@ -230,10 +230,10 @@ config TARGET_AM43XX_EVM imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_WATCHDOG imply SPL_YMODEM_SUPPORT help diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 61c76d045f3d2c0e81d4478694bc30aa51aecd42..4e4f98ea90378d4f2e8cf8ef499abc43f57d85f8 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -13,7 +13,7 @@ endif obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif obj-$(CONFIG_TI816X) += ti816x_emif4.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index d390f2e1f3e8dff2ec16e25e06b63a89ac8983dd..c44667668e9de5eca7672148be20bd67b5f54f47 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) sdram_init(); #endif @@ -351,7 +351,7 @@ int arch_misc_init(void) #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) @@ -599,7 +599,7 @@ void board_init_f(ulong dummy) int arch_cpu_init_dm(void) { hw_data_init(); -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) early_system_init(); #endif return 0; diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index 15b6b35ae7c1795fbb65b7b95b9d9000e167e1d4..459bac13e05815ad121f8f8fc718ca11ee01f760 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -22,7 +22,7 @@ #include #include -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; @@ -182,4 +182,4 @@ void sdram_init(void) &ddr3_chilisom_emif_reg_data, 0); } -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 7cdf7f158981ff8865ddb47cd7898894f4da910a..fdb8b479ea014b3d172481c94045c29c9c97fcaa 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -203,7 +203,7 @@ void spl_board_init(void) gpmc_init(); #endif #if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C) - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW) arch_misc_init(); diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 14b638a65136c5a5a6e92508bb737edf616a7917..1d8eab2dab506dee3bbe58b4d74e806e1b3d43cd 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -552,7 +552,7 @@ void scale_vcores(struct vcores_data const *vcores) if (pv->value[opp]) { /* Handle non-empty members only */ pv->value[opp] = optimize_vcore_voltage(pv, opp); - px = (struct volts *)vcores; + px = (struct volts *)vcores; j = 0; while (px < pv) { /* @@ -918,8 +918,8 @@ void gpi2c_init(void) static int gpi2c = 1; if (gpi2c) { - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE); gpi2c = 0; } } diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 363af528450b1876447d1c92eeb1445f01daf392..8b70251457e2248d7e5bb131e2ef6b18c98b166c 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -76,8 +76,8 @@ void early_system_init(void) hw_data_init(); } -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /****************************************************************************** * Routine: secure_unlock diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S index 4fa89418a11f8da6078036761331d552c5786f27..ab7cdcf3d42e8089a75025928f1b39316666172f 100644 --- a/arch/arm/mach-omap2/omap3/lowlevel_init.S +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -170,8 +170,8 @@ pll_div_val5: go_to_speed_end: #endif -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) ENTRY(lowlevel_init) ldr sp, SRAM_STACK str ip, [sp] /* stash ip register */ diff --git a/arch/arm/mach-omap2/omap5/prcm-regs.c b/arch/arm/mach-omap2/omap5/prcm-regs.c index b5baebc06926512088c34a48b434d7e8e436b59e..28c4f4f7374937ac50f29b781ee7afeab9520af4 100644 --- a/arch/arm/mach-omap2/omap5/prcm-regs.c +++ b/arch/arm/mach-omap2/omap5/prcm-regs.c @@ -300,7 +300,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_std_fuse_die_id_1 = 0x4A002208, .control_std_fuse_die_id_2 = 0x4A00220C, .control_std_fuse_die_id_3 = 0x4A002210, - .control_phy_power_usb = 0x4A002370, + .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, diff --git a/arch/arm/mach-omap2/pipe3-phy.c b/arch/arm/mach-omap2/pipe3-phy.c index 35ec81d31468ac6b4eb053c58ba7299ed67d23dd..3dfb184c43088592472a161a5af37e337d519a9d 100644 --- a/arch/arm/mach-omap2/pipe3-phy.c +++ b/arch/arm/mach-omap2/pipe3-phy.c @@ -229,4 +229,3 @@ int phy_pipe3_power_off(struct omap_pipe3 *phy) return 0; } - diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 606153e407c7d6c3251f65dd9abe11345e707b8f..a8b87f6d7103f97eba218fb01fa6c19ae7d9fba2 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -11,7 +11,7 @@ obj-y = cpu.o obj-y += dram.o obj-y += timer.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index 0adf3dcc64830734da86d92e7239d771843345f4..d7ea2e3943fc4a581324f0b3db11478625682aee 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -69,7 +69,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs = #define TVR_ARM_TIMER_OFFS 0 #define TVR_ARM_TIMER_MASK 0xffffffff #define TVR_ARM_TIMER_MAX 0xffffffff -#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff static inline ulong read_timer(void) { diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 69e40cf38273bcf939bfaa295673a97b885c03a2..0e9c0fa99622738ac3f84675482f74f9cbf49d39 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -29,7 +29,7 @@ config RCAR_GEN3 imply SPL_GZIP imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_SYS_MALLOC_SIMPLE imply SPL_TINY_MEMSET imply SPL_YMODEM_SUPPORT diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index d5e437f0d2e2b4e67df9f6f9282c29a5b75d1ce8..ea98bb00f3ba6673f98428836ad137cf997c47e4 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -133,7 +133,6 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT - default n choice prompt "Qos setting primary" diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index a6dcce180b4d5c5a5a5b3050eafe7cc0e047de53..98549742e76bb6dc1429982a6a92feebfc4d7aab 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -4,61 +4,73 @@ menu "Select Target SoC" config R8A774A1 bool "Renesas SoC R8A774A1" + select GICV2 imply CLK_R8A774A1 imply PINCTRL_PFC_R8A774A1 config R8A774B1 bool "Renesas SoC R8A774B1" + select GICV2 imply CLK_R8A774B1 imply PINCTRL_PFC_R8A774B1 config R8A774C0 bool "Renesas SoC R8A774C0" + select GICV2 imply CLK_R8A774C0 imply PINCTRL_PFC_R8A774C0 config R8A774E1 bool "Renesas SoC R8A774E1" + select GICV2 imply CLK_R8A774E1 imply PINCTRL_PFC_R8A774E1 config R8A7795 bool "Renesas SoC R8A7795" + select GICV2 imply CLK_R8A7795 imply PINCTRL_PFC_R8A7795 config R8A7796 bool "Renesas SoC R8A7796" + select GICV2 imply CLK_R8A7796 imply PINCTRL_PFC_R8A7796 config R8A77965 bool "Renesas SoC R8A77965" + select GICV2 imply CLK_R8A77965 imply PINCTRL_PFC_R8A77965 config R8A77970 bool "Renesas SoC R8A77970" + select GICV2 imply CLK_R8A77970 imply PINCTRL_PFC_R8A77970 config R8A77980 bool "Renesas SoC R8A77980" + select GICV2 imply CLK_R8A77980 imply PINCTRL_PFC_R8A77980 config R8A77990 bool "Renesas SoC R8A77990" + select GICV2 imply CLK_R8A77990 imply PINCTRL_PFC_R8A77990 config R8A77995 bool "Renesas SoC R8A77995" + select GICV2 imply CLK_R8A77995 imply PINCTRL_PFC_R8A77995 config R8A779A0 bool "Renesas SoC R8A779A0" + select GICV3 imply CLK_R8A779A0 imply PINCTRL_PFC_R8A779A0 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index f3fbf77b0aea6a53ea61831c5fdb8b598ed7398d..ef74d59fed445de19a82c322d84de94119a4abea 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -10,10 +10,6 @@ #include "rcar-base.h" -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 - /* Module stop control/status register bits */ #define MSTP0_BITS 0x00640801 #define MSTP1_BITS 0xDB6E9BDF diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index fec9f7bf5d5e9ccfe10b99ec32ffda689be01ef0..681d1ea524b3d441c3af65d44ba79e38da5c1611 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -13,9 +13,6 @@ * R-Car (R8A7791) I/O Addresses */ -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 - /* SDHI */ #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h index 8acd7ba750bd54e3e86b56ceba4a48719ff68f8d..06db64af6cfcad40393708164af78184cac15f0f 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -10,10 +10,6 @@ #include "rcar-base.h" -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 - /* Module stop control/status register bits */ #define MSTP0_BITS 0x00400801 #define MSTP1_BITS 0x9B6F987F diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 278c7768d9385e8bccd1521980b30ad958a6c299..31433c369300c48851f2c8254caf3e3412bd0bd0 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -14,9 +14,6 @@ * R8A7793 I/O Addresses */ -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 - /* SDHI */ #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 73259c7ec184e111032b64fcc482bc2c2b928535..3baa4237c262a99d5131860b45133bbbcf41f306 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -10,9 +10,6 @@ #include "rcar-base.h" -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 - /* Module stop control/status register bits */ #define MSTP0_BITS 0x00440801 #define MSTP1_BITS 0x936899DA diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h index a20740679fdb1907092747e46c94628b8679f3b0..4c98dffa073c180a65087b6cd3468c8a686c5215 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -70,14 +70,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* - * SH-I2C - * Ch2 and ch3 are different address. These are defined - * in the header of each SoCs. - */ -#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 - /* RCAR-I2C */ #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index 5cd8a8c787faf1e963e9bcb189c8664192e8d485..ca1274272d34ff07d09f58cdb8895b973e980efe 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -74,9 +74,6 @@ #define PUEN_USB1_OVC (1 << 2) #define PUEN_USB1_PWEN (1 << 1) -/* IICDVFS (I2C) */ -#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 - #ifndef __ASSEMBLY__ #include #include diff --git a/arch/arm/mach-rmobile/pfc-r8a7790.h b/arch/arm/mach-rmobile/pfc-r8a7790.h index e911be4039dcd7f1684e434beb7301ca8f47e777..3b36548aec95101c9780281c1829e8c20a6ff5f9 100644 --- a/arch/arm/mach-rmobile/pfc-r8a7790.h +++ b/arch/arm/mach-rmobile/pfc-r8a7790.h @@ -82,7 +82,7 @@ PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) #define CPU_32_PORT0_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx, sfx), \ PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \ PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \ PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b164afb5290861dea7c1dec930eb516b6de0a6d3..da6871eb182b65de5e61131aacd2162b427ce90b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,8 +11,8 @@ config ROCKCHIP_PX30 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL select TPL_NEEDS_SEPARATE_STACK if TPL imply SPL_SEPARATE_BSS - select SPL_SERIAL_SUPPORT - select TPL_SERIAL_SUPPORT + select SPL_SERIAL + select TPL_SERIAL select DEBUG_UART_BOARD_INIT imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD @@ -84,9 +84,9 @@ config ROCKCHIP_RK322X select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_DRIVERS_MISC imply ROCKCHIP_COMMON_BOARD - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD select TPL_LIBCOMMON_SUPPORT select TPL_LIBGENERIC_SUPPORT @@ -100,6 +100,7 @@ config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A select OF_BOARD_SETUP + select SKIP_LOWLEVEL_INIT_ONLY select SUPPORT_SPL select SPL select SUPPORT_TPL @@ -118,7 +119,7 @@ config ROCKCHIP_RK3288 imply TPL_RAM imply TPL_REGMAP imply TPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_SYSCON imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB @@ -145,8 +146,8 @@ config ROCKCHIP_RK3308 imply SPL_REGMAP imply SPL_SYSCON imply SPL_RAM - imply SPL_SERIAL_SUPPORT - imply TPL_SERIAL_SUPPORT + imply SPL_SERIAL + imply TPL_SERIAL imply SPL_SEPARATE_BSS help The Rockchip RK3308 is a ARM-based Soc which embedded with quad @@ -164,8 +165,8 @@ config ROCKCHIP_RK3328 imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD - imply SPL_SERIAL_SUPPORT - imply TPL_SERIAL_SUPPORT + imply SPL_SERIAL + imply TPL_SERIAL imply SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT @@ -187,8 +188,8 @@ config ROCKCHIP_RK3368 imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS - imply SPL_SERIAL_SUPPORT - imply TPL_SERIAL_SUPPORT + imply SPL_SERIAL + imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised @@ -218,7 +219,7 @@ config ROCKCHIP_RK3399 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_DRIVERS_MISC select CLK select FIT @@ -234,7 +235,7 @@ config ROCKCHIP_RK3399 imply ROCKCHIP_SDRAM_COMMON imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE @@ -381,7 +382,7 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM This enables support code in the BOOT0 hook for the TPL stage to allow multiple entries. -config SPL_MMC_SUPPORT +config SPL_MMC default y if !SPL_ROCKCHIP_BACK_TO_BROM config ROCKCHIP_SPI_IMAGE diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index 085e65062011c8a0646698a4b76b42ec3cabb4e0..637a5e1b18b8118ad55c46d94e46074e4853926f 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 16090f5b08be2448fed0db8cd30e5bfa664e36c0..aa5cc471eed00f3c41c0f9f58f12453e3354bfc3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -36,7 +36,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_LDSCRIPT diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 51cd43b396fae3c98c48e53ed8d5a73bcd4eeaeb..b746795d813f0087080744550cf5ea2272a1a472 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -22,7 +22,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y source "board/rockchip/evb_rk3036/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index e24e68ea518ab087f72618da84ef3c82537d9bd1..9a76490998ddea16cc3b537ec70586a6f1efa45b 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -24,7 +24,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_LIBCOMMON_SUPPORT diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index ad8c6cd1d7940e6de0a5bcc4f9ef44875e8e98b3..5a02914e1b0dcd23f95c50da1886cc1abafed6d9 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define GRF_BASE 0x20008000 @@ -107,7 +108,6 @@ int rk_board_late_init(void) } #ifdef CONFIG_SPL_BUILD -DECLARE_GLOBAL_DATA_PTR; static int setup_led(void) { #ifdef CONFIG_SPL_LED @@ -115,7 +115,7 @@ static int setup_led(void) char *led_name; int ret; - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + led_name = ofnode_conf_read_str("u-boot,boot-led"); if (!led_name) return 0; ret = led_get_by_label(led_name, &dev); diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 2fc6f6ea3ec9ebc6f2d49e32d19821fda00e415f..6458cd55814a7d88f05654c70e3720a39871de8f 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -20,7 +20,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_MAX_SIZE diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index a5db59ae5973eb920c261a5d70475920a6c09750..f37b1bdfd50a645be62e970c542c66f7485c5c06 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -163,7 +163,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_LDSCRIPT diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index b9fdfe2e950d8951bad28f313fdf8b4917d15c95..8fa536e15dceba755d1837eda5fcf288b927fc7f 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -14,7 +14,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config ROCKCHIP_BOOT_MODE_REG diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile index 3bddc104a74ffb3cab3c76634f1f76ed787f3eee..5910f20bff773f2abca12ba4c993b520be4c8c3e 100644 --- a/arch/arm/mach-rockchip/rk3368/Makefile +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -3,4 +3,4 @@ # Copyright (c) 2016 Andreas Färber obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += syscon_rk3368.o +obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index b360ca7ddef004ce27a2e92044471bc19162f9fc..2b5746cb31bba2e0b6ec8932de4d2e11481fe615 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -21,7 +21,7 @@ static const struct udevice_id rk3399_syscon_ids[] = { U_BOOT_DRIVER(syscon_rk3399) = { .name = "rk3399_syscon", .id = UCLASS_SYSCON, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .of_match = rk3399_syscon_ids, diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c index 20adfd11690fc68bb45c07b776d5bc6c50628c9d..5407e7827f5234fa999106199ea9dc91ca5e3a06 100644 --- a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c @@ -18,7 +18,7 @@ U_BOOT_DRIVER(syscon_rk3568) = { .name = "rk3568_syscon", .id = UCLASS_SYSCON, .of_match = rk3568_syscon_ids, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif }; diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index cc908e1b0e818e8faf88c9219afc6b9e56638e20..3c007bb450893ff78c80174911e39887d42e33fc 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -16,6 +16,10 @@ #include #include +#if CONFIG_IS_ENABLED(BANNER_PRINT) +#include +#endif + #define TIMER_LOAD_COUNT_L 0x00 #define TIMER_LOAD_COUNT_H 0x04 #define TIMER_CONTROL_REG 0x10 @@ -48,7 +52,7 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; -#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT) +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL) /* * Debug UART can be used from here if required: * diff --git a/arch/arm/mach-s5pc1xx/include/mach/sromc.h b/arch/arm/mach-s5pc1xx/include/mach/sromc.h index 45de4a799d308a5641dd87f55fa9739dd22aae75..a8eb2a38b0f5ec0e632d1c1f1915caec4a6a6da5 100644 --- a/arch/arm/mach-s5pc1xx/include/mach/sromc.h +++ b/arch/arm/mach-s5pc1xx/include/mach/sromc.h @@ -4,9 +4,9 @@ * Naveen Krishna Ch * * Note: This file contains the register description for Memory subsystem - * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. * - * Only SROMC is defined as of now + * Only SROMC is defined as of now */ #ifndef __ASM_ARCH_SROMC_H_ diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c index 2a161be137cc3c157cc69bb7f2d344bcdfa2360f..499dfdf0da6edad409c3cd54c65b623675e4c763 100644 --- a/arch/arm/mach-snapdragon/dram.c +++ b/arch/arm/mach-snapdragon/dram.c @@ -97,4 +97,3 @@ int msm_fixup_memory(void *blob) return 0; } - diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c index 985625a548e78ed4916e544bc2b551503f32c5ef..7d452f4529b79c161e58af4eeafa7d2d651d65d5 100644 --- a/arch/arm/mach-snapdragon/misc.c +++ b/arch/arm/mach-snapdragon/misc.c @@ -9,6 +9,7 @@ #include #include #include +#include /* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */ #define UNSTUFF_BITS(resp, start, size) \ @@ -33,21 +34,22 @@ u32 msm_board_serial(void) if (!mmc_dev) return 0; + if (mmc_init(mmc_dev)) + return 0; + return UNSTUFF_BITS(mmc_dev->cid, 16, 32); } void msm_generate_mac_addr(u8 *mac) { - int i; - char sn[9]; - - snprintf(sn, 9, "%08x", msm_board_serial()); - - /* fill in the mac with serialno, use locally adminstrated pool */ + /* use locally adminstrated pool */ mac[0] = 0x02; - mac[1] = 00; - for (i = 3; i >= 0; i--) { - mac[i + 2] = hextoul(&sn[2 * i], NULL); - sn[2 * i] = 0; - } + mac[1] = 0x00; + + /* + * Put the 32-bit serial number in the last 32-bit of the MAC address. + * Use big endian order so it is consistent with the serial number + * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd + */ + put_unaligned_be32(msm_board_serial(), &mac[2]); } diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h index 048708202cc718799333f86d1d0385210a686a5c..7ab951700710044dab33814edea7d215f1c83add 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -14,8 +14,8 @@ #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) -#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) -#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) @@ -26,9 +26,9 @@ #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) -#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) -#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) -#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ @@ -50,9 +50,9 @@ #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) -#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) -#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) -#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index b5f43f09d190d735f01e29299b1c9f0ccc0aa65b..ecb656e4de71191e7c29278b0c489ee59fa0a262 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -93,7 +93,7 @@ u32 spl_boot_device(void) } } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC u32 spl_mmc_boot_mode(const u32 boot_device) { #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 7c716117685c32bd6c595c9f996eace46e3a32a9..441d893333c7df236b169df1215a9f3f2fb3d4ea 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -52,7 +52,7 @@ u32 spl_boot_device(void) } } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC u32 spl_mmc_boot_mode(const u32 boot_device) { #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index cb98ab39e4234841dfa60d00de78324a19af6ec7..ba6efc1d86418bc09581a8515a36207059043f51 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -14,7 +14,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; } -#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT) +#if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 2f1e7d3a155ee7783c7c8f129ccc777ae35dd582..a439dbd10f182601bfc7f2d4f6db494469b04853 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -41,7 +41,7 @@ config STM32F7 select SPL_OF_TRANSLATE select SPL_PINCTRL select SPL_RAM - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_SYS_MALLOC_SIMPLE select SPL_TIMER select SPL_XIP_SUPPORT diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 5d7eca649a87313e605fa3546f0cb4b93f35bba4..69d56c23e11287bbae86c97ac864883a80193be9 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -15,14 +15,14 @@ config SPL select SPL_PINCTRL select SPL_REGMAP select SPL_DM_RESET - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_SYSCON select SPL_WATCHDOG if WATCHDOG imply BOOTSTAGE_STASH if SPL_BOOTSTAGE imply SPL_BOOTSTAGE if BOOTSTAGE imply SPL_DISPLAY_PRINT imply SPL_LIBDISK_SUPPORT - imply SPL_SPI_LOAD if SPL_SPI_SUPPORT + imply SPL_SPI_LOAD if SPL_SPI config SYS_SOC default "stm32mp" @@ -190,7 +190,6 @@ config STM32_ECDSA_VERIFY config CMD_STM32KEY bool "command stm32key to fuse public key hash" - default n help fuse public key hash in corresponding fuse used to authenticate binary. diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 49f94f095c184e87f00c52b8047c1bb3d96f0ac7..1d4a4fdd0c5963cfc8feaa79db8a01f4744e9c56 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -209,6 +209,8 @@ config MACH_SUN4I select DRAM_SUN4I select SUNXI_GEN_SUN4I select SUPPORT_SPL + imply SPL_SYS_I2C_LEGACY + imply SYS_I2C_LEGACY config MACH_SUN5I bool "sun5i (Allwinner A13)" @@ -219,6 +221,8 @@ config MACH_SUN5I select SUNXI_GEN_SUN4I select SUPPORT_SPL imply CONS_INDEX_2 if !DM_SERIAL + imply SPL_SYS_I2C_LEGACY + imply SYS_I2C_LEGACY config MACH_SUN6I bool "sun6i (Allwinner A31)" @@ -245,6 +249,8 @@ config MACH_SUN7I select SUNXI_GEN_SUN4I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + imply SPL_SYS_I2C_LEGACY + imply SYS_I2C_LEGACY config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" @@ -303,6 +309,7 @@ config MACH_SUN8I_R40 select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT select PHY_SUN4I_USB + imply SPL_SYS_I2C_LEGACY config MACH_SUN8I_V3S bool "sun8i (Allwinner V3/V3s/S3/S3L)" @@ -622,7 +629,6 @@ config SYS_SOC config UART0_PORT_F bool "UART0 on MicroSD breakout board" - default n ---help--- Repurpose the SD card slot for getting access to the UART0 serial console. Primarily useful only for low level u-boot debugging on @@ -633,7 +639,6 @@ config UART0_PORT_F config OLD_SUNXI_KERNEL_COMPAT bool "Enable workarounds for booting old kernels" - default n ---help--- Set this to enable various workarounds for old kernels, this results in sub-optimal settings for newer kernels, only enable if needed. @@ -764,14 +769,12 @@ config I2C0_ENABLE config I2C1_ENABLE bool "Enable I2C/TWI controller 1" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. config I2C2_ENABLE bool "Enable I2C/TWI controller 2" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -779,7 +782,6 @@ config I2C2_ENABLE if MACH_SUN6I || MACH_SUN7I config I2C3_ENABLE bool "Enable I2C/TWI controller 3" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -798,7 +800,6 @@ endif if MACH_SUN7I config I2C4_ENABLE bool "Enable I2C/TWI controller 4" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -806,7 +807,6 @@ endif config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" - default n ---help--- Say Y here to enable support for the gpio pins of the axp PMIC ICs. @@ -838,14 +838,12 @@ config VIDEO_HDMI config VIDEO_VGA bool "VGA output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) - default n ---help--- Say Y here to add support for outputting video over VGA. config VIDEO_VGA_VIA_LCD bool "VGA via LCD controller support" depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) - default n ---help--- Say Y here to add support for external DACs connected to the parallel LCD interface driving a VGA connector, such as found on the @@ -854,7 +852,6 @@ config VIDEO_VGA_VIA_LCD config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH bool "Force sync active high for VGA via LCD controller support" depends on VIDEO_VGA_VIA_LCD - default n ---help--- Say Y here if you've a board which uses opendrain drivers for the vga hsync and vsync signals. Opendrain drivers cannot generate steep enough @@ -872,7 +869,6 @@ config VIDEO_VGA_EXTERNAL_DAC_EN config VIDEO_COMPOSITE bool "Composite video output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) - default n ---help--- Say Y here to add support for outputting composite video. @@ -936,7 +932,6 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI - default n select CMD_I2C ---help--- Say y here if the LCD panel needs to be configured via i2c. This @@ -969,7 +964,6 @@ config VIDEO_LCD_IF_LVDS config SUNXI_DE2 bool - default n config VIDEO_DE2 bool "Display Engine 2 video driver" diff --git a/arch/arm/mach-sunxi/dram_sun4i.c b/arch/arm/mach-sunxi/dram_sun4i.c index 76d698214da4ba198084c1ed0d4a29f83c05f6c9..80a6c4bc0fd1763c868e808816f39a28626d4844 100644 --- a/arch/arm/mach-sunxi/dram_sun4i.c +++ b/arch/arm/mach-sunxi/dram_sun4i.c @@ -279,7 +279,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); - } else { + } else { /* any other frequency that is a multiple of 24 */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index d99a38b10aa634cfe60c10cc195dfb4413c21409..367b74061ed52aa2982dfc32d82142b5adf5bccb 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -126,8 +126,8 @@ static void auto_set_timing_para(struct dram_para *para) u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ /* Set work mode register */ mctl_set_cr(para); diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index 611eaa3024c4e5dfc2c0a6a1d90a6796814f8b81..2136ca3a4cb0107221ac074819001ee99e1fea35 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -30,7 +30,7 @@ * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2, * write levelling disabled, TDQS disabled, output buffer enabled * MR2: manual full array self refresh, dynamic ODT off, - * CAS write latency (CWL): 8 + * CAS write latency (CWL): 8 */ static u32 mr_ddr3[7] = { 0x00001c70, 0x00000040, 0x00000018, 0x00000000, diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 478c7a9e388a26397935eb0181ea1e66ec57090a..957e3ce64a5e9d4aa7ba5c348447db86b51cb1ac 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -9,7 +9,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TEGRA_CLKRST @@ -72,6 +72,7 @@ config TEGRA_ARMV7_COMMON select CPU_V7A select SPL select SPL_BOARD_INIT if SPL + select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL select SUPPORT_SPL select TEGRA_CLKRST select TEGRA_COMMON @@ -124,6 +125,7 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" + select GICV2 select TEGRA_ARMV8_COMMON select TEGRA_CLKRST select TEGRA_GPIO @@ -137,6 +139,7 @@ config TEGRA210 config TEGRA186 bool "Tegra186 family" select DM_MAILBOX + select GICV2 select TEGRA186_BPMP select TEGRA186_CLOCK select TEGRA186_GPIO diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 869db285a4e9688a0819f867e26fc487fdb53ee9..4ba3fb23fd63b64ba61b51dd32ad58cb6f8ea559 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -12,4 +12,3 @@ #include #include #include - diff --git a/arch/arm/mach-u8500/Kconfig b/arch/arm/mach-u8500/Kconfig index db7a29a54c25a3c76c9b46c34040104026a096e8..b067a719e775fbb771e0733b5f0bbc4ff5b40409 100644 --- a/arch/arm/mach-u8500/Kconfig +++ b/arch/arm/mach-u8500/Kconfig @@ -13,14 +13,15 @@ config TARGET_STEMMY The Samsung "stemmy" board supports Samsung smartphones released with the ST-Ericsson NovaThor U8500 SoC, e.g. - - Samsung Galaxy S III mini (GT-I8190) "golden" + - Samsung Galaxy Ace 2 (GT-I8160) "codina" + - Samsung Galaxy Amp (SGH-I407) "kyle" + - Samsung Galaxy Beam (GT-I8530) "gavini" + - Samsung Galaxy Exhibit (SGH-T599) "codina" (TMO) - Samsung Galaxy S Advance (GT-I9070) "janice" + - Samsung Galaxy S III mini (GT-I8190) "golden" - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" - - Samsung Galaxy Ace 2 (GT-I8160) "codina" - - and likely others as well (untested). - See board/ste/stemmy/README for details. + See doc/board/ste/stemmy.rst for details. endchoice diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index d333b7091d4bca0574b54ca96e6509be3e1c7608..5172efac0c4221295ded025d7f794af5ee5225d2 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -6,7 +6,7 @@ obj-y += boards.o obj-y += spl_board_init.o obj-y += memconf.o obj-y += bcu/ -obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc-boot-mode.o +obj-$(CONFIG_SPL_MMC) += mmc-boot-mode.o else diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index ebd2da3887ecf81f48a359e9faa677dc78c4eff4..0c6ad345ffdaedce7037e2fa079f5c2a1ff6fb66 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -21,9 +21,6 @@ config SYS_CONFIG_NAME Based on this option include/configs/.h header will be used for board configuration. -config GICV3 - def_bool y - config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c index a0babce7baad78842dce352ac4e09a7351772079..739cb2997ad70ea9e9458e1c656411e880116a61 100644 --- a/arch/arm/mach-versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c @@ -60,4 +60,3 @@ int timer_init (void) return 0; } - diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index e54310383b2965016202203adeff0b0ebb5834f2..cf2e727916ba3752155972c32230d01ab4e0a84a 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -15,16 +15,16 @@ config SPL_LIBDISK_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_MMC_SUPPORT +config SPL_MMC default y if MMC_SDHCI_ZYNQ -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config SPL_SPI_FLASH_SUPPORT default y if ZYNQ_QSPI -config SPL_SPI_SUPPORT +config SPL_SPI default y if ZYNQ_QSPI config ZYNQ_DDRC_INIT diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index d09141c3bc7ef959bbeb6477004da8845dd3158f..b1a5184b689859729997a3c6be141ed2b525c482 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -45,7 +45,7 @@ u32 spl_boot_device(void) u32 mode; switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI case ZYNQ_BM_QSPI: mode = BOOT_DEVICE_SPI; break; @@ -56,7 +56,7 @@ u32 spl_boot_device(void) case ZYNQ_BM_NOR: mode = BOOT_DEVICE_NOR; break; -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case ZYNQ_BM_SD: mode = BOOT_DEVICE_MMC1; break; diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 39144d654e3aa0fc6515750614709f0f7eb1e6a2..f7b08db35501144fa2ff76e35f6dd9e8b2dfddce 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -12,16 +12,16 @@ config SPL_LIBDISK_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_MMC_SUPPORT +config SPL_MMC default y if MMC_SDHCI_ZYNQ -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config SPL_SPI_FLASH_SUPPORT default y if ZYNQ_QSPI -config SPL_SPI_SUPPORT +config SPL_SPI default y if ZYNQ_QSPI config SYS_BOARD diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 8fcae2c6a6661cdb61c191a0bb5808c2f61ee5e7..6b836cbff2d75ae440f57b1c66b5eb1f1c1fc6fe 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -88,7 +88,7 @@ u32 spl_boot_device(void) switch (bootmode) { case JTAG_MODE: return BOOT_DEVICE_RAM; -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ return BOOT_DEVICE_MMC2; @@ -100,11 +100,11 @@ u32 spl_boot_device(void) case USB_MODE: return BOOT_DEVICE_DFU; #endif -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA case SW_SATA_MODE: return BOOT_DEVICE_SATA; #endif -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: return BOOT_DEVICE_SPI; diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index 86c93ba3faffb4640034cb2405a7d04ca7521803..632f1b1f38cca466c25b0485e29e4254c68c452f 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -6,7 +6,6 @@ #include #include -#include "version.h" #include #define _START _start @@ -38,10 +37,10 @@ _vectors: #if defined(CONFIG_CF_SBF) INITSP: .long 0 /* Initial SP */ -INITPC: .long ASM_DRAMINIT /* Initial PC */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ #else INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITPC: .long _START /* Initial PC */ #endif vector02_0F: @@ -489,7 +488,4 @@ _int_handler: /******************************************************************************/ -.globl version_string -version_string: -.ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index 8d3ab6f3fb25a57eaee390e78f038fad791e59cf..e44656db5f23f3ac79baa99561ebbcbbb9af536d 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -106,7 +106,7 @@ int watchdog_init(void) #if defined(CONFIG_MCFFEC) /* Default initializations for MCFFEC controllers. To override, * create a board-specific function called: - * int board_eth_init(struct bd_info *bis) + * int board_eth_init(struct bd_info *bis) */ int cpu_eth_init(struct bd_info *bis) diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 8c5a16495523057970b590837b4412e473c8ce66..4c9c96d7831e4e88a4237a38f1b7cdf0fda91b62 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -6,7 +6,6 @@ #include #include -#include "version.h" #include #define _START _start @@ -253,7 +252,4 @@ _int_handler: /******************************************************************************/ -.globl version_string -version_string: -.ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 0676e39141059f66236e7d4c76b93b4fceacc9fa..8f72ef567feb6cc66c905b24ff5a4ae94df91b3e 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -421,7 +421,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #if defined(CONFIG_MCFFEC) /* Default initializations for MCFFEC controllers. To override, * create a board-specific function called: - * int board_eth_init(struct bd_info *bis) + * int board_eth_init(struct bd_info *bis) */ int cpu_eth_init(struct bd_info *bis) diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 747a518f6cd5bd9a0c38abb161c63e1b1aef78ef..d3cdc4217617649900dbd7a9d25aee3839c41571 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -6,7 +6,6 @@ #include #include -#include "version.h" #include #define _START _start @@ -335,7 +334,4 @@ _int_handler: /******************************************************************************/ -.globl version_string -version_string: -.ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile index b34cb3c78c9a3146b1799950f047e65f52e44c44..6bd7cd3591dcf0bbc9c1b8e42bb1d0bc7956f9a0 100644 --- a/arch/m68k/cpu/mcf530x/Makefile +++ b/arch/m68k/cpu/mcf530x/Makefile @@ -4,4 +4,3 @@ extra-y = start.o obj-y = interrupts.o cpu.o speed.o cpu_init.o - diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 32356d875ec13a4fe67b00f9fb522dc28b21583b..0daff5d0c4cf0f6ee78c11e4e122a5f7a3d64818 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -6,7 +6,6 @@ #include #include -#include "version.h" #include #define _START _start @@ -258,9 +257,4 @@ _int_handler: /******************************************************************************/ -.globl version_string -version_string: -.ascii U_BOOT_VERSION -.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" -.ascii CONFIG_IDENT_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index d37dd3defb73ca4c752f99fbde1786c83c7f26e4..1dadffd4ca3633e7fa7e88231734e18dde242861 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -148,7 +148,7 @@ int watchdog_init(void) #if defined(CONFIG_MCFFEC) /* Default initializations for MCFFEC controllers. To override, * create a board-specific function called: - * int board_eth_init(struct bd_info *bis) + * int board_eth_init(struct bd_info *bis) */ int cpu_eth_init(struct bd_info *bis) { diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index e2d7c72ceec612cbf22560237dc253556f8ab81f..26728919160e83174e5e73a01e4b6d9fe126459a 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -9,7 +9,6 @@ #include #include -#include "version.h" #include #define _START _start @@ -268,7 +267,4 @@ _int_handler: /******************************************************************************/ -.globl version_string -version_string: -.ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c index ac1e591681612bb7b32d6abc686d55b59eeca4fa..d9a71c6b920d849384245aea00a8d7fa1534e3e3 100644 --- a/arch/m68k/cpu/mcf5445x/cpu.c +++ b/arch/m68k/cpu/mcf5445x/cpu.c @@ -110,7 +110,7 @@ int print_cpuinfo(void) #if defined(CONFIG_MCFFEC) /* Default initializations for MCFFEC controllers. To override, * create a board-specific function called: - * int board_eth_init(struct bd_info *bis) + * int board_eth_init(struct bd_info *bis) */ int cpu_eth_init(struct bd_info *bis) diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 7007d78c83faafd5fc9f87e581036587bef6636a..27bcd40c5c1ec1024ec82fe2b759f178977fd920 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -10,8 +10,6 @@ #include #include #include -#include -#include "version.h" #include #define _START _start @@ -46,16 +44,16 @@ _vectors: INITSP: .long 0 /* Initial SP */ #ifdef CONFIG_CF_SBF -INITPC: .long ASM_DRAMINIT /* Initial PC */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ #endif #ifdef CONFIG_SYS_NAND_BOOT -INITPC: .long ASM_DRAMINIT_N /* Initial PC */ +INITPC: .long ASM_DRAMINIT_N /* Initial PC */ #endif #else INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITPC: .long _START /* Initial PC */ #endif @@ -610,7 +608,4 @@ _int_handler: /******************************************************************************/ -.globl version_string -version_string: -.ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds index 64cf2ff5ef97367a9fa043a5fd02631f576e868f..affb2d93746492d2bf624f43f38e471c1961b2e1 100644 --- a/arch/m68k/cpu/u-boot.lds +++ b/arch/m68k/cpu/u-boot.lds @@ -9,6 +9,7 @@ #include OUTPUT_ARCH(m68k) +ENTRY(_start) #ifndef LDS_BOARD_TEXT #define LDS_BOARD_TEXT diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index e041e7e0afbd48c685f6b09de4554e30ccddccdf..930e0899e8ca55369bfdda11773c87d7218f7631 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -114,4 +114,3 @@ typedef struct gpio { } gpio_t; #endif /* __IMMAP_5307__ */ - diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index dce0d26a0f9ac661221f4a713cbd45730295e89a..7ebeddbb683b0f7fa4ed5a5d22cb77219421e198 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -115,7 +115,7 @@ #define MCF_GPIO_PAR_TIMER 0x10004C #define MCF_DSCR_EIM 0x100050 -#define MCF_DCSR_FEC12C 0x100052 +#define MCF_DCSR_FEC12C 0x100052 #define MCF_DCSR_UART 0x100053 #define MCF_DCSR_QSPI 0x100054 #define MCF_DCSR_TIMER 0x100055 diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h index f96e6ca29d1539169ff379afb1c0f4ec1bd570e9..67547d2dd9d9cb148fcf2117b9792fd165d60ddf 100644 --- a/arch/m68k/include/asm/m5307.h +++ b/arch/m68k/include/asm/m5307.h @@ -66,4 +66,3 @@ #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ #endif /* mcf5307_h */ - diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 51a6f938586dddb54632e1a1f6bbe54ad27803b6..27729db67e27ab9acb4c126fbf9679678fe48d45 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -32,23 +32,7 @@ static void set_clocks_in_mhz (struct bd_info *kbd); void arch_lmb_reserve(struct lmb *lmb) { - ulong sp; - - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug ("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 1K to be safe */ - sp -= 1024; - lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024); } int do_bootm_linux(int flag, int argc, char *const argv[], diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c index 23ef4b732af82d4495ed98fdd4a31ab795fed5ec..c42ca1d753e53adf7a9a935c4a6264c3a1433e51 100644 --- a/arch/m68k/lib/muldi3.c +++ b/arch/m68k/lib/muldi3.c @@ -41,7 +41,7 @@ umul_ppmm (__w.s.high, __w.s.low, u, v); \ __w.ll; }) -typedef int SItype __attribute__ ((mode (SI))); +typedef int SItype __attribute__ ((mode (SI))); typedef unsigned int USItype __attribute__ ((mode (SI))); typedef int DItype __attribute__ ((mode (DI))); typedef int word_type __attribute__ ((mode (__word__))); diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 6695ac63c7742422252f8cf16918510b6dc606d1..3a6da6e29ff8eb3b0d630515c5e330b1aaeaa611 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -34,33 +34,7 @@ static ulong get_sp(void) void arch_lmb_reserve(struct lmb *lmb) { - ulong sp, bank_end; - int bank; - - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (sp < gd->bd->bi_dram[bank].start) - continue; - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size; - if (sp >= bank_end) - continue; - lmb_reserve(lmb, sp, bank_end - sp); - break; - } + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); } static void boot_jump_linux(bootm_headers_t *images, int flag) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a5cec387a04c56ed70e797d9d5aae9e729521304..28234aa0bb6c4f02a22e5fe3695080e94f19d8de 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -22,7 +22,7 @@ config TARGET_MALTA select DYNAMIC_IO_PORT_BASE select MIPS_CM select MIPS_INSERT_BOOT_CONFIG - select MIPS_L1_CACHE_SHIFT_6 + select SYS_CACHE_SHIFT_6 select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS @@ -132,7 +132,7 @@ config TARGET_BOSTON select DM select DM_SERIAL select MIPS_CM - select MIPS_L1_CACHE_SHIFT_6 + select SYS_CACHE_SHIFT_6 select MIPS_L2_CACHE select OF_BOARD_SETUP select OF_CONTROL @@ -153,7 +153,7 @@ config TARGET_XILFPGA select DM_ETH select DM_GPIO select DM_SERIAL - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select OF_CONTROL select ROM_EXCEPTION_VECTORS select SUPPORTS_CPU_MIPS32_R1 @@ -346,7 +346,6 @@ config MIPS_RELOCATION_TABLE_SIZE config RESTORE_EXCEPTION_VECTOR_BASE bool "Restore exception vector base before booting linux kernel" - default n help In U-Boot the exception vector base will be moved to top of memory, to be used to display register dump when exception occurs. @@ -361,7 +360,6 @@ config RESTORE_EXCEPTION_VECTOR_BASE config OVERRIDE_EXCEPTION_VECTOR_BASE bool "Override the exception vector base to be restored" depends on RESTORE_EXCEPTION_VECTOR_BASE - default n help Enable this option if you want to use a different exception vector base rather than the previously saved one. @@ -376,7 +374,6 @@ config NEW_EXCEPTION_VECTOR_BASE config INIT_STACK_WITHOUT_MALLOC_F bool "Do not reserve malloc space on initial stack" - default n help Enable this option if you don't want to reserve malloc space on initial stack. This is useful if the initial stack can't hold large @@ -385,7 +382,6 @@ config INIT_STACK_WITHOUT_MALLOC_F config SPL_INIT_STACK_WITHOUT_MALLOC_F bool "Do not reserve malloc space on initial stack in SPL" - default n help Enable this option if you don't want to reserve malloc space on initial stack. This is useful if the initial stack can't hold large @@ -394,7 +390,6 @@ config SPL_INIT_STACK_WITHOUT_MALLOC_F config SPL_LOADER_SUPPORT bool - default n help Enable this option if you want to use SPL loaders without DM enabled. @@ -422,7 +417,6 @@ config MIPS_BOOT_ENV_LEGACY config MIPS_BOOT_FDT bool "Hand over a flattened device tree to Linux kernel" - default n help Enable this option if you want U-Boot to hand over a flattened device tree to the kernel. According to UHI register $a0 will be set @@ -501,7 +495,6 @@ config SYS_MIPS_CACHE_INIT_RAM_LOAD config MIPS_INIT_STACK_IN_SRAM bool - default n help Select this if the initial stack frame could be setup in SRAM. Normally the initial stack frame is set up in DRAM which is often @@ -512,7 +505,6 @@ config MIPS_INIT_STACK_IN_SRAM config MIPS_SRAM_INIT bool - default n depends on MIPS_INIT_STACK_IN_SRAM help Select this if the SRAM for initial stack needs to be initialized @@ -566,26 +558,6 @@ config SYS_CACHE_SIZE_AUTO so if you know the cache configuration for your system at compile time it would be beneficial to configure it. -config MIPS_L1_CACHE_SHIFT_4 - bool - -config MIPS_L1_CACHE_SHIFT_5 - bool - -config MIPS_L1_CACHE_SHIFT_6 - bool - -config MIPS_L1_CACHE_SHIFT_7 - bool - -config MIPS_L1_CACHE_SHIFT - int - default "7" if MIPS_L1_CACHE_SHIFT_7 - default "6" if MIPS_L1_CACHE_SHIFT_6 - default "5" if MIPS_L1_CACHE_SHIFT_5 - default "4" if MIPS_L1_CACHE_SHIFT_4 - default "5" - config MIPS_L2_CACHE bool help @@ -604,7 +576,6 @@ config MIPS_CM config MIPS_INSERT_BOOT_CONFIG bool - default n help Enable this to insert some board-specific boot configuration in the U-Boot binary at offset 0x10. diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 335aafa6a8d7dc7ee2921954a159d250c756d7eb..47251a5b92a0cc5ca268181189711c6ac7b379cb 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -233,7 +233,7 @@ wr_done: # endif #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ PTR_LA t9, lowlevel_init @@ -254,7 +254,7 @@ wr_done: nop #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ PTR_LA t9, lowlevel_init diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 00696e672de0222037266bcd81f316a226404683..d3e8a8cd414f92b135abdc1cdfda06a9867040b5 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -6,17 +6,7 @@ #ifndef __MIPS_CACHE_H__ #define __MIPS_CACHE_H__ -#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) - -/* - * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for - * DMA buffer alignment. Satisfy those drivers by providing it as a synonym - * of ARCH_DMA_MINALIGN for now. - */ -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #ifndef __ASSEMBLY__ /** diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index e65485b4fff39e6de4609c078b6d89f5cf6bd8d9..3db3965fcff55f3d51ca18bb1a3b3a69398ffdd6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -2307,8 +2307,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mflo %0, $ac0 \n" \ - " .set pop \n" \ - : "=r" (mflo0)); \ + " .set pop \n" \ + : "=r" (mflo0)); \ mflo0; \ }) @@ -2320,8 +2320,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mflo %0, $ac1 \n" \ - " .set pop \n" \ - : "=r" (mflo1)); \ + " .set pop \n" \ + : "=r" (mflo1)); \ mflo1; \ }) @@ -2333,8 +2333,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mflo %0, $ac2 \n" \ - " .set pop \n" \ - : "=r" (mflo2)); \ + " .set pop \n" \ + : "=r" (mflo2)); \ mflo2; \ }) @@ -2346,8 +2346,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mflo %0, $ac3 \n" \ - " .set pop \n" \ - : "=r" (mflo3)); \ + " .set pop \n" \ + : "=r" (mflo3)); \ mflo3; \ }) @@ -2359,8 +2359,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mfhi %0, $ac0 \n" \ - " .set pop \n" \ - : "=r" (mfhi0)); \ + " .set pop \n" \ + : "=r" (mfhi0)); \ mfhi0; \ }) @@ -2372,8 +2372,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mfhi %0, $ac1 \n" \ - " .set pop \n" \ - : "=r" (mfhi1)); \ + " .set pop \n" \ + : "=r" (mfhi1)); \ mfhi1; \ }) @@ -2385,8 +2385,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mfhi %0, $ac2 \n" \ - " .set pop \n" \ - : "=r" (mfhi2)); \ + " .set pop \n" \ + : "=r" (mfhi2)); \ mfhi2; \ }) @@ -2398,8 +2398,8 @@ do { \ " .set " MIPS_ISA_LEVEL " \n" \ " .set dsp \n" \ " mfhi %0, $ac3 \n" \ - " .set pop \n" \ - : "=r" (mfhi3)); \ + " .set pop \n" \ + : "=r" (mfhi3)); \ mfhi3; \ }) diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index fde90fced44f88fc145c0f561726be81e0a2b6ca..cab8da4860c04c3af6f38d0b61c4df7e457fe55d 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -39,14 +39,7 @@ static ulong arch_get_sp(void) void arch_lmb_reserve(struct lmb *lmb) { - ulong sp; - - sp = arch_get_sp(); - debug("## Current stack ends at 0x%08lx\n", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - lmb_reserve(lmb, sp, gd->ram_top - sp); + arch_lmb_reserve_generic(lmb, arch_get_sp(), gd->ram_top, 4096); } static void linux_cmdline_init(void) diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index b259a931c9fbbe1d8cf809c8961f6b2c11f56c8c..01d919f2dbe982d1881671ea705b1be08cf7790d 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -21,7 +21,7 @@ choice config SOC_BMIPS_BCM3380 bool "BMIPS BCM3380 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -31,7 +31,7 @@ config SOC_BMIPS_BCM3380 config SOC_BMIPS_BCM6318 bool "BMIPS BCM6318 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -41,7 +41,7 @@ config SOC_BMIPS_BCM6318 config SOC_BMIPS_BCM6328 bool "BMIPS BCM6328 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -51,7 +51,7 @@ config SOC_BMIPS_BCM6328 config SOC_BMIPS_BCM6338 bool "BMIPS BCM6338 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -61,7 +61,7 @@ config SOC_BMIPS_BCM6338 config SOC_BMIPS_BCM6348 bool "BMIPS BCM6348 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -71,7 +71,7 @@ config SOC_BMIPS_BCM6348 config SOC_BMIPS_BCM6358 bool "BMIPS BCM6358 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -81,7 +81,7 @@ config SOC_BMIPS_BCM6358 config SOC_BMIPS_BCM6368 bool "BMIPS BCM6368 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -91,7 +91,7 @@ config SOC_BMIPS_BCM6368 config SOC_BMIPS_BCM6362 bool "BMIPS BCM6362 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -101,7 +101,7 @@ config SOC_BMIPS_BCM6362 config SOC_BMIPS_BCM63268 bool "BMIPS BCM63268 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -112,7 +112,7 @@ config SOC_BMIPS_BCM63268 config SOC_BMIPS_BCM6838 bool "BMIPS BCM6838 family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h b/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h index 61cc1489889ab716c37686b55f3188056df954e2..2c0d30a80ec118ed8f2ba7b7a52294a206adc2c1 100644 --- a/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h +++ b/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h @@ -454,4 +454,3 @@ void pll_init(void); void sdram_init(void); #endif /* __JZ4780_DRAM_H__ */ - diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 8756cadb0b637ee9798e4606e9f76ed953faee71..151b004603dbd6e1129f393db9bc894f39dec7c9 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -1,6 +1,9 @@ menu "MediaTek MIPS platforms" depends on ARCH_MTMIPS +config SYS_VENDOR + default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + config SYS_MALLOC_F_LEN default 0x1000 @@ -39,7 +42,7 @@ choice config SOC_MT7620 bool "MT7620" - select MIPS_L1_CACHE_SHIFT_5 + select SYS_CACHE_SHIFT_5 select SYS_MIPS_CACHE_INIT_RAM_LOAD select PINCTRL_MT7620 select MT7620_SERIAL @@ -54,7 +57,7 @@ config SOC_MT7620 config SOC_MT7628 bool "MT7628" - select MIPS_L1_CACHE_SHIFT_5 + select SYS_CACHE_SHIFT_5 select MIPS_INIT_STACK_IN_SRAM select MIPS_SRAM_INIT select SYS_MIPS_CACHE_INIT_RAM_LOAD @@ -68,7 +71,7 @@ config SOC_MT7628 select SPL_OF_CONTROL if SPL_DM select SPL_SIMPLE_BUS if SPL_DM select SPL_DM_SERIAL if SPL_DM - select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT + select SPL_CLK if SPL_DM && SPL_SERIAL select SPL_SYSRESET if SPL_DM select SPL_OF_LIBFDT if SPL_OF_CONTROL help diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig index 5db83eb9d9a03475137ae5c762d559cd9766cf56..3ca711ad0f3fa747b1eda898c8e191d1039f04ed 100644 --- a/arch/mips/mach-mtmips/mt7620/Kconfig +++ b/arch/mips/mach-mtmips/mt7620/Kconfig @@ -66,6 +66,12 @@ config CPU_FREQ_MULTI default 6 if CPU_FREQ_600MHZ default 7 if CPU_FREQ_620MHZ -source "board/mediatek/mt7620/Kconfig" +config SYS_CONFIG_NAME + string "Board configuration name" + default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + +config SYS_BOARD + string "Board name" + default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB endif diff --git a/arch/mips/mach-mtmips/mt7620/serial.c b/arch/mips/mach-mtmips/mt7620/serial.c index 44f061cd6cc24442ec962514eded6601a49c5b34..35544b8537eddf26eb29572d2531809da87a7ca8 100644 --- a/arch/mips/mach-mtmips/mt7620/serial.c +++ b/arch/mips/mach-mtmips/mt7620/serial.c @@ -23,7 +23,7 @@ void board_debug_uart_init(void) void mtmips_spl_serial_init(void) { -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); #if CONFIG_CONS_INDEX == 1 @@ -32,5 +32,5 @@ void mtmips_spl_serial_init(void) clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, UARTF_MODE_UARTF_GPIO << UARTF_SHARE_MODE_S); #endif -#endif /* CONFIG_SPL_SERIAL_SUPPORT */ +#endif /* CONFIG_SPL_SERIAL */ } diff --git a/arch/mips/mach-mtmips/mt7628/Kconfig b/arch/mips/mach-mtmips/mt7628/Kconfig index e3f56e782ebbb4c8119c929791ffc6ed2b7db52c..e7273591bca13cfaa08988b97494c24e6ca15ad0 100644 --- a/arch/mips/mach-mtmips/mt7628/Kconfig +++ b/arch/mips/mach-mtmips/mt7628/Kconfig @@ -29,7 +29,7 @@ config BOARD_MT7628_RFB config BOARD_VOCORE2 bool "VoCore2" - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_UART2_SPIS_PINMUX help VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM @@ -39,14 +39,20 @@ endchoice config SPL_UART2_SPIS_PINMUX bool "Use alternative pinmux for UART2 in SPL stage" - depends on SPL_SERIAL_SUPPORT - default n + depends on SPL_SERIAL help Select this if the UART2 of your board is connected to GPIO 16/17 (shared with SPIS) rather than the usual GPIO 20/21. +config SYS_BOARD + string "Board name" + default "mt7628" if BOARD_MT7628_RFB + +config SYS_CONFIG_NAME + string "Board configuration name" + default "mt7628" if BOARD_MT7628_RFB + source "board/gardena/smart-gateway-mt7688/Kconfig" -source "board/mediatek/mt7628/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" source "board/vocore/vocore2/Kconfig" diff --git a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S index e4a6c03580820c8779c3f48ae480e0e991c6f7a5..83cd8fa9b6b5e8c226d2154730fc784f561d41fc 100644 --- a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S +++ b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S @@ -28,7 +28,7 @@ .set noreorder LEAF(mips_sram_init) -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) /* Setup CPU PLL */ li t0, DELAY_USEC(1000000) li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG) @@ -116,7 +116,7 @@ _cpu_pll_done: sub a1, CONFIG_SYS_DCACHE_LINE_SIZE bnez a1, 3b nop -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ jr ra nop diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c index a7d324792d739ac8e18e217acf67762ae3cff903..e5f3f87a6737004f2b1b6ff616d8b6ae65cafac7 100644 --- a/arch/mips/mach-mtmips/mt7628/serial.c +++ b/arch/mips/mach-mtmips/mt7628/serial.c @@ -11,7 +11,7 @@ void mtmips_spl_serial_init(void) { -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); #if CONFIG_CONS_INDEX == 1 @@ -30,5 +30,5 @@ void mtmips_spl_serial_init(void) 1 << SPIS_MODE_S); #endif /* CONFIG_SPL_UART2_SPIS_PINMUX */ #endif /* CONFIG_CONS_INDEX */ -#endif /* CONFIG_SPL_SERIAL_SUPPORT */ +#endif /* CONFIG_SPL_SERIAL */ } diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c index 95201b8d7ab2050af5c66df460b57841064dbf0c..fe5b49e702f11392cdc3cbdffe6cb42d8dcfc42d 100644 --- a/arch/mips/mach-mtmips/spl.c +++ b/arch/mips/mach-mtmips/spl.c @@ -17,7 +17,7 @@ void __noreturn board_init_f(ulong dummy) { spl_init(); -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL /* * mtmips_spl_serial_init() is useful if debug uart is enabled, * or DM based serial is not enabled. diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig index 5f13bf14ed6bae99b76fb851e8d3233ff67df731..2afa972074c19cf368462869756bede0259b7559 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -9,7 +9,7 @@ choice config SOC_PIC32MZDA bool "Microchip PIC32MZ[DA] family" - select MIPS_L1_CACHE_SHIFT_4 + select SYS_CACHE_SHIFT_4 select ROM_EXCEPTION_VECTORS select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index b6f16bf1244662c91ad9bdac861c684600b955e0..435333720c734afa2008fb5671a702c237392898 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -18,7 +18,6 @@ endchoice config SYS_ICACHE_OFF bool "Do not enable icache" - default n help Do not enable instruction cache in U-Boot. @@ -31,7 +30,6 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" - default n help Do not enable data cache in U-Boot. diff --git a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S index 507d79e77b8b98635210de385806474f18eef05f..d1c5b87f7e922f2a0b1c565a65015fac0f112d02 100644 --- a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S @@ -38,9 +38,9 @@ * for Orca and Emerald */ #define BOARD_ID_REG 0x104 -#define BOARD_ID_FAMILY_MASK 0xfff000 -#define BOARD_ID_FAMILY_V5 0x556000 -#define BOARD_ID_FAMILY_K7 0x74b000 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 /* * parameters for the static memory controller @@ -94,7 +94,7 @@ mem_init: move $lp, $r11 ret -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) .globl lowlevel_init lowlevel_init: move $r10, $lp @@ -144,4 +144,4 @@ enable_fpu: ret #endif -#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 73f1f52056a6fbcde49f762058e49baa568caf78..c423b38f896f4f9fd2aa1e1cb5d2cce3f852a724 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -38,9 +38,9 @@ * for Orca and Emerald */ #define BOARD_ID_REG 0x104 -#define BOARD_ID_FAMILY_MASK 0xfff000 -#define BOARD_ID_FAMILY_V5 0x556000 -#define BOARD_ID_FAMILY_K7 0x74b000 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 /* * parameters for the static memory controller @@ -164,7 +164,7 @@ sdram_b0_cr: ret -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) .globl lowlevel_init lowlevel_init: @@ -314,4 +314,4 @@ show_led: li $r8, (CONFIG_DEBUG_LED) swi $r7, [$r8] ret -#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S index 243096a663e1883a40909cd35c68cef86618a51a..8e7399d0df7277070be8bc2c4ae3e34a8da2ea54 100644 --- a/arch/nds32/cpu/n1213/ag101/watchdog.S +++ b/arch/nds32/cpu/n1213/ag101/watchdog.S @@ -16,7 +16,7 @@ ENTRY(turnoff_watchdog) #define WD_ENABLE 0x1 ! Turn off the watchdog, according to Faraday FTWDT010 spec - li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR + li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR lwi $p1, [$p0] ! Get the config of WD andi $p1, $p1, 0x1f ! Wipe out useless bits li $r0, ~WD_ENABLE diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 3395721552a3a94836659e0262d5e064fe103f5a..93ea5e4ad48e200c8da0779db8a3d3bc9560c408 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -20,7 +20,7 @@ */ #define ENA_DCAC 2UL #define DIS_DCAC ~ENA_DCAC -#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way +#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way @@ -174,7 +174,7 @@ set_ivb: jal mem_init -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) jal lowlevel_init /* * gp = ~VMA for burn mode @@ -434,21 +434,21 @@ tlb_fill: SAVE_ALL move $r0, $sp ! To get the kernel stack li $r1, 1 ! Determine interruption type - bal do_interruption + bal do_interruption .align 5 tlb_not_present: SAVE_ALL move $r0, $sp ! To get the kernel stack li $r1, 2 ! Determine interruption type - bal do_interruption + bal do_interruption .align 5 tlb_misc: SAVE_ALL move $r0, $sp ! To get the kernel stack li $r1, 3 ! Determine interruption type - bal do_interruption + bal do_interruption .align 5 tlb_vlpt_miss: diff --git a/arch/nds32/include/asm/bootm.h b/arch/nds32/include/asm/bootm.h index 804f8581b6e7c9dc0a2967abd4406b166e0a2f9e..c956fdd49c94272468d4a90aaaebfc63cfdcd792 100644 --- a/arch/nds32/include/asm/bootm.h +++ b/arch/nds32/include/asm/bootm.h @@ -12,11 +12,7 @@ extern void udc_disconnect(void); -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) +#ifdef CONFIG_SUPPORT_PASSING_ATAGS # define BOOTM_ENABLE_TAGS 1 #else # define BOOTM_ENABLE_TAGS 0 diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 4cb0f530ae1a2178c47e83aaa5907031be377720..1c7f78569991990bf25f0b1a553273240822d0e0 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -19,11 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) +#ifdef CONFIG_SUPPORT_PASSING_ATAGS static void setup_start_tag(struct bd_info *bd); # ifdef CONFIG_SETUP_MEMORY_TAGS @@ -38,7 +34,7 @@ static void setup_initrd_tag(struct bd_info *bd, ulong initrd_start, static void setup_end_tag(struct bd_info *bd); static struct tag *params; -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +#endif /* CONFIG_SUPPORT_PASSING_ATAGS */ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { @@ -82,11 +78,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) } #endif } else if (BOOTM_ENABLE_TAGS) { -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) +#ifdef CONFIG_SUPPORT_PASSING_ATAGS setup_start_tag(bd); #ifdef CONFIG_SERIAL_TAG setup_serial_tag(¶ms); @@ -127,11 +119,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) return 1; } -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) +#ifdef CONFIG_SUPPORT_PASSING_ATAGS static void setup_start_tag(struct bd_info *bd) { params = (struct tag *)bd->bi_boot_params; @@ -244,4 +232,17 @@ static void setup_end_tag(struct bd_info *bd) params->hdr.size = 0; } -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +#endif /* CONFIG_SUPPORT_PASSING_ATAGS */ + +static ulong get_sp(void) +{ + ulong ret; + + asm("move %0, $sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index f5ad184e8d0bd53bf579f1e6ab0a874c8d3659b5..acb8ca686ed977911bc5dbafad404e8f14f21983 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -6,7 +6,6 @@ #include #include -#include /* * icache and dcache configuration used only for start.S. diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 503746715155ed1aa868d57a67c3fadc43a594f7..3cb59bd977731c25bd86661a7738581260a7769c 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -10,6 +10,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ @@ -60,3 +63,16 @@ int do_bootm_linux(int flag, int argc, char *const argv[], return 1; } + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 083febe5bb3dea0478abc153041d7efb0e34efe1..cff98f7599fa783f977fcb1e1426f1047aa38722 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -8,22 +8,6 @@ choice prompt "Target select" optional -config TARGET_MPC8349EMDS - bool "Support MPC8349EMDS" - select ARCH_MPC8349 - select BOARD_EARLY_INIT_F - select SYS_FSL_DDR - select SYS_FSL_DDR_BE - select SYS_FSL_HAS_DDR2 - -config TARGET_MPC8349EMDS_SDRAM - bool "Support MPC8349EMDS_SDRAM" - select ARCH_MPC8349 - select BOARD_EARLY_INIT_F - select SYS_FSL_DDR - select SYS_FSL_DDR_BE - select SYS_FSL_HAS_DDR2 - config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -119,7 +103,7 @@ config MPC83XX_PCIE2_SUPPORT config MPC83XX_SDHC_SUPPORT bool -config MPC83XX_SATA_SUPPORT +config MPC83XX_SATA bool config MPC83XX_SECOND_I2C @@ -131,6 +115,7 @@ config MPC83XX_LDP_PIN config ARCH_MPC830X bool select MPC83XX_SDHC_SUPPORT + select SYS_CACHE_SHIFT_5 config ARCH_MPC8308 bool @@ -154,6 +139,7 @@ config ARCH_MPC831X select MPC83XX_PCI_SUPPORT select MPC83XX_TSEC1_SUPPORT select MPC83XX_TSEC2_SUPPORT + select SYS_CACHE_SHIFT_5 config ARCH_MPC8313 bool @@ -165,18 +151,11 @@ config ARCH_MPC832X bool select MPC83XX_QUICC_ENGINE select MPC83XX_PCI_SUPPORT + select SYS_CACHE_SHIFT_5 config ARCH_MPC834X bool - -config ARCH_MPC8349 - bool - select ARCH_MPC834X - select MPC83XX_PCI_SUPPORT - select MPC83XX_TSEC1_SUPPORT - select MPC83XX_TSEC2_SUPPORT - select MPC83XX_LDP_PIN - select MPC83XX_SECOND_I2C + select SYS_CACHE_SHIFT_5 config ARCH_MPC8360 bool @@ -184,6 +163,7 @@ config ARCH_MPC8360 select MPC83XX_PCI_SUPPORT select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C + select SYS_CACHE_SHIFT_5 config ARCH_MPC837X bool @@ -193,9 +173,10 @@ config ARCH_MPC837X select MPC83XX_PCIE1_SUPPORT select MPC83XX_PCIE2_SUPPORT select MPC83XX_SDHC_SUPPORT - select MPC83XX_SATA_SUPPORT + select MPC83XX_SATA select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C + select SYS_CACHE_SHIFT_5 select FSL_ELBC config SYS_IMMR @@ -214,36 +195,9 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig" -menu "Legacy options" - -if ARCH_MPC8349 - -#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT -choice - prompt "PMC slot configuration" - -config PCI_ALL_PCI1 - bool "All PMC slots on PCI1" - -config PCI_ONE_PCI1 - bool "First PMC1 on PCI1" - -config PCI_TWO_PCI1 - bool "First two PMC1 on PCI1" - -endchoice - -config PCI_64BIT - bool "PMC2 is 64bit" - -endif - -endmenu - config FSL_ELBC bool -source "board/freescale/mpc8349emds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index aeb42b109d0480ccd16d40401fd6ebb6ad145c0f..7c4ef7657e5bf4875a1969e5e38a05fe2aeb5a36 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -26,7 +26,7 @@ obj-y += cpu.o obj-y += cpu_init.o obj-y += speed.o obj-y += interrupts.o -obj-y += ecc.o +obj-$(CONFIG_DDR_ECC_CMD) += ecc.o ifndef CONFIG_PINCTRL obj-$(CONFIG_QE) += qe_io.o endif diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 7a8ec7f42f1cb493c88e52adc155739db1dd0db0..3e24752e2f6c162c822eae7e4a10d528ba11798f 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -11,7 +11,6 @@ #include #include -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) void ecc_print_status(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; @@ -386,4 +385,3 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc, " - writes pattern injecting errors with word access\n" " - writes pattern with word access, generates error\n" " - disables injects\n" " - re-inits memory"); -#endif diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 index 23e81ab0bf91c714ff70c07001232b958262f9ca..208eed0495aea9dc373425b4882d33ec6491beb3 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -22,7 +22,7 @@ config BR0_PORTSIZE_16BIT config BR0_PORTSIZE_32BIT depends on !BR0_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR0_MACHINE_GPCM bool "GPCM" config BR0_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR0_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR0_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 index 08dcc7dd2ba32ae53369ef56312c20d4d6419d82..1dc3e75076cb0f3851d9cbc114f08eac9c325b5d 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -22,7 +22,7 @@ config BR1_PORTSIZE_16BIT config BR1_PORTSIZE_32BIT depends on !BR1_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR1_MACHINE_GPCM bool "GPCM" config BR1_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR1_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR1_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 index 298d87f5e0f4c39ba34e6932eb75120ea901b46b..a9b2546cd88ea0509f8b99892aff43b8da4bdb60 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -22,7 +22,7 @@ config BR2_PORTSIZE_16BIT config BR2_PORTSIZE_32BIT depends on !BR2_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR2_MACHINE_GPCM bool "GPCM" config BR2_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR2_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR2_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 index 963831bfcbd1baff547f226c0377d7fb7d70159d..94442cdc9778e2c4ecf4546920135597c779676a 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -22,7 +22,7 @@ config BR3_PORTSIZE_16BIT config BR3_PORTSIZE_32BIT depends on !BR3_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR3_MACHINE_GPCM bool "GPCM" config BR3_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR3_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR3_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 index 0063dab96223ce2c279218e0718fd9468123403a..5d69385a23da0a80254a310fe4d70006aff6c09e 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -22,7 +22,7 @@ config BR4_PORTSIZE_16BIT config BR4_PORTSIZE_32BIT depends on !BR4_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR4_MACHINE_GPCM bool "GPCM" config BR4_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR4_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR4_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig index c367ad2ce157b9420b6bef0f81f6b7da1760a6c6..1f61108ceee6059497790d87945879008ba67146 100644 --- a/arch/powerpc/cpu/mpc83xx/hid/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig @@ -434,7 +434,7 @@ config HID2_IWLCK_1 config HID2_IWLCK_2 bool "Way 0 through 2 locked" -if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 +if ARCH_MPC8360 || ARCH_MPC8379 config HID2_IWLCK_3 bool "Way 0 through 3 locked" @@ -470,7 +470,7 @@ config HID2_DWLCK_1 config HID2_DWLCK_2 bool "Way 0 through 2 locked" -if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 +if ARCH_MPC8360 || ARCH_MPC8379 config HID2_DWLCK_3 bool "Way 0 through 3 locked" diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index 75ec9c9a3464ba13dcb1a128c23bdbf654bebd5e..71fa73801ae19c86c5816b2b4965274574963cf7 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1 bool "1 : 1" config LBMC_CLOCK_MODE_1_2 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "1 : 2" endchoice @@ -19,12 +19,12 @@ config DDR_MC_CLOCK_MODE_1_2 bool "1 : 2" config DDR_MC_CLOCK_MODE_1_1 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "1 : 1" endchoice -if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 +if !ARCH_MPC8313 && !ARCH_MPC832X choice prompt "System PLL VCO division" @@ -67,43 +67,43 @@ config SYSTEM_PLL_FACTOR_6_1 bool "6 : 1" config SYSTEM_PLL_FACTOR_7_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "7 : 1" config SYSTEM_PLL_FACTOR_8_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "8 : 1" config SYSTEM_PLL_FACTOR_9_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "9 : 1" config SYSTEM_PLL_FACTOR_10_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "10 : 1" config SYSTEM_PLL_FACTOR_11_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "11 : 1" config SYSTEM_PLL_FACTOR_12_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "12 : 1" config SYSTEM_PLL_FACTOR_13_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "13 : 1" config SYSTEM_PLL_FACTOR_14_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "14 : 1" config SYSTEM_PLL_FACTOR_15_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "15 : 1" config SYSTEM_PLL_FACTOR_16_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 + depends on ARCH_MPV8360 bool "16 : 1" endchoice @@ -310,21 +310,6 @@ config PCI_HOST_MODE_ENABLE endchoice -if ARCH_MPC8349 - -choice - prompt "PCI 64-bit mode" - -config PCI_64BIT_MODE_DISABLE - bool "Disabled" - -config PCI_64BIT_MODE_ENABLE - bool "Enabled" - -endchoice - -endif - choice prompt "PCI internal arbiter 1 mode" @@ -336,21 +321,6 @@ config PCI_INT_ARBITER1_ENABLE endchoice -if ARCH_MPC8349 - -choice - prompt "PCI internal arbiter 2 mode" - -config PCI_INT_ARBITER2_DISABLE - bool "Disabled" - -config PCI_INT_ARBITER2_ENABLE - bool "Enabled" - -endchoice - -endif - if ARCH_MPC8360 choice @@ -425,10 +395,6 @@ config BOOT_ROM_INTERFACE_PCI1 depends on MPC83XX_PCI_SUPPORT bool "PCI1" -config BOOT_ROM_INTERFACE_PCI2 - depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 - bool "PCI2" - config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM depends on ARCH_MPC837X bool "PCI2" @@ -448,15 +414,15 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT bool "Local bus GPCM - 16-bit ROM" config BOOT_ROM_INTERFACE_GPCM_32BIT - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "Local bus GPCM - 32-bit ROM" config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "Local bus NAND Flash- 8-bit small page ROM" config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "Local bus NAND Flash- 8-bit large page ROM" endchoice @@ -467,11 +433,10 @@ choice prompt "TSEC1 mode" config TSEC1_MODE_MII - depends on !ARCH_MPC8349 bool "MII" config TSEC1_MODE_RMII - depends on ARCH_MPC831X && !ARCH_MPC8349 + depends on ARCH_MPC831X bool "RMII" config TSEC1_MODE_RGMII @@ -481,14 +446,6 @@ config TSEC1_MODE_RTBI depends on ARCH_MPC831X || ARCH_MPC837X bool "RTBI" -config TSEC1_MODE_GMII - depends on ARCH_MPC8349 - bool "GMII" - -config TSEC1_MODE_TBI - depends on ARCH_MPC8349 - bool "TBI" - config TSEC1_MODE_SGMII depends on ARCH_MPC831X || ARCH_MPC837X bool "SGMII" @@ -503,11 +460,10 @@ choice prompt "TSEC2 mode" config TSEC2_MODE_MII - depends on !ARCH_MPC8349 bool "MII" config TSEC2_MODE_RMII - depends on ARCH_MPC831X && !ARCH_MPC8349 + depends on ARCH_MPC831X bool "RMII" config TSEC2_MODE_RGMII @@ -517,14 +473,6 @@ config TSEC2_MODE_RTBI depends on ARCH_MPC831X || ARCH_MPC837X bool "RTBI" -config TSEC2_MODE_GMII - depends on ARCH_MPC8349 - bool "GMII" - -config TSEC2_MODE_TBI - depends on ARCH_MPC8349 - bool "TBI" - config TSEC2_MODE_SGMII depends on ARCH_MPC831X || ARCH_MPC837X bool "SGMII" @@ -559,7 +507,7 @@ endchoice endif -if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 +if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360 choice prompt "LALE timing" @@ -603,7 +551,7 @@ config DDR_MC_CLOCK_MODE config SYSTEM_PLL_VCO_DIV int - default 0 if ARCH_MPC8349 || ARCH_MPC832X + default 0 if ARCH_MPC832X default 2 if ARCH_MPC8313 default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X @@ -675,7 +623,6 @@ config BOOT_ROM_INTERFACE hex default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM default 0x4 if BOOT_ROM_INTERFACE_PCI1 - default 0x8 if BOOT_ROM_INTERFACE_PCI2 default 0x8 if BOOT_ROM_INTERFACE_ESDHC default 0xc if BOOT_ROM_INTERFACE_SPI default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM @@ -690,26 +637,18 @@ config TSEC1_MODE default 0x0 if !MPC83XX_TSEC1_SUPPORT default 0x0 if TSEC1_MODE_MII default 0x1 if TSEC1_MODE_RMII - default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 - default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 + default 0x3 if TSEC1_MODE_RGMII + default 0x5 if TSEC1_MODE_RTBI default 0x6 if TSEC1_MODE_SGMII - default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 - default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 - default 0x2 if TSEC1_MODE_GMII - default 0x3 if TSEC1_MODE_TBI config TSEC2_MODE hex default 0x0 if !MPC83XX_TSEC2_SUPPORT default 0x0 if TSEC2_MODE_MII default 0x1 if TSEC2_MODE_RMII - default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 - default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 + default 0x3 if TSEC2_MODE_RGMII + default 0x5 if TSEC2_MODE_RTBI default 0x6 if TSEC2_MODE_SGMII - default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 - default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 - default 0x2 if TSEC2_MODE_GMII - default 0x3 if TSEC2_MODE_TBI config SECONDARY_DDR_IO int @@ -792,9 +731,7 @@ config PCI_HOST_MODE config PCI_64BIT_MODE int - default 0 if !ARCH_MPC8349 - default 0 if PCI_64BIT_MODE_DISABLE - default 1 if PCI_64BIT_MODE_ENABLE + default 0 config PCI_INT_ARBITER1 int @@ -804,9 +741,7 @@ config PCI_INT_ARBITER1 config PCI_INT_ARBITER2 int - default 0 if !ARCH_MPC8349 - default 0 if PCI_INT_ARBITER2_DISABLE - default 1 if PCI_INT_ARBITER2_ENABLE + default 0 config PCI_CLOCK_OUTPUT_DRIVE int diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h index 7d66ba726b91c4699a60968af9bfb1e80ffbe4d5..0f34267891817132dbaa9959d49a870536c656a9 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -1,11 +1,3 @@ -#ifdef CONFIG_ARCH_MPC8349 -#define TSEC1_MODE_SHIFT 17 -#define TSEC2_MODE_SHIFT 19 -#else -#define TSEC1_MODE_SHIFT 18 -#define TSEC2_MODE_SHIFT 21 -#endif - #define CONFIG_SYS_HRCW_LOW (\ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ @@ -28,8 +20,8 @@ (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ - (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ - (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ + (CONFIG_TSEC1_MODE << (31 - 18)) |\ + (CONFIG_TSEC2_MODE << (31 - 21)) |\ (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ (CONFIG_LALE_TIMING << (31 - 29)) |\ diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr index f32309e6c0f0dce383479f2a25c6d1663ef7c226..33e1295df1495b94bafea8e01814c949f7c2823b 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr @@ -38,50 +38,6 @@ endchoice endif -if ARCH_MPC8349 - -choice - prompt "TSEC1 emergency priority" - -config SPCR_TSEC1EP_UNSET - bool "Don't set value" - -config SPCR_TSEC1EP_0 - bool "Level 0 (lowest priority)" - -config SPCR_TSEC1EP_1 - bool "Level 1" - -config SPCR_TSEC1EP_2 - bool "Level 2" - -config SPCR_TSEC1EP_3 - bool "Level 3 (highest priority)" - -endchoice - -choice - prompt "TSEC2 emergency priority" - -config SPCR_TSEC2EP_UNSET - bool "Don't set value" - -config SPCR_TSEC2EP_0 - bool "Level 0 (lowest priority)" - -config SPCR_TSEC2EP_1 - bool "Level 1" - -config SPCR_TSEC2EP_2 - bool "Level 2" - -config SPCR_TSEC2EP_3 - bool "Level 3 (highest priority)" - -endchoice - -endif - config SPCR_OPT hex default 0x0 if SPCR_OPT_UNSET diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 84797c871c95f806e71256543c31de5fd320e25f..c386e4ed3fde5330bfd040b29f28da10a105ce15 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -34,148 +34,6 @@ static struct { #endif }; -#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES - -/* private structure for mpc83xx pcie hose */ -static struct mpc83xx_pcie_priv { - u8 index; -} pcie_priv[PCIE_MAX_BUSES] = { - { - /* pcie controller 1 */ - .index = 0, - }, - { - /* pcie controller 2 */ - .index = 1, - }, -}; - -static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) -{ - int bus = PCI_BUS(dev) - hose->first_busno; - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; - pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; - struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; - u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); - u32 dev_base = bus << 24 | devfn << 16; - - if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) - return -1; - /* - * Workaround for the HW bug: for Type 0 configure transactions the - * PCI-E controller does not check the device number bits and just - * assumes that the device number bits are 0. - */ - if (devfn & 0xf8) - return -1; - - out_le32(&out_win->tarl, dev_base); - return 0; -} - -#define cfg_read(val, addr, type, op) \ - do { *val = op((type)(addr)); } while (0) -#define cfg_write(val, addr, type, op) \ - do { op((type *)(addr), (val)); } while (0) - -#define cfg_read_err(val) do { *val = -1; } while (0) -#define cfg_write_err(val) do { } while (0) - -#define PCIE_OP(rw, size, type, op) \ -static int pcie_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, \ - type val) \ -{ \ - int ret; \ - \ - ret = mpc83xx_pcie_remap_cfg(hose, dev); \ - if (ret) { \ - cfg_##rw##_err(val); \ - return ret; \ - } \ - cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ - return 0; \ -} - -PCIE_OP(read, byte, u8 *, in_8) -PCIE_OP(read, word, u16 *, in_le16) -PCIE_OP(read, dword, u32 *, in_le32) -PCIE_OP(write, byte, u8, out_8) -PCIE_OP(write, word, u16, out_le16) -PCIE_OP(write, dword, u32, out_le32) - -static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, - u8 link) -{ - extern void disable_addr_trans(void); /* start.S */ - static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; - struct pci_controller *hose = &pcie_hose[bus]; - int i; - - /* - * There are no spare BATs to remap all PCI-E windows for U-Boot, so - * disable translations. In general, this is not great solution, and - * that's why we don't register PCI-E hoses by default. - */ - disable_addr_trans(); - - for (i = 0; i < 2; i++, reg++) { - if (reg->size == 0) - break; - - hose->regions[i] = *reg; - hose->region_count++; - } - - i = hose->region_count++; - hose->regions[i].bus_start = 0; - hose->regions[i].phys_start = 0; - hose->regions[i].size = gd->ram_size; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - - i = hose->region_count++; - hose->regions[i].bus_start = CONFIG_SYS_IMMR; - hose->regions[i].phys_start = CONFIG_SYS_IMMR; - hose->regions[i].size = 0x100000; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - - hose->first_busno = pci_last_busno() + 1; - hose->last_busno = 0xff; - - hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; - - hose->priv_data = &pcie_priv[bus]; - - pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); - - if (!link) - hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; - - pci_register_hose(hose); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} - -#else - -static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, - u8 link) {} - -#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ - int get_pcie_clk(int index) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; @@ -340,8 +198,6 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) printf("link\n"); else printf("No link\n"); - - mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); } /* diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index a861e8dd2ddcfe05b3ce2522678414daf2c8530f..e12043b260935d4b7b579149135b36581b673a8d 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -834,12 +834,6 @@ long int spd_sdram() #endif debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); -#if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - sdram_cfg |= SDRAM_CFG_2T_EN; -#endif /* Enable controller, and GO! */ ddr->sdram_cfg = sdram_cfg; sync(); @@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size) pattern[0] = 0xdeadbeef; pattern[1] = 0xdeadbeef; -#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) - dma_meminit(pattern[0], dram_size); -#else debug("ddr init: CPU FP write method\n"); size = dram_size; for (p = 0; p < (u64*)(size); p++) { ppcDWstore((u32*)p, pattern); } sync(); -#endif t_end = get_tbms(); icache_disable(); diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 9da22ce486a94627baf65c00b6ec678ae44320c8..c4953df4a27170870744ccc29c248df0e217489d 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -13,7 +13,6 @@ #include #include #include -#include #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ @@ -92,12 +91,6 @@ */ .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - .align 2 - .globl enable_addr_trans enable_addr_trans: /* enable address translation */ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 66ebaf529ff90dee8647bde77849f10721bfb0f6..836aeddbe29f78111dde6c7363bef8d90ab04115 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -48,6 +48,7 @@ config TARGET_MPC8548CDS bool "Support MPC8548CDS" select ARCH_MPC8548 select FSL_VIA + select SYS_CACHE_SHIFT_5 config TARGET_P1010RDB_PA bool "Support P1010RDB_PA" @@ -316,6 +317,7 @@ config ARCH_MPC8540 config ARCH_MPC8544 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A005125 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 @@ -350,6 +352,7 @@ config ARCH_MPC8560 config ARCH_P1010 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 @@ -395,6 +398,7 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 @@ -490,6 +494,7 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 @@ -510,6 +515,7 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -534,6 +540,7 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 @@ -563,6 +570,7 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004580 @@ -601,6 +609,7 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004699 @@ -624,11 +633,13 @@ config ARCH_P5040 config ARCH_QEMU_E500 bool + select SYS_CACHE_SHIFT_5 config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -651,6 +662,7 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -673,6 +685,7 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -696,6 +709,7 @@ config ARCH_T2080 select E500MC select E6500 select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -718,12 +732,14 @@ config ARCH_T2080 imply CMD_NAND imply CMD_REGINFO imply FSL_SATA + imply ID_EEPROM config ARCH_T4240 bool select E500MC select E6500 select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 15248a40824beb0c76b50a3131a0ab5c2a670892..6f4ad1f9b762017706116e3eed9c7afa2e7eb03d 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o endif obj-$(CONFIG_CPM2) += commproc.o -obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_CORENET) += liodn.o obj-$(CONFIG_MP) += mp.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 610a8ec43f5bd71faa182f5ef232783968ecaa79..cd32290410f69966477cff4dd21fa1a5b86b627c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -52,7 +53,8 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \ + defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif @@ -70,12 +72,12 @@ int checkcpu (void) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ -#ifdef CONFIG_DDR_CLK_FREQ +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; -#endif /* CONFIG_DDR_CLK_FREQ */ +#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c deleted file mode 100644 index 3c4eb1a7eba942b225f5cb59546319ff0243c3d1..0000000000000000000000000000000000000000 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * MPC8560 FCC Fast Ethernet - * Copyright (c) 2003 Motorola,Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - */ - -/* - * MPC8560 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -#include -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CONFIG_SYS_CMXFCR_MASK1, - CONFIG_SYS_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CONFIG_SYS_CMXFCR_MASK2, - CONFIG_SYS_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CONFIG_SYS_CMXFCR_MASK3, - CONFIG_SYS_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -#undef ET_DEBUG - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int i = 0; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ - BD_ENET_TX_TC | BD_ENET_TX_PAD); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); - printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); - for(i=0;i<(length/16 + 1);i++) { - printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); - } -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - txIdx = (txIdx + 1) % TX_BUF_CNT; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, struct bd_info *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - cpm->im_cpm_mux.cmxuar = 0; /* ATM */ - cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 1){ - cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 2){ - cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } - - /* 28.9 - (6): FDSR: Ethernet Syn */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fdsr = 0xD555; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fdsr = 0xD555; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fdsr = 0xD555; - } - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = 0; - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = 0; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 - * 0x9000 for MPC8541, MPC8555 - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_rbdstat = 0; - pram_ptr->fen_genfcc.fcc_rbdlen = 0; - pram_ptr->fen_genfcc.fcc_rdptr = 0; - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - pram_ptr->fen_genfcc.fcc_tbdstat = 0; - pram_ptr->fen_genfcc.fcc_tbdlen = 0; - pram_ptr->fen_genfcc.fcc_tdptr = 0; - - /* protocol-specific area */ - pram_ptr->fen_statbuf = 0x0; - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_crcec = 0; - pram_ptr->fen_alec = 0; - pram_ptr->fen_disfc = 0; - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_retcnt = 0; - pram_ptr->fen_pper = 0; - pram_ptr->fen_boffcnt = 0; - pram_ptr->fen_gaddrh = 0; - pram_ptr->fen_gaddrl = 0; - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_ethaddr() - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_ibdcount = 0; - pram_ptr->fen_ibdstart = 0; - pram_ptr->fen_ibdend = 0; - pram_ptr->fen_txlen = 0; - pram_ptr->fen_iaddrh = 0; /* disable hash */ - pram_ptr->fen_iaddrl = 0; - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ - -#if defined(ET_DEBUG) - printf("parm_ptr(0xff788500) = %p\n",pram_ptr); - printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8)(9): clear out events in FCCE */ - /* 28.9 - (9): FCCM: mask all events */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fcce = ~0x0; - cpm->im_cpm_fcc1.fccm = 0; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fcce = ~0x0; - cpm->im_cpm_fcc2.fccm = 0; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fcce = ~0x0; - cpm->im_cpm_fcc3.fccm = 0; - } - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - - /* write GFMR: disable tx/rx */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } -} - -int fec_initialize(struct bd_info *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d", - ether_fcc_info[i].ether_index + 1); - dev->priv = ðer_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - - return 1; -} - -#endif diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 5bf0047930fef9ba65507e17fea5f47e49887877..da8e0b655544bed6c0196e672dbf9be4dad742e8 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -399,4 +399,3 @@ const char *serdes_clock_to_string(u32 clock) #endif } } - diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index f5126e2c8acfb5c2b215d8182de1d1070fab09e7..2b4912bea0a331c852bb770e6e75fd6c915616b0 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -885,4 +885,3 @@ const char *serdes_clock_to_string(u32 clock) return "150"; } } - diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e229a5c5a7e0cc15901f70170728af52001729d9..1fe914a4e43157dba9cd074139b976e385282105 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -104,8 +105,8 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; else #endif -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #else sys_info->freq_ddrbus = sysclk; #endif @@ -538,12 +539,12 @@ void get_sys_info(sys_info_t *sys_info) /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ sys_info->freq_ddrbus = sys_info->freq_systembus; -#ifdef CONFIG_DDR_CLK_FREQ +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) { u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) - sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk(); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index f41e82ad189f8b7b03234a35ad860b21f803af7c..656cc6ec8024274409c2a0ee6048516232b08da4 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -77,7 +76,7 @@ _start_e500: /* Enable debug exception */ li r1,MSR_DE - mtmsr r1 + mtmsr r1 /* * If we got an ePAPR device tree pointer passed in as r3, we need that @@ -1138,11 +1137,7 @@ switch_as: .globl _start _start: .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ @@ -1164,9 +1159,9 @@ _start_cont: li r0,0 -1: subi r4,r4,4 - stw r0,0(r4) - cmplw r4,r3 +1: subi r4,r4,4 + stw r0,0(r4) + cmplw r4,r3 bne 1b #if CONFIG_VAL(SYS_MALLOC_F_LEN) diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index f112317376567b6fbc24c4783b4b6a019a338fc5..936cbda11bc37126e4cab13084c48b7ad9fc6dae 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -19,9 +19,11 @@ choice config MPC866 bool "MPC866" + select SYS_CACHE_SHIFT_4 config MPC885 bool "MPC885" + select SYS_CACHE_SHIFT_4 endchoice diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index ed735cdee00540292b7857ed03424e28cec7b4fe..0ebb7b33a8bc38b7391098876dcc6c698e5d05ae 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -62,9 +61,6 @@ */ .text .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index eda64861ee6fee89aeaf74f0956142a162caeb60..0985fb2d05776c9a4959a3c935d1f03c25ef4576 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -351,10 +351,6 @@ int fixup_cpu(void) */ int cpu_eth_init(struct bd_info *bis) { -#if defined(CONFIG_ETHER_ON_FCC) - fec_initialize(bis); -#endif - #if defined(CONFIG_UEC_ETH) uec_standard_init(bis); #endif diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index ac8eeb4caa5ab391cbf0bd9d4c518265d9f2f5b8..f753ddf799ee76b6f0be0b89335c273874f89d35 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -25,13 +25,6 @@ */ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES -/* - * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too - */ -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES -#endif - #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 2c96378efef81b63b16e56ce92eb53bdaaa382b5..a97b72de1b8846eb33389034bd3e4039038d14b0 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -26,15 +26,6 @@ #endif #endif -/* Check if boards need to enable FSL DMA engine for SDRAM init */ -#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) -#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ - ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ - !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -#define CONFIG_FSL_DMA -#endif -#endif - /* * Provide a default boot page translation virtual address that lines up with * Freescale's default e500 reset page. diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 3b26451928a0f02ae4ee767ec8e6be592c7efd0c..5038cb9f590a7a6c4b8f29f713c713bf42e791ed 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -294,8 +294,8 @@ void lbc_sdram_init(void); #define LBCR_EPAR_SHIFT 16 #define LBCR_BMT 0x0000FF00 #define LBCR_BMT_SHIFT 8 -#define LBCR_BMTPS 0x0000000F -#define LBCR_BMTPS_SHIFT 0 +#define LBCR_BMTPS 0x0000000F +#define LBCR_BMTPS_SHIFT 0 /* LCRR - Clock Ratio Register */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index f539c0be71ed763b96e220eff997e6bca73e546e..770705a8794bd44fc875d2a0d1443e91bac297f7 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1510,7 +1510,7 @@ typedef struct par_io { */ typedef struct cpc_corenet { - u32 cpccsr0; /* Config/status reg */ + u32 cpccsr0; /* Config/status reg */ u32 res1; u32 cpccfg0; /* Configuration register */ u32 res2; @@ -1573,7 +1573,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a #define CPC_SRCR0_SRAMEN 0x00000001 -#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index e03ab21f59d5541722fb1b8356632bbee8ac03e4..19e63ebf38c5c5e3950c55e9012f94ac2e2d5f96 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -46,11 +46,7 @@ #define MSR_RI (1<<1) /* Recoverable Exception */ #define MSR_LE (1<<0) /* Little Endian */ -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI -#else #define MSR_ MSR_ME|MSR_RI -#endif #ifndef CONFIG_E500 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR #else @@ -752,7 +748,7 @@ #define MAS5 SPRN_MAS5 #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 -#define MAS8 SPRN_MAS8 +#define MAS8 SPRN_MAS8 #if defined(CONFIG_MPC85xx) #define DAR_DEAR DEAR diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 31c17b5bb388d9e5bc9e15762caf837839af64c3..8d65047aa4d48aa01bd73dba19b823d1a7aab082 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -119,7 +119,7 @@ static void boot_jump_linux(bootm_headers_t *images) void arch_lmb_reserve(struct lmb *lmb) { phys_size_t bootm_size; - ulong size, sp, bootmap_base; + ulong size, bootmap_base; bootmap_base = env_get_bootm_low(); bootm_size = env_get_bootm_size(); @@ -141,21 +141,7 @@ void arch_lmb_reserve(struct lmb *lmb) lmb_reserve(lmb, base, bootm_size - size); } - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug("## Current stack ends at 0x%08lx\n", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); #ifdef CONFIG_MP cpu_mp_lmb_reserve(lmb); diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index dcef1ffcaf578f23e9533fedc3dc65b9bb1690d6..e55025181f76fd4b9bdef79db46ddea29c049b99 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -104,4 +104,3 @@ _GLOBAL(invalidate_dcache_range) sync /* wait for dcbi's to get to ram */ #endif blr - diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ec651fe0a41d1d56bdeb3bc1416f8b5c479b10d0..ba29e70acf72979d4f89800d5183f14fcc62f437 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,9 +22,11 @@ config TARGET_SIFIVE_UNLEASHED config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" + select SYS_CACHE_SHIFT_6 config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" + select SYS_CACHE_SHIFT_6 config TARGET_OPENPITON_RISCV64 bool "Support RISC-V cores on OpenPiton SoC" @@ -33,7 +35,6 @@ endchoice config SYS_ICACHE_OFF bool "Do not enable icache" - default n help Do not enable instruction cache in U-Boot. @@ -46,7 +47,6 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" - default n help Do not enable data cache in U-Boot. diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 8dd18205403c6c5b00f131d4d57f61051323411f..ff1bdf71318baca7294a4b8d307276909d7920ba 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -135,3 +135,16 @@ int do_bootm_vxworks(int flag, int argc, char *const argv[], { return do_bootm_linux(flag, argc, argv, images); } + +static ulong get_sp(void) +{ + ulong ret; + + asm("mv %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 1103530941b3b4c8016d8c9018c7574ee3e7b603..b72dafca2ba602eb97088a6cbffdfc3e358f3fc2 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -133,6 +133,19 @@ int os_write_file(const char *fname, const void *buf, int size) return 0; } +int os_filesize(int fd) +{ + off_t size; + + size = os_lseek(fd, 0, OS_SEEK_END); + if (size < 0) + return -errno; + if (os_lseek(fd, 0, OS_SEEK_SET) < 0) + return -errno; + + return size; +} + int os_read_file(const char *fname, void **bufp, int *sizep) { off_t size; @@ -144,15 +157,12 @@ int os_read_file(const char *fname, void **bufp, int *sizep) printf("Cannot open file '%s'\n", fname); goto err; } - size = os_lseek(fd, 0, OS_SEEK_END); + size = os_filesize(fd); if (size < 0) { - printf("Cannot seek to end of file '%s'\n", fname); - goto err; - } - if (os_lseek(fd, 0, OS_SEEK_SET) < 0) { - printf("Cannot seek to start of file '%s'\n", fname); + printf("Cannot get file size of '%s'\n", fname); goto err; } + *bufp = os_malloc(size); if (!*bufp) { printf("Not enough memory to read file '%s'\n", fname); @@ -172,6 +182,35 @@ err: return ret; } +int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep) +{ + void *ptr; + int size; + int ifd; + + ifd = os_open(pathname, os_flags); + if (ifd < 0) { + printf("Cannot open file '%s'\n", pathname); + return -EIO; + } + size = os_filesize(ifd); + if (size < 0) { + printf("Cannot get file size of '%s'\n", pathname); + return -EIO; + } + + ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0); + if (ptr == MAP_FAILED) { + printf("Can't map file '%s': %s\n", pathname, strerror(errno)); + return -EPERM; + } + + *bufp = ptr; + *sizep = size; + + return 0; +} + /* Restore tty state when we exit */ static struct termios orig_term; static bool term_setup; @@ -690,7 +729,6 @@ static int add_args(char ***argvp, char *add_args[], int count) continue; } } else if (!strcmp(arg, "--rm_memory")) { - ap++; continue; } argv[argc++] = arg; diff --git a/arch/sandbox/dts/overlay0.dts b/arch/sandbox/dts/overlay0.dts index 70c6cf77aad53a9345ac8c2fd15aaebe00ee5573..9e5f38962bcabbdc3b09e8b03222ad67f945c725 100644 --- a/arch/sandbox/dts/overlay0.dts +++ b/arch/sandbox/dts/overlay0.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Overlay test file + */ + /dts-v1/; /plugin/; diff --git a/arch/sandbox/dts/overlay1.dts b/arch/sandbox/dts/overlay1.dts index 51621b31105a130ae7d20e8e48edc074388548be..303e713f336c68454d74bb90ef349dc5e4848c98 100644 --- a/arch/sandbox/dts/overlay1.dts +++ b/arch/sandbox/dts/overlay1.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Overlay test file + */ + /dts-v1/; /plugin/; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index a8938a3accb25275e8e137ac494adb946fe1a0cb..127f168f022bd4f5c3ad34a98a854052bcfff01b 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Main sandbox devicetree + */ + /dts-v1/; #include diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 200fcab6a41b854cf6eb759b1d33c1cd8fb2618b..66b813faadb8fc54591080814834a45d590386fc 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * This is the common sandbox device-tree nodes. This is shared between sandbox * and sandbox64 builds. @@ -65,7 +66,7 @@ }; gpio_b: gpios@1 { - u-boot,dm-pre-proper; + u-boot,dm-spl; gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <2>; @@ -73,6 +74,12 @@ sandbox,gpio-count = <10>; }; + gpio-test { + u-boot,dm-spl; + compatible = "sandbox,gpio-test"; + test-gpios = <&gpio_b 3 0>; + }; + hexagon { compatible = "demo-simple"; colour = "white"; @@ -123,6 +130,19 @@ #sound-dai-cells = <1>; }; + irq_sandbox: irq-sbox { + u-boot,dm-spl; + compatible = "sandbox,irq"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + irq-test { + u-boot,dm-spl; + compatible = "sandbox,irq-test"; + interrupts-extended = <&irq_sandbox 3 0>; + }; + lcd { u-boot,dm-pre-proper; compatible = "sandbox,lcd-sdl"; diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index a39f94feec0cd046ebf4f3d99ed0923b06ac1810..ec53106af9dca8cc0d0e941e135d275248e104a7 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -1,3 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Main sandbox64 devicetree + */ /dts-v1/; #include diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 962bdbe55670370ab8ed94cb8f865d9c21cd7eda..e27d106466b4dfca0638be4f9fdb136c2f0dfaa1 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1,3 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Devicetree file for running sandbox tests + * + * This includes lots of extra devices used by various tests. + * + * Note that SPL use the main sandbox.dts file + */ + /dts-v1/; #include @@ -53,6 +62,9 @@ }; config { + testing-bool; + testing-int = <123>; + testing-str = "testing"; environment { from_fdt = "yes"; fdt_env_path = ""; @@ -793,6 +805,13 @@ }; }; + gpio-wdt { + gpios = <&gpio_a 7 0>; + compatible = "linux,wdt-gpio"; + hw_margin_ms = <100>; + always-running; + }; + mbox: mbox { compatible = "sandbox,mbox"; #mbox-cells = <1>; @@ -805,19 +824,27 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; timebase-frequency = <2000000>; - cpu-test1 { + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; timebase-frequency = <3000000>; compatible = "sandbox,cpu_sandbox"; u-boot,dm-pre-reloc; }; - cpu-test2 { + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; compatible = "sandbox,cpu_sandbox"; u-boot,dm-pre-reloc; }; - cpu-test3 { + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; compatible = "sandbox,cpu_sandbox"; u-boot,dm-pre-reloc; }; @@ -1272,6 +1299,7 @@ wdt0: wdt@0 { compatible = "sandbox,wdt"; + hw_margin_ms = <200>; }; axi: axi@0 { diff --git a/arch/sandbox/include/asm/cache.h b/arch/sandbox/include/asm/cache.h index 9348a13e73dab15b82cd3952999247c6d0128280..609a835967b87cf6a62fc88ac62b5c613c3dfcff 100644 --- a/arch/sandbox/include/asm/cache.h +++ b/arch/sandbox/include/asm/cache.h @@ -19,6 +19,5 @@ #else #define ARCH_DMA_MINALIGN 16 #endif -#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN #endif /* __SANDBOX_CACHE_H__ */ diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index 9e10052667d40e6f6bfc770b6cb109871b237dcb..9542fdee67e45539eb62f4b61914a512663d18c4 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -65,7 +65,7 @@ int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); * * @param dev device to use * @param offset GPIO offset within bank - * @param output 0 to set as input, 1 to set as output + * @param output 0 to set as input, 1 to set as output * @return -1 on error, 0 if ok */ int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, diff --git a/arch/sandbox/include/asm/irq.h b/arch/sandbox/include/asm/irq.h new file mode 100644 index 0000000000000000000000000000000000000000..f73fec74f5c94e66f27b34cfba2d05fbff7e42bc --- /dev/null +++ b/arch/sandbox/include/asm/irq.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2021 Google LLC + */ + +#ifndef __SANDBOX_IRQ_H +#define __SANDBOX_IRQ_H + +/** + * struct sandbox_irq_priv - private data for this driver + * + * @count: Counts the number calls to the read_and_clear() method + * @pending: true if an interrupt is pending, else false + */ +struct sandbox_irq_priv { + int count; + bool pending; +}; + +#endif /* __SANDBOX_IRQ_H */ diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index dc94f8378566e957db8e412887b06fe9c98641f4..9b71424dfe60a009db9b86bc78ace8ae13dd3def 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -12,8 +12,11 @@ #include #include #include +#include #include +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_SYS_DEBUG static void hexdump(unsigned char *buf, int len) { @@ -111,3 +114,16 @@ int do_bootm_linux(int flag, int argc, char *const argv[], /* does not return */ return 1; } + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov r15, %0" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index f951544728547d18bad8d204bd984c99e5779aa9..366500d90bed5c1008be264296aa8f1ea2e91656 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -32,4 +32,3 @@ int timer_init(void) return 0; } - diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 300b48505e44942bef531b0cad653fdc35815733..b8d8ee30838bb719419922b7bff303e8a8a45396 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -146,14 +146,12 @@ config HPET_ADDRESS config SMM_TSEG bool - default n config SMM_TSEG_SIZE hex config X86_RESET_VECTOR bool - default n select BINMAN # The following options control where the 16-bit and 32-bit init lies @@ -490,7 +488,7 @@ config FSP_SYS_MALLOC_F_LEN config FSP_USE_UPD bool depends on FSP_VERSION1 - default y + default y if !NORTHBRIDGE_INTEL_IVYBRIDGE help Most FSPs use UPD data region for some FSP customization. But there are still some FSPs that might not even have UPD. For such FSPs, @@ -536,7 +534,6 @@ config HAVE_MRC config CACHE_MRC_BIN bool depends on HAVE_MRC - default n help Enable caching for the memory reference code binary. This uses an MTRR (memory type range register) to turn on caching for the section @@ -605,7 +602,6 @@ config HAVE_MICROCODE config SMP bool "Enable Symmetric Multiprocessing" - default n help Enable use of more than one CPU in U-Boot and the Operating System when loaded. Each CPU will be started up and information can be @@ -745,7 +741,6 @@ menu "System tables" config GENERATE_PIRQ_TABLE bool "Generate a PIRQ table" - default n help Generate a PIRQ routing table for this board. The PIRQ routing table is generated by U-Boot in the system memory from 0xf0000 to 0xfffff @@ -769,7 +764,6 @@ config GENERATE_SFI_TABLE config GENERATE_MP_TABLE bool "Generate an MP (Multi-Processor) table" - default n help Generate an MP (Multi-Processor) table for this board. The MP table provides a way for the operating system to support for symmetric @@ -778,7 +772,6 @@ config GENERATE_MP_TABLE config GENERATE_ACPI_TABLE bool "Generate an ACPI (Advanced Configuration and Power Interface) table" - default n select QFW if QEMU help The Advanced Configuration and Power Interface (ACPI) specification diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index b3ce053173a81199000ddcafcbc1221cf5f84564..c7f26d171cb0374e431020b796becfc56fa9fd8b 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -12,10 +12,10 @@ config INTEL_APOLLOLAKE select INTEL_SOC select INTEL_PMC select TPL_X86_TSC_TIMER_NATIVE - select SPL_PCH_SUPPORT - select TPL_PCH_SUPPORT + select SPL_PCH + select TPL_PCH select PCIEX_LENGTH_256MB - select PCH_SUPPORT + select PCH select P2SB select SMP_AP_WORK select INTEL_GMA_SWSMISCI @@ -88,7 +88,7 @@ config CPU_ADDR_BITS config APL_SPI_FLASH_BOOT bool "Support booting with SPI-flash driver instead memory-mapped SPI" select TPL_SPI_FLASH_SUPPORT - select TPL_SPI_SUPPORT + select TPL_SPI select TPL_DM_SPI select TPL_DM_SPI_FLASH help diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 9decab7aa332f18f70ac9a3334c8f7a9262f7114..2405dec8525b1af4e3d5aa93164844b4a833de62 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -220,7 +220,7 @@ static int apl_hostbridge_of_to_plat(struct udevice *dev) ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); if (ret) return log_msg_ret("no hostbridge PINCTRL", ret); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int root; /* Get length of PCI Express Region */ @@ -375,7 +375,7 @@ struct acpi_ops apl_hostbridge_acpi_ops = { #endif }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_hostbridge_ids[] = { { .compatible = "intel,apl-hostbridge" }, { } diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index e085890d638d766e664bc1497a8c4e3018bded7c..4be6366f0438fcfc807dd9ce94109194e58e4c98 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -128,7 +128,7 @@ struct acpi_ops apl_lpc_acpi_ops = { .inject_dsdt = southbridge_inject_dsdt, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_lpc_ids[] = { { .compatible = "intel,apl-lpc" }, { } diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index 39d6ad5ed49aa39aaeb9417dc13cb7991fc292ce..a0f9b031dea31d74f129ec3c0e2249648f595bfd 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -23,7 +23,7 @@ static const struct pch_ops apl_pch_ops = { .set_spi_protect = apl_set_spi_protect, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_pch_ids[] = { { .compatible = "intel,apl-pch" }, { } diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 1d21187c96d23926a201ec6de52e342632e1d230..163119e2e9e9c706d088f9fb17576bb3047cf43b 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -107,7 +107,7 @@ int apl_pmc_ofdata_to_uc_plat(struct udevice *dev) struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); struct apl_pmc_plat *plat = dev_get_plat(dev); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) u32 base[6]; int size; int ret; @@ -206,7 +206,7 @@ static const struct acpi_pmc_ops apl_pmc_ops = { .global_reset_set_enable = apl_global_reset_set_enable, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_pmc_ids[] = { { .compatible = "intel,apl-pmc" }, { } diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c index 876fa592b8d999a3c13ff10cdbba96121764e6c3..a9362436000cd1e90c12f6c27e7bce2ea88027e1 100644 --- a/arch/x86/cpu/apollolake/uart.c +++ b/arch/x86/cpu/apollolake/uart.c @@ -123,7 +123,7 @@ static int apl_ns16550_of_to_plat(struct udevice *dev) return 0; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_ns16550_serial_ids[] = { { .compatible = "intel,apl-ns16550" }, { }, diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 69cf8f417c713ad4af0035fc5f665dae0ce8c5ba..aaa5ae112e4546be099c9caf4d3d5f450cafe3ef 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -16,8 +16,7 @@ #include #include #include - -DECLARE_GLOBAL_DATA_PTR; +#include int arch_cpu_init(void) { @@ -65,7 +64,7 @@ static void board_final_init(void) mtrr_close(&state, true); } - if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) { + if (!ofnode_conf_read_bool("u-boot,no-apm-finalize")) { /* * Issue SMI to coreboot to lock down ME and registers * when allowed via device tree diff --git a/arch/x86/cpu/intel_common/car2.S b/arch/x86/cpu/intel_common/car2.S index 086f987477eee774fd81a3a8d29dee322fbc130b..f8cf78586d020864e92eab242d65a5335977995a 100644 --- a/arch/x86/cpu/intel_common/car2.S +++ b/arch/x86/cpu/intel_common/car2.S @@ -88,7 +88,7 @@ clear_var_mtrr: * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing */ - movl $0x80000008, %eax /* Address sizes leaf */ + movl $0x80000008, %eax /* Address sizes leaf */ cpuid sub $32, %al movzx %al, %eax diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index 1eff0309831432ac0735b03072ea93b9ac3e3979..ec73b3d89312adc5d1d4b08e28b1dc0d63841dc4 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -213,7 +213,7 @@ static const struct irq_ops itss_ops = { #endif }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id itss_ids[] = { { .compatible = "intel,itss", .data = X86_IRQT_ITSS }, { } diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index d73ae438bbb07f4de7c6f888d0c269c16fb5dca1..5a7b30d94a1f75d5b57afc27b83ad6df57e704fc 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -88,7 +88,7 @@ int p2sb_of_to_plat(struct udevice *dev) struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); struct p2sb_plat *plat = dev_get_plat(dev); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int ret; u32 base[2]; @@ -159,16 +159,16 @@ static int p2sb_remove(struct udevice *dev) static int p2sb_child_post_bind(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); - int ret; - u32 pid; - - ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); - if (ret) - return ret; - pplat->pid = pid; -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; + } return 0; } @@ -177,7 +177,7 @@ static const struct p2sb_ops p2sb_ops = { .set_hide = intel_p2sb_set_hide, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id p2sb_ids[] = { { .compatible = "intel,p2sb" }, { } diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 2f423937864230cc866fa8cdf593262eec247bb1..be3ef5e5d8f8a8d5d9c439decc0d14c63e6261fa 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -45,7 +45,6 @@ config SMM_TSEG_SIZE config ENABLE_VMX bool "Enable VMX for virtualization" - default n help Virtual Machine Extensions are provided in many x86 CPUs. These provide various facilities for allowing a host OS to provide an @@ -64,10 +63,6 @@ config FSP_ADDR hex default 0xfff80000 -config FSP_USE_UPD - bool - default n - config FSP_BROKEN_HOB bool default y diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index 3e8c0bc28c5f540701b2885efe08352508c4cecd..ce3c2b8ab426e8f811adaee99ce017d1a3acbd35 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -33,7 +33,6 @@ */ #include -#include #include #include #include "mrc_util.h" @@ -191,8 +190,7 @@ void mrc_init(struct mrc_params *mrc_params) { ENTERFN(); - DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION, - U_BOOT_DATE, U_BOOT_TIME); + DPF(D_INFO, "MRC Version %04x\n", MRC_VERSION); /* Set up the data structures used by mrc_mem_init() */ mrc_adjust_params(mrc_params); diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h index 145b8784de1eb50ca3bd0527725bda275ad79343..256a3c01ed98f1b571582421db8c8462a449c62f 100644 --- a/arch/x86/include/asm/cache.h +++ b/arch/x86/include/asm/cache.h @@ -7,13 +7,8 @@ #define __X86_CACHE_H__ /* - * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise - * use 64-bytes, a safe default for x86. + * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment. */ -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 64 -#endif - #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE static inline void wbinvd(void) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 5ec31301d0b8751773e326099a2e0f4eae3a0d49..3f847711e2be8d58e0e94449b7739ed13b1e8eb7 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S index 62dc5652dbab4944a3f000de5f821b411d672fdc..9e2a02658ba82a8b37218d036df802d4bad71f30 100644 --- a/arch/x86/lib/bios_asm.S +++ b/arch/x86/lib/bios_asm.S @@ -22,8 +22,8 @@ .globl __idt_handler __idt_handler: pushal - movb $0, %al /* This instruction gets modified */ - ljmp $0, $__interrupt_handler_16bit + movb $0, %al /* This instruction gets modified */ + ljmp $0, $__interrupt_handler_16bit .globl __idt_handler_size __idt_handler_size: .long . - __idt_handler diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 733dd71257062c89689859941b77fcd5541444f8..667e5e689e35435305d8cf18ef446a83211f9abe 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -223,3 +223,21 @@ int do_bootm_linux(int flag, int argc, char *const argv[], return boot_jump_linux(images); } + +static ulong get_sp(void) +{ + ulong ret; + +#if CONFIG_IS_ENABLED(X86_64) + ret = gd->start_addr_sp; +#else + asm("mov %%esp, %0" : "=r"(ret) : ); +#endif + + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index 1302a6e34a144a9f3441ae92d7ecce9768b00666..67b931d3b28966ae6301a64fa0241f66181f630b 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -10,7 +10,7 @@ UCLASS_DRIVER(lpc) = { .id = UCLASS_LPC, .name = "lpc", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index b3e5f9c9138a46ce4702670a57482a479ea96b48..5b57e53c2ddf1b1db37e41b25f8f7519777eb5af 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -139,7 +139,7 @@ void spl_board_init(void) * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does * the auto allocation (after relocation). */ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id tpl_fake_pci_ids[] = { { .compatible = "pci-x86" }, { } diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 6de31e8c1e05d0e94bb099a8bd74d5102bf5dc3d..35e5b89dda047fcd5e059ba65c1ae36cff4a84fe 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -18,7 +18,6 @@ endchoice config SYS_ICACHE_OFF bool "Do not enable icache" - default n help Do not enable instruction cache in U-Boot. @@ -31,7 +30,6 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" - default n help Do not enable data cache in U-Boot. diff --git a/arch/xtensa/include/asm/arch-dc232b/core.h b/arch/xtensa/include/asm/arch-dc232b/core.h index c50a358c52263beba847243f087e2d26116223f9..c1453f719e44e6db35817687cc927248aa93e207 100644 --- a/arch/xtensa/include/asm/arch-dc232b/core.h +++ b/arch/xtensa/include/asm/arch-dc232b/core.h @@ -127,8 +127,6 @@ #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ - - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ @@ -419,4 +417,3 @@ #endif /* _XTENSA_CORE_CONFIGURATION_H */ - diff --git a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h index 05ce1107f5a3d008189ee70ed99669801b987cdd..35a26dca7cc39316fe4f78ef496ec8d25aaaef55 100644 --- a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h +++ b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h @@ -26,7 +26,6 @@ #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ - /* Macro to save all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). * Save area ptr (clobbered): ptr (1 byte aligned) @@ -109,12 +108,8 @@ .endif .endm // xchal_ncp_load - - #define XCHAL_NCP_NUM_ATMPS 2 - #define XCHAL_SA_NUM_ATMPS 2 #endif /*_XTENSA_CORE_TIE_ASM_H*/ - diff --git a/arch/xtensa/include/asm/arch-dc232b/tie.h b/arch/xtensa/include/asm/arch-dc232b/tie.h index 2e70311d3e4d80cbf197400d449d6e770a4fd9d5..4f8b50cd6cd6f811d989b75f6a133d6846c79cff 100644 --- a/arch/xtensa/include/asm/arch-dc232b/tie.h +++ b/arch/xtensa/include/asm/arch-dc232b/tie.h @@ -126,4 +126,3 @@ #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 #endif /*_XTENSA_CORE_TIE_H*/ - diff --git a/arch/xtensa/include/asm/arch-dc233c/core.h b/arch/xtensa/include/asm/arch-dc233c/core.h index 8a7345559c2e975a88cad28314c2607415e09491..cd3c8c115f5083522c1fc6aad293434b7a327e64 100644 --- a/arch/xtensa/include/asm/arch-dc233c/core.h +++ b/arch/xtensa/include/asm/arch-dc233c/core.h @@ -149,13 +149,10 @@ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ - - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ - #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- @@ -266,28 +263,28 @@ EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI -#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE /* Masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 @@ -450,4 +447,3 @@ #endif /* _XTENSA_CORE_CONFIGURATION_H */ - diff --git a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h index 53a1e42a7457702c3b5bf74c6f3cae17ef3b4fda..7b3d1f3c57251a12846ebafe9c20f81aab10b738 100644 --- a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h +++ b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h @@ -31,8 +31,6 @@ | ((ccuse) & XTHAL_SAS_ANYCC) \ | ((abi) & XTHAL_SAS_ANYABI) ) - - /* * Macro to save all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). @@ -164,9 +162,6 @@ #define XCHAL_NCP_NUM_ATMPS 1 - - #define XCHAL_SA_NUM_ATMPS 1 #endif /*_XTENSA_CORE_TIE_ASM_H*/ - diff --git a/arch/xtensa/include/asm/arch-dc233c/tie.h b/arch/xtensa/include/asm/arch-dc233c/tie.h index ddee4ad3f6eab842a4b384b073d6c0bde182ba9e..2c2a8493cd5b8676067d9fe0007a4c6497379ca8 100644 --- a/arch/xtensa/include/asm/arch-dc233c/tie.h +++ b/arch/xtensa/include/asm/arch-dc233c/tie.h @@ -126,4 +126,3 @@ #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 #endif /*_XTENSA_CORE_TIE_H*/ - diff --git a/arch/xtensa/include/asm/arch-de212/core.h b/arch/xtensa/include/asm/arch-de212/core.h index 7e94339e6d9143fed74f2f1d4b3aa6a0838a1ca5..60c6efba7d23c5dda1c75dd3574454fff3d9e454 100644 --- a/arch/xtensa/include/asm/arch-de212/core.h +++ b/arch/xtensa/include/asm/arch-de212/core.h @@ -89,7 +89,7 @@ #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ -#define XCHAL_HAVE_HIFI_MINI 0 +#define XCHAL_HAVE_HIFI_MINI 0 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ @@ -108,8 +108,8 @@ #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ -#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ -#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_PDX4 0 /* PDX4 */ @@ -127,8 +127,8 @@ #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ -#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ /*---------------------------------------------------------------------- @@ -206,13 +206,10 @@ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ - - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ - #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- @@ -351,28 +348,28 @@ EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI -#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE /* Masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 @@ -569,4 +566,3 @@ #endif /* _XTENSA_CORE_CONFIGURATION_H */ - diff --git a/arch/xtensa/include/asm/arch-de212/tie-asm.h b/arch/xtensa/include/asm/arch-de212/tie-asm.h index 988aa2ba578e8c19433e5ea3b3cd95198bc0913d..3192ac82ad2064c07f59c4b410c03a3e0f6ea715 100644 --- a/arch/xtensa/include/asm/arch-de212/tie-asm.h +++ b/arch/xtensa/include/asm/arch-de212/tie-asm.h @@ -146,4 +146,3 @@ #define XCHAL_SA_NUM_ATMPS 1 #endif /*_XTENSA_CORE_TIE_ASM_H*/ - diff --git a/arch/xtensa/include/asm/arch-de212/tie.h b/arch/xtensa/include/asm/arch-de212/tie.h index 2f36493d8850f6019834405363d41c2db90469e9..865c41c128d54cbc528d56aad7520c8a825006b1 100644 --- a/arch/xtensa/include/asm/arch-de212/tie.h +++ b/arch/xtensa/include/asm/arch-de212/tie.h @@ -112,4 +112,3 @@ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 #endif /*_XTENSA_CORE_TIE_H*/ - diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 6d321f886609944b39bccf17b1ed72f2fb474067..69448cfff783210c2d929147ce2ad394d62969fa 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -134,7 +134,6 @@ .endm - .macro ___flush_invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE @@ -171,7 +170,6 @@ .endm - .macro ___flush_invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h index 32b50f95114cba3355106be0b8a35c86b5e6fec7..52d6e8cc0143c632f61830d8986e26b3a8bb1e7e 100644 --- a/arch/xtensa/include/asm/regs.h +++ b/arch/xtensa/include/asm/regs.h @@ -91,4 +91,3 @@ #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */ #endif /* _XTENSA_SPECREG_H */ - diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile index c59df7d37215c83cf81624396e6a5caf61ae930f..ad4fe32cb69908e994137f415013b25124fa7ed3 100644 --- a/arch/xtensa/lib/Makefile +++ b/arch/xtensa/lib/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o -obj-y += cache.o misc.o relocate.o time.o +obj-y += cache.o misc.o relocate.o time.o diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index bb1e2886abc785d54d23389f3ddc1b38b8c74938..277af1816833750320f999c30409fd5bafd7c8a7 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -197,3 +197,15 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) return 1; } +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, a1" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); +} diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c index 91141f581e135969211fe667db81a0700e702974..3dc8edc801d7721f946bb4824c0129a41f080b1a 100644 --- a/arch/xtensa/lib/relocate.c +++ b/arch/xtensa/lib/relocate.c @@ -14,4 +14,3 @@ int clear_bss(void) memset((void *)&__bss_start, 0x00, len); return 0; } - diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 81b0ee99237260c16d100db6062461a7b8e32b8b..15da58a314536f423294673084b23415a047d8a9 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -109,7 +109,7 @@ void board_boot_order(u32 *spl_boot_list) #ifdef CONFIG_SPL_RAM_SUPPORT BOOT_DEVICE_RAM, #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC BOOT_DEVICE_MMC1, #endif }; diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig deleted file mode 100644 index 7113f2b51f6a263cbe7ecb734ab24b2717e3789c..0000000000000000000000000000000000000000 --- a/board/CarMediaLab/flea3/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FLEA3 - -config SYS_BOARD - default "flea3" - -config SYS_VENDOR - default "CarMediaLab" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "flea3" - -endif diff --git a/board/CarMediaLab/flea3/MAINTAINERS b/board/CarMediaLab/flea3/MAINTAINERS deleted file mode 100644 index c7b0df7bc4292d184027f52e484c4ce0bf5f8ca0..0000000000000000000000000000000000000000 --- a/board/CarMediaLab/flea3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FLEA3 BOARD -M: Stefano Babic -S: Maintained -F: board/CarMediaLab/flea3/ -F: include/configs/flea3.h -F: configs/flea3_defconfig diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile deleted file mode 100644 index edaac8683b360f06dea46f202cff7f201cb12fce..0000000000000000000000000000000000000000 --- a/board/CarMediaLab/flea3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y := flea3.o -obj-y += lowlevel_init.o diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c deleted file mode 100644 index 12c5ac331f9729a3b2d6f6e19f5cac0c08cfee79..0000000000000000000000000000000000000000 --- a/board/CarMediaLab/flea3/flea3.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011, Stefano Babic - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif - -#define CCM_CCMR_CONFIG 0x003F4208 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F - -static inline void dram_wait(unsigned int count) -{ - volatile unsigned int wait = count; - - while (wait--) - ; -} - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -static void board_setup_sdram(void) -{ - struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; - - /* Initialize with default values both CSD0/1 */ - writel(0x2000, &esdc->esdctl0); - writel(0x2000, &esdc->esdctl1); - - - mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, - 13, 10, 2, 0x8080); -} - -static void setup_iomux_uart3(void) -{ - static const iomux_v3_cfg_t uart3_pads[] = { - MX35_PAD_RTS2__UART3_RXD_MUX, - MX35_PAD_CTS2__UART3_TXD_MUX, - }; - - imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); -} - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - - NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - - -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SS0__CSPI1_SS0, - MX35_PAD_CSPI1_SS1__CSPI1_SS1, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* GPIO used to power off ethernet */ - MX35_PAD_STXFS4__GPIO2_31, - }; - - /* setup pins for FEC */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -int board_early_init_f(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - /* setup GPIO3_1 to set HighVCore signal */ - imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); - gpio_direction_output(65, 1); - - /* initialize PLL and clock configuration */ - writel(CCM_CCMR_CONFIG, &ccm->ccmr); - - writel(CCM_MPLL_532_HZ, &ccm->mpctl); - writel(CCM_PPLL_300_HZ, &ccm->ppctl); - - /* Set the core to run at 532 Mhz */ - writel(0x00001000, &ccm->pdr0); - - /* Set-up RAM */ - board_setup_sdram(); - - /* enable clocks */ - writel(readl(&ccm->cgr0) | - MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDIO_MASK | - MXC_CCM_CGR0_EPIT1_MASK, - &ccm->cgr0); - - writel(readl(&ccm->cgr1) | - MXC_CCM_CGR1_FEC_MASK | - MXC_CCM_CGR1_GPIO1_MASK | - MXC_CCM_CGR1_GPIO2_MASK | - MXC_CCM_CGR1_GPIO3_MASK | - MXC_CCM_CGR1_I2C1_MASK | - MXC_CCM_CGR1_I2C2_MASK | - MXC_CCM_CGR1_I2C3_MASK, - &ccm->cgr1); - - /* Set-up NAND */ - __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); - - /* Set pinmux for the required peripherals */ - setup_iomux_uart3(); - setup_iomux_i2c(); - setup_iomux_fec(); - setup_iomux_spi(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* Enable power for ethernet */ - gpio_direction_output(63, 0); - - udelay(2000); - - return 0; -} - -u32 get_board_rev(void) -{ - int rev = 0; - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -/* - * called prior to booting kernel or by 'fdt boardsetup' command - * - */ -int ft_board_setup(void *blob, struct bd_info *bd) -{ - static const struct node_info nodes[] = { - { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */ - { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ - }; - - if (env_get("fdt_noauto")) { - puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); - return 0; - } - - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - - return 0; -} diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S deleted file mode 100644 index 8186b3922bad5e034ba738098e0b5d6ad01838cb..0000000000000000000000000000000000000000 --- a/board/CarMediaLab/flea3/lowlevel_init.S +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011, Stefano Babic - */ - -#include -#include - -.globl lowlevel_init -lowlevel_init: - - core_init - - init_aips - - init_max - - init_m3if - - mov pc, lr diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 730eab7e703102f9a02880052f4b5bd7fc6c8745..22bb008745e1f616fa9cbbd16684bcf95714d816 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -73,8 +73,10 @@ int board_early_init_f(void) int board_init(void) { +#ifdef CONFIG_MACH_TYPE /* Machine number */ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; +#endif /* Boot parameters address */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig deleted file mode 100644 index 4dd49c4452b99d2ce4fb37cb0ef6024500a81d75..0000000000000000000000000000000000000000 --- a/board/Marvell/aspenite/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASPENITE - -config SYS_BOARD - default "aspenite" - -config SYS_VENDOR - default "Marvell" - -config SYS_SOC - default "armada100" - -config SYS_CONFIG_NAME - default "aspenite" - -endif diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS deleted file mode 100644 index a77d30eb78ce3e1a842ded171efe2bd7d8fa75f7..0000000000000000000000000000000000000000 --- a/board/Marvell/aspenite/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ASPENITE BOARD -M: Prafulla Wadaskar -S: Maintained -F: board/Marvell/aspenite/ -F: include/configs/aspenite.h -F: configs/aspenite_defconfig diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile deleted file mode 100644 index f67a978a12bc35664d4ec7e56be79e0cf0dfbdc1..0000000000000000000000000000000000000000 --- a/board/Marvell/aspenite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# Contributor: Mahavir Jain - -obj-y := aspenite.o diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c deleted file mode 100644 index 1f9389c0a7abeeddb0ecf3a3903a43a2c14cf76c..0000000000000000000000000000000000000000 --- a/board/Marvell/aspenite/aspenite.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u32 mfp_cfg[] = { - /* I2C */ - MFP105_CI2C_SDA, - MFP106_CI2C_SCL, - - /* Enable Console on UART1 */ - MFP107_UART1_RXD, - MFP108_UART1_TXD, - - MFP_EOC /*End of configureation*/ - }; - /* configure MFP's */ - mfp_config(mfp_cfg); - return 0; -} - -int board_init(void) -{ - /* arch number of Board */ - gd->bd->bi_arch_number = MACH_TYPE_ASPENITE; - /* adress of boot parameters */ - gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; - return 0; -} diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 8e7dbb3f3f60a55d076e428fd7a4495c760aaf24..ea87ded222e60b280b1cb3a3cf744ee1f825057f 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -77,7 +77,7 @@ int board_early_init_f(void) MPP43_GPIO, MPP44_GPIO, MPP45_GPIO, - MPP46_GPIO, /* M_RLED */ + MPP46_GPIO, /* M_RLED */ MPP47_GPIO, /* M_GLED */ MPP48_GPIO, /* B_RLED */ MPP49_GPIO, /* B_GLED */ diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c index 9aac5f0b09f554d7efaa2282504dea5e9696e1b8..e8e2d547c1ee029b7710066a72bd977c36840235 100644 --- a/board/Marvell/octeon_ebb7304/board.c +++ b/board/Marvell/octeon_ebb7304/board.c @@ -339,7 +339,7 @@ void __fixup_fdt(void) case CVMX_QLM_MODE_XFI: case CVMX_QLM_MODE_RGMII_XFI: case CVMX_QLM_MODE_RGMII_XFI_1X1: - type_str = "xfi"; + type_str = "10gbase-r"; break; case CVMX_QLM_MODE_10G_KR: case CVMX_QLM_MODE_RGMII_10G_KR: @@ -393,7 +393,7 @@ void __fixup_fdt(void) if (pmd_control.s.train_en) type_str = "10G_KR"; else - type_str = "xfi"; + type_str = "10gbase-r"; break; case 4: if (pmd_control.s.train_en) @@ -618,7 +618,7 @@ static void board_configure_qlms(void) speed[qlm] = 103125; } printf("QLM %d: XLAUI\n", qlm); - } else if (!strncmp(mode_str, "xfi", 3)) { + } else if (!strncmp(mode_str, "10gbase-r", 3)) { bool rgmii = false; speed[qlm] = 103125; diff --git a/board/Marvell/octeontx/smc.c b/board/Marvell/octeontx/smc.c index 5eeba2358b07d9440d8776ba3eec7d95bb06bbc9..8df32049bda69e99cf28c0dd78e372cc94790d4d 100644 --- a/board/Marvell/octeontx/smc.c +++ b/board/Marvell/octeontx/smc.c @@ -22,4 +22,3 @@ ssize_t smc_dram_size(unsigned int node) return regs.regs[0]; } - diff --git a/board/Marvell/octeontx2/soc-utils.c b/board/Marvell/octeontx2/soc-utils.c index 1cba7fb5963f7749144e20ee340a4a9612944ade..43a19a90717ca70278596a7b35b58212b61bba04 100644 --- a/board/Marvell/octeontx2/soc-utils.c +++ b/board/Marvell/octeontx2/soc-utils.c @@ -46,4 +46,3 @@ const char *read_board_name(void) { return fdt_get_board_model(); } - diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile index 62354cc2e82e68ffad8dbf26a3867d407b1b6e98..f688b5490631c980e742a5798d273c26a8651416 100644 --- a/board/Synology/common/Makefile +++ b/board/Synology/common/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2021 Phil Sutter -obj-y += legacy.o +obj-$(SUPPORT_PASSING_ATAGS) += legacy.o diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index 3c89e92ae7382aa75330e529764d1fb6c4a6fcb7..06f964f53a3bb2fdf1e02612488688934de70374 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -15,14 +15,15 @@ static unsigned int syno_board_id(void) { +#ifdef CONFIG_MACH_TYPE switch (CONFIG_MACH_TYPE) { case 527: return SYNO_DS109_ID; case 3036: return SYNO_AXP_4BAY_2BAY; - default: - return 0; } +#endif + return 0; } static unsigned int usb_port_modes(void) diff --git a/board/advantech/imx8qm_rom7720_a1/Kconfig b/board/advantech/imx8qm_rom7720_a1/Kconfig index cf3869ed9286e01acb474b27a6677ba359e95d4c..8bf3a7d34846981e75e8f08acd3973ebec59051d 100644 --- a/board/advantech/imx8qm_rom7720_a1/Kconfig +++ b/board/advantech/imx8qm_rom7720_a1/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8qm_rom7720" +config IMX_CONFIG + default "board/advantech/imx8qm_rom7720_a1/imximage.cfg" + source "board/freescale/common/Kconfig" endif diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index 8493bb01588d2c3a4f391ff4a44ba9e9e69630fa..5fd60212df9caad87b830f412b91302aa5fbd763 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -172,7 +172,7 @@ int board_mmc_getcd(struct mmc *mmc) void spl_board_init(void) { -#if defined(CONFIG_SPL_SPI_SUPPORT) +#if defined(CONFIG_SPL_SPI) if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) { puts("Warning: failed to initialize FSPI0\n"); @@ -185,7 +185,7 @@ void spl_board_init(void) void spl_board_prepare_for_boot(void) { -#if defined(CONFIG_SPL_SPI_SUPPORT) +#if defined(CONFIG_SPL_SPI) if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) { puts("Warning: failed to turn off FSPI0\n"); diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index 7bcfa828d7ca891e6e672998b991f5f3b06a87df..8b31045a0743c83bb7b0e717d253bb83952ca410 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -121,9 +121,8 @@ int board_init(void) void arch_preboot_os(void) { -#ifdef CONFIG_WATCHDOG - wdt_stop(gd->watchdog_dev); -#endif + if (CONFIG_IS_ENABLED(WDT)) + wdt_stop_all(); } static int led_7seg_init(unsigned int segments) diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index cc603c1bc2d190536027ea9928bd3ae4d5a6c96e..2d8fcc513f8033e6d24c94762f7c4b91a30a67d1 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -8,6 +8,9 @@ config SYS_BOARD config SYS_BOARD_VERSION default 5 +config IMX_CONFIG + default "board/aristainetos/aristainetos2.cfg" + endif if TARGET_ARISTAINETOS2CCSLB @@ -20,4 +23,7 @@ config SYS_BOARD config SYS_BOARD_VERSION default 6 +config IMX_CONFIG + default "board/aristainetos/aristainetos2.cfg" + endif diff --git a/board/armadeus/opos6uldev/Kconfig b/board/armadeus/opos6uldev/Kconfig index e66f060d140e7f81e3ca2c5c86a4c3e6eaa2f68b..2a96c0044b44833827d05c9db834c092d0aacee1 100644 --- a/board/armadeus/opos6uldev/Kconfig +++ b/board/armadeus/opos6uldev/Kconfig @@ -9,7 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "opos6uldev" -config IMX_CONFIG - default "arch/arm/mach-imx/spl_sd.cfg" - endif diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..1b0dcf96696f7e9bb7f6405418bae63f183db8cb --- /dev/null +++ b/board/armltd/vexpress/Kconfig @@ -0,0 +1,12 @@ +if TARGET_VEXPRESS_CA9X4 + +config SYS_BOARD + default "vexpress" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_ca9x4" + +endif diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..2b3e4916a5d05ab4b2c2d5360d404b48a8e4607b --- /dev/null +++ b/board/armltd/vexpress/MAINTAINERS @@ -0,0 +1,6 @@ +VERSATILE EXPRESS BOARDS +M: Kristian Amlie +S: Maintained +F: board/armltd/vexpress/ +F: include/configs/vexpress_ca9x4.h +F: configs/vexpress_ca9x4_defconfig diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/board/armltd/vexpress/Makefile similarity index 56% rename from arch/arm/cpu/arm926ejs/mx25/Makefile rename to board/armltd/vexpress/Makefile index ac5ebaf5ef8c7739c602ccbb5e4e59adc312ff1e..84804f5ce783cdfc23c9f5d824b349d3bd768d61 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/board/armltd/vexpress/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -obj-y += generic.o timer.o reset.o relocate.o +obj-y := vexpress_common.o diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c new file mode 100644 index 0000000000000000000000000000000000000000..1c830192653122315c8a61c43db149d7acd9a11d --- /dev/null +++ b/board/armltd/vexpress/vexpress_common.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; +static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; + +static void flash__init(void); +static void vexpress_timer_init(void); +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay(ulong loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; + + icache_enable(); + flash__init(); + vexpress_timer_init(); + + return 0; +} + +static void flash__init(void) +{ + /* Setup the sytem control register to allow writing to flash */ + writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, + &sysctrl_base->scflashctrl); +} + +int dram_init(void) +{ + gd->ram_size = + get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = + get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + return 0; +} + +/* + * Start timer: + * Setup a 32 bit timer, running at 1KHz + * Versatile Express Motherboard provides 1 MHz timer + */ +static void vexpress_timer_init(void) +{ + /* + * Set clock frequency in system controller: + * VEXPRESS_REFCLK is 32KHz + * VEXPRESS_TIMCLK is 1MHz + */ + writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | + SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | + readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); + + /* + * Set Timer0 to be: + * Enabled, free running, no interrupt, 32-bit, wrapping + */ + writel(SYSTIMER_RELOAD, &systimer_base->timer0load); + writel(SYSTIMER_RELOAD, &systimer_base->timer0value); + writel(SYSTIMER_EN | SYSTIMER_32BIT | + readl(&systimer_base->timer0control), + &systimer_base->timer0control); +} + +int v2m_cfg_write(u32 devfn, u32 data) +{ + /* Configuration interface broken? */ + u32 val; + + devfn |= SYS_CFG_START | SYS_CFG_WRITE; + + val = readl(V2M_SYS_CFGSTAT); + writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); + + writel(data, V2M_SYS_CFGDATA); + writel(devfn, V2M_SYS_CFGCTRL); + + do { + val = readl(V2M_SYS_CFGSTAT); + } while (val == 0); + + return !!(val & SYS_CFG_ERR); +} + +/* Use the ARM Watchdog System to cause reset */ +void reset_cpu(void) +{ + if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) + printf("Unable to reboot\n"); +} + +void lowlevel_init(void) +{ +} + +ulong get_board_rev(void){ + return readl((u32 *)SYS_ID); +} + +#ifdef CONFIG_ARMV7_NONSEC +/* Setting the address at which secondary cores start from. + * Versatile Express uses one address for all cores, so ignore corenr + */ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + /* The SYSFLAGS register on VExpress needs to be cleared first + * by writing to the next address, since any writes to the address + * at offset 0 will only be ORed in + */ + writel(~0, CONFIG_SYSFLAGS_ADDR + 4); + writel(addr, CONFIG_SYSFLAGS_ADDR); +} +#endif diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile index 87e8ca5e6af1ff29448436bbd128a700f1d877e3..7e01cb6794a0e7c2e9281bbd0cb961e318f12dcf 100644 --- a/board/atmark-techno/armadillo-800eva/Makefile +++ b/board/atmark-techno/armadillo-800eva/Makefile @@ -3,4 +3,3 @@ # Copyright (C) 2012 Nobuhiro Iwamatsu obj-y += armadillo-800eva.o - diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 1b7d946b50c36b87c16553c1a6e5ed397076b564..8c0cf3da54ba3aa6538dbde13cd5295d8353a64e 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -68,7 +69,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; #ifdef CONFIG_CMD_USB board_usb_hw_init(); @@ -77,11 +78,14 @@ int board_init(void) return 0; } +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; + return fdtdec_setup_mem_size_base(); } #define MAC24AA_MAC_OFFSET 0xfa diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS index db984b6ae479610ec6017133cc493a00e48dab86..4a65c65ec3b8639f2f7dba797a26cf9d0bec6f29 100644 --- a/board/atmel/sama5d2_icp/MAINTAINERS +++ b/board/atmel/sama5d2_icp/MAINTAINERS @@ -4,4 +4,5 @@ S: Maintained F: board/atmel/sama5d2_icp/ F: include/configs/sama5d2_icp.h F: configs/sama5d2_icp_mmc_defconfig +F: configs/sama5d2_icp_qspiflash_defconfig diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index a6937e7d5243de5b56e8d7fcdd7fe66365fb98b7..2a2439c53ae45e0006931ac276fd1c82fadcd1d6 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 5110ec89697f6eebd88599060ad00a6b609f63fc..8b5cd533d04694122b44aeeb631b6a3eff4ba8b5 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -68,7 +68,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; #ifdef CONFIG_CMD_USB board_usb_hw_init(); @@ -77,11 +77,14 @@ int board_init(void) return 0; } +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; + return fdtdec_setup_mem_size_base(); } #define AT24MAC_MAC_OFFSET 0x9a diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index 4df43d81f827199ca4a39b512d6310581710f90f..411b31160b92cb207c17501e2d84b7658cdc1cfb 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -74,4 +74,3 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } - diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig index df3125eae9a5305065cbaaa37bb731023aa8379c..58799c1a6553fe3d9490a497aac3f77d25fc55d2 100644 --- a/board/beacon/imx8mm/Kconfig +++ b/board/beacon/imx8mm/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mm_beacon" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + source "board/freescale/common/Kconfig" endif diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig index 2bcfb25cf838b909e697036d98c1845e8104a789..65d2923918d6011c0e10c6d808ff94d0981ac23f 100644 --- a/board/beacon/imx8mn/Kconfig +++ b/board/beacon/imx8mn/Kconfig @@ -11,11 +11,12 @@ config SYS_CONFIG_NAME config IMX8MN_FORCE_NOM_SOC bool "Force to use nominal mode for SOC and ARM" - default n config IMX8MN_BEACON_2GB_LPDDR bool "Enable 2GB LPDDR" - default n + +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" source "board/freescale/common/Kconfig" diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README index d3c90d31ddee401bde1ca6220be492e55e09fd8e..a9eddd4e64784ef310cddf1c76397c136952b561 100644 --- a/board/beacon/imx8mn/README +++ b/board/beacon/imx8mn/README @@ -36,4 +36,3 @@ Boot ==== Set baseboard DIP switch: S17: 1100XXXX - diff --git a/board/beacon/imx8mn/lpddr4_timing.c b/board/beacon/imx8mn/lpddr4_timing.c index 3c1ad392f1d88fe728c1cc0222f95f4df07381f1..112e892f517687fc6e15f4c8e1d77430ce0feb53 100644 --- a/board/beacon/imx8mn/lpddr4_timing.c +++ b/board/beacon/imx8mn/lpddr4_timing.c @@ -1431,4 +1431,3 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 400, 100, }, }; - diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig index dcdafb68e5d0126233e13de04701124d01904235..d4416cf09d114b4ebc68dd37394cee87a3558d2b 100644 --- a/board/beckhoff/mx53cx9020/Kconfig +++ b/board/beckhoff/mx53cx9020/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx53cx9020" +config IMX_CONFIG + default "board/beckhoff/mx53cx9020/imximage.cfg" + endif diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index a3657db8266cc0f189a1d35a1e51a02b5e246295..e7b131836b61bc5a077c4928ef2d63d5908bfc25 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -48,6 +48,7 @@ static const u32 CCAT_MODE_RUN = 0x0033DC8F; DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; @@ -59,6 +60,7 @@ u32 get_board_rev(void) return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } +#endif /* * Set CCAT mode diff --git a/board/bosch/guardian/Makefile b/board/bosch/guardian/Makefile index 11625c9dd672b5c697d766f448366360e8230a8a..20cecbfb64e4a98b7121cfd76b3198bab988105d 100644 --- a/board/bosch/guardian/Makefile +++ b/board/bosch/guardian/Makefile @@ -5,7 +5,7 @@ # Copyright (C) 2018 Robert Bosch Power Tools GmbH # -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 179511a670788cb7c276bff9205cdba15f9fe485..105b75e65e9eb01fe74515e1f26e5a606dc8f3ee 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; static const struct ddr_data ddr3_data = { @@ -142,7 +142,7 @@ void am33xx_spl_board_init(void) const struct dpll_params *get_dpll_ddr_params(void) { enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return &dpll_ddr; } diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index 13fd25e4071030209b8c74617d3647a288aaeec0..a7a9775fdf4e8d348bcf56d99818d34855ffa9df 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -51,16 +51,17 @@ static int shc_eeprom_valid; /* * Read header information from EEPROM into global structure. */ +#define EEPROM_ADDR 0x50 static int read_eeprom(void) { /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + if (i2c_probe(EEPROM_ADDR)) { puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); return -ENODEV; } /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header, sizeof(header))) { puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); return -EIO; diff --git a/board/boundary/nitrogen6x/Kconfig b/board/boundary/nitrogen6x/Kconfig index f4db56d49601c933ddec48605468f67a35231cb8..9c176c071e725b8642a4c5888c04a84f9331eddf 100644 --- a/board/boundary/nitrogen6x/Kconfig +++ b/board/boundary/nitrogen6x/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "nitrogen6x" +config DDR_MB + int "Memory size in MB" + endif diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 9d8426502935405d4f7066930f11f0027f2d107b..973b18fa93f424e77817457d2fac23c7c0b2c3c7 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -74,7 +74,7 @@ board configurations is shown in the boards.cfg file: nitrogen6q i.MX6Q/6D 1GB nitrogen6dl i.MX6DL 1GB nitrogen6s i.MX6S 512MB - nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6q2g i.MX6Q/6D 2GB nitrogen6dl2g i.MX6DL 2GB nitrogen6s1g i.MX6S 1GB diff --git a/board/boundary/nitrogen6x/README.mx6qsabrelite b/board/boundary/nitrogen6x/README.mx6qsabrelite index 6283c9575eb638cae9f9b5bca5a563ba6fbd8175..828eea216e100dfa36eaaeb1eb1085397f650347 100644 --- a/board/boundary/nitrogen6x/README.mx6qsabrelite +++ b/board/boundary/nitrogen6x/README.mx6qsabrelite @@ -116,4 +116,3 @@ Note: This will upload and run the U-Boot image in memory, the SPI will not be 5. Use one of previous descriptions to re-flash the SPI-NOR as required. 6. Ensure SW1 is returned to "00" to boot from the fuses once done. - diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index 076ac9414418659f045853cae3795e872c4ca94e..276e59b3bd222f6bae8bfeec8e8b0aee935352ab 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -38,11 +38,6 @@ int board_init(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/cadence/xtfpga/README b/board/cadence/xtfpga/README index 5f29e2592f5c5757acc725500d310da77c7ae47b..889da9e77df8ae40ba7fa0ff07e7d58e476f3e1d 100644 --- a/board/cadence/xtfpga/README +++ b/board/cadence/xtfpga/README @@ -122,4 +122,3 @@ variable to make. Because this problem is easy to fall into and difficult to debug if one doesn't expect it, the linker script provides a link-time check and fatal error message if the image size exceeds 128 KB. - diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 454c93a572f8b4895eb2c638a0080d0c4d31b7fb..3ee133521860d8756bd83a676d4dda17186819e7 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -267,7 +267,7 @@ int board_init(void) return 0; } -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) #define I2C_PMIC 0 int power_init_board(void) { @@ -293,7 +293,7 @@ int power_init_board(void) return 0; } -#endif /* CONFIG_POWER */ +#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ /* * cl_som_imx7_setup_wdog() - watchdog configuration. diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c index 9c7332b43b57b208d4d9dc3a038f0a546f816988..5d4c4d39e724ded70893f00cfe77aeeb02125a92 100644 --- a/board/compulab/cl-som-imx7/spl.c +++ b/board/compulab/cl-som-imx7/spl.c @@ -157,15 +157,15 @@ static void cl_som_imx7_spl_dram_cfg(void) } } -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI static void cl_som_imx7_spl_spi_init(void) { cl_som_imx7_espi1_pads_set(); } -#else /* !CONFIG_SPL_SPI_SUPPORT */ +#else /* !CONFIG_SPL_SPI */ static void cl_som_imx7_spl_spi_init(void) {} -#endif /* CONFIG_SPL_SPI_SUPPORT */ +#endif /* CONFIG_SPL_SPI */ void board_init_f(ulong dummy) { diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index f29b08247ecccfbd42103118eb8330e2831397d0..c54bffdae450d4397ae3e9d491438553e9f85961 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -720,10 +720,12 @@ int dram_init(void) return 0; } +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); } +#endif static struct mxc_serial_plat cm_fx6_mxc_serial_plat = { .reg = (struct mxc_uart *)UART4_BASE, diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index c3c816181fd9cc730df095a6b90da353a92dcb5e..079f196200e585756e3fc1800699e2bdca9b62d4 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -302,7 +302,7 @@ static void cm_fx6_setup_uart(void) enable_uart_clk(1); } -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI static void cm_fx6_setup_ecspi(void) { cm_fx6_set_ecspi_iomux(); @@ -350,7 +350,7 @@ void board_boot_order(u32 *spl_boot_list) } } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC static struct fsl_esdhc_cfg usdhc_cfg = { .esdhc_base = USDHC3_BASE_ADDR, .max_bus_width = 4, diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index efdade155b57d23bb581a500e1595003d03b94f1..bcfe1bfaf67072711a185bb85b246c878f8a934d 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -48,7 +48,7 @@ int board_init(void) gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_probe(TPS65218_CHIP_PM); return 0; diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index 016c63a509a5623d8bf78f94364099796622268e..e67bf81ee3a80465fac7513d9ade5eee2608dd86 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -106,7 +106,7 @@ const struct dpll_params *get_dpll_per_params(void) void scale_vcores(void) { set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (i2c_probe(TPS65218_CHIP_PM)) return; @@ -133,4 +133,3 @@ void sdram_init(void) hang(); } - diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 842fb3b6a62632bc4b92dbb68656deab26d00f4e..25dad498774c637efab327fa4248f73941c7b9f3 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -5,6 +5,6 @@ # Author: Igor Grinberg obj-y += common.o -obj-$(CONFIG_SYS_I2C_LEGACY) += eeprom.o +obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += eeprom.o obj-$(CONFIG_LCD) += omap3_display.o obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index b41c64d2a3291bcedabf05123ca7670cf800bb66..c4b257f851d664ae451c9fad5f6c5a8bf9f5d19b 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -15,15 +15,6 @@ #include #include "eeprom.h" -#ifndef CONFIG_SYS_I2C_EEPROM_ADDR -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#endif - -#ifndef CONFIG_SYS_I2C_EEPROM_BUS -#define CONFIG_SYS_I2C_EEPROM_BUS 0 -#endif - #define EEPROM_LAYOUT_VER_OFFSET 44 #define BOARD_SERIAL_OFFSET 20 #define BOARD_SERIAL_OFFSET_LEGACY 8 @@ -394,43 +385,8 @@ int eeprom_field_update_date(struct eeprom_field *field, char *value) #define LAYOUT_VERSION_VER2 3 #define LAYOUT_VERSION_VER3 4 -extern struct eeprom_field layout_unknown[1]; - #define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x -#ifdef CONFIG_CM_T3X -struct eeprom_field layout_legacy[5] = { - { "MAC address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Board Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin) }, - { "Serial Number", 8, NULL, DEFINE_PRINT_UPDATE(bin) }, - { "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { RESERVED_FIELDS, 176, NULL, eeprom_field_print_reserved, - eeprom_field_update_ascii }, -}; -#else -#define layout_legacy layout_unknown -#endif - -#if defined(CONFIG_CM_T3X) -struct eeprom_field layout_v1[12] = { - { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, - { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, - { RESERVED_FIELDS, 96, NULL, DEFINE_PRINT_UPDATE(reserved) }, - { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, - eeprom_field_update_ascii }, -}; -#else -#define layout_v1 layout_unknown -#endif - struct eeprom_field layout_v2[15] = { { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, @@ -473,14 +429,6 @@ struct eeprom_field layout_v3[16] = { void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) { switch (layout->layout_version) { - case LAYOUT_VERSION_LEGACY: - layout->fields = layout_legacy; - layout->num_of_fields = ARRAY_SIZE(layout_legacy); - break; - case LAYOUT_VERSION_VER1: - layout->fields = layout_v1; - layout->num_of_fields = ARRAY_SIZE(layout_v1); - break; case LAYOUT_VERSION_VER2: layout->fields = layout_v2; layout->num_of_fields = ARRAY_SIZE(layout_v2); diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index 51c8acf3b82d563a5119ab2336eb39c34361237a..9bd7604a999c66f8848664ae453e276ead01843d 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -10,7 +10,7 @@ #define _EEPROM_ #include -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); u32 cl_eeprom_get_board_rev(uint eeprom_bus); int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus); diff --git a/board/compulab/imx8mm-cl-iot-gate/Kconfig b/board/compulab/imx8mm-cl-iot-gate/Kconfig index 7f5c794bf54d9e13c3c8cb7b0c80b21161af8457..30760cbf4517317ec29f9c128fa02eef37340d09 100644 --- a/board/compulab/imx8mm-cl-iot-gate/Kconfig +++ b/board/compulab/imx8mm-cl-iot-gate/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mm-cl-iot-gate" +config IMX_CONFIG + default "board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" + endif diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c index 870a94aecc8ef94c4cef53784c2b8c698ba32579..9019a1f2035cd8dfd42a92b99edcbe0485aa9f3c 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c @@ -1845,4 +1845,3 @@ struct dram_timing_info ucm_dram_timing_01061010 = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 2400, 400, 100, }, }; - diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 8f592457d4c41b4d2707a1b97f5f2c361d16be22..2dc62d6682e041e1f96fbceeaf6262d808fbf5c6 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -176,7 +176,7 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, 100000, 0x7f, &i2c_pad_info1); power_init_board(); diff --git a/board/congatec/cgtqmx8/Kconfig b/board/congatec/cgtqmx8/Kconfig index 72730392615eddd64c599e71b7c66f1189fa60bd..74e9838d29ea249246901decfdb047f2c3fb6ef7 100644 --- a/board/congatec/cgtqmx8/Kconfig +++ b/board/congatec/cgtqmx8/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "cgtqmx8" +config IMX_CONFIG + default "board/congatec/cgtqmx8/imximage.cfg" + source "board/congatec/common/Kconfig" endif diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig index 5c205bd83043a2c42b1e9d0fa5e01d2480518ebd..d4a238de99bc03b56eeb1850a15b6498838a6020 100644 --- a/board/congatec/common/Kconfig +++ b/board/congatec/common/Kconfig @@ -28,7 +28,6 @@ endif config VOL_MONITOR_LTC3882_READ depends on VID bool "Enable the LTC3882 voltage monitor read" - default n help This option enables LTC3882 voltage monitor read functionality. It is used by common VID driver. @@ -36,13 +35,11 @@ config VOL_MONITOR_LTC3882_READ config VOL_MONITOR_LTC3882_SET depends on VID bool "Enable the LTC3882 voltage monitor set" - default n help This option enables LTC3882 voltage monitor set functionality. It is used by common VID driver. config USB_TCPC bool "USB Typec port controller simple driver" - default n help Enable USB type-c port controller (TCPC) driver diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index bb1188b4ea2d27ed3efd8225301755b0adc1548c..c5499a63fd36f54991033f6829fef88585a3cf90 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -22,15 +22,6 @@ config MAC_ADDR_IN_SPIFLASH their MAC address in SPI Flash from the factory Enable this option to read the MAC from SPI Flash -config MAC_ADDR_IN_EEPROM - bool "MAC address in EEPROM" - help - The DA850 EVM comes with SoM are programmed with - their MAC address in SPI Flash from the factory, - but the kit has an optional expansion board with - EEPROM available. Enable this option to read the - MAC from the EEPROM - endif endif diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile index 3fac615d7b8838c967c94c39c5ff7834dc094a1a..8187c8db22e3072f489f3bc36f451eb1aad45484 100644 --- a/board/davinci/da8xxevm/Makefile +++ b/board/davinci/da8xxevm/Makefile @@ -7,4 +7,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o -obj-$(CONFIG_MACH_OMAPL138_LCDK) += omapl138_lcdk.o +obj-$(CONFIG_TARGET_OMAPL138_LCDK) += omapl138_lcdk.o diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 6c75231ddf775403c1db9b0697aaf6594999fae2..2436aab71ccf3774e0fc3143b5660ec83e2d6c0e 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -129,19 +129,12 @@ int misc_init_r(void) { dspwake(); -#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) - - uchar env_enetaddr[6]; - int enetaddr_found; +#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) + uchar env_enetaddr[6], buff[6]; + int enetaddr_found, spi_mac_read; enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr); -#endif - -#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH - int spi_mac_read; - uchar buff[6]; - spi_mac_read = get_mac_addr(buff); buff[0] = 0; @@ -173,34 +166,6 @@ int misc_init_r(void) "with the MAC address in the environment\n"); printf("Default using MAC address from environment\n"); } - -#elif defined(CONFIG_MAC_ADDR_IN_EEPROM) - uint8_t enetaddr[8]; - int eeprom_mac_read; - - /* Read Ethernet MAC address from EEPROM */ - eeprom_mac_read = dvevm_read_mac_address(enetaddr); - - /* - * MAC address not present in the environment - * try and read the MAC address from EEPROM flash - * and set it. - */ - if (!enetaddr_found) { - if (eeprom_mac_read) - /* Set Ethernet MAC address from EEPROM */ - davinci_sync_env_enetaddr(enetaddr); - } else { - /* - * MAC address present in environment compare it with - * the MAC address in EEPROM and warn on mismatch - */ - if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) - printf("Warning: MAC address in EEPROM don't match " - "with the MAC address in the environment\n"); - printf("Default using MAC address from environment\n"); - } - #endif return 0; } @@ -267,6 +232,7 @@ const int lpsc_size = ARRAY_SIZE(lpsc); #define REV_AM18X_EVM 0x100 +#ifdef CONFIG_REVISION_TAG /* * get_board_rev() - setup to pass kernel board revision information * Returns: @@ -294,6 +260,7 @@ u32 get_board_rev(void) rev = 1; return rev; } +#endif int board_early_init_f(void) { diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index d5f43bf52044b22fcdde51b2b53a1664e5357b1b..cd021cc8e5834d2059fb5fd28f14d6ba95eb78b0 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -143,20 +143,6 @@ const int lpsc_size = ARRAY_SIZE(lpsc); #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000 #endif -/* - * get_board_rev() - setup to pass kernel board revision information - * Returns: - * bit[0-3] Maximum cpu clock rate supported by onboard SoC - * 0000b - 300 MHz - * 0001b - 372 MHz - * 0010b - 408 MHz - * 0011b - 456 MHz - */ -u32 get_board_rev(void) -{ - return 0; -} - int board_early_init_f(void) { /* @@ -236,12 +222,6 @@ int board_init(void) #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) -static int get_mac_addr(u8 *addr) -{ - /* Need to find a way to get MAC ADDRESS */ - return 0; -} - void dsp_lpsc_on(unsigned domain, unsigned int id) { dv_reg_p mdstat, mdctl, ptstat, ptcmd; @@ -304,29 +284,6 @@ int rmii_hw_init(void) int misc_init_r(void) { - uint8_t tmp[20], addr[10]; - - - if (env_get("ethaddr") == NULL) { - /* Read Ethernet MAC address from EEPROM */ - if (dvevm_read_mac_address(addr)) { - /* Set Ethernet MAC address from EEPROM */ - davinci_sync_env_enetaddr(addr); - } else { - get_mac_addr(addr); - } - - if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) { - sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", - addr[0], addr[1], addr[2], addr[3], addr[4], - addr[5]); - - env_set("ethaddr", (char *)tmp); - } else { - printf("Invalid MAC address read.\n"); - } - } - #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII /* Select RMII fucntion through the expander */ if (rmii_hw_init()) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d7c1857c16855d6b2d6bf73378a5bb7cd19d8ebf..4b3167f69d263bd2ac697e3467ae7dbce9aa517d 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "../../st/common/stpmic1.h" /* SYSCFG registers */ @@ -382,10 +383,10 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) #ifdef CONFIG_LED static int get_led(struct udevice **dev, char *led_string) { - char *led_name; + const char *led_name; int ret; - led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); + led_name = ofnode_conf_read_str(led_string); if (!led_name) { pr_debug("%s: could not find %s config string\n", __func__, led_string); diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig index 90883aced4582a445bbcda09269b95d3efa281a6..f7b1f1bf46fd21d73d870c85165e6de650087f88 100644 --- a/board/ea/mx7ulp_com/Kconfig +++ b/board/ea/mx7ulp_com/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx7ulp_com" +config IMX_CONFIG + default "board/ea/mx7ulp_com/imximage.cfg" + endif diff --git a/board/eets/pdu001/Makefile b/board/eets/pdu001/Makefile index 08c6d536d36da6ebe3a3e7ecd2e197b8232f229c..a5990ce3ad229e6bd1079552d62a041c5a135136 100644 --- a/board/eets/pdu001/Makefile +++ b/board/eets/pdu001/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index f806d1e7672a13a1dcfea25419aa742383b95c30..9f3cfd4f842d9234aca38696b8212e3dddf88aa2 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -162,7 +162,7 @@ static void set_mpu_and_core_voltage(void) } } -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, @@ -235,7 +235,7 @@ void sdram_init(void) config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); } -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ #ifdef CONFIG_DEBUG_UART void board_debug_uart_init(void) diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index dda8502c6f026e3a8b8c6b81093b8e130ba94762..a3c23bdfb64e0fb25b9379607efcaec841bbf133 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -473,7 +473,7 @@ void board_init_f(ulong dummy) /* setup GP timer */ timer_init(); -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL setup_iomux_uart(); preloader_console_init(); #endif diff --git a/board/engicam/imx8mm/Kconfig b/board/engicam/imx8mm/Kconfig index ed68516df450f695b3c4ef5c223c4ce80c7080de..5495b3bf99be44cdbc1e76439350dce7a8851bdb 100644 --- a/board/engicam/imx8mm/Kconfig +++ b/board/engicam/imx8mm/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mm_icore_mx8mm" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + source "board/freescale/common/Kconfig" endif diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index 41c49e5daa725154cd1d535928c18e8dc5cb4488..95d8b00924d8a39138fabda7866f9a26d82df690 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -8,9 +8,9 @@ #include #include #include +#include #ifdef CONFIG_SPL_BUILD -DECLARE_GLOBAL_DATA_PTR; static int setup_led(void) { #ifdef CONFIG_SPL_LED @@ -18,7 +18,7 @@ static int setup_led(void) char *led_name; int ret; - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + led_name = ofnode_conf_read_str("u-boot,boot-led"); if (!led_name) return 0; ret = led_get_by_label(led_name, &dev); diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 35a6115e5e437ffa59d3daf6aab835e08d10eee3..69620dbb74e41ec9b225afa775e7240a7f10ce3d 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -24,7 +24,6 @@ config CMD_ESBC_VALIDATE config FSL_USE_PCA9547_MUX bool "Enable PCA9547 I2C Mux on Freescale boards" - default n help This option enables the PCA9547 I2C mux on Freescale boards. diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h index 81d1aa715d5c044ee4340fd820811453091fbcc3..163496930c87b613195e313d8061733d69406f35 100644 --- a/board/freescale/common/ics307_clk.h +++ b/board/freescale/common/ics307_clk.h @@ -8,7 +8,6 @@ #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(void); -extern unsigned long get_board_ddr_clk(void); extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); #endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 35df8ba389ed0b817eda7cb82b086bf71e9b412a..431f8caeb03496e6ff4cbc3034186d9be045181b 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -62,7 +62,7 @@ static struct __attribute__ ((__packed__)) eeprom { u8 mac_count; /* 0x40 Number of MAC addresses */ u8 mac_flag; /* 0x41 MAC table flags */ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */ - u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ + u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ u32 crc; /* 0xfc - 0xff CRC32 checksum */ #endif } e; diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c index 03679e723f2c29f05c5663c7777fcd19d9f98b02..e8c2fc85c845b1d21081189b11299f0918f6d3a4 100644 --- a/board/freescale/common/zm7300.c +++ b/board/freescale/common/zm7300.c @@ -230,4 +230,3 @@ int zm_enable_wp() } return 0; } - diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig index 299691a61949498ef611de775c2f63f9456b52ec..24cc526b0abe301fc7c17cd19222f87327c25abe 100644 --- a/board/freescale/imx8mm_evk/Kconfig +++ b/board/freescale/imx8mm_evk/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mm_evk" +config IMX_CONFIG + default "board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" + endif diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 478f4ed66ed8ed2f144ffc8b8ce4313d5b26c277..0adf87bd42a115079c182fc482a845ba7d895c46 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -11,7 +11,9 @@ config SYS_CONFIG_NAME config IMX8MN_LOW_DRIVE_MODE bool "Enable the low drive mode of iMX8MN on EVK board" - default n + +config IMX_CONFIG + default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" source "board/freescale/common/Kconfig" diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c index f1509e2159a137c3acdd5ee9e7aec3ff1e7225c5..77611ea0260c771d87f34e7b6854666947ade2a8 100644 --- a/board/freescale/imx8mn_evk/ddr4_timing.c +++ b/board/freescale/imx8mn_evk/ddr4_timing.c @@ -1052,4 +1052,3 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 2400, 1066, }, }; - diff --git a/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/board/freescale/imx8mn_evk/ddr4_timing_ld.c index 983fc7d99ffe60e8d21b8ce783be3a05e6985888..a3577efd0b24be7c3facd99da02b5f54a71f2fdc 100644 --- a/board/freescale/imx8mn_evk/ddr4_timing_ld.c +++ b/board/freescale/imx8mn_evk/ddr4_timing_ld.c @@ -1054,4 +1054,3 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 1600, 1066, }, }; - diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig index 49bb29a45d8a2da1494e816c1473401d3038c7c9..42625fd58889fe69213e9a4ce26b4ffb939921ae 100644 --- a/board/freescale/imx8mp_evk/Kconfig +++ b/board/freescale/imx8mp_evk/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mp_evk" +config IMX_CONFIG + default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index a7564e9b1ae273bb8697fb1d15c90e92e188f1f4..eca42c756e433340fbf959406bad786d2b922f17 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -63,7 +63,7 @@ struct i2c_pads_info i2c_pad_info1 = { }, }; -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) #define I2C_PMIC 0 int power_init_board(void) { diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig index 421b081c761695f3f380f5d25f319fe31b971fc0..c4d20ad7c7d07d823202b3096d16c90a5d7b1e18 100644 --- a/board/freescale/imx8mq_evk/Kconfig +++ b/board/freescale/imx8mq_evk/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mq_evk" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage.cfg" + endif diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index e8e0efe485574689eafd176bc383e6b3c239ad0a..67d069b2b053637113960a5ee0f2326ef758ff5b 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -156,7 +156,7 @@ int board_mmc_init(struct bd_info *bis) return 0; } -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) #define I2C_PMIC 0 int power_init_board(void) { diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig index 93d7d5f9c576f09d4f5f15b79b17135e1c4692d6..aed6ab25ce189142519e56f9f3acf5769cafb5a2 100644 --- a/board/freescale/imx8qm_mek/Kconfig +++ b/board/freescale/imx8qm_mek/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8qm_mek" +config IMX_CONFIG + default "board/freescale/imx8qm_mek/imximage.cfg" + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig index b67300d816cc5f31cfdc5427740e1cc9eba4a00c..b9aab3789ee4ad00fc0ff1c80caaff93eb68e6f7 100644 --- a/board/freescale/imx8qxp_mek/Kconfig +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8qxp_mek" +config IMX_CONFIG + default "board/freescale/imx8qxp_mek/imximage.cfg" + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c index 479e66bddc44fa3d00afbdfa114cd9053658138c..54a733b12ce6d64af144fac21f283fef4954a6da 100644 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c @@ -71,11 +71,6 @@ u32 spl_boot_device(void) } #endif -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index eb492390dbf6a3b3a3cc870f3b301b5b27779700..61329165786d678a0e1277abaac9c13de839da64 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -71,11 +71,6 @@ u32 spl_boot_device(void) } #endif -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README index 181c4615a87124cf608f6e33e6c11514a778fd65..382b668fbec6bf4e33ececfed113d45bdcc9ce65 100644 --- a/board/freescale/ls1012afrdm/README +++ b/board/freescale/ls1012afrdm/README @@ -52,7 +52,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README index dee4b302c14c8eba74b5340451aaf1c4751ea525..c1956f9fd78a9668cc6cbada3bbc1e08fbf25a1b 100644 --- a/board/freescale/ls1012aqds/README +++ b/board/freescale/ls1012aqds/README @@ -53,7 +53,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c index 8189f41becb32036289695d31a6cf760681215c2..27f69abf60914721e47b6a6e19609d949744aef1 100644 --- a/board/freescale/ls1012aqds/eth.c +++ b/board/freescale/ls1012aqds/eth.c @@ -244,7 +244,7 @@ int pfe_eth_board_init(struct udevice *dev) bus = miiphy_get_dev_by_name(mdio_name); pfe_set_mdio(1, bus); pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); data8 = QIXIS_READ(brdcfg[12]); data8 |= 0x20; @@ -263,7 +263,7 @@ int pfe_eth_board_init(struct udevice *dev) pfe_set_mdio(0, bus); pfe_set_phy_address_mode(0, CONFIG_PFE_SGMII_2500_PHY1_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); } break; diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 33a0910a198a5a9a86a103d23fd524912094ebe6..6e21040601d2e9059bbe304c4dceb88186228362 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -265,7 +265,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) ETH_1_2_5G_MDIO_MUX); prop_val.phy_mask = cpu_to_fdt32( ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "sgmii-2500"; + prop_val.phy_mode = "2500base-x"; pfe_set_properties(l_blob, prop_val, ETH_1_PATH, ETH_1_MDIO); } else { @@ -277,7 +277,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) ETH_2_2_5G_MDIO_MUX); prop_val.phy_mask = cpu_to_fdt32( ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "sgmii-2500"; + prop_val.phy_mode = "2500base-x"; pfe_set_properties(l_blob, prop_val, ETH_2_PATH, ETH_2_MDIO); } diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h index 05ccb71aa06902edb3224c80f03ea9518053cc6f..5ab283ce8d56738ddd594b594a88a2352af7e6eb 100644 --- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h +++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h @@ -17,7 +17,7 @@ #define ETH_1_2_5G_PHY_ID 0x1 #define ETH_1_2_5G_MDIO_MUX 0x2 #define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 -#define ETH_2_5G_PHY_MODE "sgmii-2500" +#define ETH_2_5G_PHY_MODE "2500base-x" #define ETH_2_2_5G_BUS_ID 0x1 #define ETH_2_2_5G_PHY_ID 0x2 #define ETH_2_2_5G_MDIO_MUX 0x3 diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README index 572fd8c7d0835d386d772230c9b5c8d54f3d563a..5b6f306a1d9d54ce4511775f2a0a941ed00c2d56 100644 --- a/board/freescale/ls1012ardb/README +++ b/board/freescale/ls1012ardb/README @@ -48,8 +48,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 @@ -90,8 +90,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4030_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4030_0000 PPA FIT image | 2MB | 0x4040_0000 PFE firmware | 20K | 0x00a0_0000 Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index bb3fbc71ef65196b790fe85107515203ebda7e78..565f800596561b3afdc65390928a78b66dc385aa 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -121,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev) /* MAC1 */ pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); } else { /* MAC2 */ pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); } break; default: diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README index 6cf7146fb2371a7fbb8927d49aa41a86414ae388..e2ce00165bd1b3b5d2a0690cd037e302dc4d397f 100644 --- a/board/freescale/ls1021aqds/README +++ b/board/freescale/ls1021aqds/README @@ -113,6 +113,5 @@ Start Address End Address Description Size LS1021a rev1.0 Soc specific Options/Settings -------------------------------------------- -If the LS1021a Soc is rev1.0, you need modify the configure file. -Add the following define in include/configs/ls1021aqds.h: -#define CONFIG_SKIP_LOWLEVEL_INIT +If the LS1021a Soc is rev1.0, you need modify the configuration and enable +CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 711d8c290661eb97eaa5c5f16f2fbeed1129401a..fbbd27d9d71eb156dbe846201bdcb7b0212302e2 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -127,6 +127,7 @@ unsigned long get_board_sys_clk(void) return 66666666; } +#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ unsigned long get_board_ddr_clk(void) { u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); @@ -141,6 +142,7 @@ unsigned long get_board_ddr_clk(void) } return 66666666; } +#endif int dram_init(void) { diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index c1acd3040c424e486d4aea3a0bc20685214e0e48..f31e16c419a9c05ab1edad535639e081dea7874c 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2019 NXP Semiconductors +/* Copyright 2016-2019 NXP */ #include #include diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README index 896a659476827b3ea06e1e5da88ccfa8093b2fe3..a4639cd747632363e630be5acefc54aeb4dbb6ac 100644 --- a/board/freescale/ls1021atwr/README +++ b/board/freescale/ls1021atwr/README @@ -110,6 +110,5 @@ Start Address End Address Description Size LS1021a rev1.0 Soc specific Options/Settings -------------------------------------------- -If the LS1021a Soc is rev1.0, you need modify the configure file. -Add the following define in include/configs/ls1021atwr.h: -#define CONFIG_SKIP_LOWLEVEL_INIT +If the LS1021a Soc is rev1.0, you need modify the configuration and enable +CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig index ca22c922035470f99708f2cce128b05c55270e3e..40939816ad89a7051196e73ef09d39afd46b5a03 100644 --- a/board/freescale/ls1028a/Kconfig +++ b/board/freescale/ls1028a/Kconfig @@ -14,7 +14,6 @@ config SYS_CONFIG_NAME config EMMC_BOOT bool "Support for booting from EMMC" - default n config SYS_TEXT_BASE default 0x96000000 if SD_BOOT || EMMC_BOOT @@ -53,7 +52,6 @@ config SYS_CONFIG_NAME config EMMC_BOOT bool "Support for booting from EMMC" - default n config SYS_TEXT_BASE default 0x96000000 if SD_BOOT || EMMC_BOOT diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 5269fd34c693e44cefb2a704b16c3441c5d37f93..461c571b36c8e5f1b525d944c268bd765e2e9d58 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -137,7 +137,7 @@ int board_early_init_f(void) u8 uart; #endif -#ifdef CONFIG_SYS_I2C_EARLY_INIT +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) i2c_early_init_f(); #endif diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index 913537d45190e1d54cf2c39eb70b00a67174da3c..f5aa51da87eb84e70db87c0c16091a4ff91053d5 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -18,7 +18,7 @@ SoC overview. - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index c3efe8a0be649cd2f1b84ce51da1cf6898508d72..e156ba010451070c9774096b91ebc50967196f8e 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -176,7 +176,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "sgmii-riser-s4-p1"); } } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_SGMII_2500) { + PHY_INTERFACE_MODE_2500BASEX) { /* 2.5G SGMII interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); @@ -187,7 +187,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", - "sgmii-2500"); + "2500base-x"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (mdio_mux[port]) { case EMI1_SLOT1: @@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && port == FM1_10GEC1) { - /* XFI interface */ + /* 10GBase-R interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; - /* no PHY for XFI */ + /* no PHY for 10GBase-R */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); @@ -430,12 +430,12 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_2500_FM1_DTSEC1 + idx); } else { diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 76bbb6087afdc354b56a8b69a79c5b5fa7f01a09..2d5322406aa1043c80553243bdc66d672e22fc9d 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -52,10 +52,6 @@ enum { #define CFG_UART_MUX_SHIFT 1 #define CFG_LPUART_EN 0x1 -#ifdef CONFIG_SYS_I2C_EARLY_INIT -void i2c_early_init_f(void); -#endif - #ifdef CONFIG_TFABOOT struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { @@ -447,7 +443,7 @@ int board_early_init_f(void) */ out_le32(cntcr, 0x1); -#ifdef CONFIG_SYS_I2C_EARLY_INIT +#if defined(CONFIG_SYS_I2C_EARLY_INIT) i2c_early_init_f(); #endif fsl_lsch2_early_init_f(); diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index 3d9e295c4e71273b02b2b7d4ee7977bf613affc9..778b8d8d5a5a1048d175df4e3df968a5d2d9a53c 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -16,7 +16,6 @@ config SYS_CONFIG_NAME config SYS_HAS_ARMV8_SECURE_BASE bool "Enable secure address for PSCI image" depends on ARMV8_PSCI - default n help PSCI image can be re-located to secure RAM. If enabled, please also define the value for ARMV8_SECURE_BASE, diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 709ddbbef31a4cb42f68a72a870f599ce54d34ea..66ee578e99d9c8404f8feb77934f1f5864d1327d 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -17,7 +17,7 @@ SoC overview. - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and standard PCIe card - QSGMII with x4 RJ45 connector - - XFI with x1 RJ45 connector + - 10GBase-R with x1 RJ45 connector - DDR Controller - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index 1f01c15516564b4ce8f35613cbe24385680b9896..fa59116ce57b3e3414f3571ab5d0c4a6999d6022 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); - /* XFI on lane A, MAC 9 */ + /* 10GBase-R on lane A, MAC 9 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README index d7b5a7794f68344c98181f1046ea11cc467b852c..2c7c797a8791bb2f69e35fe10f0acc60e1bcc1fa 100644 --- a/board/freescale/ls1046afrwy/README +++ b/board/freescale/ls1046afrwy/README @@ -42,8 +42,8 @@ Memory map from core's view Start Address End Address Description Size 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README index b8fa32652b0da0c43c2836a8401029be426afd16..cb694735a46b0d2a9028598ce6f27d7718ba4e0d 100644 --- a/board/freescale/ls1046aqds/README +++ b/board/freescale/ls1046aqds/README @@ -18,7 +18,7 @@ SoC overview. - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s -IFC/Local Bus @@ -47,8 +47,8 @@ Memory map from core's view Start Address End Address Description Size 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB 0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 33db552adb8a32e5dd6cb8a5610aa3d03cf43118..8233f5461ee3adf9d74882f3282713f4662d1f61 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -178,7 +178,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, default: break; } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { /* 2.5G SGMII interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); @@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", - "sgmii-2500"); + "2500base-x"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: @@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, /* Backplane KR mode: skip fixups */ printf("Interface %d in backplane KR mode\n", port); } else { - /* XFI interface */ + /* 10GBase-R interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; - /* no PHY for XFI */ + /* no PHY for 10GBase-R */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 2b0786ac30d4b59d09dee9768b44413a28967634..cc95d441b607c05256202c1fc4b485c2aaf9fe05 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -37,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SYS_I2C_EARLY_INIT -void i2c_early_init_f(void); -#endif - #ifdef CONFIG_TFABOOT struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { @@ -318,7 +314,7 @@ int board_early_init_f(void) */ out_le32(cntcr, 0x1); -#ifdef CONFIG_SYS_I2C_EARLY_INIT +#if defined(CONFIG_SYS_I2C_EARLY_INIT) i2c_early_init_f(); #endif fsl_lsch2_early_init_f(); diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README index a38c9d48300e96a46987f92daf3d2352727f5d64..90c44f4bce3c0cefeb38a3bc3bf260534b946340 100644 --- a/board/freescale/ls1046ardb/README +++ b/board/freescale/ls1046ardb/README @@ -14,8 +14,8 @@ SoC overview. LS1046ARDB board Overview ----------------------- - SERDES1 Connections, 4 lanes supporting: - - Lane0: XFI with x1 RJ45 connector - - Lane1: XFI Cage + - Lane0: 10GBase-R with x1 RJ45 connector + - Lane1: 10GBase-R Cage - Lane2: SGMII.5 - Lane3: SGMII.6 - SERDES2 Connections, 4 lanes supporting: @@ -43,8 +43,8 @@ Memory map from core's view Start Address End Address Description Size 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB @@ -59,7 +59,7 @@ Start Address End Address Description Size QSPI flash map: Start Address End Address Description Size 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB -0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB +0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB 0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB 0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB 0x00_4060_0000 - 0x00_408F_FFFF Secure boot header diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index 4905302d8cd9769b4faa6e0a1d8ac0d25ab6bc5a..a3e147a48b98248b42d78ac00753f3ffc98caf1e 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); - /* XFI on lane A, MAC 9 */ + /* 10GBase-R on lane A, MAC 9 */ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README index aa0fb6ac676f4a83fb7e7fca554e939ca691a84e..5315909defc87cb7e04715c47e38ca0c33313c16 100644 --- a/board/freescale/ls1088a/README +++ b/board/freescale/ls1088a/README @@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - XFI + - 10GBase-R - QSGMII - DDR Controller - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four @@ -106,7 +106,7 @@ SW12 1111 1111 - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - 2 XFI + - 2 10GBase-R - QSGMII, SGMII with help for Riser card - 2 RGMII - 5 slot for Riser card or PCIe NIC diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index 995c42960178df7a8a4f312a3f073257a33317a1..9e0941cc9d6e48abf8e0627c82f002a3078ce451 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -88,8 +88,6 @@ found: pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - - popts->half_strength_driver_enable = 0; /* * Write leveling override diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c index a8e9ef15dc487a1e4ae1ef4818ccefcdcfe8c649..1ba5e94d0a0ab07aa09d1b497eb48c1118dec541 100644 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ b/board/freescale/ls1088a/eth_ls1088ardb.c @@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis) switch (srds_s1) { case 0x1D: /* - * XFI does not need a PHY to work, but to avoid U-boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI + * 10GBase-R does not need a PHY to work, but to avoid U-boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R * MAC error. */ wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a); diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 8e31e9e41e3e18744d93b6778924b10b9aa3a41b..971633c9c8b2dac4b0de954b61a77f316ee80c7f 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -19,7 +19,7 @@ LS2088A SoC overview. - QSGMII - SATA 3.0 - XAUI - - XFI + - 10GBase-R - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. @@ -213,4 +213,3 @@ DPMAC13 -> PHY4-P0 DPMAC14 -> PHY4-P1 DPMAC15 -> PHY4-P2 DPMAC16 -> PHY4-P3 - diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 914cd0a9ab5968c08247673bcb373ced1ad9264e..7db37898220aa1cf3e9e241af842950c8b4b9c83 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i) case 0x4B: case 0x4C: /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause - * error. + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R + * MAC, and should not use a real XAUI PHY address, since MDIO + * can access it successfully, and then MDIO thinks the XAUI + * card is used for the 10GBase-R MAC, which will cause error. */ wriop_set_phy_address(i, 0, i + 4); ls2080a_qds_enable_SFP_TX(SFP_TX); diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index c48b01f7d7d14e3a435cfea9d8cc0b9b59edc8a9..62658c4702907d18c3369388219a4cb44883885d 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -241,7 +241,7 @@ int board_init(void) int board_early_init_f(void) { -#ifdef CONFIG_SYS_I2C_EARLY_INIT +#if defined(CONFIG_SYS_I2C_EARLY_INIT) i2c_early_init_f(); #endif fsl_lsch3_early_init_f(); diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 205c45cb2af3a1fc19c845a4aa07f50409143562..4c1c36ea3a5f570990770df6de62c2c2f549452b 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview. - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. @@ -132,4 +132,3 @@ below: => setenv bootargs 'console=ttyS1,115200 root=/dev/ram earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m hugepages=16 mem=2048M' - diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index e8722f20c139489173f72dd4ed3072a6a4827f52..58b852383e995f93d475991f524f7605c0aafee9 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -314,7 +314,7 @@ int board_init(void) int board_early_init_f(void) { -#ifdef CONFIG_SYS_I2C_EARLY_INIT +#if defined(CONFIG_SYS_I2C_EARLY_INIT) i2c_early_init_f(); #endif fsl_lsch3_early_init_f(); diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index f505e82fb963967b942eac14702f2774efbdc702..e61289d228027899225cb389ec9cfac0a96646dd 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -89,7 +89,7 @@ static void uart_get_clock(void) int board_early_init_f(void) { -#ifdef CONFIG_SYS_I2C_EARLY_INIT +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) i2c_early_init_f(); #endif /* get required clock for UART IP */ diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index c4b019e2a910174ba6c3a10a4849fdca27f86bbb..8a7d8cadf02e14a1c31145f999ca00e5e929ac4f 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -98,7 +98,7 @@ CONFIG_SYS_IMMR -- define for MBAR offset CONFIG_SYS_MBAR -- define MBAR offset -CONFIG_MONITOR_IS_IN_RAM -- Not support +CONFIG_MONITOR_IS_IN_RAM -- Not support CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig deleted file mode 100644 index d1541180799e26e82043c690c17eb9f6a702e3c2..0000000000000000000000000000000000000000 --- a/board/freescale/mpc8349emds/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_MPC8349EMDS - -config SYS_BOARD - default "mpc8349emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349EMDS" - -endif - -if TARGET_MPC8349EMDS_SDRAM - -config SYS_BOARD - default "mpc8349emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349EMDS_SDRAM" - -endif diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS deleted file mode 100644 index a8f26a9a316911d89cf4ffe25ef321742409ca50..0000000000000000000000000000000000000000 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MPC8349EMDS BOARD -#M: Kim Phillips -S: Orphan (since 2018-05) -F: board/freescale/mpc8349emds/ -F: include/configs/MPC8349EMDS.h -F: configs/MPC8349EMDS_defconfig -F: configs/MPC8349EMDS_SDRAM_defconfig -F: configs/MPC8349EMDS_PCI64_defconfig -F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile deleted file mode 100644 index af02f65cb004c4ce4bdbc542aea1243cc9a7d7e8..0000000000000000000000000000000000000000 --- a/board/freescale/mpc8349emds/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8349emds.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c deleted file mode 100644 index ac5ddc6d94b83620482d381dbc8091fb9042d468..0000000000000000000000000000000000000000 --- a/board/freescale/mpc8349emds/ddr.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include - -#include -#include - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 300, 4, 4, 2, 0}, - {2, 365, 4, 6, 2, 0}, - {2, 450, 4, 7, 2, 0}, - {2, 850, 4, 31, 2, 0}, - {1, 300, 4, 4, 2, 0}, - {1, 365, 4, 6, 2, 0}, - {1, 450, 4, 7, 2, 0}, - {1, 850, 4, 31, 2, 0}, - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned int i; - ulong ddr_freq; - - if (ctrl_num != 0) /* we have only one controller */ - return; - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (pdimm[i].n_ranks) - break; - } - if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ - return; - - pbsp = udimm0; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[i].n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - popts->dqs_config = 0; /* only true DQS signal is used on board */ -} diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c deleted file mode 100644 index 5f38639afd42d8df0fc9eba8e2dd674c5791d2df..0000000000000000000000000000000000000000 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SYS_FSL_DDR2 -#include -#else -#include -#endif -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int fixed_sdram(void); -void sdram_init(void); - -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) -void ddr_enable_ecc(unsigned int dram_size); -#endif - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - -#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY - /* Use USB PHY on SYS board */ - bcsr[5] |= 0x02; -#endif - - return 0; -} - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - phys_size_t msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) -#ifndef CONFIG_SYS_FSL_DDR2 - msize = spd_sdram() * 1024 * 1024; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - ddr_enable_ecc(msize); -#endif -#else - msize = fsl_ddr_sdram(); -#endif -#else - msize = fixed_sdram() * 1024 * 1024; -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE; - u32 ddr_size = msize << 20; /* DDR size in bytes */ - u32 ddr_size_log2 = __ilog2(ddr_size); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - -#if (CONFIG_SYS_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#ifdef CONFIG_DDR_II - im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; -#else - -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.cs_config[0] = 0; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - - im->ddr.sdram_cfg = - SDRAM_CFG_SREN -#if defined(CONFIG_DDR_2T_TIMING) - | SDRAM_CFG_2T_EN -#endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; -#if defined (CONFIG_DDR_32BIT) - /* for 32-bit mode burst length is 8 */ - im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); -#endif - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; -#endif - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return msize; -} -#endif/*!CONFIG_SYS_SPD_EEPROM*/ - - -int checkboard (void) -{ - /* - * Warning: do not read the BCSR registers here - * - * There is a timing bug in the 8349E and 8349EA BCSR code - * version 1.2 (read from BCSR 11) that will cause the CFI - * flash initialization code to overwrite BCSR 0, disabling - * the serial ports and gigabit ethernet - */ - - puts("Board: Freescale MPC8349EMDS\n"); - return 0; -} - -/* - * if MPC8349EMDS is soldered with SDRAM - */ -#if defined(CONFIG_SYS_BR2_PRELIM) \ - && defined(CONFIG_SYS_OR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | - LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | - LSDMR_WRC3 | LSDMR_CL3; - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = 0x00000000; - /* LB refresh timer prescal, 266MHz/32 */ - lbc->mrtpr = 0x20000000; - /* LB sdram refresh timer, about 6us */ - lbc->lsrt = 0x32000000; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - - /* 0x40636733; normal operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - - /* 0x68636733; precharge all the banks */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* 0x48636733; auto refresh */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733; mode register write operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* 0x40636733; normal operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void sdram_init(void) -{ -} -#endif - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#ifdef CONFIG_MPC8XXX_SPI - -#define SPI_CS_MASK 0x80000000 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~SPI_CS_MASK; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= SPI_CS_MASK; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c deleted file mode 100644 index 8c76c46d4200f697afc6ff5f02e56c060f09047b..0000000000000000000000000000000000000000 --- a/board/freescale/mpc8349emds/pci.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -#ifndef CONFIG_PCISLAVE -void pib_init(void) -{ - u8 val8, orig_i2c_bus; - /* - * Assign PIB PMC slot to desired PCI bus - */ - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_PCI_64BIT) - val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(CONFIG_PCI_ALL_PCI1) - val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(CONFIG_PCI_ONE_PCI1) - val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ -#else - val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ -#endif - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - -#if defined(CONFIG_PCI_64BIT) - printf("PCI1: 64-bit on PMC2\n"); -#elif defined(CONFIG_PCI_ALL_PCI1) - printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(CONFIG_PCI_ONE_PCI1) - printf("PCI1: 32-bit on PMC1\n"); - printf("PCI2: 32-bit on PMC2, PMC3\n"); -#else - printf("PCI1: 32-bit on PMC1, PMC2\n"); - printf("PCI2: 32-bit on PMC3\n"); -#endif - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); -} - -#endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mx51evk/Kconfig b/board/freescale/mx51evk/Kconfig index f9b69cbd661b520934d027121c8fc0f001eb66b9..a26b539536e7ef2f9db9f642561bc99c93eb30e5 100644 --- a/board/freescale/mx51evk/Kconfig +++ b/board/freescale/mx51evk/Kconfig @@ -12,4 +12,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "mx51evk" +config IMX_CONFIG + default "board/freescale/mx51evk/imximage.cfg" + endif diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index c8439a6347aef08fd09e5c548c1f32e3bfd4c313..46095acedfddb3fa380f2be7fc27afd4c41d7cec 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -35,6 +35,7 @@ int dram_init(void) return 0; } +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { u32 rev = get_cpu_rev(); @@ -42,6 +43,7 @@ u32 get_board_rev(void) rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; return rev; } +#endif #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig index 5ca1672bf7a5a53ac37192ea1bd6eb328d0e427a..a690a601ac0efc5174791bc1f048adc8546b4b17 100644 --- a/board/freescale/mx53loco/Kconfig +++ b/board/freescale/mx53loco/Kconfig @@ -12,4 +12,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "mx53loco" +config IMX_CONFIG + default "board/freescale/mx53loco/imximage.cfg" + endif diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 088863056973b88c7894ce838fac3032f3e9c0c6..a9800ed7698fb981b7a94392a9383ada558051c0 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; @@ -46,6 +47,7 @@ u32 get_board_rev(void) return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } +#endif #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) diff --git a/board/freescale/mx6memcal/Kconfig b/board/freescale/mx6memcal/Kconfig index 9987cba5dcb7aa3962200d55cc148d18b8f40734..2d5c206ae45dec499fa008bf0a65eee0373fa271 100644 --- a/board/freescale/mx6memcal/Kconfig +++ b/board/freescale/mx6memcal/Kconfig @@ -87,12 +87,12 @@ choice help Select the type of DDR (DDR3 or LPDDR2) used on your design -config DDR3 +config DDR3 bool "DDR3" help Select this if your board design uses DDR3. -config LPDDR2 +config LPDDR2 bool "LPDDR2" help Select this if your board design uses LPDDR2. @@ -223,5 +223,8 @@ config REFR details. endmenu -endif +config IMX_CONFIG + default "arch/arm/mach-imx/spl_sd.cfg" + +endif diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c index 1cc744fa9ba024dd79beb350293369e9959d5007..0dfd7dec9efb9b00301d11a1f03799c418152b80 100644 --- a/board/freescale/mx6memcal/mx6memcal.c +++ b/board/freescale/mx6memcal/mx6memcal.c @@ -30,4 +30,3 @@ int dram_init(void) gd->ram_size = imx_ddr_size(); return 0; } - diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index e92ef26d0ad05f3268debb69d5463486739fa4ca..9155dcfbd09d604db2935d276c07eb6ff47b8b1a 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -321,12 +321,14 @@ static void setup_gpmi_nand(void) } #endif +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { int rev = nxp_board_rev(); return (get_cpu_rev() & ~(0xF << 8)) | rev; } +#endif static int ar8031_phy_fixup(struct phy_device *phydev) { diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig index 18482b551e5baff2d8b0f5812df3236ee124180a..e6bbb4194f46858943affed01fa0556684150a78 100644 --- a/board/freescale/mx6slevk/Kconfig +++ b/board/freescale/mx6slevk/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6slevk" +config IMX_CONFIG + default "board/freescale/mx6slevk/imximage.cfg" + endif diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig index 4ba9bbf14180bed126e35c17c9911da096e23fe3..d47f1fa90966448f867eb994f25a1986d0f66890 100644 --- a/board/freescale/mx6sllevk/Kconfig +++ b/board/freescale/mx6sllevk/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sllevk" +config IMX_CONFIG + default "board/freescale/mx6sllevk/imximage.cfg" + endif diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig index ae2ea02439497d87621aca1bd0f8f748bf68e7e0..e6da7b38f914d52a2e05a822abf617c0cbac5572 100644 --- a/board/freescale/mx6sxsabreauto/Kconfig +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabreauto" +config IMX_CONFIG + default "board/freescale/mx6sxsabreauto/imximage.cfg" + endif diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig index fcfac0aae4e7bc780a29874242b1952453669300..88ac7ee8050cb6d4ffac7ddf2c7c500fefd8e971 100644 --- a/board/freescale/mx6sxsabresd/Kconfig +++ b/board/freescale/mx6sxsabresd/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabresd" +config IMX_CONFIG + default "board/freescale/mx6sxsabresd/imximage.cfg" + endif diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig index 7eec497e3ea38cb90e4af024ea4f4f114732a9a7..49aa302553e6504390ff43bb5039f45af3e8f76e 100644 --- a/board/freescale/mx6ullevk/Kconfig +++ b/board/freescale/mx6ullevk/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ullevk" +config IMX_CONFIG + default "board/freescale/mx6ullevk/imximage.cfg" + endif diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig index c6a969ca67ffaa7a171e2f359e592d2b354162af..bf3ceafe2b4bbbfa43e47b0c4b53d4d7db2599ef 100644 --- a/board/freescale/mx7dsabresd/Kconfig +++ b/board/freescale/mx7dsabresd/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx7dsabresd" +config IMX_CONFIG + default "board/freescale/mx7dsabresd/imximage.cfg" + endif diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig index ff448311f9d06f5210fd4e617510dc4575801a4b..591697041dda74bacd1fa9c124691683903ecf9d 100644 --- a/board/freescale/mx7ulp_evk/Kconfig +++ b/board/freescale/mx7ulp_evk/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx7ulp_evk" +config IMX_CONFIG + default "board/freescale/mx7ulp_evk/imximage.cfg" + endif diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 84fc891b67caed845aca761e8a0bad4a1250e81c..c796330f1915a0de05f8ed196a6f2fee22469d50 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -427,7 +427,7 @@ int checkboard(void) dm_i2c_write(dev, 2, &val, 1); #else i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); val = 0x0; /* no polarity inversion */ i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); #endif diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 90188b099a9bfdf04cf3d15f6ea009fac850b403..118468408e2bc47257e0b92e3fa0736a72372c4f 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -99,7 +99,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) env_relocate(); #endif -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) i2c_init_all(); #else i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index dde3f8ca37f640aa07dd48c4ea1691ef1df8f82e..84deb9562a14e7e99bdd64650f90862357c9d796 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features: - One QSGMII interface - Four SGMII interface supporting 1000 Mbps - Three SGMII interfaces supporting up to 2500 Mbps - - 10GbE XFI or 10Base-KR interface + - 10GBase-R or 10Base-KR interface - Additional peripheral interfaces - Two USB 2.0 controllers with integrated PHY - SD/eSDHC/eMMC diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 56e6109288f72fa3681f209f379cb4fe6dfa36f0..4f04d2ee06d6b0ad50ce9e6392af0b6296294c56 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - /* set 10G XFI with Aquantia AQR105 PHY */ + /* set 10GBase-R with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; #endif @@ -103,7 +103,7 @@ int board_eth_init(struct bd_info *bis) #endif fm_info_set_mdio(i, dev); break; - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; @@ -133,12 +133,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { #if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && (port == FM1_DTSEC3)) { fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); fdt_setprop_string(fdt, offset, "phy-connection-type", - "sgmii-2500"); + "2500base-x"); fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); } #endif diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 71566851d01dcfe35df66c71664419ff667d58b4..ac373d7724788f2df6c632feeaa6f1c72871b940 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -30,11 +30,6 @@ unsigned long get_board_sys_clk(void) return CONFIG_SYS_CLK_FREQ; } -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - #if defined(CONFIG_SPL_MMC_BOOT) #define GPIO1_SD_SEL 0x00020000 int board_mmc_getcd(struct mmc *mmc) diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 51a36abe369a4d970590bef089ceb1214a7320e4..ab7675e2090ca857b0fce68d2eca6e3ec4c7c637 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -167,11 +167,6 @@ unsigned long get_board_sys_clk(void) return CONFIG_SYS_CLK_FREQ; } -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - #ifdef CONFIG_TARGET_T1024RDB void board_reset(void) { diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index f5fe73e62dcaef994398d583dbea78690605b269..c7df11100e04371cf3443b0a6d05bb4033115b87 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -30,11 +30,6 @@ unsigned long get_board_sys_clk(void) return CONFIG_SYS_CLK_FREQ; } -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 void board_init_f(ulong bootflag) { diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index d690857f2e28a85150d9f38317aa9a6f57af7f80..75d317342f60c21cd33137a6287715dd004a16c1 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -55,14 +55,14 @@ Memory: - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - - Four 10Gbps XFI on-board cages + - Four 10GBase-R on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: @@ -85,14 +85,14 @@ System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT -XFI: - - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to +10GBase-R: + - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to a on-board SFP+ cages, which to house optical module (fiber cable) or direct attach cable(copper), the copper cable is used to emulate 10GBASE-KR scenario. - So, for XFI usage, there are two scenarios, one will use fiber cable, + So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-Boot + introduced to indicate a 10GBase-R port will use copper cable, and U-Boot will fixup the dtb accordingly. It's used as: fsl_10gkr_copper:<10g_mac_name> The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they @@ -100,10 +100,10 @@ XFI: "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable will be used by default. for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in - hwconfig, then both four XFI ports will use copper cable. + hwconfig, then both four 10GBase-R ports will use copper cable. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two - XFI ports will use copper cable, the other two XFI ports will use fiber - cable. + 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use + fiber cable. 1000BASE-KX(1G-KX): - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane @@ -158,7 +158,6 @@ Start Address End Address Definition Max size 0xE8000000 0xE801FFFF RCW (current bank) 128KB - Software configurations and board settings ------------------------------------------ 1. NOR boot: diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 705387af3c31fac8e2d9bfb15078c230e1b9d046..2d7fc8bdda2ea1a9746151f2e61b2293d0d633de 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { - case 0x66: /* XFI interface */ + case 0x66: /* 10GBase-R interface */ case 0x6b: case 0x6c: case 0x6d: case 0x71: /* - * if the 10G is XFI, check hwconfig to see what is the - * media type, there are two types, fiber or copper, - * fix the dtb accordingly. - */ + * Check hwconfig to see what is the media type, there + * are two types, fiber or copper, fix the dtb + * accordingly. + */ switch (port) { case FM1_10GEC1: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { @@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, printf("Interface %d in backplane KR mode\n", port); } else { - /* fixed-link for XFI fiber cable */ + /* fixed-link for 10GBase-R fiber cable */ f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; @@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis) case 0x66: case 0x67: /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause + * the XAUI card is used for the 10GBase-R MAC, which will cause * error. */ fm_info_set_phy_address(FM1_10GEC1, 4); @@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis) (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { - /* As XFI is in cage intead of a slot, so + /* As 10GBase-R is in cage intead of a slot, so * ensure doesn't disable the corresponding port */ break; diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 715de106d69bd4641ba1ed7e4736df3b6878e19f..e54672a80ba40caca299b2f49874d72813b4aa8d 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void) break; case 0x66: case 0x67: - /* SD1(A:D) => XFI cage + /* SD1(A:D) => 10GBase-R cage * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xfe); break; case 0x6a: case 0x6b: - /* SD1(A:D) => XFI cage + /* SD1(A:D) => 10GBase-R cage * SD1(E) => SLOT1 PCIe4 * SD1(F:H) => SLOT2 SGMII */ @@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void) break; case 0x6c: case 0x6d: - /* SD1(A:B) => XFI cage + /* SD1(A:B) => 10GBase-R cage * SD1(C:D) => SLOT3 SGMII * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xda); break; case 0x6e: - /* SD1(A:B) => SFP Module, XFI + /* SD1(A:B) => SFP Module, 10GBase-R * SD1(C:D) => SLOT3 SGMII * SD1(E:F) => SLOT1 PCIe4 x2 * SD1(G:H) => SLOT2 SGMII diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index 8249c5df967a207af031595bae7af2213ee7336a..d4c061a5eabc48a27c216be4538be8d5b7a19fe2 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -11,7 +11,6 @@ config SYS_CONFIG_NAME config T2080RDB_REV_D bool "Support for T2080RDB revisions D and up" - default n source "board/freescale/common/Kconfig" diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index ec47c96f2b1ac435d5a7190cb06d69b7b54b5bd5..c4bfd3b466f4d16fee985fbb4863987416feb067 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -54,7 +54,7 @@ Differences between T2080 and T2081 T2080PCIe-RDB board Overview ---------------------------- - SERDES Configuration - - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) + - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) @@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview - SerDes-2 Lane G-H: to SATA1 & SATA2 - Ethernet - Two on-board 10M/100M/1G RGMII ethernet ports - - Two on-board 10Gbps XFI fiber ports + - Two on-board 10GBase-R fiber ports - Two on-board 10Gbps Base-T copper ports - DDR Memory - Supports 72bit 4GB DDR3-LP SODIMM diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index b0ce9af0007a5ea9aa4e4f4ac492801aa1b61e6b..2204a98ac8ae136aa28e94dd46d8e8a3c6dcba92 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -29,11 +29,6 @@ unsigned long get_board_sys_clk(void) return CONFIG_SYS_CLK_FREQ; } -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 73ebb4a55bfe87b2198df62f7d515cf5678a8737..3611dbbf3273743b54f9b0fc19392ffb7d429310 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -114,11 +114,6 @@ unsigned long get_board_sys_clk(void) return CONFIG_SYS_CLK_FREQ; } -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - int misc_init_r(void) { u8 reg; diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h index dc3f9f3c26ca38638e89b1f90a861d59a4f45ec3..fcac9244c8ad0d71b5d9bb2a0bbdf3f6ca2eb816 100644 --- a/board/freescale/t4rdb/cpld.h +++ b/board/freescale/t4rdb/cpld.h @@ -45,4 +45,3 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value) \ cpld_write(offsetof(struct cpld_data, reg), value) - diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index c815a3a4fa52561de76f6713b5e1a33a145a7036..34ffaa6aeb5455954c450e7afbdc90bdca45596e 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis) #if (CONFIG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && XFI */ + /* SGMII && 10GBase-R */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index e2f9c9b3de2977f4303523348a42d6368ba63eef..69d1449b070ca0a7e0de78b94a51b1ba70f233da 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -35,11 +35,6 @@ unsigned long get_board_sys_clk(void) return CONFIG_SYS_CLK_FREQ; } -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig index 3b90ed67fe6af272d6f2f57ba52c1e99df66a97f..208c7ae2f425de340dd0801a1a8fe010a43e9b2f 100644 --- a/board/freescale/vf610twr/Kconfig +++ b/board/freescale/vf610twr/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vf610twr" +config IMX_CONFIG + default "board/freescale/vf610twr/imximage.cfg" + endif diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index c0fe2d546f63db3d1838f07ad94ab7b6c55e70fb..70e4dfcfa456068c006bb4e1a041a843c3d6fc27 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -295,12 +295,12 @@ static void set_ether_addr(void) env_set("ethaddr", ethaddr); } -#ifdef CONFIG_REVISION_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG static void set_board_rev(void) { char info[64] = {0, }; - snprintf(info, ARRAY_SIZE(info), "%02x", get_board_rev()); + snprintf(info, ARRAY_SIZE(info), "%02x", get_board_revision()); env_set("board_rev", info); } #endif @@ -310,7 +310,7 @@ static void set_dtb_name(void) char info[64] = {0, }; snprintf(info, ARRAY_SIZE(info), - "s5p4418-nanopi2-rev%02x.dtb", get_board_rev()); + "s5p4418-nanopi2-rev%02x.dtb", get_board_revision()); env_set("dtb_name", info); } @@ -436,7 +436,7 @@ int board_late_init(void) { bd_update_env(); -#ifdef CONFIG_REVISION_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_rev(); #endif set_dtb_name(); diff --git a/board/friendlyarm/nanopi2/hwrev.c b/board/friendlyarm/nanopi2/hwrev.c index b1e23a48a803b3483988fd7b7def12cdd9ab2a00..585e08c944f9c9dcd012701b4582f1366abc3f7d 100644 --- a/board/friendlyarm/nanopi2/hwrev.c +++ b/board/friendlyarm/nanopi2/hwrev.c @@ -80,11 +80,18 @@ void bd_base_rev_init(void) } /* To override __weak symbols */ -u32 get_board_rev(void) +u32 get_board_revision(void) { return (base_rev << 8) | pcb_rev; } +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + return get_board_revision(); +} +#endif + const char *get_board_name(void) { bd_hwrev_init(); diff --git a/board/friendlyarm/nanopi2/hwrev.h b/board/friendlyarm/nanopi2/hwrev.h index 1b1a828afb348a3a1394866ff607bc4ce31aae21..403303131e7f32bd77ecdc5749449c102cd97e5f 100644 --- a/board/friendlyarm/nanopi2/hwrev.h +++ b/board/friendlyarm/nanopi2/hwrev.h @@ -9,7 +9,7 @@ extern void bd_hwrev_init(void); extern void bd_base_rev_init(void); -extern u32 get_board_rev(void); +extern u32 get_board_revision(void); extern const char *get_board_name(void); #endif /* __BD_HW_REV_H__ */ diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 8fa691aefc4fbebead14912515962ce66c62bb4a..360d1d4c123f1dbeeb4be04193bd500da0a94ca8 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -8,4 +8,3 @@ obj-y := gw_ventana.o gsc.o eeprom.o common.o obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o - diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h index 29d375b3a71b32d5a46bef988bd2173c0c89a78a..5c349888280e440c302ecebe190591269d8fa1f5 100644 --- a/board/gateworks/gw_ventana/gsc.h +++ b/board/gateworks/gw_ventana/gsc.h @@ -69,4 +69,3 @@ int gsc_info(int verbose); int gsc_boot_wd_disable(void); const char *gsc_get_dtb_name(int level, char *buf, int sz); #endif - diff --git a/board/gateworks/venice/Kconfig b/board/gateworks/venice/Kconfig index 64cb97c1e0a9462b9cb813106ac5566556cd8525..639bf35d205049b99820fd1123ab94adc5045fbc 100644 --- a/board/gateworks/venice/Kconfig +++ b/board/gateworks/venice/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mm_venice" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + endif diff --git a/board/gdsys/a38x/dt_helpers.c b/board/gdsys/a38x/dt_helpers.c index c859024a28bb5f3e7471caf7881ac66d2db88363..61d30c2e637319a1569da4e540dd56e3347e9bf5 100644 --- a/board/gdsys/a38x/dt_helpers.c +++ b/board/gdsys/a38x/dt_helpers.c @@ -39,4 +39,3 @@ int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name, return dm_gpio_request(gpio, gpio_name); } - diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c index c23d15092144921411819c34536fc33f0d46d5eb..e09c0006b76fa3d115b08ebfdb96e7286dfea3d1 100644 --- a/board/gdsys/a38x/ihs_phys.c +++ b/board/gdsys/a38x/ihs_phys.c @@ -110,9 +110,7 @@ int register_miiphy_bus(uint k, struct mii_dev **bus) if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, - name, - MDIO_NAME_LEN); + strlcpy(mdiodev->name, name, MDIO_NAME_LEN); mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index de4cb0d5afaa2f8c977c7422e3011992fdae61d1..a2cbd1512e9214c6380c68d36047597d628a05e4 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include "../common/vpd_reader.h" diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 7fcebba0260062735a06833e7656b91bc26dc54a..ed700f4e1da532eecb3ae3efbadb592d07d77232 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include #include "../common/ge_rtc.h" diff --git a/board/ge/common/ge_rtc.c b/board/ge/common/ge_rtc.c index 48c3778046f1292c9d2c9458c7c42437d64ed80f..6437afc7bd0aaee59a60cc692b81eb557aa06330 100644 --- a/board/ge/common/ge_rtc.c +++ b/board/ge/common/ge_rtc.c @@ -53,4 +53,3 @@ void check_time(void) else env_set("rtc_status", "OK"); } - diff --git a/board/ge/mx53ppd/Kconfig b/board/ge/mx53ppd/Kconfig index bebb2fab0173d9794fd67818666709f2a157e825..728e9a992118d13f68d9586b3d80dcbbd71736d1 100644 --- a/board/ge/mx53ppd/Kconfig +++ b/board/ge/mx53ppd/Kconfig @@ -1,4 +1,3 @@ - if TARGET_MX53PPD config SYS_BOARD @@ -13,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "mx53ppd" +config IMX_CONFIG + default "board/ge/mx53ppd/imximage.cfg" + source "board/ge/common/Kconfig" endif diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 6174125e728a23f2d0e4435b353ebc12db9f92a8..cc462d53da6a1b2da991efe7c25d7cec43a4c9bf 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include "ppd_gpio.h" #include @@ -81,10 +81,12 @@ int dram_init_banksize(void) return 0; } +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { return get_cpu_rev() & ~(0xF << 8); } +#endif #ifdef CONFIG_USB_EHCI_MX5 int board_ehci_hcd_init(int port) diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index 3240ed62aeb4f82b8e9728a159263db909a796c2..4e2c6ebde73c330a483a0ef3fc452d57c6aff828 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -92,4 +92,3 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays); - diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 85cba50d4e5c11cc50cffd11b1c688d9d5cd1c1a..53c5171d02b4e91f935e2455181a27e0e7e7e220 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -300,7 +300,7 @@ struct sysinfo_ops coral_sysinfo_ops = { .get_str = coral_get_str, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id coral_ids[] = { { .compatible = "google,coral" }, { } diff --git a/board/google/imx8mq_phanbell/Kconfig b/board/google/imx8mq_phanbell/Kconfig index fba2e9ce67218f43001f498ebb16a61829e3c9ff..54cfb99952722abdfdd002fa318baaa386604644 100644 --- a/board/google/imx8mq_phanbell/Kconfig +++ b/board/google/imx8mq_phanbell/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mq_phanbell" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage.cfg" + endif diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 12480f5729d6d4b4e532f567a46a3f8c3df4b9fa..6423c1efb24bbc36ec27412a8cd36c8d4a61d613 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; static __maybe_unused struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ @@ -69,9 +69,7 @@ static void enable_board_pin_mux(void) configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); } -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT void set_uart_mux_conf(void) { configure_module_pin_mux(uart0_pin_mux); @@ -86,7 +84,7 @@ void am33xx_spl_board_init(void) { chilisom_spl_board_init(); } -#endif +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ /* * Basic board specific setup. Pinmux has been handled already. diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index 6cc79d96a139d0cdcf1d7be55ef67f1b6644575e..b89e7e869766d20a00a7b1e20e112d460032e87f 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -195,4 +195,3 @@ int board_init(void) return 0; } - diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c index 7ee175d40a5b092d6f8a581d5436b4670d29315a..7cbe49abd93b6e4395f99502c20e2c81bd781ac9 100644 --- a/board/imgtec/ci20/ci20.c +++ b/board/imgtec/ci20/ci20.c @@ -254,7 +254,7 @@ int checkboard(void) #ifdef CONFIG_SPL_BUILD -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) int board_mmc_init(struct bd_info *bd) { ci20_mux_mmc(); diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index 086d0522c78a40c9bf39e395a979f07c56dd30a8..7dbb3a91432434177f6b821aae914e5342ed6ccd 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; @@ -38,6 +39,7 @@ u32 get_board_rev(void) return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } +#endif struct fsl_esdhc_cfg esdhc_cfg[1] = { {MMC_SDHC1_BASE_ADDR} diff --git a/board/k+p/kp_imx53/Kconfig b/board/k+p/kp_imx53/Kconfig index 017c1e30d882e2426f0b4792d4988f10aba9282d..fb35127696b74bffb96b66416b499ad71dfa7f7f 100644 --- a/board/k+p/kp_imx53/Kconfig +++ b/board/k+p/kp_imx53/Kconfig @@ -12,4 +12,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "kp_imx53" +config IMX_CONFIG + default "board/freescale/mx53loco/imximage.cfg" + endif diff --git a/board/k+p/kp_imx53/kp_id_rev.c b/board/k+p/kp_imx53/kp_id_rev.c index 7103a3e0f2b5b1c332f0d6bf38ae5b074dd62c9f..9f93cf008ce8542b84d7d933f1970694a28ed6b4 100644 --- a/board/k+p/kp_imx53/kp_id_rev.c +++ b/board/k+p/kp_imx53/kp_id_rev.c @@ -64,6 +64,10 @@ void show_eeprom(void) eth_env_set_enetaddr("ethaddr", p); } +#define I2C_EEPROM_BUS_NUM 1 +#define I2C_EEPROM_ADDR 0x50 +#define I2C_EEPROM_ADDR_LEN 2 + int read_eeprom(void) { struct udevice *dev; @@ -72,9 +76,8 @@ int read_eeprom(void) if (eeprom_has_been_read) return 0; - ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + ret = i2c_get_chip_for_busnum(I2C_EEPROM_BUS_NUM, I2C_EEPROM_ADDR, + I2C_EEPROM_ADDR_LEN, &dev); if (ret) { printf("Cannot find EEPROM !\n"); return ret; diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index 14c70b9ad06e019d2ed415cf064c95d096bf5743..ff550f7fe76684b451fc3b6c3ffcf34c3c19f1df 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -346,17 +346,17 @@ int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset) struct udevice *eedev = NULL; ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS, - CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev); + CONFIG_SYS_IVM_EEPROM_ADR, 1, &eedev); if (ret) { printf("failed to get device for EEPROM at address 0x%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); + CONFIG_SYS_IVM_EEPROM_ADR); return 1; } ret = dm_i2c_read(eedev, 0, buf, len); if (ret != 0) { printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n", - CONFIG_SYS_I2C_EEPROM_ADDR, 0); + CONFIG_SYS_IVM_EEPROM_ADR, 0); return 1; } #else diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 25937ee362ff592a8bd29e313288da64c58a5e25..da516918af162f9b6055a2d6ece11d88a95fc9d7 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -290,4 +290,3 @@ int get_scl(void) return qrio_get_gpio(KM_I2C_DEBLOCK_PORT, KM_I2C_DEBLOCK_SCL); } - diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c index 62100b19492d017940920aee4c670d7e6886e3d3..b80672d1b43f9cefa33a7e9a3bc4c1cc84ad0d9d 100644 --- a/board/keymile/km83xx/km83xx_i2c.c +++ b/board/keymile/km83xx/km83xx_i2c.c @@ -15,7 +15,7 @@ static void i2c_write_start_seq(void) { struct fsl_i2c_base *base; base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + - CONFIG_SYS_I2C_OFFSET); + CONFIG_SYS_FSL_I2C_OFFSET); udelay(DELAY_ABORT_SEQ); out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); udelay(DELAY_ABORT_SEQ); @@ -26,7 +26,7 @@ int i2c_make_abort(void) { struct fsl_i2c_base *base; base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + - CONFIG_SYS_I2C_OFFSET); + CONFIG_SYS_FSL_I2C_OFFSET); uchar last; int nbr_read = 0; int i = 0; diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig index 6f55cfab864ebb0adca3c54339b1d43a3b8381a6..c52b365b17574e462538b76b099b98e3f46a4a4e 100644 --- a/board/keymile/km_arm/Kconfig +++ b/board/keymile/km_arm/Kconfig @@ -3,37 +3,31 @@ menu "KM ARM Options" config KM_FPGA_CONFIG bool "FPGA Configuration" - default n help Include capability to change FPGA configuration. config KM_FPGA_FORCE_CONFIG bool "FPGA reconfiguration" - default n help If yes we force to reconfigure the FPGA always config KM_FPGA_NO_RESET bool "FPGA skip reset" - default n help If yes we skip triggering a reset of the FPGA config KM_ENV_IS_IN_SPI_NOR bool "Environment in SPI NOR" - default n help Put the U-Boot environment in the SPI NOR flash. config KM_PIGGY4_88E6061 bool "Piggy via Switch 88E6061" - default n help The Piggy4 board is connected via a Marvell 88E6061 switch. config KM_PIGGY4_88E6352 bool "Piggy via Switch 88E6352" - default n help The Piggy4 board is connected via a Marvell 88E6352 switch. diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index f221f05261aeb32d2ccda8438577d0147eae8e14..9c4c5fdc4a53d04d829e7d11b222b37d90ebb33e 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -30,7 +30,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c index a70166a542e37d4882760517c93126caedcefc3f..86032d7fcdf7b0e876bc6c8b9ed71b0a22e22c52 100644 --- a/board/lg/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -156,11 +156,13 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { /* Sold devices are expected to be at least revision F. */ return 6; } +#endif void get_board_serial(struct tag_serialnr *serialnr) { diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 39f70f578e584090155982830c5e1470f15b9d88..d5fe336d22dec5e144c59226613a63091ae02932 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -273,7 +273,7 @@ static void spl_dram_init(void) #endif } -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI static void displ5_init_ecspi(void) { displ5_set_iomux_ecspi_spl(); @@ -283,7 +283,7 @@ static void displ5_init_ecspi(void) static inline void displ5_init_ecspi(void) { } #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC static struct fsl_esdhc_cfg usdhc_cfg = { .esdhc_base = USDHC4_BASE_ADDR, .max_bus_width = 8, diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 0e5b8326bac7ffbfce995faf90475fa0fce06215..db2134bb9d40e70e16731d06ccae598bd17e474a 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -314,7 +314,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ /* - GPIO30 */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ /* - PEN_IRQ */\ diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile index 337df9247dfddebc539b3b46c9332d66d0c86b3c..dbaf18d3e0b30e83569f3658d09b94bed88e30f6 100644 --- a/board/logicpd/imx6/Makefile +++ b/board/logicpd/imx6/Makefile @@ -7,4 +7,3 @@ # obj-y := imx6logic.o - diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README index 19f79c5734bc544b59561aabc0b7b2fe58ab04a8..9d7b9128c4df5c89e03a13387691d2b44a2dfe9d 100644 --- a/board/logicpd/imx6/README +++ b/board/logicpd/imx6/README @@ -80,4 +80,3 @@ while starting. Additional Support Documentation can be found at: https://support.logicpd.com/ - diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h index 63c2141783e9bb9e34ab8e2f13937ba657962ef2..0de1f2a54e5b1ad404ceefb05de6e30fda754471 100644 --- a/board/logicpd/omap3som/omap3logic.h +++ b/board/logicpd/omap3som/omap3logic.h @@ -243,7 +243,7 @@ void set_muxconf_regs(void) MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/ diff --git a/board/mediatek/mt7620/Kconfig b/board/mediatek/mt7620/Kconfig deleted file mode 100644 index b9137adcc99b1ac45d00800b3545578290007fc3..0000000000000000000000000000000000000000 --- a/board/mediatek/mt7620/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB - -config SYS_BOARD - default "mt7620" - -config SYS_VENDOR - default "mediatek" - -config SYS_CONFIG_NAME - default "mt7620" - -endif diff --git a/board/mediatek/mt7622/Kconfig b/board/mediatek/mt7622/Kconfig deleted file mode 100644 index d0abdc0a676c8be0fa3731bcd3b7db95f2215fdf..0000000000000000000000000000000000000000 --- a/board/mediatek/mt7622/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_MT7622 - -config SYS_BOARD - default "mt7622" - -config SYS_CONFIG_NAME - default "mt7622" - -config MTK_BROM_HEADER_INFO - string - default "lk=1" - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/mediatek/mt7622/Makefile b/board/mediatek/mt7622/Makefile index 2c54d86fffbb7e2572ab61d9ff85150dba347163..64f101337bf16620665cc5d7a308849ba127e107 100644 --- a/board/mediatek/mt7622/Makefile +++ b/board/mediatek/mt7622/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += mt7622_rfb.o - diff --git a/board/mediatek/mt7623/Kconfig b/board/mediatek/mt7623/Kconfig deleted file mode 100644 index a8c670e71f8ce0e5eb469414c969d83e6e91e97c..0000000000000000000000000000000000000000 --- a/board/mediatek/mt7623/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if TARGET_MT7623 - -config SYS_BOARD - default "mt7623" - -config SYS_CONFIG_NAME - default "mt7623" - -config MTK_BROM_HEADER_INFO - string - default "lk=1" - -endif diff --git a/board/mediatek/mt7628/Kconfig b/board/mediatek/mt7628/Kconfig deleted file mode 100644 index d6b6f9d632f4257a5f076964603b36028789c8d5..0000000000000000000000000000000000000000 --- a/board/mediatek/mt7628/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if BOARD_MT7628_RFB - -config SYS_BOARD - default "mt7628" - -config SYS_VENDOR - default "mediatek" - -config SYS_CONFIG_NAME - default "mt7628" - -endif diff --git a/board/mediatek/mt7629/Kconfig b/board/mediatek/mt7629/Kconfig deleted file mode 100644 index 6055164b527c34a4eb9b83c6040746ca593ab93d..0000000000000000000000000000000000000000 --- a/board/mediatek/mt7629/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_MT7629 - -config SYS_BOARD - default "mt7629" - -config SYS_CONFIG_NAME - default "mt7629" - -config MTK_SPL_PAD_SIZE - hex - default 0x10000 - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/mediatek/mt8183/Kconfig b/board/mediatek/mt8183/Kconfig deleted file mode 100644 index b75c3b8d8069062f691e33ccf1d510bd9ca1e9a9..0000000000000000000000000000000000000000 --- a/board/mediatek/mt8183/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if TARGET_MT8183 - -config SYS_BOARD - default "mt8183" - -config SYS_CONFIG_NAME - default "mt8183" - -config MTK_BROM_HEADER_INFO - string - default "media=emmc" - -endif diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig deleted file mode 100644 index 87bd1fbe69c1aa24be92cf87d35a123714881485..0000000000000000000000000000000000000000 --- a/board/mediatek/mt8512/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_MT8512 - -config SYS_BOARD - default "mt8512" - -config SYS_CONFIG_NAME - default "mt8512" - - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/mediatek/mt8516/Kconfig b/board/mediatek/mt8516/Kconfig deleted file mode 100644 index a87d3872fe6e3bd5c241d034f43d9c64e1b3bf6a..0000000000000000000000000000000000000000 --- a/board/mediatek/mt8516/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if TARGET_MT8516 - -config SYS_BOARD - default "mt8516" - -config SYS_CONFIG_NAME - default "mt8516" - -config MTK_BROM_HEADER_INFO - string - default "media=emmc" - -endif diff --git a/board/mediatek/mt8518/Kconfig b/board/mediatek/mt8518/Kconfig deleted file mode 100644 index 1971c4d8c3e0609f99747ed6cc7d32f66501aece..0000000000000000000000000000000000000000 --- a/board/mediatek/mt8518/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_MT8518 - -config SYS_BOARD - default "mt8518" - -config SYS_CONFIG_NAME - default "mt8518" - - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/menlo/m53menlo/Kconfig b/board/menlo/m53menlo/Kconfig index 1953f5041b80ca17f856e363cc7194180eaf773f..34c92f4521264b82ddaf861739ae04ff1bff1ac5 100644 --- a/board/menlo/m53menlo/Kconfig +++ b/board/menlo/m53menlo/Kconfig @@ -12,4 +12,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "m53menlo" +config IMX_CONFIG + default "board/menlo/m53menlo/imximage.cfg" + endif diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c index 779bc646b2abab7069c3c1b0611fc564fc39b2f4..1649bee063cbedb92acc78a70b9a39cf822d7918 100644 --- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c +++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c @@ -2,4 +2,3 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ - diff --git a/board/mscc/jr2/Makefile b/board/mscc/jr2/Makefile index c1db2a9045138c2771e93739d81a5eb7ad2df8d3..56fd8d913e6db86e8282c9a09f7792deb72fdb9e 100644 --- a/board/mscc/jr2/Makefile +++ b/board/mscc/jr2/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: (GPL-2.0+ OR MIT) obj-$(CONFIG_SOC_JR2) := jr2.o - diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile index 9f28c81268794ea4e41159122e5f2154b35f669e..39ce9601b97fffaf527bb665d2ba549eef5e27f2 100644 --- a/board/mscc/ocelot/Makefile +++ b/board/mscc/ocelot/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: (GPL-2.0+ OR MIT) obj-$(CONFIG_SOC_OCELOT) := ocelot.o - diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index fd3cec8358aaf9ec798b749bc5de25722784f333..99ca36fbbea13292983d97d97cda17cfb1f94da8 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -241,6 +241,7 @@ int board_init(void) return 0; } +#ifdef CONFIG_REVISION_TAG /* * Routine: get_board_revision * Description: Return board revision. @@ -249,6 +250,7 @@ u32 get_board_rev(void) { return simple_strtol(hw_build_ptr, NULL, 16); } +#endif /* * Routine: setup_board_tags diff --git a/board/novtech/meerkat96/Kconfig b/board/novtech/meerkat96/Kconfig index b0e46fcc1b3f5c48b7a5e51510b4ce5c3216a5f2..23b0ba3230e54abffec73ca78b5bc227cb1ba80c 100644 --- a/board/novtech/meerkat96/Kconfig +++ b/board/novtech/meerkat96/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "meerkat96" +config IMX_CONFIG + default "board/novtech/meerkat96/imximage.cfg" + endif diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index b88aa8e964143b08527101657cfd6a387616164a..829751112f1c05a586e6c20951d537d86b88eb7b 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -16,7 +16,7 @@ #include /* TODO: Remove this code when the SPI switch is working */ -#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) +#ifndef CONFIG_TARGET_VENTANA void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c index 80f2b83b58992834afe12cb7c033d34d2d4abb9c..0cbfc08183cbe1895d0aa314d79c5dfa1b89b8bc 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c @@ -289,4 +289,3 @@ int ps7_init(void) return ret; return PS7_INIT_SUCCESS; } - diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index 4fde21c586d80273aefd2db0e7dac1189da02eea..23f2565f9f430a68335cbf3494904914d1fa535e 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -13,6 +13,9 @@ config PCM052_DDR_SIZE int default 256 +config IMX_CONFIG + default "board/phytec/pcm052/imximage.cfg" + endif if TARGET_BK4R1 @@ -30,4 +33,7 @@ config PCM052_DDR_SIZE int default 512 +config IMX_CONFIG + default "board/phytec/pcm052/imximage.cfg" + endif diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig index 92f5524bdb0760f643f229b348e0d82c51d4435a..9868e984875e0117b838f1b430d3f810b8b10819 100644 --- a/board/phytec/phycore_imx8mm/Kconfig +++ b/board/phytec/phycore_imx8mm/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "phycore_imx8mm" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + endif diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index 7a20d6e8fe44479bc864aa350f23b623de758d83..c053a46fc9d1b1b936a31ee9e61eef5788fffb50 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "phycore_imx8mp" +config IMX_CONFIG + default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" + endif diff --git a/board/phytium/durian/Makefile b/board/phytium/durian/Makefile index c2fbf19838d943b0b0e551bcb718df9589102a13..8637ba4afcef0defb72c21d59101c23414c5ea3c 100644 --- a/board/phytium/durian/Makefile +++ b/board/phytium/durian/Makefile @@ -6,4 +6,3 @@ # obj-y += durian.o - diff --git a/board/phytium/durian/cpu.h b/board/phytium/durian/cpu.h index a5a213d30cdf71515eb11cc20156ffdf9217b624..696731ede1819727f9734c9fed155554dff2e9c4 100644 --- a/board/phytium/durian/cpu.h +++ b/board/phytium/durian/cpu.h @@ -20,4 +20,3 @@ #define HNF_BASE (unsigned long)(0x3A200000) #endif /* _FT_DURIAN_H */ - diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index ef13f7cff4800462ac9ed2cce1cc1757a8e440bd..ee484749bcf1b05581e434f7b0e122987c8dea0c 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -113,4 +113,3 @@ int last_stage_init(void) } return ret; } - diff --git a/board/ppcag/bg0900/Kconfig b/board/ppcag/bg0900/Kconfig deleted file mode 100644 index d7f2368a230d9960fb1465432778bc1a9a98a10e..0000000000000000000000000000000000000000 --- a/board/ppcag/bg0900/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BG0900 - -config SYS_BOARD - default "bg0900" - -config SYS_VENDOR - default "ppcag" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "bg0900" - -endif diff --git a/board/ppcag/bg0900/MAINTAINERS b/board/ppcag/bg0900/MAINTAINERS deleted file mode 100644 index 853c0d59c8d1d27f9e35f06d5c75d3ea8d3f6c91..0000000000000000000000000000000000000000 --- a/board/ppcag/bg0900/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BG0900 BOARD -M: Marek Vasut -S: Maintained -F: board/ppcag/bg0900/ -F: include/configs/bg0900.h -F: configs/bg0900_defconfig diff --git a/board/ppcag/bg0900/Makefile b/board/ppcag/bg0900/Makefile deleted file mode 100644 index 540bd9dc12f7de86c31032f2b988d5ee69916fc8..0000000000000000000000000000000000000000 --- a/board/ppcag/bg0900/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := bg0900.o -else -obj-y := spl_boot.o -endif diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c deleted file mode 100644 index 578f5c73b6cbb978f5ca43c4d31f86deffea23f9..0000000000000000000000000000000000000000 --- a/board/ppcag/bg0900/bg0900.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PPC-AG BG0900 board - * - * Copyright (C) 2013 Marek Vasut - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - - /* BG0900 uses ENET_CLK PAD to drive FEC clock */ - writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); - - /* Reset FEC PHYs */ - gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); - udelay(200); - gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - puts("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - return ret; -} - -#endif diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c deleted file mode 100644 index b46bc8939a38dcd3bb562cc8f7d6839e419ed1d1..0000000000000000000000000000000000000000 --- a/board/ppcag/bg0900/spl_boot.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PPC-AG BG0900 Boot setup - * - * Copyright (C) 2013 Marek Vasut - */ - -#include -#include -#include -#include -#include -#include - -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* FEC0 Reset */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for SPI flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), -}; - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* - * DDR Controller Registers - * Manufacturer: Winbond - * Device Part Number: W972GG6JB-25I - * Clock Freq.: 200MHz - * Density: 2Gb - * Chip Selects: 1 - * Number of Banks: 8 - * Row address: 14 - * Column address: 10 - */ - - dram_vals[0x74 / 4] = 0x0102010A; - dram_vals[0x98 / 4] = 0x04005003; - dram_vals[0x9c / 4] = 0x090000c8; - - dram_vals[0xa8 / 4] = 0x0036b009; - dram_vals[0xac / 4] = 0x03270612; - - dram_vals[0xb0 / 4] = 0x02020202; - dram_vals[0xb4 / 4] = 0x00c80029; - - dram_vals[0xc0 / 4] = 0x00011900; - - dram_vals[0x12c / 4] = 0x07400300; - dram_vals[0x130 / 4] = 0x07400300; - dram_vals[0x2c4 / 4] = 0x02030303; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/qca/ap152/ap152.c b/board/qca/ap152/ap152.c index 1064705d2625ce18dc40159f8283fa68bbe40b16..82458c3af421ce46b9cc2c6afdf98813aec5a39c 100644 --- a/board/qca/ap152/ap152.c +++ b/board/qca/ap152/ap152.c @@ -66,7 +66,7 @@ int board_early_init_f(void) void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, MAP_NOCACHE); -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) /* CPU:775, DDR:650, AHB:258 */ qca956x_pll_init(); qca956x_ddr_init(); diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index 4ccb1a07508bf1023a13c336f3850f44497f5cf4..f9cc762a25cd5ba7a90e18e201710d65efb23941 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -73,7 +73,7 @@ static void sdhci_power_init(void) /* drive strength configs for sdhc pins */ const struct tlmm_cfg hdrv[] = { - + { SDC1_CLK_HDRV, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, }, { SDC1_CMD_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, }, { SDC1_DATA_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, }, @@ -81,14 +81,14 @@ static void sdhci_power_init(void) /* pull configs for sdhc pins */ const struct tlmm_cfg pull[] = { - + { SDC1_CLK_PULL, TLMM_NO_PULL, TLMM_PULL_MASK, }, { SDC1_CMD_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, }, { SDC1_DATA_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, }, }; const struct tlmm_cfg rclk[] = { - + { SDC1_RCLK_PULL, TLMM_PULL_DOWN, TLMM_PULL_MASK,}, }; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 372b26b6f2c05f8f2212ce57f83fa446ff99f7bb..0c7d58d18db2d21a628d16f8b07e6320da94b4b2 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -419,7 +419,7 @@ int misc_init_r(void) return 0; } -static void get_board_rev(void) +static void get_board_revision(void) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1); int ret; @@ -478,7 +478,7 @@ int board_init(void) hw_watchdog_init(); #endif - get_board_rev(); + get_board_revision(); gd->bd->bi_boot_params = 0x100; diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 3d00652a8d14ecb9d0135592a618302efea2fc53..71efeaf31319235a344ff8b443baafc4c8832b12 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { -#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/grpeach/lowlevel_init.S index 9a66dfa6c6936b0564a94b489ffadcf7d021c5d6..b83c4e8686709a923c8bde73b07bae3550cfe435 100644 --- a/board/renesas/grpeach/lowlevel_init.S +++ b/board/renesas/grpeach/lowlevel_init.S @@ -4,7 +4,6 @@ * Copyright (C) 2017 Chris Brandt */ #include -#include #include /* Watchdog Registers */ diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index d4752e57982d8b2e7e599813d9858178e36887f5..c27eb3f17d9cd2ff1773d01d7c4e817cce1dfa4a 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { -#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif @@ -75,7 +75,7 @@ int board_init(void) void reset_cpu(void) { -#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); #else /* only CA57 ? */ diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 4626d223b074a8954c7f53857d69ae804f5fa2f3..1477750f9217dad560bc9e3a36d1e219ea2b52b9 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { -#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c index c64c62f7b0f5586b4c85e5d2ec3695dcda96d349..0b14b241b30431af38b15dd30eff2082362d529d 100644 --- a/board/rockchip/evb_rk3229/evb_rk3229.c +++ b/board/rockchip/evb_rk3229/evb_rk3229.c @@ -7,4 +7,3 @@ #include #include #include - diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index 779bc646b2abab7069c3c1b0611fc564fc39b2f4..1649bee063cbedb92acc78a70b9a39cf822d7918 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -2,4 +2,3 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ - diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index 779bc646b2abab7069c3c1b0611fc564fc39b2f4..1649bee063cbedb92acc78a70b9a39cf822d7918 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -2,4 +2,3 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ - diff --git a/board/ronetix/imx8mq-cm/Kconfig b/board/ronetix/imx8mq-cm/Kconfig index 9dd6a86add174dc0fdb87eaad33b4ec0b9fdb682..f0a240cc0d15b2557f4bd9f4413ec867eeab96c5 100644 --- a/board/ronetix/imx8mq-cm/Kconfig +++ b/board/ronetix/imx8mq-cm/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mq_cm" +config IMX_CONFIG + default "board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg" + endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 1c2fe025e89c2d7a8e776816cc4ea8e23e759d94..97791aaeffe2e1047381adc02d9c2a6f76bcd786 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -185,7 +185,7 @@ int board_early_init_f(void) } #endif -#if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC) +#if CONFIG_IS_ENABLED(POWER_LEGACY) || CONFIG_IS_ENABLED(DM_PMIC) int power_init_board(void) { set_ps_hold_ctrl(); diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index e2d5a7c9ba7743589990a9f517bcb7cc83d7e32e..554fc91cc1a36c799f19fb39c24f52522081131b 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -47,18 +47,6 @@ struct odroid_rev_info odroid_info[] = { { EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" }, }; -static unsigned int odroid_get_rev(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { - if (odroid_info[i].board_type == gd->board_type) - return odroid_info[i].board_rev; - } - - return 0; -} - /* * Read ADC at least twice and check the resuls. If regulator providing voltage * on to measured point was just turned on, first reads might require time @@ -200,6 +188,19 @@ bool board_is_generic(void) return false; } +#ifdef CONFIG_REVISION_TAG +static unsigned int odroid_get_rev(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { + if (odroid_info[i].board_type == gd->board_type) + return odroid_info[i].board_rev; + } + + return 0; +} + /** * get_board_rev() - return detected board revision. * @@ -212,6 +213,7 @@ u32 get_board_rev(void) return odroid_get_rev(); } +#endif /** * get_board_type() - returns board type string. diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index b32b82fc2dadbee80e5dcb590f6e98a6ca393353..ba25ba27b8630a830c4f6a593d95e333eae8c63d 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -24,11 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { /* Set Initial global variables */ diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index e17454ad77da3e743de26f70670f80f517324bfb..7a91f448969b2dc4ba0a4aa59e9c3321913ba15a 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -12,11 +12,6 @@ #include #include -u32 get_board_rev(void) -{ - return 0; -} - int exynos_init(void) { return 0; diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 59e6fbf4b002e9af9535405c491124cdb7a216c3..a03dc8738579f066ca622d9ac02e04c215bdfe9f 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -67,10 +67,12 @@ static void check_hw_revision(void) board_rev = modelrev << 8; } +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { return board_rev; } +#endif static inline u32 get_model_rev(void) { diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 9ef11b8471caf3add95d847c6da5c866a8856d02..3764b5478b79ab07c03386414459f93f6d565261 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -33,10 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; unsigned int board_rev; static int init_pmic_lcd(void); +#ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { return board_rev; } +#endif int exynos_power_init(void) { diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index dcd73451a34876d744f7a77353a12bddd8989c63..5d9a945d64c0d27e7feffbbe250f2c1a2ae5ae2a 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -26,7 +26,10 @@ gd_t *gd; #if !CONFIG_IS_ENABLED(OF_PLATDATA) -/* Add a simple GPIO device */ +/* + * Add a simple GPIO device (don't use with of-platdata as it interferes with + * the auto-generated devices) + */ U_BOOT_DRVINFO(gpio_sandbox) = { .name = "sandbox_gpio", }; diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index 21c3ef9094159f8db31befb04fc4fa4a065ba2ee..c5a28ff0220a92a2c99b56d5194276faa39b6597 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -9,6 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "giedi" +config IMX_CONFIG + default "board/siemens/capricorn/imximage.cfg" endif if TARGET_DENEB @@ -22,4 +24,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "deneb" +config IMX_CONFIG + default "board/siemens/capricorn/imximage.cfg" + endif diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 1bdf404ac3ebcf12ab5a4a2aa469308adc3dc2f7..56283660d37754115b1949e4fbb6f083623db3ed 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -70,6 +70,7 @@ void sdram_init(void) #endif /* #ifdef CONFIG_SPL_BUILD */ #ifndef CONFIG_SPL_BUILD +#define FACTORYSET_EEPROM_ADDR 0x50 /* * Basic board specific setup. Pinmux has been handled already. */ @@ -87,7 +88,7 @@ int board_init(void) gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FACTORYSET - factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); + factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR); #endif gpmc_init(); diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index af35bc188e318fcc29cc8cc285eb24159bda5ab8..f898bba4b0eea9bbb9f3cb78c2c655388978ba8d 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -132,12 +132,16 @@ struct am335x_nand_geometry { u8 nand_bus; }; +#define EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + static int draco_read_nand_geometry(void) { struct am335x_nand_geometry geo; /* Read NAND geometry */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2, + if (i2c_read(EEPROM_ADDR, 0x80, 2, (uchar *)&geo, sizeof(struct am335x_nand_geometry))) { printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n"); return -EIO; @@ -160,20 +164,20 @@ static int draco_read_nand_geometry(void) static int read_eeprom(void) { /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + if (i2c_probe(EEPROM_ADDR)) { printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); return 1; } #ifdef CONFIG_SPL_BUILD /* Read Siemens eeprom data (DDR3) */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); set_default_ddr3_timings(); } /* Read Siemens eeprom data (CHIP) */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, (uchar *)&settings.chip, sizeof(settings.chip))) printf("Could not read chip settings\n"); diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..8f634c172c128bdd442edfe2c50c70e534ec8efe --- /dev/null +++ b/board/siemens/iot2050/Kconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) Siemens AG, 2018-2021 +# +# Authors: +# Le Jin +# Jan Kiszka + +config TARGET_IOT2050_A53 + bool "IOT2050 running on A53" + select ARM64 + select SOC_K3_AM6 + select BOARD_LATE_INIT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +if TARGET_IOT2050_A53 + +config SYS_BOARD + default "iot2050" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "iot2050" + +config IOT2050_BOOT_SWITCH + bool "Disable eMMC boot via USER button (Advanced version only)" + default y + +endif diff --git a/board/siemens/iot2050/MAINTAINERS b/board/siemens/iot2050/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..1b525356c2d614a16f63d9eb277b81d9c35d1bc8 --- /dev/null +++ b/board/siemens/iot2050/MAINTAINERS @@ -0,0 +1,9 @@ +IOT2050 BOARD +M: Le Jin +M: Jan Kiszka +S: Maintained +F: board/siemens/iot2050/ +F: include/configs/iot2050.h +F: configs/iot2050_defconfig +F: arch/arm/dts/iot2050-* +F: doc/board/siemens/iot2050.rst diff --git a/board/siemens/iot2050/Makefile b/board/siemens/iot2050/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..619594ab8e1daab9e332cafa306cb7c0ee141ae6 --- /dev/null +++ b/board/siemens/iot2050/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile for Siemens IOT2050 board +# Copyright (c) Siemens AG, 2018-2021 +# +# Authors: +# Le Jin +# + +obj-y += board.o diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c new file mode 100644 index 0000000000000000000000000000000000000000..b2110978ae053353c2abcf9e8696dfe1f245feb0 --- /dev/null +++ b/board/siemens/iot2050/board.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for IOT2050 + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin + * Jan Kiszka + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOT2050_INFO_MAGIC 0x20502050 + +struct iot2050_info { + u32 magic; + u16 size; + char name[20 + 1]; + char serial[16 + 1]; + char mlfb[18 + 1]; + char uuid[32 + 1]; + char a5e[18 + 1]; + u8 mac_addr_cnt; + u8 mac_addr[8][ARP_HLEN]; + char seboot_version[40 + 1]; +} __packed; + +/* + * Scratch SRAM (available before DDR RAM) contains extracted EEPROM data. + */ +#define IOT2050_INFO_DATA ((struct iot2050_info *) \ + TI_SRAM_SCRATCH_BOARD_EEPROM_START) + +DECLARE_GLOBAL_DATA_PTR; + +static bool board_is_advanced(void) +{ + struct iot2050_info *info = IOT2050_INFO_DATA; + + return info->magic == IOT2050_INFO_MAGIC && + strstr((char *)info->name, "IOT2050-ADVANCED") != NULL; +} + +static bool board_is_sr1(void) +{ + struct iot2050_info *info = IOT2050_INFO_DATA; + + return info->magic == IOT2050_INFO_MAGIC && + !strstr((char *)info->name, "-PG2"); +} + +static void remove_mmc1_target(void) +{ + char *boot_targets = strdup(env_get("boot_targets")); + char *mmc1 = strstr(boot_targets, "mmc1"); + + if (mmc1) { + memmove(mmc1, mmc1 + 4, strlen(mmc1 + 4) + 1); + env_set("boot_targets", boot_targets); + } + + free(boot_targets); +} + +void set_board_info_env(void) +{ + struct iot2050_info *info = IOT2050_INFO_DATA; + u8 __maybe_unused mac_cnt; + const char *fdtfile; + + if (info->magic != IOT2050_INFO_MAGIC) { + pr_err("IOT2050: Board info parsing error!\n"); + return; + } + + if (env_get("board_uuid")) + return; + + env_set("board_name", info->name); + env_set("board_serial", info->serial); + env_set("mlfb", info->mlfb); + env_set("board_uuid", info->uuid); + env_set("board_a5e", info->a5e); + env_set("fw_version", PLAIN_VERSION); + env_set("seboot_version", info->seboot_version); + + if (IS_ENABLED(CONFIG_NET)) { + /* set MAC addresses to ensure forwarding to the OS */ + for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) { + if (is_valid_ethaddr(info->mac_addr[mac_cnt])) + eth_env_set_enetaddr_by_index("eth", + mac_cnt + 1, + info->mac_addr[mac_cnt]); + } + } + + if (board_is_advanced()) { + if (board_is_sr1()) + fdtfile = "ti/k3-am6548-iot2050-advanced.dtb"; + else + fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb"; + } else { + if (board_is_sr1()) + fdtfile = "ti/k3-am6528-iot2050-basic.dtb"; + else + fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb"; + /* remove the unavailable eMMC (mmc1) from the list */ + remove_mmc1_target(); + } + env_set("fdtfile", fdtfile); + + env_save(); +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (board_is_advanced()) + gd->ram_size = SZ_2G; + else + gd->ram_size = SZ_1G; + + return 0; +} + +int dram_init_banksize(void) +{ + dram_init(); + + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + /* Bank 1 declares the memory available in the DDR high region */ + gd->bd->bi_dram[1].start = 0; + gd->bd->bi_dram[1].size = 0; + + return 0; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + struct iot2050_info *info = IOT2050_INFO_DATA; + char upper_name[32]; + + if (info->magic != IOT2050_INFO_MAGIC || + strlen(name) >= sizeof(upper_name)) + return -1; + + str_to_upper(name, upper_name, sizeof(upper_name)); + if (!strcmp(upper_name, (char *)info->name)) + return 0; + + return -1; +} +#endif + +int do_board_detect(void) +{ + return 0; +} + +#ifdef CONFIG_IOT2050_BOOT_SWITCH +static bool user_button_pressed(void) +{ + struct udevice *red_led = NULL; + unsigned long count = 0; + struct gpio_desc gpio; + + memset(&gpio, 0, sizeof(gpio)); + + if (dm_gpio_lookup_name("25", &gpio) < 0 || + dm_gpio_request(&gpio, "USER button") < 0 || + dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN) < 0) + return false; + + if (dm_gpio_get_value(&gpio) == 1) + return false; + + printf("USER button pressed - booting from external media only\n"); + + led_get_by_label("status-led-red", &red_led); + + if (red_led) + led_set_state(red_led, LEDST_ON); + + while (dm_gpio_get_value(&gpio) == 0 && count++ < 10000) + mdelay(1); + + if (red_led) + led_set_state(red_led, LEDST_OFF); + + return true; +} +#endif + +#define SERDES0_LANE_SELECT 0x00104080 + +int board_late_init(void) +{ + /* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */ + writel(0x3, SERDES0_LANE_SELECT); + + set_board_info_env(); + + /* remove the eMMC if requested via button */ + if (IS_ENABLED(CONFIG_IOT2050_BOOT_SWITCH) && board_is_advanced() && + user_button_pressed()) + remove_mmc1_target(); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int ret; + + ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000"); + if (ret < 0) + ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", + "sram@70000000"); + if (ret) + pr_err("%s: fixing up msmc ram failed %d\n", __func__, ret); + + return ret; +} +#endif + +void spl_board_init(void) +{ +} + +#if CONFIG_IS_ENABLED(LED) && CONFIG_IS_ENABLED(BOOTSTAGE) +/* + * Indicate any error or (accidental?) entering of CLI via the red status LED. + */ +void show_boot_progress(int progress) +{ + struct udevice *dev; + int ret; + + if (progress < 0 || progress == BOOTSTAGE_ID_ENTER_CLI_LOOP) { + ret = led_get_by_label("status-led-green", &dev); + if (ret == 0) + led_set_state(dev, LEDST_OFF); + + ret = led_get_by_label("status-led-red", &dev); + if (ret == 0) + led_set_state(dev, LEDST_ON); + } +} +#endif diff --git a/board/siemens/iot2050/config.mk b/board/siemens/iot2050/config.mk new file mode 100644 index 0000000000000000000000000000000000000000..267ec76c4ef181b58b5993e3e1091b2cab908033 --- /dev/null +++ b/board/siemens/iot2050/config.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) Siemens AG, 2020-2021 +# +# Authors: +# Jan Kiszka + +flash.bin: all diff --git a/board/sifive/unleashed/genimage_sdcard.cfg b/board/sifive/unleashed/genimage_sdcard.cfg new file mode 100644 index 0000000000000000000000000000000000000000..91c53bf855e4d5111e0cb5ab484a60e760a9e049 --- /dev/null +++ b/board/sifive/unleashed/genimage_sdcard.cfg @@ -0,0 +1,19 @@ +image sdcard.img { + size = 128M + + hdimage { + gpt = true + } + + partition u-boot-spl { + image = "u-boot-spl.bin" + offset = 17K + partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47 + } + + partition u-boot { + image = "u-boot.itb" + offset = 1041K + partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985 + } +} diff --git a/board/sifive/unleashed/genimage_spi-nor.cfg b/board/sifive/unleashed/genimage_spi-nor.cfg new file mode 100644 index 0000000000000000000000000000000000000000..2e5d89bfe862bb6aae5d6ae8c69dfa74d0cb9391 --- /dev/null +++ b/board/sifive/unleashed/genimage_spi-nor.cfg @@ -0,0 +1,19 @@ +image spi-nor.img { + size = 32M + + hdimage { + gpt = true + } + + partition u-boot-spl { + image = "u-boot-spl.bin" + offset = 20K + partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47 + } + + partition u-boot { + image = "u-boot.itb" + offset = 1044K + partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985 + } +} diff --git a/board/softing/vining_2000/Kconfig b/board/softing/vining_2000/Kconfig index 90d45a7f6e85d531799daf91aeef0120188247ab..36b20f805a7616f439c076d070b76ff39dcd87b7 100644 --- a/board/softing/vining_2000/Kconfig +++ b/board/softing/vining_2000/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vining_2000" +config IMX_CONFIG + default "board/softing/vining_2000/imximage.cfg" + endif diff --git a/board/somlabs/visionsom-6ull/Kconfig b/board/somlabs/visionsom-6ull/Kconfig index 37408aa798b0cbea9e9a5a9e057a84a28e5b137f..374d427ee5b5a14d13cc6619cae42eddc7615077 100644 --- a/board/somlabs/visionsom-6ull/Kconfig +++ b/board/somlabs/visionsom-6ull/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "somlabs_visionsom_6ull" +config IMX_CONFIG + default "board/somlabs/visionsom-6ull/imximage.cfg" + endif diff --git a/board/somlabs/visionsom-6ull/visionsom-6ull.c b/board/somlabs/visionsom-6ull/visionsom-6ull.c index c26e7b0555ea922060bd18be96fb2111b8af00cf..38d14f6bc268d18226a86d0d0fb788e8f0246bc2 100644 --- a/board/somlabs/visionsom-6ull/visionsom-6ull.c +++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c @@ -104,7 +104,7 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 46fcf907fc621083e149df2f4f902e9f66f19b76..34f9d6bc007afd3d2ade0c07e3f9b061fd17059b 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -46,11 +46,6 @@ int dram_init_banksize(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 3b6df1f3ab369d8c8bbfc013730f82d109850694..c170314ed8576d25e6bcb17739f47fd91a8ab71e 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -40,11 +40,6 @@ int dram_init_banksize(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index c5df9b0d9c07c0aa6467df0bb3e0455941d392bc..122273a2ae7984612d1b291428dda942f8575d06 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -40,11 +40,6 @@ int dram_init_banksize(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index efa38a0e26a6188761a59563f506560e2228b6bb..376bc06a980cd7fdfd92986a453d6882cb5978d0 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -77,12 +77,7 @@ u32 spl_boot_device(void) { return BOOT_DEVICE_XIP; } - #endif -u32 get_board_rev(void) -{ - return 0; -} int board_late_init(void) { diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 4091d5f9fde5b9df590f3204f6ffc31bd426c30d..cc8723002656e05da71c911af4be00aa1420a823 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -36,11 +36,6 @@ int dram_init_banksize(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 4091d5f9fde5b9df590f3204f6ffc31bd426c30d..cc8723002656e05da71c911af4be00aa1420a823 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -36,11 +36,6 @@ int dram_init_banksize(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 5785b2e5750f71c790fa887960f7b60915b0b136..0ece8e79f2038412eb368605c34c9080dd658434 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -41,11 +41,6 @@ int board_early_init_f(void) return 0; } -u32 get_board_rev(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 032f08d7950c1ef1d8ff3138d7d9546860df1222..1d4d7b4b59c92e1dfb72fbb099620e2e14227a7f 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -235,10 +236,10 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) static int get_led(struct udevice **dev, char *led_string) { - char *led_name; + const char *led_name; int ret; - led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); + led_name = ofnode_conf_read_str(led_string); if (!led_name) { log_debug("could not find %s config string\n", led_string); return -ENOENT; diff --git a/board/ste/stemmy/MAINTAINERS b/board/ste/stemmy/MAINTAINERS index 37daabea9c4196426a9b804682bd91a35eb5642e..fa064882843b1159d9c25a3558dd8bbf7f484c59 100644 --- a/board/ste/stemmy/MAINTAINERS +++ b/board/ste/stemmy/MAINTAINERS @@ -2,5 +2,6 @@ STEMMY BOARD M: Stephan Gerhold S: Maintained F: board/ste/stemmy/ -F: include/configs/stemmy.h F: configs/stemmy_defconfig +F: doc/board/ste/stemmy.rst +F: include/configs/stemmy.h diff --git a/board/ste/stemmy/README b/board/ste/stemmy/README deleted file mode 100644 index 1b83b833c048f99ebd78a1e07a8a82c481a44e54..0000000000000000000000000000000000000000 --- a/board/ste/stemmy/README +++ /dev/null @@ -1,50 +0,0 @@ -ST-Ericsson U8500 Samsung "stemmy" board -======================================== - -The "stemmy" board supports Samsung smartphones released with -the ST-Ericsson NovaThor U8500 SoC, e.g. - - - Samsung Galaxy S III mini (GT-I8190) "golden" - - Samsung Galaxy S Advance (GT-I9070) "janice" - - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" - - Samsung Galaxy Ace 2 (GT-I8160) "codina" - -and likely others as well (untested). - -At the moment, U-Boot is intended to be chain-loaded from -the original Samsung bootloader, not replacing it entirely. - -Installation ------------- - -1. Setup cross compiler, e.g. export CROSS_COMPILE=arm-none-eabi- -2. make stemmy_defconfig -3. make - -For newer devices (golden and skomer), the U-Boot binary has to be packed into -an Android boot image. janice boots the raw U-Boot binary from the boot partition. - -4. Obtain mkbootimg, e.g. https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg -5. mkbootimg \ - --kernel=u-boot.bin \ - --base=0x00000000 \ - --kernel_offset=0x00100000 \ - --ramdisk_offset=0x02000000 \ - --tags_offset=0x00000100 \ - --output=u-boot.img - -6. Enter Samsung download mode (press Power + Home + Volume Down) -7. Flash U-Boot image to Android boot partition using Heimdall: - https://gitlab.com/BenjaminDobell/Heimdall - - heimdall flash --Kernel u-boot.(bin|img) - -8. After reboot U-Boot prompt should appear via UART. - -UART ----- - -UART is available through the micro USB port, similar to the Carkit standard. -With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-. - -Make sure to connect the UART cable *before* turning on the phone. diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig index 4503b65419a692161c4bd5afbd2217dfe68bc593..d8f24695d0d23756b119a63dd665f22707b61a0f 100644 --- a/board/storopack/smegw01/Kconfig +++ b/board/storopack/smegw01/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "smegw01" +config IMX_CONFIG + default "board/storopack/smegw01/imximage.cfg" + endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1a46100e408d4f3a959a0ce175976781dec9a6eb..2b7d655678d0a37f3c647e802414521cba6d7a61 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -47,7 +47,7 @@ #include #include -#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +#if defined(CONFIG_VIDEO_LCD_PANEL_I2C) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ int soft_i2c_gpio_sda; int soft_i2c_gpio_scl; diff --git a/board/synopsys/axs10x/axs10x.h b/board/synopsys/axs10x/axs10x.h index 69541cc578642fcc91485ec075cdb2c2bdb55bda..db5f0628747bde1396f19c3963e77035d6219890 100644 --- a/board/synopsys/axs10x/axs10x.h +++ b/board/synopsys/axs10x/axs10x.h @@ -12,4 +12,3 @@ enum { }; #endif /* _BOARD_SYNOPSYS_AXS10X_H */ - diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S index 984b31b9d02683a5b0434847d0da84122cc1fa8f..b6f38731f11e857fb837e26916022aa9657a5632 100644 --- a/board/sysam/stmark2/sbf_dram_init.S +++ b/board/sysam/stmark2/sbf_dram_init.S @@ -5,7 +5,7 @@ * (C) Copyright 2017 Angelo Dureghello */ -.equ PPMCR0, 0xfc04002d +.equ PPMCR0, 0xfc04002d .equ MSCR_SDRAMC, 0xec094060 .equ MISCCR2, 0xec09001a .equ DDR_RCR, 0xfc0b8180 diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig deleted file mode 100644 index 59a415d65fa91aded8f06dadf58b2d94e4641a00..0000000000000000000000000000000000000000 --- a/board/syteco/zmx25/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ZMX25 - -config SYS_BOARD - default "zmx25" - -config SYS_VENDOR - default "syteco" - -config SYS_SOC - default "mx25" - -config SYS_CONFIG_NAME - default "zmx25" - -endif diff --git a/board/syteco/zmx25/MAINTAINERS b/board/syteco/zmx25/MAINTAINERS deleted file mode 100644 index 90f9fab7b84a1971ae238fb2d46e3d989206d74b..0000000000000000000000000000000000000000 --- a/board/syteco/zmx25/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZMX25 BOARD -M: Matthias Weisser -S: Maintained -F: board/syteco/zmx25/ -F: include/configs/zmx25.h -F: configs/zmx25_defconfig diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile deleted file mode 100644 index 49b3a8f18904ee1a6426f2bd5eb136153d4e05ae..0000000000000000000000000000000000000000 --- a/board/syteco/zmx25/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (c) 2010 Graf-Syteco, Matthias Weisser -# - -obj-y += zmx25.o -obj-y += lowlevel_init.o diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S deleted file mode 100644 index 7df93988412ca480f011ef1c6a2310fdaa6b42c8..0000000000000000000000000000000000000000 --- a/board/syteco/zmx25/lowlevel_init.S +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Matthias Weisser - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * Based on U-Boot and RedBoot sources for several different i.mx - * platforms. - */ - -#include -#include -#include -#include - -/* - * clocks - */ -.macro init_clocks - - /* disable clock output */ - write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 - write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 - - /* - * enable all implemented clocks in all three - * clock control registers - */ - write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff - write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff - write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff - - /* Devide NAND clock by 32 */ - write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F -.endm - -/* - * sdram controller init - */ -.macro init_lpddr - ldr r0, =IMX_ESDRAMC_BASE - ldr r2, =IMX_SDRAM_BANK0_BASE - - /* - * reset SDRAM controller - * then wait for initialization to complete - */ - ldr r1, =(1 << 1) | (1 << 2) - str r1, [r0, #ESDRAMC_ESDMISC] -1: ldr r3, [r0, #ESDRAMC_ESDMISC] - tst r3, #(1 << 31) - beq 1b - ldr r1, =(1 << 2) - str r1, [r0, #ESDRAMC_ESDMISC] - - ldr r1, =0x002a7420 - str r1, [r0, #ESDRAMC_ESDCFG0] - - /* control | precharge */ - ldr r1, =0x92216008 - str r1, [r0, #ESDRAMC_ESDCTL0] - /* dram command encoded in address */ - str r1, [r2, #0x400] - - /* auto refresh */ - ldr r1, =0xa2216008 - str r1, [r0, #ESDRAMC_ESDCTL0] - /* read dram twice to auto refresh */ - ldr r3, [r2] - ldr r3, [r2] - - /* control | load mode */ - ldr r1, =0xb2216008 - str r1, [r0, #ESDRAMC_ESDCTL0] - - /* mode register of lpddram */ - strb r1, [r2, #0x33] - - /* extended mode register of lpddrram */ - ldr r2, =0x81000000 - strb r1, [r2] - - /* control | normal */ - ldr r1, =0x82216008 - str r1, [r0, #ESDRAMC_ESDCTL0] -.endm - -.globl lowlevel_init -lowlevel_init: - init_aips - init_max - init_clocks - init_lpddr - mov pc, lr diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c deleted file mode 100644 index 2d4c5cce89203fa364a82c351e28f131ed5e7fa6..0000000000000000000000000000000000000000 --- a/board/syteco/zmx25/zmx25.c +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (c) 2011 Graf-Syteco, Matthias Weisser - * - * - * Based on tx25.c: - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby - * - * Based on imx27lite.c: - * Copyright (C) 2008,2009 Eric Jarrige - * Copyright (C) 2009 Ilya Yanok - * And: - * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init() -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), - }; - - static const iomux_v3_cfg_t dig_out_pads[] = { - MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */ - MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */ - NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */ - NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */ - }; - - static const iomux_v3_cfg_t led_pads[] = { - MX25_PAD_CSI_D9__GPIO_4_21, - MX25_PAD_CSI_D4__GPIO_1_29, - }; - - static const iomux_v3_cfg_t can_pads[] = { - NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL), - }; - - static const iomux_v3_cfg_t i2c3_pads[] = { - MX25_PAD_CSPI1_SS1__I2C3_DAT, - MX25_PAD_GPIO_E__I2C3_CLK, - }; - - icache_enable(); - - /* Setup of core voltage selection pin to run at 1.4V */ - imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */ - gpio_direction_output(IMX_GPIO_NR(3, 15), 1); - - /* Setup of SD card pins*/ - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - /* Setup of digital output for USB power and OC */ - imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */ - gpio_direction_output(IMX_GPIO_NR(1, 28), 1); - - imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */ - gpio_direction_input(IMX_GPIO_NR(1, 18)); - - /* Setup of digital output control pins */ - imx_iomux_v3_setup_multiple_pads(dig_out_pads, - ARRAY_SIZE(dig_out_pads)); - - /* Switch both output drivers off */ - gpio_direction_output(IMX_GPIO_NR(1, 7), 0); - gpio_direction_output(IMX_GPIO_NR(1, 6), 0); - - /* Setup of key input pin */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0)); - gpio_direction_input(IMX_GPIO_NR(2, 29)); - - /* Setup of status LED outputs */ - imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads)); - - /* Switch both LEDs off */ - gpio_direction_output(IMX_GPIO_NR(4, 21), 0); - gpio_direction_output(IMX_GPIO_NR(1, 29), 0); - - /* Setup of CAN1 and CAN2 signals */ - imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads)); - - /* Setup of I2C3 signals */ - imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); - - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int board_late_init(void) -{ - const char *e; - -#ifdef CONFIG_FEC_MXC -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define FEC_OUT_PAD_CTRL 0 - - static const iomux_v3_cfg_t fec_pads[] = { - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), - - MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */ - MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */ - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* assert PHY reset (low) */ - gpio_direction_output(IMX_GPIO_NR(3, 16), 0); - - udelay(5000); - - /* deassert PHY reset */ - gpio_set_value(IMX_GPIO_NR(3, 16), 1); - - udelay(5000); -#endif - - e = env_get("gs_base_board"); - if (e != NULL) { - if (strcmp(e, "G283") == 0) { - int key = gpio_get_value(IMX_GPIO_NR(2, 29)); - - if (key) { - /* Switch on both LEDs to inidcate boot mode */ - gpio_set_value(IMX_GPIO_NR(1, 29), 0); - gpio_set_value(IMX_GPIO_NR(4, 21), 0); - - env_set("preboot", "run gs_slow_boot"); - } else - env_set("preboot", "run gs_fast_boot"); - } - } - - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, - PHYS_SDRAM_SIZE); - return 0; -} diff --git a/board/tcl/sl50/Makefile b/board/tcl/sl50/Makefile index c2977d777879cffb5bc576ea7b6fc845dee98a9c..0ac0ba36cdb2f1a4e149e1a0a17730d62fc47b3f 100644 --- a/board/tcl/sl50/Makefile +++ b/board/tcl/sl50/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index d2136084991ddf51f945f85e1c87dad0c3d0ffe3..b7ddc3ba78f4d66e626a47420847a6a609a4451b 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static const struct ddr_data ddr3_sl50_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, @@ -161,7 +161,7 @@ void am33xx_spl_board_init(void) const struct dpll_params *get_dpll_ddr_params(void) { enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return &dpll_ddr_sl50; } diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 2d749dac19a460f28c8b01fef42e9baf4aef0fdc..1c0cc238df003340198e46db9b6d3fd371c02ace 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -60,7 +60,7 @@ int dram_init(void) return 0; } -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) #define I2C_PMIC 3 int power_init_board(void) { @@ -244,4 +244,3 @@ int board_ehci_hcd_init(int port) } return 0; } - diff --git a/board/technexion/pico-imx8mq/Kconfig b/board/technexion/pico-imx8mq/Kconfig index 031fc1d56364aa3514dbaef51525e5bd785415d1..628b0511490a5f7c6ae4130c9bc07959628a10fb 100644 --- a/board/technexion/pico-imx8mq/Kconfig +++ b/board/technexion/pico-imx8mq/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "pico-imx8mq" +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage.cfg" + endif diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c index bcb852668ca09f21b9fedada4ab5b48a6886e190..97b9ee27527a5e7fa0a99f094b44340aefdd38ee 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c @@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_1gb = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 667, }, }; - diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c index 9a8a323d63e8e7ca14a0c1f81817c1b3c5256c57..1572a50a05f8281ee9003948781f291f63d3d6e8 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c @@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_2gb = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 667, }, }; - diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c index 0f74ce581c3402bc2b01a4bb0f9a18e608eb6f2e..3fc60a3eeb9809e93b91ba70c4b5ba356b46102b 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c @@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_3gb = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 667, }, }; - diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c index b1d1c5223eca9ee996559aa13692c2584462f33d..93b342351628c86a5cc5481e4ae6a5d04ede5d9b 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c @@ -1731,4 +1731,3 @@ struct dram_timing_info dram_timing_4gb = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 667, }, }; - diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h index 68dc3bc279848c404b92095a7086b0d7e732e8ea..e439336d45ab6f5fef73d0561dcb07a1f26af670 100644 --- a/board/terasic/de0-nano-soc/qts/pll_config.h +++ b/board/terasic/de0-nano-soc/qts/pll_config.h @@ -81,4 +81,3 @@ #define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 #endif /* _PRELOADER_PLL_CONFIG_H_ */ - diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index c34b9b1dd8a7248c6c47cb3e340b917ae789b91c..3ccf66be5bb3459b92c9b720d6fdef7df9ff83c8 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 2e4f3d102b7d91a1ef158c7961d5a7b70ce9127c..e8555de9c937d7eb7cef6f7b4e073c518f411dee 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -79,10 +79,6 @@ void do_board_detect(void) { enable_i2c0_pin_mux(); enable_i2c2_pin_mux(); -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2); -#endif if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS)) printf("ti_i2c_eeprom_init failed\n"); @@ -99,7 +95,7 @@ struct serial_device *default_serial_console(void) } #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, @@ -253,7 +249,7 @@ static struct emif_regs ddr3_icev2_emif_reg_data = { #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL /* break into full u-boot on 'c' */ if (serial_tstc() && serial_getc() == 'c') return 1; @@ -339,13 +335,8 @@ static void scale_vcores_bone(int freq) if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) return; -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_probe(TPS65217_CHIP_PM)) - return; -#else if (power_tps65217_init(0)) return; -#endif /* @@ -438,13 +429,8 @@ void scale_vcores_generic(int freq) * 1.10V. For MPU voltage we need to switch based on * the frequency we are running at. */ -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) - return; -#else if (power_tps65910_init(0)) return; -#endif /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. @@ -472,10 +458,6 @@ void gpi2c_init(void) if (first_time) { enable_i2c0_pin_mux(); -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif first_time = false; } } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index e450ff64d87b568ef94eea584b9cccf8270d3e5c..fed737fa099acd79a0d37e6b32fb2f421d2a83af 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -345,14 +345,6 @@ void enable_i2c2_pin_mux(void) static unsigned short detect_daughter_board_profile(void) { unsigned short val; - -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_probe(I2C_CPLD_ADDR)) - return PROFILE_NONE; - - if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) - return PROFILE_NONE; -#else struct udevice *dev = NULL; int rc; @@ -362,7 +354,6 @@ static unsigned short detect_daughter_board_profile(void) rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2); if (rc) return PROFILE_NONE; -#endif return (1 << (val & PROFILE_MASK)); } diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile index 60a11d8c04d2550eec3b8573bd5cea257b35500a..8dc1d89e3ac8aa32543c6552f9896726a0dcf7bc 100644 --- a/board/ti/am43xx/Makefile +++ b/board/ti/am43xx/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index a71b588efcb0addeee7fefb91737d26cd8986cf3..529129ecc76e9939fa6989239f4677402ce55081 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -56,7 +56,7 @@ void do_board_detect(void) } #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { { /* 19.2 MHz */ @@ -393,13 +393,8 @@ void scale_vcores_generic(u32 m) { int mpu_vdd, ddr_volt; -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_probe(TPS65218_CHIP_PM)) - return; -#else if (power_tps65218_init(0)) return; -#endif switch (m) { case 1000: @@ -451,13 +446,8 @@ void scale_vcores_idk(u32 m) { int mpu_vdd; -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_probe(TPS62362_I2C_ADDR)) - return; -#else if (power_tps62362_init(0)) return; -#endif switch (m) { case 1000: @@ -492,10 +482,6 @@ void gpi2c_init(void) if (first_time) { enable_i2c0_pin_mux(); -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif first_time = false; } } @@ -632,28 +618,15 @@ void sdram_init(void) int power_init_board(void) { int rc; -#if !CONFIG_IS_ENABLED(DM_I2C) - struct pmic *p = NULL; -#endif if (board_is_idk()) { rc = power_tps62362_init(0); if (rc) goto done; -#if !CONFIG_IS_ENABLED(DM_I2C) - p = pmic_get("TPS62362"); - if (!p || pmic_probe(p)) - goto done; -#endif puts("PMIC: TPS62362\n"); } else { rc = power_tps65218_init(0); if (rc) goto done; -#if !CONFIG_IS_ENABLED(DM_I2C) - p = pmic_get("TPS65218_PMIC"); - if (!p || pmic_probe(p)) - goto done; -#endif puts("PMIC: TPS65218\n"); } done: diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 399a2e5d9130ccc13c3467506e12eb420c096bfa..cfc825e52a36868b3282d35dc7ce4376ea0624e6 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -144,13 +144,13 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, - .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -208,13 +208,13 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, - .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 212799c93ded03c03b9022c88e111b59340ab3ba..54b7050a4599cc47be2a20c6b589beb83fa5b636 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -539,7 +539,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = { {0x0884, 0, 0}, /* CFG_UART2_RTSN_OUT */ {0x0888, 683, 0}, /* CFG_UART2_RXD_IN */ {0x088C, 0, 0}, /* CFG_UART2_RXD_OEN */ - {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */ + {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */ {0x0894, 835, 0}, /* CFG_UART2_TXD_IN */ {0x0898, 0, 0}, /* CFG_UART2_TXD_OEN */ {0x089C, 0, 0}, /* CFG_UART2_TXD_OUT */ @@ -553,7 +553,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = { {0x0C48, 0, 404}, /* CFG_VOUT1_D22_IN */ {0x0C78, 0, 0}, /* CFG_VOUT1_D4_IN */ {0x0C84, 0, 365}, /* CFG_VOUT1_D5_IN */ - {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */ + {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */ {0x0C9C, 0, 218}, /* CFG_VOUT1_D7_IN */ }; diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index fda8d5f3c8386c133f5d1c3cfd41206bda01e485..d8062997e5c1c8e56a256b4abf72c6dbb0a1b4fa 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -312,6 +312,7 @@ void board_mmc_power_init(void) #endif #endif +#ifdef CONFIG_REVISION_TAG /* * get_board_rev() - get board revision */ @@ -319,3 +320,4 @@ u32 get_board_rev(void) { return 0x20; } +#endif diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 4895bfafd80adf6d851dd1efdbdb2ab23c50cf31..69726eb9ce0f3002c777352d6a68cfafd06b3c40 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -104,6 +104,7 @@ int spl_start_uboot(void) } #endif /* CONFIG_SPL_OS_BOOT */ +#ifdef CONFIG_REVISION_TAG /* * get_board_rev() - get board revision */ @@ -111,3 +112,4 @@ u32 get_board_rev(void) { return 0x20; } +#endif diff --git a/board/toradex/apalis-imx8/Kconfig b/board/toradex/apalis-imx8/Kconfig index c680d63fa1a2947330258352ad9920ae08c578d3..b43d6281b68135fc9a333a167f7d013b9efb00c4 100644 --- a/board/toradex/apalis-imx8/Kconfig +++ b/board/toradex/apalis-imx8/Kconfig @@ -25,6 +25,9 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512" +config IMX_CONFIG + default "board/toradex/apalis-imx8/apalis-imx8-imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig index ee61e09736f1488588df7d91f03d69f876d73da2..d6cda7e3ff065c8ae3164106416777b8e0961ee8 100644 --- a/board/toradex/apalis-imx8x/Kconfig +++ b/board/toradex/apalis-imx8x/Kconfig @@ -25,6 +25,9 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512" +config IMX_CONFIG + default "board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig index 14f8c10c64cf932ffab05da47ddf55314e664f97..c6ff387351c4b9f03edf909cbeb6b8b614661db3 100644 --- a/board/toradex/apalis_imx6/Kconfig +++ b/board/toradex/apalis_imx6/Kconfig @@ -48,7 +48,6 @@ config TDX_APALIS_IMX6_V1_0 This option configures DCE mode unconditionally. Whithout this option the config block stating V1.0 HW selects DCE mode, otherwise the UARTs are configuered in DTE mode. - default n source "board/toradex/common/Kconfig" diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 74060daaddd7546b96456e8e982fcb96d41c095a..f4cd28d49f91890bfe3e70763866b74f81496ff7 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -707,12 +707,11 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#if defined(CONFIG_REVISION_TAG) && \ - defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) char env_str[256]; u32 rev; - rev = get_board_rev(); + rev = get_board_revision(); snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); env_set("board_rev", env_str); diff --git a/board/toradex/colibri-imx6ull/Kconfig b/board/toradex/colibri-imx6ull/Kconfig index 3ce9885c122b1b0eccde5326a3b4061dcabc2afa..e5e4af336480f7e33d2fb320ed1ba3eb1cad19b8 100644 --- a/board/toradex/colibri-imx6ull/Kconfig +++ b/board/toradex/colibri-imx6ull/Kconfig @@ -24,6 +24,9 @@ config TDX_CFG_BLOCK_OFFSET2 config TDX_CFG_BLOCK_2ND_ETHADDR default y +config IMX_CONFIG + default "board/toradex/colibri-imx6ull/imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/colibri-imx8x/Kconfig b/board/toradex/colibri-imx8x/Kconfig index d97fed020e718ac3400ed6d9f733ad093cf12751..b89840a379c4197798cdc0d70ed99e42039b39a0 100644 --- a/board/toradex/colibri-imx8x/Kconfig +++ b/board/toradex/colibri-imx8x/Kconfig @@ -25,6 +25,9 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512" +config IMX_CONFIG + default "board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 587d92a8e997fce87918c74e1988610f71f72940..3b55f6c938ed78de60c41debb71f245a50150b66 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -611,12 +611,11 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#if defined(CONFIG_REVISION_TAG) && \ - defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) char env_str[256]; u32 rev; - rev = get_board_rev(); + rev = get_board_revision(); snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); env_set("board_rev", env_str); #endif diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig index d33ec635238e6465c7715f539d24be54771758c5..87c416ac2facf3bad19b4d97e5b632f3ccd4e9b0 100644 --- a/board/toradex/colibri_imx7/Kconfig +++ b/board/toradex/colibri_imx7/Kconfig @@ -71,6 +71,9 @@ config TDX_CFG_BLOCK_OFFSET endif +config IMX_CONFIG + default "board/toradex/colibri_imx7/imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig index 5f7129dd359bfb6d392f77cd5a58994e6ea2929d..83315d87577d7c534079e8cce0d04c5829ad08f6 100644 --- a/board/toradex/colibri_vf/Kconfig +++ b/board/toradex/colibri_vf/Kconfig @@ -21,6 +21,9 @@ config TDX_CFG_BLOCK_OFFSET config TDX_CFG_BLOCK_2ND_ETHADDR default y +config IMX_CONFIG + default "board/toradex/colibri_vf/imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index e4f9a0db9141f5528ba0a2de228ee0113f294b30..fe47cddad8034f0470789aada3d0fc873d19d3df 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -493,24 +493,24 @@ static int get_cfgblock_interactive(void) else tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ; } -#ifdef CONFIG_MACH_TYPE +#if defined(CONFIG_TARGET_APALIS_T30) || defined(CONFIG_TARGET_COLIBRI_T30) else if (!strcmp("tegra30", soc)) { - if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = APALIS_T30_IT; - else - if (gd->ram_size == 0x40000000) - tdx_hw_tag.prodid = APALIS_T30_1GB; - else - tdx_hw_tag.prodid = APALIS_T30_2GB; - } else { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = COLIBRI_T30_IT; +#ifdef CONFIG_TARGET_APALIS_T30 + if (it == 'y' || it == 'Y') + tdx_hw_tag.prodid = APALIS_T30_IT; + else + if (gd->ram_size == 0x40000000) + tdx_hw_tag.prodid = APALIS_T30_1GB; else - tdx_hw_tag.prodid = COLIBRI_T30; - } + tdx_hw_tag.prodid = APALIS_T30_2GB; +#else + if (it == 'y' || it == 'Y') + tdx_hw_tag.prodid = COLIBRI_T30_IT; + else + tdx_hw_tag.prodid = COLIBRI_T30; +#endif } -#endif /* CONFIG_MACH_TYPE */ +#endif /* CONFIG_TARGET_APALIS_T30 || CONFIG_TARGET_COLIBRI_T30 */ else if (!strcmp("tegra124", soc)) { tdx_hw_tag.prodid = APALIS_TK1_2GB; } else if (!strcmp("vf500", soc)) { diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 061abf7537bb276c9c6373776adccf75906aca90..9db4553e0f7bbffa1411d7a75e46b761aad7f26c 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -32,8 +32,8 @@ static char tdx_car_rev_str[6]; static char *tdx_carrier_board_name; #endif -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) +#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +u32 get_board_revision(void) { /* Check validity */ if (!tdx_hw_tag.ver_major) @@ -183,8 +183,8 @@ int ft_common_board_setup(void *blob, struct bd_info *bd) #else /* CONFIG_TDX_CFG_BLOCK */ -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) +#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +u32 get_board_revision(void) { return 0; } diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index 8020df5b44367e23213aa6dea6ed5774b0549491..c96e8754e9e2561312e26e70052746b089c5968b 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -10,6 +10,7 @@ #define TDX_USB_VID 0x1B67 int ft_common_board_setup(void *blob, struct bd_info *bd); +u32 get_board_revision(void); #if defined(CONFIG_DM_VIDEO) int show_boot_logo(void); diff --git a/board/toradex/verdin-imx8mm/Kconfig b/board/toradex/verdin-imx8mm/Kconfig index 149aed6da74395d36fc908fa4131b6723f8d9b19..51e8ba618b98334bbff65489bb54c726416bc5df 100644 --- a/board/toradex/verdin-imx8mm/Kconfig +++ b/board/toradex/verdin-imx8mm/Kconfig @@ -31,6 +31,9 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512" +config IMX_CONFIG + default "board/toradex/verdin-imx8mm/imximage.cfg" + source "board/toradex/common/Kconfig" endif diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c index f2b92109b6ac08e6fbceac4605242533efa97769..f2de039b6b4752266b8af89f392ac35d14137b64 100644 --- a/board/tplink/wdr4300/wdr4300.c +++ b/board/tplink/wdr4300/wdr4300.c @@ -71,7 +71,7 @@ int board_early_init_f(void) wdr4300_pinmux_config(); #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) ar934x_pll_init(560, 480, 240); ar934x_ddr_init(560, 480, 240); #endif diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 4f86a9290167dffd5bb9751a883fb289c0c26aad..de9c00174aef61e9630865ece191f30686ae5284 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -171,7 +171,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) #endif #endif -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) static struct i2c_pads_info tqma6_i2c3_pads = { /* I2C3: on board LM75, M24C64, */ .scl = { @@ -216,7 +216,7 @@ int board_init(void) #ifndef CONFIG_DM_SPI tqma6_iomuxc_spi(); #endif -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) tqma6_setup_i2c(); #endif @@ -247,7 +247,7 @@ static const char *tqma6_get_boardname(void) }; } -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) /* setup board specific PMIC */ int power_init_board(void) { diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 92a1e084b5242f81caf088a0863ec763bedb9f57..ce005d31cc66d4a88ff1e55553473f9a1648f1dd 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -96,7 +96,7 @@ static struct i2c_pads_info i2c_pad_info1 = { }; #endif -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) int power_init_board(void) { struct pmic *p; diff --git a/board/varisys/common/Makefile b/board/varisys/common/Makefile deleted file mode 100644 index b7358c7c647ed2e4009626686bc328fc5edbf638..0000000000000000000000000000000000000000 --- a/board/varisys/common/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -# necessary to create built-in.o -obj- := __dummy__.o -else -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o -endif -endif diff --git a/board/varisys/common/eeprom.h b/board/varisys/common/eeprom.h deleted file mode 100644 index 004816a0fd465a692f6416e63f4c211863c80c00..0000000000000000000000000000000000000000 --- a/board/varisys/common/eeprom.h +++ /dev/null @@ -1,6 +0,0 @@ -/* EEPROM init functions for Cyrus */ - - -void init_eeprom(int bus_num, int addr, int addr_len); -void mac_read_from_fixed_id(void); -int mac_read_from_eeprom_common(void); diff --git a/board/varisys/common/sys_eeprom.c b/board/varisys/common/sys_eeprom.c deleted file mode 100644 index 8f624e5e368d882b7c66229ee1b0bd585fd7ec9b..0000000000000000000000000000000000000000 --- a/board/varisys/common/sys_eeprom.c +++ /dev/null @@ -1,500 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Based on board/freescale/common/sys_eeprom.c - * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor - * - * This defines the API for storing board information in the - * eeprom. It has been adapted from an earlier version of the - * Freescale API, but has a number of key differences. Because - * the two APIs are independent and may diverge further, the - * Varisys version of the API is implemented separately here. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "eeprom.h" - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC -#define MAX_NUM_PORTS CONFIG_SYS_I2C_EEPROM_NXID_MAC -#else -#define MAX_NUM_PORTS 8 -#endif -#define NXID_VERSION 0 - -/** - * static eeprom: EEPROM layout for NXID formats - * - * See Freescale application note AN3638 for details. - */ -static struct __attribute__ ((__packed__)) eeprom { - u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ - u8 sn[12]; /* 0x04 - 0x0F Serial Number */ - u8 errata[5]; /* 0x10 - 0x14 Errata Level */ - u8 date[6]; /* 0x15 - 0x1a Build Date */ - u8 res_0; /* 0x1b Reserved */ - u32 version; /* 0x1c - 0x1f NXID Version */ - u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */ - u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */ - u8 tempcalflags; /* 0x2a Temperature Calibration Flags */ - u8 res_1[21]; /* 0x2b - 0x3f Reserved */ - u8 mac_count; /* 0x40 Number of MAC addresses */ - u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ - u32 crc; /* x+1 CRC32 checksum */ -} e; - -/* Set to 1 if we've read EEPROM into memory */ -static int has_been_read; - -/* Is this a valid NXID EEPROM? */ -#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ - (e.id[2] == 'I') || (e.id[3] == 'D')) - -/** Fixed ID field in EEPROM */ -static unsigned char uid[16]; - -static int eeprom_bus_num = -1; -static int eeprom_addr; -static int eeprom_addr_len; - -/** - * This must be called before any eeprom access. - */ -void init_eeprom(int bus_num, int addr, int addr_len) -{ - eeprom_bus_num = bus_num; - eeprom_addr = addr; - eeprom_addr_len = addr_len; -} - -/** - * show_eeprom - display the contents of the EEPROM - */ -void show_eeprom(void) -{ - int i; - unsigned int crc; - - /* EEPROM tag ID, either CCID or NXID */ - printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); - - /* Serial number */ - printf("SN: %s\n", e.sn); - - printf("UID: "); - for (i = 0; i < 16; i++) - printf("%02x", uid[i]); - printf("\n"); - - /* Errata level. */ - printf("Errata: %s\n", e.errata); - - /* Build date, BCD date values, as YYMMDDhhmmss */ - printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", - e.date[0], e.date[1], e.date[2], - e.date[3] & 0x7F, e.date[4], e.date[5], - e.date[3] & 0x80 ? "PM" : ""); - - /* Show MAC addresses */ - for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { - u8 *p = e.mac[i]; - - printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i, - p[0], p[1], p[2], p[3], p[4], p[5]); - } - - crc = crc32(0, (void *)&e, sizeof(e) - 4); - - if (crc == be32_to_cpu(e.crc)) - printf("CRC: %08x\n", be32_to_cpu(e.crc)); - else - printf("CRC: %08x (should be %08x)\n", - be32_to_cpu(e.crc), crc); - -#ifdef DEBUG - printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); - for (i = 0; i < sizeof(e); i++) { - if ((i % 16) == 0) - printf("%02X: ", i); - printf("%02X ", ((u8 *)&e)[i]); - if (((i % 16) == 15) || (i == sizeof(e) - 1)) - printf("\n"); - } -#endif -} - -/** - * read_eeprom - read the EEPROM into memory - */ -int read_eeprom(void) -{ - int ret; - unsigned int bus; - - if (eeprom_bus_num < 0) { - printf("EEPROM not configured\n"); - return -1; - } - - if (has_been_read) - return 0; - - bus = i2c_get_bus_num(); - i2c_set_bus_num(eeprom_bus_num); - - ret = i2c_read(eeprom_addr, 0, eeprom_addr_len, - (void *)&e, sizeof(e)); - - - /* Fixed address of ID field */ - i2c_read(0x5f, 0x80, 1, uid, 16); - - i2c_set_bus_num(bus); - -#ifdef DEBUG - show_eeprom(); -#endif - - has_been_read = (ret == 0) ? 1 : 0; - - return ret; -} - -/** - * update_crc - update the CRC - * - * This function should be called after each update to the EEPROM structure, - * to make sure the CRC is always correct. - */ -static void update_crc(void) -{ - u32 crc, crc_offset = offsetof(struct eeprom, crc); - - crc = crc32(0, (void *)&e, crc_offset); - e.crc = cpu_to_be32(crc); -} - -/** - * prog_eeprom - write the EEPROM from memory - */ -static int prog_eeprom(void) -{ - int ret = 0; - int i; - void *p; - unsigned int bus; - - if (eeprom_bus_num < 0) { - printf("EEPROM not configured\n"); - return -1; - } - - /* Set the reserved values to 0xFF */ - e.res_0 = 0xFF; - memset(e.res_1, 0xFF, sizeof(e.res_1)); - update_crc(); - - bus = i2c_get_bus_num(); - i2c_set_bus_num(eeprom_bus_num); - - /* - * The AT24C02 datasheet says that data can only be written in page - * mode, which means 8 bytes at a time, and it takes up to 5ms to - * complete a given write. - */ - for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { - ret = i2c_write(eeprom_addr, i, eeprom_addr_len, - p, min((int)(sizeof(e) - i), 8)); - if (ret) - break; - udelay(5000); /* 5ms write cycle timing */ - } - - if (!ret) { - /* Verify the write by reading back the EEPROM and comparing */ - struct eeprom e2; - - ret = i2c_read(eeprom_addr, 0, - eeprom_addr_len, (void *)&e2, sizeof(e2)); - if (!ret && memcmp(&e, &e2, sizeof(e))) - ret = -1; - } - - i2c_set_bus_num(bus); - - if (ret) { - printf("Programming failed.\n"); - has_been_read = 0; - return -1; - } - - printf("Programming passed.\n"); - return 0; -} - -/** - * h2i - converts hex character into a number - * - * This function takes a hexadecimal character (e.g. '7' or 'C') and returns - * the integer equivalent. - */ -static inline u8 h2i(char p) -{ - if ((p >= '0') && (p <= '9')) - return p - '0'; - - if ((p >= 'A') && (p <= 'F')) - return (p - 'A') + 10; - - if ((p >= 'a') && (p <= 'f')) - return (p - 'a') + 10; - - return 0; -} - -/** - * set_date - stores the build date into the EEPROM - * - * This function takes a pointer to a string in the format "YYMMDDhhmmss" - * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, - * and stores it in the build date field of the EEPROM local copy. - */ -static void set_date(const char *string) -{ - unsigned int i; - - if (strlen(string) != 12) { - printf("Usage: mac date YYMMDDhhmmss\n"); - return; - } - - for (i = 0; i < 6; i++) - e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); - - update_crc(); -} - -/** - * set_mac_address - stores a MAC address into the EEPROM - * - * This function takes a pointer to MAC address string - * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and - * stores it in one of the MAC address fields of the EEPROM local copy. - */ -static void set_mac_address(unsigned int index, const char *string) -{ - char *p = (char *)string; - unsigned int i; - - if ((index >= MAX_NUM_PORTS) || !string) { - printf("Usage: mac XX:XX:XX:XX:XX:XX\n"); - return; - } - - for (i = 0; *p && (i < 6); i++) { - e.mac[index][i] = hextoul(p, &p); - if (*p == ':') - p++; - } - - update_crc(); -} - -int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - char cmd; - - if (argc == 1) { - show_eeprom(); - return 0; - } - - cmd = argv[1][0]; - - if (cmd == 'r') { - read_eeprom(); - return 0; - } - - if (cmd == 'i') { - memcpy(e.id, "NXID", sizeof(e.id)); - e.version = NXID_VERSION; - update_crc(); - return 0; - } - - if (!is_valid) { - printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n"); - return 0; - } - - if (argc == 2) { - switch (cmd) { - case 's': /* save */ - prog_eeprom(); - break; - default: - return cmd_usage(cmdtp); - } - - return 0; - } - - /* We know we have at least one parameter */ - - switch (cmd) { - case 'n': /* serial number */ - memset(e.sn, 0, sizeof(e.sn)); - strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); - update_crc(); - break; - case 'e': /* errata */ - memset(e.errata, 0, 5); - strncpy((char *)e.errata, argv[2], 4); - update_crc(); - break; - case 'd': /* date BCD format YYMMDDhhmmss */ - set_date(argv[2]); - break; - case 'p': /* MAC table size */ - e.mac_count = hextoul(argv[2], NULL); - update_crc(); - break; - case '0' ... '9': /* "mac 0" through "mac 22" */ - set_mac_address(dectoul(argv[1], NULL), argv[2]); - break; - case 'h': /* help */ - default: - return cmd_usage(cmdtp); - } - - return 0; -} - -int mac_read_from_generic_eeprom(const char *envvar, int chip, - int address, int mac_bus) -{ - int ret; - unsigned int bus; - unsigned char mac[6]; - char ethaddr[18]; - - bus = i2c_get_bus_num(); - i2c_set_bus_num(mac_bus); - - ret = i2c_read(chip, address, 1, mac, 6); - - i2c_set_bus_num(bus); - - if (!ret) { - sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], - mac[1], - mac[2], - mac[3], - mac[4], - mac[5]); - - printf("MAC: %s\n", ethaddr); - env_set(envvar, ethaddr); - } - - return ret; -} - -void mac_read_from_fixed_id(void) -{ -#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR - mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR, - CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS); -#endif -#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR - mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR, - CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS); -#endif -} - -/** - * mac_read_from_eeprom - read the MAC addresses from EEPROM - * - * This function reads the MAC addresses from EEPROM and sets the - * appropriate environment variables for each one read. - * - * The environment variables are only set if they haven't been set already. - * This ensures that any user-saved variables are never overwritten. - * - * This function must be called after relocation. - * - * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 - * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is - * located at a different offset. - */ -int mac_read_from_eeprom_common(void) -{ - unsigned int i; - u32 crc, crc_offset = offsetof(struct eeprom, crc); - u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ - - puts("EEPROM: "); - - if (read_eeprom()) { - printf("Read failed.\n"); - return 0; - } - - if (!is_valid) { - printf("Invalid ID (%02x %02x %02x %02x)\n", - e.id[0], e.id[1], e.id[2], e.id[3]); - return 0; - } - - crc = crc32(0, (void *)&e, crc_offset); - crcp = (void *)&e + crc_offset; - if (crc != be32_to_cpu(*crcp)) { - printf("CRC mismatch (%08x != %08x)\n", crc, - be32_to_cpu(e.crc)); - return 0; - } - - /* - * MAC address #9 in v1 occupies the same position as the CRC in v0. - * Erase it so that it's not mistaken for a MAC address. We'll - * update the CRC later. - */ - if (e.version == 0) - memset(e.mac[8], 0xff, 6); - - for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { - if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && - memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { - char ethaddr[18]; - char enetvar[9]; - - sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - e.mac[i][0], - e.mac[i][1], - e.mac[i][2], - e.mac[i][3], - e.mac[i][4], - e.mac[i][5]); - sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); - /* Only initialize environment variables that are blank - * (i.e. have not yet been set) - */ - if (!env_get(enetvar)) - env_set(enetvar, ethaddr); - } - } - - printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); - - return 0; -} diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile index c34b9b1dd8a7248c6c47cb3e340b917ae789b91c..3ccf66be5bb3459b92c9b720d6fdef7df9ff83c8 100644 --- a/board/vscom/baltos/Makefile +++ b/board/vscom/baltos/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 0007cac1aaa7120701f23178a73eecf100c7b9fd..07fe45447186699aed29b654c0c8fbc0735f080b 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -187,7 +187,7 @@ void am33xx_spl_board_init(void) */ i2c_set_bus_num(1); - printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED); + printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED); if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { puts("i2c: cannot access TPS65910\n"); diff --git a/board/warp/Kconfig b/board/warp/Kconfig index dc0263631906afe07f2f4f8530158d533ce0acbf..9c2fc9df67ee24ebce39c173f8c931dc8d87721f 100644 --- a/board/warp/Kconfig +++ b/board/warp/Kconfig @@ -6,4 +6,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "warp" +config IMX_CONFIG + default "board/warp/imximage.cfg" + endif diff --git a/board/warp7/Kconfig b/board/warp7/Kconfig index c089bca2bafb053d9c5c6faec0384c417ae0d7a2..e5051cdda66a49929509d1cf6a7c8623c44388ed 100644 --- a/board/warp7/Kconfig +++ b/board/warp7/Kconfig @@ -20,4 +20,7 @@ config SYS_FDT_ADDR help The address the FDT file should be loaded to. +config IMX_CONFIG + default "board/warp7/imximage.cfg" + endif diff --git a/board/warp7/README b/board/warp7/README index 579bb2de38a9d40fd5972193d4722b765b0b512c..05cdfd00275a6f26d7c36aa429ce340ed35b70d5 100644 --- a/board/warp7/README +++ b/board/warp7/README @@ -19,7 +19,7 @@ $ make This will generate the U-Boot binary called u-boot-dtb.imx. -Put warp7 board in USB download mode: +Put warp7 board in USB download mode: Remove the CPU board from the base board then put switch 2 in the upper position diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 0f202241dd78dc1e978822591a200fe37a9efcdb..c5c5433048dd708d6c9b9118dcb32465b6206df4 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -134,7 +134,7 @@ int checkboard(void) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG struct tag_serialnr serialnr; char serial_string[0x20]; #endif @@ -156,7 +156,7 @@ int board_late_init(void) env_set_ulong(HAB_ENABLED_ENVNAME, 0); #endif -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* Set serial# standard environment variable based on OTP settings */ get_board_serial(&serialnr); snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c index e8e559ce1f9cc45d40e4d529728fd12f5dac82f9..5f625e6f52ad45f4a4f8ee999c023b3c1e606502 100644 --- a/board/work-microwave/work_92105/work_92105_display.c +++ b/board/work-microwave/work_92105/work_92105_display.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 21363d878f7524d86786822ff11bb407510201c7..da0ddeefff3dab6c1dca607abe4c3097c3f1fd26 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -195,4 +195,3 @@ void board_cleanup_before_linux(void) { xen_fini(); } - diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index 04d4cdb14115f0a22ac17654c3b80b482ae04a40..797c1a5d68925357f99d712e842a8c6a99feeada 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -102,4 +102,3 @@ U_BOOT_CMD(versal, 4, 1, do_versal, "versal sub-system", versal_help_text ) - diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 61e0a90c119b65b33e417fc70ee9dc793bbfb099..1111ad6fca9c4ea5c29c0b317595c9018dd351d4 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -151,3 +152,37 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_NOWHERE; } } + +#if defined(CONFIG_SET_DFU_ALT_INFO) + +#define DFU_ALT_BUF_LEN SZ_1K + +void set_dfu_alt_info(char *interface, char *devstr) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + if (env_get("dfu_alt_info")) + return; + + memset(buf, 0, sizeof(buf)); + + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_SD: + snprintf(buf, DFU_ALT_BUF_LEN, + "mmc 0:1=boot.bin fat 0 1;" + "u-boot.img fat 0 1"); + break; + case ZYNQ_BM_QSPI: + snprintf(buf, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw 0 0x1500000;" + "u-boot.img raw 0x%x 0x500000", + CONFIG_SYS_SPI_U_BOOT_OFFS); + break; + default: + return; + } + + env_set("dfu_alt_info", buf); + puts("DFU alt info setting: done\n"); +} +#endif diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index 337af2d9649fbf2cc156624689cf9278303de187..c2a6f9199aceb2ae2098dd7636c4e112ebeaa1b8 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -12399,8 +12399,6 @@ unsigned long ps7_post_config_1_0[] = { // }; - - #include "xil_io.h" unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; @@ -12477,15 +12475,9 @@ ps7_init() ret = ps7_config (ps7_ddr_init_data); if (ret != PS7_INIT_SUCCESS) return ret; - - // Peripherals init ret = ps7_config (ps7_peripherals_init_data); if (ret != PS7_INIT_SUCCESS) return ret; //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); return PS7_INIT_SUCCESS; } - - - - diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index 248c72861c8e730fbd4f063c2aff811e9a6a65f0..fd102a3ce4af82a2eca7d9f5787f6db574d56446 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -12732,8 +12732,6 @@ unsigned long ps7_post_config_1_0[] = { // }; - - #include "xil_io.h" unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; @@ -12810,8 +12808,6 @@ ps7_init() ret = ps7_config (ps7_ddr_init_data); if (ret != PS7_INIT_SUCCESS) return ret; - - // Peripherals init ret = ps7_config (ps7_peripherals_init_data); if (ret != PS7_INIT_SUCCESS) return ret; diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index c84ee6b1f214b7d609ae38ee65439d1cb42d2752..796e5b0c5f629e0d6c337408a46140c2788f7c49 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -12639,8 +12639,6 @@ unsigned long ps7_post_config_1_0[] = { // }; - - #include "xil_io.h" unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; @@ -12717,15 +12715,9 @@ ps7_init() ret = ps7_config (ps7_ddr_init_data); if (ret != PS7_INIT_SUCCESS) return ret; - - // Peripherals init ret = ps7_config (ps7_peripherals_init_data); if (ret != PS7_INIT_SUCCESS) return ret; //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); return PS7_INIT_SUCCESS; } - - - - diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index 7a15ea572969d90d85ca1901d44e7b0e176c1f22..baf89a580001b456085ef5f487ddcb7d7a61611c 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -12297,8 +12297,6 @@ unsigned long ps7_post_config_1_0[] = { // }; - - #include "xil_io.h" unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; @@ -12375,15 +12373,9 @@ ps7_init() ret = ps7_config (ps7_ddr_init_data); if (ret != PS7_INIT_SUCCESS) return ret; - - // Peripherals init ret = ps7_config (ps7_peripherals_init_data); if (ret != PS7_INIT_SUCCESS) return ret; //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); return PS7_INIT_SUCCESS; } - - - - diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c index fda6d18dd92ce6ccf02ed3e119883e84ad5d3656..04d2e5f13755e43b2d27c78396781c082cabddb3 100644 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c @@ -12565,4 +12565,3 @@ int ps7_init(void) return ret; return PS7_INIT_SUCCESS; } - diff --git a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c new file mode 100644 index 0000000000000000000000000000000000000000..348f0e7789a71699188d9015a48998d0df6821dc --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c @@ -0,0 +1,2052 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate); + +static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res); + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); + psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0); + psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4023E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + int cur_PLLCR0; + + cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL0PLLCR0; + + cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL1PLLCR0; + + cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL2PLLCR0; + + cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL3PLLCR0; + + cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL4PLLCR0; + + cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SLBPLLCR0; + + cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; + Xil_Out32(0xFD080068, 0x02120000); + Xil_Out32(0xFD081404, 0x02120000); + Xil_Out32(0xFD081444, 0x02120000); + Xil_Out32(0xFD081484, 0x02120000); + Xil_Out32(0xFD0814C4, 0x02120000); + Xil_Out32(0xFD081504, 0x02120000); + Xil_Out32(0xFD0817C4, 0x02120000); + int cur_div2; + + cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; + int cur_fbdiv; + + cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; + dpll_prog(1, 49, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + Xil_Out32(0xFD0800C0U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000331U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000B36U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000C56U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000E19U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00001616U); + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD070010U, 0x80000010U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + + Xil_Out32(0xFD080068, cur_PLLCR0); + Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); + Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); + Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); + Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); + Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); + Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + + dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); + prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0014FE01); + + regval = Xil_In32(0xFD080030); + while (regval != 0x8000007E) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x000091C7U); + regval = Xil_In32(0xFD080030); + while (regval != 0x80008FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x800091C7U); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD070180U, 0x02160010U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + for (int tp = 0; tp < 4000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); + prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); + prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); + prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); + prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); + prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); + prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); + prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); + prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + + return 1; +} + +static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (pllsel == 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (pllsel == 1) + mask_poll(0xFD4063E4, 0x00000010U); + if (pllsel == 2) + mask_poll(0xFD40A3E4, 0x00000010U); + if (pllsel == 3) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080); + + Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); + return 1; +} + +static int serdes_bist_static_settings(u32 lane_active) +{ + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + } + + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + } + + if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } + return 1; +} + +static int serdes_bist_run(u32 lane_active) +{ + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); + } + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); + return 1; +} + +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + + if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; + return 1; +} + +static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol, + u32 lane3_rate, u32 lane2_protocol, + u32 lane2_rate, u32 lane1_protocol, + u32 lane1_rate, u32 lane0_protocol, + u32 lane0_rate, u32 gen2_calib) +{ + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; + } + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + } + + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(pllsel, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, lane1_protocol, + lane1_rate, lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2); + + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && + prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && + currbistresult[loop] == 0 && itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + itercount - 1 - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64); + + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue; + + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop]; + + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + } + } + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + } + + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + + Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); + } + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); + } + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); + } + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } + return 1; +} + +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset; + + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); + } + + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0; + + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0); + + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); + } + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0; + + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0); + + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0; + + serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); + } + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + + serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); + } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); + } + + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); + } + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + } + + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } + } + + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37); + + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37); + + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37); + + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37); + + return 1; +} + +static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res) +{ + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); + pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); + pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); + pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); + pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); + pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_status_regval = 0x00000000; + while ((pll_status_regval & 0x00000002U) != 0x00000002U) + pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xc] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ea15e62eb21eaf19c0e8effe418c46ee09f276fe..000a7cde8d8415027abcf463277a230010e1aada 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -672,6 +672,7 @@ int board_late_init(void) mode = "mmc"; bootseq = dev_seq(dev); + env_set("modeboot", "emmcboot"); break; case SD_MODE: puts("SD_MODE\n"); diff --git a/cmd/Kconfig b/cmd/Kconfig index 3a857b3f6e2ed9f8540632005f772aab9b136111..5b30b13e438f12c4341ac94e0f00b539c66fb1ab 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -471,7 +471,6 @@ config CMD_SAVEENV config CMD_ERASEENV bool "eraseenv" - default n depends on CMD_SAVEENV help Erase environment variables from the compiled-in persistent @@ -614,6 +613,37 @@ config EEPROM_LAYOUT_HELP_STRING Help printed with the LAYOUT VERSIONS part of the 'eeprom' command's help. +config SYS_I2C_EEPROM_BUS + int "I2C bus of the EEPROM device." + depends on CMD_EEPROM + default 0 + +config SYS_I2C_EEPROM_ADDR_LEN + int "Length in bytes of the EEPROM memory array address" + depends on CMD_EEPROM || ID_EEPROM + default 1 + range 1 2 + help + Note: This is NOT the chip address length! + +config SYS_EEPROM_SIZE + depends on CMD_EEPROM + int "Size in bytes of the EEPROM device" + default 256 + +config SYS_EEPROM_PAGE_WRITE_BITS + int "Number of bits used to address bytes in a single page" + depends on CMD_EEPROM + default 8 + help + The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. + A 64 byte page, for example would require six bits. + +config SYS_EEPROM_PAGE_WRITE_DELAY_MS + int "Number of milliseconds to delay between page writes" + depends on CMD_EEPROM || CMD_I2C + default 0 + config LOOPW bool "loopw" help @@ -621,14 +651,12 @@ config LOOPW config CMD_MD5SUM bool "md5sum" - default n select MD5 help Compute MD5 checksum. config MD5SUM_VERIFY bool "md5sum -v" - default n depends on CMD_MD5SUM help Add -v option to verify data against an MD5 checksum. @@ -1088,7 +1116,6 @@ if CMD_MMC config CMD_BKOPS_ENABLE bool "mmc bkops enable" depends on CMD_MMC - default n help Enable command for setting manual background operations handshake on a eMMC device. The feature is optionally available on eMMC devices @@ -1416,7 +1443,6 @@ config CMD_SETEXPR config CMD_SETEXPR_FMT bool "setexpr_fmt" - default n depends on CMD_SETEXPR help Evaluate format string expression and store result in an environment @@ -1428,7 +1454,6 @@ menu "Android support commands" config CMD_AB_SELECT bool "ab_select" - default n depends on ANDROID_AB help On Android devices with more than one boot slot (multiple copies of @@ -1733,7 +1758,6 @@ config CMD_EFIDEBUG bool "efidebug - display/configure UEFI environment" depends on EFI_LOADER select EFI_DEVICE_PATH_TO_TEXT - default n help Enable the 'efidebug' command which provides a subset of UEFI shell utility with simplified functionality. It will be useful @@ -2336,7 +2360,6 @@ config CMD_TRACE config CMD_AVB bool "avb - Android Verified Boot 2.0 operations" depends on AVB_VERIFY - default n help Enables a "avb" command to perform verification of partitions using Android Verified Boot 2.0 functionality. It includes such subcommands: @@ -2376,7 +2399,6 @@ config CMD_UBI config CMD_UBI_RENAME bool "Enable rename" depends on CMD_UBI - default n help Enable a "ubi" command to rename ubi volume: ubi rename diff --git a/cmd/bedbug.c b/cmd/bedbug.c index 549c9056ddcae2e4672466ab2ff90d0a56531cf6..0bd67fcf47c5410ffc7bcc7d790f17844b56e41a 100644 --- a/cmd/bedbug.c +++ b/cmd/bedbug.c @@ -39,7 +39,6 @@ int bedbug_puts (const char *str) } /* bedbug_puts */ - /* ====================================================================== * Initialize the bug_ctx structure used by the bedbug debugger. This is * specific to the CPU since each has different debug registers and @@ -53,7 +52,6 @@ int bedbug_init(void) } /* bedbug_init */ - /* ====================================================================== * Entry point from the interpreter to the disassembler. Repeated calls * will resume from the last disassembled address. @@ -183,7 +181,6 @@ void do_bedbug_breakpoint (struct pt_regs *regs) } /* do_bedbug_breakpoint */ - /* ====================================================================== * Called from the CPU-specific breakpoint handling routine. Enter a * mini main loop until the stopped flag is cleared from the breakpoint @@ -241,7 +238,6 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) } /* bedbug_main_loop */ - /* ====================================================================== * Interpreter command to continue from a breakpoint. Just clears the * stopped flag in the context so that the breakpoint routine will diff --git a/cmd/cramfs.c b/cmd/cramfs.c index 44c0818d5d42ed703d42f55203e7609fc7bdc51f..d79292bad55a90fe9ffc41e35ba5220d2af5d582 100644 --- a/cmd/cramfs.c +++ b/cmd/cramfs.c @@ -3,7 +3,7 @@ * * based on: cmd_jffs2.c * - * Add support for a CRAMFS located in RAM + * Add support for a CRAMFS located in RAM */ diff --git a/cmd/date.c b/cmd/date.c index 149ca426e8c4f3936685b7b22117889b51e126cd..0e2dfbc4fc28f8a62b8523f2dbb711461aafccdf 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -49,7 +49,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } } -#elif defined(CONFIG_SYS_I2C_LEGACY) +#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) old_bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); #else @@ -122,7 +122,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, } /* switch back to original I2C bus */ -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) i2c_set_bus_num(old_bus); #elif !defined(CONFIG_DM_RTC) I2C_SET_BUS(old_bus); diff --git a/cmd/eeprom.c b/cmd/eeprom.c index efd6f3ac0325888df060356d972c57553d8f2c09..cdd65af763b04f13d08386d52c9490f67f209aca 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -15,7 +15,7 @@ * degradation (typical for EEPROM) is incured for FRAM memory: * * #define CONFIG_SYS_I2C_FRAM - * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS + * Set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to 0 * */ @@ -27,18 +27,6 @@ #include #include -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif - -#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0 -#endif - -#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8 -#endif - #ifndef I2C_RXTX_LEN #define I2C_RXTX_LEN 128 #endif @@ -46,21 +34,6 @@ #define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS) #define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1)) -/* - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is - * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. - * - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is - * 0x00000nxx for EEPROM address selectors and page number at n. - */ -#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C) -#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \ - (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \ - (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2) -#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2 -#endif -#endif - #if CONFIG_IS_ENABLED(DM_I2C) static int eeprom_i2c_bus; #endif @@ -75,13 +48,20 @@ void eeprom_init(int bus) /* I2C EEPROM */ #if CONFIG_IS_ENABLED(DM_I2C) eeprom_i2c_bus = bus; -#elif defined(CONFIG_SYS_I2C_LEGACY) +#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) if (bus >= 0) i2c_set_bus_num(bus); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif } +/* + * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is + * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. + * + * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is + * 0x00000nxx for EEPROM address selectors and page number at n. + */ static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr) { unsigned blk_off; @@ -183,8 +163,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer, buffer += len; offset += len; +#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0 if (!read) udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#endif } return rcode; @@ -243,10 +225,10 @@ static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc, int argc_no_bus = argc_no_bus_addr + 1; int argc_bus_addr = argc_no_bus_addr + 2; -#ifdef CONFIG_SYS_DEF_EEPROM_ADDR +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR if (argc == argc_no_bus_addr) { *i2c_bus = -1; - *i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR; + *i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR; return 0; } diff --git a/cmd/fdt.c b/cmd/fdt.c index c42f1c79d499c1903de5cd926434bb4d1a0468af..2a207bf2b51554aac48d2768a02636bff3a583f8 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -624,7 +624,7 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) fdt_strerror(err)); return CMD_RET_FAILURE; } -#ifdef CONFIG_SOC_KEYSTONE +#ifdef CONFIG_ARCH_KEYSTONE ft_board_setup_ex(working_fdt, gd->bd); #endif } diff --git a/cmd/i2c.c b/cmd/i2c.c index c7c08c4e32de2adf3028061e4eafff65af9d65ce..9050b2b8d27a504b1a144e68127aa41494be94ea 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -98,7 +98,7 @@ static uint i2c_mm_last_alen; * pairs. The following macros take care of this */ #if defined(CONFIG_SYS_I2C_NOPROBES) -#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) static struct { uchar bus; @@ -114,7 +114,7 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) #define NO_PROBE_ADDR(i) i2c_no_probes[(i)] -#endif /* defined(CONFIG_SYS_I2C_LEGACY) */ +#endif /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */ #endif #define DISP_LINE_LEN 16 @@ -195,54 +195,6 @@ void i2c_init_board(void) { } -/* TODO: Implement architecture-specific get/set functions */ - -/** - * i2c_get_bus_speed() - Return I2C bus speed - * - * This function is the default implementation of function for retrieveing - * the current I2C bus speed in Hz. - * - * A driver implementing runtime switching of I2C bus speed must override - * this function to report the speed correctly. Simple or legacy drivers - * can use this fallback. - * - * Returns I2C bus speed in Hz. - */ -#if !defined(CONFIG_SYS_I2C_LEGACY) && !CONFIG_IS_ENABLED(DM_I2C) -/* - * TODO: Implement architecture-specific get/set functions - * Should go away, if we switched completely to new multibus support - */ -__weak -unsigned int i2c_get_bus_speed(void) -{ - return CONFIG_SYS_I2C_SPEED; -} - -/** - * i2c_set_bus_speed() - Configure I2C bus speed - * @speed: Newly set speed of the I2C bus in Hz - * - * This function is the default implementation of function for setting - * the I2C bus speed in Hz. - * - * A driver implementing runtime switching of I2C bus speed must override - * this function to report the speed correctly. Simple or legacy drivers - * can use this fallback. - * - * Returns zero on success, negative value on error. - */ -__weak -int i2c_set_bus_speed(unsigned int speed) -{ - if (speed != CONFIG_SYS_I2C_SPEED) - return -1; - - return 0; -} -#endif - /** * get_alen() - Small parser helper function to get address length * @@ -922,7 +874,7 @@ static int mod_i2c_mem(struct cmd_tbl *cmdtp, int incrflag, int flag, int argc, if (ret) return i2c_report_err(ret, I2C_ERR_WRITE); -#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS +#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif if (incrflag) @@ -1725,7 +1677,7 @@ static void show_bus(struct udevice *bus) * * Returns zero always. */ -#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -1811,7 +1763,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, * Returns zero on success, CMD_RET_USAGE in case of misuse and negative * on error. */ -#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \ +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \ CONFIG_IS_ENABLED(DM_I2C) static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -1834,7 +1786,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, printf("Current bus is %d\n", bus_no); } else { bus_no = dectoul(argv[1], NULL); -#if defined(CONFIG_SYS_I2C_LEGACY) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", bus_no); return -1; @@ -1852,7 +1804,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, return ret ? CMD_RET_FAILURE : 0; } -#endif /* defined(CONFIG_SYS_I2C_LEGACY) */ +#endif /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */ /** * do_i2c_bus_speed() - Handle the "i2c speed" command-line command @@ -1951,20 +1903,18 @@ static int do_i2c_reset(struct cmd_tbl *cmdtp, int flag, int argc, printf("Error: Not supported by the driver\n"); return CMD_RET_FAILURE; } -#elif defined(CONFIG_SYS_I2C_LEGACY) +#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr); -#else - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif return 0; } static struct cmd_tbl cmd_i2c_sub[] = { -#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""), #endif U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), -#if defined(CONFIG_SYS_I2C_LEGACY) || \ +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), #endif /* CONFIG_I2C_MULTI_BUS */ @@ -2036,12 +1986,12 @@ static int do_i2c(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /***************************************************/ #ifdef CONFIG_SYS_LONGHELP static char i2c_help_text[] = -#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n" "i2c " /* That's the prefix for the crc32 command below. */ #endif "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" -#if defined(CONFIG_SYS_I2C_LEGACY) || \ +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) "i2c dev [dev] - show or set current I2C bus\n" #endif /* CONFIG_I2C_MULTI_BUS */ diff --git a/cmd/load.c b/cmd/load.c index 381ed1b3e25bb2ace17a607bbd9a2394e6df2b7b..249ebd4ae078a267848bfcf54c0a881eae31fc48 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -474,6 +474,14 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc, addr = load_serial_ymodem(offset, xyzModem_ymodem); + if (addr == ~0) { + image_load_addr = 0; + printf("## Binary (ymodem) download aborted\n"); + rcode = 1; + } else { + printf("## Start Addr = 0x%08lX\n", addr); + image_load_addr = addr; + } } else if (strcmp(argv[0],"loadx")==0) { printf("## Ready for binary (xmodem) download " "to 0x%08lX at %d bps...\n", @@ -482,6 +490,14 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc, addr = load_serial_ymodem(offset, xyzModem_xmodem); + if (addr == ~0) { + image_load_addr = 0; + printf("## Binary (xmodem) download aborted\n"); + rcode = 1; + } else { + printf("## Start Addr = 0x%08lX\n", addr); + image_load_addr = addr; + } } else { printf("## Ready for binary (kermit) download " @@ -535,6 +551,9 @@ static ulong load_serial_bin(ulong offset) udelay(1000); } + if (size == 0) + return ~0; /* Download aborted */ + flush_cache(offset, size); printf("## Total Size = 0x%08x = %d Bytes\n", size, size); @@ -975,6 +994,7 @@ static ulong load_serial_ymodem(ulong offset, int mode) res = xyzModem_stream_open(&info, &err); if (!res) { + err = 0; while ((res = xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0) { store_addr = addr + offset; @@ -987,6 +1007,9 @@ static ulong load_serial_ymodem(ulong offset, int mode) rc = flash_write((char *) ymodemBuf, store_addr, res); if (rc != 0) { + xyzModem_stream_terminate(true, &getcxmodem); + xyzModem_stream_close(&err); + printf("\n"); flash_perror(rc); return (~0); } @@ -998,16 +1021,24 @@ static ulong load_serial_ymodem(ulong offset, int mode) } } + if (err) { + xyzModem_stream_terminate((err == xyzModem_cancel) ? false : true, &getcxmodem); + xyzModem_stream_close(&err); + printf("\n%s\n", xyzModem_error(err)); + return (~0); /* Download aborted */ + } + if (IS_ENABLED(CONFIG_CMD_BOOTEFI)) efi_set_bootdev("Uart", "", "", map_sysmem(offset, 0), size); } else { - printf("%s\n", xyzModem_error(err)); + printf("\n%s\n", xyzModem_error(err)); + return (~0); /* Download aborted */ } - xyzModem_stream_close(&err); xyzModem_stream_terminate(false, &getcxmodem); + xyzModem_stream_close(&err); flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN)); diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index 340fb3aff6b85e7731912a7e02c1423aeadbd0c1..ac8b0afd20e59d29c401ad00bfa5a121a61fa929 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -3,7 +3,6 @@ depends on ARCH_MVEBU config CMD_MVEBU_BUBT bool "bubt" - default n select SHA256 if ARMADA_3700 help bubt - Burn a u-boot image to flash diff --git a/cmd/pci.c b/cmd/pci.c index af75a6cfff4ada78f61c0af34b35ffa2d5905116..cfabdc0f3012fbcb3818f08e6e777de6563181da 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -59,7 +59,7 @@ static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs) } } -int pci_bar_show(struct udevice *dev) +static int pci_bar_show(struct udevice *dev) { u8 header_type; int bar_cnt, bar_id, mem_type; @@ -223,7 +223,7 @@ static struct pci_reg_info regs_cardbus[] = { * * @dev: Bus+Device+Function number */ -void pci_header_show(struct udevice *dev) +static void pci_header_show(struct udevice *dev) { unsigned long class, header_type; @@ -251,7 +251,7 @@ void pci_header_show(struct udevice *dev) } } -void pciinfo_header(int busnum, bool short_listing) +static void pciinfo_header(int busnum, bool short_listing) { printf("Scanning PCI devices on bus %d\n", busnum); diff --git a/cmd/pvblock.c b/cmd/pvblock.c index 4e99b06122be971d1cb55a6bc34b7e578237ebf6..56ce8b18d511cd10ef5798e05a4e2d6778ea8aef 100644 --- a/cmd/pvblock.c +++ b/cmd/pvblock.c @@ -27,4 +27,3 @@ U_BOOT_CMD(pvblock, 5, 1, do_pvblock, "pvblock write addr blk# cnt - read/write `cnt'" " blocks starting at block `blk#'\n" " to/from memory address `addr'"); - diff --git a/cmd/qfw.c b/cmd/qfw.c index eb6a552f6fad745b1591d5f44044fbd744b73821..d58615040c64dc110fd5aac1dcfe46846668d136 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -121,11 +121,7 @@ static int qemu_fwcfg_do_load(struct cmd_tbl *cmdtp, int flag, env = env_get("loadaddr"); load_addr = env ? (void *)hextoul(env, NULL) : -#ifdef CONFIG_LOADADDR - (void *)CONFIG_LOADADDR; -#else - NULL; -#endif + (void *)CONFIG_SYS_LOAD_ADDR; env = env_get("ramdiskaddr"); initrd_addr = env ? diff --git a/cmd/scp03.c b/cmd/scp03.c index 655e0bba08b205eed61324015ea57de500764527..216c942dd48bafc4140d39be6774a38de891501d 100644 --- a/cmd/scp03.c +++ b/cmd/scp03.c @@ -49,4 +49,3 @@ static char text[] = U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text, U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable), U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision)); - diff --git a/cmd/smccc.c b/cmd/smccc.c index f5271817729ab9cb76773fcb3f51878ca6c7dc3a..0539a42587e26d66097b7cf63018b461533bea56 100644 --- a/cmd/smccc.c +++ b/cmd/smccc.c @@ -69,4 +69,3 @@ U_BOOT_CMD( " - id Session ID, passed to W7 (defaults to zero)\n" ); #endif - diff --git a/cmd/spi.c b/cmd/spi.c index bdbdbacecd9705ad1d237daf359aad33bf25e7a7..6dc32678da108b5cfe9782abcd2503cf659453cd 100644 --- a/cmd/spi.c +++ b/cmd/spi.c @@ -29,9 +29,9 @@ static unsigned int bus; static unsigned int cs; static unsigned int mode; static unsigned int freq; -static int bitlen; -static uchar dout[MAX_SPI_BYTES]; -static uchar din[MAX_SPI_BYTES]; +static int bitlen; +static uchar dout[MAX_SPI_BYTES]; +static uchar din[MAX_SPI_BYTES]; static int do_spi_xfer(int bus, int cs) { diff --git a/cmd/spl.c b/cmd/spl.c index 472703f8fe1542bf1215f852d927a78072ffadb0..8a2ded72be9ff7703426cc6df1bf66cf8933b465 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -32,11 +32,7 @@ static const char **subcmd_list[] = { NULL, }, [SPL_EXPORT_ATAGS] = (const char * []) { -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) +#ifdef CONFIG_SUPPORT_PASSING_ATAGS "start", "loados", #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/cmd/version.c b/cmd/version.c index 685b458ce262a2061252875cf38e1362acc43750..f83f6aff92ca6c1df5c04ea8c8263c0ef628e46f 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -6,13 +6,18 @@ #include #include +#include #include +#include #include #ifdef CONFIG_SYS_COREBOOT #include #endif -const char __weak version_string[] = U_BOOT_VERSION_STRING; +#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING + +const char version_string[] = U_BOOT_VERSION_STRING; static int do_version(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/common/Kconfig b/common/Kconfig index ee14d3ad5bfd8e7df90030c39552d39071cdfa73..0543b839d180d34647089ea855efc128042a9403 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -548,6 +548,12 @@ config MISC_INIT_R help Enabling this option calls 'misc_init_r' function +config ID_EEPROM + bool "Enable I2C connected system identifier EEPROM" + help + A number of different systems and vendors enable a vendor-specified + EEPROM that contains various identifying features. + config PCI_INIT_R bool "Enumerate PCI buses during init" depends on PCI @@ -627,7 +633,6 @@ config TPL_HASH config STACKPROTECTOR bool "Stack Protector buffer overflow detection" - default n help Enable stack smash detection through compiler's stack-protector canary logic @@ -635,12 +640,10 @@ config STACKPROTECTOR config SPL_STACKPROTECTOR bool "Stack Protector buffer overflow detection for SPL" depends on STACKPROTECTOR && SPL - default n config TPL_STACKPROTECTOR bool "Stack Protector buffer overflow detection for TPL" depends on STACKPROTECTOR && TPL - default n endmenu @@ -648,7 +651,6 @@ menu "Update support" config UPDATE_COMMON bool - default n select DFU_WRITE_ALT config UPDATE_TFTP @@ -680,7 +682,6 @@ config UPDATE_FIT config ANDROID_AB bool "Android A/B updates" - default n help If enabled, adds support for the new Android A/B update model. This allows the bootloader to select which slot to boot from based on the diff --git a/common/Kconfig.boot b/common/Kconfig.boot index 902a5b8fbeaef3e77492390c50cd3371d42a28e9..f23b99885212ab82dc2ee5428870bd1cd0535843 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -80,7 +80,6 @@ config FIT_SIGNATURE_MAX_SIZE config FIT_RSASSA_PSS bool "Support rsassa-pss signature scheme of FIT image contents" depends on FIT_SIGNATURE - default n help Enable this to support the pss padding algorithm as described in the rfc8017 (https://tools.ietf.org/html/rfc8017). @@ -373,6 +372,26 @@ config CHROMEOS_VBOOT distinguishing between booting Chrome OS in a basic way (developer mode) and a full boot. +config RAMBOOT_PBL + bool "Freescale PBL(pre-boot loader) image format support" + help + Some SoCs use PBL to load RCW and/or pre-initialization instructions. + For more details refer to doc/README.pblimage + +config SYS_FSL_PBL_PBI + string "PBI(pre-boot instructions) commands for the PBL image" + depends on RAMBOOT_PBL + help + PBI commands can be used to configure SoC before it starts the execution. + Please refer doc/README.pblimage for more details. + +config SYS_FSL_PBL_RCW + string "Aadditional RCW (Power on reset configuration) for the PBL image" + depends on RAMBOOT_PBL + help + Enables addition of RCW (Power on reset configuration) in built image. + Please refer doc/README.pblimage for more details. + endmenu # Boot images menu "Boot timing" @@ -682,7 +701,6 @@ config NOR_BOOT config NAND_BOOT bool "Support for booting from NAND flash" - default n imply MTD_RAW_NAND help Enabling this will make a U-Boot binary that is capable of being @@ -691,7 +709,6 @@ config NAND_BOOT config ONENAND_BOOT bool "Support for booting from ONENAND" - default n imply MTD_RAW_NAND help Enabling this will make a U-Boot binary that is capable of being @@ -700,7 +717,6 @@ config ONENAND_BOOT config QSPI_BOOT bool "Support for booting from QSPI flash" - default n help Enabling this will make a U-Boot binary that is capable of being booted via QSPI flash. This is not a must, some SoCs need this, @@ -708,7 +724,6 @@ config QSPI_BOOT config SATA_BOOT bool "Support for booting from SATA" - default n help Enabling this will make a U-Boot binary that is capable of being booted via SATA. This is not a must, some SoCs need this, @@ -716,7 +731,6 @@ config SATA_BOOT config SD_BOOT bool "Support for booting from SD/EMMC" - default n help Enabling this will make a U-Boot binary that is capable of being booted via SD/EMMC. This is not a must, some SoCs need this, @@ -724,7 +738,6 @@ config SD_BOOT config SPI_BOOT bool "Support for booting from SPI flash" - default n help Enabling this will make a U-Boot binary that is capable of being booted via SPI flash. This is not a must, some SoCs need this, @@ -758,7 +771,6 @@ config BOOTDELAY config AUTOBOOT_KEYED bool "Stop autobooting via specific input key / string" - default n help This option enables stopping (aborting) of the automatic boot feature only by issuing a specific input key or @@ -845,7 +857,6 @@ config AUTOBOOT_STOP_STR config AUTOBOOT_KEYED_CTRLC bool "Enable Ctrl-C autoboot interruption" depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION - default n help This option allows for the boot sequence to be interrupted by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey". diff --git a/common/Makefile b/common/Makefile index ae0430c35fe460318b8711758815b8c84deaaf65..fb8173a5b8290a82ca0eb03beb652174a2203b20 100644 --- a/common/Makefile +++ b/common/Makefile @@ -66,7 +66,7 @@ ifdef CONFIG_SPL_DFU obj-$(CONFIG_DFU_OVER_USB) += dfu.o endif obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o -obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o +obj-$(CONFIG_SPL_NET) += miiphyutil.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o ifdef CONFIG_SPL_USB_HOST @@ -85,9 +85,9 @@ obj-$(CONFIG_HWCONFIG) += hwconfig.o obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_TPL_SERIAL_SUPPORT) += console.o +obj-$(CONFIG_TPL_SERIAL) += console.o else -obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o +obj-$(CONFIG_SPL_SERIAL) += console.o endif else obj-y += console.o diff --git a/common/autoboot.c b/common/autoboot.c index 5bb2e190895fc62d788fa4143c5f4212cf405095..6251c6831089a23ca511defdd9d67e28cc4adfee 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -24,6 +24,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -424,12 +425,12 @@ static void process_fdt_options(const void *blob) ulong addr; /* Add an env variable to point to a kernel payload, if available */ - addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0); + addr = ofnode_conf_read_int("kernel-offset", 0); if (addr) env_set_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); /* Add an env variable to point to a root disk, if available */ - addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); + addr = ofnode_conf_read_int("rootdisk-offset", 0); if (addr) env_set_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); #endif /* CONFIG_SYS_TEXT_BASE */ @@ -446,8 +447,7 @@ const char *bootdelay_process(void) bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; if (IS_ENABLED(CONFIG_OF_CONTROL)) - bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", - bootdelay); + bootdelay = ofnode_conf_read_int("bootdelay", bootdelay); debug("### main_loop entered: bootdelay=%d\n\n", bootdelay); diff --git a/common/board_f.c b/common/board_f.c index f2746537c96b1f8a044370e7e2d4700cdce213e0..3dc0eaa59c53eef55dd5be5aa8ba2957176bc3f2 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -244,7 +244,7 @@ __weak int dram_init_banksize(void) return 0; } -#if defined(CONFIG_SYS_I2C_LEGACY) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) static int init_func_i2c(void) { puts("I2C: "); @@ -871,7 +871,7 @@ static const init_fnc_t init_sequence_f[] = { misc_init_f, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_SYS_I2C_LEGACY) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) init_func_i2c, #endif #if defined(CONFIG_VID) && !defined(CONFIG_SPL) diff --git a/common/board_r.c b/common/board_r.c index 630c2451a272e0f5ec1beba88c691348f3a75b27..31a59c585a8d93861c2a39b92891b10ffb76da41 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -67,6 +67,7 @@ #endif #include #include +#include #include #include #include @@ -448,8 +449,7 @@ static int initr_pvblock(void) static int should_load_env(void) { if (IS_ENABLED(CONFIG_OF_CONTROL)) - return fdtdec_get_config_int(gd->fdt_blob, - "load-environment", 1); + return ofnode_conf_read_int("load-environment", 1); if (IS_ENABLED(CONFIG_DELAY_ENVIRONMENT)) return 0; @@ -720,7 +720,7 @@ static init_fnc_t init_sequence_r[] = { #endif INIT_FUNC_WATCHDOG_RESET cpu_secondary_init_r, -#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) +#if defined(CONFIG_ID_EEPROM) mac_read_from_eeprom, #endif INIT_FUNC_WATCHDOG_RESET diff --git a/common/cli.c b/common/cli.c index 048eacb9ef97bd3d240c61e44a74b9c00004a639..d86046a728b8500ff36b90289c4f1fcdb137a1e9 100644 --- a/common/cli.c +++ b/common/cli.c @@ -19,8 +19,7 @@ #include #include #include - -DECLARE_GLOBAL_DATA_PTR; +#include #ifdef CONFIG_CMDLINE /* @@ -157,7 +156,7 @@ int do_run(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) bool cli_process_fdt(const char **cmdp) { /* Allow the fdt to override the boot command */ - char *env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd"); + const char *env = ofnode_conf_read_str("bootcmd"); if (env) *cmdp = env; /* @@ -165,7 +164,7 @@ bool cli_process_fdt(const char **cmdp) * Always use 'env' in this case, since bootsecure requres that the * bootcmd was specified in the FDT too. */ - return fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0) != 0; + return ofnode_conf_read_int("bootsecure", 0); } /* diff --git a/common/hash.c b/common/hash.c index 6277fe65b3eb43650a3a9ab17661725dac137466..3884298edf23f08fffd488d1dd388fa7bcf6a388 100644 --- a/common/hash.c +++ b/common/hash.c @@ -228,7 +228,7 @@ static struct hash_algo hash_algo[] = { #endif #ifdef CONFIG_SHA1 { - .name = "sha1", + .name = "sha1", .digest_size = SHA1_SUM_LEN, .chunk_size = CHUNKSZ_SHA1, #ifdef CONFIG_SHA_HW_ACCEL diff --git a/common/hwconfig.c b/common/hwconfig.c index 26a561c365b7b91eed7dd1791e391c8daad3209a..63b3ccaf84e29c786028a800328ec04ee02e5793 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -179,7 +179,7 @@ int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf) * * This call is similar to hwconfig_f(), except that it takes additional * argument @subopt. In this example: - * "dr_usb:mode=peripheral" + * "dr_usb:mode=peripheral" * "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its * argument. */ diff --git a/common/image-fdt.c b/common/image-fdt.c index 9441e63a3d4fd717dc6f6bf62068312a43601e2e..b698e961fe795f32ff872f8ab634745f362d165b 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -628,7 +628,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, if (!ft_verify_fdt(blob)) goto err; -#if defined(CONFIG_SOC_KEYSTONE) +#if defined(CONFIG_ARCH_KEYSTONE) if (IMAGE_OF_BOARD_SETUP) ft_board_setup_ex(blob, gd->bd); #endif diff --git a/common/image-fit.c b/common/image-fit.c index f02d437539ffddbd677f45594ecb581516d8d192..5a0a0cc200727890c32ae797c2dc207681089c97 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -25,6 +25,10 @@ #include #include #include +#ifdef CONFIG_DM_HASH +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ @@ -1214,6 +1218,31 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) int calculate_hash(const void *data, int data_len, const char *name, uint8_t *value, int *value_len) { +#if !defined(USE_HOSTCC) && defined(CONFIG_DM_HASH) + int rc; + enum HASH_ALGO hash_algo; + struct udevice *dev; + + rc = uclass_get_device(UCLASS_HASH, 0, &dev); + if (rc) { + debug("failed to get hash device, rc=%d\n", rc); + return -1; + } + + hash_algo = hash_algo_lookup_by_name(algo); + if (hash_algo == HASH_ALGO_INVALID) { + debug("Unsupported hash algorithm\n"); + return -1; + }; + + rc = hash_digest_wd(dev, hash_algo, data, data_len, value, CHUNKSZ); + if (rc) { + debug("failed to get hash value, rc=%d\n", rc); + return -1; + } + + *value_len = hash_algo_digest_size(hash_algo); +#else struct hash_algo *algo; int ret; @@ -1225,6 +1254,7 @@ int calculate_hash(const void *data, int data_len, const char *name, algo->hash_func_ws(data, data_len, value, algo->chunk_size); *value_len = algo->digest_size; +#endif return 0; } diff --git a/common/image.c b/common/image.c index 59c52a1f9ad36c14af287933f5507ce9be25ffe4..e199d61a4c3913fc85d0331b2c7bedf5b2f6ad9a 100644 --- a/common/image.c +++ b/common/image.c @@ -216,6 +216,8 @@ static const struct comp_magic_map image_comp[] = { { IH_COMP_GZIP, "gzip", {0x1f, 0x8b},}, { IH_COMP_LZMA, "lzma", {0x5d, 0x00},}, { IH_COMP_LZO, "lzo", {0x89, 0x4c},}, + { IH_COMP_LZ4, "lz4", {0x04, 0x22},}, + { IH_COMP_ZSTD, "zstd", {0x28, 0xb5},}, { IH_COMP_NONE, "none", {}, }, }; diff --git a/common/lcd_console.c b/common/lcd_console.c index 9c0ff4480eb807eb7ac4c07ab3c636d05f9555d6..ed36c78440c0a5469e3668c634436b4823fedf20 100644 --- a/common/lcd_console.c +++ b/common/lcd_console.c @@ -258,4 +258,3 @@ U_BOOT_CMD( "print string on lcd-framebuffer", " " ); - diff --git a/common/main.c b/common/main.c index ae5bcdb32f8bacec599d558a636df6dc7f3664d4..3f5214fd44b8643199e9a6bd69a2711d833c5049 100644 --- a/common/main.c +++ b/common/main.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include static void run_preboot_environment_command(void) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 29a46c47877a4d930be4ca66107ce42451325c9f..34f6fc2cfad6b17ca98bef13136c8c50d1899c72 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -196,7 +196,7 @@ config SPL_BOOTCOUNT_LIMIT config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" - default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) + default n if (ARCH_MX6 && (SPL_MMC || SPL_SATA)) default y if !TI_SECURE_DEVICE help SPL will support loading and booting a RAW image when this option @@ -453,7 +453,7 @@ config SPL_FIT_IMAGE_TINY ensure this information is available to the next image invoked). -config SPL_CACHE_SUPPORT +config SPL_CACHE bool "Support CACHE drivers" help Enable CACHE drivers in SPL. These drivers can keep data so that @@ -522,12 +522,13 @@ config SPL_SAVEENV config SPL_ETH bool "Support Ethernet" depends on SPL_ENV_SUPPORT + depends on SPL_NET help Enable access to the network subsystem and associated Ethernet drivers in SPL. This permits SPL to load U-Boot over an Ethernet link rather than from an on-board peripheral. Environment support is required since the network stack uses a number of environment - variables. See also SPL_NET_SUPPORT. + variables. See also SPL_NET. config SPL_FS_EXT4 bool "Support EXT filesystems" @@ -637,7 +638,7 @@ config SPL_DM_MAILBOX this option to build the drivers in drivers/mailbox as part of SPL build. -config SPL_MMC_SUPPORT +config SPL_MMC bool "Support MMC" depends on MMC select HAVE_BLOCK_DEVICE @@ -658,8 +659,7 @@ config SYS_MMCSD_FS_BOOT_PARTITION config SPL_MMC_TINY bool "Tiny MMC framework in SPL" - depends on SPL_MMC_SUPPORT - default n + depends on SPL_MMC help Enable MMC framework tinification support. This option is useful if if your SPL is extremely size constrained. Heed the warning, enable @@ -675,13 +675,12 @@ config SPL_MMC_TINY config SPL_MMC_WRITE bool "MMC/SD/SDIO card support for write operations in SPL" - depends on SPL_MMC_SUPPORT - default n + depends on SPL_MMC help Enable write access to MMC and SD Cards in SPL -config SPL_MPC8XXX_INIT_DDR_SUPPORT +config SPL_MPC8XXX_INIT_DDR bool "Support MPC8XXX DDR init" help Enable support for DDR-SDRAM (double-data-rate synchronous dynamic @@ -747,12 +746,6 @@ config SPL_UBI README.ubispl for more info. if SPL_DM -config SPL_CACHE - depends on CACHE - bool "Support cache drivers in SPL" - help - Enable support for cache drivers in SPL. - config SPL_DM_SPI bool "Support SPI DM drivers in SPL" help @@ -849,14 +842,13 @@ config SPL_UBI_LOAD_ARGS_ID config UBI_SPL_SILENCE_MSG bool "silence UBI SPL messages" - default n help Disable messages from UBI SPL. This leaves warnings and errors enabled. endif # if SPL_UBI -config SPL_NET_SUPPORT +config SPL_NET bool "Support networking" help Enable support for network devices (such as Ethernet) in SPL. @@ -865,7 +857,7 @@ config SPL_NET_SUPPORT the network stack uses a number of environment variables. See also SPL_ETH. -if SPL_NET_SUPPORT +if SPL_NET config SPL_NET_VCI_STRING string "BOOTP Vendor Class Identifier string sent by SPL" help @@ -874,7 +866,7 @@ config SPL_NET_VCI_STRING of a client. This is often used in practice to allow for the DHCP server to specify different files to load depending on if the ROM, SPL or U-Boot itself makes the request -endif # if SPL_NET_SUPPORT +endif # if SPL_NET config SPL_NO_CPU_SUPPORT bool "Drop CPU code in SPL" @@ -912,7 +904,6 @@ config SPL_ONENAND_SUPPORT config SPL_OS_BOOT bool "Activate Falcon Mode" depends on !TI_SECURE_DEVICE - default n help Enable booting directly to an OS from SPL. for more info read doc/README.falcon @@ -945,7 +936,7 @@ config SPL_PCI necessary driver support. This enables the drivers in drivers/pci as part of an SPL build. -config SPL_PCH_SUPPORT +config SPL_PCH bool "Support PCH drivers" help Enable support for PCH (Platform Controller Hub) devices in SPL. @@ -985,6 +976,7 @@ config SPL_POWER config SPL_POWER_DOMAIN bool "Support power domain drivers" + select SPL_POWER help Enable support for power domain control in SPL. Many SoCs allow power to be applied to or removed from portions of the SoC (power @@ -1014,7 +1006,7 @@ config SPL_REMOTEPROC Enable support for REMOTEPROCs in SPL. This permits to load a remote processor firmware in SPL. -config SPL_RTC_SUPPORT +config SPL_RTC bool "Support RTC drivers" help Enable RTC (Real-time Clock) support in SPL. This includes support @@ -1023,7 +1015,7 @@ config SPL_RTC_SUPPORT needed. This enables the drivers in drivers/rtc as part of an SPL build. -config SPL_SATA_SUPPORT +config SPL_SATA bool "Support loading from SATA" help Enable support for SATA (Serial AT attachment) in SPL. This allows @@ -1035,7 +1027,7 @@ config SPL_SATA_SUPPORT config SPL_SATA_RAW_U_BOOT_USE_SECTOR bool "SATA raw mode: by sector" - depends on SPL_SATA_SUPPORT + depends on SPL_SATA default y if ARCH_MVEBU help Use sector number for specifying U-Boot location on SATA disk in @@ -1049,7 +1041,7 @@ config SPL_SATA_RAW_U_BOOT_SECTOR Sector on the SATA disk to load U-Boot from, when the SATA disk is being used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes). -config SPL_SERIAL_SUPPORT +config SPL_SERIAL bool "Support serial" select SPL_PRINTF select SPL_STRTO @@ -1060,7 +1052,7 @@ config SPL_SERIAL_SUPPORT unless there are space reasons not to. Even then, consider enabling SPL_USE_TINY_PRINTF which is a small printf() version. -config SPL_SPI_SUPPORT +config SPL_SPI bool "Support SPI drivers" help Enable support for using SPI in SPL. This is used for connecting @@ -1072,14 +1064,14 @@ config SPL_SPI_SUPPORT config SPL_SPI_FLASH_SUPPORT bool "Support SPI flash drivers" - depends on SPL_SPI_SUPPORT + depends on SPL_SPI help Enable support for using SPI flash in SPL, and loading U-Boot from SPI flash. SPI flash (Serial Peripheral Bus flash) is named after the SPI bus that is used to connect it to a system. It is a simple but fast bidirectional 4-wire bus (clock, chip select and two data lines). This enables the drivers in drivers/mtd/spi as part of an - SPL build. This normally requires SPL_SPI_SUPPORT. + SPL build. This normally requires SPL_SPI. if SPL_SPI_FLASH_SUPPORT @@ -1162,13 +1154,14 @@ if SPL_USB_GADGET config SPL_USB_ETHER bool "Support USB Ethernet drivers" + depends on SPL_NET help Enable access to the USB network subsystem and associated drivers in SPL. This permits SPL to load U-Boot over a USB-connected Ethernet link (such as a USB Ethernet dongle) rather than from an onboard peripheral. Environment support is required since the network stack uses a number of environment variables. - See also SPL_NET_SUPPORT and SPL_ETH. + See also SPL_NET and SPL_ETH. config SPL_DFU bool "Support DFU (Device Firmware Upgrade)" @@ -1199,7 +1192,7 @@ endchoice config SPL_USB_SDP_SUPPORT bool "Support SDP (Serial Download Protocol)" - depends on SPL_SERIAL_SUPPORT + depends on SPL_SERIAL help Enable Serial Download Protocol (SDP) device support in SPL. This allows to download images into memory and execute (jump to) them @@ -1225,7 +1218,7 @@ config SPL_WATCHDOG config SPL_YMODEM_SUPPORT bool "Support loading using Ymodem" - depends on SPL_SERIAL_SUPPORT + depends on SPL_SERIAL help While loading from serial is slow it can be a useful backup when there is no other option. The Ymodem protocol provides a reliable @@ -1359,7 +1352,6 @@ config TPL_LDSCRIPT config TPL_NEEDS_SEPARATE_TEXT_BASE bool "TPL needs a separate text-base" - default n depends on TPL help Enable, if the TPL stage should not inherit its text-base @@ -1368,12 +1360,23 @@ config TPL_NEEDS_SEPARATE_TEXT_BASE config TPL_NEEDS_SEPARATE_STACK bool "TPL needs a separate initial stack-pointer" - default n depends on TPL help Enable, if the TPL stage should not inherit its initial stack-pointer from the settings for the SPL stage. +config TPL_POWER + bool "Support power drivers" + help + Enable support for power control in TPL. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in TPL to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of an TPL build. + config TPL_TEXT_BASE hex "Base address for the .text section of the TPL stage" depends on TPL_NEEDS_SEPARATE_TEXT_BASE @@ -1458,17 +1461,17 @@ config TPL_LIBGENERIC_SUPPORT Enable support for generic U-Boot libraries within TPL. See SPL_LIBGENERIC_SUPPORT for details. -config TPL_MPC8XXX_INIT_DDR_SUPPORT +config TPL_MPC8XXX_INIT_DDR bool "Support MPC8XXX DDR init" help Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See - SPL_MPC8XXX_INIT_DDR_SUPPORT for details. + SPL_MPC8XXX_INIT_DDR for details. -config TPL_MMC_SUPPORT +config TPL_MMC bool "Support MMC" depends on MMC help - Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details. + Enable support for MMC within TPL. See SPL_MMC for details. config TPL_NAND_SUPPORT bool "Support NAND flash" @@ -1483,7 +1486,7 @@ config TPL_PCI necessary driver support. This enables the drivers in drivers/pci as part of a TPL build. -config TPL_PCH_SUPPORT +config TPL_PCH bool "Support PCH drivers" help Enable support for PCH (Platform Controller Hub) devices in TPL. @@ -1505,7 +1508,7 @@ config TPL_RAM_DEVICE be already in memory when TPL takes over, e.g. loaded by the boot ROM. -config TPL_RTC_SUPPORT +config TPL_RTC bool "Support RTC drivers" help Enable RTC (Real-time Clock) support in TPL. This includes support @@ -1514,12 +1517,12 @@ config TPL_RTC_SUPPORT needed. This enables the drivers in drivers/rtc as part of an TPL build. -config TPL_SERIAL_SUPPORT +config TPL_SERIAL bool "Support serial" select TPL_PRINTF select TPL_STRTO help - Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for + Enable support for serial in TPL. See SPL_SERIAL for details. config TPL_SPI_FLASH_SUPPORT @@ -1545,10 +1548,10 @@ config TPL_SPI_LOAD Enable support for loading next stage, U-Boot or otherwise, from SPI NOR in U-Boot TPL. -config TPL_SPI_SUPPORT +config TPL_SPI bool "Support SPI drivers" help - Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for + Enable support for using SPI in TPL. See SPL_SPI for details. config TPL_DM_SPI @@ -1563,7 +1566,7 @@ config TPL_DM_SPI_FLASH config TPL_YMODEM_SUPPORT bool "Support loading using Ymodem" - depends on TPL_SERIAL_SUPPORT + depends on TPL_SERIAL help While loading from serial is slow it can be a useful backup when there is no other option. The Ymodem protocol provides a reliable @@ -1575,7 +1578,6 @@ endif # TPL config SPL_AT91_MCK_BYPASS bool "Use external clock signal as a source of main clock for AT91 platforms" depends on ARCH_AT91 - default n help Use external 8 to 24 Mhz clock signal as source of main clock instead of an external crystal oscillator. diff --git a/common/spl/Makefile b/common/spl/Makefile index c576a78126818e54269045995f9048831d1fa12b..cb15c8e827ce4d26047dbb60e3547247e9fb094b 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -19,15 +19,15 @@ obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o endif obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o -obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o -obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o +obj-$(CONFIG_$(SPL_TPL_)NET) += spl_net.o +obj-$(CONFIG_$(SPL_TPL_)MMC) += spl_mmc.o obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o -obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o +obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o diff --git a/common/spl/spl.c b/common/spl/spl.c index d55d3c2848514fd02e24313ff5cbb2ff3c0681c2..ed94d5146cca9c0d13b8d3859b5865cd73eb3375 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -24,6 +24,9 @@ #include #include #include +#if CONFIG_IS_ENABLED(BANNER_PRINT) +#include +#endif #include #include #include @@ -486,7 +489,7 @@ static int spl_common_init(bool setup_malloc) return ret; } #endif - if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { + if (CONFIG_IS_ENABLED(OF_REAL)) { ret = fdtdec_setup(); if (ret) { debug("fdtdec_setup() returned error %d\n", ret); @@ -623,7 +626,7 @@ static int boot_from_devices(struct spl_image_info *spl_image, if (CONFIG_IS_ENABLED(SHOW_ERRORS)) ret = -ENXIO; loader = spl_ll_find_loader(bootdev); - if (CONFIG_IS_ENABLED(SERIAL_SUPPORT) && + if (CONFIG_IS_ENABLED(SERIAL) && CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && !IS_ENABLED(CONFIG_SILENT_CONSOLE)) { if (loader) @@ -821,7 +824,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) */ void preloader_console_init(void) { -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL gd->baudrate = CONFIG_BAUDRATE; serial_init(); /* serial communications setup */ diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 212a2b0992891521e5494d61995002d9b48211fc..d52f8a3eefe6221cca7b3acfa22beab21f127d30 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -194,7 +194,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); if (err) continue; - if (info.sys_ind == + if (info.sys_ind == CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) { partition = type_part; break; diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index df1d5b43d8b52828d7018ae74ae23932f5074910..df9f3a4d00f0ac567af90503319313acebdd92c6 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -81,5 +81,3 @@ SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image); #if CONFIG_IS_ENABLED(DFU) SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image); #endif - - diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 9884e7c18500ce2024ba0691d9b8e2ef629942c5..46ee4058e76616f717368713dc6768617fe4752b 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -16,8 +16,7 @@ #include #include #include - -DECLARE_GLOBAL_DATA_PTR; +#include #ifdef CONFIG_SPL_OS_BOOT /* @@ -103,11 +102,10 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) - payload_offs = fdtdec_get_config_int(gd->fdt_blob, - "u-boot,spl-payload-offset", - payload_offs); -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset", + payload_offs); + } #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header)) diff --git a/common/stdio.c b/common/stdio.c index 4083e4edb8f86ef527ce6b4a73db33b16a316397..0f2eb6f0d618a00fca5746b958846e8cc0958e7e 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -336,7 +336,7 @@ int stdio_add_devices(void) dev->name); } } -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) i2c_init_all(); #endif if (IS_ENABLED(CONFIG_DM_VIDEO)) { diff --git a/common/usb_storage.c b/common/usb_storage.c index 946c6b2b323ab62747c82e5d31b5f6b43d62b6ba..c9e2d7343ce2d81e3676da8e69330f64c395b612 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -94,7 +94,7 @@ struct us_data { int action; /* what to do */ int ip_wanted; /* needed */ int *irq_handle; /* for USB int requests */ - unsigned int irqpipe; /* pipe for release_irq */ + unsigned int irqpipe; /* pipe for release_irq */ unsigned char irqmaxp; /* max packed for irq Pipe */ unsigned char irqinterval; /* Intervall for IRQ Pipe */ struct scsi_cmd *srb; /* current srb */ diff --git a/common/xyzModem.c b/common/xyzModem.c index fc3459ebbafe6de956a48afad41f97042283fe2d..ece25acb183b57cfd3ff70c10fcb62c6947cb258 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -32,6 +32,7 @@ /* Values magic to the protocol */ #define SOH 0x01 #define STX 0x02 +#define ETX 0x03 /* ^C for interrupt */ #define EOT 0x04 #define ACK 0x06 #define BSP 0x08 @@ -283,6 +284,7 @@ xyzModem_get_hdr (void) hdr_found = true; break; case CAN: + case ETX: xyz.total_CAN++; ZM_DEBUG (zm_dump (__LINE__)); if (++can_total == xyzModem_CAN_COUNT) @@ -494,7 +496,7 @@ xyzModem_stream_read (char *buf, int size, int *err) total = 0; stat = xyzModem_cancel; /* Try and get 'size' bytes into the buffer */ - while (!xyz.at_eof && (size > 0)) + while (!xyz.at_eof && xyz.len >= 0 && (size > 0)) { if (xyz.len == 0) { @@ -572,6 +574,8 @@ xyzModem_stream_read (char *buf, int size, int *err) CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); ZM_DEBUG (zm_dprintf ("FINAL ACK (%d)\n", __LINE__)); } + else + stat = 0; xyz.at_eof = true; break; } @@ -587,7 +591,7 @@ xyzModem_stream_read (char *buf, int size, int *err) } } /* Don't "read" data from the EOF protocol package */ - if (!xyz.at_eof) + if (!xyz.at_eof && xyz.len > 0) { len = xyz.len; if (size < len) @@ -606,10 +610,10 @@ xyzModem_stream_read (char *buf, int size, int *err) void xyzModem_stream_close (int *err) { - diag_printf + ZM_DEBUG (zm_dprintf ("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX, - xyz.total_CAN, xyz.total_retries); + xyz.total_CAN, xyz.total_retries)); ZM_DEBUG (zm_flush ()); } diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index 31630fe218dbb77db62bc6a7430be8eaa797c062..1ebbcc50f391f55f1a915261fe09fa99a78b811b 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -3,8 +3,10 @@ CONFIG_SYS_CONFIG_NAME="10m50_devboard" CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard" +CONFIG_SYS_LOAD_ADDR=0xcc000000 CONFIG_FIT=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 61a242e2d138ed9769884fd944e2d2c83c898053..edbc8ab139aa7392445ee24d757549cce8c21c9f 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -3,8 +3,10 @@ CONFIG_SYS_CONFIG_NAME="3c120_devboard" CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" +CONFIG_SYS_LOAD_ADDR=0xd4000000 CONFIG_FIT=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index caa0bbf516fc0cbcef31f8eb4ce1bbc16a252565..90f12308bab919004c39b174dbd6525edb014bc5 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -13,6 +13,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_AXP_ALDO3_VOLT=2800 diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index aea7e9bbb2a995dd8ae0f7a87614d1f72ffdb2b4..99f5785751781bed19eb130cf96753449f26fe98 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -10,6 +10,9 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_AXP152_POWER=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 568f64ee66cfd82e824878565393fb02acf141bc..f9d17b19500f14ec1e346e893f65f8c2b3e964dd 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,6 +13,9 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUNXI_NO_PMIC=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index a26064c1b5495d9d9fb88cbc406077dc1b6f39b7..8c9043559bdb23ab1ecb8714f0859a779e69e0f0 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -20,6 +20,9 @@ CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 3936da18c56bee34d41ba5c91b4b4674923275fa..918fc64e0e067d01fe5aa096d0987011db6c81ac 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -19,6 +19,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_REALTEK=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index a8200da0c519769056ac8b1d49d5a5243b3feae1..903e3fdbcc875c0936ebeea7ccc73f28cec81598 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -17,6 +17,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index c949922303c6fe53a557c551768d21183379e44a..c06050610de8a1eb74b624bacad9f35437a19465 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -11,6 +11,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 9679f440542d7a22cf1e153b6184c59aab4465c8..cf3fc682e447bc79b6a9503f8cff8cc09b4af7ff 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -13,6 +13,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 9c8eae1a552ad641e54b164c0c39b7a11e6e432d..81c27432cdca18801ee8ed60824ff06b27478a00 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -14,6 +14,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index a3a701e4e7a2992b4aaea844641f7bc6b2d1c5dd..ececdaca150fe247d571ddaff8777dd7133c9bf3 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -15,6 +15,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 6f2ab1b1ea3ece29cd4fb807e383f7d57e12e6d2..829e7bbcd33ba0c43a7d5faa3ae69fd4da812f03 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -16,6 +16,9 @@ CONFIG_AHCI=y CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_ADDR=3 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index e2388b7a4dafae7fd0de787f24f3da8efc36fbe6..5b96ddc68ba47d458b239c58e9e42c7b407dd3c7 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -15,6 +15,9 @@ CONFIG_AHCI=y CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_ADDR=3 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 7952200cf9849a9fcbdb425cb76ecd33a6b9dad8..9a18af8c6e1129eae2c29bedbabe69c3b431b766 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -15,4 +15,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 638411e2c3abc76274dc73716fb733b00eb23d03..7bf3dfcd8a5ef9f1f14fe5f63aae312c205f812a 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -16,5 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 1ac80a1d964348712e714076d60c7e095282f67d..7d81f12f766df64a1b308dcaa995dcde80b47c2f 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -9,6 +9,9 @@ CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index d1a1de77e49a83bffb20e90eff3a2288eb2a812b..4c7154b04c499e584507b505326078a3bdf64407 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 4073b4dbf13a8476ff3811903d6392e802544fa9..a24c6003010f68f54f39979a44c0a30286fd7fa0 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -13,6 +13,10 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_RGMII=y CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO4_VOLT=2500 diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 41d356b25eb471ce223644c99a83c88021bf0cc7..7f59fc9b3d3e507b85890bacc2265b9a70b1d753 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -12,6 +12,9 @@ CONFIG_AHCI=y CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index ad75ac4f1239bcab72d345a56ae1cf6f89ed8faf..e075635aaddf20194881586001238f1ec951ead2 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -14,6 +14,9 @@ CONFIG_AHCI=y CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 5347d329e218ee2441ebc1f421854972d0752e3b..cd9bdbfd36f77a2b3e92794b4125528ee5faffd5 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -10,6 +10,9 @@ CONFIG_CHIP_DIP_SCAN=y CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 # CONFIG_MMC is not set CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index d013081d3d213ef86dc7d29684c852ac15349a78..34f609a61d223d092c2c4e2c0e31ea535a2ab20d 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -13,6 +13,9 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(ubo CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot-env" +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 4ac95a656165c772489f4aaa504110f247b9e51e..02b3e69584f1857d07eb09eeefd8ae5195f39dc0 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -15,6 +15,9 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y CONFIG_VIDEO_LCD_SPI_CS="PA0" CONFIG_VIDEO_LCD_SPI_SCLK="PA1" diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index a6b3bd438a8cc31fb8111ed41679bbf90fd22a18..31541f898d4e6dab41eb970028874fa12e33eb30 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -17,6 +17,14 @@ CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SPEED=50000 +CONFIG_SYS_I2C_SOFT_SLAVE=0x00 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index d4fc7a59b589ffaa7b88a1061208bd3b91b5a218..b06a3ae4238d97ec53da6ba1ff66345839865a66 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -10,6 +10,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 2a22bc07f69d9b2049b2ae141c3a187f18b8a1bc..93a7932b76a83fa4f33a7f5c0953e14f393bbe41 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -10,6 +10,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 8ec24491c9d80814bc543dd5b586a2887afb89a8..a4f7b872ff02cb49b57e9bb200d4c66373d848f7 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -19,6 +19,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 48d7f344bdd853dd9627674376451666d25e25ea..a4f88697312e5fe14f1c6f6255bf5c34b82cad91 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -16,6 +16,11 @@ CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO3_VOLT=2500 diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index 3811808f3cd060f7f6a56689aab0889752849132..a9bbe8bcffac8b853c3d8f3a2a707f3e3ca81abf 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -17,5 +17,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 8482d8ff2656ecda8e317a33c0c1bcc4d40a20f6..fc1f26b7a998636e608b858efeb5af5b81ee50f0 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -16,5 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 62c0eda5647eea952831a2ea4e19ed8878f49e7d..482e0fb7a83d7ecc5f40571cf3f62c0fbf312221 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -16,4 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 4609347922818d51993d1b42479acd2e4b62be1b..58184422147871cf4068ff2135eba5f5dd309ec1 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -10,6 +10,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index d949f550b7ab7e08af07bca3912c3bf9c457ef7a..6dd7b7ae7024a6123f86b5a789f66df51ad40134 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -12,6 +12,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_B53_SWITCH=y CONFIG_B53_PHY_PORTS=0x1f CONFIG_PHY_REALTEK=y diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index f7151fcf13faa3f0de9229642c470afc82db39e5..25cea8437394bf646eef103a71117880b9d95dd1 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -12,6 +12,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 467e517c7f50b7961abfe0be85d00f61d49a48aa..de88dd0a3031081ff705b0008ebba1074d5f112a 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -10,6 +10,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index dd81e2a9a395f857011d1353aaaeb6f6d8d3920b..49dcfa098ee2a5724c469c01874f219458d464c8 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -7,6 +7,9 @@ CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 3fa0f0783f34e4d58c317478f2b0d73432b3a4da..4d2c300be0f54b847dd5c3d0e48b3e00a3cd719b 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE" CONFIG_TARGET_M5208EVBE=y +CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set @@ -17,6 +19,11 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x2000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x58000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 393bb4998bf2912e3b76d9c87cce77a5cbae023c..c6d4fb115f03a707aae80feeb76c74db8232760f 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFC00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32" CONFIG_TARGET_M5235EVB=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set @@ -22,6 +24,11 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xFFE04000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x300 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index 59a344979814ec638c43ebfc0ae9361e2103f98d..d271144eb994e4c5d177b3c3b432cf955d11b98a 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M5235EVB" CONFIG_TARGET_M5235EVB=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set @@ -22,6 +24,11 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xFFE04000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x300 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index 1535aeca95569964f67eaffa35c2db0984c98dbe..2b7588c0fb6bf38bcfd4dc01478e535cfc3daf40 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" CONFIG_TARGET_M5249EVB=y +CONFIG_SYS_LOAD_ADDR=0x200000 # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_DEVICE_NULLDEV=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 7b3bf78b8f86e40f2e5ef2d858a7a4f9060e1973..ff4142b9255aded7e2fd97288387c1628b13076e 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO" CONFIG_TARGET_M5253DEMO=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set @@ -18,4 +20,9 @@ CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y CONFIG_ENV_ADDR=0xFF804000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x280 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 0a6360d85ea5f13b2cb86ad03692b03c41d29d3e..37b357d9668bfcee10a60e5b1284a1d148119067 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="M5272C3" CONFIG_TARGET_M5272C3=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 5547ee33e3662d0d3cd21bfc4bab0f4cce30bd02..51cbd729fba1c248b88e05703378e85bb4741b3d 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="M5275EVB" CONFIG_TARGET_M5275EVB=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set @@ -20,6 +22,11 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_ADDR=0xFFE04000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x300 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 90a4cf819fb2eb50cee8e168725120233cd8852f..74937278f2f312bab6e12255bb0b4ed7bf761e90 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="M5282EVB" CONFIG_TARGET_M5282EVB=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 950a0fb3382cca8125554dd9084514817d08693e..b4eb9687e5ab31dedba65ecd5368a92f3778dba9 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_SECT_SIZE=0x8000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M53017EVB" CONFIG_TARGET_M53017EVB=y +CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2" @@ -19,6 +21,11 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x40000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x58000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 078abb2356c411f7484e24e781746f345a0aae9f..2c0ef9d0afbb33f1ad3ae7e5c03e9419b6726dcf 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE" CONFIG_TARGET_M5329EVB=y +CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set @@ -20,6 +22,11 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0x4000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x58000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 8b1325e71fe76b3931bab9775f7d8c93cd73afc0..1ff8c87d4fe0a218b15886e40cfefbdb1b5a092a 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE" CONFIG_TARGET_M5329EVB=y +CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set @@ -20,6 +22,11 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0x4000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x58000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 07955785e2e571613770c3a82692e3d91345a5ad..82264cda9c156c44e884f40030cddc6d7d62ae2c 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="M5373EVB" CONFIG_TARGET_M5373EVB=y +CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set @@ -20,6 +22,11 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0x4000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x58000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 924ab160d6ca82f9b4a67688eb271696bd3bc51b..625465557f5a1483de5d25f488a7166876b5f411 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_OR6_PRELIM=0xFFFF0908 CONFIG_SYS_BR7_PRELIM_BOOL=y CONFIG_SYS_BR7_PRELIM=0x1C000001 CONFIG_SYS_OR7_PRELIM=0xFFFF810A +CONFIG_SYS_LOAD_ADDR=0x200000 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 6f003f88d09f21bdb5138b31c204cf7ee5795825..3ed962d7cd94e50a39b579c3cf84c3d26109c341 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -6,5 +6,8 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig deleted file mode 100644 index 8652ff2adcc67c0e1c181c542ebbe74481a69d0b..0000000000000000000000000000000000000000 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ /dev/null @@ -1,117 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_64BIT_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig deleted file mode 100644 index a79fb0e2b47698195989b2c1a1f2e68d71cff1cf..0000000000000000000000000000000000000000 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS_SDRAM=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW2=y -CONFIG_LBLAW2_BASE=0xF0000000 -CONFIG_LBLAW2_NAME="SDRAM" -CONFIG_LBLAW2_LENGTH_64_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="SDRAM" -CONFIG_BR2_OR2_BASE=0xF0000000 -CONFIG_BR2_PORTSIZE_32BIT=y -CONFIG_BR2_MACHINE_SDRAM=y -CONFIG_OR2_COLS_9=y -CONFIG_OR2_ROWS_13=y -CONFIG_OR2_EAD_EXTRA=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_PCI_ONE_PCI1=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig deleted file mode 100644 index 2b7d2fd43fc3230ca88344e95cbb75d6dc5b6a64..0000000000000000000000000000000000000000 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ /dev/null @@ -1,117 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66666666 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_64BIT_MODE_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_PCI_ONE_PCI1=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig deleted file mode 100644 index d8c7951385fc27a8c23d6720475669d164b55fce..0000000000000000000000000000000000000000 --- a/configs/MPC8349EMDS_defconfig +++ /dev/null @@ -1,120 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_PCI_ONE_PCI1=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7106fd15f659682b3753dae1c97d97029163ed16..4945207ef4999f817155279b98599911219a568b 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y @@ -168,6 +169,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_ADDR=0xFE080000 CONFIG_DM=y CONFIG_FSL_SATA=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=400000 CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 72ec1e0f77a17bac0107597218be420df59eb40f..a0e40921d941a6a21fb183e3e453242f3540180a 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -12,8 +13,10 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 # CONFIG_MISC_INIT_R is not set +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y @@ -24,7 +27,12 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_ADDR=0xFFF60000 CONFIG_DM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 9db54768fb5dae841d1d0fe14cede953f150d792..e2b2131f5ee1d99626af01954de04872c5f1da9e 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -11,8 +12,10 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 # CONFIG_MISC_INIT_R is not set +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y @@ -23,7 +26,12 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_ADDR=0xFFF60000 CONFIG_DM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 83f7382e9167736088f599ff1898c3fea1d03fc3..2923ba34ddcd806a58d0b785d865db70bb2cfc69 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -12,8 +13,10 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" CONFIG_BOOTDELAY=10 # CONFIG_MISC_INIT_R is not set +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_MII=y @@ -23,7 +26,12 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_ADDR=0xFFF60000 CONFIG_DM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 901e50090663db9f1411f25360de38c4d9b410db..071169fd298908af268a379350ef64d395654545 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -11,3 +11,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index a0aee660b406d3311b6842fbb4801eb7ff1ffaa8..61d978319751156e28c7d143c7f30fd35946c577 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -6,6 +6,9 @@ CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_SUNXI_NO_PMIC=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 21165f0d44b3f4d68ca4d1f6710bc5d88d29a45b..d3a01275cf51892618c1aea7d772fb039803ff4b 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -10,6 +10,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index ebe24306c8ddbf455fcc538bb7b10c74339f93ed..77cb464c9326ac5cc83f567873917452553a8022 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -10,6 +10,9 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index a6a0e6e406e72e721e76c9e243da8761d56d28a7..f2ee3b1c0cf0817130f165e8b25426dbd28f1cc2 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -11,6 +11,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 89c633c11e0f90369f03c9a7e8cd77205e14f2b5..e8bc14857663150c4ab3b9c62de12188480b5745 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -7,6 +7,9 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index 737978f652ba1a7f623b4cf3ad88cda9740399f2..d69bc7af93b7ac6a50f7ee5980652042ff6a17b3 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -14,6 +14,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index f0ea0fcc8b13ae070ecb3fb562eb2b4f687f4fbe..508cace424c97493fb7fa725bf48128576742e88 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -16,6 +16,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 9625719c0f80bd12dbfd2223b39249354d152cc1..9c09a9e61b54a8dd29bed04ca125417c69aaef24 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y @@ -29,11 +30,13 @@ CONFIG_TPL=y CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -49,7 +52,15 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 34d2dbbb8135769488a274d65c0aac60f0aff798..59c75692728dff1f2cb5d7e96c810ddd397b2338 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y @@ -17,6 +18,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -32,7 +35,14 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index efb696dd32f3e5af59b00c3907442038fb2440d8..e8df2c3df5310d6e81ffa566ada30a047298d471 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -26,9 +27,11 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -44,7 +47,14 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 75ab1f64f903f287fbe865365e2a819df55e7baf..7d2ccc7a22e46067c3058172919ae1ab97024d0d 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -5,13 +5,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y @@ -28,9 +29,11 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -46,7 +49,14 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 827ec0cb6da8c2881b6a481f3656406a05067fa4..9bd62ce6228d8b2724c9ed2155c968da3e47fee0 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y @@ -28,11 +29,13 @@ CONFIG_TPL=y CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -48,7 +51,15 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index baa245a9883e0e984368ceca636ab2eb9664aa2b..abeb43342700583ada1693df6fb57600ddf450c1 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y @@ -16,6 +17,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -31,7 +34,14 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 1c725b99c1b6acc58ce153e9f06f6daecc3e0e92..a29ff2725e9211715bab9d813e97b45b6bad0a1b 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -25,9 +26,11 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -43,7 +46,14 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 0798d3b7b8af8bd2d11c273712db26c7eb171a44..51923777c8b70a919640b01a9f21de4a13a66369 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -5,13 +5,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_FIT=y @@ -27,9 +28,11 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -45,7 +48,14 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index ce16c196bdce0b58a00d3e22ed967a7f6580ae63..5ba090bdaf169c38063b3824025bf745e33b9140 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y @@ -22,6 +23,7 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_NAND_SUPPORT=y @@ -29,11 +31,13 @@ CONFIG_TPL=y CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -49,7 +53,16 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 8f149181030d9c8cbb36fc605374c97ccf9d1abf..44ba09cb3189fa2a3a6e24f12d40f627a2afb2d8 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y @@ -15,8 +16,11 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -32,7 +36,15 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 967d7af0ba10dfe4a923257de8edcb2f6aea942d..a895c61c7c6d68e1551523774da2e3711cd740c5 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -22,13 +23,16 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -44,7 +48,15 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 2d3154e72c6ec584086ccf96eff9426359d5513f..ce175e8e2482c4e74ecf2e81407633a3c49ebab4 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -5,13 +5,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y @@ -24,13 +25,16 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -46,7 +50,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 1d4d0fe9ae73fd77698187494d81f63ab278fb82..e47a277b82aeb4242ec4603162a5217414380f49 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y @@ -21,6 +22,7 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_NAND_SUPPORT=y @@ -28,11 +30,13 @@ CONFIG_TPL=y CONFIG_TPL_DRIVERS_MISC=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -48,7 +52,16 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index a1c6fbf4d4f0593df52331b132e3313fb68cfbb9..46fbed2e3428573a13b370bdfc07a9190f521014 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y @@ -14,8 +15,11 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -31,7 +35,15 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index f1b19f0415edff0d7837e3435b30bf7b03ce5abe..db47f4f8cd003d2ee6dbdabc476e1fef06499c58 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -21,13 +22,16 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -43,7 +47,15 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 261c120607a8ff4637c6c3d32763ced7d3221d47..5c549cc9921d1b09914efd50fd79f4fe07a362f8 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -5,13 +5,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_FIT=y @@ -23,13 +24,16 @@ CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -45,7 +49,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 5a4cc22cb255ff3de111ec09bf1bd989241d135e..0ff1f41b842b981902bf619d63006fdda817c501 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL=y @@ -28,12 +29,14 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_TPL=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -48,7 +51,16 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index c24a57f132808ef4c9bf706cb8d47ef7ee54b7df..9941c14aa35180d6e6e1697a1050a55f22d8dcfa 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -26,10 +27,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -44,7 +47,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 6bf0dd664e5b9cf837d297faf81cb6c332b0818a..6152ef9f3ef1d2296a59186086b3826b7fc233aa 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -5,12 +5,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y @@ -28,10 +29,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -46,7 +49,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 86b36bcd3ba247b4d5947488ddeb64007e258bd0..d7cc4dbc7df57b906fb4b0f83472a9994d1ba8cf 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -19,6 +20,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -33,7 +36,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 8ef9170ef79944816e57dcebaf0328e714128ee8..95d97ed735ef6e7fb6e10889b44eb9bddec6ce99 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL=y @@ -27,12 +28,14 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_TPL=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -47,7 +50,16 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 708db07d61ed28213e1b66cb9ed68b32985a679b..5d668ca660d956b85bd00d4640b4bb49013fd7c4 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -25,10 +26,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -43,7 +46,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 96bce812b6c202ab034769c7a5d65e33db02c2af..bc5f577468a1ed7dc60f80973058abf30881a618 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -5,12 +5,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y @@ -27,10 +28,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -45,7 +48,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 1af1d2cae92d40bd12775867d7b398d23431031c..0778dc696331e745015c722e5a02f19c35e59f0d 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -18,6 +19,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -32,7 +35,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 27402f6e922bbf32d41c6de219f3a334c78ebb43..17a1ab962a9020ad3f3987cc9c40e715539aeb7c 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL=y @@ -27,12 +28,14 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_TPL=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -50,7 +53,16 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 51ceb84f23a9971f15f172e98dec47ebbcb95fd9..4f4e5f52686e0b4eb97475e74a1aa5cd4ad27fa5 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -25,10 +26,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -46,7 +49,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index f95daa1be48c46162df75791fa2f0f99d5756be2..205ca03b493b46b5ddc080f2bff9a8d45e7f0e8e 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -5,12 +5,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y @@ -27,10 +28,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -48,7 +51,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index bcc00dc84d66715dec53b92680743791aadd7f9d..c7ba60ce321f8b52933ae4db19893176b8032d74 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -18,6 +19,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -35,7 +38,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 85fe2f33db7f510f8f91fe602a347bb3afdfea60..d34a129b52c6d726a1a6e132a3dcea14f07b92b3 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL=y @@ -28,12 +29,14 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_TPL=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -52,7 +55,16 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 61ac850c7300151f687ecb1b2434ea3982380633..282ed313f80c8b187bbf545fddfc751b41d7a2c9 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -26,10 +27,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -48,7 +51,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index b011006a433f04e9869fbae4398e35e8d03ba65b..fe2bf1af570a8cb1ffc39c2c683a4bcb3b4072e6 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -5,12 +5,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y @@ -28,10 +29,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -50,7 +53,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 3f9c9f3357aa412d5b0223d6c4b8417828b46496..92521518ea27d92a9423bbebf8bdf6a81db6a086 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -19,6 +20,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -37,7 +40,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 7d81ce63261fb566ae7f57ea8ad9edfe933e7270..3b57b0c1a640b7866319e23d1dc173854e39fa73 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -2,9 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11001000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL=y @@ -27,12 +28,14 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_TPL=y CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_TPL_MPC8XXX_INIT_DDR=y CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -51,7 +54,16 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_TPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index fd98748b4a0b3c52da3136880efcce8b22b0a8fa..32e509d78be3b060239d0709a0633e2ae018d241 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -4,10 +4,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -25,10 +26,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -47,7 +50,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 0bc6cb5b6454573ed824020a7b4fde1960d2cf31..bfee816e3a160cffa39fbdb606a7176151cea742 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -5,12 +5,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y @@ -27,10 +28,12 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -49,7 +52,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index cd9d8dad8719444064da23a2739148fee031fb2f..dbd2d873582063251b53b5df5183c8c7d3f35fdf 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set @@ -18,6 +19,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -36,7 +39,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 40d4c78a69b3a1187d13d9c639f296dba46e3ae0..d979b14c9c180d8fc30a06cc718e4351bc0d4f68 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y @@ -10,13 +11,17 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -34,6 +39,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 55766d1efe7e9163c6e0bf712a2e1b0de0221186..67c4f40f2b80d2a58837e003f7017f76c22f2719 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y @@ -10,13 +11,18 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -34,6 +40,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 1e0711e9c3532e579bffe43513ff5c5ca5d87a74..6e0b99adadff9ac152f5c308fb6988c9bffe6663 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y @@ -11,13 +12,18 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -35,6 +41,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 224ae422d1e071749225284fee82fb5a88dccc3d..49e485defd7aee8bd197c44d2ff7cdb7db364741 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y @@ -13,9 +14,11 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -33,6 +36,9 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 20ab931d3e6d7b5d942d1db3b232e7111dd0e663..7d6164de33d3740f786274c9f166fb6466162770 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y @@ -10,10 +11,13 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -32,7 +36,12 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 87ed18dc518628c529a8e19ff5f57090acc4bcb8..43d0d312595a5c210a4efdfb8ac2ee05a7e5dec4 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y @@ -10,10 +11,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -32,7 +37,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 48ca8b731d53c0c2419b08434e6f71af25907a12..f905a5aa6c1e49b5506072428d6dbf052f62a9e3 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y @@ -11,10 +12,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -33,7 +38,12 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 4369f404a55145a945bdaaddf8b6d22967ba216a..7406b1e4ff2aed88d36f6ff0b5b71a84a5eb0bff 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y @@ -13,6 +14,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -31,7 +33,12 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 97ef317b07f933a5b7f900efb956efcab1fc1231..ed46a1bcd55e64385e6b187f0c0be196e1d15e94 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y @@ -10,10 +11,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -32,7 +37,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 6447124c6e03683b33834e53eaa85e8e017ef747..ae46fd418d59a3f3f08e3c42ed98e6182154a09e 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y @@ -11,10 +12,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -33,7 +38,12 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index f6c43bcd290879bd6de8e7a114b55d1add371084..d9094b975f3807f684783b835bc579441ea2be40 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y @@ -13,6 +14,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -31,7 +33,12 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 1a55f498b9406033613e00b24828dfdd58958c56..9707f0c80be0ea3082f748106eef3ab50275b097 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y @@ -10,10 +11,13 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -33,7 +37,12 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 85c8da1537607b33309ee1d886c18d720b234ec7..a1b4cf3f7f4e06820fbcc1b6d8dc8d3d664d0061 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y @@ -10,10 +11,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -32,7 +37,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 48020df78cfbd250d497cc9a671c42bf1c2784b9..27b009cf404aa72c5608282f1f32b4f809ba037d 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y @@ -11,10 +12,14 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -33,7 +38,12 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 2be7c7769e464d2251a7204ca3355cd898827657..89924b4983077dfd36725b108095bf446720feb5 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y @@ -13,6 +14,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -31,7 +33,12 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 238a1c49e1cbf96cf661915d5c8e8f3e78d253e0..b0903d63a6412962970f18f1a577752ab20c714d 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw" CONFIG_IDENT_STRING="\nSBx81LIFKW" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 77a8fc6683d4842bed6931b2b12661c1622e12e7..c6629bc37758995419dbcb8e1df713a53b298704 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat" CONFIG_IDENT_STRING="\nSBx81LIFXCAT" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 0a3cc7b4cc3a593abb55f45c4b701b7be4d973d7..dd12941f837eee2b14ef06956a81cce332190107 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -6,9 +6,10 @@ CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -19,22 +20,28 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -55,7 +62,16 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 814cde6e4e3384221810d3589531c0caa122e48f..82848a7ebbb1753d3e8009abeb7612c37d5a0aec 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -6,10 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -18,21 +19,28 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -53,7 +61,16 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 825d9102c39bdaa6a7d6ecfdb1f25cc0af5db409..a9424fad1fd3f5d01f2f9fe59928ad14693cd3b2 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -7,34 +7,42 @@ CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -55,7 +63,16 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 3533b78ba2316b8c8c2c112c42004fcc65465d2a..8b07e21fbc628b73ee0354fcbb8c15ff93d2498d 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y @@ -17,9 +18,13 @@ CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -41,7 +46,16 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index c15c5a2694bab1de07ecd8876bf42dd1a66e8a81..e92c98c61f02cda9c66aec7c680704e78f56b07b 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x180000 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -17,7 +17,9 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -28,7 +30,7 @@ CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y @@ -50,7 +52,20 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 2bd35288813bf4f87ae0c92d5c4b385c02be4561..6d9f777658a4217cc6cb8eaed35dbbe5ee4f5e4f 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -6,8 +6,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -16,7 +16,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -27,7 +30,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -48,7 +51,20 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index d56e5a800b1e9d81bbd92b57532d72041ff19e85..b818e6315746fbf48bd9cd207ed8b9ca3e702599 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -7,18 +7,21 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -29,7 +32,7 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -50,7 +53,20 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index cf6c264f8f90daeb1d810e66ad1e48805a51c964..2fdf4703eb52b176a265aa06f2004c14df0bea9c 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -36,7 +36,20 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 06d4f66385ab2b7b4b74ade7e8e373970cd5d11f..0e37eb748f8988690c2f17585fc1b3d52c8573b4 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x140000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -18,7 +18,9 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -26,7 +28,7 @@ CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y @@ -48,7 +50,20 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 45a3bbb71849d4bcb404196a6213603a1c56cd28..0046c7120a89588d732ac1711d63ab7e5095e24f 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -7,8 +7,8 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -17,7 +17,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -25,7 +28,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -46,7 +49,20 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 739fbf8d70d81c5dc9ebb6a37e357a906bcb9aa8..dc3e98544a98c2da28ae26e1537c107c7ac4241d 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -33,7 +33,20 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 921760c3807bab6c9b0d38b308d0b41d89678c84..9c1912e0d9b6512c2fc0a85612be3ce743b66b24 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -8,18 +8,21 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -27,7 +30,7 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -48,7 +51,20 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index c7bc3ecf7a3d049855249f7fdb506f5d95de0fc3..344e2cb240b558aa069d85a4fd674cfef295f6ef 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -31,7 +31,20 @@ CONFIG_ENV_IS_IN_REMOTE=y CONFIG_ENV_ADDR=0xFFE20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index f92a4573bf10d720a80a5d3f0cc49cd837e538dd..1679ef1481fae40ce4642716559cea9ef11f578a 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -34,7 +34,20 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 93d8d4ba56e488d4a6367ba40c9554e2587cd186..4b0b78a0f25445d9089b62bcdce8740cc5170b6a 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -19,7 +19,9 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -27,10 +29,11 @@ CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -52,7 +55,21 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 10598804a1fe9caa5cd93a56cd192895c5eb6855..68989d722d4c7d709edd46d978b7c0e510be1dd2 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -8,8 +8,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -18,7 +18,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -26,9 +29,10 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -50,7 +54,21 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 59963fdf3741ce3a73999012bf8c182c48b3767d..6a9752ab416f7c9bb575439f25061b0ca77046e3 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -9,18 +9,21 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -28,9 +31,10 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -52,7 +56,21 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 466e91743f50f78fb8b1949affbc64261008c6e1..db0c09b8768369e6e34b21f026128a41903c00eb 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -38,7 +39,21 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index f6eeade2a39dce1442fee006779f90870f3094fe..7255b525a8c3273aea35c166815ebdb78c69e5b4 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -20,7 +20,9 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -28,10 +30,11 @@ CONFIG_SPL_NAND_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -53,7 +56,21 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 0286610cb03bedd05960d52b75e3fbbdb82fd1a1..f7f37e861ba0afb9fc83a76fae2fdde09de6691f 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -8,8 +8,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -19,7 +19,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -27,9 +30,10 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -51,7 +55,21 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index eb073ce4be5f0da6b61035a3638e1173c397ae93..f91e7a8b44946904423fefb823b2a5ffbfd75cf4 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -9,11 +9,11 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_T2080RDB_REV_D=y @@ -21,7 +21,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -29,9 +32,10 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -53,7 +57,21 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index ab7096e520255418b66cb35496b511f3979284da..d20b57673ece9d52ff2a4e19fb6de5b6531047c2 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y @@ -39,7 +40,21 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133330000 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 +CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y +CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 +CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y +CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index c1ca2565e2697da27d2a01bd9d629d5ab8247d1a..6d6673673fdcc8723f441c246eb87133e7871fbd 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -6,8 +6,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y @@ -16,7 +16,10 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_FRAMEWORK is not set @@ -24,7 +27,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_FSL_PBL=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y @@ -43,7 +46,16 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 14594b0579108609004352e077e67bfec452dfca..a3ae720f907e60a70b5b5fcbb11d201665be399c 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -31,7 +31,16 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x118000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 78c40c067a0a35a92675c12a30a30aabc090c135..b5728073086313f86f40b3362e3aa154cb4a835d 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -21,6 +21,12 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SPEED=50000 +CONFIG_SYS_I2C_SOFT_SLAVE=0x00 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index ee7d4867844b1ff68fe537844c5c5af7da294560..101ce57aa44dcbe4efcdcae55f3ab395a76c5a74 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -14,6 +14,9 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 4c4d3be255d96c0667f3ef88b7c6d48527250070..83b82133b96bc8b69fb83a4835dc41a50dba84d5 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -14,6 +14,9 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 6fdb1524d1b68388e975ede56bf8c457bda0815c..e0687bf887dbd444c63e7eaf0711a37b5439e05e 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -8,6 +8,9 @@ CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 4f89d716cd566f78d31cc1bae72d99a5cfb2cd9b..1b88cfabf0447b57472288b7040136808d2f15e3 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -20,4 +20,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index 83faf8098aac3faad859e81db84400fdf991d9ff..cf2535ed6f8ee2c1c377874681a3b085ba0f4911 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -1,11 +1,14 @@ CONFIG_NDS32=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x4A000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae3xx" CONFIG_TARGET_ADP_AE3XX=y +CONFIG_SYS_LOAD_ADDR=0x300000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 # CONFIG_AUTO_COMPLETE is not set diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 3e898e5787ba38e11ae9c0c72657b6448f6a5d95..c1cdb11a7c46c007236352606f267a6f0b7cb270 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -1,10 +1,13 @@ CONFIG_NDS32=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ag101p" CONFIG_TARGET_ADP_AG101P=y +CONFIG_SYS_LOAD_ADDR=0x300000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 # CONFIG_AUTO_COMPLETE is not set diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 4e7a1686a64d59d6a5fc2f5e429acb3c265175b8..dab35f9bd613dbb999d35e2b3d69234a649c8099 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -2,9 +2,11 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_TARGET_AX25_AE350=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 34c6af6e7e170bfaa7d736ed556da8d4d3e8640e..11063e9e1b7bfe1e25f2a6bf8d63af6a87dc8025 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -2,12 +2,14 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x01200000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_TARGET_AX25_AE350=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_BOOTDELAY=3 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 4a8da32955942faf1754de596ee8b4657935ade1..2a6423f0c5717a728ac3415f614d18d55a3a5881 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x01200000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 @@ -10,6 +11,7 @@ CONFIG_TARGET_AX25_AE350=y CONFIG_RISCV_SMODE=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_BOOTDELAY=3 diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index f66adc3f8a55e60c697ad2b0aad359a4ba6a9966..d1d544ec27f85834a2677ea95753de2f9b9dff1e 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -2,10 +2,12 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_TARGET_AX25_AE350=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 05eee371ac2f747dad5d83925a2cc365ab38d276..d2d0e31827cdee5b5bb3cadf25782abe0c40fe87 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -2,10 +2,12 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 9cd7848c92ebbb98d2396a8aa2a96c99eab4f5da..90511ae0bf5b096c08c76bf36e6e6ffcbe986bcb 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x01200000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y @@ -9,6 +10,7 @@ CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_BOOTDELAY=3 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 188fa08dfbd56767b627197e2f003017bb6dcc7a..55cfd11c0eead32c151f847585d2492b35b2c9e1 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x01200000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 @@ -11,6 +12,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_BOOTDELAY=3 diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index cb2b0f14dc00f2b3ed5ca6054a29ea84c36c8c06..568ada1f232152493cd8fe4898f3e1cd9ed15e61 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -2,11 +2,13 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index bbc20eefa6bbfb1303d55871839d2cc5d4de7a9f..966e2a185fcb54e4ea77bd510a4cc492683f9854 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Alt" CONFIG_R8A7794=y CONFIG_TARGET_ALT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 21550925a7533d42c765cf7d80357c06fa79b124..3b67e019376861e8c03f759981c4ed1eb27f44a6 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -6,8 +6,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_BALTOS=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -28,6 +28,7 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -50,7 +51,10 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_OMAP24_I2C_SPEED=1000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SPEED=1000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP_HS_ADMA=y CONFIG_MTD=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index d7c1a76b039211d648f413b33f888a7961c41f47..f0b197a0501b60da908c67ed7d783cc7824a3bf6 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -21,12 +21,13 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MUSB_NEW=y # CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y CONFIG_CMD_SPL=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y @@ -47,6 +48,7 @@ CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index ef8de5999e0d58c44b0dbcc6d1cf7118c475daaa..7fd90ce9fe5666ef2a4cc8d519ffdc3d77b08edc 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -21,13 +21,14 @@ CONFIG_SPL_MUSB_NEW=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00080000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -57,6 +58,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 4fea5cee62d3c8010a69714ef4dc3d71835be565..94ea4ecab6448cc17b9e142998971dbe86bb4ae5 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -6,10 +6,10 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_AM33XX=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -25,6 +25,7 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_SPL=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -55,6 +56,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_SPL_DM_MMC is not set # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MMC_OMAP_HS=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index fd495f2b9be2b69bc97f45a70aba6e323e35ed05..fe8ddf61e64e2e13261950e2b2de450796279516 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_GUARDIAN=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y @@ -35,7 +35,7 @@ CONFIG_SPL_MUSB_NEW=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL" CONFIG_SPL_POWER=y CONFIG_SPL_USB_GADGET=y @@ -64,6 +64,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y @@ -78,6 +79,8 @@ CONFIG_CLK_TI_CTRL=y CONFIG_CLK_TI_DIVIDER=y CONFIG_CLK_TI_GATE=y CONFIG_CLK_TI_MUX=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index bc19d070529d40976a0b5fd36285024fdd08afbb..9f96b78fffa00be1a9a98c900842cae7e4f8da03 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y # CONFIG_SPL_YMODEM_SUPPORT is not set +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -50,6 +51,7 @@ CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index a1e19b6ce909c5402573f5c2cedc889df106ca3a..a1ee1412bfee38207795a445508c974164e80427 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -6,7 +6,7 @@ CONFIG_ISW_ENTRY_ADDR=0x40301950 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_AM33XX=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set @@ -28,6 +28,7 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -52,6 +53,7 @@ CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 0ec6851f32862e9e16cff0a758744631f7161a33..af94cc090cfb36db554e99417349538ed106df11 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -9,14 +9,13 @@ CONFIG_ENV_SIZE=0x18000 CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_IGEP003X=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_FS_EXT4=y @@ -68,6 +67,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index 00338797626dbff8bea93f561196604727024e20..ffadc909fc6b23054126c793c3404e06f62c051d 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -8,8 +8,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" CONFIG_AM33XX=y CONFIG_TARGET_PDU001=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 0c4186daa4d711ff2647ecd7ebed5de6848381e6..4169d13d2a82fe484a165487fecc12f872b439ac 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -9,8 +9,8 @@ CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x9000 CONFIG_SPL_FS_FAT=y @@ -51,6 +51,10 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SLAVE=0x1 +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 354586b70b6cd05519663f2a7c84d835d4f4b254..1d25adf7cde5197da25c46d63801ac5712543e35 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -9,8 +9,8 @@ CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x9000 CONFIG_SPL_FS_FAT=y @@ -52,6 +52,10 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SLAVE=0x1 +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 43fef20380d65b09d782c7d8fa83011ef9bb6c83..0ab3acb77e18601bc4d86701a311fd0ba6dfd023 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -9,8 +9,8 @@ CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x9000 CONFIG_SPL_FS_FAT=y @@ -52,6 +52,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SLAVE=0x1 +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 4010d83fec790635c3516f52c3348ef30811cb6d..914f21cb7cbf8b6f6ca15ddb558b3f8ee9e618ac 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -9,8 +9,8 @@ CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x9000 CONFIG_SPL_FS_FAT=y @@ -51,6 +51,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SLAVE=0x1 +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 1f3b680bd630693ccc2a1bea9bcbbd50c56e46be..aa1e196d4081c4c398ea7dca4937f54b9b575eb2 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -8,8 +8,8 @@ CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_SL50=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x20000 CONFIG_SPL_FS_FAT=y @@ -29,7 +29,7 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER=y @@ -38,6 +38,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -57,6 +58,9 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 1234aa2251e402998e14e9c1d9b8150fcdad1bb4..864d16cf01ce13fb4e86ab3ee3abc72b755a56b8 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -77,6 +77,8 @@ CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=57 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_AM35X=y CONFIG_BCH=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 5d35176890122bf3d3ec7d2ddf0f7982d1c25115..b60090d4c3c19395a91b815ac1b8ea7dc4219534 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y @@ -20,7 +21,7 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_USB_HOST=y @@ -29,6 +30,7 @@ CONFIG_SPL_USB_ETHER=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -54,6 +56,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -75,11 +78,11 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index f42218bb46b84f1a9127130fdf8398294eee19bc..31b564b7ba9f32bb24069d4d326d4d82dfe251aa 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -11,7 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm" CONFIG_AM43XX=y CONFIG_ENV_OFFSET_REDUND=0x120000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI,QSPI_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="QSPI" CONFIG_QSPI_BOOT=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -43,21 +43,24 @@ CONFIG_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_SPL_POWER_I2C=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 955ea087acb30bfcb66ce432d522aea000fe7bed..a4450cc0d90bf9c1d7fe25e4ba9ce1c6cc259b47 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y @@ -23,6 +24,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -41,6 +43,7 @@ CONFIG_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -57,10 +60,10 @@ CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 98b07b9a19274bb459edce58e7a87d1031f23a9d..9efeccc1e5537a002334711858103661c70dc131 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_ISW_ENTRY_ADDR=0x40300350 @@ -22,7 +23,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_ETHER=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 @@ -79,11 +79,11 @@ CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 43f47385ade2b06de8762acf76bc9cf31769b14e..f34013053fea2d0c6eaeaa1aa275363f3fa16c27 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y @@ -29,11 +30,12 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -59,6 +61,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -80,11 +83,11 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index cc11323b9d51a58bd3424243e12847ab960ed765..9a038a6bc69332454b005262d22d9944051b0833 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -12,7 +12,7 @@ CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -39,6 +39,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_CMD_SPL=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -78,6 +79,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -106,6 +108,7 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 5763264adb1a9ee00aa7846f573ff50efe5179ab..0a99df487e1506b75ec0b7508829090f4a62ee34 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -15,7 +15,7 @@ CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -41,6 +41,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -74,6 +75,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -102,6 +104,7 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index f2ae04583739930dd389c0b5f5d39ec300f988a0..dbbe18d51b8d899e37dd173c96444ade5728b4fe 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -17,7 +17,7 @@ CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -48,6 +48,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -81,6 +82,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -110,6 +112,7 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index fa58a3137fb7abae7ddb1d89f7b0eca2e2ede484..859306d1fa67a70430c230b66731b1a47332de97 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -9,17 +10,18 @@ CONFIG_K3_ATF_LOAD_ADDR=0x701c0000 CONFIG_TARGET_AM642_A53_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 5d8d4c5fa9ac3e29ad81c7feadac7f7b8803177b..1659760674b7cd6249905117d97ef31cb2a9552c 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -8,12 +8,13 @@ CONFIG_SOC_K3_AM642=y CONFIG_TARGET_AM642_R5_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm" CONFIG_SPL_TEXT_BASE=0x70000000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SIZE_LIMIT=0x190000 @@ -21,7 +22,7 @@ CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set @@ -40,7 +41,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 5773d21ff3afb6b3a1a742733ff9397d2693990b..f13a1be3c9a167fe243789fdf870a9103e14916f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -8,19 +9,20 @@ CONFIG_SOC_K3_AM6=y CONFIG_TARGET_AM654_A53_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x6A0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index e4f0d25be59f83c446c9da2612455b0c930d58be..cccd7104c58ccc5ef143248abf7a41a6ab77a691 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -9,12 +9,13 @@ CONFIG_SOC_K3_AM6=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_AM654_R5_EVM=y CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 @@ -22,7 +23,7 @@ CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -41,7 +42,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index be68a4f7f17275e173412b76dbbcd53ac76c7cc3..c8ee3a508621e1c7ce60e08cd869b7f1e870de80 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -9,10 +9,11 @@ CONFIG_SOC_K3_AM6=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_AM654_R5_EVM=y CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y @@ -30,7 +31,6 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index b8bee2fff771ca61428fc12688c5f55b28df63ed..f5e1b085df6bb5de17a2c38b38453f1522ffc795 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -9,10 +9,11 @@ CONFIG_SOC_K3_AM6=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_AM654_R5_EVM=y CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y @@ -29,7 +30,6 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 557517bad684eb1879648def472362a53515ef49..cef00dd02d0b8fbb823809211c794c19bf6cdef8 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -9,19 +10,20 @@ CONFIG_SOC_K3_AM6=y CONFIG_TARGET_AM654_A53_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x6A0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig index 9924a37bb956c57682b6fa5938ec8e311b477c2e..7df36fba8fdaf8b417cef10d5e9e5e7bbd4e2537 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am65x_hs_evm_r5_defconfig @@ -10,18 +10,19 @@ CONFIG_SOC_K3_AM6=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_AM654_R5_EVM=y CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y @@ -38,7 +39,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index a17cc21cb49d4b74379e01502a8c066945eaf35e..4befa7a62bdd40028485cb2e2c41896d83963bc1 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -3,8 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xFFC00000 CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="amcore" CONFIG_TARGET_AMCORE=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_BOOTDELAY=1 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index 6f0cf6f0637ab8fdd9d7e812ddc638c4620d90cc..9549bc385289e6f5742d0d6b2f970967e35b1f81 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -6,12 +6,14 @@ CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="ap121" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xb8020000 CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_ARCH_ATH79=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 1aae19c3bf22ed2680603c8ad2d323cc5f674792..7384b521e3d3fbdf487be40c8c9c0ff94c8cd874 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="ap143" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xb8020000 @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP143=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig index 0f7a81730d3bd26a0316666f5c0d98e6bb12af42..71809b2e8477e55620dd106dbbd3fa12f7b79ebc 100644 --- a/configs/ap152_defconfig +++ b/configs/ap152_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="ap152" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xb8020000 @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP152=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 59179e2bd3a0ae194f1b2dd870bcb1d946d0f3ea..2c5d6925a03ec0270fe8a05d812ea63a267ce155 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -7,13 +7,14 @@ CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" CONFIG_TARGET_APALIS_IMX8=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8-imximage.cfg" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y @@ -34,6 +35,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig index ed9686e0d8708226f47eb024221ac1d0105604e6..4ad6f7fd07a20f2aa642a7c9864c5aed646d2e80 100644 --- a/configs/apalis-imx8x_defconfig +++ b/configs/apalis-imx8x_defconfig @@ -7,13 +7,14 @@ CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" CONFIG_TARGET_APALIS_IMX8X=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x89000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" CONFIG_BOOTDELAY=1 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -36,6 +37,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 39e1c1dff17b89a253dac71cf1149da8e833e407..659e58f0933ca570767a7780dbe5164a713cd8fc 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_APALIS_TK1=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=1 diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index a0e85ba23a48d37c941f53a76e033157c1507fd1..52f2539f111acfd0303796e9129d65d13a0301bb 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -11,17 +11,20 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6Q=y CONFIG_TARGET_APALIS_IMX6=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -70,6 +73,9 @@ CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_MXC_I2C3_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 1420ca219f37471a2f8878b3adec786dab8d3f05..59e5113e37aefb7eb396f92e18a13ccf0ae1275a 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA30=y CONFIG_TARGET_APALIS_T30=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 67fc4e3e23cc5267c9c15514f670fd60f917cd74..0a4c48fb5dd5779830f43ba0e4d50e9b5dd1d8ec 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -13,7 +13,6 @@ CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=-2 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_ENCRYPTION=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index c156a6ade808c86acf61fcd7b5297c1e275d7c77..342e4e9a458de48aa327dba1cdfba373f154bc4b 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -13,7 +13,6 @@ CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=-2 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_ENCRYPTION=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index e06ef7d272f670a88ad951b6f70616e6da4a51db..39e408ef69df6ba56a68c0dd7220932798045a81 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -7,9 +7,11 @@ CONFIG_SYS_TEXT_BASE=0xE80C0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board" CONFIG_R8A7740=y CONFIG_TARGET_ARMADILLO_800EVA=y +CONFIG_SYS_LOAD_ADDR=0x44000000 CONFIG_BOOTDELAY=3 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 133c0eb8884ebda0cdf5f0d6566df685f83ed99d..ab93240db4f2ad7e25bcc38dbe504ded3ee3f261 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 @@ -7,11 +9,13 @@ CONFIG_TARGET_ARNDALE=y CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x86200 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale" CONFIG_SPL_TEXT_BASE=0x02023400 CONFIG_SPL=y CONFIG_IDENT_STRING=" for ARNDALE" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_USE_PREBOOT=y @@ -31,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig deleted file mode 100644 index 37e6871dddfb6179872a1a3b73a18ea72eed34be..0000000000000000000000000000000000000000 --- a/configs/aspenite_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_TARGET_ASPENITE=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_IDENT_STRING="\nMarvell-Aspenite DB" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -# CONFIG_MMC is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 9d20cb93e05e811172f985da28557258f3e38c80..45796df36308db23acc59d07ebbfc5a504c1f4af 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_SECT_SIZE=0x8000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l" CONFIG_TARGET_ASTRO_MCF5373L=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion" @@ -25,6 +27,11 @@ CONFIG_FPGA_ALTERA=y CONFIG_FPGA_CYCLON2=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN3=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x58000 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 76ad67bf9ee42378c00fadb939552300408fa866..d80ac2d486a0c1fdfab8300637d712b5532d7935 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 07d3911d900d63518a7a472a3889331356c11805..f9ddc15cbdff0375a3286a246b10f750fc8a7f39 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 24a40f2137d3000f72929db1fdb93c550917a1db..c44a425ce0ae7e1e1032898bca3e95e1f303102f 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 79e3e02e9f86c4d191519c297856f849909249aa..14204c06aea2dfb7e48ecc67b9d5d706c07a9b6c 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9261EK=y @@ -7,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 29e08af51d8c6257ad897a30d9eb85f2a3f0c37f..523f581674bc6e83a7e31cd741e99a17254073bd 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9261EK=y @@ -7,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index e5d54e463fd7806040b35166c0344bb37355588d..7033fc470cf69b0035372161f38612462a1ae186 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -11,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 64e2ea8eeda092a36f422508c2edd8c39b0a759c..c051645d1161b4c17dce22073a67e3e57a49e9bf 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 64e2ea8eeda092a36f422508c2edd8c39b0a759c..c051645d1161b4c17dce22073a67e3e57a49e9bf 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 73aef06a7cf3999bff2a0dd6123fbf513e850478..4cb1f6234bba4830ebb87bc952a2550ed4a561a1 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 8b5377dc1bd64c3761c654d7393e849832e7fb7d..887714e3d0c0b0e6b1fc29bbd2fd93f7861c6b91 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -7,12 +7,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x50000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index ee4edec2daad975bd810fa45b3a36076aec51818..d90e6219de19492e128f2a3353ec7e7e9daae170 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -7,12 +8,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x50000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index a9acd1d46ef28453ed58561bb293fd73e3ceaaf9..7c26200d4bd615b2434f92ab75ddb1a40787e42a 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9261EK=y @@ -7,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 4c92ee4593cbc797b8c4e0a5299b66e14f5a4bd0..211927be5806f5f610e35986e9c408ffe175f50f 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9261EK=y @@ -7,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 414e41b48fbcfe9d923784a0dffa2f883000167a..f62bdf805f7394aeacbb8cbe070bdf2622141733 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -11,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index d3d95c726cbada6d4dba86b4cc7202fd21aefba8..59588bf25568fba1807c676cfb9cac6f59cc2f81 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -7,12 +8,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x2000 +CONFIG_SYS_MALLOC_LEN=0x23000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 4e9f8e2dbc9e09b29aaac3eae2360acf0cfdbb36..1f533f6bb5f2e937ef202bf2013926bc3d49de93 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index e0478ef1a93f44535f60b5569ca1d67f09926090..5a717ef8cf12fd8698180f29fecde100aa17dcbc 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 2bc57c8af732589aadb7068d8ddd6d544e61ee02..665a2949b912a7eed9bd6f68938005860faacd67 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 14b32a9e6e865210640c9b9d37f8b08e621b4e01..3c4e8475fed3dbf9e2f7ac15cb4741852b4f19bf 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 07683608d0486b20d049e917faa417a146c94938..8ad87c818b1b91091d3243fd4facf72c88c7d1fe 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -1,16 +1,19 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x73f00000 CONFIG_TARGET_AT91SAM9M10G45EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x2c000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 568743d5e2e5515f1d74f98861038cca750d8cb4..49da6f3ab479cdf5fc23d80a7b52fe5f2c492a7d 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x73f00000 CONFIG_TARGET_AT91SAM9M10G45EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -11,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 2e0e596962834e67a41ac33a5e6c69bbcb551720..28815b5d441de2d6d1883133cd533e59353ea82e 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9N12EK=y @@ -11,6 +12,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 483e5e9618c8dcb89b60c98047642bf6d32fed28..ab51b702789acf6b04cdc0e51a842edde6581056 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9N12EK=y @@ -11,6 +12,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 0bed29bb431f0917f9b70b586faccdb3864dcbe1..0eb24031827af3593d8a67ba1be1b1712154db9b 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9N12EK=y @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 47eee7d8a0b1164c98ad874f713c43c333d76e64..444e43eb4d58e3643371cebdc2dd16ce7c1fae5c 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index 781d91e2ca353a296098c96544bd6853a188349d..6f5c6f3166b64cb2f86270e6ccb4d3f73a36683a 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -6,12 +7,14 @@ CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x2c000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index 1fa557ff83fb4b3cbff81a1854516756cf9c063b..623e21ba71b6cc166bfd2434081bd553a239e4d2 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index a8e1a36b50723ff7ffadef8526a3153cb49a1935..dfbac625d29b0b1a6fb7346fdae3afb1d18ae171 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9X5EK=y @@ -7,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 3bd0897cfed5081c786b72f34ee68350d21d401a..8064f362982c9861d91214f38693cf997b864f30 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -1,16 +1,19 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 90c8f796f9e11d2c3fed264dd1a1eb3ca7f9b2fc..4ff4f1080f0423254cd0da87a44c30df38badf2a 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -11,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 71bbd743df65baa35e89fb7ca222be624abbbaab..2a60f74e3409cf0fbccaca94e88cf2f21b4a5062 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_AT91SAM9X5EK=y @@ -7,12 +8,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0x5000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 2573c3c3407526c50bb7f89796859a3cdc400974..0ca1b6cf4a4c0acc2c6f88d881153d609fcd90b1 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index f2baad78e6c16fceaf671e03e8b493a11f190c70..1b7b4a7fca2aa82a17d18ccc388eb2b10c153b50 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -8,12 +9,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index a1026a78fd5fd4c7cc7c2e7937ecb94a0b1d4d02..e7f13a0694483d636267ba038db810747f4e62be 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index dbbe2d5d66c78cf8a71b236334028963c97c91c1..6a492665ddfdf15de3e9e15a1f35d157249459f7 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -4,17 +4,19 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_SYS_MALLOC_LEN=0x4008000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ZYNQ_MAC_IN_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index aa9197f2c0a8dcd2ff464669192a3911d0ae435b..a013338477862a50e6ead051f5af154129954bab 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y @@ -14,6 +16,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 @@ -22,9 +25,10 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068" +CONFIG_SYS_LOAD_ADDR=0x22000000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flash_self" diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 7af881e45bca3596a0dff2bee082b1d5fff1aee3..5dd323dc45646c341521fa5447f6ffedfbc490fc 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,12 +1,14 @@ CONFIG_ARC=y CONFIG_TARGET_AXS101=y CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="axs101" CONFIG_DEBUG_UART_BASE=0xe0022000 CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=750000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 7394272ee3f447d9656b7bcd8394e382dd381f3d..698dbdafe4d1c7d693c5f4cb784a720a373a6eb3 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -1,12 +1,14 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="axs103" CONFIG_DEBUG_UART_BASE=0xe0022000 CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 83115560b2ccbfb1d0e4172e3c9c0416ad70fc88..b89dd8ea62b4608cdc35d268223665858b0b4731 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -10,6 +10,9 @@ CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 4d95373790dc7b8d70c1cc4a1b7010b1648e6011..2f0c22f62fa8c807d9be406b082a349c73df1838 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -12,6 +12,9 @@ CONFIG_AHCI=y CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 16dd7fdfd0d74f19d7812780edf6f6abb837466a..8b7f37675a17942699c9f2e7c53f3f4dac5fb394 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -10,6 +10,10 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_RGMII=y CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO4_VOLT=2500 diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index a42a6acb06d572a7c4830f1c38b4d1907a295395..ec58dd25369318b1bfcbf5e57b2485a4a5c17d56 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -1,11 +1,14 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_BCMSTB=y CONFIG_SYS_TEXT_BASE=0x10100000 CONFIG_TARGET_BCM7260=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x814800 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_ENV_OFFSET_REDUND=0x824800 +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTDELAY=1 diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 96e8da0748aeff454bf921467f6469c0be43a463..d5dd4b70102e5a74746f4b82287a42b40a1bca71 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_BCMSTB=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TARGET_BCM7445=y @@ -6,7 +7,9 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1E0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_ENV_OFFSET_REDUND=0x1F0000 +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTDELAY=1 diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index f7f1b353892342aaff426ecfeef70626dac58db4..5b6af9e215af1259f8f4efa7489015070c91d19d 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -1,14 +1,17 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y # CONFIG_ARM64_SUPPORT_AARCH32 is not set CONFIG_ARCH_BCM63158=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="bcm963158" CONFIG_TARGET_BCM963158=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_RSASSA_PSS=y diff --git a/configs/bcm968360bg_ram_defconfig b/configs/bcm968360bg_ram_defconfig index 2d759fa648589223f93382c5baf16eeb22650ba2..bdc2e1ead79eab7a37f33e21b31ddecb8a7b41a9 100644 --- a/configs/bcm968360bg_ram_defconfig +++ b/configs/bcm968360bg_ram_defconfig @@ -1,13 +1,16 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_BCM68360=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg" CONFIG_TARGET_BCM968360BG=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 4415faa9fe501eeed99a9c22a157bd0b3162bec5..855f1c24366a02123907e8d9251bc6752412ecb7 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6838=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index 09d09eede6e04722743849e0dd8d2ebf49ca6f33..c5ab9761cef094cd0108dc40612a4a3c33b8af0a 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -1,13 +1,16 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_BCM6858=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" CONFIG_TARGET_BCM968580XREF=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index f158b82941678b6ce3dd5be6d4d2919120d46009..3fa24351c7411c3060d8ff2af33862dc555e9dc5 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -4,7 +4,9 @@ CONFIG_TARGET_BCMNS3=y CONFIG_SYS_TEXT_BASE=0xFF000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x80000 +CONFIG_SYS_MALLOC_LEN=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="ns3-board" +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_SIGNATURE_MAX_SIZE=0x20000000 diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 76ad5efb6aa8f095ab2703100b5e75161dbc7e90..ec452690752a87de462f24eb3ae65cb8f9984127 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA30=y CONFIG_TARGET_BEAVER=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index ebd887978307439ab4105b741de57bbf8e30a632..7735c70e3f42880835ada7b6450f39e68bc4d5c7 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" beelink" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig index df2580287d4343c97f4d46e2ac5cc31d9bf974f4..93c5739672d16250c0042f50bfae352963583c3d 100644 --- a/configs/beelink-gtkingpro_defconfig +++ b/configs/beelink-gtkingpro_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" beelink" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig deleted file mode 100644 index d5aeb97c8ee6fe9c9a84f09430295f95f660ee6c..0000000000000000000000000000000000000000 --- a/configs/bg0900_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_BG0900=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 299206e85b30b7a6a62a781b199047fe40451713..79cff7505f4dc1f7c54d16712be688fe0001bf96 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_DEBUG_UART=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 20262e8be1d5ccba5a2a2e32071e6e3abde9f898..7691eec0b429db1a9a2d306cc147bdf4db0d11bc 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 @@ -8,6 +9,7 @@ CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 +CONFIG_SYS_MALLOC_LEN=0x402000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1" CONFIG_BOOTCOUNT_BOOTLIMIT=3 @@ -15,8 +17,8 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x220000 CONFIG_TARGET_BK4R1=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter passphrase to stop autoboot, booting in %d seconds\n" @@ -58,10 +60,6 @@ CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_I2C_EEPROM_BUS=2 -CONFIG_SYS_EEPROM_SIZE=32768 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index eb1dd71c67bc5939fac073e727056efd1136e769..e3770cc845581a5c861f7f291a24d2a789330ec2 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -8,11 +8,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot" CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche" CONFIG_R8A7792=y CONFIG_TARGET_BLANCHE=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index b1182043315b8c3eed922122edeeb3e8d7eceb48..756bc0e946949c97fe4a7ca4c54e49dbf1b85dd0 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -4,12 +4,14 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 479282178d182f550086d12377890acfaa014f43..94e7c9f17965f8e149e95ddba92708f36ccbfc10 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_SYS_LITTLE_ENDIAN=y @@ -11,6 +12,7 @@ CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 0e2c15651baf7a72ed27a8a99f2929f54dc6b42a..1c5a0a97b245526b54c1f586143e5093a87f8efe 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_CPU_MIPS32_R6=y @@ -11,6 +12,7 @@ CONFIG_CPU_MIPS32_R6=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index ba53f292e653673961328cfd578a171b5eefc727..9bd00d52c2f7b5e157703052f5a58e8565f05591 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_SYS_LITTLE_ENDIAN=y @@ -12,6 +13,7 @@ CONFIG_CPU_MIPS32_R6=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 47eead6275608d8ccefa8a6935c4e7c56d89fa8a..32632e19edfa483981e109c7ff28358e45124b4d 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_CPU_MIPS64_R2=y @@ -11,6 +12,7 @@ CONFIG_CPU_MIPS64_R2=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index c8da92ffd18b2e588d9182298889d13ba10625ab..82eeba1e923b8a680a7724f1ed571f954cdec3ab 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_SYS_LITTLE_ENDIAN=y @@ -12,6 +13,7 @@ CONFIG_CPU_MIPS64_R2=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index 8c8d74a5f5926726192d847486420ba8c5ae32d9..72651ccefd643676264fb3c05c86067651ed720a 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_CPU_MIPS64_R6=y @@ -11,6 +12,7 @@ CONFIG_CPU_MIPS64_R6=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index aca64ea32f7cc7535cfaa9f898ed236931807613..942ca975043621f3cf07c1e579a56a8e8531c87d 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_TARGET_BOSTON=y CONFIG_SYS_LITTLE_ENDIAN=y @@ -12,6 +13,7 @@ CONFIG_CPU_MIPS64_R6=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 683d0e768892d1219ca712b6572890e338beda70..ba971a4d43d25e408e66eddb8731ae4f13a8f26c 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -7,15 +7,17 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc" CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x50000 # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x80000000 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 5bd5845661b43714e7ce643b50eb884cb2721ad0..88f281c11f8211fc641fe610a3789e4a453de40a 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -7,13 +7,15 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x60000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-nand" CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x80000000 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 7fe7f56224c7cd08499a4ee03f7cef997393fd24..ec31c8dc203ff81df5e7d1d1598d05f820b55d51 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -8,17 +8,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi" CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x30000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x80000000 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_SPI_BOOT=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index 51c13726505d3e6db9f831c5e24de1cd2a2a690f..517eb9444cfd51349a9a5ff4b564058681720b95 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -14,17 +14,18 @@ CONFIG_ENV_OFFSET=0x20000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6QDL=y CONFIG_TARGET_BRPPT2=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_CMD_BMODE is not set # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x10700000 CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index 7f5c78248b1926a69d96d779bb718e043a29553a..f0037fcf0948750064717ff24335255e27f1999f 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -7,19 +7,21 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brsmarc1" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=600 CONFIG_TARGET_BRSMARC1=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x30000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x80000000 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index bc8c5db995aa6ac8cd2ec61340e8c94600867e1e..346a10c9017935db19402b13b383d09a0e55eaad 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -6,17 +6,19 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brxre1" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=1000 CONFIG_TARGET_BRXRE1=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x50000 # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x80000000 # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 34ff94615b2a9b86d0984fbbaf29ead628468416..141dec8a3cc8c1eb672448863480b016edaef44e 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_OWL=y CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" CONFIG_MACH_S900=y CONFIG_IDENT_STRING="\nBubblegum-96" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x7ffc0 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyOWL5,115200n8" diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index b4d38c569ccc8880ba61736769d3c2f808633fc5..6fb808db9e6668c0f8df1be2c3c637e4db6f9941 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA30=y CONFIG_TARGET_CARDHU=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 077324a0de9c2fc3896b40ecdcab965b8a5c892b..8923fd0224c13d955869857126cf4a90b4224f9a 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -4,11 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y CONFIG_ARMV7_PSCI_0_1=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 34aca6ea858d56cdac4d6518c987875f06d9a17c..c7dac3b6053ac8dec927b935eac2798ee6d96ed8 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -9,23 +9,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MALLOC_LEN=0x2400000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8" CONFIG_TARGET_CONGA_QMX8=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y @@ -46,6 +46,7 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y CONFIG_CLK_IMX8=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 85302addfdf160d499eaf42d8e1e6a8bd97796aa..f6ae494b8ee4b2add1a188e2e55c8828a10dbe9f 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -9,8 +9,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am335x-chiliboard" CONFIG_AM33XX=y CONFIG_TARGET_CHILIBOARD=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x22000 CONFIG_SPL_FS_FAT=y @@ -47,6 +47,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MISC=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index acc3286f09d80903f32b51bd3260e88adfe2bbc2..80ed1f0a1450f498dc723e78837227e38ab81104 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 @@ -6,15 +7,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_ROCKCHIP_RK3288=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBIT_MICKEY=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index f3f367a29c138793231dfaf5377b22bfc101f16f..fe938c659172184a83d362b387423653fc0d1fd7 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -9,12 +10,13 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index eb0884f1f5d7ba5482bf0ea9fcfa99ea479d0f85..321ad7de5b7fcd70621994fde1a14aeeefc64cf2 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -44,7 +44,9 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_CPU=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_PCI=y +CONFIG_SPL_POWER=y # CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_TPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y CONFIG_CMD_PMC=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index a2901ac08418282ffb24a7ca04dd872c7254760b..85f612093df4844373915a53d32272096a214ac6 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 @@ -6,14 +7,15 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_ROCKCHIP_RK3288=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index b48505aa1e20fc55fd44749757d72540fa5cd7c2..c43d9dcb927cdc9f99fdf5aa24956c34ff8a39df 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -35,10 +35,10 @@ CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_PCI=y -CONFIG_SPL_PCH_SUPPORT=y -CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_PCH=y +CONFIG_SPL_RTC=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 30044a802b0fddbc9d84c78ad0b03314db5bbe06..41a3fe1a3c5eb780595a4369d6b38a391111fbff 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 @@ -6,15 +7,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_ROCKCHIP_RK3288=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_MINNIE=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 6eef4ba896ff5195c30e0244ef3668712ac336ca..b231b3b0dbdcd9b7213ded088be875f372544b68 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -34,11 +34,11 @@ CONFIG_BLOBLIST_ADDR=0xff7c0000 CONFIG_HANDOFF=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_PCI=y -CONFIG_SPL_PCH_SUPPORT=y +CONFIG_SPL_PCH=y CONFIG_TPL_PCI=y -CONFIG_TPL_PCH_SUPPORT=y +CONFIG_TPL_PCH=y CONFIG_TPL_DM_SPI=y CONFIG_TPL_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index fe6528f190e6db089465576ab326d94627aef0d5..b396d9f70551b102ad798c8e4b2abeea3bb6c85d 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 @@ -6,15 +7,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_ROCKCHIP_RK3288=y -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_SPEEDY=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index c2efe39008825c2cf12ed6a37c24d3934465ec68..363bdfd49898d73e4fdd80e08ad4f40307820f06 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -6,11 +7,13 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x83800 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="ci20" CONFIG_SPL_TEXT_BASE=0xf4000a00 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_ARCH_JZ47XX=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1" diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index f5d146038c1d2ed5a0db100fcfa2144cf94abda6..99c46853a82db3584186c83ea822484cc0e24c12 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -7,18 +7,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_TARGET_CL_SOM_IMX7=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_LATE_INIT=y @@ -37,6 +38,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -60,6 +62,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -77,7 +82,9 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_MII=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index d8edc453fff3d550b1359a4f6599d6f33bd7a4b5..f613107ccdd56eac452d86851ba4e94523bf087d 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y @@ -12,13 +13,14 @@ CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index c94d63ee48543e68ec9e98809525e6637531ce18..89b978db6bc40a4c89aad006ba8b9d607b7c8006 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index de7870b123fcda94845577c896fee6dc8930b436..f6c0daac4235b608eb9688b0796ee85642c64cee 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -10,18 +10,21 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6QDL=y CONFIG_TARGET_CM_FX6=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_CMD_BMODE is not set CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" CONFIG_USE_PREBOOT=y @@ -38,6 +41,9 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -63,6 +69,11 @@ CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_MXC_I2C3_SPEED=400000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index af8e786f62e3c37b34bef38ddd7fb9bc967bf6c2..fd4e36393b85c0c99b0992cbd5b51e121b487340 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -8,8 +8,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x300000 CONFIG_AM33XX=y CONFIG_TARGET_CM_T335=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -30,6 +30,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -47,12 +49,15 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=64 CONFIG_LED_STATUS_BOOT_ENABLE=y CONFIG_LED_STATUS_BOOT=0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 289c3fc5b74adc5c56713e33a84c43b689fe6c14..45b41d3fcaf724b2f0e03839869c8098e8300bbc 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -12,13 +13,13 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-cm-t43" CONFIG_SPL_TEXT_BASE=0x40300350 CONFIG_AM43XX=y CONFIG_TARGET_CM_T43=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -42,6 +43,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -61,6 +64,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -77,6 +82,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ATHEROS=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -84,4 +91,4 @@ CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_OMAP_USB_PHY=y +CONFIG_USB_XHCI_OMAP=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 17739fbd502ce17e84c5297f94fb471da3543521..bbcdf45697c8752ff9d44e43c3281755f8a1b300 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -2,8 +2,10 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="cobra5272" CONFIG_TARGET_COBRA5272=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 739eea7c07f9b56db5545735c7afaf1ec9728283..f5fd4815d45ec06cc8d7259eef914908d5572681 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -8,11 +8,11 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x380000 CONFIG_MX6ULL=y CONFIG_TARGET_COLIBRI_IMX6ULL=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,IMX_NAND" CONFIG_BOOTDELAY=1 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index a0816acc27c9a0f423bb31f452d4e7222625c76c..d9c1e4d61650af3ca4bfe6c8e34397061cc63974 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -7,12 +7,13 @@ CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" CONFIG_TARGET_COLIBRI_IMX8X=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y @@ -32,6 +33,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 47b1cfb1917927c71309ae10c9a55fc98f915910..62a207f5547a6399b51cdada5623ccb927a06bcc 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -11,16 +11,19 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6DL=y CONFIG_TARGET_COLIBRI_IMX6=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_CMD_HDMIDETECT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -69,6 +72,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_MXC_I2C3_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 39149167e0008e4538c275f4baabd746451b01af..c22332c489e9f763a3f5cf3b829c4f8e5be5ea55 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x380000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand" CONFIG_TARGET_COLIBRI_IMX7=y @@ -12,7 +13,6 @@ CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" CONFIG_BOOTDELAY=1 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y @@ -59,9 +59,9 @@ CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_FSL_CAAM=y CONFIG_DFU_NAND=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 87527671fef198ece9e3776d82b43ae7c083465c..b1adb8dc3b72ec0132510a164116e65fe25415b8 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8c000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc" CONFIG_TARGET_COLIBRI_IMX7=y @@ -14,7 +15,6 @@ CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" CONFIG_BOOTDELAY=1 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y @@ -46,7 +46,6 @@ CONFIG_CMD_CACHE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y @@ -54,7 +53,6 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_FSL_CAAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 @@ -62,6 +60,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 814d87e939364051c06bf0b8bb4d0d6f0be05711..9234f57ac00d403ef42cc50e6e595e49c899a8b8 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -7,7 +7,9 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0xa0000000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" CONFIG_SYS_DEVICE_NULLDEV=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index ac98e84b440105b211eff5955bc5a9ae6a845d9c..c9fb555341dcdd56dee7a3f3915f211530c63749 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_COLIBRI_T20=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 618f7c10a1b1aee1986cc1f3d1a05716c616e48a..3c37341932ebd04aa7624af2f6dc34f5435bf190 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA30=y CONFIG_TARGET_COLIBRI_T30=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index abb81178046099598ede7c56c30c6be3329a576c..3fb13ea20cb6633c8016167d3a002e3d2c648c99 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 @@ -8,11 +9,12 @@ CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x180000 +CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" CONFIG_TARGET_COLIBRI_VF=y CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,IMX_NAND" +CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb" diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index 0e7d9cd8b152f28769195f9a435263f8f461b9d7..2278763adaedf3d9815f012c6060a2674156a2f9 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6318=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 655db1bba6ebc2ad4f6005408e4e80f2d3ca3867..7497ac2baee4303c70e09ed264c9d77d3671b93d 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6328=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index d051f3db5db8cbfda757b9709a0d50b4f8eecde4..647031014a2c7e5e3b17a0eee8c7a76732f0cb03 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6348=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index ac963efdcc2ced2c915a2ec5deb6d0293ba04d82..2cb0bac6c802923dba4d346a1b4352c6160af655 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM63268=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index af565c519a0b73be636c27eec1da936773ca4c1a..8864a1342411efdcdc357524acc45a96b4fd4d35 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6368=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index bb1e09585c0a0c5d56e1037832a8a1018e67fb1c..bf0581ad168283e8de30f4b26606b128f64d20c3 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 @@ -12,13 +14,14 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig index d84db883d2f70b894c778b675d1c9accd35e99b9..04a99348726eaa0880bb557d3e48296578647cb6 100644 --- a/configs/cortina_presidio-asic-base_defconfig +++ b/configs/cortina_presidio-asic-base_defconfig @@ -4,9 +4,11 @@ CONFIG_TARGET_PRESIDIO_ASIC=y CONFIG_SYS_TEXT_BASE=0x04000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x820000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/cortina_presidio-asic-emmc_defconfig b/configs/cortina_presidio-asic-emmc_defconfig index e5163d1e0fc5c6ef693a9b1fca20072e988dd7d0..b5b2fb7072a34a04eaeb61937113cc2887d6ca51 100644 --- a/configs/cortina_presidio-asic-emmc_defconfig +++ b/configs/cortina_presidio-asic-emmc_defconfig @@ -4,9 +4,11 @@ CONFIG_TARGET_PRESIDIO_ASIC=y CONFIG_SYS_TEXT_BASE=0x04000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x820000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig index a865cbf4c6a1dba7b385ac769b3bd9e168e5a55f..51451fbc43c30d19d25231d58620c5a0f98dde9b 100644 --- a/configs/cortina_presidio-asic-pnand_defconfig +++ b/configs/cortina_presidio-asic-pnand_defconfig @@ -4,9 +4,11 @@ CONFIG_TARGET_PRESIDIO_ASIC=y CONFIG_SYS_TEXT_BASE=0x04000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x820000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 42c0a48b23b4d8ae15456bd8750af7b8d18fa8fa..72f4310d3cfb55e4bfaa29eb852605a485d0d240 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -11,12 +13,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" +CONFIG_SYS_LOAD_ADDR=0x70000000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig index f924efb6e02bc1b82acdcff277819270c7a38aed..bf6186030cffa853bc3228844a56f32d42f6f1ef 100644 --- a/configs/crs305-1g-4s-bit_defconfig +++ b/configs/crs305-1g-4s-bit_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s-bit" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index 677e248e6b8e325ab38792efacd0b2be8d44eb44..5fc805875bde5d3c467146533cdc917eaaa1f8f6 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig index 61bb79e63ef909a33d6fb0f18a939fb06369afee..3de29490e89862e980e5b38e8c60a6b093857c4a 100644 --- a/configs/crs326-24g-2s-bit_defconfig +++ b/configs/crs326-24g-2s-bit_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s-bit" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig index 87e64e93dd3d34246347dd04c0aa679b06f1617b..77296abfc9bfb06ee3a23994f0253182ded51982 100644 --- a/configs/crs326-24g-2s_defconfig +++ b/configs/crs326-24g-2s_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig index 19cdd5bdf82d0594b62e7a013bb8e0947d21addb..513cc52562edc40b57951771b083aad8c27e71d9 100644 --- a/configs/crs328-4c-20s-4s-bit_defconfig +++ b/configs/crs328-4c-20s-4s-bit_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s-bit" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig index 703fcaceb5536825c3e1234c3e76d69e76eaacab..dd0cd63b90c84b93aad73947d20f8c027969b86b 100644 --- a/configs/crs328-4c-20s-4s_defconfig +++ b/configs/crs328-4c-20s-4s_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig index 8efb94dea83dc588653036036b094c60daef118d..2937a54d1195143d8776a8b06bb637a941654c8b 100644 --- a/configs/cubieboard7_defconfig +++ b/configs/cubieboard7_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_OWL=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7" CONFIG_MACH_S700=y CONFIG_IDENT_STRING="\ncubieboard7" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x7ffc0 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyOWL3,115200n8" diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 017bb216230e00b661e3e75f8b66f4b7124450d4..d32a9affe52d9e6d30eb91b49805949ca537235b 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net" CONFIG_IDENT_STRING=" D2 v2" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="d2v2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y @@ -43,6 +46,10 @@ CONFIG_ENV_ADDR=0x70000 CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index af565f65106446c360068a58298bd2b1f93074d7..c1a857f1d9cb19c8345ffb41aa16cfb34d6ba864 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 @@ -11,14 +13,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x110000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_BOOTDELAY=3 CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index e69da40a110122d57b803c4296e479c1d4a314bc..15bdd7e82fba3faf679a554bceaec4aea781d6d6 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0x60000000 @@ -9,9 +10,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2800 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x110000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 7803bf5c5060684d1d75292dee9c6bef60fd49cf..6d59cc5d9f84354eb556a100aa47d2029f607679 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 @@ -9,14 +11,16 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x110000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_BOOTDELAY=3 CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index dabdb070642ab7ae68436d43be80384cabc4d8bd..8c5ac9de1b891a26905ae032cb6ad640bdf7fda1 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA114=y CONFIG_TARGET_DALMORE=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 7f9d65f020b12262f10b593e6b566c9ef4f86034..632a22f46fdbbc016367b641d9fe709e92021275 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 @@ -12,12 +13,13 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" CONFIG_SPL_TEXT_BASE=0x40004030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -45,6 +47,10 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 96841d786278ca43cce7ad7cd5c0102b3f0ce4f8..af8c372b84b1dc1fd04121f4f9c1cb5965502fc5 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 @@ -12,11 +13,12 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 0ab8722c82fc2c2382672e9e5e8351607809fdbe..2e0f9384f2ad6855c3719b712d78f71db1ca2aab 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 @@ -12,12 +13,13 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -48,6 +50,10 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_AHCI_MVEBU=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index a4345bae2b0b717cdfd165437b3824ca76373f7b..26aa5d080a2bbac409b55377e82622406444612a 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -12,12 +12,13 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" CONFIG_SPL_TEXT_BASE=0x40004030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -49,6 +50,10 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 9a162df295df9aea72e16c4ad875e1383eff086e..c32a48a97de66b6fcc1c29f0ba715a14cf34cccb 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg" CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index 4e2c6d668f50e6d9f824d02401dd812ae38e10ed..4046fbec087ba29cca8543e2e8ec82990fc02148 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -8,20 +8,21 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb" CONFIG_SPL_TEXT_BASE=0x100000 CONFIG_TARGET_DENEB=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -32,7 +33,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index b56408f98afc689fe1817bebb2224761698956f4..a1d277914167ef0506b448e32e874bf1732dc454 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y @@ -9,9 +10,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xA0000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_TEXT_BASE=0x00000000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" @@ -37,6 +40,9 @@ CONFIG_CMD_JFFS2=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y +CONFIG_DMA_LPC32XX=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_LPC32XX=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 2be548ea2c97b8e91a2dfacf3768b369b617bca6..0ec943a4ae32b4d36e24ae89888e3ade66331356 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_DEVKIT8000=y CONFIG_SPL=y @@ -34,6 +35,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TWL4030_LED=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index ce966420f83fc3c5ebe3eedeabc1f54b734f108f..eb588b68d3c41ce6a84c9fe42123a052fa2a6094 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -17,22 +17,21 @@ CONFIG_TARGET_DHCOMIMX6=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x110000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index 24f460817bfd8b22f854c9fc94473aacbac77855..e1067b66eec2117f0e3c83c04ca304b3625535fa 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -16,5 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index d6541876f14a7f7a535b127b5e5023adf7a3cadb..a49bf331796c11fbbab2d2af7047253d31d0d010 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -15,10 +15,11 @@ CONFIG_TARGET_DISPLAY5=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 @@ -26,13 +27,12 @@ CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_MISC_INIT_R=y CONFIG_SPL_BOOTCOUNT_LIMIT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set @@ -52,6 +52,10 @@ CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -82,16 +86,13 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_I2C_EEPROM_BUS=2 -CONFIG_SYS_EEPROM_SIZE=32768 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 7dbed0473a72f87372260aa568c371053df88ccc..5a2e478c4847a601c669838d6f691c912c709e60 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -15,21 +15,21 @@ CONFIG_TARGET_DISPLAY5=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="echo SDP Display5 recovery" @@ -52,6 +52,10 @@ CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -86,16 +90,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_I2C_EEPROM_BUS=2 -CONFIG_SYS_EEPROM_SIZE=32768 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index edcdb87d54ffd3640d2d652a877371998f07754e..c6598f7b7a3c8a234d7dae96bd7f186ca2439c56 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325" CONFIG_IDENT_STRING="\nD-Link DNS-325" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 8d43609cd11a9b7d6f69a119968a4f4a6da94778..d82dfd02697684ea08ae4de0760b065c20ff97b1 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar" CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 0c253da80cb95bf3837a03672b14737cf14783ef..11dc022b6cc896b56304a8b553e3c228eefc69b3 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -12,7 +12,7 @@ CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -40,6 +40,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_CMD_SPL=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -82,6 +83,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -122,6 +124,7 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 885b236f188619a28d3becc3b505b7692c4d1c95..c231991ea5835e36e577dfc63917182ab11058e4 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -15,7 +15,7 @@ CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -44,6 +44,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_BOOTP_DNS2=y @@ -85,6 +86,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -125,6 +127,7 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index efdd9f31c74a2871e5e1184845c06cb7d6df24f3..09aa07379a8badb37bf47b1a604014c0f03ba03d 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -17,7 +17,7 @@ CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -44,6 +44,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y @@ -81,6 +82,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -119,6 +121,7 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 629d20a9ef4a97c922e3bbd023d9a11a7b81692b..dfb98c6daed274d8bb447ef5824f16bd60834b70 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -7,21 +7,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_DRACO=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -76,6 +78,8 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index b8aae592b6609c74267d3e57f6de5288b9b24557..f3e3815715164376eea53fb01d0f927417436eb6 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -4,9 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x8f600000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x802000 CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80080000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index 3a9cf0a5ef043f6477547a598f6637343eb9f083..9d8819fe3fc0c893077da6a2d4c0cd89e5065d26 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -3,10 +3,12 @@ CONFIG_ARCH_SNAPDRAGON=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x804000 CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c" CONFIG_TARGET_DRAGONBOARD820C=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyMSM0,115200n8" # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 664391371ad2016c9520507cd80ca77084b8ac6f..c112389c5e270a8b49265ece5becf47c97a80c94 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug" CONFIG_IDENT_STRING="\nMarvell-DreamPlug" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 9f146ec3d4acdd8d24e01f464dbc1eab39357bc3..d7e865111f4d9b3060414ed9c6d4a007220ea9b7 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -1,7 +1,13 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_STATIC_MACH_TYPE=y +CONFIG_MACH_TYPE=527 CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_DS109=y @@ -10,6 +16,7 @@ CONFIG_ENV_OFFSET=0x3D0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_USE_PREBOOT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index bfe2e5f4fe70f57ee9e26b846e91608dfc6c70d0..6402e253d1d4e9a20068989b3d07f3eb876cc5e0 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -1,22 +1,29 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_STATIC_MACH_TYPE=y +CONFIG_MACH_TYPE=3036 CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_DS414=y +CONFIG_DDR_32BIT=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x7E0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" CONFIG_SPL_TEXT_BASE=0x40004030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1" @@ -46,6 +53,10 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 8c6df755d51ae1d1d5a591e3fcde82c3227888ea..60910c3ce3542bd3a767631d69a267f6ea2aaa46 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -15,4 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/durian_defconfig b/configs/durian_defconfig index 77b9795d10623b1413db81a421ea0869142eb0a8..bc418f65618e7643e867afb450d6b49451b37df5 100644 --- a/configs/durian_defconfig +++ b/configs/durian_defconfig @@ -4,10 +4,12 @@ CONFIG_TARGET_DURIAN=y CONFIG_SYS_TEXT_BASE=0x500000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x101000 CONFIG_DEFAULT_DEVICE_TREE="phytium-durian" # CONFIG_PSCI_RESET is not set CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig index e8d60b573eaacf82bf91fa785b13e87311f50078..8d9a905c4271ea8fb699c79f293da921c9e0fdab 100644 --- a/configs/ea-lpc3250devkitv2_defconfig +++ b/configs/ea-lpc3250devkitv2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_EA_LPC3250DEVKITV2=y CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80100000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set # CONFIG_AUTOBOOT is not set # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 95f1df9a4c65439594d47b5fccd0b870719391a4..9bbfcf284d0f2e7c3f0aa9d630557aefcd3be631 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -4,6 +4,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282" CONFIG_TARGET_EB_CPU5282=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set @@ -18,6 +19,10 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0xFF040000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x300 +CONFIG_SYS_I2C_SLAVE=0 CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=8 diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index a2bffaf2377d9fd0c6e1adbbab53dc3140c5d0e6..abc87ecc657317b8ade431233de4c0ca5ba1ffdf 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -4,6 +4,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal" CONFIG_TARGET_EB_CPU5282=y +CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,6 +18,10 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0xFF040000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x300 +CONFIG_SYS_I2C_SLAVE=0 CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=8 diff --git a/configs/edison_defconfig b/configs/edison_defconfig index a78963006c298c41abea4ee817d8d9eca57c67b5..53d5ce683a9fce82b3743ab703cf813c7f74203d 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -3,12 +3,14 @@ CONFIG_SYS_TEXT_BASE=0x1101000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_MALLOC_LEN=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="edison" CONFIG_ENV_OFFSET_REDUND=0x600000 CONFIG_VENDOR_INTEL=y CONFIG_TARGET_EDISON=y CONFIG_SMP=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index 3d1365dd68f108ef75fac0bbfcc196c1d32f3864..e74f4dbed95c7a2a2e5c64cc41ebf59729c0b09e 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -8,11 +8,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SPL_TEXT_BASE=0xffff0000 CONFIG_TARGET_EDMINIV2=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_IDENT_STRING=" EDMiniV2" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -31,6 +33,10 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xFFF84000 CONFIG_NETCONSOLE=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index af4f3f1d231b683544d34db0d2960f3db6e632bf..ee5bfddc438380f71c8c495904ffb6778b2d8594 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 @@ -10,6 +11,7 @@ CONFIG_TARGET_ELGIN_RV1108=y CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x62000000 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig index 1948c76fee2196505cc0a21dfd123c180bd8120e..1ae7382f2aec8f70d5a61960e4ed05bfe016bfbc 100644 --- a/configs/emsdp_defconfig +++ b/configs/emsdp_defconfig @@ -4,8 +4,10 @@ CONFIG_CPU_ARCEM6=y CONFIG_TARGET_EMSDP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x10000 CONFIG_DEFAULT_DEVICE_TREE="emsdp" CONFIG_SYS_CLK_FREQ=40000000 +CONFIG_SYS_LOAD_ADDR=0x10000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index a079accfae2981b70b60683d31e386f436181e8a..fc968816d5afc42bae4a62d5ad19b04425a74538 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -6,8 +6,10 @@ CONFIG_ARCH_EXYNOS7=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420" CONFIG_IDENT_STRING=" for ESPRESSO7420" +CONFIG_SYS_LOAD_ADDR=0x43e00000 # CONFIG_AUTOBOOT is not set CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 0991a51bece3f9a59873db3f05a03bf3fb96ec3b..f60ce5b8fa4dd24316474f584be057b370bc56d4 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -8,21 +8,23 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x980000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_ETAMIN=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xB80000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -77,6 +79,8 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 4da3c1d4f4c9b6f76cd3eb6abd9b37fc689c70db..91fa97df82dffd0d611f04999c40e3cae3900496 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x27000000 @@ -8,8 +9,10 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x21000 CONFIG_ENV_OFFSET=0x3DE000 CONFIG_ENV_SECT_SIZE=0x21000 +CONFIG_SYS_MALLOC_LEN=0x121000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ethernut5" +CONFIG_SYS_LOAD_ADDR=0x020000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -55,6 +58,9 @@ CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ev-imx280-nano-x-mb_defconfig b/configs/ev-imx280-nano-x-mb_defconfig index afb2a68a3020ef4b3c5a02a0e61457c04fc8916b..dd4586f1a5b02d9d90330646446b9c08cdf1a788 100644 --- a/configs/ev-imx280-nano-x-mb_defconfig +++ b/configs/ev-imx280-nano-x-mb_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_MX6ULL=y CONFIG_TARGET_O4_IMX6ULL_NANO=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_EV_IMX280_NANO_X_MB=y CONFIG_IMX_MODULE_FUSE=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 91334195118f43de2a37ba5ecc73db636034141b..3dab945503fd84cdc3e785e3635f667bdf56a69e 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -6,8 +6,10 @@ CONFIG_TARGET_EVB_AST2500=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb" CONFIG_PRE_CON_BUF_ADDR=0x1e720000 +CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw" CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index 19b9210bd1de993c9ed300258a987d5dc6388366..56ab885d9b9b5eb3122d53ca010183a96a766d99 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -9,12 +9,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x10000 CONFIG_SPL=y # CONFIG_ARMV7_NONSEC is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_FIT=y # CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_USE_BOOTARGS=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index f4b30ed3bbc739ba4a9fa3fbe902e214a5a2aeb6..7265ac4c5c47da2b723aa050a0244145fcf02199 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -16,6 +17,7 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 50a4bc143656131dd4d99a45fb7c29889c02b6f5..0cca4164be2e2117cd7405804bd8d4b1eefcce6c 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -15,8 +16,9 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF1c0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 324528e29684a364a648011e67cfad0cb3083b2a..ce44c3602b50439d0115f10e27b14c1e78a24374 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y @@ -13,6 +15,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x60800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 10628016423c0e3f1dc87e021d1c2560a2c1c03d..e446a226415ce46a4d5d6c0bb38a009901a1fa3a 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=2 @@ -8,6 +9,7 @@ CONFIG_ROCKCHIP_RK3128=y CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x60800800 CONFIG_FIT=y CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 02e19fa10cc1ba8d4553eb9f25fa1238e3c47370..0bf91d61b45d4d4c5548f8a8256fcfb1a12e81ba 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -1,4 +1,7 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x61000000 CONFIG_NR_DRAM_BANKS=2 @@ -13,6 +16,7 @@ CONFIG_SPL_STACK_R_ADDR=0x60600000 CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x61800800 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 658ddc97504d68a434f9cb93dcbf160366ac8450..efb2a3ede699ed232fbe9a97ad2e584d8a1d3f2e 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=2 @@ -11,6 +13,7 @@ CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index bd4a03ae64c620fabe40d7952b20c9a3ae398326..15a6e376f58ad47471f7eb108780f69b41c27990 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00600000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -13,6 +14,7 @@ CONFIG_SPL_STACK_R_ADDR=0xc00000 CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 7cc828fb69f52ae708eb012db816fe73cab8e17e..8b59b8c11866a68474bb15018a2f68ccf3bbd4b0 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -15,6 +16,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d5eba1d903ca2c8651ddb3f99f72c5a4d68b5197..4aa49102bf3e19cfba84af576a765066dfc85d19 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index a102a5a99904ec1d46eb72b24d5232ab3a17df7a..7453ccf1274f4204c572e471ae5eb1e3049d4899 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00a00000 CONFIG_NR_DRAM_BANKS=2 @@ -8,6 +9,7 @@ CONFIG_TARGET_EVB_RK3568=y CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index be7ebd47079ce1db7507e08befe84762ee4167f5..916a6fb8510fa2bf06d0a67fe259cf858a43046b 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 @@ -7,6 +8,7 @@ CONFIG_ROCKCHIP_RV1108=y CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x62000000 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index a2df9eab3c28aedd9d94f3b8944f50eedfa552f5..61c5602a3d080215881eedf92794e1fc0b9ff467 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ENV_OFFSET=0x3F8000 @@ -10,6 +11,7 @@ CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 64744d534cbe9bdaf4577c3ee9071cfd1b4cec27..363fa636f3ce525e9d231c9af7b9a7689a41acdb 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -17,6 +18,7 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 91b7974c408dbd50d46acf53b474560d5b9ac57b..057e9095f0509edf8b9afce4aaf78ddc2bf87534 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 @@ -11,6 +13,7 @@ CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 2ca2ac35e43110f9ef6d78ec3fe61c1d917834c8..d576b5c38d99af00e717e4f476384c9f499c93b4 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig deleted file mode 100644 index 07ae0f76738adaae538179fd179d9d74e594d0d1..0000000000000000000000000000000000000000 --- a/configs/flea3_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_TARGET_FLEA3=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="flea3 U-Boot > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA0090000 -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index ae6dbfd6dc8175835026bda06487e35fb7411839..4e1b44e0fc68d24de1796676997c67f332b2d223 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x22900000 @@ -8,20 +10,25 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x0 CONFIG_ENV_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="x" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -32,20 +39,26 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_WDT=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_UUID=y CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="atmel_nand:1536k(uboot),10752k(unused),-(ubi)" CONFIG_CMD_UBI=y @@ -58,6 +71,8 @@ CONFIG_ENV_UBI_PART="ubi" CONFIG_ENV_UBI_VOLUME="uboot_env0" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_env1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SPL_DM=y @@ -71,6 +86,7 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y +CONFIG_MTD_UBI_FASTMAP=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -84,3 +100,4 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_WDT=y CONFIG_WDT_AT91=y # CONFIG_UBIFS_SILENCE_MSG is not set +CONFIG_LZMA=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 46b9849b1c98e566b6cd0aa9c48f29cd714a9c9a..6b1f9ac2d6b6d73fc63b46cf034b0a7d6f2fd2db 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -6,8 +7,9 @@ CONFIG_SYS_MEMTEST_START=0x0 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xA0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000 CONFIG_SPL=y @@ -15,10 +17,13 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xB0000 CONFIG_ARCH_MTMIPS=y CONFIG_SOC_MT7628=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 23d10bfa4a7547ae565e2e533b1f88baa033d805..91f913493d409f5d1f069db02cc507e9ae70b2da 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_START=0x00001000 CONFIG_SYS_MEMTEST_END=0x07e00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" CONFIG_IDENT_STRING=" gazerbeam 0.01" diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index cea6a736492c636b81a1c59c9116295d96e6ff05..ef32a4bc6ddcd08722ea5f85717b436fc94facd7 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -12,22 +12,22 @@ CONFIG_ENV_SECT_SIZE=0x10000 # CONFIG_GE_RTC is not set CONFIG_MX6QDL=y CONFIG_TARGET_GE_B1X5V2=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x21ec000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=1 CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 76e478b580699dcc66624dcb28a11c00c36c8997..690fa11782832c9504e76d5ed94d85177f9ab624 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_MX6Q=y CONFIG_TARGET_GE_BX50V3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3" CONFIG_BOOTCOUNT_BOOTLIMIT=10 diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 55892f07f2cc2ed0dd81a5632cca85c4cbc2bc62..719c6c7c65e314ae913fb8787e90484a0189a795 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SYS_MALLOC_F_LEN=0x1000 @@ -9,6 +10,7 @@ CONFIG_TARGET_GEEKBOX=y CONFIG_DEBUG_UART_BASE=0xFF690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index 759640065a3e029b88e1e47493cb479752466258..94fda05c5269fe6061e43c2d084e23c3410e4d95 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -8,20 +8,21 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" CONFIG_SPL_TEXT_BASE=0x100000 CONFIG_TARGET_GIEDI=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -32,7 +33,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index d0a9e216a507fc364f18aef4ccdba64fc3ee8c11..e8a2f36761979cde14f6ae5fb6686b0c5f894a28 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet" CONFIG_IDENT_STRING="\nSeagate GoFlex Home" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index a5414f74c79ec829537f4608f959ccd5d3ce283f..b51cb4add072445c2d73069946d78ba0c0909dd9 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Gose" CONFIG_R8A7793=y CONFIG_TARGET_GOSE=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index e4a570de564652d6612da58a2c564d79ddd43de5..4a3a3f1b21cefe4fc405839a99e9c4aff3ac485b 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -6,9 +6,11 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot" CONFIG_RZA1=y +CONFIG_SYS_LOAD_ADDR=0x20400000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="ignore_loglevel" diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 896a3b15088d2058fd8c3ad33a02000d1088f081..03051054596a4f15e7513a2869a545996e4f88b8 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -1,11 +1,14 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x73f00000 CONFIG_TARGET_GURNARD=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" +CONFIG_SYS_LOAD_ADDR=0x23000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" CONFIG_BOOTDELAY=3 diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 619254c2b5514537fdb11f2f7cb017b1d63671dc..4a9cd23113c87feafa05b1c034945c3e4febf2d1 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus" CONFIG_IDENT_STRING="\nMarvell-GuruPlug" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 9e764f40a2297bcf544023f9a21ac3172ed7b417..000bdb5949193b3fdafa77e995ec82ea99f6617b 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -9,12 +9,16 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xB1400 CONFIG_MX6QDL=y CONFIG_TARGET_GW_VENTANA=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_CMD_EECONFIG=y CONFIG_CMD_GSC=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 @@ -26,7 +30,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -76,10 +79,14 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -96,8 +103,10 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index bab61e7daad08cbc0f73be28106cd531397fbf65..87851f352457db1ba1d96c6a4a90c5367cece047 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -9,12 +9,16 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xB1400 CONFIG_MX6QDL=y CONFIG_TARGET_GW_VENTANA=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_CMD_EECONFIG=y CONFIG_CMD_GSC=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 @@ -26,7 +30,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -76,10 +79,14 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -100,8 +107,10 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index e59efebab7770062ee55b49357b7dc220df88871..ff5001ef9611344df4caeb2d43c0aad6b48842e0 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -9,12 +9,16 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x1000000 CONFIG_MX6QDL=y CONFIG_TARGET_GW_VENTANA=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_CMD_EECONFIG=y CONFIG_CMD_GSC=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1080000 @@ -26,7 +30,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -78,10 +81,14 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -102,8 +109,10 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 874311e487bd3592c3e5a876dfad1ad20f50f9fb..2372d17f5fae52b9e026bf7a6d8de6e1c688cdf9 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_HARMONY=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 4e593601efd1f3c6be3f3355876bec1bc4afd6d7..c121a3caf6cc1527cb950194425f0be7b6628bf2 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y @@ -12,13 +13,14 @@ CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index a6aed676d4f6f8acefe20a6e1483b2c2b674242e..43a070e723376d9516c79f691a3b025076d342e9 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -1,13 +1,16 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_HIGHBANK=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index d91604045aeccdd851260b4d2de2d22fd26fea94..f0d07fcd185ee50023493a8bf7cc65a9d5384a62 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -4,11 +4,13 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot" CONFIG_RCAR_GEN3=y CONFIG_TARGET_HIHOPE_RZG2=y # CONFIG_SPL is not set +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig index 316a0420df0952d4c9f10e9fd383f2cbcf9e31a1..5c193508d7e9428a90656c5c8119653c5681ace1 100644 --- a/configs/hikey960_defconfig +++ b/configs/hikey960_defconfig @@ -4,9 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x1ac98000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x801000 CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960" CONFIG_IDENT_STRING="\nHikey960" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw" diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 0ec1ed78a0bd42c5a8205c7d5386721a81c095b5..5d3d28d9319485eaf4ea1a23ae86572ff7ae25fe 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -4,9 +4,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=6 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x801000 CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey" CONFIG_IDENT_STRING="hikey" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw" @@ -24,6 +26,7 @@ CONFIG_SYS_MMC_ENV_PART=2 CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_DM_ETH=y +CONFIG_POWER_LEGACY=y CONFIG_CONS_INDEX=4 CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 03f1e8b82c482d1f8effced6a084a8274c4bbe4f..792cc1a99d5951dc5756dc68de7cdab7eb7ad275 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -3,12 +3,14 @@ CONFIG_ISA_ARCV2=y CONFIG_TARGET_HSDK=y CONFIG_BOARD_HSDK_4XD=y CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="hsdk-4xd" CONFIG_DEBUG_UART_BASE=0xf0005000 CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=500000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index e4245630c0ba5630c9364b638673c63e62a4ff20..c72ad9f6f778eb905b280acb0334cb23f2134115 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -2,12 +2,14 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_TARGET_HSDK=y CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="hsdk" CONFIG_DEBUG_UART_BASE=0xf0005000 CONFIG_DEBUG_UART_CLOCK=33333333 CONFIG_SYS_CLK_FREQ=500000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 987ad318765126f795a277bf5eb48041861d5b69..81a412bed796f381a286058d36db5b70c844947a 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6358=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 8f99db7bcaae141334448b70754bcb5094d70778..257dd89af45b45b53205e94eb6a10d813338f8f3 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -8,6 +8,9 @@ CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 5efbf212b61bfee13ce67aee07524e2765e0cdf7..436e3a8c209f88d42347cfc7f4488f8cd7907f08 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -15,4 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 4aeb19b6526975bf453c6fee128a5290a85f927f..6978f8b0aabd439a47d4b9e5ae8dbc5abe78801c 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -15,4 +15,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index b85df7f0d64284c1ea0809a22c4c8641add3b870..2c8ecb51de05f7bc1372beec5c40b1611f144e6b 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -14,5 +14,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 7f203043900271161a2e30d3d18916e1f612b2cc..eeab2e8c119f4dfd0f823b1b2f1aa58be1785d6f 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0" CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index e69c79f3fef0a4dc2a5e21cb4050dd7f37b85dbc..de766b226bb5c524d0e6673305ee19b0b7691046 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -1,5 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_SERIAL_TAG=y +CONFIG_STATIC_MACH_TYPE=y +CONFIG_MACH_TYPE=4283 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac" CONFIG_SPL=y CONFIG_MACH_SUN7I=y @@ -15,6 +21,9 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_CMD_UNZIP=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 1e3f85387d52d08d6b270812cabcd526d3c61cef..d8593bcdd2835cf7c8220a57769921a4fdc4910a 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect" CONFIG_IDENT_STRING=" Iomega iConnect" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 3f5824d76fccdb56fd7b1d2b86113568fb02e8f6..8435de16338d48d003741c6154d12736aacffb35 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_SYS_BOOTCOUNT_ADDR=0x9 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -117,6 +118,7 @@ CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y @@ -154,6 +156,11 @@ CONFIG_ENV_ADDR_REDUND=0xFFFE0000 CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_I2C=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=400000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index a3b97e512c05915b0a3c3dcf1360f139cd985b1e..da0d5982b9ab644ae1867fb5470557f942346f49 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -54,6 +54,8 @@ CONFIG_ENV_UBI_VOLUME_REDUND="config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_SYS_MTDPARTS_RUNTIME=y diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig index c8e09829dff89237a34bc9451eb6bf9d32b56e74..79c57587ea4cf821e5d04670e47cc7c41681ab76 100644 --- a/configs/imgtec_xilfpga_defconfig +++ b/configs/imgtec_xilfpga_defconfig @@ -1,10 +1,15 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr" CONFIG_TARGET_XILFPGA=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y +CONFIG_SYS_LOAD_ADDR=0x80500000 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index cab908e4fd37247aae8ad5e63c2aca890662ae13..f4e65ffec3c0e0ae6b1462219f988bec52848e3f 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -7,19 +7,21 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 +CONFIG_IMX_CONFIG="" CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="imx28-xea" CONFIG_SPL_TEXT_BASE=0x1000 CONFIG_TARGET_XEA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index fed8793c435fc770a486e94541bc0af7688a0316..70d5edf7dae3173d05bc03a6c58cdaf70f1e1b72 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -11,16 +11,16 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 48f0c0356d33dd4c6d96d090997e98144c3a08f8..70268d0ab5d6bff46ca70652abb77bca9316a229 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -8,12 +8,12 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6DL_MAMOJ=y +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_IMX_HAB=y # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_OS_BOOT=y CONFIG_CMD_SPL=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 3064a1301baca16276cfc7780d1a8bb6895aa8c0..3c2fee90ffa3e94cc02fafd62246684476547916 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_FIT=y @@ -21,7 +22,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index ed8db745b6fb106ee8931b28db649519d0fbee11..1200311c330ab908d5b2dbcb01ceda93307a88b5 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -12,16 +12,16 @@ CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6Q=y CONFIG_MX6_OCRAM_256KB=y CONFIG_TARGET_MX6LOGICPD=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index d3191a250a9935bc948f2b9b7037bebaabbd07ef..8c9843696f2a4d39287c6178b7cf1a6a9f690fca 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x021f0000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -27,7 +28,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_OS_BOOT=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 76375ae9111c2ed7097553e87037b1c532ed2ecc..b80f28af01df1911a03f2c1eed9e53d28e4b32ed 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024 CONFIG_SPL=y @@ -30,7 +31,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_OS_BOOT=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 3064a1301baca16276cfc7780d1a8bb6895aa8c0..3c2fee90ffa3e94cc02fafd62246684476547916 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_FIT=y @@ -21,7 +22,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 328e68d20aee1ba800f1b3ed19df909b20b8d0a7..4594df010e924a54ed140ad206538f56eda2b322 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set @@ -24,7 +25,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_OS_BOOT=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index ebcccdd85add2f7f7a116e1ed3046cae0232a3d3..541ab31f8a0ed4fb5a93309a07a97854f97370e4 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set @@ -22,7 +23,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 8f9583d86f4fe9cde7613089273ac22332f1ad84..fcfdb21c35428837f2b70aabb2bc16ebb0f1d32b 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_FIT=y @@ -21,7 +22,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 18850f6a4382d0727cf6a11c2a48d07241b01663..8b27b8d23bdc253a6510ac5a0e8381720ecbcc89 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set @@ -22,7 +23,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index a29dac03df41b7356b0dafeaccd8d3c77c8153ab..d60905758bea9d9556e9567d394bd9b04ec68a00 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -11,9 +11,10 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_ENGICAM=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_FIT=y @@ -21,7 +22,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig index 72a1dc29e94afb5a2f89f0e1390b1455b2ef5f02..8b9b1ad387ae028dc8b3e2bf2b8491b67092b4c9 100644 --- a/configs/imx7_cm_defconfig +++ b/configs/imx7_cm_defconfig @@ -10,17 +10,17 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7-cm" CONFIG_TARGET_IMX7_CM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" # CONFIG_BOARD_EARLY_INIT_F is not set @@ -62,6 +62,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 79e4bde07036dcbc7ae53ac38e72fcc7987d9ba7..b19fd22c6abec997b9f7dc875bceb36f9baac78b 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -9,25 +9,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4400 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_CL_IOT_GATE=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y @@ -83,7 +81,6 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_DM_KEYBOARD=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index abc4d659c385e6b6235f4f3a5423345ec1220f06..388002262c8adf0cfc33d5331ba221cef7a12e34 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -7,21 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y @@ -56,7 +57,6 @@ CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 5f45e3352fbcb9d0c7b3e411319173d84f172651..8879c81949b63c32d7d1b9fd8c93e1f76ba0a17b 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -7,21 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-edimm2.2" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y @@ -56,7 +57,6 @@ CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 78334c45e74358498698a9b02baa7a1b4290a6a9..02cdeda23e57d017a3ed09430d73cf6ee4bc3900 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -7,24 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_BEACON=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y @@ -69,7 +67,6 @@ CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index f7f39b8dc63c564c0d36f4951f5e3401060d78e7..36230cf74189d55137d27dbfda2796682fa18568 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -7,24 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y @@ -57,7 +55,6 @@ CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 44ff5f84da469399b4f04d2e4f850fb258130573..c622211926f75d4e22f2a2e33fa03405fb82c53f 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -9,27 +9,25 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xff0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_VENICE=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xff8000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" @@ -72,7 +70,6 @@ CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 8fec003edd3618595e9d86730742c44e46467d7c..cb37442d3662cb06b1d026d583fd959b298669e8 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -10,26 +10,24 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x44000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_IMX8MN_BEACON_2GB_LPDDR=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -84,7 +82,6 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 5296204aad84c3822d8d83920edfbdd6c46f1b35..59cae55c88449ad0d915859cc805baba5844ecc9 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -10,25 +10,23 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x44000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BEACON=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -84,7 +82,6 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 78943dd91d38b84a2522845703e4ba9c4690be68..c10846feeeae73a67f333f5cdbacd48ffd77f2ac 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -7,25 +7,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_DDR4_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -60,7 +58,6 @@ CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 4b4a0d0d0b2847266364a56785395e47c44cb296..ae38f3479d4cb1249ba6a8df1438f3ff39564bc5 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -9,24 +9,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y @@ -62,7 +60,6 @@ CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 2c6fc16cdf56de239416fdaf1acf3a26b720cb39..0abe1370273b49d61494c2147380e4fdd69c3507 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -10,22 +10,23 @@ CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y @@ -62,7 +63,7 @@ CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set -CONFIG_SYS_I2C_MXC=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -80,9 +81,11 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index e0a038b168c95245e99428901238aabad1d13d77..5b9dc5277a46a74b01355020c35cbae3ee015c1b 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -9,20 +9,21 @@ CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x600000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MQ_CM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y @@ -46,7 +47,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 50132c833e238cb11bfbdb0f791fada13b9eb933..62fe6f15236bf0e0667ad36dc3d4a70d1c5dcd12 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -3,18 +3,22 @@ CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x600000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MQ_EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -38,7 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -48,11 +52,13 @@ CONFIG_PHY=y CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y CONFIG_DM_RESET=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 3a1b60b8a3953b9db9f865683247d5b8f5b1ecb0..911c3391db5a51d8ae06b8834c92c58117786331 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -4,17 +4,21 @@ CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x600000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MQ_PHANBELL=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" CONFIG_SD_BOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y @@ -44,17 +48,19 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y CONFIG_DM_RESET=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index a181d37ff751a3ee5bd7e73a7f5e5ff33112a743..01ba6cffb91664e776ea59063098239c871639f1 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -8,25 +8,25 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MALLOC_LEN=0x2400000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" CONFIG_SPL_TEXT_BASE=0x100000 CONFIG_TARGET_IMX8QM_MEK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y @@ -50,6 +50,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y CONFIG_CLK_IMX8=y diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index 33556356cf947e396e73f5bb24e1e364d7da7723..bf7b1f134d48f218dc9da566dd4ac13f0c67a324 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -7,23 +7,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MALLOC_LEN=0x2800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8qm-rom7720-a1" CONFIG_TARGET_IMX8QM_ROM7720_A1=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/advantech/imx8qm_rom7720_a1/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y @@ -46,6 +46,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 19e7076f8ca7ee51b3d04ccce8d507250c8a9ad8..37b6a8259ea86f61440b170fa15fe3df71d2dee2 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -8,25 +8,25 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MALLOC_LEN=0x2400000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" CONFIG_SPL_TEXT_BASE=0x100000 CONFIG_TARGET_IMX8QXP_MEK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y @@ -50,6 +50,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index 2a97c6dc44724947c78f2ecbf5df28df4463a7ed..f156100888044442407fe1677d86566e28d61d26 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -7,16 +7,19 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_IMX_CONFIG="" +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk" CONFIG_SPL_TEXT_BASE=0x22020000 CONFIG_TARGET_IMX8ULP_EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80480000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 @@ -37,6 +40,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_IMX_RGPIO2P=y diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index e53c5caa88c3b1faa0ead2ee91a675db0766eeba..450f715eedbb4168db31743d4f68d59642d0aacf 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -7,15 +7,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk" CONFIG_SPL_TEXT_BASE=0x20209000 CONFIG_TARGET_IMXRT1020_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x20209000 CONFIG_SD_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 6b302a7b82936b0c9e8821b0da454f967a65f370..94363cf6ea93eef4a5d069c2c70259151bf8845c 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -9,15 +9,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" CONFIG_SPL_TEXT_BASE=0x20209000 CONFIG_TARGET_IMXRT1050_EVK=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x20209000 CONFIG_SD_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index f9905d74e547b451780d7203dd5887e11a378158..f81120b119755427b462d02a134f853e314e2cba 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -15,6 +15,9 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index ebe52681a850b0cfd99bdad18cfd9191efaa39e5..d5d2dc32c9356882be65c779675c85412cd282be 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -14,4 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index ad6f944216b415ea08122dd82f3f6af323efec5e..bd6c45bd661adff7bfb2a2d88109fb02c5ece10a 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -16,5 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index b309d7f7b316782b06d3678aa3a9e17d5dcdbcdb..4485f9302364e1e303156a708297d49fdbb71084 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -14,4 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 6141e15179d6e1f364c4437a6c8f6d092c95ce8d..cd62a9d8eab44ca9187949188e15694183ddfb37 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2" CONFIG_IDENT_STRING=" IS v2" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y @@ -43,6 +46,10 @@ CONFIG_ENV_ADDR=0x70000 CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index 378bf936d7378014e1b106ca5f7bfc1db928b421..e0ded8857e407e23df69dca10390500c1eb7dc8a 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -5,6 +5,8 @@ CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM720T=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 +CONFIG_SYS_MALLOC_LEN=0x28000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index 4ec2961a4ecbd774f5bbb144f200f349388647b1..2283bf6e1dcce34650c0c3d44531ec0f7fdba260 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -5,6 +5,8 @@ CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM920T=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 +CONFIG_SYS_MALLOC_LEN=0x28000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index 012d346500f5c1fc04d59985862739f27dc954dc..63128d0a8f984221e0b9d50c74599d7f2f6573ba 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -5,6 +5,8 @@ CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM926EJ_S=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 +CONFIG_SYS_MALLOC_LEN=0x28000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 1868c7024f0ffea847729c4f8b5686a3047f4f6b..043cc54999404f6e22534a6b92ab0426952c395a 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -5,6 +5,8 @@ CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM946ES=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 +CONFIG_SYS_MALLOC_LEN=0x28000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index 824308c44b7f79e08ed3985366f81ee1270805e0..d72e380b924494c4d840fea7eb9fa9bbe245ec50 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -6,6 +6,8 @@ CONFIG_CM1136=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x22000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 93479e5d14341624457d714072006bfb64816859..184fcc4603ccea5d66f2d45cede35d4f109f1e85 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -6,6 +6,8 @@ CONFIG_CM920T=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x22000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index 5ee90cd27e95c33aced219057bca683610a27aed..0bd4d63906572234775afddb6310b880eac31a9a 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -6,6 +6,8 @@ CONFIG_CM926EJ_S=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x22000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index 61c902093f304c6cdd8d95839c05cb296bf0ab3f..d532eb68c8b9d2415de43116f3d89034227166c8 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -6,6 +6,8 @@ CONFIG_CM946ES=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x22000 +CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..72ee5c83f11b74fdc50f3bb79530fc82407e9486 --- /dev/null +++ b/configs/iot2050_defconfig @@ -0,0 +1,136 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM6=y +CONFIG_TARGET_IOT2050_A53=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_ENV_OFFSET_REDUND=0x6a0000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTSTAGE=y +CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SYS_PROMPT="IOT2050> " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl" +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_LED=y +CONFIG_SPL_LED=y +CONFIG_LED_GPIO=y +CONFIG_SPL_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +CONFIG_PCI=y +CONFIG_PCI_KEYSTONE=y +CONFIG_PHY=y +CONFIG_AM654_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_K3_RTI=y +CONFIG_WDT_K3_RTI_LOAD_FW=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig index e58b98dcdb2d15d779d8cb481949c458fa759af4..e7d2cb3f2620d6a7d5970343a41b73308b2decb6 100644 --- a/configs/iot_devkit_defconfig +++ b/configs/iot_devkit_defconfig @@ -6,9 +6,11 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_TARGET_IOT_DEVKIT=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x10000 CONFIG_DEFAULT_DEVICE_TREE="iot_devkit" CONFIG_SYS_CLK_FREQ=16000000 CONFIG_LOCALVERSION="-iotdk-1.0" +CONFIG_SYS_LOAD_ADDR=0x30000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_PROMPT="IoTDK# " # CONFIG_CMD_BOOTD is not set diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 81cc4031682c8a1856b74c098bfe18810705a71b..02e53d01f1230fe1ea7ebfafda40cf2b6b4aee7b 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -9,19 +9,20 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J7200_A72_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x6A0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -45,7 +46,6 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 5cbc043dc5fe340461b95709d80a5678ac97423a..f13ece9d0b472ec7b02d733d8529da58c600be93 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -8,18 +8,19 @@ CONFIG_SOC_K3_J721E=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J7200_R5_EVM=y CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 @@ -42,7 +43,6 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index ea83fec69f1c30681e9221163f72a1ac9ccb3c9c..df1b850f42b28821854e55be73dc634c6ffe698e 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -9,19 +9,20 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_A72_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x6A0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -42,7 +43,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index b5fd3bf23734430be1a4cb720b0df6f12e0975e7..1a58135da4793e95a1d06de5d61a318adc22666c 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -8,18 +8,19 @@ CONFIG_SOC_K3_J721E=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J721E_R5_EVM=y CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 @@ -40,7 +41,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index a424072c7850859775952b6641d71d50a5dd650b..65b99085aef8c42a3388a2a5b45f058100de2505 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -9,18 +9,19 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_A72_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x700000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -40,7 +41,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index 3a8e0b1cd15b4443f247e620edfd7d46eb06a1ae..eb3a600d4072b07af121e0fa543f0bf32c24613c 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -9,19 +9,20 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_R5_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board" CONFIG_SPL_TEXT_BASE=0x41c00000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x700000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 @@ -38,7 +39,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 1e252eaa1ee669ffdb5c47a4eb63a752d621e888..0ff666b2ee5c0e5b3e54d0d7ebd08297073414ee 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -9,6 +9,9 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 31acb2770fb7799f1bb6902c75add5fe625896bc..50e85be9dca498ca8f32e034b0a1ddc4eaabecfe 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_JETSON_TK1=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 1bd02ce3f277cb09d12bf0424cf54befca503cbf..6eccf6d1e8d62815d895abc2b9d0d00b84047984 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -11,12 +13,13 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2E_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -30,6 +33,9 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -50,9 +56,11 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_TI_EDMA3=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index b59cf2bdae2b7b4de4436b9e7d33b4a5e00cd389..0978b1b011a993f7df8f6f50b8a9d7f3acd415ac 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -10,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2E_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y @@ -17,6 +19,9 @@ CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -35,9 +40,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_TI_EDMA3=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 000205e0205fb55cbc9be47c629df9623ca7ade5..aed3385460e90f2fef228f13563dff828f8d5ed1 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -10,12 +12,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2G_EVM=y CONFIG_ENV_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -28,6 +31,9 @@ CONFIG_SPL_NAND_BASE=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -51,8 +57,10 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_DFU_MMC=y +CONFIG_TI_EDMA3=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 528b95f680a3dadfd14c958618ecdb318ad1f6ae..ffa41decc44442b839041e77eb3784eec094ceb4 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -9,6 +10,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2G_EVM=y CONFIG_ENV_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y @@ -16,6 +18,9 @@ CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -37,8 +42,11 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM=y CONFIG_DFU_MMC=y +CONFIG_TI_EDMA3=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 384063fee61f6875bb1f11bd65d2f65d05acb10a..c7e6f7e38fc593f7a84b3a5453c0cb9dec1c3c65 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -11,12 +13,13 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2HK_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -30,6 +33,9 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -50,9 +56,11 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_TI_EDMA3=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 030dd47c19144494a6a1177cc9274e97983e000b..1c0132e8a29661be105bb76bf08c4ce51700cf18 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -10,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2HK_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y @@ -17,6 +19,9 @@ CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -35,9 +40,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_TI_EDMA3=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index f0f2ff1c9c4c40373387798220110f225ffa4525..7324d7a29878119dab1107baf34fdeb95778b6bb 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -11,12 +13,13 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2L_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set @@ -30,6 +33,9 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -50,9 +56,11 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_TI_EDMA3=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 096d65b302e05375faa65d93789defd5036c7c79..e46efc781ceb5e719e5a16eef0f72c03c67a3747 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y @@ -10,12 +11,16 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_K2L_EVM=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set @@ -36,9 +41,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_TI_EDMA3=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index c564086704c14de290e5f4c3fa21178793ff82b1..6b9df2a230e77ba050d05a4b8643fc5626b95bec 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 4c63686ef263fc33e18ad2184d06c3705e903df7..47b2b34bf0faeea0677e432894e220d8befc2fd6 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 1e44e2b5c1737d7f766ffdfdb371821225956dcf..1caadb0c8280823e23ccbb57e042f0bcad9b5da7 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index eb6202ba5ca7e7799f633a813370b8050094399c..c852f7f3f9eddf4de9b16592b315f440dfb13226 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim2" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index e8809a83808835f2aa2322d298ba189cc5cd785e..a225a564b2803501053c11756facbc2d6b308cb5 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index 8eb52c0f69d4c4321d3a7721962f8dd727a516d3..9d94c31891c6fff92279e39c9a91669ce2017b06 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim3l" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 103ef54e04da85dd900651d8ddfdd0a74ba9305a..5565635ab1397cea6e033fab50c9197a2b3113d4 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index e00d14c4933aa87af398b3a821a4532b59720095..d6624dd9551d54184e800dc8c5d150bdff030038 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" @@ -24,6 +26,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -43,6 +48,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x0 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index 490538d7915699510d9742d6f02fc4211b32fd7e..bf696cd2db28883c99c4c1a59cd42f8f4393a0f3 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" @@ -24,6 +26,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -43,6 +48,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x0 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index 1f14a9b0fe93b60ccdaad297f3c559423722e93b..0731bb5572930fa8c38b831b89140b4fb7bb9c28 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" @@ -25,6 +27,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -44,6 +49,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x0 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 102af968397f2c97132dd10b086828eeb0832ca5..dafd5dacbcea5cbcacdc85740ff9929d6f3e4f5a 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -44,6 +44,7 @@ CONFIG_ENV_ADDR_REDUND=0xebf00000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index a54808df6078c277763e38121d6737b5432a6079..9a56f44c7cc6823c76741cae1d7ab2176748fb52 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -156,6 +156,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -169,6 +170,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y # CONFIG_CMD_PINMUX is not set @@ -189,6 +193,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 51f0f87193afb2771d47d67a60242e63ba645b36..12aa23095cced530a1ab41668cd1e002e66908c0 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -14,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_ENV_OFFSET_REDUND=0xD0000 CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" @@ -28,6 +30,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -47,6 +52,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x0 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 5138a5680c8759e36e9452e5033017cea43d1efd..e1bce4a7d07454dda3bc114d1373614dca259749 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -127,6 +127,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -140,6 +141,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y @@ -159,6 +163,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 9b98034e88963c723744fa2fd6d2b3a7c8ef141c..06b2d1fb571d65b46fc40114cb495266134d1497 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -14,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_ENV_OFFSET_REDUND=0xD0000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" @@ -28,6 +30,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -47,6 +52,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x0 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 80f74eac8cfe5fc5d461f08552b9b3815c291a8e..75ab1ae1a7871bba9ae9eae4400438292282b730 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -139,6 +139,7 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -152,6 +153,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y @@ -171,6 +174,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 0482634ead0df70d4db2cd93d91d0c78b3514d26..be5034f4d70f400abca6bfb4754b910f5dc12c53 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -119,6 +119,7 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -132,6 +133,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -150,6 +153,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig index e0b0ad61d12f81c90415219ba9ae49198858417e..a528bf5cfe90485b3955b56ec951e7cf2c3c89a2 100644 --- a/configs/kmsuse2_defconfig +++ b/configs/kmsuse2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -15,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_ENV_OFFSET_REDUND=0xD0000 CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" @@ -29,6 +31,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -48,6 +53,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x0 +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index d98b2eb19cc74241f6e56fba5aba534704f80247..315ba867b5f43f57a3cfdc6e4331fb307c2f74cd 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -118,6 +118,7 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" @@ -132,6 +133,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y CONFIG_CMD_DHCP=y @@ -152,6 +155,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 665adee38bac4415672f42a87a560939832a42a1..4c5509bfc1295067d964ed129be3b6c5caa92fc8 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -139,6 +139,7 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -152,6 +153,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -170,6 +173,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 228078a28321cfe8db805beeeea6c44162c9ee98..b254879741b496d71f2138619adc8cf6a575c3f2 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Koelsch" CONFIG_R8A7791=y CONFIG_TARGET_KOELSCH=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index a9038789cb92f9881ab90ecdb2d206a2f2d65682..4e25dafaaffff6a2b953c8b0b1aef47d97cdde7e 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -7,19 +7,21 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x3e0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" CONFIG_SPL_TEXT_BASE=0x18010000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -31,7 +33,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 CONFIG_CMD_ASKENV=y @@ -60,8 +62,9 @@ CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 4a2d8afe4ee38f255cedacedb40422e9125f883b..b8f6d8ad81ab3353b60c6a34f0fbebeb3575ecd0 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -5,12 +5,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_TARGET_KP_IMX53=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" CONFIG_ENV_OFFSET_REDUND=0x102000 # CONFIG_CMD_BMODE is not set +CONFIG_SYS_LOAD_ADDR=0x72000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR="." @@ -38,6 +39,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PHYLIB=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 96c1061683bdc5c8d5f3db2a40aaa5742683c30b..85fdfad834e67649c2bca795093a729631119704 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -11,18 +11,15 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6QDL=y CONFIG_MX6_DDRCAL=y CONFIG_TARGET_KP_IMX6Q_TPC=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x102000 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index c051307939df9c803834f53aa99b36393f38c9ee..00c156409ff984ce983f31f675a6d2afdd11ab3f 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y @@ -15,6 +17,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x60800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig index 8a51bf0026b7eae8839fb950cac2eeccb79f9fdb..af611dbe081cadc76b04e88f53fa282b5bcddde3 100644 --- a/configs/kzm9g_defconfig +++ b/configs/kzm9g_defconfig @@ -6,8 +6,10 @@ CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x60000 CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT" CONFIG_TARGET_KZM9G=y +CONFIG_SYS_LOAD_ADDR=0x43000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200" @@ -24,6 +26,8 @@ CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x40000 CONFIG_VERSION_VARIABLE=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SH=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index ab6b208388e4a87bfaf6b08803472cb3cd52df2c..2d323ed0f82be56aeeb24cd7a8ea47916f887e21 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Lager" CONFIG_R8A7790=y CONFIG_TARGET_LAGER=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index a3afb1d81bdb1866bcdbb925fb345782b594ca0d..0f8a795d2a1e4996c5920b490149e83e0b74c327 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 200d9ac2ef1e04b2875cc84fdd71dddd5dd62221..52bddd5996d7d7699f158dcfe0301e8fe7d8cecb 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -1,10 +1,13 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 CONFIG_TARGET_LEGOEV3=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x110000 CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3" +CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n" @@ -34,6 +37,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_NET is not set CONFIG_DM=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index c494b581fb34dd642566ebf165d4f6daa3a3c15e..fa4427a815a93fdfc5084055ea15031b50f99629 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-ac" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 8beb850ae24cab42cd93a42a6b41e64169644815..b729308c8eeb25877741c7e4b378f3a8b4d4cb02 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index be9501052fc3c195012f577c3610c3de7dab275e..9f8a914bb7412b0c44b88dfcebb9436a7053d3f2 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -12,6 +12,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc-v2" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index 825add43875a700db34f4eb75878803f38321843..bde2bb877ca628db104b2c09916f865a65b43985 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-s905d-pc" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index 49e7d85ac76d9d4a38848ed8139f0f289587cb90..536f9e8d121f3edf638226741afe79a952c039db 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -12,6 +12,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-s912-pc" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index cf2f204ad461c62a4a4eed61e6045dd8416170e4..b217f83c36ca7c25c4be091bd48d1b7be7b54d13 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -1,20 +1,25 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 CONFIG_SPL=y CONFIG_ARCH_MTMIPS=y CONFIG_SOC_MT7628=y CONFIG_BOARD_LINKIT_SMART_7688=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 5f7d1018143a5fff44c616a415053de5eaaf1640..e214cf5707fe8961e2cb13b257a1664aae1e65d6 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -14,8 +15,9 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index a04cfdbe15f5a66aca902ddfa2e806c7a09a5357..c8f3ee3fbd245079aefb5bdcc555ee51b3900269 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -11,14 +11,14 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6UL=y CONFIG_TARGET_LITEBOARD=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=1 CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb" CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 79ac94a23348bf4640dfa00022b3067c720e12d2..fa0189429e875ecbe8fc2d1829556d732a8f2b7d 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" CONFIG_FSL_LS_PPA=y @@ -17,7 +18,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -41,6 +41,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 7360a13cb559c40637d3510d405db7edfd4bf000..171a982c9085a3a17cf37c9a06dc38c645d6590b 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" CONFIG_QSPI_AHB_INIT=y @@ -41,6 +42,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 3844691403b32d143d349c62d528c65796023a5e..d21525d13afd538971d9f4953fb657ce4f71be48 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" CONFIG_FSL_LS_PPA=y @@ -16,7 +17,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 9046ec7617db4f03609199fa57535e629a6c73b0..67c6f2aa67a8dea23ba62eefd1ef41c7ac6a6164 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" CONFIG_QSPI_AHB_INIT=y @@ -38,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 9d3572724879db4b113b293d8b00c5b62672d9ab..53fb7517dde4710626d480dd4c35a35d3afaf359 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_FSL_LS_PPA=y @@ -15,7 +16,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -38,6 +38,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 853014e76f8dd88626fda4c815c8fb69eb283914..637fe862a0f72f755e73571fb9251eb54f190476 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x1D0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_FSL_LS_PPA=y @@ -16,7 +17,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -43,6 +43,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index ca055570ea50971db39c3e0e206149c807cbf161..e11d6f8437545185c171097af688a2cff6dd161e 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -38,6 +39,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 3282756be0ef2d07a77628a1d71473550dbcb733..b75103651580e9f33def1530050550f324444fe4 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x1D0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -42,6 +43,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 2124716d77c5b09f0be60716bc3a152429037457..0903650c18d6a2449c42b61e67603a8fa955cac6 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" CONFIG_FSL_LS_PPA=y @@ -17,7 +18,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -26,8 +26,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y @@ -54,6 +57,8 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index ec92358b008215b229478c7f6442505d1d61070f..02eecf0d13f34144fc0d009c38321fc4a1eb163c 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" CONFIG_QSPI_AHB_INIT=y @@ -24,8 +25,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y @@ -42,6 +46,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 82a698f6e336628b8a3b6b788d7c9c0a2be02590..fad0c1c3bee16a7b7515ab80d816487b24eb6834 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" CONFIG_QSPI_AHB_INIT=y @@ -26,8 +27,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y @@ -54,6 +58,8 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index da45a3d9cfa473cef15553a3f9b0665a882ef9bb..e190fbddb0ddb3e0b28063d4d46d27929784647d 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_FSL_LS_PPA=y @@ -16,7 +17,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -42,6 +42,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 830e7868c046f774500b7aa5735d17242cddeb5c..7f72a7b14238ff79b4dc88a40a736a6f7699a883 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_FSL_LS_PPA=y @@ -17,7 +18,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -44,6 +44,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index fd1f6fa62fe8ca6279a5ba98a14d56f0e058b215..dcde6ca2a79a916a21e30dd048be9ab38a6519b3 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_QSPI_AHB_INIT=y @@ -41,6 +42,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index c83248c304003f104ad3ca181b0e77191a53f7b5..390ccb5aa21704e0d9a643391fbe5d87ff443ab1 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_QSPI_AHB_INIT=y @@ -43,6 +44,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 131026ca4d4628dd1312bc8b7f4fa070971e83c4..10aeaf36f1a38fdca01cfd11e2ca2a45de2d2b8b 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -5,14 +5,21 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" CONFIG_AHCI=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_QSPI_BOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -31,6 +38,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 7c198988b8891940a4c2cf0dc5627851eb648b1b..742cfaa787ad34db1ab57ffd1b1e1af6da4853f3 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -4,20 +4,31 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_AHCI=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -37,6 +48,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index cf64f0fc76218b86e9cd36d5f0d618615ae6dad4..fea76a0d093fb666cf9477d762ec1f245fecb933 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,10 +7,15 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -18,10 +24,12 @@ CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -43,7 +51,13 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index cb63fb65e82ab2e9e61407634dc204bbb2f2cd11..59790da8a75477c755f415322b6bfaeab902a0df 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,10 +7,15 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -19,10 +25,12 @@ CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -44,7 +52,13 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 072a1e6c7397fd1b7766a49b1e01014e822c50e7..6fff54b8c58183296e34ef52ce423392f5cce0c2 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -8,36 +10,46 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -60,8 +72,14 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index e9d29f4314497f704b277aeba40b8e742697a43d..734e9cd98522a3e4766d763fc04125a400895a24 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,11 +7,16 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -19,10 +25,12 @@ CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -41,8 +49,14 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 4c4050a403c2787f42a5ccae948859b106796f7e..ae96127392c447f32c26a33c7f914b916a44bb2f 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,10 +7,15 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -18,10 +24,12 @@ CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -43,8 +51,14 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 3378fc1e787ea7b69df955c20915bdb49b0ca8ec..e3b506dc0e2e131c9af14aab2bb1bece8ba51eed 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,10 +7,15 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -19,10 +25,12 @@ CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -44,8 +52,14 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 69a02a4af906015963370c4c2b6160a3e4120fb4..31fd7866b25d9961920f023ad01eac92684849ca 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=1 @@ -7,23 +8,29 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -45,7 +52,12 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 50ba009d70fddf985b9e05fc7278a84d9f822525..c7dd54c4b79f7389a2e14742300a1c9da39c88da 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -8,34 +10,44 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -58,8 +70,14 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 0c74e9b513433b6959b63239ed0abeb838725454..a5e64fab17b9fdd68740e2a12922cefc02ea6e27 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -8,33 +10,43 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -57,7 +69,12 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 6103ab32a49e1d353df4bbdc3240d8b9e6b0b893..9645ad0d5d72c6eb8900cc8acc4497e6ff6b0ba9 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -5,19 +5,25 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y @@ -32,6 +38,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 8cc0360ae7c5b7b46f3ad0a6663d96fe41489bed..f76e56735518ef9a4e92665aa5a18a9c1d9d9342 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -6,29 +6,39 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y @@ -43,6 +53,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index d2d2fcc1ba1b016ac5a6025b48c7b3f69de73215..8abf5a6da9af895cafd4195a181044a777651aa1 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,11 +7,16 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -21,8 +27,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -36,6 +44,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index fa20ee8c0e96176fd6e6469ed85d3b01cc30cae5..b0883c554e0b09ed03e26956ff5214edd3c59ec5 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,10 +7,15 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -20,8 +26,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -38,6 +46,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 11d210846c4abf35f52afd82d549a815ee477586..8a38382f6935e69a3ddaa726c775ee08aefa0cd1 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -6,10 +7,15 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -22,8 +28,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -40,6 +48,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 50337a874f189d6828acdb20eadfce187725f91a..00d98717505f70ba1f267faf700a7d1afef79aa5 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=1 @@ -7,15 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -24,7 +29,9 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -41,6 +48,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 106f8ecad5dd8ef9640dc6240827602431d52475..561a39044a8720fa1133bb1a55a0bf6c644c32ee 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -8,34 +10,44 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -52,6 +64,9 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 67b83b7739cf47d428ecf942dae576cf45a56c88..3bf93ddf012a0c6471939ebb000ed500ea7e7655 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -8,19 +10,27 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,15 +38,17 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -53,6 +65,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index c82c29781ac6af041acb678c34bcfff37fe496b7..624fba9dfe1bf34d98df86613bdb7ff7db516efd 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -8,19 +10,27 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -28,14 +38,16 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -52,6 +64,9 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 5b60c4af8d9b49128df774bff39b786512110e53..6dc1b7ff727825dca9246717181a05c166f3f2a2 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" CONFIG_FSPI_AHB_EN_4BYTE=y @@ -22,7 +24,9 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -40,11 +44,12 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 311cfe3c7a2bf3f10eaf5651faf811f1ca5e0aba..a0a277c87129ba04e08c80b860007f7a44de1109 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y @@ -9,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" CONFIG_FSPI_AHB_EN_4BYTE=y @@ -23,7 +25,9 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -46,11 +50,12 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 6805f5eaaa18982956b1c4a569ee25534d38701c..2ae107704dcf5ecbb69768bc11689822c9eb7cab 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 @@ -8,6 +9,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart" CONFIG_FSPI_AHB_EN_4BYTE=y @@ -23,7 +25,9 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -46,11 +50,12 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 7eecbae13e751710abbc8adc43173db599202cba..995cfa66f10e3f688373a4c73397b0bb604f8ae5 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" CONFIG_FSPI_AHB_EN_4BYTE=y @@ -21,7 +23,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -39,11 +43,12 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 6934a597a52c0cb2052521fe8025bd8299c64e52..9f10146fcfd683959bf4ad76764ef65808584253 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y @@ -9,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" CONFIG_FSPI_AHB_EN_4BYTE=y @@ -22,7 +24,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -45,11 +49,12 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index d89f6571bd05501bd680159c34f6f73870cb5d83..4c799628603bd2e518d0741d354869f8856034ac 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -6,6 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -22,6 +27,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -40,7 +46,13 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 8e4eaf22bec6cfe5446ee4e83e3ca3f66f80969c..6df098382db970f2b681c34b16a0435295d4af3b 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -6,6 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -23,6 +28,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -41,7 +47,13 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 0bc43273e22b795c640da0bb23c556fc8b9d49f2..57908b43a60619bf5b932e0175a76d1761a95774 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -8,19 +8,27 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -32,12 +40,13 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -57,7 +66,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 1fbb5ea0b80ddf4ff9bc42b155a7540c23fad360..09edcd9600eb142ffe78a9e01fdce49c6beadfcf 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -6,6 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -22,6 +27,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -40,8 +46,14 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 4f7e457a36cc3f8361153be62252d4959369dd86..fbd845fbf363322f97b05d103adec7b11759864b 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -7,6 +7,11 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -15,7 +20,6 @@ CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -24,6 +28,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -42,7 +47,14 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 8e780b31cb097fb2bb4e0102a1bf4eae19d12982..ae89982b781cad316882f444b998936f955ecb0d 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -8,20 +8,28 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -33,11 +41,12 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -57,7 +66,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 2cb088cddec04a1e27ed0d129bb72262b91bdf1a..f5324114e7452de32d98ee702946bf29e69280f0 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -8,20 +8,28 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -33,10 +41,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -55,7 +64,14 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 6b908edc8688880f4a8468c98df066a622b96624..327dc8f3590e52c46475d2ac2260466b0bc89561 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -7,6 +7,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -24,6 +29,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -39,7 +45,14 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index a229001d8af801974ace28250126162a55db97d8..7855c7b287c0a033b792dffe97ce0dcb485bd5cc 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -8,6 +8,11 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -25,6 +30,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -49,7 +55,14 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 8885896f7b12d5fe23aea1b1809b8dfca28e7cb2..394ae1e2107763b1edf537a331c1fe28a2b93a0e 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y @@ -15,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -28,7 +34,12 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y +# CONFIG_DDR_SPD is not set +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 413e0c7941c7bbc1aaaa704ed054230a2f9d5fd3..cc9bc5a778e56ca868a1a54821e03c51d10ef829 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y @@ -15,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -31,7 +37,12 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_FSL_CAAM=y +# CONFIG_DDR_SPD is not set +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 2d3fe4fb6ddc3b0b4bb778cc49184d26220a9f54..8e47f81277391469c39c89323934537015378b0c 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -6,17 +6,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -27,10 +31,11 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -48,6 +53,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 7bc186a1b3048262fc30b44d300ee5d0118e9304..5b839bcc14036d322db6c109a46c19d0cf9ac38c 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -6,17 +6,25 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -29,10 +37,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -51,6 +60,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index d5864180b2204d0bf64f2067525a13d63cc9428e..fef8121da7f7d56bd1ffa363de31b134228d008e 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -6,18 +6,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -27,10 +31,11 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -49,6 +54,8 @@ CONFIG_DM=y CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index c91f9dfd5066a601b6cfa957726f8d0d9ad10ef8..a625ec753ad90214f72f760ef59deb5e5cf0c8de 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -6,18 +6,26 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -28,10 +36,11 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -50,6 +59,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index a3c17f0b9a02993622467300a81945ea763cf155..b48d5f49f1e10950d59836af4dd6a4ff5de3b818 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -5,6 +5,11 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -17,6 +22,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -30,7 +36,12 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y +# CONFIG_DDR_SPD is not set +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 58313e4ae510f9df80dfeb28e3a38a432a7ff352..f785d990c23e92d32caea47ae118ce94f3636e38 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -6,6 +6,11 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -18,6 +23,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -36,7 +42,12 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_ADDR=0x60500000 CONFIG_DM=y CONFIG_FSL_CAAM=y +# CONFIG_DDR_SPD is not set +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index b5100282dc1cf6905062fd29cd7ffefd3925287c..ebca3c79b87c394c630be191d6688646faa35eb9 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" CONFIG_FSL_USE_PCA9547_MUX=y @@ -18,6 +19,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -32,7 +34,10 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 96ab70bfaf511bbef43d7757ab26174f1ad9d8ab..6816fb3ff006c3f5579ce880406a69d356c6a0b0 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" CONFIG_FSL_USE_PCA9547_MUX=y @@ -20,6 +21,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -38,7 +40,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +# CONFIG_DDR_SPD is not set CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 1e70e37fe592e4dd2e9afa4cec0b363e86cede5b..32ed2aa108bd28330e52fc59d42a221288c4d2c6 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -6,6 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -22,6 +27,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -38,7 +44,12 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 7351e490566c949302f4990be5437859c771e5f0..240bd07596357f3fb66dddd22dfc91795da163f3 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -6,6 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -22,6 +27,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -41,7 +47,12 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index c6f8a363475b249dc1a6000faa140b2e4086e1ce..27632812bfe8e1dc616d042c6a32298d33a67281 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -6,6 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -23,6 +28,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -42,7 +48,12 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index c406d866bd0c905413d8cf43c16256411b43ffc1..597938139db4e9f2b7a8cf9d84315f426261f0af 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -6,18 +6,25 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -28,9 +35,11 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -50,7 +59,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index a088c82904d948522587c053b73279c4307ef7e7..a3ac42f41c0aaee5fcdb6a63a86b8fcbbd7645be 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -7,6 +7,11 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -23,6 +28,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -42,7 +48,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 15f8d45a25152d3d3a3e92195d1a0001c3c6203a..7bf63bbf093d029aaece09d92f64d95c13c8ac44 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -8,20 +8,27 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -34,11 +41,12 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -59,7 +67,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 3278cd2d2a802681e694375f3e6beae51707f0ce..3761aafe8a18e51a2efee5a0eeadd23b7cd87e00 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -8,20 +8,28 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -34,10 +42,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -57,7 +66,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 42d67dc7072084e2d44bd37abf3f11d71d1b8ade..8b75fe8aba81162b5e40b76a6327478f8106b623 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -7,6 +7,11 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -24,6 +29,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -40,7 +46,13 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 8ae5159f423bd5a20f977a046fdc872ce996e1dc..ff0d8ffec075b7e24169ff72808bc328f866e4ad 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -8,6 +8,11 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -25,6 +30,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -49,7 +55,13 @@ CONFIG_ENV_ADDR=0x40500000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index eeb6e939ba1393c61654fac6efa0b73b74c255fe..e5402a24a64495716047c49f8a60be6c3e1d8469 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -6,19 +6,27 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,EMMC_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -31,8 +39,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -52,7 +61,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -70,6 +83,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index edb20e7e9f8ba2c40560c19b87369fc702cf1606..cd9e3a464164162486d2a5c21d82962ba3b25a38 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FSL_LS_PPA=y @@ -12,11 +17,15 @@ CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -33,7 +42,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -52,6 +65,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 087c17bb6136605e715e07499a3304f90c6baec1..93f0e88e3a1d007cdc01eae8fbd4a01dbeffcbb9 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -5,6 +5,11 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FSL_LS_PPA=y @@ -13,11 +18,15 @@ CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -37,7 +46,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -56,6 +69,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 45ee90447da853b3743aa50c59e22ec4adfdacd2..a88baafd1e34b4b6f8202b84d7d45e36b5363694 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -7,13 +7,18 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y CONFIG_SPL_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y @@ -22,6 +27,9 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -30,12 +38,13 @@ CONFIG_MISC_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_OS_BASE=0x40980000 CONFIG_SPL_WATCHDOG=y CONFIG_CMD_SPL=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -56,7 +65,11 @@ CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -74,6 +87,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 9481e0a6abb339f356600f8536037c3c89486094..c4a9315890255c09cd6a73d8df25663a6cd26319 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -6,18 +6,25 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -28,8 +35,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -48,8 +56,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -67,6 +79,8 @@ CONFIG_FMAN_ENET=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index cd53d48b538ab2e8cd9279fcbb289d339ac59bb3..9ed24bb554cd9b22a262eeb8c3adbedfeafacdd8 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -6,19 +6,26 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_RAMBOOT_PBL=y +CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -30,8 +37,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -51,7 +59,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -69,6 +81,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index bc37699c0a607b798a6ac52ba01442999b5f2570..a14df4dc9f091a68721a183d8cd0267a0d681090 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -5,6 +5,11 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_QSPI_AHB_INIT=y @@ -18,6 +23,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -33,7 +39,11 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -52,6 +62,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 997fa1936e7a90924efabe49460067a4fdaf6d0d..85491a37e46fda5c30c8a690bad7d028089779b2 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -6,6 +6,11 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_QSPI_AHB_INIT=y @@ -19,6 +24,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_MISC_INIT_R=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -39,7 +45,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -58,6 +68,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index ef35ae4a077867b4155ee40896b24ea96196241e..bb7321ddb4073ffc2f56ffe7532a09274df134f3 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -16,13 +17,13 @@ CONFIG_AHCI=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -44,6 +45,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index eddfd40733c497106a266076a02f4d66b8af7893..70b4a70f303e71ebb84889a1a2aa194f7d39c3dc 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -18,13 +19,14 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_QSPI_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -42,6 +44,10 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 255b97739cbe6aaa435b5939b992cd3a1a71b15b..45e8d30374f74efe54846c0d83b8387c30319ca2 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -19,13 +20,14 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_QSPI_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -45,6 +47,10 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 10e1fecee236cc2b7985fd76775903fb236cef74..20efb7510714ce138d72bbaadc796af9f30099c4 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -9,19 +9,19 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" @@ -31,9 +31,10 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -55,6 +56,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index a8023113a0930ca4793af819160b98609fa810b0..e724e8be0de90ce59f5e71a2cc25b5305d9d20f7 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -9,13 +9,14 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y @@ -34,8 +35,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -55,6 +57,10 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index a2d0d6da57b9c0e40e9e3ec80361aaabd56d3a59..1b32f1f541167d2254acf4e9c36e5a17576e4ac9 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -21,13 +22,13 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -54,11 +55,14 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index dae51c4e70cbe7b8e63331764b13df0df46280d4..5af7d53c47647dc5932452812b3fc5a9cebda558 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -18,7 +19,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_QSPI_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set @@ -26,6 +27,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -44,6 +46,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_MXC_I2C1_SPEED=40000000 +CONFIG_SYS_MXC_I2C2_SPEED=40000000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 6032f6ca8b1180bffee1371f196263324ef8f24c..1133dde4dd32a243f1b3d743f9e80e759ba656b5 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -19,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_QSPI_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set @@ -27,6 +28,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -47,6 +49,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_MXC_I2C1_SPEED=40000000 +CONFIG_SYS_MXC_I2C2_SPEED=40000000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index b7c72cb3baf6e74fa5182fcc587e7d723560fcd1..7301a09b4dfc71d2a0b3451c28c5edf8b2a3d634 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -9,13 +9,14 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y @@ -34,8 +35,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -56,6 +58,12 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SCSI_AHCI=y # CONFIG_SPL_BLK is not set +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_MXC_I2C1_SPEED=40000000 +CONFIG_SYS_MXC_I2C2_SPEED=40000000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 28affca58ba0a6d0ba3faf980260c53b7683050b..17c4c6a794d5cbc08c2f5d7effdc3e1fc304049a 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -9,13 +9,14 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y @@ -35,8 +36,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -57,6 +59,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_MXC_I2C1_SPEED=40000000 +CONFIG_SYS_MXC_I2C2_SPEED=40000000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 69a3cef7a4063e75427506100da20f8072bdf052..dca0cf6930564d2a2ddf916dca3a3bf7f7afdaa2 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -20,7 +21,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set @@ -28,6 +28,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -45,11 +46,13 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 794908962526e4ce53e5abb712c3243af5bbfad5..eeb45cee941428aa51e5fa40d0d7e12c541f094a 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -21,7 +22,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set @@ -29,6 +29,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y @@ -51,11 +52,13 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index fcbd732dd67e51e8fb40b1fcd2019e8e4df6d144..67c8481268d4ad080c4630724658aa91f5e00702 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y @@ -20,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -36,6 +39,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 3a457a72d7a8d63efd500adf83b735bdd396759e..61a073dc153fa13260fb13d3c76aab304af46242 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y @@ -20,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -39,6 +42,11 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index e4c7a301633e9c9f1fc9d9ce8071e592148586d3..3976284ac962da6aca299a9e4fa1ead60cd47b5c 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -7,10 +7,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y @@ -25,10 +26,12 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -50,6 +53,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 0b0e673816af692ce9c8e9578fb8c3e0e33e764f..51c15637d4fee8cd0c22ee39c8622791502b72df 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_AHCI=y @@ -13,7 +14,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -21,6 +21,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,6 +43,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 29df680d0604e1647b6122127b80edc8d87a2059..ff953a7bbe4beabb70eb822f634b6ad8da7efef9 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -7,19 +7,19 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -29,8 +29,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y @@ -48,6 +49,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 365ee87bdbc55413936cc3c1d780bbfbf0e6ac8a..6706aa8474174187297331d4d318b53f0fef5aa9 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y @@ -21,6 +22,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -36,6 +39,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index cb46f4e4bbcd3fdbff64f7114fa6e73a4e5a70bf..5d079473a23f687e36b84d79be359bdd43d47bf8 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y @@ -21,6 +22,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -39,6 +42,11 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index d371fa5e69b2d87d5451ea98db72b5501ac04be5..cd2cab4a08d5bce127a0dbbf64071f3accb95ce2 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -7,10 +7,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y @@ -26,11 +27,13 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -49,6 +52,11 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 26692b2e73e78b7008d5cb53a17b231e9523cd32..5f7b45d686591f2e0433993a5757ef68b09c4074 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_LS_PPA=y @@ -22,6 +23,7 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -39,6 +41,12 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 113f6a4139fb6f028408698bec6f6b9c257344a7..72115712a27cdb767140faa5fe2fb01247f1658f 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -24,6 +25,8 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -49,11 +52,14 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index bd16602413f9aa40aaa260db9852e76bf4e2e601..1a4f70975ed500dab7fedc9b635bf02c1a4ea1cb 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_FSL_USE_PCA9547_MUX=y @@ -20,6 +21,7 @@ CONFIG_BOOTDELAY=10 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -35,6 +37,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 3a426031b91868c043016386d1c8715bf359c7c4..ef27812f90c0c271cdab3c8c39f366dad5581ade 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_FSL_USE_PCA9547_MUX=y @@ -23,6 +24,7 @@ CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -42,6 +44,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 1799c09fbfb8db6d9023f95068db88a5f8c47ec9..daf459d136c4a5198c5cd6b6f71da0694f887b0e 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_FSL_USE_PCA9547_MUX=y @@ -25,6 +26,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -40,11 +43,14 @@ CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index cfd3df430f829477d35f845ae59ef3252f87d8b6..16d373c4b46302245415cc7ed04369bbe38d34b5 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_FSL_USE_PCA9547_MUX=y @@ -26,6 +27,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -47,11 +50,14 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DDR_CLK_FREQ=133333333 +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 79f5960e71d20ca5f8eadbb4f5ee40606fa82fa6..471b17e2efb3bbaf4091e8b3ae0c4e49ddd31895 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2" CONFIG_IDENT_STRING=" LS-CHLv2" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_API=y CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 08405a1fc761b782fe86da39e2d3b0921a73cebb..4188c3264f23894b279433744198c23f2667ad49 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl" CONFIG_IDENT_STRING=" LS-XHL" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_API=y CONFIG_SYS_EXTRA_OPTIONS="LSXHL" CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 91fba1961826d5838bc4f188d39f83b6b85024a5..ff2bce0c233a56661e298f7c12d7e3279315211d 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2160AQDS=y CONFIG_TFABOOT=y @@ -7,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -25,6 +27,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -41,11 +45,14 @@ CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index d52063c7a872550ed93af258857a70e72bd60c8f..06f0797f38bbc72a5097668a44b3fff3fe8ff3d1 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2160AQDS=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -27,6 +29,8 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -48,11 +52,14 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 94e103c5d1dd6bdafe1412df440679a63ed3abbb..d603c32ed6221e761aa6c74cbbf1c5f73fa3d58a 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2160ARDB=y CONFIG_TFABOOT=y @@ -7,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -25,6 +27,8 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -39,9 +43,12 @@ CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index d09bcde92e740b63409cb7a9c96c54e007f1001f..e763fa623a2d478f787fa0a1569430290c273b5e 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2160ARDB=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -27,6 +29,8 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -47,9 +51,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 93b1e49cf2d0f7415a90240bb2321bf71bd54449..222a8c522e78c8f84858e22ff7bb0af7bc8dfd9a 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2160ARDB=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_FSL_USE_PCA9547_MUX=y @@ -28,6 +30,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -47,9 +51,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 7ade20205c6d74ff3310d9744b4fe2996192d43c..f91067d54744cf9aa391ad08b0a0839914d9321f 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2162AQDS=y CONFIG_TFABOOT=y @@ -7,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -23,8 +25,11 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -42,12 +47,15 @@ CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 2724f045ed6304fe0c4450fc40881f5e9b77fd36..10262aae6885f9013fb4eea5aae9c74a50068422 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2162AQDS=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -25,8 +27,11 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -49,12 +54,15 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index fa2a02753f47952069455cabb1243bed4376905b..962323833027acbe1b7b70882b860beeb0c598b6 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2162AQDS=y CONFIG_TFABOOT=y @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_FSL_USE_PCA9547_MUX=y @@ -26,8 +28,11 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y +CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -50,12 +55,15 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DYNAMIC_DDR_CLK_FREQ=y +CONFIG_DDR_ECC=y +CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 505dd078b0c95725803cb9678bb98bd4d054f483..a0fceb3573026df78439b800b14b868fcd1b4ad0 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -9,19 +9,23 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_TARGET_M53MENLO=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo" CONFIG_SPL_TEXT_BASE=0x70008000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x180000 # CONFIG_CMD_BMODE is not set +CONFIG_SYS_LOAD_ADDR=0x70800000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc0,115200" @@ -66,6 +70,9 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index d1c63c2fd42fbf9d05de0599e7daa11cabd8b5bc..a6fe5c1bcacdf02f49d08f37188148a46efc3232 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -2,9 +2,11 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mti,malta" CONFIG_TARGET_MALTA=y CONFIG_CPU_MIPS64_R2=y +CONFIG_SYS_LOAD_ADDR=0xffffffff81000000 # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 5b51a3755d00cd74b77343dc4edb6dae6193c082..909b3647f717fb398b48673e7d71ac91b075d667 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -2,11 +2,13 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mti,malta" CONFIG_TARGET_MALTA=y CONFIG_BUILD_TARGET="u-boot-swap.bin" CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R2=y +CONFIG_SYS_LOAD_ADDR=0xffffffff81000000 # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 756ed8aba7346409f43f8edfc3bcaea5c63d01d8..0af46171053364c514652fcf39908113bc25b5a5 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -2,8 +2,10 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xBE000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mti,malta" CONFIG_TARGET_MALTA=y +CONFIG_SYS_LOAD_ADDR=0x81000000 # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 384bb2ff56fd4da56fdee65d33f5726acfe62b6d..1564e922516ba89cd72122867f4a175a5698a9f6 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -2,10 +2,12 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xBE000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mti,malta" CONFIG_TARGET_MALTA=y CONFIG_BUILD_TARGET="u-boot-swap.bin" CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_SYS_LOAD_ADDR=0x81000000 # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 62f0b2f1c2a500155dba3e546ec308e665361e95..8e0aa045c82a6e0eca1e8b268ac71c5e6e2ddca9 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -5,12 +5,16 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" CONFIG_MX6Q=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard" CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -29,6 +33,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index f4e493cc928501133756eca2b54b184ac5bd81d5..bc36a83b4c086e4b6db1ed11dfa4c6d0f50ebe73 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -12,11 +12,12 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" CONFIG_SPL_TEXT_BASE=0x40004030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -36,6 +37,10 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 # CONFIG_MMC is not set CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 2c82e3ca45b68fe5f975c5a1afa4e15c1c2ecb93..9fabc298bc217d7256d81c64645c1de392580dfd 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -6,20 +6,19 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_nor.cfg" CONFIG_MX6QDL=y CONFIG_TARGET_MCCMON6=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 5c1aea8f7a8618c227b567c66f894e2078763db4..f9d586a900d0f9a6458a68059a77cc95d13e809b 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -6,21 +6,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_sd.cfg" CONFIG_MX6QDL=y CONFIG_TARGET_MCCMON6=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 92378389168e6e3eed1d1c02b084e6807ae25563..c50d077d2386b9930e9ced2838a88c8d7e873ef1 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_MEDCOM_WIDE=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/meerkat96_defconfig b/configs/meerkat96_defconfig index ee6b9e14d05f055bb58ee1aec322283dc1403b9d..67934ae04c293c872303f7cb980a24ccd1d2d7a8 100644 --- a/configs/meerkat96_defconfig +++ b/configs/meerkat96_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96" CONFIG_TARGET_MEERKAT96=y @@ -13,7 +14,6 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/novtech/meerkat96/imximage.cfg" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 9d4c9ebff9b7fc35da661db65010afc54efa2f50..b3b1f30cce0aed1721633f25c1985b66cb03fba6 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -8,8 +9,10 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_ENV_SECT_SIZE=0x210 +CONFIG_SYS_MALLOC_LEN=0x2d000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_SYS_LOAD_ADDR=0x20100000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index 69d89359bbd57c4de0b783a0a5dcd9b9bf87ed3e..38473af91988d71b8e4d894a452ec04c1180e72d 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 @@ -6,8 +7,10 @@ CONFIG_TARGET_MEESC=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_SYS_LOAD_ADDR=0x20100000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index bd6e10a5e212d5301d0d2dfe4c7d718dab6b6c96..8db9bacd3b82964df5512c7d9938116671fd30f0 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0xc0000 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_TARGET_MICROBLAZE_GENERIC=y CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 @@ -13,6 +14,7 @@ CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=-1 diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 1cb29201b42a301d586d73e286a1af2a950ea26e..90ae76cc1281bcf95b6fa331a312559603059039 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -1,12 +1,14 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" CONFIG_TARGET_MICROCHIP_ICICLE=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SBI_V01=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index d815fda9a1e528dca0a7a0cfec0f06d9865c0de6..ddffbc612540851c5f68cd6e9acef06a67d78d28 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 @@ -12,6 +13,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 082f4616b988c887cb25412a5e9a141b2c89a8c1..21f7a6e535d2091d4731e8cb404143852475ad69 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -8,6 +8,9 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index b5e9d23cb6fb905f4aa99f269fa980531aca7a4f..416565e5af2bc655d29028927c54c127da1cee0b 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,6 +5,9 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUNXI_NO_PMIC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 38b00b2b4ebfde65aaae99d4e9f97012471fd8a4..965a9cd5c4b09658ffe15c846f0a5803c5836381 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 8907dc2a3c411dfedd803fdbf10277cd6c0c9222..03b378dd25644ac78e2a92e8106169461fc68b74 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -16,6 +17,7 @@ CONFIG_ARCH_MSCC=y CONFIG_SOC_JR2=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 498ddd50d3475c3f77cb98bb6d6712e1f8c02fd4..8364e49254f310b331642ba649853d214ab9014c 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -18,6 +19,7 @@ CONFIG_DDRTYPE_MT47H128M8HQ=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 0d5c13a55fb2853e45aa67185929bec176409f87..cc1aa79e477b1dc123d5d8b85d2da12082123f96 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -15,6 +16,7 @@ CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_ARCH_MSCC=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index 6d9e8276f582a23641725c038351316679dedada..8af95aa97e437bffe19596dd66fd5e43ba9c8f8b 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106" CONFIG_ENV_OFFSET_REDUND=0x140000 @@ -13,6 +14,7 @@ CONFIG_ARCH_MSCC=y CONFIG_SOC_SERVAL=y CONFIG_DDRTYPE_H5TQ1G63BFA=y CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index 0e982527c9983f7b55aab972570883f1fc9f838e..1530fef7f058e9619992dadc6964007aed652fa9 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -6,12 +6,14 @@ CONFIG_SYS_MEMTEST_END=0x9fc00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1f0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="servalt_pcb116" CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_ARCH_MSCC=y CONFIG_SOC_SERVALT=y CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig index 5e9d267f27a367864f2e58d19374190e193d2546..d6095faaf21c1b0eb520b0e4d07d4063cc967293 100644 --- a/configs/mt7620_mt7530_rfb_defconfig +++ b/configs/mt7620_mt7530_rfb_defconfig @@ -1,21 +1,26 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x30000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xb0000c00 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_ARCH_MTMIPS=y CONFIG_BOARD_MT7620_MT7530_RFB=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x80010000 CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig index cbdd9b67baf5573aa41c42bec307b575e7db8881..7a6a3de9689aba838ce3ddfa934ff733313f98ad 100644 --- a/configs/mt7620_rfb_defconfig +++ b/configs/mt7620_rfb_defconfig @@ -1,20 +1,25 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x30000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xb0000c00 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_ARCH_MTMIPS=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x80010000 CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index ebb4045cda2d92bea94dc1c597288e274cca95b1..4615be17931474c72ba12a2567ec6fdde01c614c 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x4007ff28 CONFIG_FIT=y CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" CONFIG_LOGLEVEL=7 diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index 7085f367b4946711b7ad89ec5f526984e6353c6a..c846dcebc853ce8957a56e20f42f0e939aa86138 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc" CONFIG_TARGET_MT7623=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index bd35dbac4dbb2ce58a857e51e1bc401f85f4f7b8..d5c10822d860c29c447c1a2bc5555409b262e465 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" CONFIG_TARGET_MT7623=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig index 039686096c6f936540281249795c57059c3608af..1e051311a79e61c4299dcb200576dc444b984e23 100644 --- a/configs/mt7628_rfb_defconfig +++ b/configs/mt7628_rfb_defconfig @@ -1,19 +1,24 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x30000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 CONFIG_SPL=y CONFIG_ARCH_MTMIPS=y CONFIG_SOC_MT7628=y CONFIG_BOARD_MT7628_RFB=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_MIPS_BOOT_FDT=y +CONFIG_SYS_LOAD_ADDR=0x80010000 CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 43e707030a6e8315f5679a553d6f509e22ff9da8..cd993bc53259152ceb2678c3ef703ed8d3850e7e 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -9,12 +9,13 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" CONFIG_SPL_TEXT_BASE=0x201000 CONFIG_TARGET_MT7629=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x40800000 CONFIG_SPL_PAYLOAD="u-boot-lzma.img" CONFIG_BUILD_TARGET="u-boot-mtk.bin" CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" +CONFIG_SYS_LOAD_ADDR=0x42007f1c CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 diff --git a/configs/mt8183_pumpkin_defconfig b/configs/mt8183_pumpkin_defconfig index a2f06a952abc5a28b93f60e4a42c3014124bb386..08fc60394d62534f388d28e5de895be1cbfcc510 100644 --- a/configs/mt8183_pumpkin_defconfig +++ b/configs/mt8183_pumpkin_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=26000000 # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x4c000000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -60,6 +61,7 @@ CONFIG_MMC_MTK=y CONFIG_DM_ETH=y CONFIG_PHY=y CONFIG_PHY_MTK_TPHY=y +# CONFIG_POWER is not set CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index 3e2d6458296cff9bac6e47afe870c6652c034951..cdb7f45366240a3678b64ef0f4929d9cc5af9241 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -5,9 +5,11 @@ CONFIG_SYS_TEXT_BASE=0x44e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc" CONFIG_TARGET_MT8512=y +CONFIG_SYS_LOAD_ADDR=0x41000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index 63da1eac9fd0695c5592b0085bbd0aa174882ad6..c0786bd98e385481af40f9016394873b0f07b38d 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -12,6 +12,7 @@ CONFIG_DEBUG_UART_BASE=0x11005000 CONFIG_DEBUG_UART_CLOCK=26000000 # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x4c000000 CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index e6c2dd019d6e1b3bc5714d93da80856671646612..73418a004d684d47418ca7ce6c7870ba8278e42f 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -5,8 +5,10 @@ CONFIG_SYS_TEXT_BASE=0x40008000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc" CONFIG_TARGET_MT8518=y +CONFIG_SYS_LOAD_ADDR=0x41000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc.dtb" diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index e1075d71a4d762c37a4c995d85bd4c8d8c6ebc55..f0f50a96697ece436d6308838aad09e1a6a186b7 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -14,6 +14,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 4fadc23b2b453c4788027d2b019a323a45f67937..d401f4765fa6efef4ae2cb645870629a6eae5994 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index adcc5d130a9cb3dd1fd35799491ecc0e09997e75..4ad6d4d7e25a8fb2baf30def8d837f54fc6cd9d2 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 0ab1cc8d8895528147ce621c608e9098604c76fc..ec020ab1dd5cd7edf9b9db6ca5bf9e5d18e08b95 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 761187479fc7429ac115fb238eecc6063385cd0c..01cf24aec918acc9f6ec58a578f66159503ce4a1 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 7fd9e25b5a84c26e0310f1cba73a477152d5b170..44f16b62cfb8e552a556b75da2ff136ba43df22e 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index 5653f921e99841cbb56c615c1fd6f672f79b9301..c521f2c1015b97df3acc00af6ad0d79033691fa5 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n" CONFIG_AUTOBOOT_STOP_STR="s" diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 5805205a8a61e4db424126b80ccbb3cca2015ded..7fc7cc66ef65d779737e9858a86cfe095f52316e 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -7,12 +7,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_IMX_CONFIG="" CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX23_OLINUXINO=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index ab45a9c80f9b346981afeece7f71b7f577a68d8d..8808f20d45d0d8f6f89ddc25cbc65957f360d6d9 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -7,12 +7,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_IMX_CONFIG="" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx23-evk" CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX23EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index 1f61dda5ed98800870b1da1a090b5ca25382b206..9346efb699ea0520bfa79a763f9af60c7b6d378d 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -7,10 +7,12 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_IMX_CONFIG="" CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 306a678aefd5ae85e154103f80014b34d30597e0..fa73fa2a221e6d5be8601f983d45a9da050dcd7e 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -7,12 +7,14 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_IMX_CONFIG="" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx28-evk" CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index e40f83f92e0179d15b37a8c21d6c54a2bb9423b0..17f5ba45a457106944b95056c71897fcc9d09876 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -7,11 +7,13 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_IMX_CONFIG="" CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x380000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 577515e347622d07a25103ab7d94db612c7aec64..9ccc30d42ae436421cb918cfd5b28d28deb7e7f8 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -6,10 +6,12 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 +CONFIG_IMX_CONFIG="" CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 6c8b9b62e517c6689fd2e348cd5f01865f1716ac..f9ca4ee50af9835c529be96caf57a3fc9f41db67 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -5,10 +5,11 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_TARGET_MX51EVK=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage" # CONFIG_CMD_BMODE is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x92000000 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -41,6 +42,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX5=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index 8ee442f2b90fa8edf428d56f27c2067a78036fac..8e3522da2de5fa35a4be0e3abea7a7c313c4887b 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -5,11 +5,12 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_TARGET_MX53CX9020=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x70010000 CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y CONFIG_CMD_MMC=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 296886dd6c8bd27c89b2ba14eee4863c9440c372..04df33cdb2bcec8b37213f888808d1fd53eff7ab 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -6,11 +6,15 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_TARGET_MX53LOCO=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb" # CONFIG_CMD_BMODE is not set +CONFIG_SYS_LOAD_ADDR=0x72000000 CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -32,6 +36,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PHYLIB=y @@ -42,9 +48,11 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX5=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 4a8fa34c275405651db6df35c31130027cbc094c..081707f27ebf3ca2f99a10d39e0992b415ed64a1 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -5,13 +5,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2800 CONFIG_TARGET_MX53PPD=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd" CONFIG_BOOTCOUNT_BOOTLIMIT=10 +CONFIG_SYS_LOAD_ADDR=0x72000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index dd2710f47502562995a859a6daa0d46cdf4b9a88..7af56d4f3a16ad8c597b13fd948c3296866b1f37 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -9,11 +9,12 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFE000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6CUBOXI=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set @@ -21,7 +22,6 @@ CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" @@ -52,6 +52,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 6b9311d210b88d49ab627128ded35d2df4b6d5ee..2defa119edba4b532a87c819f9870be705add4a4 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -10,11 +10,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_MX6QDL=y CONFIG_MX6_DDRCAL=y CONFIG_TARGET_MX6MEMCAL=y +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL" CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 7d0453ac384c3ec8140024fdefcdb65dc084f6b9..419626a26351cb9ef8bc2fd3702648459618eab0 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -7,14 +7,19 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" CONFIG_MX6Q=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabrelite" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024,SABRELITE" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y @@ -48,6 +53,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 1059c5a8a3b0307a08bf4f27536fc98eb4dfeda4..4427079422ed405c65ef0c4d78544e08770e996a 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -10,11 +10,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6SABREAUTO=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_NXP_BOARD_REVISION=y @@ -23,7 +27,6 @@ CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -68,6 +71,9 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y @@ -84,7 +90,9 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 61e9054717b8c97778665c27a808c65541aff985..5216bcaddea8d7c52d1b23901ed83f4e1a5c9346 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -10,11 +10,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6QDL=y CONFIG_TARGET_MX6SABRESD=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_FIT=y @@ -22,7 +26,6 @@ CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -77,6 +80,9 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -93,8 +99,10 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 9e1032938f120a64eb9e3a825b2ba49d482242b1..c041cb7095139e86e922536e25340381aeb4d9da 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -6,11 +6,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SL=y CONFIG_TARGET_MX6SLEVK=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -38,6 +38,7 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 8df10ed2ae5de0215c0d119cef63150381285f9c..1e6aae68d7466892280e7c6703d9d7c5f740955e 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -7,11 +7,11 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6SL=y CONFIG_TARGET_MX6SLEVK=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" CONFIG_SPI_BOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y @@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 987573f6c0d8f21fe63246cd7ee91eee122e481d..7c445e6e0c8bff8ff94f4a7ab98d432e29810c6d 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -9,16 +9,19 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SL=y CONFIG_TARGET_MX6SLEVK=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y @@ -47,6 +50,8 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 9f02ec838a033a0178c8c78f974ff78d1164cbee..43a349fc0e8a51340baf13b64a22096ebdf21d9f 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -8,11 +8,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6SLL=y CONFIG_TARGET_MX6SLLEVK=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 6fc49150b3c17555a433cc7a972d32e60e075ddd..b61bab71787041be227c9d02a518fd75145ea49a 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -8,12 +8,12 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6SLL=y CONFIG_TARGET_MX6SLLEVK=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" CONFIG_USE_IMXIMG_PLUGIN=y # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index d888e7255d2dab73de89c7a4e1ffd5ed09579a82..c9691e1f1f9c3ee0dc8367a5d9a90873ec395c5f 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -6,11 +6,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SX=y CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -37,6 +37,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 67dfcda8fa7473b89acd39ce8cc351a268c845d0..b80dc946565d56641c812140da082398ea82df7d 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -6,12 +6,12 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6SX=y CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" # CONFIG_CMD_BMODE is not set CONFIG_NXP_BOARD_REVISION=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -40,6 +40,7 @@ CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index d28b6f6e3cef8308010cc62dcd4369a34b5cd453..c9760df4b57c7694d946ee666a3f7f5400ceac3b 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -11,15 +11,17 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y @@ -57,6 +59,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 1425724429e1ab51a47b175335dab92d98283da3..a373e202997642f01ffb0d86c545f640ed5d0282 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -11,15 +11,17 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y @@ -50,6 +52,8 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 24e18c1d4ebde7ac96eab1b969596abb7a4cdfde..8ecb496571b50de02678cbdf0e7d009f070ba4c8 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -36,6 +36,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 2700f98e6c6a8d17b2d99025867d86f236f2d4b9..64719b1efde12b1242239dacdf2e35ffcb169fae 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -8,11 +8,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" CONFIG_USE_IMXIMG_PLUGIN=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -37,6 +37,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 23c821079e5dcfe74ebb7aa92c597eae4745778c..e233931d407e33e1e9e363da3cabcf18e447faf1 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -35,6 +35,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 39e73042bfb9c58e942cd4912530215b5356a57d..c10dafacc75c318a2f1f4910a7bb4a315a9d36c8 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_TARGET_MX7DSABRESD=y @@ -13,7 +14,6 @@ CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CMD_BOOTD is not set @@ -45,6 +45,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index f5d2f253657ccb39855412117ecde9fcada54fe7..0da33c4507bbbf51ac427efa5f244ce428035e6f 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" CONFIG_TARGET_MX7DSABRESD=y @@ -12,7 +13,6 @@ CONFIG_TARGET_MX7DSABRESD=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CMD_BOOTD is not set @@ -44,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig index 62992fecdf26df04b6dfc2ee0e97cd3894065ae8..6e6b821d9046feab6c317f3bbeb2232327f18534 100644 --- a/configs/mx7ulp_com_defconfig +++ b/configs/mx7ulp_com_defconfig @@ -4,11 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com" CONFIG_LDO_ENABLED_MODE=y CONFIG_TARGET_MX7ULP_COM=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x60800000 CONFIG_DEFAULT_FDT_FILE="imx7ulp-com" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index c7738a6b80750758a67597c2b4cdfdfb28028ec8..04ace671586ddecf030ebaefe3552ca75a1fd2cf 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -6,11 +6,12 @@ CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_SYS_LOAD_ADDR=0x60800000 CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 05e62fc165fe2df41b7fd81ceb934c77d440a1f3..fff865f5b06b27f6ae00db61ce177fb9fdbfbe08 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -6,10 +6,11 @@ CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x9e000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" CONFIG_TARGET_MX7ULP_EVK=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x60800000 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index d7a68d6c51605f9eb0e21c794f095896358f5538..022f9ffd82d63c354c2a0d399a1351e9c84b4762 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -9,14 +9,14 @@ CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x4000 CONFIG_MX6ULL=y CONFIG_TARGET_MYS_6ULX=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval" CONFIG_SPL_TEXT_BASE=0x908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index a94f428deffcf7288bf5a396e240cead780d19ce..d86faf196cc15cd0c4058ceef41f6023411863e9 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index 1c28c2cab51eb10b823ecb674efb8208ad29e66e..7452caaad6b3d33e4552ce609e81d08a83f452cd 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" nanopi-k2" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index c9833fdb8543d26ad0682da5abb27d615ff1e02c..100cd336cd29747b6d0b928b30f23cc0aecdf32c 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 2b2fcac3666d52eccd74e04f1d82e025e5749dbe..ba02b6e6dffef77e69ff84e891596fd91d851fb9 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 6d3afe1b63d60154a1274af5a46270cc22ccedd7..7916307b071a3046944528f9816767d9d41ca412 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 1bf5d1d0956e39b6d99080b551e97777316ed5bd..5aa226a6cfeeb6a516c35fd6392ef988e199b03f 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 0dfac0a42f7169cfdd790a18b90e250913dada97..cafb38ffcee772ceebbca17d4a7c9ac8c9cc857f 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -15,6 +16,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -66,6 +68,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 351d2eb55361efd52870e97ead512aba88620ae5..7d176ce28e26a10edc2e0861f5613dbbe7bdac46 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 10fcf214466955d2f492faf56dc515e116c27805..386ebcae7f95f8c1b106e325b1d6c98e0daad43f 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0xA0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220" CONFIG_IDENT_STRING="\nNAS 220" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 841842cefb614e25cd7d8d4e35fe55225e859162..5d84a5dd1264f3f0f75bd3780f8f3d5eecd49a51 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big" CONFIG_IDENT_STRING=" 2Big v2" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="2big2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y @@ -43,6 +46,10 @@ CONFIG_ENV_ADDR=0x70000 CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index 94eebdf09991368ca46db75f30a8bc34d4f9ad0d..b961b58ac394f2b29e542961e50f62e2c909da9b 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -1,14 +1,18 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" CONFIG_ARCH_BMIPS=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index 1f21f685996e0baf330581739f8ee9e926eb7286..89638d33de6ef33777e42e815629b6046e53bd2e 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6362=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 1c577faab74c0f54eb8a458bd41c64411dab7c3f..15cc556f0ae1b5889dc3858ceba025595f38b3b3 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite" CONFIG_IDENT_STRING=" NS v2 Lite" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y @@ -43,6 +46,10 @@ CONFIG_ENV_ADDR=0x70000 CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index d5af1150647eb3db7a26c713402729acf61627d1..1946e440062c00ea2e61e6e0bac388d01f07e6d8 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max" CONFIG_IDENT_STRING=" NS Max v2" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y @@ -43,6 +46,10 @@ CONFIG_ENV_ADDR=0x70000 CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 5d9ea06259b22a857eed3db8636265d9960f2ce4..2bcb8498b505feb18b22e7c544c68d23fa0b2d27 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini" CONFIG_IDENT_STRING=" NS v2 Mini" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +45,10 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_BLK=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index c152a310a2730c9c440da09e0804fd6953043393..b281a40c4140ab9ab20c6ede32b65f3e69768b44 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -11,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2" CONFIG_IDENT_STRING=" NS v2" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -22,6 +24,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y @@ -43,6 +46,10 @@ CONFIG_ENV_ADDR=0x70000 CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SATA_MV=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 865f6fac84a1c296d299fc59f9276764c06d033e..a56cb2c49746c61befb76398bc47ac6af1b2a28a 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -8,14 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl2g.cfg" CONFIG_MX6DL=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=2048 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,DDR_MB=2048" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -51,6 +56,8 @@ CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 7852eb8638c7e49998006f3db737838feb11c3df..68d286c96cfdf95df39b84d569bd11c9261fcab2 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -8,14 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl.cfg" CONFIG_MX6DL=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -51,6 +56,8 @@ CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 2007126023d0fce825d691eeb9107757afbb9eac..cbe9ced14a1d9bf7ee64db418fcf1826d9e3a3c7 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -8,14 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q2g.cfg" CONFIG_MX6Q=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=2048 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,DDR_MB=2048" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -53,6 +58,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index af38dd711f2996634e8742a426c9d2690a8bfe7c..95e60f9c059e6c9445c447d139cca586ec05bf29 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -8,14 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" CONFIG_MX6Q=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -53,6 +58,8 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index ae00482f9cb8198c940f68acea79b583052bfe14..43c0787dc14b1862b8366a87d1bf5dc1a564326c 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -8,14 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg" CONFIG_MX6S=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -51,6 +56,8 @@ CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 92ccabaa26ca77f9463381e810c8e6b0bdc1fd1a..a8428dc3ab46cbea0818a8d7ad9794d1447b9e2f 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -8,14 +8,19 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s.cfg" CONFIG_MX6S=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 +CONFIG_DDR_MB=512 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,DDR_MB=512" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -51,6 +56,8 @@ CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 981e6f95cb1ffb15e4a23ef7ec134b3d8be0f072..69784d972ad54b34c4342b31cb9d520a92966b6c 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -1,12 +1,21 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_REVISION_TAG=y +CONFIG_STATIC_MACH_TYPE=y +CONFIG_MACH_TYPE=1955 CONFIG_SYS_TEXT_BASE=0x80008000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MALLOC_LEN=0xc0000 CONFIG_TARGET_NOKIA_RX51=y CONFIG_OPTIMIZE_INLINING=y CONFIG_LTO=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x80000000 # CONFIG_FIT is not set CONFIG_BOOTDELAY=30 CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 54180362bc10b1cfa630334b10d65e7ae4a063c1..66aa34281e9f18401422e968fce4104456e7ed89 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -10,10 +10,14 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6Q=y CONFIG_MX6_DDRCAL=y CONFIG_TARGET_KOSAGI_NOVENA=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x84000 CONFIG_SPL_FS_FAT=y @@ -22,7 +26,6 @@ CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc1,115200 " CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs" @@ -33,6 +36,8 @@ CONFIG_SPL_I2C=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -52,6 +57,9 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y @@ -61,6 +69,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 8765dc3dd187e9d48970bd78ff77fca14db5d758..c2c5994315a201d8368a868ebf8d97b65839e0d3 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -9,6 +10,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s" CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/nsim_700_defconfig b/configs/nsim_700_defconfig index a67963a4b791762522625fdabbfd4fc2651120d6..3607583c60b39602927fe26a11a82f4668b597b4 100644 --- a/configs/nsim_700_defconfig +++ b/configs/nsim_700_defconfig @@ -2,11 +2,13 @@ CONFIG_ARC=y CONFIG_TARGET_NSIM=y CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=arc700 -mlock -mswape" CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="nsim" CONFIG_DEBUG_UART_BASE=0xf0000000 CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/nsim_700be_defconfig b/configs/nsim_700be_defconfig index 5852a0cd8e42cb95d60b9d3d41a7d980e6f760e2..2d8a3e4a06e7a94a44a112b960a11f0f432a2218 100644 --- a/configs/nsim_700be_defconfig +++ b/configs/nsim_700be_defconfig @@ -3,11 +3,13 @@ CONFIG_CPU_BIG_ENDIAN=y CONFIG_TARGET_NSIM=y CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=arc700 -mlock -mswape" CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="nsim" CONFIG_DEBUG_UART_BASE=0xf0000000 CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/nsim_hs38_defconfig b/configs/nsim_hs38_defconfig index cdbcba1f25ce3b5d0dfd7203592a706c67350fbc..51ce560c1af657b1b88a2252d07fab280d50be78 100644 --- a/configs/nsim_hs38_defconfig +++ b/configs/nsim_hs38_defconfig @@ -3,11 +3,13 @@ CONFIG_ISA_ARCV2=y CONFIG_TARGET_NSIM=y CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=archs" CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="nsim" CONFIG_DEBUG_UART_BASE=0xf0000000 CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/nsim_hs38be_defconfig b/configs/nsim_hs38be_defconfig index 41e3618ffe2c6bb7ef1043d72747ccd7b993a218..60e609481828962b17ea0b3b1a001632e0164fe4 100644 --- a/configs/nsim_hs38be_defconfig +++ b/configs/nsim_hs38be_defconfig @@ -4,11 +4,13 @@ CONFIG_CPU_BIG_ENDIAN=y CONFIG_TARGET_NSIM=y CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=archs" CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="nsim" CONFIG_DEBUG_UART_BASE=0xf0000000 CONFIG_DEBUG_UART_CLOCK=70000000 CONFIG_SYS_CLK_FREQ=70000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 3f6bb94c7b85c5454a5d97f12e60f7d7d8717474..9d7d54e6c3718236580680f4ad459486d9874515 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x81000100 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000 @@ -12,6 +13,7 @@ CONFIG_DEBUG_UART_CLOCK=408000000 CONFIG_TEGRA124=y CONFIG_TARGET_NYAN_BIG=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x82408000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/o4-imx6ull-nano_defconfig b/configs/o4-imx6ull-nano_defconfig index 45d4dcadb9d1ce8c69b7dc60167d0ec1dcdbc9f6..d8a71617449ed047124b702d140fbec7076783a7 100644 --- a/configs/o4-imx6ull-nano_defconfig +++ b/configs/o4-imx6ull-nano_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_MX6ULL=y CONFIG_TARGET_O4_IMX6ULL_NANO=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_MT41K256M16HA_125E=y CONFIG_IMX_MODULE_FUSE=y diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index a2b8c3ce7fc3617d68ce06a5802bdf9337957123..c30ccedeb933657ee79b141e669645e3b4831121 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEBUG_UART_BASE=0x8001180000000800 CONFIG_DEBUG_UART_CLOCK=1200000000 CONFIG_ARCH_OCTEON=y @@ -12,6 +13,7 @@ CONFIG_ARCH_OCTEON=y CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000 CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_LOAD_ADDR=0xffffffff80100000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index 3d60b36160a3c475062fcb290eaa982b9c77fd48..0f191804037403bbde98827a27d22a41160f0132 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xe000 CONFIG_ENV_SECT_SIZE=0x100 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEBUG_UART_BASE=0x8001180000000800 CONFIG_DEBUG_UART_CLOCK=800000000 CONFIG_ARCH_OCTEON=y @@ -14,6 +15,7 @@ CONFIG_TARGET_OCTEON_NIC23=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_LOAD_ADDR=0xffffffff80100000 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 8a912d86b1b00f3ceaf855d2924b08aa6037f69d..6d8457f1d0701ff4daf3d3067e39b8e617c315ff 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -10,10 +10,12 @@ CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX2_95XX=y +CONFIG_SYS_MALLOC_LEN=0x4008000 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x4000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 02bb0f6d5c1bdefe709675b360bdfa17adf86cc4..b72caef77d8f1d034ddd42309ef8a5fd830c798a 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -8,12 +8,14 @@ CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX2_96XX=y +CONFIG_SYS_MALLOC_LEN=0x4008000 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x4000000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index e14957c9b1ecc4a5f573215439370f513336c5a9..52678d59ff1f26ae0798e5951d719ad1072094d5 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -10,11 +10,13 @@ CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX_81XX=y +CONFIG_SYS_MALLOC_LEN=0x4008000 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x2800000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index f9f285a899b8b75a167515986e43677df3abdab7..3890c1e97d46aa387a83946d4bb47f644db1ffc8 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -8,11 +8,13 @@ CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xF00000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_TARGET_OCTEONTX_83XX=y +CONFIG_SYS_MALLOC_LEN=0x4008000 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x2800000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 7c9683164049bf6f10cd242fe13c5b4d10a23c58..6f93df231ba0eee6edb597c121908e038d98eb1a 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig index 356a9c9be29205efca1fcd5849c1c7fd574b044a..bc778a641a35da266a69af22c9c24980b2768b24 100644 --- a/configs/odroid-c4_defconfig +++ b/configs/odroid-c4_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c4/hc4" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index aafec84f109168a29577cb3fd69701cc92dc6c6f..c744c3a6ea35056df5f59ff243e09e0492720e90 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -19,6 +20,7 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -81,6 +83,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index 1f718a3154ef0736fbb0c280cecb3abbace3d08a..8e9e8f8fb78403482cb3280ddbe5811aa0a68360 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-n2/n2-plus" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index f56dfb7d8e2ff269b02ae2f1d28749b193e1bdab..b24317356f563fb247fa7f55ebac03c61b045964 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 @@ -6,10 +7,12 @@ CONFIG_ARCH_EXYNOS5=y CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x310000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2" CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -42,6 +45,7 @@ CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 +CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MTD=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index b95cefd54d08b482e9c78e03e8b7461dca6d3af2..fa2c5e00e305d7a5ad401bf0164cca1760535fb5 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43e00000 @@ -7,9 +8,11 @@ CONFIG_TARGET_ODROID=y CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x140000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 8b0c94302458d00cf07558399d42b9aaf2ccdfa5..d699efb2faca6dab0bec16a9882379a54578f79a 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -53,6 +53,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 2ab92551e4d0b89ac16090031a67a9a838227006..9f3a88f28ecf3d5693dcc6883fe72e311cb7b77c 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -52,6 +52,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -81,6 +82,8 @@ CONFIG_OMAP3_SPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 462f94ed056269ebf158d8ece6b62dc8d1a22757..578e6829ff14a77101fbb35ab4a2aaf7db4e5768 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -56,6 +56,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=1 @@ -82,6 +84,8 @@ CONFIG_OMAP3_SPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=147 CONFIG_USB_OMAP3=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_OMAP2PLUS=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 9d4db33f6462997352b14d5a787fb9ab1d2eab1c..9a86beb6b40f1fb4169e3cc15b6cea0c537a1f22 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -57,6 +57,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_GPIO_HOG=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index ec7a8a6e3760afe2eeee89afa1ed05307dfaae97..9424755b31bcf685f899e8aee529c912669915b7 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -52,6 +52,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP36XX_PINS=y CONFIG_MTD=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index f2e9d20e8fae6663990c1133dbf082885be4c9e5..7a78682bf69add4e889acd2479ffaa1f34d539bb 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -52,6 +52,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP36XX_PINS=y CONFIG_MTD=y @@ -82,6 +83,8 @@ CONFIG_OMAP3_SPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 3585566cc0173be5a596e6bb5a9e0be20cda5c66..8c6baaf4fda515cd6962060b1b1cfdbb9b36be01 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -32,12 +32,18 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_DM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_ETH=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=1 +CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=62 CONFIG_USB_OMAP3=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 17102770888f8711bfbb0bf53023a9380a20bd42..9dae340f643bd74421a36356c49a279632a646e4 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -33,6 +33,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_VERSION_VARIABLE=y CONFIG_DM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_ETH=y CONFIG_CONS_INDEX=3 diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 16264ae457d3cc4105591e4e0bd3a78a56af64a5..0280b4ac8d073cd03f61d1a958ec6ebe99ca70e1 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -39,6 +39,8 @@ CONFIG_SCSI_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_CMD_TCA642X=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_ETH=y @@ -47,6 +49,10 @@ CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=80 +CONFIG_HAS_OMAP_EHCI_PHY3_RESET_GPIO=y +CONFIG_OMAP_EHCI_PHY3_RESET_GPIO=79 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 0cde86a2f960c293734a35003ed2980d7ed913a3..80e90230b4551eeab419c2817f3ce8cb7bb3f8fd 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 @@ -12,12 +14,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x110000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk" CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_BOOTDELAY=3 CONFIG_LOGLEVEL=3 # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig index cd66db2fe528843ae40216c2c3b758e857563591..04cc058a779d01d19ca1072e530e41f5d855d8bc 100644 --- a/configs/openpiton_riscv64_defconfig +++ b/configs/openpiton_riscv64_defconfig @@ -1,6 +1,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x80200000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x10000000 CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" CONFIG_TARGET_OPENPITON_RISCV64=y CONFIG_ARCH_RV64I=y @@ -10,6 +11,7 @@ CONFIG_OF_BOARD_FIXUP=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_ENV_VARS_UBOOT_CONFIG=y # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x87000000 # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_PROMPT="openpiton$ " diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index 180652ba8f9c39e96bb65484defe32ee93167d8d..ae178f7f284561ae1c6939c9609255f2086a83c3 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -1,8 +1,8 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x10000000 CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" -CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -15,6 +15,7 @@ CONFIG_RISCV_SMODE=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_ENV_VARS_UBOOT_CONFIG=y # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x87000000 # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set @@ -23,7 +24,7 @@ CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SPL_BANNER_PRINT is not set CONFIG_SPL_CPU=y CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_RTC=y CONFIG_SYS_PROMPT="openpiton$ " # CONFIG_CMD_CPU is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 72d6358d4c5a3ced15ac8f5260320982cbd156f2..0e22f6902aa30b28bc3d638e7b08cabb53545822 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y @@ -11,6 +12,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base" CONFIG_IDENT_STRING="\nOpenRD-Base" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 1b49abb8d78845fba9a53b3594908019309d2930..069f96ce2a5fc03a282a7d9f75ad34f7f8c7fa4b 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y @@ -11,6 +12,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client" CONFIG_IDENT_STRING="\nOpenRD-Client" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index fafe53e72ea19d35288ab0643ab5bdb9ed0fe9a6..7483c45b23dde6b9248803f33a78d2993c726bcb 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y @@ -11,6 +12,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate" CONFIG_IDENT_STRING="\nOpenRD-Ultimate" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 1e8d56e78812badf92e35ea5f7eb808920698563..32adb5d8189ec733b0ffce7db6b84eaf8fe67a02 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -9,10 +9,11 @@ CONFIG_ENV_SIZE=0x2800 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6UL=y CONFIG_TARGET_OPOS6ULDEV=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 9f0053914ae15aee251666521e40e820a4049a22..9857fb10653fca6a671a8d19d85ef1e8711adf7e 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index efb7e8c9b46621da83f152b39c9e07f907686eef..7aaa5190b3a319381eb1bddf4ace47f4492e2ce3 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index f17241fc0ad848e0960ba0f836f636705c8b2a1e..2eaddcf684134a833ddb60b79fb3c2e14587347f 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -9,6 +9,8 @@ CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_SY8106A_VOUT1_VOLT=1100 diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 622cac06580f946e633f2ea7cf959bd96c157f5e..905ff7b1271dbce80e2c5d65017b975e8820a8bf 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -6,6 +6,8 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index 3aeb2def00e6f3055d61cd57d0c5607a9d8cb0e5..f845138153dba42f0f017da0590055ef0f3175a1 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index bce2f5f664ace8dc1923fd311ec53845b8def694..138a6a72b8ce0d9c871dafe1f865791554ab60ba 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -8,6 +8,8 @@ CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 7f778c747466690058d057438d7d8f0f2f1f2546..76de72aa2287daab3148b75c4e4ea3b9d0a5026a 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -10,6 +10,8 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 5334ff7bc113264b4eec5d14bac69abd86b3ff69..edb765f02fd5e619f6308879853492b0c7725184 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -11,5 +11,10 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 932c107c57c34ccc070a6d9ec66ff90a3fdc3dea..d6b890646dfdf5b95ab0c8a340aecb08b06441ea 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y @@ -7,11 +9,13 @@ CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_ORIGEN=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4200 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen" CONFIG_SPL_TEXT_BASE=0x02021410 CONFIG_SPL=y CONFIG_IDENT_STRING=" for ORIGEN" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x43e00000 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/p200_defconfig b/configs/p200_defconfig index 10b240b30b3c7a06fd5a7e47133f90ed3ddf5486..9f75552bf0a718c557889751481622a164684a5d 100644 --- a/configs/p200_defconfig +++ b/configs/p200_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p200" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/p201_defconfig b/configs/p201_defconfig index 612f32fb7c44bfe557d9619f0fd05d668b8e446a..1e07794ee13cf810825e135c20980fe1da4fdce6 100644 --- a/configs/p201_defconfig +++ b/configs/p201_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p201" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 493b33391eed163a26d0a905b13c9dcd76c6115e..b1d2ca83500fa499779537d551cab803af387727 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p212" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 039293feef4bc597b66fb27b493190acfa2c77c3..43d9095adc02c978b69fa779ec834b4817169334 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -4,8 +4,10 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" CONFIG_TEGRA210=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index a4dfed72a1b172fec67a78e9c09698213e58811b..c9498b39b8fc352173354b373017112d18c25ae1 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -4,9 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180" CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 8c3a184d19508d7df06e3e98a5fd98bc98b79e76..27cc68e220632296621ed4c40389f0583dc9442c 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -4,9 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" CONFIG_TEGRA210=y CONFIG_TARGET_P2571=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 18ec21aaa79161f0ce8248a9eeb1be98a0995707..90e93960489db08202d05cda9082a86db4fe2ff0 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000" CONFIG_TEGRA186=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index c0a9a459f7525d65daf88ab9940e96287963a2c5..6bdc1132f6d356cef87b57590c26c45fffb482ec 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500" CONFIG_TEGRA186=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index 9f9a5edd0e20a1957bbb8befe0700fdb7c5e5b84..0587ca9c6bab9d44cd70eaeb7687228b8f744275 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -5,9 +5,11 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" CONFIG_TEGRA210=y CONFIG_TARGET_P3450_0000=y +CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 4ce36474e2b470fcced9829ad8be4c9743a8097a..a209e41d428534437f3f458ef9c2043a95f4fe0d 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_PAZ00=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # " diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 260d3d459b4808fdc029713e2457e153688a8c4a..59cebf89bf3dd3b2d796d1aa9107b206f0169459 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 @@ -7,11 +8,12 @@ CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xA0000 +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052" CONFIG_ENV_OFFSET_REDUND=0xC0000 CONFIG_TARGET_PCM052=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y @@ -42,10 +44,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_I2C_EEPROM_BUS=2 -CONFIG_SYS_EEPROM_SIZE=32768 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index f9babdb504f2a4b39d310aa69bba08d4e11405e3..0adfb985f533d0890a59dd7e352eda69a416e220 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -11,21 +11,21 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6Q=y CONFIG_MX6_OCRAM_256KB=y CONFIG_TARGET_PCM058=y +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-phytec-mira-rdk-nand" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x110000 CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_CMD_HDMIDETECT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 92d6be43f81708098f1d55dad6ba1b0a7a598685..173ed4efa1078a8a1a34c5eb5c056a23d27fd442 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x23E00000 @@ -8,11 +10,13 @@ CONFIG_NR_DRAM_BANKS=7 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3FC000 CONFIG_ENV_SECT_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" CONFIG_SPL_TEXT_BASE=0x02024410 CONFIG_SPL=y CONFIG_IDENT_STRING=" for Peach-Pi" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x23e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -38,6 +42,7 @@ CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 824a664904e85ebe8ed4a382e7745d0dfb5d4157..af4865f82a080bd822f5f728737d69846efcdbd5 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x23E00000 @@ -7,11 +9,13 @@ CONFIG_TARGET_PEACH_PIT=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3FC000 CONFIG_ENV_SECT_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" CONFIG_SPL_TEXT_BASE=0x02024410 CONFIG_SPL=y CONFIG_IDENT_STRING=" for Peach-Pit" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x23e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -37,6 +41,7 @@ CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 27e8192ded7c446eedc66bf280c34baff597be65..6426a332a0af00c436f2766a322b2c0e42835a0e 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_PG_WCOM_EXPU1=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -12,11 +13,13 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1004000 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -48,8 +51,9 @@ CONFIG_ENV_ADDR=0x60060000 CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y -CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_LEGACY=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 99389d64059a046d86d172026a12af5d2350b2ac..05ba20d52b95ce0a6dc034a464f6c60657951151 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_TARGET_PG_WCOM_SELI8=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NR_DRAM_BANKS=1 @@ -12,11 +13,13 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x1004000 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -48,8 +51,9 @@ CONFIG_ENV_ADDR=0x60060000 CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y -CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_LEGACY=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 966fc1f3220acac31c2f90a1b11f6edf0dc5f006..3de815c0b2cecded507cef1f829fa90cb24dab7b 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -9,8 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=1000 CONFIG_TARGET_PHYCORE_AM335X_R2=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 4718359d34e2a8e2d8c098745ffe390a5d000b39..5137bec8a0a7ae10ab56b21328c66c10f402b4cc 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -9,8 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=1000 CONFIG_TARGET_PHYCORE_AM335X_R2=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 7892cd492651fd651d394b6deddf77821c1e9429..91360b7d1a5ceb4491adeb2da2e2d19c810cd4ce 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -7,24 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -38,6 +36,10 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -66,14 +68,9 @@ CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 -CONFIG_SYS_EEPROM_SIZE=4096 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 84a0a5cbaf248b348f967d868e82628754bd2ab9..f22798e2bb32236c20456728ee55afbe7d3bb323 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -8,21 +8,22 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -38,6 +39,10 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y @@ -66,14 +71,10 @@ CONFIG_CLK_IMX8MP=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set -CONFIG_SYS_I2C_MXC=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 -CONFIG_SYS_EEPROM_SIZE=4096 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y @@ -91,9 +92,11 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 8ee99e54c7631b5fbf1a03bc63e96d9d579eb872..a20274702046808cb6ce817e95b9dc9b2e48474d 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 @@ -12,6 +13,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index a74a7a3eec6c2683e63aaa306cfe134f70e4eb16..03d3e6f84abb7375251268ccb952852fd3c1b079 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -9,13 +9,13 @@ CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x4000 CONFIG_MX6UL=y CONFIG_TARGET_PCL063=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand" CONFIG_SPL_TEXT_BASE=0x00909000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index c2a83d418f2b2ea5d453e478ce24cd6ac6bdabf9..6524349840f55a63c19e7776ac427b26ffc4cf60 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -7,14 +7,14 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_MX6ULL=y CONFIG_TARGET_PCL063_ULL=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc" CONFIG_SPL_TEXT_BASE=0x908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index f8c46fa347052f0fed42215e2f0d088d8b74c343..093fa2a3c5df03e265988093b41c1c1bea9b6182 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -4,12 +4,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x88080000 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" CONFIG_MACH_PIC32=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x88500000 CONFIG_BOOTDELAY=5 CONFIG_SYS_PROMPT="dask # " # CONFIG_CMD_SAVEENV is not set diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index 673911ca63296b3888b4ce0fb0848aa08f668c8f..cf49e7cc00f09a0693b9be9007ac170d4749beca 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -11,14 +11,14 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y CONFIG_TARGET_PICO_IMX6UL=y +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi" -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb" @@ -50,6 +50,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 1ef415f03adb99942c36f18d05dfcb4fbe26028b..1be6605ae3914a6b1abbd4dd104737a0aa375aae 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -6,17 +6,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_SPL_I2C=y @@ -53,6 +57,9 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -65,6 +72,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 0c11d0c88cf66ebf613f902aa27610e72dde5b0f..089411122774581ced5cb2493c94cad7473a0d3a 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -11,15 +11,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y CONFIG_TARGET_PICO_IMX6UL=y +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" @@ -51,6 +51,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 64a76a947753b5767df973b8c72a12ccd7807d6e..a0c034c83b143f43efea4d27c638527a82e0cc9b 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -6,17 +6,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" CONFIG_SPL_I2C=y @@ -53,6 +57,9 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -65,6 +72,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index c3cd660813c841709e8f955a822ac1ee47447eb1..fd102611f932df8d084fd0fb928b7de198ce7939 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -9,11 +9,12 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6QDL=y CONFIG_TARGET_PICO_IMX6=y +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y @@ -21,7 +22,6 @@ CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run default_boot" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index f027c866f564aff8c0542b485f8bba8e5ed02ccf..d7c3821a0cb3faf69387ee4b9e854ba48780b9ca 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -11,15 +11,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y CONFIG_TARGET_PICO_IMX6UL=y +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" @@ -54,6 +54,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 4657d51e23bfb796f6f7a659bece0315ba753d10..df81717a325a855855c678cc3f8d9c0156f99694 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -7,17 +7,21 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SPL_I2C=y CONFIG_SPL_USB_HOST=y CONFIG_SPL_USB_GADGET=y @@ -48,6 +52,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PHYLIB=y @@ -59,6 +66,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=4 CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index c68294821851fe723956ea8c81dcfe84547e9beb..7d535625bf783aa8ea750ef254345d6df0adb9d8 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -6,17 +6,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SPL_I2C=y @@ -53,6 +57,9 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -65,6 +72,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 9d664c07f06579eb56547df7671f19aac3fd5336..b90a49242477461bc13dc16979b1654db5353742 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -3,17 +3,21 @@ CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x600000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PICO_IMX8MQ=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -42,17 +46,19 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y CONFIG_DM_RESET=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 1ef415f03adb99942c36f18d05dfcb4fbe26028b..1be6605ae3914a6b1abbd4dd104737a0aa375aae 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -6,17 +6,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_SPL_I2C=y @@ -53,6 +57,9 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -65,6 +72,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 93606bf487875f0498447019b88b92fbdfad4a5c..c3999ec7a4e7f78e490739437da8ca5da11ef490 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -11,15 +11,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6UL=y CONFIG_TARGET_PICO_IMX6UL=y +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb" @@ -51,6 +51,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 8d668936d7760d854ada18c456ef4460d6da99db..e0be1b0abc9c4318971f21d2c828b06e29d03c75 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -6,17 +6,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" CONFIG_SPL_I2C=y @@ -53,6 +57,9 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -65,6 +72,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index f97d5e872b069cb7aa440d5af93d7c6e107e924d..81aedb28e37b6f4cd62790c0766dbdb72a8bbc4b 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,8 +10,9 @@ CONFIG_TARGET_PINEBOOK_PRO_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 533a736999c13da4e456bb59d92b7772d1b6bd44..f63e3e47f539fcdef65420d6e88186dd6c645ac5 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -8,6 +8,8 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index abe299755169ff710bd8f3028963ebff423716e7..742da36502ed5b163bd09a425dc6cf5ac2affd90 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -8,6 +8,11 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 # CONFIG_NETDEVICES is not set CONFIG_AXP209_POWER=y CONFIG_AXP_DCDC2_VOLT=1250 diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index f47a8f57673bb4ddafa4082f5b4580b84f8c2859..4000de19397512936bd96fa4aef0e085deae14c3 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_PLUTUX=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index f253deacc43f06ecf78ec6e9a2520bd7d2986d3a..9aaf775c6116ecb88b07f80728c80bb90abf4643 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -7,8 +7,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x50000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 193622e59456ba8f18a41df2092445a9ec5465b7..f0ad4b3c65ed7bbfb9e22c050f40468032fcf3b7 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -7,8 +7,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x50000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 7941ee2772407fb522146b5bc2888789187f4722..bcac445befc0871e29aa539a9dec0b6bf5b5854e 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x73f00000 CONFIG_TARGET_PM9G45=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -11,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index e3d2238794c43397fea74f680accab7af93a3452..056c1902977c9dc4477c90c565b6edccca4d22b5 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y @@ -10,6 +11,7 @@ CONFIG_ENV_OFFSET=0x60000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02" CONFIG_IDENT_STRING="\nPogo E02" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig index 82833ff096705aa1d6373bee4212a5cc3a6eb7c2..007d1163fa9e1285a86f8e88e3e1af9bb5d37a2e 100644 --- a/configs/poplar_defconfig +++ b/configs/poplar_defconfig @@ -5,9 +5,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1F0000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar" CONFIG_IDENT_STRING="poplar" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="poplar# " CONFIG_CMD_MMC=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 5b6d8cab870a95ae4bcbc67f1b1223781d3832fd..98fb823c928b5206f416f46869b86de2af3ce775 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 @@ -12,6 +13,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 135feca93884f3641e2329580614a3092ed00052..4708c7442877b47c142c784e8ec2b1708e1b2158 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Porter" CONFIG_R8A7791=y CONFIG_TARGET_PORTER=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index 1f9b3e0077571c14b59ce26baa92f2a38f30a882..a62c9f8fa37f7603238b3196775b675ba708441e 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -15,4 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_MUSB_HOST=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index eaa3cddd4e1cec9048b401d2bba35a6131fcf3ba..afc54fe45cf83623740ca29f4301ab08fabec54b 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -12,8 +13,9 @@ CONFIG_TARGET_PUMA_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y @@ -44,6 +46,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -67,6 +70,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index aed790b6a6ff0358a0668f11ec3f23c1065f32ed..91461918d649d62e2e120fa9a75edbbdf25a4b6c 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -17,6 +18,7 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 0340039ce711f7de98579a7d00f833fcbff8a830..46077fa64e9d47d1cdc0c5f4bd6beb969320c9a2 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -17,6 +18,7 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 70c4a1801dddb06352c573c64c0088f617f81543..624e98ce1bdded6b8973429ea73f5bd6a73aae4b 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -7,20 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=720 CONFIG_TARGET_PXM2=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -75,6 +77,9 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SPEED=400000 # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 3319f38c12d008605753c63f7375a5f19f880c62..f269b8a588950f3619819277e2aef20707d23f29 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -16,5 +16,8 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 8ac16cf4186eed709cc445f19166657a1284fd2c..f49d49e1d3a6a06ddbbf2275485d8d3e3b50eca4 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -1,8 +1,10 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 05eda439618f3561f9a23052a32bb820f5b37f2b..f13661e2ed7d059cb56acb0332b15ca2b9b9efe6 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -1,9 +1,11 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index ee81e552724d55c1343d86aece0bd6959a75d17b..da7a4d2c80985158094341f5be0c04efd045daae 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -1,11 +1,13 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index daf5d655d01f58b0dad53a847fcd34472f669eb1..506ac4382c74e718910bbecf2ad18c3fe38fd9e2 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -1,9 +1,11 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 4a6416e2540bdc37357a28a98238102e9e150a5d..63b205d2a75c2fd6d83f66b5aed3f002c7678c68 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -1,10 +1,12 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 429d4d814e658fd05de964b869957ce59694d817..96f2e3ae5d1a5584c15c161a09d4d32497d6167d 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -1,12 +1,14 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 3a3b81c8b83bf273d946ce844b485b11422f6add..2dfb48b3831cce46722d3c992c554eb9f6d763dc 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -34,10 +34,10 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET=y CONFIG_SPL_PCI=y -CONFIG_SPL_PCH_SUPPORT=y -CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_PCH=y +CONFIG_SPL_RTC=y CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 2969e90ca872fd8f830a7e68142e1351e7920ce2..cf5a03e8a2ff12f6ffdbb4deb46d1c034c2795b5 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -4,8 +4,10 @@ CONFIG_ARCH_QEMU=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40200000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 000cb3532892e3f58e6494cec00bec9a0bdab2af..ded58d387ad5e2d3287592802138fad9a0655e52 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -4,10 +4,12 @@ CONFIG_ARCH_QEMU=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_TARGET_QEMU_ARM_32BIT=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40200000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 73b2c99c6aea65b3b6c42a2b40f06c83c40874d0..16a24c30b214b6455d5e08fc561dbee5e3015f97 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -2,8 +2,10 @@ CONFIG_SH=y CONFIG_SYS_TEXT_BASE=0x8FE00000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus" CONFIG_TARGET_R2DPLUS=y +CONFIG_SYS_LOAD_ADDR=0x8e000000 CONFIG_BOOTDELAY=-1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200" diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index cad22615847378fd73fdbc9d1c155a665a8c18ac..8875a09b2c98c5ded62c62a7f5173bd7d101c584 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -7,6 +7,9 @@ CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig index 7ba4ac05f5e07f86859e7aec61352d7945c2d99e..4e52dd0070c128d9c15be8d7dcc6355cb849c3f2 100644 --- a/configs/r8a774a1_beacon_defconfig +++ b/configs/r8a774a1_beacon_defconfig @@ -3,12 +3,14 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit" CONFIG_RCAR_GEN3=y CONFIG_TARGET_BEACON_RZG2M=y # CONFIG_SPL is not set CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set diff --git a/configs/r8a774b1_beacon_defconfig b/configs/r8a774b1_beacon_defconfig index 6f1a6085ecd05f606452920d638aa4f39fe7ea7b..deb0d0e15ec738ee80fcd45523803e00b897d8ee 100644 --- a/configs/r8a774b1_beacon_defconfig +++ b/configs/r8a774b1_beacon_defconfig @@ -3,12 +3,14 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit" CONFIG_RCAR_GEN3=y CONFIG_TARGET_BEACON_RZG2N=y # CONFIG_SPL is not set CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set diff --git a/configs/r8a774e1_beacon_defconfig b/configs/r8a774e1_beacon_defconfig index 9cde39f4673f705dddd2b3025a2c84f1b6857bb9..92d0899e9a8c7c3f639331945d74784054b330c5 100644 --- a/configs/r8a774e1_beacon_defconfig +++ b/configs/r8a774e1_beacon_defconfig @@ -3,12 +3,14 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit" CONFIG_RCAR_GEN3=y CONFIG_TARGET_BEACON_RZG2H=y # CONFIG_SPL is not set CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index eaa67e22873227ae2b8a17de32772d0322c5ad32..bf6cdd538e35bbe0b3880d8b3787e71041fd1f25 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -6,11 +6,13 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x700000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot" CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_EAGLE=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 355008c851ea7198f2bafa52ede42dae18499633..1c9abad4d68dde1e9eac1e23817c6bb4afd4116c 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -6,11 +6,13 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x700000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot" CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_CONDOR=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 5ed4b958fbd0746692d7c3a4a2214d09f7c835d7..6ba8b3a502afbfc03c1f463f8dc88501ad622c3e 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -5,11 +5,13 @@ CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot" CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_EBISU=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -18,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" CONFIG_UPDATE_TFTP=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -54,10 +57,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x70 -CONFIG_SYS_I2C_EEPROM_BUS=7 -CONFIG_SYS_EEPROM_SIZE=128 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 41bf992272437ff69fbb8b47a7a44c36b2510221..23a4c87e73a42cd7d771311a2edf6c4e31fb3d42 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -5,11 +5,13 @@ CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot" CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_DRAAK=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index 4b80c8f87a9f1c02ea823247b02c909b02295cc9..0151ca5dfd6e44116bc0eb227fc2f8bf2595dcac 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC00000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot" CONFIG_SPL_TEXT_BASE=0xe6338000 @@ -12,6 +13,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_FALCON=y # CONFIG_PSCI_RESET is not set CONFIG_ARMV8_PSCI=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 82dd4e42e7b1021b8f9a76727f4b8da70c1591a4..1e9def2bb21fa51f0ec451c82f99d10e24d10578 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -7,21 +7,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_RASTABAN=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -76,6 +78,8 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index f48adf996a44cdcc944b6ff4456ed60778872195..3b48ab2751b2240112da28e5573046fdf5dd9feb 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -3,11 +3,13 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot" CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -15,6 +17,7 @@ CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb" CONFIG_UPDATE_TFTP=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -55,10 +58,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x70 -CONFIG_SYS_I2C_EEPROM_BUS=7 -CONFIG_SYS_EEPROM_SIZE=128 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index 6e9382b96c2cbba852f4272f524a7d59759bc4f1..1213baa6146a49e75e8cc0227ff7bc073cdb28b2 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -5,11 +5,13 @@ CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot" CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -17,6 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb" CONFIG_UPDATE_TFTP=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -56,10 +59,6 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x70 -CONFIG_SYS_I2C_EEPROM_BUS=7 -CONFIG_SYS_EEPROM_SIZE=128 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 2f4553604ef1069b6bf52ef53fc2da4da5e04307..1fb708433fcee4d3e84474e92bb40633dac4d882 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -7,17 +7,21 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 +CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg" CONFIG_MX6S=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -40,6 +44,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 257893edcaad150fe91b66b33aed5cb55181bd58..59c101e4f0d4ec4d1b21a70aab16d7cb1b3bf996 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00600000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -13,6 +14,7 @@ CONFIG_SPL_STACK_R_ADDR=0xc00000 CONFIG_DEBUG_UART_BASE=0xFF0C0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 4351a5f4bc8b86961251c1ef59384f9ee588bcf1..cf04bbc768f87ff19db12d58d27795cc6f96c482 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -15,6 +16,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -69,6 +71,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 8d0f57021b94378e6655aa6fb0c05f9d4f860b83..199624fe0df846a59faec8f80cfcbbc62b4d4d32 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -12,8 +13,9 @@ CONFIG_TARGET_ROC_PC_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 4e5c90439d3964a1ef89caccb2ed6b7dbd57b81d..bc124c8fec6f7903181bd6c5578f5b6af80874c6 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -12,8 +13,9 @@ CONFIG_TARGET_ROC_PC_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index f01b6a3935413f050c0838073b83c29c2da4148d..9366eba8f15d9b533fd0fe0aa8ab2a367fcfd7b5 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ae35633292ecee0534a687397b361aa548f13d2a..ac045d1492f1d64be26fd62ca5acbde14375138c 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -9,6 +10,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 4816b1ebbee71d7e4d8bb8f1bb7880e301c74764..520ad8aa883800f6cee4e112cd933e1d49d1c139 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -16,6 +17,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index e5df6779decd05252fd9833e5983193e45348d2f..0b89ae9a8a8bf105872bafa73db260ed0bf9af91 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -10,6 +11,7 @@ CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 935f569db5cfeb843c7155978ff3589f7498e660..c06094145ea593d2a3750121beb101f9c964d611 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y @@ -12,6 +14,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 2f1743a7065b5bc69ef1e91c5bcd14e69d07fcf6..c9a5ba2bba52480f2118fcb98899f2808790fe7a 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 @@ -12,6 +13,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb" diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index f0ef1e5c98f45113e44f8d32184a9ca1a1ead2e1..38b91569c23d216ac6945fa7d35a125648ed1660 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y @@ -15,6 +16,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -68,6 +70,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 0233e0ea5276d210a78e4c91addf0564d2be85be..e46f07e74d24531170f0924eb689e6b44e43993f 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ENV_OFFSET=0x3F8000 @@ -8,6 +9,7 @@ CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 91221736061e7926a33632eb45de1f0e66853cd2..bc97636d10bbb4228fc02056a85ead81d0d04d41 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y @@ -14,6 +16,7 @@ CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x60800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index ae11a8f5eb0f6dec21c844d1404b4185deecf732..637c5c2466cc834fb82b1326ac4d0457bac0485d 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -10,8 +11,9 @@ CONFIG_TARGET_ROCKPRO64_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index d17e1020525f1d8ae227aece6e4e8700a54f81df..6d76d12910d3c84553bffbc875fe067388514358 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 8b8affb77745366f01f8f7a0848cb73e83ca6080..19316071322ac9017d926d033c3c92e422bae299 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00008000 @@ -7,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index b867b7fa7bf3dfb5af54de0e6edfe3bbf9fe600f..827fc423453d794ded152fdf16e742354532cf1b 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00008000 @@ -8,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 043665c3d1aa0118ec17a3085ce9baa579fe0832..e99a7dfbd2012e66e315f4d49be18b2f434ddb29 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 3cebd657da7b258003567e0b0f2c8df08c6a3bfa..5df388437372f8e11ef93f1974e8ee56f9415bda 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index b813d0463987b5353cb114243275cf2d0e908cd1..d592df50706c52aad9e090d017c4f9b8d9e03f9f 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_RPI_4_32B=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x4000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index de2658ae88d6111cd7cbfe6e58cfa37aa352d296..ab5cc90d912f3b9efce4313a19cfade95d8efb31 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_RPI_4=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x4000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index f90107e548e4555c7875b9ec5071bc7977a02082..382d99dc2eb4920928cfa4feb7b0e23e9292b4f3 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_RPI_ARM64=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x4000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="pci enum; usb start;" diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index af2189b8fe2a626fd0ac254e2c9dc28c2401a160..8acf04d0e43214bf471e5e0013673762db7f7b6a 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 01b993087529479c3591d54e7cf0c5e5545ee6bd..39f9a0cd3731b04d91c417f1571ddc274e01fd9b 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -7,20 +7,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-rut" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=600 CONFIG_TARGET_RUT=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -42,6 +44,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_CMD_ASKENV=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -75,6 +78,8 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig index 313c6575cda6764069defcf16d2f6b7ea5222b1c..4467e66929962c5f6f0d814d5a1fa59bd04b5f30 100644 --- a/configs/s400_defconfig +++ b/configs/s400_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" s400" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index d99c30b6c39f66034b7c3f3ce199ce6f095f73f7..eb6098947632b38703b2ed8f686184a1e6cc240b 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x71000000 CONFIG_SYS_MEMTEST_END=0xb0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x2E0200 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2" CONFIG_TARGET_NANOPI2=y @@ -14,6 +15,7 @@ CONFIG_S5P4418_ONEWIRE=y CONFIG_ROOT_DEV=1 CONFIG_BOOT_PART=1 CONFIG_ROOT_PART=2 +CONFIG_SYS_LOAD_ADDR=0x71080000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 59aec970aa91042a490754f6351ba04438d27220..1783bec0da0eba09be45db18a240b5557dd8f114 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -5,9 +5,11 @@ CONFIG_SYS_TEXT_BASE=0x34800000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 +CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" CONFIG_TARGET_S5P_GONI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x34000000 # CONFIG_AUTOBOOT is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}" diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index f6bb60e9ca8d1750290752e3b18b5a8cfe9f74c6..231eeb2d0d0ff5958781731ffc8c5d209fdbf094 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x44800000 @@ -7,8 +8,10 @@ CONFIG_TARGET_S5PC210_UNIVERSAL=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 +CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x44800000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="Please use defined boot" # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index d29a19e7415e9d1fa15c0f0f4ba305edb47eb3e5..35ce6ae8776d6aac08dfe8a85b53097ce7cf1979 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -6,10 +7,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6338=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index e1fceec4bb5b560f68e76d884988d095c112cc84..178f113d7bfec8cfd243cd4e75fcaa9fbbe74b22 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -1,16 +1,19 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_SAM9X60EK=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 @@ -44,6 +47,7 @@ CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y CONFIG_AT91_GENERIC_CLK=y CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y CONFIG_AT91_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_AT91=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index 35368f3139bd09c11699a4f517be4a3c89e7c3a7..67924fccfc031a646b41a3b97fd88560a73823c9 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -1,9 +1,11 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_SAM9X60EK=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -11,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 @@ -46,6 +49,7 @@ CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y CONFIG_AT91_GENERIC_CLK=y CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y CONFIG_AT91_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_AT91=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index 1c6abdc476db6fbef0bd7deb9cc7d65a658d8ac2..07bc7537785a41fab4bf18a763e3bcbdacf92092 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_SAM9X60EK=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x81000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" CONFIG_DEBUG_UART_BOARD_INIT=y @@ -12,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 @@ -54,6 +57,7 @@ CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y CONFIG_AT91_GENERIC_CLK=y CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y CONFIG_AT91_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_AT91=y diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig index 2d13dc2145ab4eddbe15b3f0d1da5d64c490ca0a..169b693079484b8b8a510f32c0ace23d8bdd9df5 100644 --- a/configs/sama5d27_giantboard_defconfig +++ b/configs/sama5d27_giantboard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 0326cd3d37a045f721c5883f95bc0b3fecf9ff5a..e67e37bfb4e5f54b237aed648cc379f65bb50121 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 @@ -11,8 +12,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -22,6 +23,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index c606c8a12e9c03cd4b4ea2b56b5b5bd460096dfc..0fe64ee40d922e9514022c4dde7a5dc44d5d5b5f 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 33a0cadb580266d457e23c1c7a53f4806069dcd4..be214d92f703ab44194cb21a4fe9c45e25cc508f 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_QSPI_BOOT=y diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index e88b0799d8a00d9d9461a404c43a381feafac623..041a7609076008e765073e47fa1f2e34112966ac 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y @@ -10,8 +11,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -21,6 +22,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 5902a933c1ad18ef1f25f4932ecbcc8b2581fb31..1b16bc075c7beb779b967935f2c52acfd2af6e1c 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y @@ -11,16 +12,17 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_QSPI_BOOT=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 54f5a314be79cba1866cbd55963684a3f9ca769b..df3b430b34a480ba2289f4c1ebef361414d8b6e1 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -10,8 +11,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp" -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -21,6 +22,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..bf442bff2a2696fe4de14abf48d7f0afb5f20993 --- /dev/null +++ b/configs/sama5d2_icp_qspiflash_defconfig @@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f00000 +CONFIG_TARGET_SAMA5D2_ICP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MEMTEST_START=0x20000000 +CONFIG_SYS_MEMTEST_END=0x40000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp" +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlycon earlyprintk=serial,ttyS0, ignore_loglevel root=/dev/mmcblk0p2 memtest=0 rootfstype=ext4 rw rootwait" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CONFIG=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=2 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=66000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SF_DEFAULT_SPEED=66000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SPL_OF_LIBFDT=y +# CONFIG_EFI_LOADER_HII is not set diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 8e8d41bb509ee6345f854e06b26c3e89b612806a..5f7dbc6a04a91d39f4340753d9d3a74ff6e22a65 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index cd73859db1201043f5671a09a7e2e931f558a3be..e7b48d687286fcec90d8098baa9abfca6a6e709a 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_CLOCK=82000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_NAND_BOOT=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index 9bf34b885ee524caadef23ef7fbd3e3413e6d2e2..2bf4613cbc7d96184e2d043b2c61aaa2a09873db 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -11,8 +12,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -22,6 +23,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" CONFIG_SD_BOOT=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 5871e7bd089c83643c4ad4462bcd34dcb4eaa28f..d7d577ed171f5fa6b6961e2e8cc4d65dd30bc651 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" CONFIG_SD_BOOT=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 16534fbc2f4a009e3cfe45fb90d5efd527ab546f..03e832ba204a05666fa17a6460ae59cfef2371c2 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" CONFIG_QSPI_BOOT=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 7a8df06249b1f265d9739105b1f12c15d0a865cd..1d43c77adeb420a7af56590cf73a896244eaf04d 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -15,16 +16,17 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 0077217492d9cb4a28dbf15efdf64defda7e32b6..828a79e46a986ddc1ffb5e637d3355686925d749 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index ca072f481c1a242091788cab74d226ea06f2c153..e6418138d69e5fbe41e7fc7ab672cb3e721af18c 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -13,6 +14,7 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index f4d13a5ac7358b676a965337563766319386f2bc..35241fd75a6a99812dd84e70c3d24d45dec742b2 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -15,6 +16,7 @@ CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 1045758824bc2aec24e2f95c49acab7af9906e54..2833717386d430b211c82bff72d331be5d95f335 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 594424d681c7500aa33d67be9d955957d167c99e..0fd2c4259c426969918cfedb6061bc0a98bec2bc 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -11,7 +12,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -20,6 +21,7 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 106e91db92e90883ed82b8cc2fa7677b62938ace..e1a8ab702547fafbf31bec59e2130e79022ac3ea 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 2d7d349d63120edc0779f0fb8c181679f02c9a75..2e1fdf7b6f1f5e32ca889642e569da905c88860c 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -11,7 +12,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -20,6 +21,7 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 307f1fca9bebb509e469079afa14b93c20db08a6..2d22e2d229f19d8cfd193786654736043efe3ecd 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -15,16 +16,17 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 68747d8a79cced051dc60e86209117107fc2c5ea..4e5c513c4dc7a17b6a2c24641428cf3d22b662eb 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index c6ff96b1bc0a145542866558b63baa7a7b7be80a..e64240926d9fb68349c9cb56a1f29ce3f88d7138 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -11,7 +12,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -20,6 +21,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 42829057b4899d2d01e89edbe88e131c50c590e3..ba529db3b61787337aaa25c1c3ad52f987b9f906 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -15,16 +16,17 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 098e6ba49bd5884c27241d87534a30f5c4257f4c..bfd4d89d23f86caa6089679e5eead189895d3c2b 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -12,8 +13,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -23,6 +24,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index fd285a757f7daa045bbd897f67459d2a099f9b93..a3cd8c5300e3db85ec429744760d0210d62de5de 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -11,7 +12,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y @@ -20,6 +21,7 @@ CONFIG_DEBUG_UART_CLOCK=88000000 CONFIG_ENV_OFFSET_REDUND=0x100000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 662568a955deb5e53fce5d43d659b16c4480b352..9896076e2d5399eaec2e424c4f31f191818afe52 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 @@ -15,16 +16,17 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" CONFIG_SPL_TEXT_BASE=0x200000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index e076e07e11cca223541208c49d5fbed964547677..bb03db4c0f0d6d19b08c7273f320018280aa89fa 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -14,10 +14,13 @@ CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index 96549c23f8170b3dd7a56bd5963de1e71f96724b..b5dd64c6125ee0c7f710d6ab05bc6e992bad3d1a 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -14,10 +14,13 @@ CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index f7098b49698311b5025d16c9dbd67f2cf7d4fd5d..df9633d762a2d908dee590eca5376cbeb967f7b1 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -3,12 +3,14 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="sandbox64" CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_SANDBOX64=y CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -223,7 +225,9 @@ CONFIG_OSD=y CONFIG_SANDBOX_OSD=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y +# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_WDT=y +CONFIG_WDT_GPIO=y CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index ea08a9e5bd18c10d7f7666c55ef4946aee4ffbfe..f1067b9adaaf3520c93412c44b6c6758ba3ccdf3 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -3,11 +3,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_PRE_CON_BUF_ADDR=0xf0000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_RSASSA_PSS=y @@ -281,7 +283,9 @@ CONFIG_W1=y CONFIG_W1_GPIO=y CONFIG_W1_EEPROM=y CONFIG_W1_EEPROM_SANDBOX=y +# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_WDT=y +CONFIG_WDT_GPIO=y CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index a6e2544dc138368fc5a76e568399cb04bec0473a..11015744e7a4d3ce0603d866f006781df124f145 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -3,10 +3,12 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index 88443f5ab2744e854e163d054ca840a250d82075..b3584563d245deabf51b4f54c7c2e24f4f5552a7 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -1,12 +1,14 @@ CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y @@ -14,6 +16,7 @@ CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_SANDBOX_SPL=y CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -31,7 +34,7 @@ CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_RTC=y CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y @@ -120,6 +123,7 @@ CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y +# CONFIG_SPL_DM_I2C_GPIO is not set CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 77dd83cf6fddcedb8f750136bf5c16aa000c3c74..73cf5dd2b0457e43a492a7d4230a7d3aa579a226 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -1,12 +1,14 @@ CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y @@ -14,6 +16,7 @@ CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_SANDBOX_SPL=y CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -32,7 +35,7 @@ CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_RTC=y CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y @@ -122,6 +125,7 @@ CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y +# CONFIG_SPL_DM_I2C_GPIO is not set CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index aef9a1c681b6c89775076fc7d5c5b19a5243eb90..7a32f36ff4caed30ac11df83b8b8327967451474 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_SEABOARD=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index dbe0171ce128ff646b9b1144dd5966d1027d21cc..caff2a69add839b64245d7c328440427e2414b2b 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -10,14 +10,14 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3c00000 CONFIG_MX6ULL=y CONFIG_TARGET_NPI_IMX6ULL=y +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board" CONFIG_SPL_TEXT_BASE=0x908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index 8099b40b556e1a1622311806044fcd4af44217fc..7e60922f33fcab1cac6020cb20755424e2e1a91a 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xFFFF0000 +CONFIG_SYS_MALLOC_LEN=0x8000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510" CONFIG_MESON_G12A=y @@ -14,6 +15,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" sei510" # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run load_logo" diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index e11f36ac798e95bf5692738ceafdb97b2ecc72c6..6a45c5e1472f4dd338edc739ee8c33e5bed0b77b 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xFFFF0000 +CONFIG_SYS_MALLOC_LEN=0x8000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610" CONFIG_MESON_G12A=y @@ -14,6 +15,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" sei610" # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run load_logo" diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 097d583430249304ca9753f91a49a0a3002652c7..bbcb944212be71d8ef7dbc94a1272c07c3b7a013 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 @@ -7,10 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" CONFIG_ARCH_BMIPS=y CONFIG_SOC_BMIPS_BCM6358=y CONFIG_BOARD_SFR_NB4_SER=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 60256d19fdabd0a74e3d3d39e2dbf16e7a3e2e39..61a2d5a66ec5a5122063a0f95222dd85f8d42646 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_NR_DRAM_BANKS=1 @@ -8,6 +9,7 @@ CONFIG_TARGET_SHEEP=y CONFIG_DEBUG_UART_BASE=0xFF1b0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index d09789a96e08d3c04507b56170ed87d169066d3c..24d416e7877b87c61d6e7aef0bde924e3f27fcfa 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y @@ -11,6 +12,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index fd686dfadc9e826299ab92f3816ad9377a3dffd2..b9e4d8d64495227d2ce09d1debc2328013578c00 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -2,16 +2,18 @@ CONFIG_RISCV=y CONFIG_SPL_GPIO=y CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_TARGET_SIFIVE_UNLEASHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb" @@ -22,7 +24,6 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 1dde98e0aef41c8359adaaa50455e2e946b1893a..55646550d3ad6b4f076c3484fbc4efb61fb86274 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -2,26 +2,28 @@ CONFIG_RISCV=y CONFIG_SPL_GPIO=y CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_AHCI=y CONFIG_TARGET_SIFIVE_UNMATCHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_SPL_USE_ARCH_MEMMOVE is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ID_EEPROM=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y @@ -32,6 +34,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_SPL_CLK=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_E1000=y CONFIG_NVME=y CONFIG_PCI=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 0377c9e28e90022839f2f8b5204cf44a93e63855..1c340ea45042a21a0a4c5c2626becceceeda6772 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -6,11 +6,13 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3F0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot" CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SILINUX_EK874=y +CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 020e6b0d0f06433d71fc2e6699855fc47cd99941..4a3b15ef957cb0515ce8b4575f287178d9606ddf 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Silk" CONFIG_R8A7794=y CONFIG_TARGET_SILK=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 33c67c0b540366a6d14f80d082b8cc428f8e40f7..4bfb6eeb1792e03e976ef71bc10708f36425ef34 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -2,8 +2,10 @@ CONFIG_RISCV=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y +CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_STACK_SIZE=0x100000 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run k210_bootcmd" diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig index c20c389cace85aed7f9a3de11bb988bb47061c60..2ab06725999f610b7901002bd3dd4c4864c3bd71 100644 --- a/configs/sipeed_maix_smode_defconfig +++ b/configs/sipeed_maix_smode_defconfig @@ -3,9 +3,11 @@ CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y +CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_STACK_SIZE=0x100000 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run k210_bootcmd" diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index c171ccad2a70b41dd323a340582a2b941d07455e..38696358151148b1786ccecea5cea4d044d298ef 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SPL_SYS_ICACHE_OFF=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SPL_SYS_THUMB_BUILD=y @@ -13,10 +15,12 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb" CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" CONFIG_BOOTDELAY=3 diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 3ed1947fd682ed44941830a78f71953e0e5f4f08..f1d38eea669bc5f78a78fd36821e84aa728a99b2 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -10,11 +12,13 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3FC000 CONFIG_ENV_SECT_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" CONFIG_SPL_TEXT_BASE=0x02023400 CONFIG_SPL=y CONFIG_IDENT_STRING=" for SMDK5250" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -38,6 +42,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 7b739400a5bfc5ba6f12b64ebf9338ee2f7f60cd..fa0c2ea752b151e181cb2d54bbeb74d5372ba8c2 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x23E00000 @@ -8,11 +10,13 @@ CONFIG_NR_DRAM_BANKS=7 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3FC000 CONFIG_ENV_SECT_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" CONFIG_SPL_TEXT_BASE=0x02024410 CONFIG_SPL=y CONFIG_IDENT_STRING=" for SMDK5420" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x23e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -33,6 +37,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index f9df12813552a74c118e3c8af46ea9323594848e..5bbe19973c1e070ca5af8270f9e8446b5074ef16 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -4,9 +4,11 @@ CONFIG_ARCH_S5PC1XX=y CONFIG_SYS_TEXT_BASE=0x34800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" CONFIG_TARGET_SMDKC100=y CONFIG_IDENT_STRING=" for SMDKC100" +CONFIG_SYS_LOAD_ADDR=0x30000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)" diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index ac84fde7d3180fb564df522101d5f99d58918e26..ba773dc12f5497e3518fcf8a7e06bc0e0aa95643 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -1,15 +1,19 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS4=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4200 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" CONFIG_SPL_TEXT_BASE=0x02021410 CONFIG_SPL=y CONFIG_IDENT_STRING=" for SMDKC210/V310" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x43e00000 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_SPL_FRAMEWORK is not set CONFIG_SYS_PROMPT="SMDKV310 # " diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 75fd5bc24a81816277ca0c4c9c4b23763b1ab36c..7a779f3429a06a3966bd4c533de123d27b2bdc3a 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01" CONFIG_TARGET_SMEGW01=y @@ -14,7 +15,6 @@ CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/storopack/smegw01/imximage.cfg" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index f9cc1a6c7e9f4a5782a29d1453e33bdf3e9cc538..87bb607d305c30f8c04e834d71a7d50b13590243 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -6,6 +7,8 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_LOAD_ADDR=0x23000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" CONFIG_BOOTDELAY=3 @@ -33,6 +36,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_TFTP_TSIZE=y CONFIG_AT91_GPIO=y CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x7F # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index e3a325a271000ec7a74225506fc5fed7770895f5..6fd58ada506eb8258b682b682d4ce15bc459c37d 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 @@ -6,6 +7,8 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_LOAD_ADDR=0x23000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_BOOTDELAY=3 @@ -32,6 +35,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_TFTP_TSIZE=y CONFIG_AT91_GPIO=y CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SOFT=y +CONFIG_SYS_I2C_SOFT_SLAVE=0x7F # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 20a8211f615ce63dc0f2a79b19cfe0c52fa1e36e..76e77e8ec486d1bd21575c05e3cc7db0e47d5584 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -3,6 +3,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_SNIPER=y CONFIG_SPL=y @@ -22,7 +23,9 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NFS is not set CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_OMAP24_I2C_SPEED=400000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_SPEED=400000 CONFIG_TWL4030_INPUT=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 diff --git a/configs/snow_defconfig b/configs/snow_defconfig index a5fbd1d346da9e291bdc8266cfec3b6d1ce97c4a..407777c032aca768ffd081dd85968f6b773f2d95 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -10,6 +12,7 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3FC000 CONFIG_ENV_SECT_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" CONFIG_SPL_TEXT_BASE=0x02023400 CONFIG_SPL=y @@ -18,6 +21,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_IDENT_STRING=" for snow" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -43,6 +47,7 @@ CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_LDO=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 414f49be6739c0d2f41febff84b2f516a285e864..a44f6e429dff3c20a873380f9b2e3109115ee240 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -6,12 +6,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 87fa61d6d9752c686f1bd788273ff528284dd138..1ad41036796658a21beb50c58d734047e67aedfe 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 @@ -14,6 +15,7 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y # CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index c8028275ddf642d6016f6ddb8d7b034ad9484e86..9d3ec539ab58a29107b493d1e825de7892809ebe 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 @@ -13,6 +14,7 @@ CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index ef9bbb9c3ac5a01028164218960d3ef302910daf..bf793d967247f21c730eab743825228adb36c8f0 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_SPL_TEXT_BASE=0xFFE00000 diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a295aaefa329e33324bb7cb0b5471652f9378f86..fa729cd26eb56e06eb24a1635938b21764f06601 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index ad6a417eba93cf434874dcf5ccf7e4bd75192a10..456b0d55f157efa35ab1f16f0ec97114c38b2af8 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index c2b2cf4563e89da398b5a7541b3c0ffdcc402a4c..20d7f5b5307b9d68244dc9bfaa96ddf040bdde2e 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 4539d08dea5809a39585784f714a0a66c0ca0264..17c160dd2aab9844a6fe510b8a213dab4edaab8c 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 3b31fdb6a3742d7034e964954779fdcea1d0c5bd..0a356280e7917f4dd964b7db7f898fbbf585aefb 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 945ff08d5b6238ddac9bd7d120e20a1453ecb3a1..7108486e598d8f188737ac57e0f6e45f4b87efcf 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 723f82457540b8d51c9399ab67cda7c992600f26..1913b6f865502254b5c4eff8f7c437cb67ae0bf5 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index da25479a0f2e03800377efef567d402c0764e2fe..9d039174d0e4fdc57aed8a1fde47787dd06f4381 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 3b5246ec359d2887fa770467fab56d1fef9d51c7..7961fb27ebe34d8905ebb81a58f125d5d0446a55 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index a5649aee5381ac53551576fa8cfb5e20b177a557..02175b0c0e4bfa05a5e35cb0670674799db5c516 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index cb3f3a9afb11ec50f3c752a755e945c661158732..8847d9189d40fe5777c4d8b0910f4ac099cfe79f 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 854efe33627dd8ccc949ec34b30757e1fd4b9206..963215d14327ff4eb4d921f05120569d80839434 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -3,17 +3,19 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1" CONFIG_SPL_TEXT_BASE=0xFFFF0000 -# CONFIG_SPL_MMC_SUPPORT is not set +# CONFIG_SPL_MMC is not set CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_SOCFPGA_ARRIA5_SECU1=y CONFIG_ENV_OFFSET_REDUND=0x120000 # CONFIG_SPL_LIBDISK_SUPPORT is not set -# CONFIG_SPL_SPI_SUPPORT is not set +# CONFIG_SPL_SPI is not set CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\"" @@ -31,6 +33,8 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=1024 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -61,8 +65,6 @@ CONFIG_DM_I2C_GPIO=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_EEPROM_SIZE=1024 -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 301df41b326edffc0912959e1f55bc071e34e7ed..ebb9fbeb76e22421376e40fcc10246bc4d6ebf1b 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 64e7d4f4a2904f88033f0e5bc6220bc0ecc909c1..b5fd445efbe7ab0c3b6929fb78ca6d5dfd9ced51 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index ff1df8ff4e380ac43ee6fc0e24e65ceb211998a0..23261aeb890d307b05a762d49f4612b1e335e372 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_END=0x40000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_SPL_TEXT_BASE=0xFFFF0000 diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 43c583bdaeaa8439c15c8337591cf558b827361c..ff0373e5f8dd5f0e158a985c20640ff61f6493bd 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -6,12 +6,14 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index c352c451f87d4d5d1eb123b201564a91f406e61b..a7f39913ab11b38a4e6cf11df12c92cbfdce2200 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x3fe00000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 +CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_SPL_TEXT_BASE=0xFFE00000 @@ -16,6 +17,7 @@ CONFIG_SPL_FS_FAT=y # CONFIG_PSCI_RESET is not set CONFIG_OPTIMIZE_INLINING=y CONFIG_SPL_OPTIMIZE_INLINING=y +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon" diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index cbdb897f19f1d8627a8b40bde2efc6d7eec930af..5e7fda3bef2ccb9e0f78f13c6f2ad2dfb8302661 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" CONFIG_SPL_TEXT_BASE=0xFFFF0000 @@ -27,6 +28,8 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -71,8 +74,6 @@ CONFIG_LED_STATUS_CMD=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x0 diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 0c407b3ff9b72e6834a0672877ab70ae291e712f..6523d2a976a0e09ad3f9a2f1cc4a8d9ef0e3f8c9 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_MX6ULL=y CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 53c375e5b4f2f8212c68677e4daea41ba9a1b257..a9062b29ad26c802955e26d7a77b9215826ecf53 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -10,6 +12,7 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x3FC000 CONFIG_ENV_SECT_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring" CONFIG_SPL_TEXT_BASE=0x02023400 CONFIG_SPL=y @@ -18,6 +21,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_IDENT_STRING=" for spring" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_SILENT_CONSOLE=y @@ -43,6 +47,7 @@ CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_LDO=y +CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig index f31960b81473b4edb61613aa810dd3809facb24d..cf86146696c62d5f92114ed715cf80a3762fa453 100644 --- a/configs/stemmy_defconfig +++ b/configs/stemmy_defconfig @@ -1,8 +1,16 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_U8500=y +CONFIG_SUPPORT_PASSING_ATAGS=y +# CONFIG_SETUP_MEMORY_TAGS is not set +CONFIG_INITRD_TAG=y CONFIG_SYS_TEXT_BASE=0x100000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy" +CONFIG_SYS_LOAD_ADDR=0x100000 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run fastbootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CONFIG=y @@ -14,5 +22,17 @@ CONFIG_CMD_PART=y CONFIG_CMD_GETTIME=y CONFIG_EFI_PARTITION=y # CONFIG_NET is not set +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x18100000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 # CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_USB=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 +CONFIG_USB_GADGET_PRODUCT_NUM=0x685d +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MCDE_SIMPLE=y # CONFIG_EFI_LOADER is not set diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 071dac96aff6c398d68810ebaac0c1f976d64d57..d5ec00e1e03e95c346c8f63b240a2e5bdb8e7944 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -1,11 +1,14 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_STI=y CONFIG_SYS_TEXT_BASE=0x7D600000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 +CONFIG_SYS_MALLOC_LEN=0x1800000 CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260" CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index b0dcb38b3bdf68443f59730e18ca70eaafefa107..b6388cf00a32c91a3ca1113439ab843081477289 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -5,10 +5,12 @@ CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco" CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x90400000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index b614182b4fe78fa44e92651e5adf0fe75c4c603c..a75c269d9b7592b4c99975dbdb6ee35db9708c3e 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval" CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_EVALUATION=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x400000 CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 7960618d4654ef462add84dd473cb8b4e71fccb2..ecca110850114a8446109406b7bbce35b0e481be 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco" CONFIG_STM32F4=y CONFIG_TARGET_STM32F469_DISCOVERY=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x400000 CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 05d7ec2d79be1a89c22f6a9fe2b78b104dd3310e..2694a32f7dd741b96f482a7b620d9847ed93c8e4 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -4,11 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x08008000 CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 40f94ac7728ec0aaa2a933ed27358dec4c9e7103..10af6388403c528c36d4ceddf1ebfdec692d1e4c 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -4,11 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x08008000 CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index 03c17867eb67818fb11c2040142e1c809c9dd045..d62913a4bf323614321eb18203a5c76253bf93e3 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco" CONFIG_STM32H7=y CONFIG_TARGET_STM32H743_DISCO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xd0400000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index 9d78fb7fe826f1e94f14a2abc2114c22a223fe0d..042d042e0ab7ef8508e0e1e7e22a58c43fbbc5b4 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval" CONFIG_STM32H7=y CONFIG_TARGET_STM32H743_EVAL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xd0400000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig index 1af66c5b1bc1288be6c09b499f19c340a91b5a37..66a5a4ffdfe2cd3e67725b2e74e8ee0964d96a69 100644 --- a/configs/stm32h750-art-pi_defconfig +++ b/configs/stm32h750-art-pi_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x90000000 CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi" CONFIG_STM32H7=y CONFIG_TARGET_STM32H750_ART_PI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc1800000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index a7e5f566b0d4c0df68cafec813c8827316fe28e8..14bf6d1376a3f4db89001490223ee9a564fc6cec 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -6,12 +6,13 @@ CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_ICORE_STM32MP1=y CONFIG_ENV_OFFSET_REDUND=0x2C0000 # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index 4860ae445119524c5332f97aa1d978523700860a..648ecbfc6766f53f0eebe23507c42b2eb7404d05 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -6,12 +6,13 @@ CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_ICORE_STM32MP1=y CONFIG_ENV_OFFSET_REDUND=0x2C0000 # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index b0753651825b8ed8bfbef7469027a1c8ad5a2022..f422ffbedaa4ffb170a7bbed80f244619cc90408 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -6,12 +6,13 @@ CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_MICROGEA_STM32MP1=y CONFIG_ENV_OFFSET_REDUND=0x2C0000 # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index be68c8a39723ab2e006f5a9c25f677396267d42a..244d9ccf4edad740c88af7bf9a580bec6aa61d2d 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -6,12 +6,13 @@ CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_MICROGEA_STM32MP1=y CONFIG_ENV_OFFSET_REDUND=0x2C0000 # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 9cf6ab1f0f6a94633d8b3a4a530469f07166fa5b..b9a9cdc450cd376d9df7e11512d83e999dd98744 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_ST_STM32MP15x=y CONFIG_CMD_STM32KEY=y @@ -16,9 +16,10 @@ CONFIG_CMD_STM32PROG=y CONFIG_ENV_OFFSET_REDUND=0x2C0000 CONFIG_TYPEC_STUSB160X=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index e725b916b9c46f90d6fc6d4763b2afe433f4e3c9..74a7c12d379c08e6cdf8cfa68093ec62c4e7f2c0 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_STM32PROG=y CONFIG_ENV_OFFSET_REDUND=0x4C0000 CONFIG_TYPEC_STUSB160X=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index c2227c06b06a340dd8065f2ee0e700bbc0c8e460..5b85f6ad03b3fa915487a47ebdd150aec97b94cb 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -8,13 +8,14 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its" @@ -35,6 +36,7 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y @@ -93,7 +95,6 @@ CONFIG_DM_MAILBOX=y CONFIG_STM32_IPCC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 11750cb67bc53e3ce5abd74bf494c2bb675193dd..37dd2754c033a80f42034bc66146ee073ee953b1 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -6,13 +6,14 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96" CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its" @@ -33,6 +34,7 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y @@ -89,7 +91,6 @@ CONFIG_DM_MAILBOX=y CONFIG_STM32_IPCC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 2e2f0c76cac7e3ea5eff631eadbf7fe49b8fedc6..04564e21fa99246121f7f1ae7eb3e9430bc1aa65 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_STM32PROG=y CONFIG_ENV_OFFSET_REDUND=0x2C0000 CONFIG_TYPEC_STUSB160X=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 408d104e32baa600da611a22340f35674be89727..bca22c5830ff69503b1f358da1752c4c00d17a2e 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -3,8 +3,10 @@ CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="stmark2" CONFIG_TARGET_STMARK2=y +CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1" diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 0fb8affa633113eafffc0476aebd1c0b3d7aaf42..b4a5290f22d9b34be380d3e1d4999f08393aa8d5 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -12,17 +12,19 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 CONFIG_ARCH_RMOBILE_BOARD_STRING="Stout" CONFIG_R8A7790=y CONFIG_TARGET_STOUT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 7fe5f99f4d4725ae06ec52d1cdbcfbdb2d9dfa5d..b6ec831e6dd486d6e62136b1b103b56faad4306e 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -9,7 +9,9 @@ CONFIG_SYS_MEMTEST_END=0x00100000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x30000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x14000 CONFIG_DEFAULT_DEVICE_TREE="stv0991" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_SYS_EXTRA_OPTIONS="STV0991" CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 4dcc1190a3d1c9cce748e05958edac3e2df9de76..3fee7c2e50c0d159a233d5a5237d3fc4a6ec4847 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -12,5 +12,8 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 13736a4f039d8851caeb2211705e23598e315dfe..a88856b272710a4db00ead61390a0a5f520d9e18 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -1,14 +1,15 @@ CONFIG_ARM=y -CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SYNQUACER=y -CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_TEXT_BASE=0x08200000 CONFIG_ENV_SIZE=0x30000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" CONFIG_TARGET_DEVELOPERBOX=y CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_FIT=y CONFIG_BOOTSTAGE_STASH_SIZE=4096 CONFIG_HUSH_PARSER=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index b5ec025db9c3af4af137fb8c73e7e1034aaa5e9d..6e4e101a8813839c6dd3c6c8ddc326860379a010 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 80f75ce3d2acfe0e9580d824ed4c9a0ee670caff..0bb28d4d12f76b8f53f60d6885fe39e3ec30cbf3 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SPL_SYS_ICACHE_OFF=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y @@ -16,6 +18,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 @@ -24,9 +27,10 @@ CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067" +CONFIG_SYS_LOAD_ADDR=0x22000000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 99ef8a1192254188eab6f5e34996e53565d3b91d..96dc4791d96f8461fab6100872046b5e6acc5199 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -2,8 +2,10 @@ CONFIG_ARC=y CONFIG_TARGET_TB100=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_ENV_SIZE=0x800 +CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" CONFIG_SYS_CLK_FREQ=500000000 +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index a14f9d46c9d25f506de784f882018efe62989229..d393975a19055a1b101132a9ae115893dfdbda4b 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6Q=y CONFIG_TARGET_TBS2910=y +CONFIG_SYS_MALLOC_LEN=0x8000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910" CONFIG_PRE_CON_BUF_ADDR=0x7c000000 diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 9d0b1f01e5af8aac4d7b5bf83979b187b2702237..760e5160d04742ac70ad9137450ec6761485b18a 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA30=y CONFIG_TARGET_TEC_NG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 529016841fe9c7a4e400cb9437ce1985f0e19d0e..b235784a4c0be704987c541153c87b9a989a2d19 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_TEC=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 41d34745a12882f8452cf9007e7cd8407af34bfb..115ce7844859e4ff7980368eff6841879ef1a395 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -9,6 +9,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 93b0c6b0645d348577c0fef5c5a69fc39859f199..98e4c1a4b9d8dda7429acee1fdee4bcf4e1b821d 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -13,12 +13,13 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" CONFIG_SPL_TEXT_BASE=0x40004030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -57,6 +58,10 @@ CONFIG_SATA_MV=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y CONFIG_FPGA_ALTERA=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x0 # CONFIG_MMC is not set CONFIG_SF_DEFAULT_SPEED=27777777 CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index ffd5c28728337ce0f56b921b157ee2e0fd9e2467..5daa63a146423605d9e979388d2f7c19be8b7aaf 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -7,21 +7,23 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_THUBAN=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" @@ -76,6 +78,8 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 97a41d8ee708abf6a2edaa919e5e211e87608185..0462804e2582610b67a56fd25785b26c0da1655f 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -3,11 +3,13 @@ CONFIG_TARGET_THUNDERX_88XX=y CONFIG_SYS_TEXT_BASE=0x00500000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x101000 CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" CONFIG_DEBUG_UART_BASE=0x87e024000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x500000 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000 debug maxcpus=48 rootwait rw root=/dev/sda2 coherent_pool=16M" diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 7a93ebb731162a4f3820ec28ea9365c359295272..dc24bb852700814e1cb386edcfd6e32ff6b3b762 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -10,8 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm" CONFIG_SPL_TEXT_BASE=0x40400000 CONFIG_TI816X=y CONFIG_TARGET_TI816X_EVM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1E0000 CONFIG_SPL_FS_FAT=y @@ -53,6 +54,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 3ac314ab891a03d4cb3e9aa33aead4e7e36fb761..a9c9a122f64c4984155807513e3a41ed32445fcc 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_SPL_GPIO=y @@ -12,6 +14,7 @@ CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" @@ -64,6 +67,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 35e84b7088568d97ffa645c0c5bad89de7c4e23a..5145cbc9e17b74d2d31410d66764345b102885fb 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_SPL_GPIO=y @@ -12,6 +14,7 @@ CONFIG_SPL_SIZE_LIMIT=0x4B000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" @@ -64,6 +67,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index f54bc1802ca7db38f006202765b0eb0d2fb60b69..64a015b3557b637529a487d09fb880dd50a4485f 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -1,6 +1,8 @@ CONFIG_SYS_TEXT_BASE=0 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index e9e03a2aa4883bfe3ded6d08c2dc31b7d62cd664..b43e546ded803c39176fb50aea35a43fe858a5cb 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -18,6 +18,7 @@ CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BOOTDELAY=0 CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 8aec2af0c8bfc702891873ce017d8f17bd408aed..a8a0ff22473e854877ee2e12ea23cffb19da9dd6 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -18,6 +18,7 @@ CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BOOTDELAY=0 CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 6c2754137005f4fec948f7fb3070072b6da34e68..7f8cb4bbdba1a97da9117921b230a0e418ff6ff3 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -18,6 +18,7 @@ CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BOOTDELAY=0 CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index d95918ee9938fee267e202aa4baec0f136f75315..313507ad7c4e8d486678624098913ca6b2b43d14 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -6,8 +6,10 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_ENV_SIZE=0x2a00000 +CONFIG_SYS_MALLOC_LEN=0x3200000 CONFIG_DEFAULT_DEVICE_TREE="total_compute" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 849d3329c4ec1fec5f8c030d71eb4dab169016c6..500e77734bda2b94defa17792fedb268728b7b8d 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -4,9 +4,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_MEMTEST_START=0x80100000 CONFIG_SYS_MEMTEST_END=0x83f00000 CONFIG_ENV_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300" CONFIG_ARCH_ATH79=y CONFIG_BOARD_TPLINK_WDR4300=y +CONFIG_SYS_LOAD_ADDR=0xa1000000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index a6705bd103673dc2d8f686d2fcd01f53cf52a67f..8ca32b1322eddb593ac016b2d3ae733949a0fd28 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6DL=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -35,6 +37,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 82d9b95beabe8b9035b20ad14c9f53ecbe75d93f..75b034a2c24daba43a14d92dda6a2b2430ed136d 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6DL=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_TQMA6X_SPI_BOOT=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" CONFIG_ENV_OFFSET_REDUND=0x90000 @@ -18,6 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -39,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index bbda3791f063508ed1a08df3bc9da9c80c48971a..f2ba64943a41b9333577222e1e395628fded778c 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6Q=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -35,6 +37,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index c4f5b1c11ffef388e5b22eeed440719305ceab6a..65c52aab559570df42e0e01cad5016993ae05f17 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6Q=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_TQMA6X_SPI_BOOT=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b" CONFIG_ENV_OFFSET_REDUND=0x90000 @@ -18,6 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -39,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 04fa16977eea86c5a8e806f321b95f289656f443..fce236e5c8a537f0d0d39095f44abd3a115e00f6 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6S=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -35,6 +37,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index ab1f55bb9485c62882dc2bebf3ca281f0b1a994e..23aa03095560ffa1ded944947ac2269975939073 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6S=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_TQMA6X_SPI_BOOT=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" CONFIG_ENV_OFFSET_REDUND=0x90000 @@ -18,6 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -39,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 17c8c75545567d3dd47951a12ead8eefeadd6b76..f630962d3a787774f5c79e28dd953b3f200d4d61 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43e00000 @@ -6,9 +7,11 @@ CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_TRATS2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 +CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 5709c4fd3c30d2468b7bce0598786e20d3d52600..12002492324b7b28418a76a0ab07b32b174e2fd3 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x63300000 @@ -6,8 +7,10 @@ CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_TRATS=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 +CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x44800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 0b418e731bbb2afd024f9e4250bc5f19617692ba..8881645dc5f6056731f12aa44dbeea71233120e3 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_TRIMSLICE=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 0dbf850952f60aaea0a0acd353ad7546f1cd82c1..a8fa07c4c072c47eca0fcc365a62f7d8718dde29 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -119,6 +119,7 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -132,6 +133,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -150,6 +153,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 9a9102430e67fdf9b31e750f0b8f6c38b4a1457d..82ad68b6a1f666d302c49eb985e4a3d15c2670fd 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -16,6 +16,7 @@ CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index a724a1baa16ed7bdae5d2b6f12c1dacc3442733a..4d080baa143cb5a2def2b1e72d23bc2dfe8722a8 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y @@ -17,13 +18,14 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 58a374cf6569ec2f5d05497f22d3bd30daaceb43..fd94323384efb2520dd15c59b49500fd87c18832 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -141,6 +141,7 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y @@ -154,6 +155,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -172,6 +175,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_SYS_I2C_SLAVE=0x7F +CONFIG_SYS_I2C_SPEED=200000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/u200_defconfig b/configs/u200_defconfig index 909afc59ea1636ec04806c1e6422691db7f35516..144c394010f3ccce243b54eef210010feedbf56c 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" u200" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 1ea3aad5ff2a2b1c62e79dcd2522d1b95172d5d6..a06a25378ec5427c5d983e4f83c29ba7c20d7108 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -14,6 +14,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_USE_PREBOOT=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index eecca2e6c50f894b7244c73019c0ad6b289c9b0c..601ac02b8e71aa2d5a3bc89074b0c93efa36d03d 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -9,16 +9,16 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6QDL=y CONFIG_TARGET_UDOO=y +CONFIG_SYS_MALLOC_LEN=0x0200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y @@ -39,6 +39,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 63960d069743f84fbd9fcb0342a5e0b48fa59690..2f549b35759be7e91e0d458ae357e04a8bb4dc99 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -9,16 +9,17 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SX=y CONFIG_TARGET_UDOO_NEO=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_ENV_SUPPORT=y @@ -36,6 +37,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y @@ -46,5 +50,7 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 117b76005ffe08110ddd3d322da41142cbac40fc..1c2533cc41cb0f8e918ef32ae5fc1dc32aff7511 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -6,10 +6,11 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref" CONFIG_SPL_TEXT_BASE=0x00040000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y +CONFIG_SYS_LOAD_ADDR=0x85000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_USE_PREBOOT=y @@ -19,6 +20,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_CMD_CONFIG=y # CONFIG_CMD_XIMG is not set +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -39,7 +41,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_UNIPHIER=y CONFIG_MTD=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index d92f5f40c567d56be6c0e7c66a83835528227976..19701c278bcc4dcc0abe8c964bdabe4463aa7ec5 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -6,10 +6,11 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka" CONFIG_SPL_TEXT_BASE=0x00100000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y +CONFIG_SYS_LOAD_ADDR=0x85000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_USE_PREBOOT=y @@ -19,6 +20,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_CMD_CONFIG=y # CONFIG_CMD_XIMG is not set +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -40,7 +42,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_UNIPHIER=y CONFIG_MTD=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 8eeb455e626501dbb9e81a23adb81c274065fe74..946665b3b32e4068eb3b7de1f1c17872224c5618 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" CONFIG_ARCH_UNIPHIER_V8_MULTI=y CONFIG_MICRO_SUPPORT_CARD=y +CONFIG_SYS_LOAD_ADDR=0x85000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_USE_PREBOOT=y @@ -16,6 +17,7 @@ CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 CONFIG_CMD_CONFIG=y # CONFIG_CMD_XIMG is not set +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -35,7 +37,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index 983072dc7faebf193a417d17244ccd3586baa277..cfd9ef84117ff09e071df2c2f349b2e5565f64e0 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 @@ -8,8 +9,10 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_SYS_MALLOC_LEN=0x26000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="usb_a9263" +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index b52cfc6673e8bfb86cc7592ea65f7dbc1b72d2e9..f259554645fc4feaf02a35a6a13e482ce87162c9 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -7,10 +7,14 @@ CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_TARGET_USBARMORY=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory" # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x72000000 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y @@ -23,6 +27,8 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 930a178bc6a866b97a3e31412aa94e1ca93f1b68..e93ce8e3a034290b364011bb1c737559210b3065 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -8,14 +8,14 @@ CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x2000 CONFIG_MX6ULL=y CONFIG_TARGET_DART_6UL=y +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SPL_USB_HOST=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index cdc76062b0bec622d3e49d69f701fe3a0ba8568e..dba47c99feab844b1ec4f643cc3de266e3c59552 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 +CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_VENICE2=y +CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index d628840047cb4ed8c872667ea19d21a95e00303d..4472f9655e1df75823923ba5cf80418709038ebf 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_TEGRA20=y CONFIG_TARGET_VENTANA=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 624f1b99096e435033161898f5f577150cffecc3..98799994cea10e2b10db21f25ee4c8c583ac7a48 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -9,24 +9,22 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_VERDIN_IMX8MM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mm/imximage.cfg" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb" CONFIG_LOG=y @@ -73,7 +71,6 @@ CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 118b917dfd8efcb05f1e23057b2b31093b680854..3125adaf5c4d48f4d1c84cbd179a9db8c434f148 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -7,8 +7,10 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x810000 CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 2ecb7762ce1716ef3dea27cf5330214631af6f4b..8dcd459e82a2a6d0a6c91be99055f4e5122e314d 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -7,8 +7,10 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_SYS_MALLOC_LEN=0x840000 CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..1e59d27fc40e2d13a8f9440dce922ab2bfedf17b --- /dev/null +++ b/configs/vexpress_ca9x4_defconfig @@ -0,0 +1,46 @@ +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS_CA9X4=y +CONFIG_SYS_TEXT_BASE=0x60800000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="vexpress-v2p-ca9" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 +CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" +CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0x47F80000 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_ARM_PL180_MMCI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_SMC911X=y +CONFIG_SMC911X_32_BIT=y +CONFIG_BAUDRATE=38400 +CONFIG_CONS_INDEX=0 diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 24a7bdedf0acaf67ce8bcea1086cc0054932e374..add1a071df76682a7cf38b64f2c9e5bb87573566 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 @@ -7,9 +8,12 @@ CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_LOGLEVEL=3 CONFIG_BOARD_EARLY_INIT_F=y @@ -37,6 +41,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_VYBRID_GPIO=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 7cf8ae6604208258f9db50819a6b1d98b0877b81..3544833ae6ae618b7774e19c89b91349085b5ffe 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 @@ -7,9 +8,12 @@ CONFIG_SYS_MEMTEST_START=0x80010000 CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x180000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0x0220000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg" +CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_BOOTDELAY=3 CONFIG_LOGLEVEL=3 CONFIG_BOARD_EARLY_INIT_F=y @@ -37,6 +41,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_VYBRID_GPIO=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 07fb27f68b76ff6983b64592730c5dedccb3b65f..5297c54b5977f0c1054676826597eaa3a3f95160 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x20f00000 @@ -9,6 +10,7 @@ CONFIG_ENV_OFFSET=0x10000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="at91-vinco" CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index f1ac8e80a2c4f1c9e19d2733a6aa0a5c2c4e3ef6..24989ff2aa949b10b7f7f293893f925c20ca7780 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -11,11 +11,14 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SX=y CONFIG_MX6_DDRCAL=y CONFIG_TARGET_SOFTING_VINING_2000=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-softing-vining-2000" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_SPL_LIBDISK_SUPPORT=y @@ -23,7 +26,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg" CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y @@ -61,6 +63,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y @@ -73,6 +78,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index 9ca285285ecadd626270186ff60eaf4da4013a17..165fef46de6853d7137fae74d8e4e82b89ad6d8e 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -1,10 +1,12 @@ CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x04e000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 @@ -13,11 +15,14 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ARCH_MTMIPS=y CONFIG_SOC_MT7628=y CONFIG_BOARD_VOCORE2=y +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y CONFIG_MIPS_BOOT_FDT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_SYS_BOOT_GET_CMDLINE=y CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_SYS_LOAD_ADDR=0x80100000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 2faaa801c5aaf2f6ef5b7e08335ef7b6c3c8caa9..752987f11cbe127286ef478c638da4198360c4b3 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y @@ -12,6 +14,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index d3f0e0e68c349fa48a347b02344df2e7a202e66f..08f8677718a4052ae657233fac72a385019ea59d 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -12,11 +12,12 @@ CONFIG_TARGET_WANDBOARD=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revd1" CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_CMD_HDMIDETECT=y @@ -26,7 +27,6 @@ CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -57,6 +57,7 @@ CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index ec078178abf80b6abdb7f366bcf031d9a9ade67e..d127a4f8d32650d333d2fbbb462a8c15c519c798 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" CONFIG_TARGET_WARP7=y @@ -12,7 +13,6 @@ CONFIG_IMX_HAB=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y @@ -32,11 +32,13 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 19c0c183f7e594e1e1230f2a36ce06a2a3b03c6b..4b339b47caf4b1516bf122bc6ae151aa7ac845f6 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" CONFIG_TARGET_WARP7=y @@ -15,7 +16,6 @@ CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set CONFIG_CMD_BOOTZ=y @@ -38,11 +38,13 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index dce2170354bd07b070ad4150bb0f6b854d37a7f8..3d6c67240f8413ff9c155bad32b5a6073f9b3d3c 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -6,9 +6,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6SL=y CONFIG_TARGET_WARP=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_MALLOC_LEN=0x2300000 # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y @@ -32,8 +34,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index 40726735ba974483f9290cdf1257f004aa445c2f..ce947b5625863b30d4bf476777093725b7cd0e8c 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" wetek-core2" CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 507f24fc375a62338e317ddd8f8b3e4ed8d94311..b09c855ed4b92794600473d49924317668730d29 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y @@ -12,10 +13,12 @@ CONFIG_CMD_HD44760=y CONFIG_CMD_MAX6957=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_TEXT_BASE=0x00000000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x120000 +CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS2,115200n8" @@ -29,6 +32,7 @@ CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_BASE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -42,7 +46,11 @@ CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_VERSION_VARIABLE=y +CONFIG_SYS_I2C_LEGACY=y +CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_LPC32XX=y +CONFIG_SYS_I2C_SPEED=350000 +CONFIG_SYS_I2C_EEPROM_ADDR=0x56 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 6df383b81e67a41fd2334c3ca3bc24023eda2889..fcc384dcae0cace32c11541158337d294047cb93 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 @@ -13,11 +14,12 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530" CONFIG_SPL_TEXT_BASE=0x40000030 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SILENT_CONSOLE=y diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index e1707614979ea851788b4c9c1a8611ddc0508218..b72e40a139953942d18a00d33d8e742328b2d959 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -3,7 +3,9 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_TARGET_XENGUEST_ARM64=y CONFIG_SYS_TEXT_BASE=0x40080000 CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_IDENT_STRING=" xenguest" +CONFIG_SYS_LOAD_ADDR=0x40000000 CONFIG_BOOTDELAY=10 CONFIG_SYS_PROMPT="xenguest# " # CONFIG_CMD_BDI is not set diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 5731a1f276724a0eb0dd94bba0b34fed2f72cd46..ffa17e44ca2df3b92b6aa76b1422643c4c1b848e 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 7547b2699cbe684cefabd33120a62c77de1ee285..ef5433cae871f781b1927aa9aa513436a479fd26 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 0854d50eb492339a70f0a179296eeaa84de7f6ab..f642977d86ebc899a7059c1bec31f94a4cbe2bc2 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 590a2171c11499da3d1662ce5d89a6d3211d3609..11598623954da3f2f48a7e87d094470ef7e5f639 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -11,6 +11,7 @@ CONFIG_CMD_FRU=y CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -61,7 +62,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 66af37ae185734bad68341ea786a6f1a52ce71b0..901e91dd1542712cdcecea7ee6eedc5eab527774 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_ZYNQ_AES=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -49,6 +50,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y @@ -69,6 +71,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y @@ -80,7 +84,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y @@ -122,3 +125,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_DISPLAY=y CONFIG_SPL_GZIP=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 427d019e455d7413bb14287c2517b123af4e500e..a831bac0209709cfac6162607034b7545246d93f 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -6,10 +6,12 @@ CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x1a00 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index f9b2c0ade458c621481cb547162fbc025817fcac..4143597709b6bbefcbdd69e13fbda30a9ecf5f38 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -6,10 +6,12 @@ CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0" CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL=y # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 996e65d58cfa43f43ed68b459df274c6f62fb94d..3317eb5a6739e98968782fc63b05d5d786982261 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -6,10 +6,12 @@ CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1" CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL=y # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 1213d9c957840e9ab6ad954fa21a5738b645cd8c..8cc90c6b41c3bcdcc989843af6284caff4f76538 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -5,8 +5,10 @@ CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index b3ff78b7399100d51e89cbc78bc6fd5b1dad2de1..fe467f315166db05990ff40ec63fad1d26738caa 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -5,8 +5,10 @@ CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 664a333b0ba98bb2effdc0591b01d75768f16d9b..8958e3f4d3a76cd8c6904ad7b978fd357cd01f1f 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x1a00 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" CONFIG_SPL=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y @@ -12,6 +13,7 @@ CONFIG_ZYNQMP_NO_DDR=y # CONFIG_CMD_ZYNQMP is not set # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index 143c253f0efd47c87311b45eb0c88eff5ebfba9b..8f3585d8c26da1b22a67af9a759a06b0480b33b3 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -1,13 +1,16 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_ZYNQMP_R5=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x1400000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5" CONFIG_DEBUG_UART_BASE=0xff010000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BOOTSTAGE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="ZynqMP r5> " diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 2c8dc3427cfe9864f229dba2b3451b88acf80eba..278eaae8bffd2942fe5837bf8d737a6934d2c207 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_SYS_MALLOC_LEN=0x4040000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" CONFIG_SPL_STACK_R_ADDR=0x18000000 @@ -12,13 +13,14 @@ CONFIG_SPL_SIZE_LIMIT=0x2a000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_ZYNQ_MAC_IN_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_CMD_FRU=y CONFIG_ZYNQMP_USB=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -122,7 +124,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 78f8d63be7d3bb3ddfcf7e9edb0456429bad5c3a..cd5425a4c17b33fba4aaf998895663da1f117240 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -2,7 +2,9 @@ CONFIG_XTENSA=y CONFIG_SYS_CPU="dc233c" CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_XTFPGA_KC705=y +CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=10 CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig deleted file mode 100644 index 2afe429986854d764fe436c6d10a5bcad0b564d7..0000000000000000000000000000000000000000 --- a/configs/zmx25_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX25=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_TARGET_ZMX25=y -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="boot in %d s\n" -CONFIG_AUTOBOOT_DELAY_STR="delaygs" -CONFIG_AUTOBOOT_STOP_STR="stopgs" -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="zmx25> " -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xA0040000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_LZO=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 990eaf87ed13e597a49c1cdc1aa1b4dfdbb07bc9..7774b2751922a2d4197b0d8e75b6dbf94a818581 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y @@ -11,6 +13,7 @@ CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 # CONFIG_AUTOBOOT is not set CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index cb372fcf4fb11b57247cb2f2edba6096179b2bf2..a74dcc0568b25d15910610e63ba07e3c1d37fd4d 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y @@ -11,6 +13,7 @@ CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 # CONFIG_AUTOBOOT is not set CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 7fa776bc75007653c945b87d04257c7aa9d5e88f..99aaa1a5e83a40f3cb9faa1c4aebc93e785b356b 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y @@ -16,6 +18,7 @@ CONFIG_DEBUG_UART_CLOCK=0 CONFIG_DEBUG_UART=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_SYS_LOAD_ADDR=0x0 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set # CONFIG_AUTOBOOT is not set CONFIG_USE_PREBOOT=y diff --git a/disk/Makefile b/disk/Makefile index ccd033595905af6852532b5f9a14d63de8337bde..6ce5a687b36c0f3e46e3adc53a82488b558de7ee 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,7 +5,7 @@ #ccflags-y += -DET_DEBUG -DDEBUG -obj-$(CONFIG_PARTITIONS) += part.o +obj-$(CONFIG_PARTITIONS) += part.o obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o diff --git a/disk/part_efi.c b/disk/part_efi.c index fdca91a69747c24bf1c36903f712aec8d5387135..0ca7effc327f868bcef29bb08663fe55b756f54a 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -23,12 +23,11 @@ #include #include #include +#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_HAVE_BLOCK_DEVICE /* GUID for basic data partitons */ @@ -563,9 +562,8 @@ static uint32_t partition_entries_offset(struct blk_desc *dev_desc) * from the start of the device) to be specified as a property * of the device tree '/config' node. */ - config_offset = fdtdec_get_config_int(gd->fdt_blob, - "u-boot,efi-partition-entries-offset", - -EINVAL); + config_offset = ofnode_conf_read_int( + "u-boot,efi-partition-entries-offset", -EINVAL); if (config_offset != -EINVAL) { offset_bytes = PAD_TO_BLOCKSIZE(config_offset, dev_desc); offset_blks = offset_bytes / dev_desc->blksz; diff --git a/disk/part_iso.c b/disk/part_iso.c index 822f2c4d9f4084abf7e3424d8face1e55a353108..1061f341d3532dc2062b5a4d3568253849071a88 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -220,7 +220,7 @@ static void part_print_iso(struct blk_desc *dev_desc) printf("Part Start Sect x Size Type\n"); i=1; do { - printf(" %2d " LBAFU " " LBAFU " %6ld %.32s\n", + printf(" %2d %8" LBAFlength "u %8" LBAFlength "u %6ld %.32s\n", i, info.start, info.size, info.blksz, info.type); i++; } while (part_get_info_iso_verb(dev_desc, i, &info, 0) != -1); diff --git a/doc/README.SPL b/doc/README.SPL index 0448835f5f15374ea05d134ed4de9c314a647239..011fd42537a89556852645d41917c9b5cc51e588 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -49,10 +49,10 @@ CONFIG_SPL_LIBCOMMON_SUPPORT (common/libcommon.o) CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o) CONFIG_SPL_I2C (drivers/i2c/libi2c.o) CONFIG_SPL_GPIO (drivers/gpio/libgpio.o) -CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o) -CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o) +CONFIG_SPL_MMC (drivers/mmc/libmmc.o) +CONFIG_SPL_SERIAL (drivers/serial/libserial.o) CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o) -CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o) +CONFIG_SPL_SPI (drivers/spi/libspi.o) CONFIG_SPL_FS_FAT (fs/fat/libfat.o) CONFIG_SPL_FS_EXT4 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) diff --git a/doc/README.commands.spl b/doc/README.commands.spl index cb3e0c8e0aca7d874854bb44521b689b04cbf455..ecfd3ca9ee589a0f76a15bc580391c2d79c8cf68 100644 --- a/doc/README.commands.spl +++ b/doc/README.commands.spl @@ -17,14 +17,14 @@ TYPICAL CALL on OMAP3: nandecc hw -nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ -spl export atags /* export ATAGS */ +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +spl export atags /* export ATAGS */ nand erase 0x680000 0x20000 /* erase - one page */ nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ call with FDT: nandecc hw -nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ spl export fdt 0x82000000 - 0x80000100 /* export FDT */ nand erase 0x680000 0x20000 /* erase - one page */ diff --git a/doc/README.dfutftp b/doc/README.dfutftp index a3341bbb614206b23b259fcb9e1c0ea587b6ee2a..1206507911761ea5832ac8b8aa2979e8195fcc59 100644 --- a/doc/README.dfutftp +++ b/doc/README.dfutftp @@ -88,7 +88,6 @@ for pure DFU USB transfer. possible to set large enough default buffer (8 MiB @ BBB) - FIT image format for download ----------------------------- @@ -110,7 +109,6 @@ should look like where "u-boot.bin" is the DFU entity name to be stored. - To do ----- diff --git a/doc/README.distro b/doc/README.distro index c4f041ca7124ae6260713c3c19a4d6ed439670fe..fa8cec110288b4a416362260f2d192df5bd35aec 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -233,7 +233,7 @@ fdtfile: the DTB with a different DTB. fdtfile will automatically be set for you if it matches the format ${soc}-${board}.dtb which covers most 32 bit use cases. AArch64 generally does not match as the Linux kernel put the dtb files under - SoC vendor directories. + SoC vendor directories. ramdisk_addr_r: diff --git a/doc/README.falcon b/doc/README.falcon index 713d7063a1d8cb0e8642f5540ac0e52d87ec1e58..88218d35b93e14df8cfac8e5040877721887acc6 100644 --- a/doc/README.falcon +++ b/doc/README.falcon @@ -69,7 +69,7 @@ CONFIG_CMD_SPL_NAND_OFS Offset in NAND where the parameters area was saved. CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved. -CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied +CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied CONFIG_SPL_OS_BOOT Activate Falcon Mode. @@ -89,7 +89,7 @@ Environment variables A board may chose to look at the environment for decisions about falcon mode. In this case the following variables may be supported: -boot_os : Set to yes/Yes/true/True/1 to enable booting to OS, +boot_os : Set to yes/Yes/true/True/1 to enable booting to OS, any other value to fall back to U-Boot (including unset) falcon_args_file : Filename to load as the 'args' portion of falcon mode diff --git a/doc/README.odroid b/doc/README.odroid index bc77ae317554abb4f01b05c866b711d61ec794a7..1090a0ea141292b54f1bcef765bde7090f269fe7 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -296,8 +296,8 @@ Odroid # usb part 0 Partition Map for USB device 0 -- Partition Type: DOS Part Start Sector Num Sectors UUID Type - 1 3072 263168 000c4046-01 06 - 2 266240 13457408 000c4046-02 83 + 1 3072 263168 000c4046-01 06 + 2 266240 13457408 000c4046-02 83 Odroid # ls usb 0:2 /boot 4096 . diff --git a/doc/README.pcap b/doc/README.pcap index 97b3e55fd8c376f37a0691dd60d6e70a4b0e25ed..8e30b93c663fadbc72e77a84ec3a918fcdc57a99 100644 --- a/doc/README.pcap +++ b/doc/README.pcap @@ -59,4 +59,3 @@ PCAP status: # pcap stop # tftpput 0xffffffff80100000 $pcapsize 10.0.2.2:capture.pcap - diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network index e05270673dbd947d9f0f2f5b16383aab76ba547d..9599729d8f9617fb09405a7ec8bf1dcafda8850b 100644 --- a/doc/SPL/README.am335x-network +++ b/doc/SPL/README.am335x-network @@ -7,7 +7,7 @@ NAND and bricked (empty) board with only a network cable. I. Building the required images 1. You have to enable generic SPL configuration options (see -doc/README.SPL) as well as CONFIG_SPL_NET_SUPPORT, +doc/README.SPL) as well as CONFIG_SPL_NET, CONFIG_SPL_ETH, CONFIG_SPL_LIBGENERIC_SUPPORT and CONFIG_SPL_LIBCOMMON_SUPPORT in your board configuration file to build SPL with support for booting over the network. Also you have to enable diff --git a/doc/board/AndesTech/adp-ag101p.rst b/doc/board/AndesTech/adp-ag101p.rst index 879eba0294682356804e2109cf9408091913d1d7..f867eeae3eb2849950ba7ef2a82d99606165fbfd 100644 --- a/doc/board/AndesTech/adp-ag101p.rst +++ b/doc/board/AndesTech/adp-ag101p.rst @@ -23,8 +23,8 @@ CONFIG_MEM_REMAP: CONFIG_SKIP_LOWLEVEL_INIT: If you want to boot this system from SPI ROM and bypass e-bios (the - other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT - in "include/configs/adp-ag101p.h". + other boot loader on ROM). You should enable CONFIG_SKIP_LOWLEVEL_INIT + when running menuconfig or similar. Build and boot steps -------------------- diff --git a/doc/board/index.rst b/doc/board/index.rst index 33087074fa872653456dd4d01233a5973b32f09e..aa397ab94213e9fffab03acb0af81636340a06ea 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -22,10 +22,12 @@ Board-specific doc openpiton/index qualcomm/index rockchip/index + siemens/index sifive/index sipeed/index socionext/index st/index + ste/index tbs/index ti/index toradex/index diff --git a/doc/board/siemens/index.rst b/doc/board/siemens/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..082936ea7e713b6d50bd7412a5e5821fedf50488 --- /dev/null +++ b/doc/board/siemens/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Siemens +======= + +.. toctree:: + :maxdepth: 2 + + iot2050 diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst new file mode 100644 index 0000000000000000000000000000000000000000..592c59be03559b33ba2b42830f189488751563c8 --- /dev/null +++ b/doc/board/siemens/iot2050.rst @@ -0,0 +1,78 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Jan Kiszka + +SIMATIC IOT2050 BASIC and ADVANCED +================================== + +The SIMATIC IOT2050 is an open industrial IoT gateway that is using the TI +AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced +variant is prepared for secure boot. + +The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader +called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and +OP-TEE, before booting U-Boot on the A53 cores. This describes how to build all +open artifacts into a flashable image for the OSPI flash. The flash image will +work on both variants. + +Dependencies +------------ + +ATF: Upstream release 2.4 or newer +OP-TEE: Upstream release 3.10.0 or newer + +Binary dependencies can be found in +https://github.com/siemens/meta-iot2050/tree/master/recipes-bsp/u-boot/files/prebuild. +The following binaries from that source need to be present in the build folder: + + - tiboot3.bin + - sysfw.itb + - sysfw.itb_HS + - sysfw_sr2.itb + - sysfw_sr2.itb_HS + +Building +-------- + +Make sure that CROSS_COMPILE is set appropriately: + +.. code-block:: text + + $ export CROSS_COMPILE=aarch64-linux-gnu- + +ATF: + +.. code-block:: text + + $ make PLAT=k3 SPD=opteed K3_USART=1 + +OP-TEE: + +.. code-block:: text + + $ make PLATFORM=k3-am65x CFG_ARM64_core=y CFG_TEE_CORE_LOG_LEVEL=2 CFG_CONSOLE_UART=1 + +U-Boot: + +.. code-block:: text + + $ export ATF=/path/to/bl31.bin + $ export TEE=/path/to/tee-pager_v2.bin + $ make iot2050_defconfig + $ make + +Flashing +-------- + +Via U-Boot: + +.. code-block:: text + + IOT2050> sf probe + IOT2050> load mmc 0:1 $loadaddr /path/to/flash.bin + IOT2050> sf update $loadaddr 0x0 $filesize + +Via external programmer Dediprog SF100 or SF600: + +.. code-block:: text + + $ dpcmd --vcc 2 -v -u flash.bin diff --git a/doc/board/ste/index.rst b/doc/board/ste/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..bef520ce63fd2ecda97637b760cd76ea05c60659 --- /dev/null +++ b/doc/board/ste/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ST-Ericsson +=========== + +.. toctree:: + :maxdepth: 2 + + stemmy diff --git a/doc/board/ste/stemmy.rst b/doc/board/ste/stemmy.rst new file mode 100644 index 0000000000000000000000000000000000000000..6d77fe9c8312792be7a2b17ebad13f25cbf3c6af --- /dev/null +++ b/doc/board/ste/stemmy.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Stephan Gerhold + +ST-Ericsson U8500 Samsung "stemmy" board +======================================== + +The "stemmy" board supports Samsung smartphones released with +the ST-Ericsson NovaThor U8500 SoC, e.g. + + +---------------------------+----------+--------------+----------------+ + | Device | Model | Codename | U-Boot | + +===========================+==========+==============+================+ + | Samsung Galaxy Ace 2 | GT-I8160 | codina | ``u-boot.bin`` | + +---------------------------+----------+--------------+----------------+ + | Samsung Galaxy Amp | SGH-I407 | kyle | ``u-boot.img`` | + +---------------------------+----------+--------------+----------------+ + | Samsung Galaxy Beam | GT-I8530 | gavini | ``u-boot.bin`` | + +---------------------------+----------+--------------+----------------+ + | Samsung Galaxy Exhibit | SGH-T599 | codina (TMO) | ``u-boot.bin`` | + +---------------------------+----------+--------------+----------------+ + | Samsung Galaxy S Advance | GT-I9070 | janice | ``u-boot.bin`` | + +---------------------------+----------+--------------+----------------+ + | Samsung Galaxy S III mini | GT-I8190 | golden | ``u-boot.img`` | + +---------------------------+----------+--------------+----------------+ + | Samsung Galaxy Xcover 2 | GT-S7710 | skomer | ``u-boot.img`` | + +---------------------------+----------+--------------+----------------+ + +At the moment, U-Boot is intended to be chain-loaded from +the original Samsung bootloader, not replacing it entirely. + +Installation +------------ +First, setup ``CROSS_COMPILE`` for ARMv7. Then, build U-Boot for ``stemmy``:: + + $ export CROSS_COMPILE=arm-none-eabi- + $ make stemmy_defconfig + $ make + +This will build ``u-boot.bin`` in the configured output directory. + +For newer devices (check ``u-boot.img`` in the table above), the U-Boot binary +has to be packed into an Android boot image. Devices with ``u-boot.bin`` boot +the raw U-Boot binary from the boot partition. You can build the Android boot +image with ``mkbootimg``, e.g. from from android-7.1.2_r37_:: + + $ mkbootimg \ + --kernel=u-boot.bin \ + --base=0x00000000 \ + --kernel_offset=0x00100000 \ + --ramdisk_offset=0x02000000 \ + --tags_offset=0x00000100 \ + --output=u-boot.img + +.. _android-7.1.2_r37: https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg + +To flash the U-Boot binary, enter the Samsung download mode +(press Power + Home + Volume Down). Use Heimdall_ to flash the U-Boot image to +the Android boot partition:: + + $ heimdall flash --Kernel u-boot.(bin|img) + +If this is not working but there are messages like ``Android recovery image`` in +the UART console, you can try flashing to the recovery partition instead:: + + $ heimdall flash --Kernel2 u-boot.(bin|img) + +.. _Heimdall: https://gitlab.com/BenjaminDobell/Heimdall + +After a reboot the U-Boot prompt should appear via UART. Unless interrupted it +automatically boots to USB Fastboot mode where Android boot images can be booted +via ``fastboot boot boot.img``. It is mainly intended to boot mainline Linux, +but booting original Samsung Android boot images is also supported (e.g. for +charging). + +UART +---- +UART is available through the micro USB port, similar to the Carkit standard. +With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-. + +.. note:: + Make sure to connect the UART cable **before** turning on the phone. diff --git a/board/ti/am335x/README b/doc/board/ti/am335x_evm.rst similarity index 53% rename from board/ti/am335x/README rename to doc/board/ti/am335x_evm.rst index 19e0eccbac931d6ff73b6908f7783725c0636f0b..a90f32da7aea517b81632a65424939d6b817a081 100644 --- a/board/ti/am335x/README +++ b/doc/board/ti/am335x_evm.rst @@ -1,21 +1,24 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Tom Rini + Summary ======= -This document covers various features of the 'am335x_evm' build, and some of -the related build targets (am335x_evm_uartN, etc). +This document covers various features of the `am335x_evm` default +configuration, some of the related defconfigs, and how to enable hardware +features not present by default in the defconfigs. Hardware -======== +-------- The binary produced by this board supports, based on parsing of the EEPROM documented in TI's reference designs: -- AM335x GP EVM -- AM335x EVM SK -- Beaglebone White -- Beaglebone Black +* AM335x GP EVM +* AM335x EVM SK +* The Beaglebone family of designs Customization -============= +------------- Given that all of the above boards are reference platforms (and the Beaglebone platforms are OSHA), it is likely that this platform code and @@ -24,24 +27,21 @@ worth noting that aside from things such as NAND or MMC only being required if a custom platform makes use of these blocks, the following are required, depending on design: -- GPIO is only required if DDR3 power is controlled in a way similar to - EVM SK -- SPI is only required for SPI flash, or exposing the SPI bus. +* GPIO is only required if DDR3 power is controlled in a way similar to EVM SK +* SPI is only required for SPI flash, or exposing the SPI bus. The following blocks are required: -- I2C, to talk with the PMIC and ensure that we do not run afoul of + +* I2C, to talk with the PMIC and ensure that we do not run afoul of errata 1.0.24. -When removing options as part of customization, -CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your -needs and to remove no longer relevant options as in some cases we -define additional text blocks (such as for NAND or DFU strings). Also -note that all of the SPL options are grouped together, rather than with -the IP blocks, so both areas will need their choices updated to reflect -the custom design. +When removing options as part of customization, note that you will likely need +to look at both `include/configs/am335x_evm.h`, +`include/configs/ti_am335x_common.h` and `include/configs/am335x_evm.h` as the +migration to Kconfig is not yet complete. NAND -==== +---- The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In this example to program the NAND we assume that an SD card has been @@ -58,6 +58,9 @@ Step-1: Building u-boot for NAND boot CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) Step-2: Flashing NAND via MMC/SD + +.. code-block:: text + # select BOOTSEL to MMC/SD boot and boot from MMC/SD card U-Boot # mmc rescan # erase flash @@ -83,31 +86,9 @@ Step-2: Flashing NAND via MMC/SD Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. The device should boot from images flashed on NAND device. -NOR -=== - -The Beaglebone White can be equipped with a "memory cape" that in turn can -have a NOR module plugged into it. In this case it is then possible to -program and boot from NOR. Note that due to how U-Boot is designed we -must build a specific version of U-Boot that knows we have NOR flash. This -build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot' -build that will assume that the environment is on NOR rather than NAND. In -the following example we assume that and SD card has been populated with -MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the -'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a -binary must be written to the start of NOR, with no header or similar -prepended. In the following example we use a size of 512KiB (0x80000) -as that is how much space we set aside before the environment, as per -the config file. - -U-Boot # mmc rescan -U-Boot # load mmc 0 ${loadaddr} u-boot.bin -U-Boot # protect off 08000000 +80000 -U-Boot # erase 08000000 +80000 -U-Boot # cp.b ${loadaddr} 08000000 ${filesize} Falcon Mode -=========== +----------- The default build includes "Falcon Mode" (see doc/README.falcon) via NAND, eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is @@ -119,18 +100,20 @@ boards with multiple boot methods, recovery should not be an issue in this worst-case however. Falcon Mode: eMMC -================= +----------------- The recommended layout in this case is: -MMC BLOCKS |--------------------------------| LOCATION IN BYTES -0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 -0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 -0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 -0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 -0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 -0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 -0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 +.. code-block:: text + + MMC BLOCKS |--------------------------------| LOCATION IN BYTES + 0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 + 0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 + 0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 + 0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 + 0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 + 0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 + 0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 Note that when we run 'spl export' it will prepare to boot the kernel. This includes relocation of the uImage from where we loaded it to the entry @@ -144,28 +127,30 @@ had a FAT partition (such as on a Beaglebone Black) it is not enough to write garbage into the area, you must delete it from the partition table first. -# Ensure we are able to talk with this mmc device -U-Boot # mmc rescan -U-Boot # tftp 81000000 am335x/MLO -# Write to two of the backup locations ROM uses -U-Boot # mmc write 81000000 100 100 -U-Boot # mmc write 81000000 200 100 -# Write U-Boot to the location set in the config -U-Boot # tftp 81000000 am335x/u-boot.img -U-Boot # mmc write 81000000 300 400 -# Load kernel and device tree into memory, perform export -U-Boot # tftp 81000000 am335x/uImage -U-Boot # run findfdt -U-Boot # tftp ${fdtaddr} am335x/${fdtfile} -U-Boot # run mmcargs -U-Boot # spl export fdt 81000000 - ${fdtaddr} -# Write the updated device tree to MMC -U-Boot # mmc write ${fdtaddr} 80 80 -# Write the uImage to MMC -U-Boot # mmc write 81000000 900 2000 +.. code-block:: text + + # Ensure we are able to talk with this mmc device + U-Boot # mmc rescan + U-Boot # tftp 81000000 am335x/MLO + # Write to two of the backup locations ROM uses + U-Boot # mmc write 81000000 100 100 + U-Boot # mmc write 81000000 200 100 + # Write U-Boot to the location set in the config + U-Boot # tftp 81000000 am335x/u-boot.img + U-Boot # mmc write 81000000 300 400 + # Load kernel and device tree into memory, perform export + U-Boot # tftp 81000000 am335x/uImage + U-Boot # run findfdt + U-Boot # tftp ${fdtaddr} am335x/${fdtfile} + U-Boot # run mmcargs + U-Boot # spl export fdt 81000000 - ${fdtaddr} + # Write the updated device tree to MMC + U-Boot # mmc write ${fdtaddr} 80 80 + # Write the uImage to MMC + U-Boot # mmc write 81000000 900 2000 Falcon Mode: FAT SD cards -========================= +------------------------- In this case the additional file is written to the filesystem. In this example we assume that the uImage and device tree to be used are already on @@ -173,23 +158,31 @@ the FAT filesystem (only the uImage MUST be for this to function afterwards) along with a Falcon Mode aware MLO and the FAT partition has already been created and marked bootable: -U-Boot # mmc rescan -# Load kernel and device tree into memory, perform export -U-Boot # load mmc 0:1 ${loadaddr} uImage -U-Boot # run findfdt -U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} -U-Boot # run mmcargs -U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +.. code-block:: text + + U-Boot # mmc rescan + # Load kernel and device tree into memory, perform export + U-Boot # load mmc 0:1 ${loadaddr} uImage + U-Boot # run findfdt + U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} + U-Boot # run mmcargs + U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} This will print a number of lines and then end with something like: - Using Device Tree in place at 80f80000, end 80f85928 - Using Device Tree in place at 80f80000, end 80f88928 + +.. code-block:: text + + Using Device Tree in place at 80f80000, end 80f85928 + Using Device Tree in place at 80f80000, end 80f88928 + So then you: -U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 +.. code-block:: text + + U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 Falcon Mode: NAND -================= +----------------- In this case the additional data is written to another partition of the NAND. In this example we assume that the uImage and device tree to be are @@ -197,9 +190,11 @@ already located on the NAND somewhere (such as filesystem or mtd partition) along with a Falcon Mode aware MLO written to the correct locations for booting and mtdparts have been configured correctly for the board: -U-Boot # nand read ${loadaddr} kernel -U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb -U-Boot # run nandargs -U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} -U-Boot # nand erase.part u-boot-spl-os -U-Boot # nand write ${fdtaddr} u-boot-spl-os +.. code-block:: text + + U-Boot # nand read ${loadaddr} kernel + U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb + U-Boot # run nandargs + U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} + U-Boot # nand erase.part u-boot-spl-os + U-Boot # nand write ${fdtaddr} u-boot-spl-os diff --git a/doc/board/ti/index.rst b/doc/board/ti/index.rst index c0da04b109cb598fb0de4234edb123db0a7f7ede..014a097178ab98295548fa960042b1a327b687ea 100644 --- a/doc/board/ti/index.rst +++ b/doc/board/ti/index.rst @@ -6,4 +6,5 @@ Texas Instruments .. toctree:: :maxdepth: 2 + am335x_evm j721e_evm diff --git a/doc/develop/checkpatch.rst b/doc/develop/checkpatch.rst new file mode 100644 index 0000000000000000000000000000000000000000..51fed1bd72ec46f3d3ef9501fe4e128f90de627a --- /dev/null +++ b/doc/develop/checkpatch.rst @@ -0,0 +1,755 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +========== +Checkpatch +========== + +Checkpatch (scripts/checkpatch.pl) is a perl script which checks for trivial +style violations in patches and optionally corrects them. Checkpatch can +also be run on file contexts and without the kernel tree. + +Checkpatch is not always right. Your judgement takes precedence over checkpatch +messages. If your code looks better with the violations, then its probably +best left alone. + + +Options +======= + +This section will describe the options checkpatch can be run with. + +Usage:: + + ./scripts/checkpatch.pl [OPTION]... [FILE]... + +Available options: + + - -q, --quiet + + Enable quiet mode. + + - -v, --verbose + Enable verbose mode. Additional verbose test descriptions are output + so as to provide information on why that particular message is shown. + + - --no-tree + + Run checkpatch without the kernel tree. + + - --no-signoff + + Disable the 'Signed-off-by' line check. The sign-off is a simple line at + the end of the explanation for the patch, which certifies that you wrote it + or otherwise have the right to pass it on as an open-source patch. + + Example:: + + Signed-off-by: Random J Developer + + Setting this flag effectively stops a message for a missing signed-off-by + line in a patch context. + + - --patch + + Treat FILE as a patch. This is the default option and need not be + explicitly specified. + + - --emacs + + Set output to emacs compile window format. This allows emacs users to jump + from the error in the compile window directly to the offending line in the + patch. + + - --terse + + Output only one line per report. + + - --showfile + + Show the diffed file position instead of the input file position. + + - -g, --git + + Treat FILE as a single commit or a git revision range. + + Single commit with: + + - + - ^ + - ~n + + Multiple commits with: + + - .. + - ... + - - + + - -f, --file + + Treat FILE as a regular source file. This option must be used when running + checkpatch on source files in the kernel. + + - --subjective, --strict + + Enable stricter tests in checkpatch. By default the tests emitted as CHECK + do not activate by default. Use this flag to activate the CHECK tests. + + - --list-types + + Every message emitted by checkpatch has an associated TYPE. Add this flag + to display all the types in checkpatch. + + Note that when this flag is active, checkpatch does not read the input FILE, + and no message is emitted. Only a list of types in checkpatch is output. + + - --types TYPE(,TYPE2...) + + Only display messages with the given types. + + Example:: + + ./scripts/checkpatch.pl mypatch.patch --types EMAIL_SUBJECT,BRACES + + - --ignore TYPE(,TYPE2...) + + Checkpatch will not emit messages for the specified types. + + Example:: + + ./scripts/checkpatch.pl mypatch.patch --ignore EMAIL_SUBJECT,BRACES + + - --show-types + + By default checkpatch doesn't display the type associated with the messages. + Set this flag to show the message type in the output. + + - --max-line-length=n + + Set the max line length (default 100). If a line exceeds the specified + length, a LONG_LINE message is emitted. + + + The message level is different for patch and file contexts. For patches, + a WARNING is emitted. While a milder CHECK is emitted for files. So for + file contexts, the --strict flag must also be enabled. + + - --min-conf-desc-length=n + + Set the Kconfig entry minimum description length, if shorter, warn. + + - --tab-size=n + + Set the number of spaces for tab (default 8). + + - --root=PATH + + PATH to the kernel tree root. + + This option must be specified when invoking checkpatch from outside + the kernel root. + + - --no-summary + + Suppress the per file summary. + + - --mailback + + Only produce a report in case of Warnings or Errors. Milder Checks are + excluded from this. + + - --summary-file + + Include the filename in summary. + + - --debug KEY=[0|1] + + Turn on/off debugging of KEY, where KEY is one of 'values', 'possible', + 'type', and 'attr' (default is all off). + + - --fix + + This is an EXPERIMENTAL feature. If correctable errors exists, a file + .EXPERIMENTAL-checkpatch-fixes is created which has the + automatically fixable errors corrected. + + - --fix-inplace + + EXPERIMENTAL - Similar to --fix but input file is overwritten with fixes. + + DO NOT USE this flag unless you are absolutely sure and you have a backup + in place. + + - --ignore-perl-version + + Override checking of perl version. Runtime errors maybe encountered after + enabling this flag if the perl version does not meet the minimum specified. + + - --codespell + + Use the codespell dictionary for checking spelling errors. + + - --codespellfile + + Use the specified codespell file. + Default is '/usr/share/codespell/dictionary.txt'. + + - --typedefsfile + + Read additional types from this file. + + - --color[=WHEN] + + Use colors 'always', 'never', or only when output is a terminal ('auto'). + Default is 'auto'. + + - --kconfig-prefix=WORD + + Use WORD as a prefix for Kconfig symbols (default is `CONFIG_`). + + - -h, --help, --version + + Display the help text. + +Message Levels +============== + +Messages in checkpatch are divided into three levels. The levels of messages +in checkpatch denote the severity of the error. They are: + + - ERROR + + This is the most strict level. Messages of type ERROR must be taken + seriously as they denote things that are very likely to be wrong. + + - WARNING + + This is the next stricter level. Messages of type WARNING requires a + more careful review. But it is milder than an ERROR. + + - CHECK + + This is the mildest level. These are things which may require some thought. + +Type Descriptions +================= + +This section contains a description of all the message types in checkpatch. + +.. Types in this section are also parsed by checkpatch. +.. The types are grouped into subsections based on use. + + +Allocation style +---------------- + + **ALLOC_ARRAY_ARGS** + The first argument for kcalloc or kmalloc_array should be the + number of elements. sizeof() as the first argument is generally + wrong. + See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html + + **ALLOC_SIZEOF_STRUCT** + The allocation style is bad. In general for family of + allocation functions using sizeof() to get memory size, + constructs like:: + + p = alloc(sizeof(struct foo), ...) + + should be:: + + p = alloc(sizeof(*p), ...) + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#allocating-memory + + **ALLOC_WITH_MULTIPLY** + Prefer kmalloc_array/kcalloc over kmalloc/kzalloc with a + sizeof multiply. + See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html + + +API usage +--------- + + **ARCH_DEFINES** + Architecture specific defines should be avoided wherever + possible. + + **ARCH_INCLUDE_LINUX** + Whenever asm/file.h is included and linux/file.h exists, a + conversion can be made when linux/file.h includes asm/file.h. + However this is not always the case (See signal.h). + This message type is emitted only for includes from arch/. + + **AVOID_BUG** + BUG() or BUG_ON() should be avoided totally. + Use WARN() and WARN_ON() instead, and handle the "impossible" + error condition as gracefully as possible. + See: https://www.kernel.org/doc/html/latest/process/deprecated.html#bug-and-bug-on + + **CONSIDER_KSTRTO** + The simple_strtol(), simple_strtoll(), simple_strtoul(), and + simple_strtoull() functions explicitly ignore overflows, which + may lead to unexpected results in callers. The respective kstrtol(), + kstrtoll(), kstrtoul(), and kstrtoull() functions tend to be the + correct replacements. + See: https://www.kernel.org/doc/html/latest/process/deprecated.html#simple-strtol-simple-strtoll-simple-strtoul-simple-strtoull + + **LOCKDEP** + The lockdep_no_validate class was added as a temporary measure to + prevent warnings on conversion of device->sem to device->mutex. + It should not be used for any other purpose. + See: https://lore.kernel.org/lkml/1268959062.9440.467.camel@laptop/ + + **MALFORMED_INCLUDE** + The #include statement has a malformed path. This has happened + because the author has included a double slash "//" in the pathname + accidentally. + + **USE_LOCKDEP** + lockdep_assert_held() annotations should be preferred over + assertions based on spin_is_locked() + See: https://www.kernel.org/doc/html/latest/locking/lockdep-design.html#annotations + + **UAPI_INCLUDE** + No #include statements in include/uapi should use a uapi/ path. + + +Comment style +------------- + + **BLOCK_COMMENT_STYLE** + The comment style is incorrect. The preferred style for multi- + line comments is:: + + /* + * This is the preferred style + * for multi line comments. + */ + + The networking comment style is a bit different, with the first line + not empty like the former:: + + /* This is the preferred comment style + * for files in net/ and drivers/net/ + */ + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting + + **C99_COMMENTS** + C99 style single line comments (//) should not be used. + Prefer the block comment style instead. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting + + +Commit message +-------------- + + **BAD_SIGN_OFF** + The signed-off-by line does not fall in line with the standards + specified by the community. + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1 + + **BAD_STABLE_ADDRESS_STYLE** + The email format for stable is incorrect. + Some valid options for stable address are:: + + 1. stable@vger.kernel.org + 2. stable@kernel.org + + For adding version info, the following comment style should be used:: + + stable@vger.kernel.org # version info + + **COMMIT_COMMENT_SYMBOL** + Commit log lines starting with a '#' are ignored by git as + comments. To solve this problem addition of a single space + infront of the log line is enough. + + **COMMIT_MESSAGE** + The patch is missing a commit description. A brief + description of the changes made by the patch should be added. + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes + + **MISSING_SIGN_OFF** + The patch is missing a Signed-off-by line. A signed-off-by + line should be added according to Developer's certificate of + Origin. + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin + + **NO_AUTHOR_SIGN_OFF** + The author of the patch has not signed off the patch. It is + required that a simple sign off line should be present at the + end of explanation of the patch to denote that the author has + written it or otherwise has the rights to pass it on as an open + source patch. + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin + + **DIFF_IN_COMMIT_MSG** + Avoid having diff content in commit message. + This causes problems when one tries to apply a file containing both + the changelog and the diff because patch(1) tries to apply the diff + which it found in the changelog. + See: https://lore.kernel.org/lkml/20150611134006.9df79a893e3636019ad2759e@linux-foundation.org/ + + **GERRIT_CHANGE_ID** + To be picked up by gerrit, the footer of the commit message might + have a Change-Id like:: + + Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b + Signed-off-by: A. U. Thor + + The Change-Id line must be removed before submitting. + + **GIT_COMMIT_ID** + The proper way to reference a commit id is: + commit <12+ chars of sha1> ("") + + An example may be:: + + Commit e21d2170f36602ae2708 ("video: remove unnecessary + platform_set_drvdata()") removed the unnecessary + platform_set_drvdata(), but left the variable "dev" unused, + delete it. + + See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes + + +Comparison style +---------------- + + **ASSIGN_IN_IF** + Do not use assignments in if condition. + Example:: + + if ((foo = bar(...)) < BAZ) { + + should be written as:: + + foo = bar(...); + if (foo < BAZ) { + + **BOOL_COMPARISON** + Comparisons of A to true and false are better written + as A and !A. + See: https://lore.kernel.org/lkml/1365563834.27174.12.camel@joe-AO722/ + + **COMPARISON_TO_NULL** + Comparisons to NULL in the form (foo == NULL) or (foo != NULL) + are better written as (!foo) and (foo). + + **CONSTANT_COMPARISON** + Comparisons with a constant or upper case identifier on the left + side of the test should be avoided. + + +Macros, Attributes and Symbols +------------------------------ + + **ARRAY_SIZE** + The ARRAY_SIZE(foo) macro should be preferred over + sizeof(foo)/sizeof(foo[0]) for finding number of elements in an + array. + + The macro is defined in include/linux/kernel.h:: + + #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + + **AVOID_EXTERNS** + Function prototypes don't need to be declared extern in .h + files. It's assumed by the compiler and is unnecessary. + + **AVOID_L_PREFIX** + Local symbol names that are prefixed with `.L` should be avoided, + as this has special meaning for the assembler; a symbol entry will + not be emitted into the symbol table. This can prevent `objtool` + from generating correct unwind info. + + Symbols with STB_LOCAL binding may still be used, and `.L` prefixed + local symbol names are still generally usable within a function, + but `.L` prefixed local symbol names should not be used to denote + the beginning or end of code regions via + `SYM_CODE_START_LOCAL`/`SYM_CODE_END` + + **BIT_MACRO** + Defines like: 1 << <digit> could be BIT(digit). + The BIT() macro is defined in include/linux/bitops.h:: + + #define BIT(nr) (1UL << (nr)) + + **CONST_READ_MOSTLY** + When a variable is tagged with the __read_mostly annotation, it is a + signal to the compiler that accesses to the variable will be mostly + reads and rarely(but NOT never) a write. + + const __read_mostly does not make any sense as const data is already + read-only. The __read_mostly annotation thus should be removed. + + **DATE_TIME** + It is generally desirable that building the same source code with + the same set of tools is reproducible, i.e. the output is always + exactly the same. + + The kernel does *not* use the ``__DATE__`` and ``__TIME__`` macros, + and enables warnings if they are used as they can lead to + non-deterministic builds. + See: https://www.kernel.org/doc/html/latest/kbuild/reproducible-builds.html#timestamps + + **DEFINE_ARCH_HAS** + The ARCH_HAS_xyz and ARCH_HAVE_xyz patterns are wrong. + + For big conceptual features use Kconfig symbols instead. And for + smaller things where we have compatibility fallback functions but + want architectures able to override them with optimized ones, we + should either use weak functions (appropriate for some cases), or + the symbol that protects them should be the same symbol we use. + See: https://lore.kernel.org/lkml/CA+55aFycQ9XJvEOsiM3txHL5bjUc8CeKWJNR_H+MiicaddB42Q@mail.gmail.com/ + + **INIT_ATTRIBUTE** + Const init definitions should use __initconst instead of + __initdata. + + Similarly init definitions without const require a separate + use of const. + + **INLINE_LOCATION** + The inline keyword should sit between storage class and type. + + For example, the following segment:: + + inline static int example_function(void) + { + ... + } + + should be:: + + static inline int example_function(void) + { + ... + } + + **MULTISTATEMENT_MACRO_USE_DO_WHILE** + Macros with multiple statements should be enclosed in a + do - while block. Same should also be the case for macros + starting with `if` to avoid logic defects:: + + #define macrofun(a, b, c) \ + do { \ + if (a == 5) \ + do_this(b, c); \ + } while (0) + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#macros-enums-and-rtl + + **WEAK_DECLARATION** + Using weak declarations like __attribute__((weak)) or __weak + can have unintended link defects. Avoid using them. + + +Functions and Variables +----------------------- + + **CAMELCASE** + Avoid CamelCase Identifiers. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#naming + + **FUNCTION_WITHOUT_ARGS** + Function declarations without arguments like:: + + int foo() + + should be:: + + int foo(void) + + **GLOBAL_INITIALISERS** + Global variables should not be initialized explicitly to + 0 (or NULL, false, etc.). Your compiler (or rather your + loader, which is responsible for zeroing out the relevant + sections) automatically does it for you. + + **INITIALISED_STATIC** + Static variables should not be initialized explicitly to zero. + Your compiler (or rather your loader) automatically does + it for you. + + **RETURN_PARENTHESES** + return is not a function and as such doesn't need parentheses:: + + return (bar); + + can simply be:: + + return bar; + + +Spacing and Brackets +-------------------- + + **ASSIGNMENT_CONTINUATIONS** + Assignment operators should not be written at the start of a + line but should follow the operand at the previous line. + + **BRACES** + The placement of braces is stylistically incorrect. + The preferred way is to put the opening brace last on the line, + and put the closing brace first:: + + if (x is true) { + we do y + } + + This applies for all non-functional blocks. + However, there is one special case, namely functions: they have the + opening brace at the beginning of the next line, thus:: + + int function(int x) + { + body of function + } + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + **BRACKET_SPACE** + Whitespace before opening bracket '[' is prohibited. + There are some exceptions: + + 1. With a type on the left:: + + ;int [] a; + + 2. At the beginning of a line for slice initialisers:: + + [0...10] = 5, + + 3. Inside a curly brace:: + + = { [0...10] = 5 } + + **CODE_INDENT** + Code indent should use tabs instead of spaces. + Outside of comments, documentation and Kconfig, + spaces are never used for indentation. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation + + **CONCATENATED_STRING** + Concatenated elements should have a space in between. + Example:: + + printk(KERN_INFO"bar"); + + should be:: + + printk(KERN_INFO "bar"); + + **ELSE_AFTER_BRACE** + `else {` should follow the closing block `}` on the same line. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + **LINE_SPACING** + Vertical space is wasted given the limited number of lines an + editor window can display when multiple blank lines are used. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **OPEN_BRACE** + The opening brace should be following the function definitions on the + next line. For any non-functional block it should be on the same line + as the last construct. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + **POINTER_LOCATION** + When using pointer data or a function that returns a pointer type, + the preferred use of * is adjacent to the data name or function name + and not adjacent to the type name. + Examples:: + + char *linux_banner; + unsigned long long memparse(char *ptr, char **retptr); + char *match_strdup(substring_t *s); + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **SPACING** + Whitespace style used in the kernel sources is described in kernel docs. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **SWITCH_CASE_INDENT_LEVEL** + switch should be at the same indent as case. + Example:: + + switch (suffix) { + case 'G': + case 'g': + mem <<= 30; + break; + case 'M': + case 'm': + mem <<= 20; + break; + case 'K': + case 'k': + mem <<= 10; + /* fall through */ + default: + break; + } + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation + + **TRAILING_WHITESPACE** + Trailing whitespace should always be removed. + Some editors highlight the trailing whitespace and cause visual + distractions when editing files. + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces + + **WHILE_AFTER_BRACE** + while should follow the closing bracket on the same line:: + + do { + ... + } while(something); + + See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces + + +Others +------ + + **CONFIG_DESCRIPTION** + Kconfig symbols should have a help text which fully describes + it. + + **CORRUPTED_PATCH** + The patch seems to be corrupted or lines are wrapped. + Please regenerate the patch file before sending it to the maintainer. + + **DOS_LINE_ENDINGS** + For DOS-formatted patches, there are extra ^M symbols at the end of + the line. These should be removed. + + **EXECUTE_PERMISSIONS** + There is no reason for source files to be executable. The executable + bit can be removed safely. + + **NON_OCTAL_PERMISSIONS** + Permission bits should use 4 digit octal permissions (like 0700 or 0444). + Avoid using any other base like decimal. + + **NOT_UNIFIED_DIFF** + The patch file does not appear to be in unified-diff format. Please + regenerate the patch file before sending it to the maintainer. + + **PRINTF_0XDECIMAL** + Prefixing 0x with decimal output is defective and should be corrected. + + **TRAILING_STATEMENTS** + Trailing statements (for example after any conditional) should be + on the next line. + Like:: + + if (x == y) break; + + should be:: + + if (x == y) + break; diff --git a/doc/develop/driver-model/of-plat.rst b/doc/develop/driver-model/of-plat.rst index 8a8eaed4c11e017381fa53153d3f8706f9fe35e4..237af38ad4d8b5bc281a962faf26d84bc59f7223 100644 --- a/doc/develop/driver-model/of-plat.rst +++ b/doc/develop/driver-model/of-plat.rst @@ -215,16 +215,16 @@ For example: static int mmc_of_to_plat(struct udevice *dev) { - #if !CONFIG_IS_ENABLED(OF_PLATDATA) + if (CONFIG_IS_ENABLED(OF_REAL)) { /* Decode the devicetree data */ struct mmc_plat *plat = dev_get_plat(dev); const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); - #endif + } - return 0; + return 0; } static int mmc_probe(struct udevice *dev) @@ -600,6 +600,11 @@ as a macro included in the driver definition:: Problems -------- +This section shows some common problems and how to fix them. + +Driver not found +~~~~~~~~~~~~~~~~ + In some cases you will you see something like this:: WARNING: the driver rockchip_rk3188_grf was not found in the driver list @@ -633,8 +638,11 @@ the devicetree. For example, if the devicetree has:: then dtoc looks at the first compatible string ("rockchip,rk3188-grf"), converts that to a C identifier (rockchip_rk3188_grf) and then looks for that. +Missing .compatible or Missing .id +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + Various things can cause dtoc to fail to find the driver and it tries to -warn about these. For example: +warn about these. For example:: rockchip_rk3188_uart: Missing .compatible in drivers/serial/serial_rockchip.c : WARNING: the driver rockchip_rk3188_uart was not found in the driver list @@ -649,6 +657,130 @@ Checks are also made to confirm that the referenced driver has a .compatible member and a .id member. The first provides the array of compatible strings and the second provides the uclass ID. +Missing parent +~~~~~~~~~~~~~~ + +When a device is used, its parent must be present as well. If you see an error +like:: + + Node '/i2c@0/emul/emul0' requires parent node '/i2c@0/emul' but it is not in + the valid list + +it indicates that you are using a node whose parent is not present in the +devicetree. In this example, if you look at the device tree output +(e.g. fdtdump tpl/u-boot-tpl.dtb in your build directory), you may see something +like this:: + + emul { + emul0 { + compatible = "sandbox,i2c-rtc-emul"; + #emul-cells = <0x00000000>; + phandle = <0x00000003>; + }; + }; + +In this example, 'emul0' exists but its parent 'emul' has no properties. These +have been dropped by fdtgrep in an effort to reduce the devicetree size. This +indicates that the two nodes have different phase settings. Looking at the +source .dts:: + + i2c_emul: emul { + u-boot,dm-spl; + reg = <0xff>; + compatible = "sandbox,i2c-emul-parent"; + emul0: emul0 { + u-boot,dm-pre-reloc; + compatible = "sandbox,i2c-rtc-emul"; + #emul-cells = <0>; + }; + }; + +you can see that the child node 'emul0' usees 'u-boot,dm-pre-reloc', indicating +that the node is present in all SPL builds, but its parent uses 'u-boot,dm-spl' +indicating it is only present in SPL, not TPL. For a TPL build, this will fail +with the above message. The fix is to change 'emul0' to use the same +'u-boot,dm-spl' condition, so that it is not present in TPL, like its parent. + +Link errors / undefined reference +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Sometimes dtoc does not find the problem for you, but something is wrong and +you get a link error, e.g.:: + + :(.u_boot_list_2_udevice_2_spl_test5+0x0): undefined reference to + `_u_boot_list_2_driver_2_sandbox_spl_test' + /usr/bin/ld: dts/dt-uclass.o:(.u_boot_list_2_uclass_2_misc+0x8): + undefined reference to `_u_boot_list_2_uclass_driver_2_misc' + +The first one indicates that the device cannot find its driver. This means that +there is a driver 'sandbox_spl_test' but it is not compiled into the build. +Check your Kconfig settings to make sure it is. If you don't want that in the +build, adjust your phase settings, e.g. by using 'u-boot,dm-spl' in the node +to exclude it from the TPL build:: + + spl-test5 { + u-boot,dm-tpl; + compatible = "sandbox,spl-test"; + stringarray = "tpl"; + }; + +We can drop the 'u-boot,dm-tpl' line so this node won't appear in the TPL +devicetree and thus the driver won't be needed. + +The second error above indicates that the MISC uclass is needed by the driver +(since it is in the MISC uclass) but that uclass is not compiled in the build. +The fix above would fix this error too. But if you do want this uclass in the +build, check your Kconfig settings to make sure the uclass is being built +(CONFIG_MISC in this case). + +Another error that can crop up is something like:: + + spl/dts/dt-device.c:257:38: error: invalid application of ‘sizeof’ to + incomplete type ‘struct sandbox_irq_priv’ + 257 | u8 _sandbox_irq_priv_irq_sbox[sizeof(struct sandbox_irq_priv)] + | ^~~~~~ + +This indicates that `struct sandbox_irq_priv` is not defined anywhere. The +solution is to add a DM_HEADER() line, as below, so this is included in the +dt-device.c file:: + + U_BOOT_DRIVER(sandbox_irq) = { + .name = "sandbox_irq", + .id = UCLASS_IRQ, + .of_match = sandbox_irq_ids, + .ops = &sandbox_irq_ops, + .priv_auto = sizeof(struct sandbox_irq_priv), + DM_HEADER(<asm/irq.h>) + }; + +Note that there is no dependency checking on the above, so U-Boot will not +regenerate the dt-device.c file when you update the source file (here, +`irq_sandbox.c`). You need to run `make mrproper` first to get a fresh build. + +Another error that can crop up is something like:: + + spl/dts/dt-device.c:257:38: error: invalid application of ‘sizeof’ to + incomplete type ‘struct sandbox_irq_priv’ + 257 | u8 _sandbox_irq_priv_irq_sbox[sizeof(struct sandbox_irq_priv)] + | ^~~~~~ + +This indicates that `struct sandbox_irq_priv` is not defined anywhere. The +solution is to add a DM_HEADER() line, as below, so this is included in the +dt-device.c file:: + + U_BOOT_DRIVER(sandbox_irq) = { + .name = "sandbox_irq", + .id = UCLASS_IRQ, + .of_match = sandbox_irq_ids, + .ops = &sandbox_irq_ops, + .priv_auto = sizeof(struct sandbox_irq_priv), + DM_HEADER(<asm/irq.h>) + }; + +Note that there is no dependency checking on the above, so U-Boot will not +regenerate the dt-device.c file when you update the source file (here, +`irq_sandbox.c`). You need to run `make mrproper` first to get a fresh build. + Caveats ------- @@ -697,7 +829,7 @@ Internals --------- Generated files -``````````````` +~~~~~~~~~~~~~~~ When enabled, dtoc generates the following five files: @@ -738,7 +870,7 @@ spl/dt-plat.c. CONFIG options -`````````````` +~~~~~~~~~~~~~~ Several CONFIG options are used to control the behaviour of of-platdata, all available for both SPL and TPL: @@ -793,7 +925,7 @@ READ_ONLY the nodes cannot be updated, OF_PLATDATA_NO_BIND is enabled. Data structures -``````````````` +~~~~~~~~~~~~~~~ A few extra data structures are used with of-platdata: @@ -821,7 +953,7 @@ A few extra data structures are used with of-platdata: `device_get_by_ofplat_idx()`. Other changes -````````````` +~~~~~~~~~~~~~ Some other changes are made with of-platdata: diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 24056b10fdd75bff49c9b18cbebdd4b6d0980444..5e064a4dac1f3c662fb87c16d42739e8886a6b06 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -56,5 +56,6 @@ Refactoring .. toctree:: :maxdepth: 1 + checkpatch coccinelle moveconfig diff --git a/doc/develop/version.rst b/doc/develop/version.rst index 066901bcd2d92ddffa5e47dac5dcc0f25b06e0e7..8f3231b7611b6f976a76a9b5533e9c0decb47060 100644 --- a/doc/develop/version.rst +++ b/doc/develop/version.rst @@ -60,15 +60,6 @@ The following are available: This is used as part of the banner string when U-Boot starts. - U_BOOT_VERSION_STRING (string #define) - U_BOOT_VERSION followed by build-time information - and CONFIG_IDENT_STRING. - - Examples:: - - U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700) - U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring - U_BOOT_VERSION_NUM (integer #define) Release year, e.g. 2021 for release 2021.01. Note this is an integer, not a string. @@ -77,6 +68,18 @@ The following are available: Patch number, e.g. 1 for release 2020.01. Note this is an integer, not a string. +Human readable U-Boot version string is available in header file +include/version_string.h in following variable: + + version_string (const char[]) + U_BOOT_VERSION followed by build-time information + and CONFIG_IDENT_STRING. + + Examples:: + + U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700) + U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring + Build date/time is also included. See the generated file include/generated/timestamp_autogenerated.h for the available fields. For example:: diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt index 85379fbbe531d51f56e32d231bb1c046b3def5e7..3151778b2c9ce9e1894c05b387d20d99717debe6 100644 --- a/doc/device-tree-bindings/config.txt +++ b/doc/device-tree-bindings/config.txt @@ -2,8 +2,8 @@ The /config node (Configuration Options) ---------------------------------------- A number of run-time configuration options are provided in the /config node -of the control device tree. You can access these using fdtdec_get_config_int(), -fdtdec_get_config_bool() and fdtdec_get_config_string(). +of the control device tree. You can access these using ofnode_conf_read_int(), +ofnode_conf_read_bool() and ofnode_conf_read_str(). These options are designed to affect the operation of U-Boot at runtime. Runtime-configuration items can help avoid proliferation of different builds diff --git a/doc/device-tree-bindings/firmware/linaro,optee-tz.txt b/doc/device-tree-bindings/firmware/linaro,optee-tz.txt index d38834c67dffe910af59fa15531b9fcd2303a33b..2d75c2b1b53c90837c9fdf5102fd0b3cd72edd99 100644 --- a/doc/device-tree-bindings/firmware/linaro,optee-tz.txt +++ b/doc/device-tree-bindings/firmware/linaro,optee-tz.txt @@ -21,7 +21,6 @@ the reference implementation maintained by Linaro. in drivers/tee/optee/optee_smc.h - Example: firmware { optee { diff --git a/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt b/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt index f3add0d4e7ae5ac804591e2c79d133c6198db2cb..c25d7091bfe3b3ebff00d3a643a30b02383866db 100644 --- a/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt +++ b/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt @@ -10,7 +10,7 @@ Secure Proxy Device Node: Required properties: -------------------- - compatible: Shall be: "ti,am654-secure-proxy" -- reg-names data - Map the data region +- reg-names data - Map the data region scfg - Map the secure configuration region rt - Map the Realtime region. - reg: Contains the register map per reg-names. diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt index c4cf26eaa4cf7e6df4c037132905a470bb186554..dd0260b3940721af908f8834bb4bc57230345675 100644 --- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt +++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt @@ -11,7 +11,7 @@ Required properties: -------------------- - compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200 "ti,am64-ddrss" for am642 -- reg-names cfg - Map the controller configuration region +- reg-names cfg - Map the controller configuration region ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr - reg: Contains the register map per reg-names. - power-domains: Should contain two entries: diff --git a/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt b/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt index 4ed731c52422909f16eeec7fbf5787967a29692e..1e11edf7b197a80106a8a3f356300e5473be428f 100644 --- a/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt +++ b/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt @@ -14,7 +14,7 @@ DDRSS device node: Required properties: -------------------- - compatible: Shall be: "ti,am654-ddrss" -- reg-names ss - Map the sub system wrapper logic region +- reg-names ss - Map the sub system wrapper logic region ctl - Map the controller region phy - Map the PHY region - reg: Contains the register map per reg-names. diff --git a/doc/device-tree-bindings/mmc/snps,dw-mmc.txt b/doc/device-tree-bindings/mmc/snps,dw-mmc.txt index 69faefa95e92b9599847b3d5a20fd8b1877b9108..0c9e3ada5a3dd6cc5d95bec464226b5201826b94 100644 --- a/doc/device-tree-bindings/mmc/snps,dw-mmc.txt +++ b/doc/device-tree-bindings/mmc/snps,dw-mmc.txt @@ -30,4 +30,3 @@ mmc0@f000a000 { clock-names = "biu", "ciu"; max-frequency = <25000000>; }; - diff --git a/doc/device-tree-bindings/net/altera_tse.txt b/doc/device-tree-bindings/net/altera_tse.txt index cb190df65fa417e7228e231b863d94bb42cd229a..96ab1d6ebca23e76e3451a95e6a9655810615332 100644 --- a/doc/device-tree-bindings/net/altera_tse.txt +++ b/doc/device-tree-bindings/net/altera_tse.txt @@ -90,7 +90,7 @@ Example: tse_sub_1_eth_tse_0: ethernet@0x1,00001000 { compatible = "altr,tse-msgdma-1.0"; - reg = <0x00000001 0x00001000 0x00000400>, + reg = <0x00000001 0x00001000 0x00000400>, <0x00000001 0x00001460 0x00000020>, <0x00000001 0x00001480 0x00000020>, <0x00000001 0x000014A0 0x00000008>, diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt index cfc376bc977aa0a25e64d4e1ef617a1a326fe634..648a1aee694dfa4ff39a7bd0910d990389b8c3b8 100644 --- a/doc/device-tree-bindings/net/ethernet.txt +++ b/doc/device-tree-bindings/net/ethernet.txt @@ -41,7 +41,17 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. * "2500base-x", * "rxaui" * "xaui" - * "10gbase-kr" (10GBASE-KR, XFI, SFI) + * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol + used with various different mediums. Please refer to the IEEE standard for + a definition of this. Note: 10GBASE-R is just one protocol that can be used + with XFI and SFI. XFI and SFI permit multiple protocols over a single + SERDES lane, and also defines the electrical characteristics of the signals + with a host compliance board plugged into the host XFP/SFP connector. + Therefore, XFI and SFI are not PHY interface types in their own right.) + * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with + Clause 73 autonegotiation. Please refer to the IEEE standard for further + information. Note: due to legacy usage, some 10GBASE-R usage incorrectly + makes use of this definition). - phy-connection-type: the same as "phy-mode" property but described in the Devicetree Specification; - phy-handle: phandle, specifies a reference to a node representing a PHY diff --git a/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt b/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt index e237825bac62f24d3e26720e7bc4dabf3a473df3..5c6d548caeca0aa0003aaf84b1349f1bf6fe3dc2 100644 --- a/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt +++ b/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt @@ -21,7 +21,7 @@ Example: fec0: ethernet@9000 { compatible = "fsl,mcf-dma-fec"; - reg = <0x9000 0x800>; + reg = <0x9000 0x800>; mii-base = <0>; phy-addr = <0>; timeout-loop = <5000>; diff --git a/doc/device-tree-bindings/net/fsl,mcf-fec.txt b/doc/device-tree-bindings/net/fsl,mcf-fec.txt index 39bbaa52f3256eaaf90214f0c29e386ba6bd421f..2699b5ac070af886a748b9337ced3ec44b8347f7 100644 --- a/doc/device-tree-bindings/net/fsl,mcf-fec.txt +++ b/doc/device-tree-bindings/net/fsl,mcf-fec.txt @@ -15,7 +15,7 @@ Example: fec0: ethernet@fc030000 { compatible = "fsl,mcf-fec"; - reg = <0xfc030000 0x400>; + reg = <0xfc030000 0x400>; mii-base = <0>; phy-addr = <0>; timeout-loop = <5000>; diff --git a/doc/device-tree-bindings/net/mdio.txt b/doc/device-tree-bindings/net/mdio.txt index 15953250502b11daa4860db11cb2868741df84bb..a7d8ac5b15aae447a7e0c1dbf72223762de22d39 100644 --- a/doc/device-tree-bindings/net/mdio.txt +++ b/doc/device-tree-bindings/net/mdio.txt @@ -33,4 +33,3 @@ requires no compatible property for probing. reg = <2>; }; }; - diff --git a/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt b/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt index 2034f059936d2923428e2d986f60dd452a2046a8..ace66ead5cd0bda0a1a92abc512290d49e5bff85 100644 --- a/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt @@ -2,7 +2,7 @@ Required properties for the pinctrl driver: - compatible: "brcm,bcm6838-pinctrl" -- regmap: specify the gpio test port syscon +- regmap: specify the gpio test port syscon - brcm,pins-count: the number of pin - brcm,functions-count: the number of function diff --git a/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt index 51f2f2c79c50b482c5e3c12ef54b3a3f92ff783b..0d6f8614455af21c1f5ab6cb570eb52b7a1a1386 100644 --- a/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt @@ -3,19 +3,19 @@ ---------------------------------------------------------------------- MPP# 0x1 0x2 0x3 0x4 ---------------------------------------------------------------------- -0 SDIO_CLK - SPI0_CLK - +0 SDIO_CLK - SPI0_CLK - 1 SDIO_CMD - SPI0_MISO - -2 SDIO_D[0] - SPI0_MOSI - -3 SDIO_D[1] - SPI0_CS0n - +2 SDIO_D[0] - SPI0_MOSI - +3 SDIO_D[1] - SPI0_CS0n - 4 SDIO_D[2] - I2C0_SDA SPI0_CS1n 5 SDIO_D[3] - I2C0_SCK - 6 SDIO_DS - - - 7 SDIO_D[4] - UART1_RXD - -8 SDIO_D[5] - UART1_TXD - -9 SDIO_D[6] - SPI0_CS1n - +8 SDIO_D[5] - UART1_TXD - +9 SDIO_D[6] - SPI0_CS1n - 10 SDIO_D[7] - - - -11 - - UART0_TXD - -12 SDIO_CARD_PW_OFF SDIO_HW_RST - - +11 - - UART0_TXD - +12 SDIO_CARD_PW_OFF SDIO_HW_RST - - 13 - - - - 14 - - - - 15 - - - - diff --git a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt index 1fc1bc66456a0062c3c69275f9979c77736cd7d1..c6984ddd60b09d6041f32a02967c0bb4d4ca7679 100644 --- a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt @@ -11,7 +11,7 @@ Required properties for the pinctrl driver: "marvell,armada-8k-cpm-pinctrl", "marvell,armada-8k-cps-pinctrl" - bank-name: A string defining the pinc controller bank name -- reg: A pair of values defining the pin controller base address +- reg: A pair of values defining the pin controller base address and the address space - pin-count: Numeric value defining the amount of multi purpose pins included in this bank diff --git a/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt b/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt index 2a60e4941b6b88d1149e2a3bbff9fdd0e71e00fd..bd272384afa4c92eb46dc1b9889f3bb034d8a402 100644 --- a/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt +++ b/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt @@ -8,21 +8,21 @@ Required properties: - anatop-reg-offset: u32 value representing the anatop MFD register offset. - anatop-vol-bit-shift: u32 value representing the bit shift for the register. - anatop-vol-bit-width: u32 value representing the number of bits used in the - register. + register. - anatop-min-bit-val: u32 value representing the minimum value of this - register. + register. - anatop-min-voltage: u32 value representing the minimum voltage of this - regulator. + regulator. - anatop-max-voltage: u32 value representing the maximum voltage of this - regulator. + regulator. Optional properties: - anatop-delay-reg-offset: u32 value representing the anatop MFD step time - register offset. + register offset. - anatop-delay-bit-shift: u32 value representing the bit shift for the step - time register. + time register. - anatop-delay-bit-width: u32 value representing the number of bits used in - the step time register. + the step time register. - anatop-enable-bit: u32 value representing regulator enable bit offset. - vin-supply: input supply phandle. diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt index 420ec9529fb4414c646d640ec264e3c710a097e2..e57897ac0c69d28b5779a80b47cead196d7c89c2 100644 --- a/doc/device-tree-bindings/spi/spi-bus.txt +++ b/doc/device-tree-bindings/spi/spi-bus.txt @@ -8,10 +8,10 @@ in slave mode. The SPI master node requires the following properties: - #address-cells - number of cells required to define a chip select - address on the SPI bus. + address on the SPI bus. - #size-cells - should be zero. - compatible - name of SPI bus controller following generic names - recommended practice. + recommended practice. - cs-gpios - (optional) gpios chip select. No other properties are required in the SPI bus node. It is assumed that a driver for an SPI bus device will understand that it is an SPI bus. @@ -45,16 +45,16 @@ SPI slave nodes must be children of the SPI master node and can contain the following properties. - reg - (required) chip select address of device. - compatible - (required) name of SPI device following generic names - recommended practice + recommended practice - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz - spi-cpol - (optional) Empty property indicating device requires - inverse clock polarity (CPOL) mode + inverse clock polarity (CPOL) mode - spi-cpha - (optional) Empty property indicating device requires - shifted clock phase (CPHA) mode + shifted clock phase (CPHA) mode - spi-cs-high - (optional) Empty property indicating device requires - chip select active high + chip select active high - spi-3wire - (optional) Empty property indicating device requires - 3-wire mode. + 3-wire mode. - spi-tx-bus-width - (optional) The bus width(number of data wires) that used for MOSI. Defaults to 1 if not present. - spi-rx-bus-width - (optional) The bus width(number of data wires) that diff --git a/doc/device-tree-bindings/spi/spi-qup.txt b/doc/device-tree-bindings/spi/spi-qup.txt index 3697df2631085fc958771e9f7c93a1c8b3c6a888..2f2f070c5ac5378a8be7ec373677dc30aa2db13b 100644 --- a/doc/device-tree-bindings/spi/spi-qup.txt +++ b/doc/device-tree-bindings/spi/spi-qup.txt @@ -7,7 +7,7 @@ Required properties: - reg : Physical base address and size of SPI registers map. - clock : Clock phandle (see clock bindings for details). - #address-cells : Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. + address on the SPI bus. Should be set to 1. - #size-cells : Should be zero. - pinctrl-names : Must be "default" - pinctrl-n : At least one pinctrl phandle diff --git a/doc/device-tree-bindings/tpm2/sandbox.txt b/doc/device-tree-bindings/tpm2/sandbox.txt index 3d0f727cc41a0c54862cdf0d9a6b48a7c5d5e4b5..05a310e057fb742510f2ff61249b37b18f3f124d 100644 --- a/doc/device-tree-bindings/tpm2/sandbox.txt +++ b/doc/device-tree-bindings/tpm2/sandbox.txt @@ -7,5 +7,5 @@ Required properties: Example: tpm { - compatible = "sandbox,tpm2"; + compatible = "sandbox,tpm2"; }; diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt index 3a2ee4bd1759a7fecdf232239a4c597c980252d9..16f870225fdbeeda017e5e3063d37fba5258bb27 100644 --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt @@ -6,7 +6,8 @@ Required properties: - reg : SPI Chip select Optional properties: -- gpio-reset : Reset GPIO (if not connected to the SoC reset line) +- reset-gpios : Reset GPIO (if not connected to the SoC reset line) +- gpio-reset : Reset GPIO (deprecated, use reset-gpios instead) - spi-max-frequency : See spi-bus.txt Example: diff --git a/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt b/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt index 2e91be93b784aba27e080e64cf85524029008dd5..3ad8d460f2c60cca222cbc8caa7cc410db1221d6 100644 --- a/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt +++ b/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt @@ -34,4 +34,3 @@ onewire_tm: onewire { compatible = "maxim,ds24xxx"; } }; - diff --git a/doc/device-tree-bindings/w1-eeprom/ds2502.txt b/doc/device-tree-bindings/w1-eeprom/ds2502.txt index 7f05fc432e0ff757ed9f9ec8dd0d68e6d7dce3e6..8788e570587b368d470605afccb1a56e388da6e6 100644 --- a/doc/device-tree-bindings/w1-eeprom/ds2502.txt +++ b/doc/device-tree-bindings/w1-eeprom/ds2502.txt @@ -30,4 +30,3 @@ Example with parent bus: compatible = "maxim,ds2502"; }; }; - diff --git a/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt b/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt index 82bb5899af914818a71c5c9cdcac8c76f7536ef4..ebf718c74322ab8e3aeb5d48e83873e004ea24ab 100644 --- a/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt +++ b/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt @@ -31,4 +31,3 @@ onewire_tm: onewire { compatible = "sandbox,w1-eeprom"; } }; - diff --git a/doc/device-tree-bindings/w1/w1-gpio.txt b/doc/device-tree-bindings/w1/w1-gpio.txt index 5a582448e40c2d45055aa5daa59622ecee0eeb31..2ba86d7d91f5d6703468eface48cd30ce900048d 100644 --- a/doc/device-tree-bindings/w1/w1-gpio.txt +++ b/doc/device-tree-bindings/w1/w1-gpio.txt @@ -37,4 +37,3 @@ onewire_tm: onewire { compatible = "maxim,ds24xxx"; } }; - diff --git a/doc/device-tree-bindings/watchdog/gpio-wdt.txt b/doc/device-tree-bindings/watchdog/gpio-wdt.txt new file mode 100644 index 0000000000000000000000000000000000000000..c9a8559a3efa82edf1aa2bec369dbd2f551b6177 --- /dev/null +++ b/doc/device-tree-bindings/watchdog/gpio-wdt.txt @@ -0,0 +1,19 @@ +GPIO watchdog timer + +Describes a simple watchdog timer which is reset by toggling a gpio. + +Required properties: + +- compatible: Must be "linux,wdt-gpio". +- gpios: gpio to toggle when wdt driver reset method is called. +- always-running: Boolean property indicating that the watchdog cannot + be disabled. At present, U-Boot only supports this kind of GPIO + watchdog. + +Example: + + gpio-wdt { + gpios = <&gpio0 1 0>; + compatible = "linux,wdt-gpio"; + always-running; + }; diff --git a/doc/imx/common/imx25.txt b/doc/imx/common/imx25.txt deleted file mode 100644 index 0ca21b6dfe491c9b7c209baec8af80f6043200c0..0000000000000000000000000000000000000000 --- a/doc/imx/common/imx25.txt +++ /dev/null @@ -1,10 +0,0 @@ -U-Boot for Freescale i.MX25 - -This file contains information for the port of U-Boot to the Freescale i.MX25 -SoC. - -1. CONVENTIONS FOR FUSE ASSIGNMENTS ------------------------------------ - -1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the - natural MAC byte order (i.e. MSB first). diff --git a/doc/imx/common/imx6.txt b/doc/imx/common/imx6.txt index 0b5061128c45847b089871a382415a157e058328..9007cfbf587a8339fb8e0eb1fa5b1718ed76dd79 100644 --- a/doc/imx/common/imx6.txt +++ b/doc/imx/common/imx6.txt @@ -9,7 +9,7 @@ SoC. 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the 16 msbs in word 3[15:0]. For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address - is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in + is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in word 4. Example: diff --git a/doc/kwboot.1 b/doc/kwboot.1 index 1e9ca268f7ce7db4f8b113a0f6a825cc18d3f9cc..acdea891d9f0fc2135bc6c63fa87cca0d1a2b40a 100644 --- a/doc/kwboot.1 +++ b/doc/kwboot.1 @@ -1,21 +1,22 @@ -.TH KWBOOT 1 "2012-05-19" +.TH KWBOOT 1 "2021-08-25" .SH NAME -kwboot \- Boot Marvell Kirkwood SoCs over a serial link. +kwboot \- Boot Marvell Kirkwood (and others 32-bit) SoCs over a serial link. .SH SYNOPSIS .B kwboot .RB [ "-b \fIimage\fP" ] -.RB [ "-p" ] .RB [ "-t" ] .RB [ "-B \fIbaudrate\fP" ] .RB \fITTY\fP .SH "DESCRIPTION" -The \fBmkimage\fP program boots boards based on Marvell's Kirkwood -platform over their integrated UART. Boot image files will typically +The \fBkwboot\fP program boots boards based on Marvell's 32-bit +platforms including Kirkwood, Dove, A370, AXP, A375, A38x +and A39x over their integrated UART. Boot image files will typically contain a second stage boot loader, such as U-Boot. The image file must conform to Marvell's BootROM firmware image format -(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP. +(\fIkwbimage v0\fP or \fIv1\fP), created using a tool such as +\fBmkimage\fP. Following power-up or a system reset, system BootROM code polls the UART for a brief period of time, sensing a handshake message which @@ -36,25 +37,23 @@ by the second-stage loader. Handshake; then upload file \fIimage\fP over \fITTY\fP. Note that for the encapsulated boot code to be executed, \fIimage\fP -must be of type "UART boot" (0x69). Boot images of different types, -such as backup images of vendor firmware downloaded from flash memory -(type 0x8B), will not work (or not as expected). See \fB-p\fP for a -workaround. +must be of type "UART boot" (0x69). The \fBkwboot\fP program changes +this type automatically, unless the \fIimage\fP is signed, in which +case it cannot be changed. This mode writes handshake status and upload progress indication to -stdout. +stdout. It is possible that \fIimage\fP contains an optional binary +code in it's header which may also print some output via UART (for +example U-Boot SPL does this). In such a case, this output is also +written to stdout after the header is sent. .TP .BI "\-p" -In combination with \fB-b\fP, patches the header in \fIimage\fP prior -to upload, to "UART boot" type. +Obsolete. Does nothing. -This option attempts on-the-fly conversion of some none-UART image -types, such as images which were originally formatted to be stored in -flash memory. - -Conversion is performed in memory. The contents of \fIimage\fP will -not be altered. +In the past, when this option was used, the program patched the header +in the image prior upload, to "UART boot" type. This is now done by +default. .TP .BI "\-t" @@ -65,11 +64,26 @@ If used in combination with \fB-b\fP, terminal mode is entered immediately following a successful image upload. If standard I/O streams connect to a console, this mode will terminate -after receiving 'ctrl-\\' followed by 'c' from console input. +after receiving \fBctrl-\e\fP followed by \fBc\fP from console input. .TP .BI "\-B \fIbaudrate\fP" -Adjust the baud rate on \fITTY\fP. Default rate is 115200. +If used in combination with \fB-b\fP, inject into the image header +code that changes baud rate to \fIbaudrate\fP after uploading image +header, and code that changes the baud rate back to the default +(115200 Bd) before executing payload, and also adjust the baud rate +on \fITTY\fP correspondingly. This can make the upload significantly +faster. + +If used in combination with \fB-t\fP, adjust the baud rate to +\fIbaudrate\fP on \fITTY\fP before starting terminal. + +If both \fB-b\fP and \fB-t\fP are used, the baud rate is changed +back to 115200 after the upload. + +Tested values for \fIbaudrate\fP for Armada 38x include: 115200, +230400, 460800, 500000, 576000, 921600, 1000000, 1152000, 1500000, +2000000, 2500000, 3125000, 4000000 and 5200000. .SH "SEE ALSO" .PP @@ -82,3 +96,7 @@ Daniel Stodden <daniel.stodden@gmail.com> Luka Perkov <luka@openwrt.org> .br David Purdy <david.c.purdy@gmail.com> +.br +Pali Rohár <pali@kernel.org> +.br +Marek Behún <marek.behun@nic.cz> diff --git a/doc/mvebu/armada-8k-memory.txt b/doc/mvebu/armada-8k-memory.txt index 064518eb51be1daa3002309c32adecf9c88273c8..f554d71e99caec58675fe7e2fe6af4b1dcd83e76 100644 --- a/doc/mvebu/armada-8k-memory.txt +++ b/doc/mvebu/armada-8k-memory.txt @@ -53,4 +53,3 @@ Start End Use 0xFFF00000 0xFFFFFFFF Bootrom 0x100000000 <DRAM Size>-1 DRAM - diff --git a/doc/mvebu/cmd/bubt.txt b/doc/mvebu/cmd/bubt.txt index a539c15bcde9dc5ed39a0aef0fb6349a65ffdfde..6051243f11659a8d2fd7d9533439d10ca4420935 100644 --- a/doc/mvebu/cmd/bubt.txt +++ b/doc/mvebu/cmd/bubt.txt @@ -52,4 +52,3 @@ Notes: - NAND: # nand write <load_address> 0 <ATF Size> - SPI: # sf write <load_address> 0 <ATF Size> - SD/eMMC: # mmc write <load_address> [0|1] <ATF Size>/<block_size> - diff --git a/doc/usage/qfw.rst b/doc/usage/qfw.rst index 87463e1e5bb822f9160739d07f98d81afe8f492b..b3704b92d6d91fa41da3c35e0d399eb44fcef61b 100644 --- a/doc/usage/qfw.rst +++ b/doc/usage/qfw.rst @@ -26,7 +26,7 @@ The *qfw load* command is used to load a kernel and an initial RAM disk. kernel_addr address to which the file specified by the -kernel parameter of QEMU shall be loaded. Defaults to environment variable *loadaddr* and further to - the value of *CONFIG_LOADADDR*. + the value of *CONFIG_SYS_LOAD_ADDR*. initrd_addr address to which the file specified by the -initrd parameter of QEMU shall diff --git a/drivers/Makefile b/drivers/Makefile index fd218c905638d10c60cc825f627ae70ed48f3bed..4cbc40787db3243b0e720584f4cc8c35b9052260 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,9 +1,12 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ +obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/ +obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/ obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/ @@ -12,48 +15,40 @@ obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C) += i2c/ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ -obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/ +obj-$(CONFIG_$(SPL_TPL_)MMC) += mmc/ obj-y += mtd/ obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux/ -obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/ +obj-$(CONFIG_$(SPL_TPL_)ETH) += net/ +obj-$(CONFIG_$(SPL_TPL_)PCH) += pch/ obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/ obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ +obj-$(CONFIG_$(SPL_TPL_)POWER) += power/ obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ -obj-$(CONFIG_$(SPL_TPL_)RTC_SUPPORT) += rtc/ -obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/ -obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ +obj-$(CONFIG_$(SPL_TPL_)RTC) += rtc/ +obj-$(CONFIG_$(SPL_TPL_)SERIAL) += serial/ +obj-$(CONFIG_$(SPL_TPL_)SPI) += spi/ obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ -obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_$(SPL_)FPGA) += fpga/ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/ -obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/ obj-$(CONFIG_SPL_CPU) += cpu/ obj-$(CONFIG_SPL_CRYPTO) += crypto/ -obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ +obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ -obj-$(CONFIG_SPL_POWER) += power/ power/pmic/ -obj-$(CONFIG_SPL_POWER) += power/regulator/ -obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ obj-$(CONFIG_SPL_DM_RESET) += reset/ -obj-$(CONFIG_SPL_DMA) += dma/ -obj-$(CONFIG_SPL_ETH) += net/ -obj-$(CONFIG_SPL_ETH) += net/phy/ -obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ @@ -61,7 +56,7 @@ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/ obj-$(CONFIG_SPL_WATCHDOG) += watchdog/ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ -obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ +obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ @@ -70,8 +65,7 @@ endif ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_TPL_BOOTCOUNT_LIMIT) += bootcount/ -obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ +obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/ endif @@ -83,7 +77,6 @@ obj-y += bus/ obj-$(CONFIG_DM_DEMO) += demo/ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ -obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 6f0b7723836470ac19d8c66ffef0435faafae563..5639536811c25db90ca03f85b7e83433afbd0a9b 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -36,10 +36,17 @@ menu "SATA/SCSI device support" config AHCI_PCI bool "Support for PCI-based AHCI controller" + depends on PCI depends on DM_SCSI help Enables support for the PCI-based AHCI controller. +config SPL_AHCI_PCI + bool "Support for PCI-based AHCI controller for SPL" + depends on SPL + depends on SPL_PCI + depends on SPL_SATA_SUPPORT && DM_SCSI + config SATA_CEVA bool "Ceva Sata controller" depends on AHCI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 4811b2f82c4e649879a5d456075fd76f5f0db337..cd88131dcd1331791d68cf73119f157641b33978 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o obj-$(CONFIG_AHCI) += ahci-uclass.o -obj-$(CONFIG_AHCI_PCI) += ahci-pci.o +obj-$(CONFIG_$(SPL_)AHCI_PCI) += ahci-pci.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/axi/axi-uclass.c b/drivers/axi/axi-uclass.c index afb4844ecbde264ea03c77bca221563c06669f1d..41551ae85c9cdad48442cf2bdae7d167d854a899 100644 --- a/drivers/axi/axi-uclass.c +++ b/drivers/axi/axi-uclass.c @@ -38,4 +38,3 @@ UCLASS_DRIVER(axi) = { .post_bind = dm_scan_fdt_dev, .flags = DM_UC_FLAG_SEQ_ALIAS, }; - diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 4023332dd98c8ed281256d6a730faa7d41e8785a..56a4eec05ac7863dfdc06e7107716ee6d3b08d68 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -52,14 +52,12 @@ config BLOCK_CACHE config SPL_BLOCK_CACHE bool "Use block device cache in SPL" depends on SPL_BLK - default n help This option enables the disk-block cache in SPL config TPL_BLOCK_CACHE bool "Use block device cache in TPL" depends on TPL_BLK - default n help This option enables the disk-block cache in TPL diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index 2c7983d0ceafa16f6160abfc4faf8e8c5573ea6d..bbdb76bd574f5c835b40e7180843c0cfd3268d2e 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -68,8 +68,8 @@ struct v5l2_plat { struct l2cache *regs; u32 iprefetch; u32 dprefetch; - u32 tram_ctl[2]; - u32 dram_ctl[2]; + u32 tram_ctl[2]; + u32 dram_ctl[2]; }; static int v5l2_enable(struct udevice *dev) diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c index 0fb767e43399c95175d8140cbd41d87e5014aa9f..955dfc8a0f844be525c8171455d4780734c445de 100644 --- a/drivers/cache/sandbox_cache.c +++ b/drivers/cache/sandbox_cache.c @@ -31,7 +31,7 @@ static int snadbox_disable(struct udevice *dev) static const struct cache_ops sandbox_cache_ops = { .get_info = sandbox_get_info, - .enable = sandbox_enable, + .enable = sandbox_enable, .disable = snadbox_disable, }; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 5d93e6a7e52952d6e285cf3e6a1c65a7999e4141..aec0bca7b3cb0fd7768f5f4e0fc4ea992535ca92 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -12,13 +12,15 @@ #include <asm/processor.h> #include <clk-uclass.h> #include <common.h> +#include <div64.h> #include <dm.h> #include <linux/clk-provider.h> #include <linux/clk/at91_pmc.h> #include "pmc.h" -#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk" +#define UBOOT_DM_CLK_AT91_MASTER_PRES "at91-master-clk-pres" +#define UBOOT_DM_CLK_AT91_MASTER_DIV "at91-master-clk-div" #define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk" #define MASTER_PRES_MASK 0x7 @@ -73,7 +75,7 @@ static int clk_master_enable(struct clk *clk) return 0; } -static ulong clk_master_get_rate(struct clk *clk) +static ulong clk_master_pres_get_rate(struct clk *clk) { struct clk_master *master = to_clk_master(clk); const struct clk_master_layout *layout = master->layout; @@ -81,7 +83,7 @@ static ulong clk_master_get_rate(struct clk *clk) master->characteristics; ulong rate = clk_get_parent_rate(clk); unsigned int mckr; - u8 pres, div; + u8 pres; if (!rate) return 0; @@ -90,29 +92,21 @@ static ulong clk_master_get_rate(struct clk *clk) mckr &= layout->mask; pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; - div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) - rate /= 3; + pres = 3; else - rate >>= pres; - - rate /= characteristics->divisors[div]; - - if (rate < characteristics->output.min) - pr_warn("master clk is underclocked"); - else if (rate > characteristics->output.max) - pr_warn("master clk is overclocked"); + pres = (1 << pres); - return rate; + return DIV_ROUND_CLOSEST_ULL(rate, pres); } -static const struct clk_ops master_ops = { +static const struct clk_ops master_pres_ops = { .enable = clk_master_enable, - .get_rate = clk_master_get_rate, + .get_rate = clk_master_pres_get_rate, }; -struct clk *at91_clk_register_master(void __iomem *base, +struct clk *at91_clk_register_master_pres(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, @@ -140,7 +134,7 @@ struct clk *at91_clk_register_master(void __iomem *base, pmc_read(master->base, master->layout->offset, &val); clk = &master->clk; clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL; - ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name, + ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_PRES, name, parent_names[val & AT91_PMC_CSS]); if (ret) { kfree(master); @@ -150,10 +144,81 @@ struct clk *at91_clk_register_master(void __iomem *base, return clk; } -U_BOOT_DRIVER(at91_master_clk) = { - .name = UBOOT_DM_CLK_AT91_MASTER, +U_BOOT_DRIVER(at91_master_pres_clk) = { + .name = UBOOT_DM_CLK_AT91_MASTER_PRES, + .id = UCLASS_CLK, + .ops = &master_pres_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +static ulong clk_master_div_get_rate(struct clk *clk) +{ + struct clk_master *master = to_clk_master(clk); + const struct clk_master_layout *layout = master->layout; + const struct clk_master_characteristics *characteristics = + master->characteristics; + ulong rate = clk_get_parent_rate(clk); + unsigned int mckr; + u8 div; + + if (!rate) + return 0; + + pmc_read(master->base, master->layout->offset, &mckr); + mckr &= layout->mask; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + + rate = DIV_ROUND_CLOSEST_ULL(rate, characteristics->divisors[div]); + if (rate < characteristics->output.min) + pr_warn("master clk is underclocked"); + else if (rate > characteristics->output.max) + pr_warn("master clk is overclocked"); + + return rate; +} + +static const struct clk_ops master_div_ops = { + .enable = clk_master_enable, + .get_rate = clk_master_div_get_rate, +}; + +struct clk *at91_clk_register_master_div(void __iomem *base, + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics) +{ + struct clk_master *master; + struct clk *clk; + int ret; + + if (!base || !name || !parent_name || !layout || !characteristics) + return ERR_PTR(-EINVAL); + + master = kzalloc(sizeof(*master), GFP_KERNEL); + if (!master) + return ERR_PTR(-ENOMEM); + + master->layout = layout; + master->characteristics = characteristics; + master->base = base; + master->num_parents = 1; + + clk = &master->clk; + clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL; + ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_DIV, name, + parent_name); + if (ret) { + kfree(master); + clk = ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(at91_master_div_clk) = { + .name = UBOOT_DM_CLK_AT91_MASTER_DIV, .id = UCLASS_CLK, - .ops = &master_ops, + .ops = &master_div_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 1bfae5fd01656c18f7cce58a91eb27290f4d3819..383f79cfbaf52abfe31f5a57ad08ea1cfae603a7 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -439,4 +439,3 @@ U_BOOT_DRIVER(at91_sam9x60_frac_pll_clk) = { .ops = &sam9x60_frac_pll_ops, .flags = DM_FLAG_PRE_RELOC, }; - diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index f07f535e492d2aefc089d8597d3d4430d859132e..2b4dd9a3d96c29bd071351d88e9b03ceafa36706 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -97,12 +97,17 @@ sam9x60_clk_register_frac_pll(void __iomem *base, const char *name, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, bool critical); struct clk * -at91_clk_register_master(void __iomem *base, const char *name, +at91_clk_register_master_pres(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, const u32 *mux_table); struct clk * +at91_clk_register_master_div(void __iomem *base, + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics); +struct clk * at91_clk_sama7g5_register_master(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const u32 *mux_table, const u32 *clk_mux_table, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 9e9a643d62d7af32de13f621b214846c4c7cb3c1..4d00ee2ddc37e3e0f24650cb5ac015a649367bf3 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -31,7 +31,7 @@ * @ID_PLL_A_FRAC: APLL fractional clock identifier * @ID_PLL_A_DIV: APLL divider clock identifier - * @ID_MCK: MCK clock identifier + * @ID_MCK_DIV: MCK DIV clock identifier * @ID_UTMI: UTMI clock identifier @@ -43,6 +43,8 @@ * @ID_DDR: DDR system clock identifier * @ID_QSPI: QSPI system clock identifier * + * @ID_MCK_PRES: MCK PRES clock identifier + * * Note: if changing the values of this enums please sync them with * device tree */ @@ -60,7 +62,7 @@ enum pmc_clk_ids { ID_PLL_A_FRAC = 9, ID_PLL_A_DIV = 10, - ID_MCK = 11, + ID_MCK_DIV = 11, ID_UTMI = 12, @@ -73,6 +75,8 @@ enum pmc_clk_ids { ID_DDR = 17, ID_QSPI = 18, + ID_MCK_PRES = 19, + ID_MAX, }; @@ -93,7 +97,8 @@ static const char *clk_names[] = { [ID_MAINCK] = "mainck", [ID_PLL_U_DIV] = "upll_divpmcck", [ID_PLL_A_DIV] = "plla_divpmcck", - [ID_MCK] = "mck", + [ID_MCK_PRES] = "mck_pres", + [ID_MCK_DIV] = "mck_div", }; /* Fractional PLL output range. */ @@ -260,10 +265,10 @@ static const struct { u8 id; u8 cid; } sam9x60_systemck[] = { - { .n = "ddrck", .p = "mck", .id = 2, .cid = ID_DDR, }, + { .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, }, { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, - { .n = "qspick", .p = "mck", .id = 19, .cid = ID_QSPI, }, + { .n = "qspick", .p = "mck_pres", .id = 19, .cid = ID_QSPI, }, }; /** @@ -508,7 +513,7 @@ static int sam9x60_clk_probe(struct udevice *dev) clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c); } - /* Register MCK clock. */ + /* Register MCK pres clock. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_MAINCK]; p[2] = clk_names[ID_PLL_A_DIV]; @@ -519,25 +524,36 @@ static int sam9x60_clk_probe(struct udevice *dev) cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4, fail); - c = at91_clk_register_master(base, clk_names[ID_MCK], p, 4, &mck_layout, - &mck_characteristics, tmpclkmux); + c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4, + &mck_layout, &mck_characteristics, + tmpclkmux); + if (IS_ERR(c)) { + ret = PTR_ERR(c); + goto fail; + } + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c); + + /* Register MCK div clock. */ + c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV], + clk_names[ID_MCK_PRES], + &mck_layout, &mck_characteristics); if (IS_ERR(c)) { ret = PTR_ERR(c); goto fail; } - clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK), c); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c); /* Register programmable clocks. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK]; + p[3] = clk_names[ID_MCK_DIV]; p[4] = clk_names[ID_PLL_A_DIV]; p[5] = clk_names[ID_PLL_U_DIV]; cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV); cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) { @@ -572,7 +588,7 @@ static int sam9x60_clk_probe(struct udevice *dev) for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout, sam9x60_periphck[i].n, - clk_names[ID_MCK], + clk_names[ID_MCK_DIV], sam9x60_periphck[i].id, &r); if (IS_ERR(c)) { @@ -587,7 +603,7 @@ static int sam9x60_clk_probe(struct udevice *dev) p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK]; + p[3] = clk_names[ID_MCK_DIV]; p[4] = clk_names[ID_PLL_A_DIV]; p[5] = clk_names[ID_PLL_U_DIV]; m[0] = 0; @@ -599,7 +615,7 @@ static int sam9x60_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV); cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index c0d9271966d3d576939f9c2f5d9860654324b535..d1ec3c82b5473e6e5d9104ac196fac3171d605cd 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -44,7 +44,8 @@ * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier * @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier - * @ID_MCK0: MCK0 clock identifier + * @ID_MCK0_PRES: MCK0 PRES clock identifier + * @ID_MCK0_DIV: MCK0 DIV clock identifier * @ID_MCK1: MCK1 clock identifier * @ID_MCK2: MCK2 clock identifier * @ID_MCK3: MCK3 clock identifier @@ -95,7 +96,7 @@ enum pmc_clk_ids { ID_PLL_ETH_FRAC = 20, ID_PLL_ETH_DIV = 21, - ID_MCK0 = 22, + ID_MCK0_DIV = 22, ID_MCK1 = 23, ID_MCK2 = 24, ID_MCK3 = 25, @@ -121,6 +122,8 @@ enum pmc_clk_ids { ID_PCK6 = 42, ID_PCK7 = 43, + ID_MCK0_PRES = 44, + ID_MAX, }; @@ -147,7 +150,8 @@ static const char *clk_names[] = { [ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck", [ID_PLL_AUDIO_DIVIO] = "audiopll_diviock", [ID_PLL_ETH_DIV] = "ethpll_divpmcck", - [ID_MCK0] = "mck0", + [ID_MCK0_DIV] = "mck0_div", + [ID_MCK0_PRES] = "mck0_pres", }; /* Fractional PLL output range. */ @@ -504,7 +508,7 @@ static const struct { struct clk_range r; u8 id; } sama7g5_periphck[] = { - { .n = "pioA_clk", .p = "mck0", .id = 11, }, + { .n = "pioA_clk", .p = "mck0_div", .id = 11, }, { .n = "sfr_clk", .p = "mck1", .id = 19, }, { .n = "hsmc_clk", .p = "mck1", .id = 21, }, { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, @@ -514,7 +518,7 @@ static const struct { { .n = "aes_clk", .p = "mck1", .id = 27, }, { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, }, { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, }, - { .n = "cpkcc_clk", .p = "mck0", .id = 32, }, + { .n = "cpkcc_clk", .p = "mck0_div", .id = 32, }, { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, }, { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, }, { .n = "eic_clk", .p = "mck1", .id = 37, }, @@ -1210,7 +1214,7 @@ static int sama7g5_clk_probe(struct udevice *dev) sama7g5_plls[i].c)); } - /* Register MCK0 clock. */ + /* Register MCK0_PRES clock. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_MAINCK]; p[2] = clk_names[ID_PLL_CPU_DIV]; @@ -1221,15 +1225,19 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, fail); - clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0), - at91_clk_register_master(base, clk_names[ID_MCK0], p, + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES), + at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], p, 4, &mck0_layout, &mck0_characteristics, tmpclkmux)); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV), + at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV], + clk_names[ID_MCK0_PRES], &mck0_layout, &mck0_characteristics)); + /* Register MCK1-4 clocks. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK0]; + p[3] = clk_names[ID_MCK0_DIV]; m[0] = 0; m[1] = 1; m[2] = 2; @@ -1237,7 +1245,7 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { for (j = 0; j < sama7g5_mckx[i].ep_count; j++) { p[4 + j] = sama7g5_mckx[i].ep[j]; @@ -1267,7 +1275,7 @@ static int sama7g5_clk_probe(struct udevice *dev) p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK0]; + p[3] = clk_names[ID_MCK0_DIV]; p[4] = clk_names[ID_PLL_SYS_DIV]; p[5] = clk_names[ID_PLL_DDR_DIV]; p[6] = clk_names[ID_PLL_IMG_DIV]; @@ -1277,7 +1285,7 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_DDR_DIV); cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_IMG_DIV); @@ -1315,7 +1323,7 @@ static int sama7g5_clk_probe(struct udevice *dev) p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK0]; + p[3] = clk_names[ID_MCK0_DIV]; m[0] = 0; m[1] = 1; m[2] = 2; @@ -1323,7 +1331,7 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { for (j = 0; j < sama7g5_gck[i].ep_count; j++) { p[4 + j] = sama7g5_gck[i].ep[j]; diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index cea38a4c6e522a196a8cc23b903a0823adcd05af..493018b33eb6ae583ec19bb7ba4462d4935fa11f 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -35,10 +35,9 @@ struct clk *dev_get_clk_ptr(struct udevice *dev) return (struct clk *)dev_get_uclass_priv(dev); } -#if CONFIG_IS_ENABLED(OF_CONTROL) -# if CONFIG_IS_ENABLED(OF_PLATDATA) -int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, - struct clk *clk) +#if CONFIG_IS_ENABLED(OF_PLATDATA) +int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, + struct clk *clk) { int ret; @@ -49,7 +48,9 @@ int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, return 0; } -# else +#endif + +#if CONFIG_IS_ENABLED(OF_REAL) static int clk_of_xlate_default(struct clk *clk, struct ofnode_phandle_args *args) { @@ -412,7 +413,7 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } -# endif /* OF_PLATDATA */ +#endif /* OF_REAL */ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) { @@ -465,8 +466,6 @@ int clk_release_all(struct clk *clk, int count) return 0; } -#endif /* OF_CONTROL */ - int clk_request(struct udevice *dev, struct clk *clk) { const struct clk_ops *ops; diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c index e51f94a937108d84e62b02d74481c94af28e9b69..41b0d9c0603ed9929e955b37b0450c1785a94e9a 100644 --- a/drivers/clk/clk_fixed_factor.c +++ b/drivers/clk/clk_fixed_factor.c @@ -40,17 +40,17 @@ const struct clk_ops clk_fixed_factor_ops = { static int clk_fixed_factor_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - int err; - struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + int err; + struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); - err = clk_get_by_index(dev, 0, &ff->parent); - if (err) - return err; + err = clk_get_by_index(dev, 0, &ff->parent); + if (err) + return err; - ff->div = dev_read_u32_default(dev, "clock-div", 1); - ff->mult = dev_read_u32_default(dev, "clock-mult", 1); -#endif + ff->div = dev_read_u32_default(dev, "clock-div", 1); + ff->mult = dev_read_u32_default(dev, "clock-mult", 1); + } return 0; } diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 325a9b2dcfb07dea945f2b6b33a7ee8743644008..e0dc4ab85f8153c5b9bd462796c7a100654dd891 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -32,9 +32,10 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, struct clk_fixed_rate *plat) { struct clk *clk = &plat->clk; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0); -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) + plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", + 0); + /* Make fixed rate clock accessible from higher level struct clk */ /* FIXME: This is not allowed */ dev_set_uclass_priv(dev, clk); diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 62523d290999e40ec101c31d8b5c0afced556af8..a9dd57b098fe57fa3de28502a6a4f468902aafbc 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[clk->id].clk_id; - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + if (versal_clock_gate(clk_id)) + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + + return 0; } static struct clk_ops versal_clk_ops = { diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index b5cbf800543b4b93b0cb2425beeb6e4c0c54d69f..077757efcb82094e7c94d8a8907f4c5f47bfaa7c 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -160,7 +160,7 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate) } static const struct clk_ops clk_pllv3_sys_ops = { - .enable = clk_pllv3_generic_enable, + .enable = clk_pllv3_generic_enable, .disable = clk_pllv3_generic_disable, .get_rate = clk_pllv3_sys_get_rate, .set_rate = clk_pllv3_sys_set_rate, diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 7204383e173e37087abbd4f7ef2b0e2b7de1d966..b9c6bd66cfab736e931bdd0da514a1641c756d22 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -7,4 +7,3 @@ obj-$(CONFIG_CLK_MESON_GX) += gxbb.o obj-$(CONFIG_CLK_MESON_AXG) += axg.o obj-$(CONFIG_CLK_MESON_G12A) += g12a.o obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o - diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 83d45c75ee221aa30fb83fc6c634a6c89fab2173..8d2aaf5b843df0faa3471a26a6522e42443a42dc 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -359,4 +359,3 @@ rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, else return ps; } - diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index a49b6f19f4f6685b8eae367971d167a8ea5f0903..617ce0dce5ace541f775464f81321b6ac8e4bcaf 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1367,7 +1367,7 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) { struct px30_clk_priv *priv = dev_get_priv(clk->dev); @@ -1418,7 +1418,7 @@ static int px30_clk_enable(struct clk *clk) static struct clk_ops px30_clk_ops = { .get_rate = px30_clk_get_rate, .set_rate = px30_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = px30_clk_set_parent, #endif .enable = px30_clk_enable, diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 1b62d8d2898be7aad3da436fd49b6db6d4f29f17..038cb55965e89bfa012642da708d6713b53c7c53 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -540,11 +540,11 @@ static struct clk_ops rk3188_clk_ops = { static int rk3188_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3188_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3188_clk_priv *priv = dev_get_priv(dev); - priv->cru = dev_read_addr_ptr(dev); -#endif + priv->cru = dev_read_addr_ptr(dev); + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 221a5bd400f68be3052448a79d66abb538fb2bd7..3b29992c3e59385039f903d151c1883cec457853 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -950,18 +950,18 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par static struct clk_ops rk3288_clk_ops = { .get_rate = rk3288_clk_get_rate, .set_rate = rk3288_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3288_clk_set_parent, #endif }; static int rk3288_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3288_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3288_clk_priv *priv = dev_get_priv(dev); - priv->cru = dev_read_addr_ptr(dev); -#endif + priv->cru = dev_read_addr_ptr(dev); + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 5248e596853e9559120ccd30d2bee598b77b03b2..2876643e6be791f887742c258c13b1f623e6578d 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -939,7 +939,7 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent) { struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); @@ -976,7 +976,7 @@ static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *par static struct clk_ops rk3308_clk_ops = { .get_rate = rk3308_clk_get_rate, .set_rate = rk3308_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3308_clk_set_parent, #endif }; diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 780b49ccd89b68119e64866118cb480b435f498a..39caf23c31fc7e7ce92f8d672f4b629e6c8b0821 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -158,7 +158,7 @@ static void rkclk_init(struct rk3368_cru *cru) } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) +#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) { u32 div, con, con_id, rate; @@ -470,7 +470,7 @@ static ulong rk3368_clk_get_rate(struct clk *clk) case SCLK_SPI0 ... SCLK_SPI2: rate = rk3368_spi_get_clk(priv->cru, clk->id); break; -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) +#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: rate = rk3368_mmc_get_clk(priv->cru, clk->id); @@ -501,7 +501,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_ddr_set_clk(priv->cru, rate); break; #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) +#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: ret = rk3368_mmc_set_clk(clk, rate); @@ -574,7 +574,7 @@ static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *par static struct clk_ops rk3368_clk_ops = { .get_rate = rk3368_clk_get_rate, .set_rate = rk3368_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3368_clk_set_parent, #endif }; @@ -596,11 +596,11 @@ static int rk3368_clk_probe(struct udevice *dev) static int rk3368_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3368_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3368_clk_priv *priv = dev_get_priv(dev); - priv->cru = dev_read_addr_ptr(dev); -#endif + priv->cru = dev_read_addr_ptr(dev); + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index f8cbda44551e0bbecdb6a886b0e3a4b5d32b88a6..7d31a9f22a85fdb0673922eba9734cf9af238b0a 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1289,7 +1289,7 @@ static int rk3399_clk_disable(struct clk *clk) static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3399_clk_set_parent, #endif .enable = rk3399_clk_enable, @@ -1402,11 +1402,12 @@ static int rk3399_clk_probe(struct udevice *dev) static int rk3399_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3399_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3399_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + } - priv->cru = dev_read_addr_ptr(dev); -#endif return 0; } @@ -1614,11 +1615,12 @@ static int rk3399_pmuclk_probe(struct udevice *dev) static int rk3399_pmuclk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); + + priv->pmucru = dev_read_addr_ptr(dev); + } - priv->pmucru = dev_read_addr_ptr(dev); -#endif return 0; } diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 9ae188c1dfc5b918227d2b5f565bd8ccd5aaafe2..8f7703c8b580c972b2f185eb97e9af5e04360230 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -80,7 +80,6 @@ config DM_DEVICE_REMOVE config SPL_DM_DEVICE_REMOVE bool "Support device removal in SPL" depends on SPL_DM - default n help We can save some code space by dropping support for removing a device. This is not normally required in SPL, so by default this @@ -107,7 +106,6 @@ config DM_SEQ_ALIAS config SPL_DM_SEQ_ALIAS bool "Support numbered aliases in device tree in SPL" depends on SPL_DM - default n help Most boards will have a '/aliases' node containing the path to numbered devices (e.g. serial0 = &serial0). This feature can be @@ -132,7 +130,6 @@ config TPL_DM_INLINE_OFNODE config DM_DMA bool "Support per-device DMA constraints" depends on DM - default n help Enable this to extract per-device DMA constraints, only supported on device-tree systems for now. This is needed in order translate @@ -274,7 +271,6 @@ config OF_TRANSLATE config SPL_OF_TRANSLATE bool "Translate addresses using fdt_translate_address in SPL" depends on SPL_DM && SPL_OF_CONTROL - default n help If this option is enabled, the reg property will be translated using the fdt_translate_address() function. This is necessary diff --git a/drivers/core/device.c b/drivers/core/device.c index 29668f6fb30e4eecd10308264e362bf5ef47c037..42ba2dce46584ac52bce79487ebc5ad33c616b56 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -670,7 +670,7 @@ static int device_get_device_tail(struct udevice *dev, int ret, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * device_find_by_ofnode() - Return device associated with given ofnode * @@ -1074,7 +1074,7 @@ void dev_set_uclass_plat(struct udevice *dev, void *uclass_plat) dev->uclass_plat_ = uclass_plat; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) bool device_is_compatible(const struct udevice *dev, const char *compat) { return ofnode_device_is_compatible(dev_ofnode(dev), compat); diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 4ffbd6b2ebc1ec0e7235a2cc4f1c69ba09b6d78d..6dfda20772636ffa56c31037a73a5e5afeeef3e8 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) fdt_addr_t addr; if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { diff --git a/drivers/core/lists.c b/drivers/core/lists.c index e214306b904bc0032f333d7ad15a6ff74bde7ba3..350b9d32687c189bd596326943b14d9b94cd9f92 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -154,7 +154,7 @@ int device_bind_driver_to_node(struct udevice *parent, const char *drv_name, return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * driver_check_compatible() - Check if a driver matches a compatible string * diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 701b23e2c91285ffde9ec618c94074516f739d43..08705ef8d99b98a8b77f988982af24aae0440787 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1103,3 +1103,36 @@ int ofnode_set_enabled(ofnode node, bool value) else return ofnode_write_string(node, "status", "disabled"); } + +bool ofnode_conf_read_bool(const char *prop_name) +{ + ofnode node; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return false; + + return ofnode_read_bool(node, prop_name); +} + +int ofnode_conf_read_int(const char *prop_name, int default_val) +{ + ofnode node; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return default_val; + + return ofnode_read_u32_default(node, prop_name, default_val); +} + +const char *ofnode_conf_read_str(const char *prop_name) +{ + ofnode node; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return NULL; + + return ofnode_read_string(node, prop_name); +} diff --git a/drivers/core/root.c b/drivers/core/root.c index 78eee082c95433243466d1bc776b22dbfce6a8cc..fecdcb5b308fb35f11cf2e17f0b680aea97d9d07 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -245,7 +245,7 @@ int dm_scan_plat(bool pre_reloc_only) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node * @@ -372,7 +372,7 @@ static int dm_scan(bool pre_reloc_only) return ret; } - if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { + if (CONFIG_IS_ENABLED(OF_REAL)) { ret = dm_extended_scan(pre_reloc_only); if (ret) { debug("dm_extended_scan() failed: %d\n", ret); diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index abc55c217197b5df23a1d057f30073c1634c7f6b..6022e7514e0e99ebda831a5724a2eb877a7ff9f5 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -65,7 +65,7 @@ UCLASS_DRIVER(simple_bus) = { .per_device_plat_auto = sizeof(struct simple_bus_plat), }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id generic_simple_bus_ids[] = { { .compatible = "simple-bus" }, { .compatible = "simple-mfd" }, diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index cb33facc7138939ad44e70f2c95c7401f2fd8b69..25fdb66eaa07154ae53dc46960d9e3e1696678d1 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -186,7 +186,7 @@ static const struct udevice_id generic_syscon_ids[] = { U_BOOT_DRIVER(generic_syscon) = { .name = "syscon", .id = UCLASS_SYSCON, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .of_match = generic_syscon_ids, diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 3146dfd0320d75be404cda41819e6d5933f32331..c5a50952fd0d29729aafe7355cd5b2bd1e115e6f 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -397,7 +397,7 @@ done: return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent, const char *name, struct udevice **devp) { diff --git a/drivers/core/util.c b/drivers/core/util.c index 5be4ee79deb99bfb7c95ca56c671ec36b2667c92..aa60fdd15bc4b1ed9ba55c013f234d9caf5a3b2c 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -22,7 +22,7 @@ int list_count_items(struct list_head *head) return count; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int pci_get_devfn(struct udevice *dev) { struct fdt_pci_addr addr; diff --git a/drivers/cpu/at91_cpu.c b/drivers/cpu/at91_cpu.c index 9ef1b3102cd1d0a512306d669d62eff293711ee6..34a3f61c7e95709afb42a4dd2a35e05ed075714f 100644 --- a/drivers/cpu/at91_cpu.c +++ b/drivers/cpu/at91_cpu.c @@ -70,6 +70,7 @@ static const struct cpu_ops at91_cpu_ops = { static const struct udevice_id at91_cpu_ids[] = { { .compatible = "arm,cortex-a7" }, + { .compatible = "arm,arm926ej-s" }, { /* Sentinel. */ } }; diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index fe6772ba5ac22b32167f0e5e91d2c9e36ca90d2a..2e871fe313c107d83a0c85e103e406cfe2ed57fe 100644 --- a/drivers/cpu/cpu_sandbox.c +++ b/drivers/cpu/cpu_sandbox.c @@ -38,7 +38,7 @@ static int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf, return 0; } -static const char *cpu_current = "cpu-test1"; +static const char *cpu_current = "cpu@1"; void cpu_sandbox_set_current(const char *name) { diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 1ea116be7503b7e3054fc72fe48fb2afd563bb58..0082177c21f00c80ff64b3c3078aed6c000f16e2 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -1,5 +1,7 @@ menu "Hardware crypto devices" +source drivers/crypto/hash/Kconfig + source drivers/crypto/fsl/Kconfig endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index efbd1d3fca0561d8530761563ddc8c81d89512be..e8bae43e3f09ed41ff31dc8b87fdc6c8bc153a09 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2013 Samsung Electronics Co., Ltd. -# http://www.samsung.com +# http://www.samsung.com obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o obj-y += rsa_mod_exp/ obj-y += fsl/ +obj-y += hash/ diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..cd29a5c6a4f39c69e03b26825f0db15faf13e7ee --- /dev/null +++ b/drivers/crypto/hash/Kconfig @@ -0,0 +1,16 @@ +config DM_HASH + bool "Enable Driver Model for Hash" + depends on DM + help + If you want to use driver model for Hash, say Y. + +config HASH_SOFTWARE + bool "Enable driver for Hash in software" + depends on DM_HASH + depends on MD5 + depends on SHA1 + depends on SHA256 + depends on SHA512_ALGO + help + Enable driver for hashing operations in software. Currently + it support multiple hash algorithm including CRC/MD5/SHA. diff --git a/drivers/crypto/hash/Makefile b/drivers/crypto/hash/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..33d88161ed4ad084871d85c75e56fb6e8555780e --- /dev/null +++ b/drivers/crypto/hash/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021 ASPEED Technology Inc. + +obj-$(CONFIG_DM_HASH) += hash-uclass.o +obj-$(CONFIG_HASH_SOFTWARE) += hash_sw.o diff --git a/drivers/crypto/hash/hash-uclass.c b/drivers/crypto/hash/hash-uclass.c new file mode 100644 index 0000000000000000000000000000000000000000..446eb9e56a4f9246db856d96bb4f6082723c540b --- /dev/null +++ b/drivers/crypto/hash/hash-uclass.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 ASPEED Technology Inc. + * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com> + */ + +#define LOG_CATEGORY UCLASS_HASH + +#include <common.h> +#include <dm.h> +#include <asm/global_data.h> +#include <u-boot/hash.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/io.h> +#include <linux/list.h> + +struct hash_info { + char *name; + uint32_t digest_size; +}; + +static const struct hash_info hash_info[HASH_ALGO_NUM] = { + [HASH_ALGO_CRC16_CCITT] = { "crc16-ccitt", 2 }, + [HASH_ALGO_CRC32] = { "crc32", 4 }, + [HASH_ALGO_MD5] = { "md5", 16 }, + [HASH_ALGO_SHA1] = { "sha1", 20 }, + [HASH_ALGO_SHA256] = { "sha256", 32 }, + [HASH_ALGO_SHA384] = { "sha384", 48 }, + [HASH_ALGO_SHA512] = { "sha512", 64}, +}; + +enum HASH_ALGO hash_algo_lookup_by_name(const char *name) +{ + int i; + + if (!name) + return HASH_ALGO_INVALID; + + for (i = 0; i < HASH_ALGO_NUM; ++i) + if (!strcmp(name, hash_info[i].name)) + return i; + + return HASH_ALGO_INVALID; +} + +ssize_t hash_algo_digest_size(enum HASH_ALGO algo) +{ + if (algo >= HASH_ALGO_NUM) + return -EINVAL; + + return hash_info[algo].digest_size; +} + +const char *hash_algo_name(enum HASH_ALGO algo) +{ + if (algo >= HASH_ALGO_NUM) + return NULL; + + return hash_info[algo].name; +} + +int hash_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_digest) + return -ENOSYS; + + return ops->hash_digest(dev, algo, ibuf, ilen, obuf); +} + +int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_digest_wd) + return -ENOSYS; + + return ops->hash_digest_wd(dev, algo, ibuf, ilen, obuf, chunk_sz); +} + +int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_init) + return -ENOSYS; + + return ops->hash_init(dev, algo, ctxp); +} + +int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_update) + return -ENOSYS; + + return ops->hash_update(dev, ctx, ibuf, ilen); +} + +int hash_finish(struct udevice *dev, void *ctx, void *obuf) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_finish) + return -ENOSYS; + + return ops->hash_finish(dev, ctx, obuf); +} + +UCLASS_DRIVER(hash) = { + .id = UCLASS_HASH, + .name = "hash", +}; diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c new file mode 100644 index 0000000000000000000000000000000000000000..fea9d12609679b7737520483df18600c8588ce51 --- /dev/null +++ b/drivers/crypto/hash/hash_sw.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 ASPEED Technology Inc. + * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com> + */ +#include <config.h> +#include <common.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <watchdog.h> +#include <u-boot/hash.h> +#include <u-boot/crc.h> +#include <u-boot/md5.h> +#include <u-boot/sha1.h> +#include <u-boot/sha256.h> +#include <u-boot/sha512.h> + +/* CRC16-CCITT */ +static void hash_init_crc16_ccitt(void *ctx) +{ + *((uint16_t *)ctx) = 0; +} + +static void hash_update_crc16_ccitt(void *ctx, const void *ibuf, uint32_t ilen) +{ + *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), ibuf, ilen); +} + +static void hash_finish_crc16_ccitt(void *ctx, void *obuf) +{ + *((uint16_t *)obuf) = *((uint16_t *)ctx); +} + +/* CRC32 */ +static void hash_init_crc32(void *ctx) +{ + *((uint32_t *)ctx) = 0; +} + +static void hash_update_crc32(void *ctx, const void *ibuf, uint32_t ilen) +{ + *((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), ibuf, ilen); +} + +static void hash_finish_crc32(void *ctx, void *obuf) +{ + *((uint32_t *)obuf) = *((uint32_t *)ctx); +} + +/* MD5 */ +static void hash_init_md5(void *ctx) +{ + MD5Init((struct MD5Context *)ctx); +} + +static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen) +{ + MD5Update((struct MD5Context *)ctx, ibuf, ilen); +} + +static void hash_finish_md5(void *ctx, void *obuf) +{ + MD5Final(obuf, (struct MD5Context *)ctx); +} + +/* SHA1 */ +static void hash_init_sha1(void *ctx) +{ + sha1_starts((sha1_context *)ctx); +} + +static void hash_update_sha1(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha1_update((sha1_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha1(void *ctx, void *obuf) +{ + sha1_finish((sha1_context *)ctx, obuf); +} + +/* SHA256 */ +static void hash_init_sha256(void *ctx) +{ + sha256_starts((sha256_context *)ctx); +} + +static void hash_update_sha256(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha256_update((sha256_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha256(void *ctx, void *obuf) +{ + sha256_finish((sha256_context *)ctx, obuf); +} + +/* SHA384 */ +static void hash_init_sha384(void *ctx) +{ + sha384_starts((sha512_context *)ctx); +} + +static void hash_update_sha384(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha384_update((sha512_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha384(void *ctx, void *obuf) +{ + sha384_finish((sha512_context *)ctx, obuf); +} + +/* SHA512 */ +static void hash_init_sha512(void *ctx) +{ + sha512_starts((sha512_context *)ctx); +} + +static void hash_update_sha512(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha512_update((sha512_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha512(void *ctx, void *obuf) +{ + sha512_finish((sha512_context *)ctx, obuf); +} + +struct sw_hash_ctx { + enum HASH_ALGO algo; + uint8_t algo_ctx[]; +}; + +struct sw_hash_impl { + void (*init)(void *ctx); + void (*update)(void *ctx, const void *ibuf, uint32_t ilen); + void (*finish)(void *ctx, void *obuf); + uint32_t ctx_alloc_sz; +}; + +static struct sw_hash_impl sw_hash_impl[HASH_ALGO_NUM] = { + [HASH_ALGO_CRC16_CCITT] = { + .init = hash_init_crc16_ccitt, + .update = hash_update_crc16_ccitt, + .finish = hash_finish_crc16_ccitt, + .ctx_alloc_sz = sizeof(uint16_t), + }, + + [HASH_ALGO_CRC32] = { + .init = hash_init_crc32, + .update = hash_update_crc32, + .finish = hash_finish_crc32, + .ctx_alloc_sz = sizeof(uint32_t), + }, + + [HASH_ALGO_MD5] = { + .init = hash_init_md5, + .update = hash_update_md5, + .finish = hash_finish_md5, + .ctx_alloc_sz = sizeof(struct MD5Context), + }, + + [HASH_ALGO_SHA1] = { + .init = hash_init_sha1, + .update = hash_update_sha1, + .finish = hash_finish_sha1, + .ctx_alloc_sz = sizeof(sha1_context), + }, + + [HASH_ALGO_SHA256] = { + .init = hash_init_sha256, + .update = hash_update_sha256, + .finish = hash_finish_sha256, + .ctx_alloc_sz = sizeof(sha256_context), + }, + + [HASH_ALGO_SHA384] = { + .init = hash_init_sha384, + .update = hash_update_sha384, + .finish = hash_finish_sha384, + .ctx_alloc_sz = sizeof(sha512_context), + }, + + [HASH_ALGO_SHA512] = { + .init = hash_init_sha512, + .update = hash_update_sha512, + .finish = hash_finish_sha512, + .ctx_alloc_sz = sizeof(sha512_context), + }, +}; + +static int sw_hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) +{ + struct sw_hash_ctx *hash_ctx; + struct sw_hash_impl *hash_impl = &sw_hash_impl[algo]; + + hash_ctx = malloc(sizeof(hash_ctx->algo) + hash_impl->ctx_alloc_sz); + if (!hash_ctx) + return -ENOMEM; + + hash_ctx->algo = algo; + + hash_impl->init(hash_ctx->algo_ctx); + + *ctxp = hash_ctx; + + return 0; +} + +static int sw_hash_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen) +{ + struct sw_hash_ctx *hash_ctx = ctx; + struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo]; + + hash_impl->update(hash_ctx->algo_ctx, ibuf, ilen); + + return 0; +} + +static int sw_hash_finish(struct udevice *dev, void *ctx, void *obuf) +{ + struct sw_hash_ctx *hash_ctx = ctx; + struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo]; + + hash_impl->finish(hash_ctx->algo_ctx, obuf); + + free(ctx); + + return 0; +} + +static int sw_hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz) +{ + int rc; + void *ctx; + const void *cur, *end; + uint32_t chunk; + + rc = sw_hash_init(dev, algo, &ctx); + if (rc) + return rc; + + if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { + cur = ibuf; + end = ibuf + ilen; + + while (cur < end) { + chunk = end - cur; + if (chunk > chunk_sz) + chunk = chunk_sz; + + rc = sw_hash_update(dev, ctx, cur, chunk); + if (rc) + return rc; + + cur += chunk; + WATCHDOG_RESET(); + } + } else { + rc = sw_hash_update(dev, ctx, ibuf, ilen); + if (rc) + return rc; + } + + rc = sw_hash_finish(dev, ctx, obuf); + if (rc) + return rc; + + return 0; +} + +static int sw_hash_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf) +{ + /* re-use the watchdog version with input length as the chunk_sz */ + return sw_hash_digest_wd(dev, algo, ibuf, ilen, obuf, ilen); +} + +static const struct hash_ops hash_ops_sw = { + .hash_init = sw_hash_init, + .hash_update = sw_hash_update, + .hash_finish = sw_hash_finish, + .hash_digest_wd = sw_hash_digest_wd, + .hash_digest = sw_hash_digest, +}; + +U_BOOT_DRIVER(hash_sw) = { + .name = "hash_sw", + .id = UCLASS_HASH, + .ops = &hash_ops_sw, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRVINFO(hash_sw) = { + .name = "hash_sw", +}; diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index d4b393d25e07977be1c5fca14429b3878ff1691e..eec9d480b096ad265c8aa74016ea8b58d3f1dcd3 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1,2 +1,34 @@ +choice + prompt "Method to determine DDR clock frequency" + default STATIC_DDR_CLK_FREQ + depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \ + || ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \ + || FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2 + help + The DDR clock frequency can either be defined statically now at + build time, or can be determined at run-time via the + get_board_ddr_clk function. + +config DYNAMIC_DDR_CLK_FREQ + bool "Run-time DDR clock frequency" + +config STATIC_DDR_CLK_FREQ + bool "Build-time static DDR clock frequency" + +endchoice + +config DDR_CLK_FREQ + int "DDR clock frequency in Hz" + depends on STATIC_DDR_CLK_FREQ + default 100000000 + help + The DDR clock frequency, specified in Hz. + +config DDR_SPD + bool "JEDEC Serial Presence Detect (SPD) support" + help + For memory controllers that can utilize it, add enable support for + using the JEDEC SDP standard. + source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 3caa2e14f9466212d48ba9bed089a66e90c16d67..d3a6d21860c2a40dbb7f88541a91f98ec35071fa 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -335,4 +335,3 @@ int sdram_mmr_init_full(struct udevice *dev) debug("DDR: HMC init success\n"); return 0; } - diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 8246f627982c1ff27ad5c011ed2192e2bbd03dbe..fe3d6fc9700e922b3196512ba6f78d7b55b16493 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -10,6 +10,8 @@ config SYS_FSL_MMDC help Select Freescale Multi Mode DDR controller (MMDC). +if SYS_FSL_DDR || SYS_FSL_MMDC + config SYS_FSL_DDR_BE bool help @@ -116,28 +118,51 @@ choice config SYS_FSL_DDR4 bool "Freescale DDR4 controller" depends on SYS_FSL_HAS_DDR4 + imply DDR_SPD select SYS_FSL_DDRC_GEN4 config SYS_FSL_DDR3 bool "Freescale DDR3 controller" depends on SYS_FSL_HAS_DDR3 + imply DDR_SPD select SYS_FSL_DDRC_GEN3 if PPC select SYS_FSL_DDRC_ARM_GEN3 if ARM config SYS_FSL_DDR2 bool "Freescale DDR2 controller" depends on SYS_FSL_HAS_DDR2 + imply DDR_SPD select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) config SYS_FSL_DDR1 bool "Freescale DDR1 controller" depends on SYS_FSL_HAS_DDR1 + imply DDR_SPD select SYS_FSL_DDRC_GEN1 endchoice endmenu +config FSL_DMA + def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER + +config DDR_ECC + bool "ECC DDR memory support" + +config DDR_ECC_CMD + bool "Access the ECC features of the memory controller" + depends on DDR_ECC && MPC83xx + default y + +config ECC_INIT_VIA_DDRCONTROLLER + bool "DDR Memory controller initializes memory." + help + Use the DDR controller to auto initialize memory. If not enabled, + the DMA controller is responsible for doing this. + +endif + config SYS_FSL_ERRATUM_A008378 bool diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index 8464438c544fed2ff6ebb569238a34c563dc1e37..1f8db90c45bde2b6956a150d9ba2182cdf679728 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -36,18 +36,18 @@ * 0110 16Gb 2GB * * SPD byte8 - module memory bus width - * bit[2:0] primary bus width + * bit[2:0] primary bus width * 000 8bits - * 001 16bits - * 010 32bits - * 011 64bits + * 001 16bits + * 010 32bits + * 011 64bits * * SPD byte7 - module organiztion - * bit[2:0] sdram device width - * 000 4bits - * 001 8bits - * 010 16bits - * 011 32bits + * bit[2:0] sdram device width + * 000 4bits + * 001 8bits + * 010 16bits + * 011 32bits * */ static unsigned long long diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 2512b58cb7b221dc7b3a5d81320f14e1f8f8eb0f..0ddd5aea75e5bbc0fe66052ce7878d30d23adedd 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -2895,4 +2895,3 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void) return odt_n; } - diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index 270691e9bcd35f8e9ea226f72da0fe406939546c..970651f8702944897ac3ce95c797a7c455b73530 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -19,10 +19,10 @@ #define FAR_END_DIMM_ADDR 0x50 #define MAX_DIMM_ADDR 0x60 -#ifndef CONFIG_DDR_FIXED_SIZE +#ifndef CONFIG_SYS_SDRAM_SIZE #define SDRAM_CS_SIZE 0xFFFFFFF #else -#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) +#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) #endif #define SDRAM_CS_BASE 0x0 #define SDRAM_DIMM_SIZE 0x80000000 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 10d064d0a308355ae76011aace40176c50c0a1ba..437a02efbac9651ea0e75312d095a808e5b6516c 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -16,11 +16,7 @@ * Level 3: Provides the windows margin of each DQ as a results of DQS * centeralization */ -#ifdef CONFIG_DDR_LOG_LEVEL #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL -#else -#define DDR3_LOG_LEVEL 0 -#endif #define DDR3_PBS 1 diff --git a/drivers/ddr/marvell/axp/ddr3_spd.c b/drivers/ddr/marvell/axp/ddr3_spd.c index e2305d881450dc78519adb6428de351d944cc325..dd772e63ab19303efbfd2db8b2abbf0572e116fc 100644 --- a/drivers/ddr/marvell/axp/ddr3_spd.c +++ b/drivers/ddr/marvell/axp/ddr3_spd.c @@ -46,7 +46,7 @@ #define SPD_COL_NUM_MASK (7 << SPD_COL_NUM_OFF) #define SPD_MODULE_ORG_BYTE 7 -#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0 +#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0 #define SPD_MODULE_SDRAM_DEV_WIDTH_MASK (7 << SPD_MODULE_SDRAM_DEV_WIDTH_OFF) #define SPD_MODULE_BANK_NUM_MIN 1 #define SPD_MODULE_BANK_NUM_OFF 3 diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index b50547476cbd37e978f77e4716c835a56b724526..48e41bc2629030d3df5014f60dbecff3e8987cb9 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -16,7 +16,6 @@ config DFU_OVER_TFTP if DFU config DFU_WRITE_ALT bool - default n config DFU_TFTP bool "DFU via TFTP" diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1993c1d31dfea12c19ef05cdef538850a3e1a69b..9cacea88d0cb9ebfd94a63fb967ebbcbd5744b6d 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -35,19 +35,40 @@ config BCM6348_IUDMA This driver support data transfer from devices to memory and from memory to devices. +config DMA_LPC32XX + bool "LPC32XX DMA driver" + select DMA_LEGACY + help + Enable some legacy DMA code for lpc32xx. It provides some direct + functions likes lpc32xx_dma_wait_status() which can be called from + other code. + + This should be converted to use driver model and UCLASS_DMA. + config TI_EDMA3 bool "TI EDMA3 driver" + select DMA_LEGACY help Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. This driver support data transfer between memory regions. +config TI_KSNAV + bool "TI Keystone Navigator DMA driver" + depends on ARCH_KEYSTONE + default y + select DMA_LEGACY + help + Enable the Keystone Navigator driver for Keystone 2 platforms. + config APBH_DMA bool "Support APBH DMA" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M + select DMA_LEGACY help Enable APBH DMA driver. + if APBH_DMA config APBH_DMA_BURST bool "Enable DMA BURST" @@ -57,6 +78,15 @@ config APBH_DMA_BURST8 endif +config DMA_LEGACY + bool "Legacy DMA support" + default y if FSLDMAFEC + help + Enable legacy DMA support. This does not use driver model and should + be migrated to the new API. + + It is required for some PowerPC boards. + source "drivers/dma/ti/Kconfig" endmenu # menu "DMA Support" diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index b7eddf0f04c5d377fe47d2d42b92fe396be76144..1864b5d88b08b36e889ca47a80f0ab623ac617f7 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -130,11 +130,9 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { /* * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER - * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA */ #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ - !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ - (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))) void dma_meminit(uint val, uint size) { uint *p = 0; diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index 443e4b23669a2b0ae2fd4e87a7d70fe226718257..9a5ba79f3fe523d404dbe3d7b72021c58548785a 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -11,20 +11,20 @@ #include <linux/delay.h> struct qm_config qm_memmap = { - .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE, - .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE, - .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS, - .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE, - .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE, - .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE, - .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE, - .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE, - .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE, - .region_num = CONFIG_KSNAV_QM_REGION_NUM, - .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE, - .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE, - .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE, - .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM, + .stat_cfg = KS2_QM_QUEUE_STATUS_BASE, + .queue = (void *)KS2_QM_MANAGER_QUEUES_BASE, + .mngr_vbusm = KS2_QM_BASE_ADDRESS, + .i_lram = KS2_QM_LINK_RAM_BASE, + .proxy = (void *)KS2_QM_MANAGER_Q_PROXY_BASE, + .status_ram = KS2_QM_STATUS_RAM_BASE, + .mngr_cfg = (void *)KS2_QM_CONF_BASE, + .intd_cfg = KS2_QM_INTD_CONF_BASE, + .desc_mem = (void *)KS2_QM_DESC_SETUP_BASE, + .region_num = KS2_QM_REGION_NUM, + .pdsp_cmd = KS2_QM_PDSP1_CMD_BASE, + .pdsp_ctl = KS2_QM_PDSP1_CTRL_BASE, + .pdsp_iram = KS2_QM_PDSP1_IRAM_BASE, + .qpool_num = KS2_QM_QPOOL_NUM, }; /* @@ -252,7 +252,7 @@ int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers) writel(0, &pktdma->global->emulation_control); /* Set QM base address, only for K2x devices */ - writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); + writel(KS2_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); /* Enable all channels. The current state isn't important */ for (j = 0; j < pktdma->tx_ch_num; j++) { diff --git a/drivers/dma/keystone_nav_cfg.c b/drivers/dma/keystone_nav_cfg.c index 9a64801cf9b277d06109f783a5f2e1faac8c8220..301419b6fdac8f00ca5ad4315687b3e9ce6a119c 100644 --- a/drivers/dma/keystone_nav_cfg.c +++ b/drivers/dma/keystone_nav_cfg.c @@ -8,19 +8,17 @@ #include <asm/ti-common/keystone_nav.h> -#ifdef CONFIG_KSNAV_PKTDMA_NETCP /* NETCP Pktdma */ struct pktdma_cfg netcp_pktdma = { - .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE, - .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE, - .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM, - .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE, - .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM, - .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE, - .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE, - .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM, - .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE, - .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE, - .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE, + .global = (void *)KS2_NETCP_PDMA_CTRL_BASE, + .tx_ch = (void *)KS2_NETCP_PDMA_TX_BASE, + .tx_ch_num = KS2_NETCP_PDMA_TX_CH_NUM, + .rx_ch = (void *)KS2_NETCP_PDMA_RX_BASE, + .rx_ch_num = KS2_NETCP_PDMA_RX_CH_NUM, + .tx_sched = (u32 *)KS2_NETCP_PDMA_SCHED_BASE, + .rx_flows = (void *)KS2_NETCP_PDMA_RX_FLOW_BASE, + .rx_flow_num = KS2_NETCP_PDMA_RX_FLOW_NUM, + .rx_free_q = KS2_NETCP_PDMA_RX_FREE_QUEUE, + .rx_rcv_q = KS2_NETCP_PDMA_RX_RCV_QUEUE, + .tx_snd_q = KS2_NETCP_PDMA_TX_SND_QUEUE, }; -#endif diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 9cbd5f334dc819b51b92ce00b1a423f4007914ee..87c026e049031aa2575ed36674a87e20be12f864 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -9,7 +9,6 @@ config TI_K3_NAVSS_UDMA select TI_K3_NAVSS_RINGACC select TI_K3_NAVSS_PSILCFG select TI_K3_PSIL - default n help Support for UDMA used in K3 devices. endif diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 2d1836a80e09becea542714ab50a7cbf586151f7..d5e4a02098a2da23f1b3ce4a1b4257c684e5f8d9 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -74,7 +74,6 @@ config FASTBOOT_FLASH config FASTBOOT_UUU_SUPPORT bool "Enable FASTBOOT i.MX UUU special command" - default n help The fastboot protocol includes "UCmd" and "ACmd" command. Be aware that you provide full access to any U-Boot command, diff --git a/drivers/firmware/firmware-uclass.c b/drivers/firmware/firmware-uclass.c index bfaf283eed5f85ba97ca79025ba47a12c4ff227b..e83a147a000b6d919cd10d530e4b4b1ac209efe7 100644 --- a/drivers/firmware/firmware-uclass.c +++ b/drivers/firmware/firmware-uclass.c @@ -9,7 +9,7 @@ UCLASS_DRIVER(firmware) = { .id = UCLASS_FIRMWARE, .name = "firmware", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile index e1e02240664d640f17715c98b9e231711bfa2f52..966475ec10af0657ef83903660a4c54eccc2a795 100644 --- a/drivers/firmware/scmi/Makefile +++ b/drivers/firmware/scmi/Makefile @@ -1,5 +1,5 @@ obj-y += scmi_agent-uclass.o obj-y += smt.o -obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o +obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o obj-$(CONFIG_DM_MAILBOX) += mailbox_agent.o obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 685957626be6e071041cdf6450b9c41d4f6b633d..d73414d5ac54140c677b01172e61536e29d5a6ce 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -69,4 +69,3 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); } - diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e37ac9f49410a94251d85252e6d52e438546ae11..f0439e24178455505d6fb11686cc3aaf02ea81c4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -2,7 +2,19 @@ # GPIO infrastructure and drivers # -menu "GPIO Support" +menuconfig GPIO + bool "GPIO support" + default y + help + Enable support for GPIOs (General-purpose Input/Output) in U-Boot. + GPIOs allow U-Boot to read the state of an input line (high or + low) and set the state of an output line. This can be used to + drive LEDs, control power to various system parts and read user + input. GPIOs can be useful to enable a 'sign-of-life' LED, + for example. Enable this option to build the drivers in + drivers/gpio as part of an U-Boot build. + +if GPIO config DM_GPIO bool "Enable Driver Model for GPIO drivers" @@ -39,7 +51,6 @@ config TPL_DM_GPIO config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO - default n help Enable gpio hog support The GPIO chip may contain GPIO hog definitions. GPIO hogging @@ -91,13 +102,11 @@ config CORTINA_GPIO config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO - default n help Support for the Designware APB GPIO driver. config AT91_GPIO bool "AT91 PIO GPIO driver" - default n help Say yes here to select AT91 PIO GPIO driver. AT91 PIO controller manages up to 32 fully programmable input/output @@ -110,7 +119,6 @@ config AT91_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" depends on DM_GPIO - default n help Say yes here to support the Atmel PIO4 driver. The PIO4 is new version of Atmel PIO controller, which manages @@ -150,13 +158,11 @@ config INTEL_ICH6_GPIO config IMX_RGPIO2P bool "i.MX7ULP RGPIO2P driver" depends on DM - default n help This driver supports i.MX7ULP Rapid GPIO2P controller. config IPROC_GPIO bool "Broadcom iProc GPIO driver(without pinconf)" - default n help The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray, use the same GPIO Controller IP hence this driver could be used @@ -168,14 +174,12 @@ config IPROC_GPIO config HSDK_CREG_GPIO bool "HSDK CREG GPIO griver" depends on DM_GPIO - default n help This driver supports CREG GPIOs on Synopsys HSDK SOC. config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM - default n help Support for the LPC32XX GPIO driver. @@ -203,7 +207,6 @@ config MSCC_SGPIO config MSM_GPIO bool "Qualcomm GPIO driver" depends on DM_GPIO - default n help Support GPIO controllers on Qualcomm Snapdragon family of SoCs. This controller have single bank (default name "soc"), every @@ -345,7 +348,6 @@ config GPIO_UNIPHIER config VYBRID_GPIO bool "Vybrid GPIO driver" depends on DM - default n help Say yes here to support Vybrid vf610 GPIOs. @@ -513,4 +515,4 @@ config NOMADIK_GPIO into a number of banks each with 32 GPIOs. The GPIOs for a device are defined in the device tree with one node for each bank. -endmenu +endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 58f4704f6bc0c77d7e05a237759eb9270df8e6a7..a9dc546a20b45bc231d0a1ed7019eddedbcad7ba 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -23,7 +23,6 @@ obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o -obj-$(CONFIG_MARVELL_MFP) += mvmfp.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o @@ -33,7 +32,7 @@ obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o obj-$(CONFIG_S5P) += s5p_gpio.o -obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o +obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o @@ -62,7 +61,7 @@ obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o +obj-$(CONFIG_$(SPL_TPL_)PM8916_GPIO) += pm8916_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 8c77777dbe3b6ca1724ee70536900c7ca10c47ac..bb2f23241edba54f6baddc051c6ad14ee9cf09e5 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <dt-structs.h> #include <log.h> #include <dm/devres.h> #include <dm/device_compat.h> @@ -231,7 +232,7 @@ static int gpio_find_and_xlate(struct gpio_desc *desc, return gpio_xlate_offs_flags(desc->dev, desc, args); } -#if defined(CONFIG_GPIO_HOG) +#if CONFIG_IS_ENABLED(GPIO_HOG) struct gpio_hog_priv { struct gpio_desc gpiod; @@ -1137,7 +1138,7 @@ err: return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int _gpio_request_by_name_nodev(ofnode node, const char *list_name, int index, struct gpio_desc *desc, int flags, bool add_index) @@ -1226,6 +1227,27 @@ int gpio_get_list_count(struct udevice *dev, const char *list_name) } #endif /* OF_PLATDATA */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) +int gpio_request_by_phandle(struct udevice *dev, + const struct phandle_2_arg *cells, + struct gpio_desc *desc, int flags) +{ + struct ofnode_phandle_args args; + struct udevice *gpio_dev; + const int index = 0; + int ret; + + ret = device_get_by_ofplat_idx(cells->idx, &gpio_dev); + if (ret) + return ret; + args.args[0] = cells->arg[0]; + args.args[1] = cells->arg[1]; + + return gpio_request_tail(ret, NULL, &args, NULL, index, desc, flags, + index > 0, gpio_dev); +} +#endif + int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc) { /* For now, we don't do any checking of dev */ @@ -1430,7 +1452,7 @@ static int gpio_post_bind(struct udevice *dev) } #endif - if (IS_ENABLED(CONFIG_GPIO_HOG)) { + if (CONFIG_IS_ENABLED(OF_REAL) && IS_ENABLED(CONFIG_GPIO_HOG)) { dev_for_each_subnode(node, dev) { if (ofnode_read_bool(node, "gpio-hog")) { const char *name = ofnode_get_name(node); diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c index 04f8d904a2f49100a573954889ca73d9d7f53f85..e287c31b93fc11ae6e487abe377bcacd0f79f185 100644 --- a/drivers/gpio/hi6220_gpio.c +++ b/drivers/gpio/hi6220_gpio.c @@ -54,8 +54,6 @@ static int hi6220_gpio_get_value(struct udevice *dev, unsigned gpio) return !!readb(bank->base + (BIT(gpio + 2))); } - - static const struct dm_gpio_ops gpio_hi6220_ops = { .direction_input = hi6220_gpio_direction_input, .direction_output = hi6220_gpio_direction_output, @@ -91,5 +89,3 @@ U_BOOT_DRIVER(gpio_hi6220) = { .probe = hi6220_gpio_probe, .priv_auto = sizeof(struct gpio_bank), }; - - diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c index f15ce7b59eeae8e0ffdae49c3b9179dff79b4758..4a3ec6d6350230ae36a8a870cedb0a088d81a889 100644 --- a/drivers/gpio/intel_gpio.c +++ b/drivers/gpio/intel_gpio.c @@ -204,7 +204,7 @@ static const struct dm_gpio_ops gpio_intel_ops = { #endif }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id intel_intel_gpio_ids[] = { { .compatible = "intel,gpio" }, { } diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c deleted file mode 100644 index 511042c19905ac8a85152948e52c918bb47cabb3..0000000000000000000000000000000000000000 --- a/drivers/gpio/mvmfp.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, - */ - -#include <common.h> -#include <asm/io.h> -#include <mvmfp.h> -#include <asm/arch/mfp.h> - -/* - * mfp_config - * - * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin - * configuration registers to configure each GPIO/Function pin on the - * SoC. - * - * This function reads the array of values for - * MFPR_X registers and programms them into respective - * Multi-Function Pin registers. - * It supports - Alternate Function Selection programming. - * - * Whereas, - * The Configureation value is constructed using MFP() - * array consists of 32bit values as defined in MFP(xx,xx..) macro - */ -void mfp_config(u32 *mfp_cfgs) -{ - u32 *p_mfpr = NULL; - u32 cfg_val, val; - - do { - cfg_val = *mfp_cfgs++; - /* exit if End of configuration table detected */ - if (cfg_val == MFP_EOC) - break; - - p_mfpr = (u32 *)(MV_MFPR_BASE - + MFP_REG_GET_OFFSET(cfg_val)); - - /* Write a mfg register as per configuration */ - val = 0; - if (cfg_val & MFP_VALUE_MASK) - val |= cfg_val & MFP_VALUE_MASK; - - writel(val, p_mfpr); - } while (1); - /* - * perform a read-back of any MFPR register to make sure the - * previous writings are finished - */ - readl(p_mfpr); -} diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 06e6b2279f6e3ab6f87521bf9c6319a8dda23773..03471db9e80ec914dba5ab0681a214580dfdcc07 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -44,7 +44,7 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) @@ -352,7 +352,7 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 0, (struct gpio_regs *)GPIO1_BASE_ADDR }, { 1, (struct gpio_regs *)GPIO2_BASE_ADDR }, { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, @@ -376,7 +376,7 @@ U_BOOT_DRVINFOS(mxc_gpios) = { { "gpio_mxc", &mxc_plat[0] }, { "gpio_mxc", &mxc_plat[1] }, { "gpio_mxc", &mxc_plat[2] }, -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 7b9d88a8a75dc03409119c1c814ded7f9c97bbee..1356f89ac2f080e3c5a8adc94bcac4d5e3ad1d52 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -262,7 +262,7 @@ static int mxs_gpio_probe(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mxs_of_to_plat(struct udevice *dev) { struct mxs_gpio_plat *plat = dev_get_plat(dev); @@ -301,7 +301,7 @@ U_BOOT_DRIVER(fsl_imx23_gpio) = { .probe = mxs_gpio_probe, .priv_auto = sizeof(struct mxs_gpio_priv), .plat_auto = sizeof(struct mxs_gpio_plat), -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mxs_gpio_ids, .of_to_plat = mxs_of_to_plat, #endif diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 316a28efa6bb5bfef3f143d9889ddbe5b73dcc2d..50c4f75ddf5db592bebe735c0bb73e75b444e28e 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -336,7 +336,7 @@ static int omap_gpio_bind(struct udevice *dev) } #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id omap_gpio_ids[] = { { .compatible = "ti,omap3-gpio" }, { .compatible = "ti,omap4-gpio" }, @@ -362,7 +362,7 @@ U_BOOT_DRIVER(gpio_omap) = { .name = "gpio_omap", .id = UCLASS_GPIO, #if CONFIG_IS_ENABLED(OF_CONTROL) -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_gpio_ids, .of_to_plat = of_match_ptr(omap_gpio_of_to_plat), .plat_auto = sizeof(struct omap_gpio_plat), diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index d008fdd22249c2def99861f32276fec682792b5d..106b2a7b27c25edec466a0649aa372b553731166 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -323,11 +323,13 @@ static const struct dm_gpio_ops gpio_sandbox_ops = { static int sandbox_gpio_of_to_plat(struct udevice *dev) { - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - uc_priv->gpio_count = dev_read_u32_default(dev, "sandbox,gpio-count", - 0); - uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); + uc_priv->gpio_count = + dev_read_u32_default(dev, "sandbox,gpio-count", 0); + uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); + } return 0; } @@ -371,6 +373,8 @@ U_BOOT_DRIVER(sandbox_gpio) = { DM_DRIVER_ALIAS(sandbox_gpio, sandbox_gpio_alias) +#if CONFIG_IS_ENABLED(PINCTRL) + /* pincontrol: used only to check GPIO pin configuration (pinmux command) */ struct sb_pinctrl_priv { @@ -579,3 +583,5 @@ U_BOOT_DRIVER(sandbox_pinctrl_gpio) = { .priv_auto = sizeof(struct sb_pinctrl_priv), ACPI_OPS_PTR(&pinctrl_sandbox_acpi_ops) }; + +#endif /* PINCTRL */ diff --git a/drivers/gpio/sandbox_test.c b/drivers/gpio/sandbox_test.c new file mode 100644 index 0000000000000000000000000000000000000000..c76e19974196ffb5e2cc9ec23ebf46eed40c0b48 --- /dev/null +++ b/drivers/gpio/sandbox_test.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox driver for testing GPIOs with of-platdata + * + * Copyright 2021 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <asm-generic/gpio.h> + +static const struct udevice_id sandbox_gpio_test_ids[] = { + { .compatible = "sandbox,gpio-test" }, + { } +}; + +U_BOOT_DRIVER(sandbox_gpio_test) = { + .name = "sandbox_gpio_test", + .id = UCLASS_MISC, + .of_match = sandbox_gpio_test_ids, +}; diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 5d3af8a016da431fb084bb8383accc3900234228..e00f104b9f3d75df26ad79009a4373ec723c4740 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -23,8 +23,8 @@ #include <dm/device-internal.h> #include <dt-bindings/gpio/gpio.h> -static const int CONFIG_SFIO = 0; -static const int CONFIG_GPIO = 1; +static const int CFG_SFIO = 0; +static const int CFG_GPIO = 1; static const int DIRECTION_INPUT = 0; static const int DIRECTION_OUTPUT = 1; @@ -54,7 +54,7 @@ static int get_config(unsigned gpio) debug("get_config: port = %d, bit = %d is %s\n", GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - return type ? CONFIG_GPIO : CONFIG_SFIO; + return type ? CFG_GPIO : CFG_SFIO; } /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ @@ -68,7 +68,7 @@ static void set_config(unsigned gpio, int type) GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - if (type != CONFIG_SFIO) + if (type != CFG_SFIO) u |= 1 << GPIO_BIT(gpio); else u &= ~(1 << GPIO_BIT(gpio)); @@ -216,7 +216,7 @@ void gpio_config_table(const struct tegra_gpio_config *config, int len) set_direction(config[i].gpio, DIRECTION_OUTPUT); break; } - set_config(config[i].gpio, CONFIG_GPIO); + set_config(config[i].gpio, CFG_GPIO); } } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 63d03a3cebfcd969fb9cbc3c294c28d1a19808ff..57cac4483f0a59ec7adfb56aa93f3f7c74dd3495 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -47,6 +47,35 @@ config SPL_DM_I2C device (bus child) info is kept as parent platdata. The interface is defined in include/i2c.h. +config SYS_I2C_LEGACY + bool "Enable legacy I2C subsystem and drivers" + depends on !DM_I2C + help + Enable the legacy I2C subsystem and drivers. While this is + deprecated in U-Boot itself, this can be useful in some situations + in SPL or TPL. + +config SPL_SYS_I2C_LEGACY + bool "Enable legacy I2C subsystem and drivers in SPL" + depends on SUPPORT_SPL && !SPL_DM_I2C + help + Enable the legacy I2C subsystem and drivers in SPL. This is useful + in some size constrained situations. + +config TPL_SYS_I2C_LEGACY + bool "Enable legacy I2C subsystem and drivers in TPL" + depends on SUPPORT_TPL && !SPL_DM_I2C + help + Enable the legacy I2C subsystem and drivers in TPL. This is useful + in some size constrained situations. + +config SYS_I2C_EARLY_INIT + bool "Enable legacy I2C subsystem early in boot" + depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC + help + Add the function prototype for i2c_early_init_f which is called in + board_early_init_f. + config I2C_CROS_EC_TUNNEL tristate "Chrome OS EC tunnel I2C bus" depends on CROS_EC @@ -124,11 +153,36 @@ config SYS_I2C_IPROC config SYS_I2C_FSL bool "Freescale I2C bus driver" - depends on DM_I2C help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. +if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) +config SYS_FSL_I2C_OFFSET + hex "Offset from the IMMR of the address of the first I2C controller" + +config SYS_FSL_HAS_I2C2_OFFSET + bool "Support a second I2C controller" + +config SYS_FSL_I2C2_OFFSET + hex "Offset from the IMMR of the address of the second I2C controller" + depends on SYS_FSL_HAS_I2C2_OFFSET + +config SYS_FSL_HAS_I2C3_OFFSET + bool "Support a third I2C controller" + +config SYS_FSL_I2C3_OFFSET + hex "Offset from the IMMR of the address of the third I2C controller" + depends on SYS_FSL_HAS_I2C3_OFFSET + +config SYS_FSL_HAS_I2C4_OFFSET + bool "Support a fourth I2C controller" + +config SYS_FSL_I2C4_OFFSET + hex "Offset from the IMMR of the address of the fourth I2C controller" + depends on SYS_FSL_HAS_I2C4_OFFSET +endif + config SYS_I2C_CADENCE tristate "Cadence I2C Controller" depends on DM_I2C @@ -139,7 +193,6 @@ config SYS_I2C_CADENCE config SYS_I2C_CA tristate "Cortina-Access I2C Controller" depends on DM_I2C && CORTINA_PLATFORM - default n help Add support for the Cortina Access I2C host controller. Say yes here to select Cortina-Access I2C Host Controller. @@ -152,7 +205,6 @@ config SYS_I2C_DAVINCI config SYS_I2C_DW bool "Designware I2C Controller" - default n help Say yes here to select the Designware I2C Host Controller. This controller is used in various SoCs, e.g. the ST SPEAr, Altera @@ -205,10 +257,7 @@ config SYS_I2C_MXC channels and operating on standard mode up to 100 kbits/s and fast mode up to 400 kbits/s. -# These settings are not used with DM_I2C, however SPL doesn't use -# DM_I2C even if DM_I2C is enabled, and so might use these settings even -# when main u-boot does not! -if SYS_I2C_MXC && (!DM_I2C || SPL) +if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) config SYS_I2C_MXC_I2C1 bool "NXP MXC I2C1" help @@ -267,7 +316,7 @@ config SYS_MXC_I2C1_SPEED MXC I2C Channel 1 speed config SYS_MXC_I2C1_SLAVE - int "I2C1 Slave" + hex "I2C1 Slave" default 0 help MXC I2C1 Slave @@ -282,7 +331,7 @@ config SYS_MXC_I2C2_SPEED MXC I2C Channel 2 speed config SYS_MXC_I2C2_SLAVE - int "I2C2 Slave" + hex "I2C2 Slave" default 0 help MXC I2C2 Slave @@ -296,7 +345,7 @@ config SYS_MXC_I2C3_SPEED MXC I2C Channel 3 speed config SYS_MXC_I2C3_SLAVE - int "I2C3 Slave" + hex "I2C3 Slave" default 0 help MXC I2C3 Slave @@ -310,7 +359,7 @@ config SYS_MXC_I2C4_SPEED MXC I2C Channel 4 speed config SYS_MXC_I2C4_SLAVE - int "I2C4 Slave" + hex "I2C4 Slave" default 0 help MXC I2C4 Slave @@ -324,7 +373,7 @@ config SYS_MXC_I2C5_SPEED MXC I2C Channel 5 speed config SYS_MXC_I2C5_SLAVE - int "I2C5 Slave" + hex "I2C5 Slave" default 0 help MXC I2C5 Slave @@ -338,7 +387,7 @@ config SYS_MXC_I2C6_SPEED MXC I2C Channel 6 speed config SYS_MXC_I2C6_SLAVE - int "I2C6 Slave" + hex "I2C6 Slave" default 0 help MXC I2C6 Slave @@ -352,7 +401,7 @@ config SYS_MXC_I2C7_SPEED MXC I2C Channel 7 speed config SYS_MXC_I2C7_SLAVE - int "I2C7 Slave" + hex "I2C7 Slave" default 0 help MXC I2C7 Slave @@ -366,7 +415,7 @@ config SYS_MXC_I2C8_SPEED MXC I2C Channel 8 speed config SYS_MXC_I2C8_SLAVE - int "I2C8 Slave" + hex "I2C8 Slave" default 0 help MXC I2C8 Slave @@ -394,20 +443,6 @@ config SYS_I2C_OMAP24XX help Add support for the OMAP2+ I2C driver. -if SYS_I2C_OMAP24XX -config SYS_OMAP24_I2C_SLAVE - int "I2C Slave addr channel 0" - default 1 - help - OMAP24xx I2C Slave address channel 0 - -config SYS_OMAP24_I2C_SPEED - int "I2C Slave channel 0 speed" - default 100000 - help - OMAP24xx Slave speed channel 0 -endif - config SYS_I2C_RCAR_I2C bool "Renesas RCar I2C driver" depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C @@ -437,6 +472,73 @@ config SYS_I2C_SANDBOX bus. Devices can be attached to the bus using the device tree which specifies the driver to use. See sandbox.dts as an example. +config SYS_I2C_SH + bool "Legacy SuperH I2C interface" + depends on ARCH_RMOBILE && SYS_I2C_LEGACY + help + Enable the legacy SuperH I2C interface. + +if SYS_I2C_SH +config SYS_I2C_SH_NUM_CONTROLLERS + int + default 5 + +config SYS_I2C_SH_BASE0 + hex + default 0xE6820000 + +config SYS_I2C_SH_BASE1 + hex + default 0xE6822000 + +config SYS_I2C_SH_BASE2 + hex + default 0xE6824000 + +config SYS_I2C_SH_BASE3 + hex + default 0xE6826000 + +config SYS_I2C_SH_BASE4 + hex + default 0xE6828000 + +config SH_I2C_8BIT + bool + default y + +config SH_I2C_DATA_HIGH + int + default 4 + +config SH_I2C_DATA_LOW + int + default 5 + +config SH_I2C_CLOCK + int + default 104000000 +endif + +config SYS_I2C_SOFT + bool "Legacy software I2C interface" + help + Enable the legacy software defined I2C interface + +config SYS_I2C_SOFT_SPEED + int "Software I2C bus speed" + depends on SYS_I2C_SOFT + default 100000 + help + Speed of the software I2C bus + +config SYS_I2C_SOFT_SLAVE + hex "Software I2C slave address" + depends on SYS_I2C_SOFT + default 0xfe + help + Slave address of the software I2C bus + config SYS_I2C_OCTEON bool "Octeon II/III/TX/TX2 I2C driver" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C @@ -449,7 +551,7 @@ config SYS_I2C_OCTEON config SYS_I2C_S3C24X0 bool "Samsung I2C driver" - depends on ARCH_EXYNOS4 && DM_I2C + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C help Support for Samsung I2C controller as Samsung SoCs. @@ -511,7 +613,6 @@ config SYS_I2C_VERSATILE config SYS_I2C_MVTWSI bool "Marvell I2C driver" - depends on DM_I2C help Support for Marvell I2C controllers as used on the orion5x and kirkwood SoC families. @@ -526,6 +627,25 @@ config TEGRA186_BPMP_I2C by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case. +config SYS_I2C_SLAVE + hex "I2C Slave address channel (all buses)" + depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY + default 0xfe + help + I2C Slave address channel 0 for all buses in the legacy drivers. + Many boards/controllers/drivers don't support an I2C slave + interface so provide a default slave address for them for use in + common code. A real value for CONFIG_SYS_I2C_SLAVE should be + defined for any board which does support a slave interface and + this default used otherwise. + +config SYS_I2C_SPEED + int "I2C Slave channel 0 speed (all buses)" + depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY + default 100000 + help + I2C Slave speed channel 0 for all buses in the legacy drivers. + config SYS_I2C_BUS_MAX int "Max I2C busses" depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c16ebb24913c833d4e478207bf2ec4f9bad165b3..67841bf3e02bfb17babae30bf17a6bb04e60d6f0 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o obj-$(CONFIG_I2C_MV) += mv_i2c.o -obj-$(CONFIG_SYS_I2C_LEGACY) += i2c_core.o +obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e57eed0f6cddc3c81064d2fe4ae73f8d1554b1b4..d95f77649e4aad9b1b6f59e6010b5c120d795028 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -674,24 +674,6 @@ U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, dw_i2c_write, dw_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) -#if CONFIG_SYS_I2C_BUS_MAX >= 2 -U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, - dw_i2c_write, dw_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) -#endif - -#if CONFIG_SYS_I2C_BUS_MAX >= 3 -U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, - dw_i2c_write, dw_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) -#endif - -#if CONFIG_SYS_I2C_BUS_MAX >= 4 -U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, - dw_i2c_write, dw_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) -#endif - #else /* CONFIG_DM_I2C */ /* The DM I2C functions */ diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index 9b2349a0a2c7e7eeb7118c1d2255a69d87c487f0..b56d7dd22f70249db034deab4cf2c4f06a4202b5 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -112,7 +112,7 @@ struct i2c_regs { #define IC_TX_EMPTY 0x0010 #define IC_TX_OVER 0x0008 #define IC_RX_FULL 0x0004 -#define IC_RX_OVER 0x0002 +#define IC_RX_OVER 0x0002 #define IC_RX_UNDER 0x0001 /* fifo threshold register definitions */ diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 2200303ea83b82b986cef030a8df02bf40e2f9b7..eafd801cdc3af047750fb4d8d489e04d6df041b7 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -538,24 +538,24 @@ static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) */ U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) #ifdef CONFIG_SYS_FSL_I2C2_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) #endif #ifdef CONFIG_SYS_FSL_I2C3_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) #endif #ifdef CONFIG_SYS_FSL_I2C4_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) #endif #else /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c index aeec6aa9fa66bbf1419080e1364b25d4332824f1..1107cf309fcea14755986610fd40e1f07db7058d 100644 --- a/drivers/i2c/i2c-emul-uclass.c +++ b/drivers/i2c/i2c-emul-uclass.c @@ -79,7 +79,7 @@ UCLASS_DRIVER(i2c_emul) = { UCLASS_DRIVER(i2c_emul_parent) = { .id = UCLASS_I2C_EMUL_PARENT, .name = "i2c_emul_parent", -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index db1c9d94624408675d90ae3fe51bb5a7951b4aee..71bc2b5b8a6db420e2077e14fcc49434e1132efd 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -633,7 +633,7 @@ int i2c_deblock(struct udevice *bus) return ops->deblock(bus); } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip) { int addr; @@ -655,7 +655,7 @@ int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip) static int i2c_pre_probe(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); unsigned int max = 0; ofnode node; @@ -678,7 +678,7 @@ static int i2c_pre_probe(struct udevice *dev) static int i2c_post_probe(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); i2c->speed_hz = dev_read_u32_default(dev, "clock-frequency", @@ -692,7 +692,7 @@ static int i2c_post_probe(struct udevice *dev) static int i2c_child_post_bind(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct dm_i2c_chip *plat = dev_get_parent_plat(dev); if (!dev_has_ofnode(dev)) @@ -709,7 +709,7 @@ static int i2c_post_bind(struct udevice *dev) debug("%s: %s, seq=%d\n", __func__, dev->name, dev_seq(dev)); -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) ret = dm_scan_fdt_dev(dev); #endif return ret; diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 85cf75ecd9221c0f71824b914c971e0f643334a4..09f91e674d441af342818f4c185d8315d93da950 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -190,11 +190,6 @@ __weak void i2c_init_board(void) { } -/* implement possible for i2c specific early i2c init */ -__weak void i2c_early_init_f(void) -{ -} - /* * i2c_init_all(): * diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 02f0144930cca55a86a353082441fe0894497f38..ecca90628e79e0d0c23b637ff336d71c01f75ff5 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -6,19 +6,14 @@ #include <common.h> #include <i2c.h> -#if CONFIG_IS_ENABLED(DM_I2C) #include <dm.h> #include <regmap.h> -#else -#include <gdsys_fpga.h> -#endif #include <log.h> #include <asm/global_data.h> #include <asm/unaligned.h> #include <linux/bitops.h> #include <linux/delay.h> -#if CONFIG_IS_ENABLED(DM_I2C) struct ihs_i2c_priv { uint speed; struct regmap *map; @@ -39,37 +34,6 @@ struct ihs_i2c_regs { #define ihs_i2c_get(map, member, valp) \ regmap_get(map, struct ihs_i2c_regs, member, valp) -#else /* !CONFIG_DM_I2C */ -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SYS_I2C_IHS_DUAL - -#define I2C_SET_REG(fld, val) \ - do { \ - if (I2C_ADAP_HWNR & 0x10) \ - FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ - else \ - FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ - } while (0) -#else -#define I2C_SET_REG(fld, val) \ - FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val) -#endif - -#ifdef CONFIG_SYS_I2C_IHS_DUAL -#define I2C_GET_REG(fld, val) \ - do { \ - if (I2C_ADAP_HWNR & 0x10) \ - FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ - else \ - FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ - } while (0) -#else -#define I2C_GET_REG(fld, val) \ - FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) -#endif -#endif /* CONFIG_DM_I2C */ - enum { I2CINT_ERROR_EV = BIT(13), I2CINT_TRANSMIT_EV = BIT(14), @@ -91,23 +55,13 @@ enum { I2COP_READ = 1, }; -#if CONFIG_IS_ENABLED(DM_I2C) static int wait_for_int(struct udevice *dev, int read) -#else -static int wait_for_int(bool read) -#endif { u16 val; uint ctr = 0; -#if CONFIG_IS_ENABLED(DM_I2C) struct ihs_i2c_priv *priv = dev_get_priv(dev); -#endif -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_get(priv->map, interrupt_status, &val); -#else - I2C_GET_REG(interrupt_status, &val); -#endif /* Wait until error or receive/transmit interrupt was raised */ while (!(val & (I2CINT_ERROR_EV | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { @@ -116,40 +70,24 @@ static int wait_for_int(bool read) debug("%s: timed out\n", __func__); return -ETIMEDOUT; } -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_get(priv->map, interrupt_status, &val); -#else - I2C_GET_REG(interrupt_status, &val); -#endif } return (val & I2CINT_ERROR_EV) ? -EIO : 0; } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_transfer(struct udevice *dev, uchar chip, uchar *buffer, int len, int read, bool is_last) -#else -static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, - bool is_last) -#endif { u16 val; u16 data; int res; -#if CONFIG_IS_ENABLED(DM_I2C) struct ihs_i2c_priv *priv = dev_get_priv(dev); -#endif /* Clear interrupt status */ data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_set(priv->map, interrupt_status, data); ihs_i2c_get(priv->map, interrupt_status, &val); -#else - I2C_SET_REG(interrupt_status, data); - I2C_GET_REG(interrupt_status, &val); -#endif /* If we want to write and have data, write the bytes to the mailbox */ if (!read && len) { @@ -157,11 +95,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, if (len > 1) val |= buffer[1] << 8; -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_set(priv->map, write_mailbox_ext, val); -#else - I2C_SET_REG(write_mailbox_ext, val); -#endif } data = I2CMB_NATIVE @@ -170,17 +104,9 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, | ((len > 1) ? I2CMB_2BYTE : 0) | (is_last ? 0 : I2CMB_HOLD_BUS); -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_set(priv->map, write_mailbox, data); -#else - I2C_SET_REG(write_mailbox, data); -#endif -#if CONFIG_IS_ENABLED(DM_I2C) res = wait_for_int(dev, read); -#else - res = wait_for_int(read); -#endif if (res) { if (res == -ETIMEDOUT) debug("%s: time out while waiting for event\n", __func__); @@ -190,11 +116,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, /* If we want to read, get the bytes from the mailbox */ if (read) { -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_get(priv->map, read_mailbox_ext, &val); -#else - I2C_GET_REG(read_mailbox_ext, &val); -#endif buffer[0] = val & 0xff; if (len > 1) buffer[1] = val >> 8; @@ -203,12 +125,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, return 0; } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read) -#else -static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, - int read) -#endif { int res; @@ -216,13 +133,8 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, int transfer = min(len, 2); bool is_last = len <= transfer; -#if CONFIG_IS_ENABLED(DM_I2C) res = ihs_i2c_transfer(dev, chip, data, transfer, read, hold_bus ? false : is_last); -#else - res = ihs_i2c_transfer(chip, data, transfer, read, - hold_bus ? false : is_last); -#endif if (res) return res; @@ -233,27 +145,14 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, return 0; } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen, bool hold_bus) -#else -static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) -#endif { -#if CONFIG_IS_ENABLED(DM_I2C) return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE); -#else - return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE); -#endif } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr, int alen, uchar *buffer, int len, int read) -#else -static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, - int alen, uchar *buffer, int len, int read) -#endif { int res; @@ -261,23 +160,13 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, if (len <= 0) return -EINVAL; -#if CONFIG_IS_ENABLED(DM_I2C) res = ihs_i2c_address(dev, chip, addr, alen, len); -#else - res = ihs_i2c_address(chip, addr, alen, len); -#endif if (res) return res; -#if CONFIG_IS_ENABLED(DM_I2C) return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); -#else - return ihs_i2c_send_buffer(chip, buffer, len, false, read); -#endif } -#if CONFIG_IS_ENABLED(DM_I2C) - int ihs_i2c_probe(struct udevice *bus) { struct ihs_i2c_priv *priv = dev_get_priv(bus); @@ -358,120 +247,3 @@ U_BOOT_DRIVER(i2c_ihs) = { .priv_auto = sizeof(struct ihs_i2c_priv), .ops = &ihs_i2c_ops, }; - -#else /* CONFIG_DM_I2C */ - -static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* - * Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif -} - -static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) -{ - uchar buffer[2]; - int res; - - res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true); - if (res) - return res; - - return 0; -} - -static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - u8 addr_bytes[4]; - - put_unaligned_le32(addr, addr_bytes); - - return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, - I2COP_READ); -} - -static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - u8 addr_bytes[4]; - - put_unaligned_le32(addr, addr_bytes); - - return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, - I2COP_WRITE); -} - -static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - if (speed != adap->speed) - return -EINVAL; - return speed; -} - -/* - * Register IHS i2c adapters - */ -#ifdef CONFIG_SYS_I2C_IHS_CH0 -U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_0, - CONFIG_SYS_I2C_IHS_SLAVE_0, 0) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_0_1, - CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16) -#endif -#endif -#ifdef CONFIG_SYS_I2C_IHS_CH1 -U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_1, - CONFIG_SYS_I2C_IHS_SLAVE_1, 1) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_1_1, - CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17) -#endif -#endif -#ifdef CONFIG_SYS_I2C_IHS_CH2 -U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_2, - CONFIG_SYS_I2C_IHS_SLAVE_2, 2) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_2_1, - CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18) -#endif -#endif -#ifdef CONFIG_SYS_I2C_IHS_CH3 -U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_3, - CONFIG_SYS_I2C_IHS_SLAVE_3, 3) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_3_1, - CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) -#endif -#endif -#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 20c5de0007a872a0ba620b4737f92f188d9fdb38..0eff3531618cdf48c6fee61be32828789fc97db9 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -80,7 +80,7 @@ static void i2c_reset(struct mv_i2c *base) i2c_clk_enable(); - writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ + writel(0x0, &base->isar); /* set our slave address */ /* set control reg values */ writel(I2C_ICR_INIT | icr_mode, &base->icr); writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index d33e2c7c9d836086bf64e159c77392cf34576b22..236bfb8d8e7f55222a6e6bef9a2f7ff5afb55858 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -17,7 +17,9 @@ #include <linux/bitops.h> #include <linux/compat.h> #if CONFIG_IS_ENABLED(DM_I2C) +#include <clk.h> #include <dm.h> +#include <reset.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -835,7 +837,18 @@ static int mvtwsi_i2c_bind(struct udevice *bus) static int mvtwsi_i2c_probe(struct udevice *bus) { struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + struct reset_ctl reset; + struct clk clk; uint actual_speed; + int ret; + + ret = reset_get_by_index(bus, 0, &reset); + if (!ret) + reset_deassert(&reset); + + ret = clk_get_by_index(bus, 0, &clk); + if (!ret) + clk_enable(&clk); __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); dev->speed = actual_speed; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 003aa33f6ecdbb508fb1c140369e47baf15c2741..aa13af3ae109bfdcd8830402b11b39450b68e693 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -110,32 +110,6 @@ static u16 i2c_clk_div[50][2] = { }; #endif -#ifndef CONFIG_SYS_MXC_I2C1_SPEED -#define CONFIG_SYS_MXC_I2C1_SPEED 100000 -#endif -#ifndef CONFIG_SYS_MXC_I2C2_SPEED -#define CONFIG_SYS_MXC_I2C2_SPEED 100000 -#endif -#ifndef CONFIG_SYS_MXC_I2C3_SPEED -#define CONFIG_SYS_MXC_I2C3_SPEED 100000 -#endif -#ifndef CONFIG_SYS_MXC_I2C4_SPEED -#define CONFIG_SYS_MXC_I2C4_SPEED 100000 -#endif - -#ifndef CONFIG_SYS_MXC_I2C1_SLAVE -#define CONFIG_SYS_MXC_I2C1_SLAVE 0 -#endif -#ifndef CONFIG_SYS_MXC_I2C2_SLAVE -#define CONFIG_SYS_MXC_I2C2_SLAVE 0 -#endif -#ifndef CONFIG_SYS_MXC_I2C3_SLAVE -#define CONFIG_SYS_MXC_I2C3_SLAVE 0 -#endif -#ifndef CONFIG_SYS_MXC_I2C4_SLAVE -#define CONFIG_SYS_MXC_I2C4_SLAVE 0 -#endif - /* * Calculate and set proper clock divider */ @@ -798,8 +772,6 @@ void bus_i2c_init(int index, int speed, int unused, bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); } - - /* * Init I2C Bus */ diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 71f6f5f7ac8ad60512ef5d1e0921e02fdfb0c0dc..a767dee9866c8258114ee8df0377bccacec4e2df 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -936,62 +936,34 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip); } -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) -#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) -#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, - CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 0) U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, - CONFIG_SYS_OMAP24_I2C_SPEED1, - CONFIG_SYS_OMAP24_I2C_SLAVE1, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 1) #if (CONFIG_SYS_I2C_BUS_MAX > 2) -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) -#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) -#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, NULL, - CONFIG_SYS_OMAP24_I2C_SPEED2, - CONFIG_SYS_OMAP24_I2C_SLAVE2, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 2) #if (CONFIG_SYS_I2C_BUS_MAX > 3) -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) -#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) -#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, NULL, - CONFIG_SYS_OMAP24_I2C_SPEED3, - CONFIG_SYS_OMAP24_I2C_SLAVE3, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 3) #if (CONFIG_SYS_I2C_BUS_MAX > 4) -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) -#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) -#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, NULL, - CONFIG_SYS_OMAP24_I2C_SPEED4, - CONFIG_SYS_OMAP24_I2C_SLAVE4, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 4) #endif #endif @@ -1062,7 +1034,7 @@ static int omap_i2c_probe(struct udevice *bus) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int omap_i2c_of_to_plat(struct udevice *bus) { struct omap_i2c_plat *plat = dev_get_plat(bus); @@ -1091,7 +1063,7 @@ static const struct dm_i2c_ops omap_i2c_ops = { U_BOOT_DRIVER(i2c_omap) = { .name = "i2c_omap", .id = UCLASS_I2C, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_i2c_ids, .of_to_plat = omap_i2c_of_to_plat, .plat_auto = sizeof(struct omap_i2c_plat), diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index 14bb6603d59ec927b92298030dffaeef0dba4157..d9ece5e3a8006af5222a7db0ff65a3400e20d44a 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -64,6 +64,8 @@ enum rcar_i2c_type { struct rcar_i2c_priv { void __iomem *base; struct clk clk; + u32 fall_ns; + u32 rise_ns; u32 intdelay; u32 icccr; enum rcar_i2c_type type; @@ -278,7 +280,7 @@ static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz) * = F[sum * ick / 1000000000] * = F[(ick / 1000000) * sum / 1000] */ - sum = 35 + 200 + priv->intdelay; + sum = priv->fall_ns + priv->rise_ns + priv->intdelay; round = (ick + 500000) / 1000000 * sum; round = (round + 500) / 1000; @@ -323,6 +325,10 @@ static int rcar_i2c_probe(struct udevice *dev) int ret; priv->base = dev_read_addr_ptr(dev); + priv->rise_ns = dev_read_u32_default(dev, + "i2c-scl-rising-time-ns", 200); + priv->fall_ns = dev_read_u32_default(dev, + "i2c-scl-falling-time-ns", 35); priv->intdelay = dev_read_u32_default(dev, "i2c-scl-internal-delay-ns", 5); priv->type = dev_get_driver_data(dev); diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 56f0f69885e4ac785d30f1e63ccfff776f4e3bb5..e0f499d759f8638c379fc46ab7845bca9e94961a 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -21,12 +21,6 @@ #include <i2c.h> #include "s3c24x0_i2c.h" -#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE -#define SYS_I2C_S3C24X0_SLAVE_ADDR 0 -#else -#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE -#endif - DECLARE_GLOBAL_DATA_PTR; /* @@ -83,6 +77,8 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } +#define SYS_I2C_S3C24X0_SLAVE_ADDR 0 + static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) { struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 26a87006698ecf0a0e968e2a07bc993e0dd97cd5..6cecec41450ec51dbf3e8741a5597ec1e0b71592 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -294,20 +294,20 @@ static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, * Register RCAR i2c adapters */ U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0) #ifdef CONFIG_SYS_I2C_SH_BASE1 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1) #endif #ifdef CONFIG_SYS_I2C_SH_BASE2 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2) #endif #ifdef CONFIG_SYS_I2C_SH_BASE3 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3) #endif #ifdef CONFIG_SYS_I2C_SH_BASE4 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4) #endif diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index db69c18cb6deb16844813dc6ebf0de6c1733b2a4..c72839eb0111678fe02c99be7ceadcb270410e88 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -438,80 +438,3 @@ U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe, soft_i2c_read, soft_i2c_write, NULL, CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE, 0) -#if defined(I2C_SOFT_DECLARATIONS2) -U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_2, - CONFIG_SYS_I2C_SOFT_SLAVE_2, - 1) -#endif -#if defined(I2C_SOFT_DECLARATIONS3) -U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_3, - CONFIG_SYS_I2C_SOFT_SLAVE_3, - 2) -#endif -#if defined(I2C_SOFT_DECLARATIONS4) -U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_4, - CONFIG_SYS_I2C_SOFT_SLAVE_4, - 3) -#endif -#if defined(I2C_SOFT_DECLARATIONS5) -U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_5, - CONFIG_SYS_I2C_SOFT_SLAVE_5, - 4) -#endif -#if defined(I2C_SOFT_DECLARATIONS6) -U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_6, - CONFIG_SYS_I2C_SOFT_SLAVE_6, - 5) -#endif -#if defined(I2C_SOFT_DECLARATIONS7) -U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_7, - CONFIG_SYS_I2C_SOFT_SLAVE_7, - 6) -#endif -#if defined(I2C_SOFT_DECLARATIONS8) -U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_8, - CONFIG_SYS_I2C_SOFT_SLAVE_8, - 7) -#endif -#if defined(I2C_SOFT_DECLARATIONS9) -U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_9, - CONFIG_SYS_I2C_SOFT_SLAVE_9, - 8) -#endif -#if defined(I2C_SOFT_DECLARATIONS10) -U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_10, - CONFIG_SYS_I2C_SOFT_SLAVE_10, - 9) -#endif -#if defined(I2C_SOFT_DECLARATIONS11) -U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_11, - CONFIG_SYS_I2C_SOFT_SLAVE_11, - 10) -#endif -#if defined(I2C_SOFT_DECLARATIONS12) -U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_12, - CONFIG_SYS_I2C_SOFT_SLAVE_12, - 11) -#endif diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 565d99e7e57f9c805c9e0b8fa0369c553721f4e0..d3743dc37f72fcbeec421118ba200b2917b4a785 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -150,8 +150,8 @@ static int kbd_reset(int quirk) else if ((quirk & QUIRK_DUP_POR) && config == KBD_POR) config = kbd_cmd_read(CMD_RD_CONFIG); - config |= CONFIG_AT_TRANS; - config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN); + config |= CFG_AT_TRANS; + config &= ~(CFG_KIRQ_EN | CFG_MIRQ_EN); if (kbd_cmd_write(CMD_WR_CONFIG, config)) goto err; diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 6250e274e12f10dd9232f40a2c174f1689116252..c4bc88c15108bec1acc18dd454036d2e15dca22a 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -9,11 +9,10 @@ #include <common.h> #include <asm/ti-common/ti-aemif.h> -#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4) -#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60) -#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c) -#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ - + (cs * 4)) +#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4) +#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60) +#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c) +#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4)) #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 997b7132211025ad5561058fdd9e0627169c82da..099ff2934897eef7e7cfe64e684572e619b0b56d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -398,36 +398,12 @@ config SPL_I2C_EEPROM This option is an SPL-variant of the I2C_EEPROM option. See the help of I2C_EEPROM for details. -if I2C_EEPROM - config SYS_I2C_EEPROM_ADDR hex "Chip address of the EEPROM device" + depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM default 0 -config SYS_I2C_EEPROM_BUS - int "I2C bus of the EEPROM device." - default 0 - -config SYS_EEPROM_SIZE - int "Size in bytes of the EEPROM device" - default 256 - -config SYS_EEPROM_PAGE_WRITE_BITS - int "Number of bits used to address bytes in a single page" - default 0 - help - The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. - A 64 byte page, for example would require six bits. - -config SYS_EEPROM_PAGE_WRITE_DELAY_MS - int "Number of milliseconds to delay between page writes" - default 0 - -config SYS_I2C_EEPROM_ADDR_LEN - int "Length in bytes of the EEPROM memory array address" - default 1 - help - Note: This is NOT the chip address length! +if I2C_EEPROM config SYS_I2C_EEPROM_ADDR_OVERFLOW hex "EEPROM Address Overflow" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b64cd2a4de9100e56d764b6b2ce058d178f06310..c16a77c34c40343ecea14dcdfd380a08c12e0911 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -42,7 +42,7 @@ obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_IRQ) += irq-uclass.o -obj-$(CONFIG_SANDBOX) += irq_sandbox.o +obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index af65c559dc6963fa4b57d77c8a71437aeba6a1c6..715dabb27992f957c4c268d31f236a4e4a871b12 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -2,8 +2,8 @@ * I2C Driver for Atmel ATSHA204 over I2C * * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com - * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com - * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com + * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as @@ -40,11 +40,11 @@ DECLARE_GLOBAL_DATA_PTR; * * int i, j; * for (i = 0; i < 256; ++i) { - * u8 c = 0; - * for (j = 0; j < 8; ++j) { - * c = (c << 1) | ((i >> j) & 1); - * } - * bitreverse_table[i] = c; + * u8 c = 0; + * for (j = 0; j < 8; ++j) { + * c = (c << 1) | ((i >> j) & 1); + * } + * bitreverse_table[i] = c; * } */ @@ -88,14 +88,14 @@ static u8 const bitreverse_table[256] = { * * int i, j; * for (i = 0; i < 256; ++i) { - * u16 c = i << 8; - * for (j = 0; j < 8; ++j) { - * int b = c >> 15; - * c <<= 1; - * if (b) - * c ^= 0x8005; - * } - * crc16_table[i] = c; + * u16 c = i << 8; + * for (j = 0; j < 8; ++j) { + * int b = c >> 15; + * c <<= 1; + * if (b) + * c ^= 0x8005; + * } + * crc16_table[i] = c; * } */ static u16 const crc16_table[256] = { @@ -339,7 +339,7 @@ int atsha204a_read(struct udevice *dev, enum atsha204a_zone zone, bool read32, retry--; atsha204a_wakeup(dev); } while (retry >= 0); - + if (res) { debug("ATSHA204A read failed\n"); return res; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 2a15094d20a6c1ef4d54c64bff67a980219a7d61..c627c1df6c22a7475eb66434da1ed822f34f8f41 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -414,7 +414,7 @@ static int ec_command(struct udevice *dev, uint cmd, int cmd_version, int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan) { - if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan, + if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan, sizeof(scan->data)) != sizeof(scan->data)) return -1; @@ -1671,7 +1671,7 @@ UCLASS_DRIVER(cros_ec) = { .id = UCLASS_CROS_EC, .name = "cros-ec", .per_device_auto = sizeof(struct cros_ec_dev), -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif .flags = DM_UC_FLAG_ALLOC_PRIV_DMA, diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c index abd20b4d61f5e4813752214b2ef4419d13381cae..cfe03b40cd0199566ec1e10a4fa93cc0243d865b 100644 --- a/drivers/misc/fsl_devdis.c +++ b/drivers/misc/fsl_devdis.c @@ -25,4 +25,3 @@ void device_disable(const struct devdis_table *tbl, uint32_t num) tbl[i].mask); } } - diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 3aa26f61d9e60b2feed41227bab77073ef083345..eb9f3b902f4cc5571a35e02e64ba6fcc759f470c 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -64,8 +64,8 @@ int irq_read_and_clear(struct irq *irq) } #if CONFIG_IS_ENABLED(OF_PLATDATA) -int irq_get_by_driver_info(struct udevice *dev, - struct phandle_1_arg *cells, struct irq *irq) +int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells, + struct irq *irq) { int ret; @@ -74,6 +74,12 @@ int irq_get_by_driver_info(struct udevice *dev, return ret; irq->id = cells->arg[0]; + /* + * Note: we could call irq_of_xlate_default() here to do this properly. + * For now, this is good enough for existing cases. + */ + irq->flags = cells->arg[1]; + return 0; } #else diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c index 1f7e62e66142e837bfc9dee9557737ea0e2c51a2..8b5573fcaddda24ea0d7c93b8a370f7d875c5bad 100644 --- a/drivers/misc/irq_sandbox.c +++ b/drivers/misc/irq_sandbox.c @@ -9,19 +9,9 @@ #include <dm.h> #include <irq.h> #include <acpi/acpi_device.h> +#include <asm/irq.h> #include <asm/test.h> -/** - * struct sandbox_irq_priv - private data for this driver - * - * @count: Counts the number calls to the read_and_clear() method - * @pending: true if an interrupt is pending, else false - */ -struct sandbox_irq_priv { - int count; - bool pending; -}; - static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low) { if (irq > 10) @@ -103,10 +93,11 @@ static const struct udevice_id sandbox_irq_ids[] = { { } }; -U_BOOT_DRIVER(sandbox_irq_drv) = { +U_BOOT_DRIVER(sandbox_irq) = { .name = "sandbox_irq", .id = UCLASS_IRQ, .of_match = sandbox_irq_ids, .ops = &sandbox_irq_ops, .priv_auto = sizeof(struct sandbox_irq_priv), + DM_HEADER(<asm/irq.h>) }; diff --git a/drivers/misc/irq_sandbox_test.c b/drivers/misc/irq_sandbox_test.c new file mode 100644 index 0000000000000000000000000000000000000000..95c45c24edb82adb294fe48c62ac12b0d5286187 --- /dev/null +++ b/drivers/misc/irq_sandbox_test.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox driver for testing interrupts with of-platdata + * + * Copyright 2021 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <irq.h> +#include <asm/irq.h> + +static const struct udevice_id sandbox_irq_test_ids[] = { + { .compatible = "sandbox,irq-test" }, + { } +}; + +U_BOOT_DRIVER(sandbox_irq_test) = { + .name = "sandbox_irq_test", + .id = UCLASS_MISC, + .of_match = sandbox_irq_test_ids, +}; diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 72720b0e590cdd50dfffb6c06b74c696be058269..cbfacc3801a39c5ecfc810666fece37f46f8a765 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -70,7 +70,7 @@ int misc_set_enabled(struct udevice *dev, bool val) UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index 94d273de9b3f3d19fbe8decfc845263fd0eb670d..f24857a1515e27201ab9a642498864a43d84e701 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -183,16 +183,16 @@ int p2sb_set_port_id(struct udevice *dev, int portid) static int p2sb_child_post_bind(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); - int ret; - u32 pid; - - ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); - if (ret) - return ret; - pplat->pid = pid; -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; + } return 0; } diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 1569e8c44aca892469d41cb3865bb719d0feebf4..e0927ce1c9bd6625e42b809af124d67c09bf011f 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -123,7 +123,6 @@ config MMC_IO_VOLTAGE config SPL_MMC_IO_VOLTAGE bool "Support IO voltage configuration in SPL" - default n help IO voltage configuration allows selecting the voltage level of the IO lines (not the level of main supply). This is required for UHS @@ -193,7 +192,6 @@ config MMC_VERBOSE config MMC_TRACE bool "MMC debugging" - default n help This is an option for use by developer. Enable MMC core debugging. @@ -221,7 +219,6 @@ config MMC_DW_CORTINA depends on DM_MMC depends on MMC_DW depends on BLK - default n help This selects support for Cortina SoC specific extensions to the Synopsys DesignWare Memory Card Interface driver. Select this option @@ -770,7 +767,6 @@ config FTSDC010 config FTSDC010_SDIO bool "Support ftsdc010 sdio" - default n depends on FTSDC010 help This can enable ftsdc010 sdio function. @@ -805,7 +801,6 @@ config FSL_ESDHC_SUPPORT_ADMA2 config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND bool "enable eSDHC workaround for 3.3v IO reliability issue" depends on FSL_ESDHC && DM_MMC - default n help When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index dde6cd563ff5f007354d5fb6c501d4a373d4659c..7e819d2b3a25c0e80ee14339dca2c5d4e23c6f11 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -65,7 +65,7 @@ obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o -obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o +obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index aabf39535f9ff4d18ed9bc9ed269d6e1c1f477c8..5dfd484ef9a4a82fa1adbb490ee5454058ab5ea7 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1411,7 +1411,6 @@ __weak void init_clk_usdhc(u32 index) static int fsl_esdhc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct fsl_esdhc_priv *priv = dev_get_priv(dev); #if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *vqmmc_dev; @@ -1419,10 +1418,12 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) #endif const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); - fdt_addr_t addr; unsigned int val; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; @@ -1494,7 +1495,7 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) priv->vs18_enable = 1; } #endif -#endif + return 0; } @@ -1598,11 +1599,11 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = mmc_of_parse(dev, &plat->cfg); - if (ret) - return ret; -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; + } mmc = &plat->mmc; mmc->cfg = &plat->cfg; diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 0fa037224fbe80e7be8ee6f6fdbc6f4f75799aea..570d54cf9d8fa68b5fc04ea6cda7ab145f4e1433 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -30,8 +30,6 @@ #include <syscon.h> #include <linux/err.h> -DECLARE_GLOBAL_DATA_PTR; - #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ @@ -392,34 +390,29 @@ static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswid static int ftsdc010_mmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ftsdc_priv *priv = dev_get_priv(dev); struct ftsdc010_chip *chip = &priv->chip; - chip->name = dev->name; - chip->ioaddr = dev_read_addr_ptr(dev); - chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bus-width", 4); - chip->priv = dev; - priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "fifo-depth", 0); - priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "fifo-mode"); - if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "clock-freq-min-max", priv->minmax, 2)) { - int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", -EINVAL); - if (val < 0) - return val; - - priv->minmax[0] = 400000; /* 400 kHz */ - priv->minmax[1] = val; - } else { - debug("%s: 'clock-freq-min-max' property was deprecated.\n", - __func__); + + if (CONFIG_IS_ENABLED(OF_REAL)) { + chip->name = dev->name; + chip->ioaddr = dev_read_addr_ptr(dev); + chip->buswidth = dev_read_u32_default(dev, "bus-width", 4); + chip->priv = dev; + priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); + priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); + if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { + if (dev_read_u32(dev, "max-frequency", &priv->minmax[1])) + return -EINVAL; + + priv->minmax[0] = 400000; /* 400 kHz */ + } else { + debug("%s: 'clock-freq-min-max' property was deprecated.\n", + __func__); + } } -#endif chip->sclk = priv->minmax[1]; chip->regs = chip->ioaddr; + return 0; } @@ -440,7 +433,7 @@ static int ftsdc010_mmc_probe(struct udevice *dev) chip->priv = dev; chip->dev_index = 1; memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #endif diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d3babbfeb1cb46151b6d0de2e9e30d8510910f3d..ba54b19c140b1a145c4b25bc789596f9206aba55 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -699,7 +699,7 @@ static int mmc_send_op_cond(struct mmc *mmc) mmc_go_idle(mmc); start = get_timer(0); - /* Asking to the card its capabilities */ + /* Asking to the card its capabilities */ for (i = 0; ; i++) { err = mmc_send_op_cond_iter(mmc, i != 0); if (err) diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 591137f50e39b0274237629874384bf2d0429449..336ebf141026e45c0e0eb85690a9e0d8891de41c 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -44,29 +44,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base) #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS static struct sdhci_ops mv_ops; - -#if defined(CONFIG_SHEEVA_88SV331xV5) -#define SD_CE_ATA_2 0xEA -#define MMC_CARD 0x1000 -#define MMC_WIDTH 0x0100 -static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) -{ - struct mmc *mmc = host->mmc; - u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2; - - if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) { - if (mmc->bus_width == 8) - writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata); - else - writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata); - } - - writeb(val, host->ioaddr + reg); -} - -#else -#define mv_sdhci_writeb NULL -#endif /* CONFIG_SHEEVA_88SV331xV5 */ #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) @@ -84,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) host->max_clk = max_clk; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS memset(&mv_ops, 0, sizeof(struct sdhci_ops)); - mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 8fd41764152fa291e6908057a097e008f139aa6a..35a8e21058edaf607e6dd54fa43bd2a1d4789c88 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -665,7 +665,7 @@ static const struct dm_mmc_ops mxsmmc_ops = { .set_ios = mxsmmc_set_ios, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mxsmmc_of_to_plat(struct udevice *bus) { struct mxsmmc_plat *plat = dev_get_plat(bus); @@ -709,7 +709,7 @@ static const struct udevice_id mxsmmc_ids[] = { U_BOOT_DRIVER(fsl_imx23_mmc) = { .name = "fsl_imx23_mmc", .id = UCLASS_MMC, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mxsmmc_ids, .of_to_plat = mxsmmc_of_to_plat, #endif diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 306ce0fe1e2b2db10c67981fddc3110bb5b75ed0..820065800fe32c7e59888fe6e1b4b1bbb516d73a 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -42,7 +42,7 @@ #include <asm/arch/mux_dra7xx.h> #include <asm/arch/dra7xx_iodelay.h> #endif -#if !defined(CONFIG_SOC_KEYSTONE) +#if !defined(CONFIG_ARCH_KEYSTONE) #include <asm/gpio.h> #include <asm/arch/sys_proto.h> #endif @@ -1559,7 +1559,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ + defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \ defined(CONFIG_HSMMC2_8BIT) /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ host_caps_val |= MMC_MODE_8BIT; @@ -1891,7 +1891,7 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) } #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) #ifdef CONFIG_OMAP54XX __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) { @@ -2009,7 +2009,7 @@ static int omap_hsmmc_probe(struct udevice *dev) return omap_hsmmc_init_setup(mmc); } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct omap_mmc_of_data dra7_mmc_of_data = { .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, @@ -2027,7 +2027,7 @@ static const struct udevice_id omap_hsmmc_ids[] = { U_BOOT_DRIVER(omap_hsmmc) = { .name = "omap_hsmmc", .id = UCLASS_MMC, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_hsmmc_ids, .of_to_plat = omap_hsmmc_of_to_plat, .plat_auto = sizeof(struct omap_hsmmc_plat), diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index d7d5361fd50b29c535f83185a40e475f053e7352..7f8dea1e343d70b6ff0a77babc695d482a4e8622 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,10 +52,12 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) static int rockchip_dwmmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + host->name = dev->name; host->ioaddr = dev_read_addr_ptr(dev); host->buswidth = dev_read_u32_default(dev, "bus-width", 4); @@ -95,7 +97,7 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev) debug("%s: 'clock-freq-min-max' property was deprecated.\n", __func__); } -#endif + return 0; } @@ -121,7 +123,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #else diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 582129d0df162a7498629ddd1000044ebf33161b..9496903e861908b9aa437458640008835276e9f2 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -4,7 +4,7 @@ * drivers and users. * * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> - * Copyright © 2006 Red Hat UK Limited + * Copyright © 2006 Red Hat UK Limited * */ @@ -123,7 +123,7 @@ void *idr_get_next(struct idr *idp, int *next) } else { *next = 0; } - + return ret; } @@ -799,8 +799,8 @@ static bool mtd_device_matches_name(struct mtd_info *mtd, const char *name) * device name * @name: MTD device name to open * - * This function returns MTD device description structure in case of - * success and an error code in case of failure. + * This function returns MTD device description structure in case of + * success and an error code in case of failure. */ struct mtd_info *get_mtd_device_nm(const char *name) { diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index a901ce55111767e8b8427dc69e9be37f47c4e054..bb8cffcabcefd28c9dc5efd7297d7451edf76a90 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -31,12 +31,10 @@ if NAND_ATMEL config ATMEL_NAND_HWECC bool "Atmel Hardware ECC" - default n config ATMEL_NAND_HW_PMECC bool "Atmel Programmable Multibit ECC (PMECC)" select ATMEL_NAND_HWECC - default n help The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. @@ -59,7 +57,6 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER bool "Atmel PMECC Header Generation" select ATMEL_NAND_HWECC select ATMEL_NAND_HW_PMECC - default n help Generate Programmable Multibit ECC (PMECC) header for SPL image. @@ -108,6 +105,10 @@ config NAND_DAVINCI Enable this driver for NAND flash controllers available in TI Davinci and Keystone2 platforms +config KEYSTONE_RBL_NAND + depends on ARCH_KEYSTONE + def_bool y + config NAND_DENALI bool select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 9ad3a57690e5be6b063fd6069d390550b74232da..e4860561f8eb1c115b150a76800621b45e15e4ab 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -39,7 +39,7 @@ #define NAND_TIMEOUT 10240 #define NAND_ECC_BUSY 0xC #define NAND_4BITECC_MASK 0x03FF03FF -#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 +#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 #define ECC_STATE_NO_ERR 0x0 #define ECC_STATE_TOO_MANY_ERRS 0x1 #define ECC_STATE_ERR_CORR_COMP_P 0x2 @@ -347,9 +347,9 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = { }; #ifdef CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 +#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11) #elif defined(CONFIG_SYS_NAND_PAGE_4K) -#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 +#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12) #endif /** @@ -371,7 +371,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, struct nand_ecclayout *saved_ecc_layout; /* save current ECC layout and assign Keystone RBL ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { saved_ecc_layout = chip->ecc.layout; chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; mtd->oobavail = chip->ecc.layout->oobavail; @@ -402,7 +402,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, err: /* restore ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = saved_ecc_layout; mtd->oobavail = saved_ecc_layout->oobavail; } @@ -433,7 +433,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip * struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; /* save current ECC layout and assign Keystone RBL ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; mtd->oobavail = chip->ecc.layout->oobavail; } @@ -463,7 +463,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip * } /* restore ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = saved_ecc_layout; mtd->oobavail = saved_ecc_layout->oobavail; } diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 0c1bd7b4740ac9a8246212a64d4be5312c2a237c..ddfd75d32d069766edf23760a520af896c7fd147 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -716,7 +716,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->bbt_td = &bbt_main_descr; nand->bbt_md = &bbt_mirror_descr; - /* set up nand options */ + /* set up nand options */ nand->options = NAND_NO_SUBPAGE_WRITE; nand->bbt_options = NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 59cef205754b58726aa5f4d1467cb4445953d335..c38f286e61d5457c1fc7f372e8b4feff365b0dce 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -11,7 +11,7 @@ #include <linux/delay.h> #include <linux/err.h> #include <asm/io.h> -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \ +#if defined(CONFIG_MX27) || \ defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif diff --git a/drivers/mtd/nand/raw/mxc_nand.h b/drivers/mtd/nand/raw/mxc_nand.h index 1c7f3a2e227d808628a16e90db02b167efa1bb18..771f61e24919c06dc39bba8d8bf113c3ac6dc198 100644 --- a/drivers/mtd/nand/raw/mxc_nand.h +++ b/drivers/mtd/nand/raw/mxc_nand.h @@ -29,11 +29,6 @@ #define is_mxc_nfc_1() 1 #define is_mxc_nfc_21() 0 #define is_mxc_nfc_32() 0 -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) -#define MXC_NFC_V2_1 -#define is_mxc_nfc_1() 0 -#define is_mxc_nfc_21() 1 -#define is_mxc_nfc_32() 0 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53) #define MXC_NFC_V3 #define MXC_NFC_V3_2 diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 17f46ae5e919c1f20c90394efffc96d100b86ce6..d16224a2e088a0728415071cad9a38d2595266dc 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -295,4 +295,3 @@ int nand_default_bbt(struct mtd_info *mtd) void nand_deselect(void) { } - diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index b1fd779884fe0e8ac4c8ab0219384927c9b645bb..b533683dfe6562c69fc6784ade5740060b482b7c 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -263,7 +263,7 @@ static void ioread8_rep(void *addr, uint8_t *buf, int len) static void ioread16_rep(void *addr, void *buf, int len) { int i; - u16 *p = (u16 *) buf; + u16 *p = (u16 *) buf; for (i = 0; i < len; i++) p[i] = readw(addr); @@ -905,11 +905,11 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ret) return ret; - u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; - u32 time_start; - - time_start = get_timer(0); - while (get_timer(time_start) < timer) { + u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; + u32 time_start; + + time_start = get_timer(0); + while (get_timer(time_start) < timer) { if (chip->dev_ready) { if (chip->dev_ready(mtd)) break; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 3104f879f666f6414ab3c0cca0727e9107f494e7..2a50f0b2144ce75856d970cc1da3ecf54721c2ef 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -30,7 +30,7 @@ struct nand_flash_dev nand_flash_ids[] = { LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS), #endif diff --git a/drivers/mtd/nand/raw/nand_util.c b/drivers/mtd/nand/raw/nand_util.c index 00c3c6c412260476dea75cd151491f02083f976d..d03b8645c4463c075e1922fa4f328658ae500b79 100644 --- a/drivers/mtd/nand/raw/nand_util.c +++ b/drivers/mtd/nand/raw/nand_util.c @@ -189,7 +189,7 @@ int nand_erase_opts(struct mtd_info *mtd, #define NAND_CMD_LOCK_TIGHT 0x2c #define NAND_CMD_LOCK_STATUS 0x7a - + /****************************************************************************** * Support for locking / unlocking operations of some NAND devices *****************************************************************************/ @@ -545,8 +545,6 @@ int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf) return rval ? -EIO : 0; } - - /** * nand_write_skip_bad: * diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index e33953ec7c64b5f747d8af394288abef162e9150..13fd631cb402f89021bcfeda78693becb8ab6210 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -109,19 +109,19 @@ #define STATUS_BYTE1_MASK 0x000000FF /* NFC_FLASH_CONFIG Field */ -#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 -#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 -#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) -#define CONFIG_DMA_REQ_BIT (1<<20) -#define CONFIG_ECC_MODE_MASK 0x000E0000 -#define CONFIG_ECC_MODE_SHIFT 17 -#define CONFIG_FAST_FLASH_BIT (1<<16) -#define CONFIG_16BIT (1<<7) -#define CONFIG_BOOT_MODE_BIT (1<<6) -#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) -#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) -#define CONFIG_PAGE_CNT_MASK 0xF -#define CONFIG_PAGE_CNT_SHIFT 0 +#define CFG_ECC_SRAM_ADDR_MASK 0x7FC00000 +#define CFG_ECC_SRAM_ADDR_SHIFT 22 +#define CFG_ECC_SRAM_REQ_BIT (1<<21) +#define CFG_DMA_REQ_BIT (1<<20) +#define CFG_ECC_MODE_MASK 0x000E0000 +#define CFG_ECC_MODE_SHIFT 17 +#define CFG_FAST_FLASH_BIT (1<<16) +#define CFG_16BIT (1<<7) +#define CFG_BOOT_MODE_BIT (1<<6) +#define CFG_ADDR_AUTO_INCR_BIT (1<<5) +#define CFG_BUFNO_AUTO_INCR_BIT (1<<4) +#define CFG_PAGE_CNT_MASK 0xF +#define CFG_PAGE_CNT_SHIFT 0 /* NFC_IRQ_STATUS Field */ #define IDLE_IRQ_BIT (1<<29) @@ -342,8 +342,8 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode) { vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, - CONFIG_ECC_MODE_MASK, - CONFIG_ECC_MODE_SHIFT, ecc_mode); + CFG_ECC_MODE_MASK, + CFG_ECC_MODE_SHIFT, ecc_mode); } static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) @@ -666,16 +666,16 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) chip->ecc.size = PAGE_2K; /* Set configuration register. */ - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); - vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_16BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_ADDR_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BUFNO_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BOOT_MODE_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_DMA_REQ_BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_FAST_FLASH_BIT); /* Disable virtual pages, only one elementary transfer unit */ - vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, - CONFIG_PAGE_CNT_SHIFT, 1); + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CFG_PAGE_CNT_MASK, + CFG_PAGE_CNT_SHIFT, 1); /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { @@ -684,7 +684,7 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) } if (cfg.width == 16) - vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_16BIT); /* Bad block options. */ if (cfg.flash_bbt) @@ -734,12 +734,12 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) /* Set ECC_STATUS offset */ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, - CONFIG_ECC_SRAM_ADDR_MASK, - CONFIG_ECC_SRAM_ADDR_SHIFT, + CFG_ECC_SRAM_ADDR_MASK, + CFG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR >> 3); /* Enable ECC status in SRAM */ - vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_ECC_SRAM_REQ_BIT); } /* second phase scan */ diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 09daa0dd36ec18c7207c423beabe66ecafee0a4e..46aeef258d9877f5bb9d048eb3972c87d2c9b75c 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -2306,8 +2306,8 @@ static int flexonenand_get_boundary(struct mtd_info *mtd) /** * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info - * boundary[], diesize[], mtd->size, mtd->erasesize, - * mtd->eraseregions + * boundary[], diesize[], mtd->size, mtd->erasesize, + * mtd->eraseregions * @param mtd - MTD device structure */ static void flexonenand_get_size(struct mtd_info *mtd) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index f03fe05e333d3771ffeac369c7afac03e6951b50..408a53f86178cf98837dcf204c85e460227a1b53 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -99,7 +99,6 @@ config SPI_FLASH_SMART_HWCAPS config SPI_FLASH_SOFT_RESET bool "Software Reset support for SPI NOR flashes" - default n help Enable support for xSPI Software Reset. It will be used to switch from Octal DTR mode to legacy mode on shutdown and boot (if enabled). @@ -107,7 +106,6 @@ config SPI_FLASH_SOFT_RESET config SPI_FLASH_SOFT_RESET_ON_BOOT bool "Perform a Software Reset on boot on flashes that boot in stateful mode" depends on SPI_FLASH_SOFT_RESET - default n help Perform a Software Reset on boot to allow detecting flashes that are handed to us in Octal DTR mode. Do not enable this config on flashes diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4aef1ddd6e23a19f2e3e70f4990a27a5a42bd122..0bff52d5f2a4b4b85cbfd99ec16f55edc4895105 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -76,7 +76,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, - { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, + { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ /* EON -- en25xxx */ diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index a78fd51ba7dcf21c14e6b00cb56b5a131766ba94..67a3cf1d7a50ca003d109e4a9309b7e304c994a3 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -68,7 +68,6 @@ config MTD_UBI_BEB_LIMIT config MTD_UBI_FASTMAP bool "UBI Fastmap (Experimental feature)" - default n help Important: this feature is experimental so far and the on-flash format for fastmap may change in the next kernel versions diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 61e38ba1ab777f9a7caf606f844152eda7039ed1..e2bd32697eaa073c86cc75953ac42deee63af70a 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -115,7 +115,7 @@ static struct ubi_device *ubi_devices[UBI_MAX_DEVICES]; #else struct ubi_device *ubi_devices[UBI_MAX_DEVICES]; #endif - + #ifndef __UBOOT__ /* Serializes UBI devices creations and removals */ DEFINE_MUTEX(ubi_devices_mutex); diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c index 9ce061c861308d90f9ae5566c680ed7c25ea4532..35820c753e1fd75df6bbe3b24eaaa9b9569c6e37 100644 --- a/drivers/mtd/ubi/crc32.c +++ b/drivers/mtd/ubi/crc32.c @@ -293,8 +293,8 @@ EXPORT_SYMBOL(crc32_be); * * A big-endian CRC written this way would be coded like: * for (i = 0; i < input_bits; i++) { - * multiple = remainder & 0x80000000 ? CRCPOLY : 0; - * remainder = (remainder << 1 | next_input_bit()) ^ multiple; + * multiple = remainder & 0x80000000 ? CRCPOLY : 0; + * remainder = (remainder << 1 | next_input_bit()) ^ multiple; * } * Notice how, to get at bit 32 of the shifted remainder, we look * at bit 31 of the remainder *before* shifting it. @@ -313,14 +313,14 @@ EXPORT_SYMBOL(crc32_be); * This changes the code to: * for (i = 0; i < input_bits; i++) { * remainder ^= next_input_bit() << 31; - * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; - * remainder = (remainder << 1) ^ multiple; + * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; + * remainder = (remainder << 1) ^ multiple; * } * With this optimization, the little-endian code is simpler: * for (i = 0; i < input_bits; i++) { * remainder ^= next_input_bit(); - * multiple = (remainder & 1) ? CRCPOLY : 0; - * remainder = (remainder >> 1) ^ multiple; + * multiple = (remainder & 1) ? CRCPOLY : 0; + * remainder = (remainder >> 1) ^ multiple; * } * * Note that the other details of endianness have been hidden in CRCPOLY @@ -330,19 +330,19 @@ EXPORT_SYMBOL(crc32_be); * order, we can actually do the merging 8 or more bits at a time rather * than one bit at a time: * for (i = 0; i < input_bytes; i++) { - * remainder ^= next_input_byte() << 24; - * for (j = 0; j < 8; j++) { - * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; - * remainder = (remainder << 1) ^ multiple; - * } + * remainder ^= next_input_byte() << 24; + * for (j = 0; j < 8; j++) { + * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; + * remainder = (remainder << 1) ^ multiple; + * } * } * Or in little-endian: * for (i = 0; i < input_bytes; i++) { - * remainder ^= next_input_byte(); - * for (j = 0; j < 8; j++) { - * multiple = (remainder & 1) ? CRCPOLY : 0; - * remainder = (remainder << 1) ^ multiple; - * } + * remainder ^= next_input_byte(); + * for (j = 0; j < 8; j++) { + * multiple = (remainder & 1) ? CRCPOLY : 0; + * remainder = (remainder << 1) ^ multiple; + * } * } * If the input is a multiple of 32 bits, you can even XOR in a 32-bit * word at a time and increase the inner loop count to 32. diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index d4dc72046c4e084e17ced7a6f8a63db5242aef38..6c12959f3794060708e8f15bdedebaa3a15326bc 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2,6 +2,9 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" source "drivers/net/fsl-mc/Kconfig" +config ETH + def_bool y + config DM_ETH bool "Enable Driver Model for Ethernet drivers" depends on DM @@ -557,7 +560,6 @@ endif #DM_ETH config SMC911X_32_BIT bool "Enable SMC911X 32-bit interface" - default n help Define this if data bus is 32 bits. If your processor use a narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit @@ -711,7 +713,6 @@ config FEC1_PHY config PHY_NORXERR bool "PHY_NORXERR" depends on ETHER_ON_FEC1 - default n help The PHY does not have a RXERR line (RMII only). (so program the FEC to ignore it). @@ -736,7 +737,6 @@ config FEC2_PHY config FEC2_PHY_NORXERR bool "PHY_NORXERR" depends on ETHER_ON_FEC2 - default n help The PHY does not have a RXERR line (RMII only). (so program the FEC to ignore it). diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b94ccea1003bab77b2ef621a2d12cce9b5d99a2f..e4078d15a99f868e4a3dd7aebcf40a4594f748ad 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -3,13 +3,14 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +obj-y += phy/ + obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o obj-$(CONFIG_BCMGENET) += bcmgenet.o -obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o @@ -33,6 +34,7 @@ obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o obj-$(CONFIG_EP93XX) += ep93xx_eth.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_FEC_MXC) += fec_mxc.o +obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index 018891e173c37e1d6ba2e16df11004ce36810185..5d4b90c6ba72ad5f7375d7448053dd539bd64f03 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -717,7 +717,7 @@ int armada100_fec_register(unsigned long base_addr) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = smi_reg_read; mdiodev->write = smi_reg_write; diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c deleted file mode 100644 index e40b94ad892d191f2ffa61bfe57b620b5e49fd4c..0000000000000000000000000000000000000000 --- a/drivers/net/at91_emac.c +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG - * Jens Scharsig (esw@bus-elektronik.de) - * - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_emac.h> -#include <asm/arch/clk.h> -#include <asm/arch/at91_pio.h> -#include <net.h> -#include <netdev.h> -#include <malloc.h> -#include <miiphy.h> -#include <linux/delay.h> -#include <linux/mii.h> - -#undef MII_DEBUG -#undef ET_DEBUG - -#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) -#error AT91 EMAC supports max 1024 RX buffers. \ - Please decrease the CONFIG_SYS_RX_ETH_BUFFER value -#endif - -#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR -#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 -#endif - -/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ -#if (AT91C_MASTER_CLOCK > 80000000) - #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 -#elif (AT91C_MASTER_CLOCK > 40000000) - #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 -#elif (AT91C_MASTER_CLOCK > 20000000) - #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 -#else - #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 -#endif - -#ifdef ET_DEBUG -#define DEBUG_AT91EMAC 1 -#else -#define DEBUG_AT91EMAC 0 -#endif - -#ifdef MII_DEBUG -#define DEBUG_AT91PHY 1 -#else -#define DEBUG_AT91PHY 0 -#endif - -#ifndef CONFIG_DRIVER_AT91EMAC_QUIET -#define VERBOSEP 1 -#else -#define VERBOSEP 0 -#endif - -#define RBF_ADDR 0xfffffffc -#define RBF_OWNER (1<<0) -#define RBF_WRAP (1<<1) -#define RBF_BROADCAST (1<<31) -#define RBF_MULTICAST (1<<30) -#define RBF_UNICAST (1<<29) -#define RBF_EXTERNAL (1<<28) -#define RBF_UNKNOWN (1<<27) -#define RBF_SIZE 0x07ff -#define RBF_LOCAL4 (1<<26) -#define RBF_LOCAL3 (1<<25) -#define RBF_LOCAL2 (1<<24) -#define RBF_LOCAL1 (1<<23) - -#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER -#define RBF_FRAMELEN 0x600 - -typedef struct { - unsigned long addr, size; -} rbf_t; - -typedef struct { - rbf_t rbfdt[RBF_FRAMEMAX]; - unsigned long rbindex; -} emac_device; - -void at91emac_EnableMDIO(at91_emac_t *at91mac) -{ - /* Mac CTRL reg set for MDIO enable */ - writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); -} - -void at91emac_DisableMDIO(at91_emac_t *at91mac) -{ - /* Mac CTRL reg set for MDIO disable */ - writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); -} - -int at91emac_read(at91_emac_t *at91mac, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - unsigned long netstat; - at91emac_EnableMDIO(at91mac); - - writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | - AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | - AT91_EMAC_MAN_PHYA(addr), - &at91mac->man); - - do { - netstat = readl(&at91mac->sr); - debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); - } while (!(netstat & AT91_EMAC_SR_IDLE)); - - *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; - - at91emac_DisableMDIO(at91mac); - - debug_cond(DEBUG_AT91PHY, - "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value); - - return 0; -} - -int at91emac_write(at91_emac_t *at91mac, unsigned char addr, - unsigned char reg, unsigned short value) -{ - unsigned long netstat; - debug_cond(DEBUG_AT91PHY, - "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value); - - at91emac_EnableMDIO(at91mac); - - writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | - AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | - AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), - &at91mac->man); - - do { - netstat = readl(&at91mac->sr); - debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); - } while (!(netstat & AT91_EMAC_SR_IDLE)); - - at91emac_DisableMDIO(at91mac); - - return 0; -} - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - -at91_emac_t *get_emacbase_by_name(const char *devname) -{ - struct eth_device *netdev; - - netdev = eth_get_dev_by_name(devname); - return (at91_emac_t *) netdev->iobase; -} - -int at91emac_mii_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - unsigned short value = 0; - at91_emac_t *emac; - - emac = get_emacbase_by_name(bus->name); - at91emac_read(emac , addr, reg, &value); - return value; -} - - -int at91emac_mii_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value) -{ - at91_emac_t *emac; - - emac = get_emacbase_by_name(bus->name); - at91emac_write(emac, addr, reg, value); - return 0; -} - -#endif - -static int at91emac_phy_reset(struct eth_device *netdev) -{ - int i; - u16 status, adv; - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_ADVERTISE, adv); - debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name); - at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, - (BMCR_ANENABLE | BMCR_ANRESTART)); - - for (i = 0; i < 30000; i++) { - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_BMSR, &status); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } - - if (status & BMSR_ANEGCOMPLETE) { - debug_cond(VERBOSEP, - "%s: Autonegotiation complete\n", netdev->name); - } else { - printf("%s: Autonegotiation timed out (status=0x%04x)\n", - netdev->name, status); - return -1; - } - return 0; -} - -static int at91emac_phy_init(struct eth_device *netdev) -{ - u16 phy_id, status, adv, lpa; - int media, speed, duplex; - int i; - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - - /* Check if the PHY is up to snuff... */ - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_PHYSID1, &phy_id); - if (phy_id == 0xffff) { - printf("%s: No PHY present\n", netdev->name); - return -1; - } - - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_BMSR, &status); - - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - if (at91emac_phy_reset(netdev)) - return -2; - - for (i = 0; i < 100000 / 100; i++) { - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_BMSR, &status); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - if (!(status & BMSR_LSTATUS)) { - debug_cond(VERBOSEP, "%s: link down\n", netdev->name); - return -3; - } else { - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_ADVERTISE, &adv); - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_LPA, &lpa); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n", - netdev->name, - speed ? "100" : "10", - duplex ? "full" : "half"); - } - return 0; -} - -int at91emac_UpdateLinkSpeed(at91_emac_t *emac) -{ - unsigned short stat1; - - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); - - if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ - return -1; - - if (stat1 & BMSR_100FULL) { - /*set Emac for 100BaseTX and Full Duplex */ - writel(readl(&emac->cfg) | - AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, - &emac->cfg); - return 0; - } - - if (stat1 & BMSR_10FULL) { - /*set MII for 10BaseT and Full Duplex */ - writel((readl(&emac->cfg) & - ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) - ) | AT91_EMAC_CFG_FD, - &emac->cfg); - return 0; - } - - if (stat1 & BMSR_100HALF) { - /*set MII for 100BaseTX and Half Duplex */ - writel((readl(&emac->cfg) & - ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) - ) | AT91_EMAC_CFG_SPD, - &emac->cfg); - return 0; - } - - if (stat1 & BMSR_10HALF) { - /*set MII for 10BaseT and Half Duplex */ - writel((readl(&emac->cfg) & - ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), - &emac->cfg); - return 0; - } - return 0; -} - -static int at91emac_init(struct eth_device *netdev, struct bd_info *bd) -{ - int i; - u32 value; - emac_device *dev; - at91_emac_t *emac; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - emac = (at91_emac_t *) netdev->iobase; - dev = (emac_device *) netdev->priv; - - /* PIO Disable Register */ - value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC | - ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 | - ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS | - ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 | - ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; - - writel(value, &pio->pioa.pdr); - writel(value, &pio->pioa.mux.pio2.asr); - -#ifdef CONFIG_RMII - value = ATMEL_PMX_BA_ERXCK; -#else - value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL | - ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 | - ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER | - ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; -#endif - writel(value, &pio->piob.pdr); - writel(value, &pio->piob.mux.pio2.bsr); - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); - - /* Init Ethernet buffers */ - for (i = 0; i < RBF_FRAMEMAX; i++) { - dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i]; - dev->rbfdt[i].size = 0; - } - dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; - dev->rbindex = 0; - writel((u32) &(dev->rbfdt[0]), &emac->rbqp); - - writel(readl(&emac->rsr) & - ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), - &emac->rsr); - - value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | - HCLK_DIV; -#ifdef CONFIG_RMII - value |= AT91_EMAC_CFG_RMII; -#endif - writel(value, &emac->cfg); - - writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, - &emac->ctl); - - if (!at91emac_phy_init(netdev)) { - at91emac_UpdateLinkSpeed(emac); - return 0; - } - return -1; -} - -static void at91emac_halt(struct eth_device *netdev) -{ - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), - &emac->ctl); - debug_cond(DEBUG_AT91EMAC, "halt MAC\n"); -} - -static int at91emac_send(struct eth_device *netdev, void *packet, int length) -{ - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - - while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) - ; - writel((u32) packet, &emac->tar); - writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); - while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) - ; - debug_cond(DEBUG_AT91EMAC, "Send %d\n", length); - writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); - return 0; -} - -static int at91emac_recv(struct eth_device *netdev) -{ - emac_device *dev; - at91_emac_t *emac; - rbf_t *rbfp; - int size; - - emac = (at91_emac_t *) netdev->iobase; - dev = (emac_device *) netdev->priv; - - rbfp = &dev->rbfdt[dev->rbindex]; - while (rbfp->addr & RBF_OWNER) { - size = rbfp->size & RBF_SIZE; - net_process_received_packet(net_rx_packets[dev->rbindex], size); - - debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n", - dev->rbindex, size, rbfp->addr); - - rbfp->addr &= ~RBF_OWNER; - rbfp->size = 0; - if (dev->rbindex < (RBF_FRAMEMAX-1)) - dev->rbindex++; - else - dev->rbindex = 0; - - rbfp = &(dev->rbfdt[dev->rbindex]); - if (!(rbfp->addr & RBF_OWNER)) - writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, - &emac->rsr); - } - - if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { - /* EMAC silicon bug 41.3.1 workaround 1 */ - writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); - writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); - dev->rbindex = 0; - printf("%s: reset receiver (EMAC dead lock bug)\n", - netdev->name); - } - return 0; -} - -static int at91emac_write_hwaddr(struct eth_device *netdev) -{ - at91_emac_t *emac; - emac = (at91_emac_t *) netdev->iobase; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - debug_cond(DEBUG_AT91EMAC, - "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", - netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], - netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]); - writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 | - netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24), - &emac->sa2l); - writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h); - debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n", - readl(&emac->sa2h), readl(&emac->sa2l)); - return 0; -} - -int at91emac_register(struct bd_info *bis, unsigned long iobase) -{ - emac_device *emac; - emac_device *emacfix; - struct eth_device *dev; - - if (iobase == 0) - iobase = ATMEL_BASE_EMAC; - emac = malloc(sizeof(*emac)+512); - if (emac == NULL) - return -1; - dev = malloc(sizeof(*dev)); - if (dev == NULL) { - free(emac); - return -1; - } - /* alignment as per Errata (64 bytes) is insufficient! */ - emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); - memset(emacfix, 0, sizeof(emac_device)); - - memset(dev, 0, sizeof(*dev)); - strcpy(dev->name, "emac"); - dev->iobase = iobase; - dev->priv = emacfix; - dev->init = at91emac_init; - dev->halt = at91emac_halt; - dev->send = at91emac_send; - dev->recv = at91emac_recv; - dev->write_hwaddr = at91emac_write_hwaddr; - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = at91emac_mii_read; - mdiodev->write = at91emac_mii_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - return 1; -} diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index c862c141461c9e91452aa13b001c7f1cd6bdfb81..88dc3ab384668af05b1e0592a858465cbbfe2ea5 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -250,7 +250,7 @@ int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num) if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = eth->miiphy_read; mdiodev->write = eth->miiphy_write; diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index b98d709117aaa1acddc28094e4a7d1f2bd0b61b9..eb1e2a756cd3c5ce273b153682090e723a7352b3 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -587,7 +587,7 @@ static const struct eth_ops xgmac_eth_ops = { .start = xgmac_eth_start, .send = xgmac_tx, .recv = xgmac_rx, - .free_pkt = xgmac_free_pkt, + .free_pkt = xgmac_free_pkt, .stop = xgmac_eth_stop, .write_hwaddr = xgmac_eth_write_hwaddr, .read_rom_hwaddr = xgmac_eth_read_rom_hwaddr, diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index e46a269af909f841049a37331476186df30e2508..4f062e99d9bd8b16bf0bc3c250129ca1869c781e 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -28,7 +28,7 @@ v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: -------------------------------------- 12/15/2003 Initial port to u-boot by - Sascha Hauer <saschahauer@web.de> + Sascha Hauer <saschahauer@web.de> 06/03/2008 Remy Bohmer <linux@bohmer.net> - Fixed the driver to work with DM9000A. @@ -66,7 +66,7 @@ TODO: external MII is not functional, only internal at the moment. #define DM9000_DBG(fmt,args...) printf(fmt, ##args) #define DM9000_DMP_PACKET(func,packet,length) \ do { \ - int i; \ + int i; \ printf("%s: length: %d\n", func, length); \ for (i = 0; i < length; i++) { \ if (i % 8 == 0) \ diff --git a/drivers/net/dsa_sandbox.c b/drivers/net/dsa_sandbox.c index 4b62670e5d17afe54d62571b3b535be99556d725..235f2f22d9aa93ac8bdea0dd71837cf74eb42ebf 100644 --- a/drivers/net/dsa_sandbox.c +++ b/drivers/net/dsa_sandbox.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ #include <asm/eth.h> diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 5bdcede8f1449ae6192e6abf3f3283ab45991a6b..4e34248ff6f0cbaed8733e7a43e62580b3bf0483 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5251,11 +5251,7 @@ e1000_configure_tx(struct e1000_hw *hw) mdelay(20); } - - E1000_WRITE_REG(hw, TCTL, tctl); - - } /** diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 082154a997e60ca70300feea8c04450413f3d19c..f96f12c8f445a0eeea6f22ab8515b56392c9fb81 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -249,7 +249,7 @@ struct e1000_phy_stats { #define E1000_ERR_MASTER_REQUESTS_PENDING 10 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 #define E1000_BLK_PHY_RESET 12 -#define E1000_ERR_SWFW_SYNC 13 +#define E1000_ERR_SWFW_SYNC 13 /* PCI Device IDs */ #define E1000_DEV_ID_82542 0x1000 diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 934b881219e947e6008746187084d1ad7b7374df..935cd9c99cef7f9327ad9e18d2b0fafacae56975 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -493,7 +493,7 @@ static int eepro100_initialize_mii(struct eepro100_priv *priv) if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, priv->name, MDIO_NAME_LEN); mdiodev->read = eepro100_miiphy_read; mdiodev->write = eepro100_miiphy_write; mdiodev->priv = priv; diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c index 0218349b04500adda12aecbd6aeb3ee2176192a3..9f8df7de060970e0bdba5d87f6a0688b197b37f0 100644 --- a/drivers/net/ep93xx_eth.c +++ b/drivers/net/ep93xx_eth.c @@ -427,7 +427,7 @@ int ep93xx_miiphy_initialize(struct bd_info * const bd) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN); + strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN); mdiodev->read = ep93xx_miiphy_read; mdiodev->write = ep93xx_miiphy_write; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 9bb42e5ca9078c7ccb8396545891fbd0864d1040..40a86a3e12fa55cfa106ba052bfdbdd3380e1c5e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -521,7 +521,7 @@ static int fec_open(struct eth_device *edev) &fec->eth->ecntrl); #endif -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) udelay(100); /* setup the MII gasket for RMII mode */ diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 62b55ef3959a99862ed347a99c97b867883b5842..1c0d0e5b8f89be1587d27ca3c29d0c26c50fdb66 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -128,7 +128,7 @@ struct ethernet_regs { uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ @@ -196,7 +196,7 @@ struct ethernet_regs { #define FEC_X_DES_ACTIVE_TDAR 0x01000000 #define FEC_R_DES_ACTIVE_RDAR 0x01000000 -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) /* defines for MIIGSK */ /* RMII frequency control: 0=50MHz, 1=5MHz */ #define MIIGSK_CFGR_FRCONT (1 << 6) diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 5be0ad2ab3db3d93914434a41d3151e07ada43f4..6e3d008199a5c6f9c6a7d9bc7ab7136c25cef6bd 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -100,7 +100,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) env_get_f("hwconfig", buffer, sizeof(buffer)); buf = buffer; - /* check if XFI interface enable in hwconfig for 10g */ + /* check if 10GBase-R interface enable in hwconfig for 10g */ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", "sfp_amc", "sfp", buf)) { if ((port == FM1_10GEC1 || diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 7c23ccc1f0e6e3405d3ab3db8cca90bb2012d880..5e0d0bca9b53b4a684537a79941660890c9791b1 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -50,7 +50,7 @@ static void dtsec_configure_serdes(struct fm_eth *priv) u32 value; struct mii_dev bus; bool sgmii_2500 = (priv->enet_if == - PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + PHY_INTERFACE_MODE_2500BASEX) ? true : false; int i = 0, j; #ifndef CONFIG_DM_ETH @@ -133,7 +133,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || - fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) + fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) dtsec_configure_serdes(fm_eth); } @@ -432,7 +432,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth) /* For some reason we need to set SPEED_100 */ if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || - (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) || + (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) || (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && mac->set_if_mode) mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); @@ -829,7 +829,7 @@ static int init_phy(struct fm_eth *fm_eth) if (fm_eth->type == FM_ETH_10G_E) supported = PHY_10G_FEATURES; - if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) + if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) supported |= SUPPORTED_2500baseX_Full; #endif @@ -1090,7 +1090,7 @@ static int fm_eth_probe(struct udevice *dev) if (fm_eth->num != 0) break; case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: fm_eth->pcs_mdio = fm_get_internal_mdio(dev); break; default: diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index ba4da69423aa29db85123a9c0319dc816f6e759e..e1abf8f6bb71ad7075400ff1b4326073836bfb49 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -79,7 +79,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) case FM1_DTSEC2: if ((port == FM1_DTSEC2) && is_serdes_configured(SGMII_2500_FM1_DTSEC2)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC9: @@ -87,7 +87,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) return PHY_INTERFACE_MODE_SGMII; else if ((port == FM1_DTSEC9) && is_serdes_configured(SGMII_2500_FM1_DTSEC9)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; break; default: break; diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 49b540bd30b08ebbb35bdbbb0ccf9b538a12f02c..09df0aa53766517fba46d1bdd6c4d577389a0b1a 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -99,7 +99,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) case FM1_DTSEC10: if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + port - FM1_DTSEC5)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; break; default: break; diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 36f50d27826e596e58cde63a86195380c78e0376..eeb67a39a77f1aa8af8920d57b632984c80d84ab 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -93,12 +93,12 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= (IF_MODE_GMII | IF_MODE_RM); break; case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_QSGMII: if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_XGMII: if_mode &= ~IF_MODE_MASK; if_mode |= IF_MODE_XGMII; @@ -107,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, break; } /* Enable automatic speed selection for Non-XGMII */ - if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI) + if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER) if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII || diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 6fc3b9033701f870f4453330e7d87097cbc2bccc..696e74c9e6fef1951cc30ac4f374ba238dea9574 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -63,7 +63,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) return PHY_INTERFACE_MODE_SGMII; else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 + port - FM1_DTSEC1)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; break; default: break; diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index 443e430695ec579589b37ecdde275f72a9b03716..5290be20c85e4b630939f0cc4190613df6de71c8 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -525,4 +525,3 @@ int dpni_reset_statistics(struct fsl_mc_io *mc_io, /* send command to mc*/ return mc_send_command(mc_io, &cmd); } - diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 566cdc7e546a6728ca64d14c42a39ecaa80f7401..915c7c80256fd7e1b5e424a5fa97f609ee863126 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -144,7 +144,7 @@ static int enetc_init_sgmii(struct udevice *dev) if (!enetc_has_imdio(dev)) return 0; - if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500) + if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX) is2500 = true; /* @@ -226,9 +226,8 @@ static void enetc_setup_mac_iface(struct udevice *dev, case PHY_INTERFACE_MODE_RGMII_TXID: enetc_init_rgmii(dev, phydev); break; - case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); if_mode &= ~ENETC_PM_IF_IFMODE_MASK; @@ -270,7 +269,7 @@ static void enetc_start_pcs(struct udevice *dev) priv->imdio.read = enetc_mdio_read; priv->imdio.write = enetc_mdio_write; priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; - strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); + strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); if (!miiphy_get_dev_by_name(priv->imdio.name)) mdio_register(&priv->imdio); } @@ -291,12 +290,11 @@ static void enetc_start_pcs(struct udevice *dev) switch (priv->if_type) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: enetc_init_sgmii(dev); break; - case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: enetc_init_sxgmii(dev); break; }; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index c20aef4ab28dd20bcca07cebcd42de551dd7f9d1..e103f79305e788e2effc5fe29e7bc2eb77e262b1 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -541,7 +541,7 @@ static int mcdmafec_probe(struct udevice *dev) info->bus = mdio_alloc(); if (!info->bus) return -ENOMEM; - strncpy(info->bus->name, dev->name, MDIO_NAME_LEN); + strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN); info->bus->read = mcffec_miiphy_read; info->bus->write = mcffec_miiphy_write; diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 265d813c4f89c2eb37165d8fb48d616181bdd56d..7e54d4642ddfdda54b32ce2846800370ad45f99f 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -476,7 +476,7 @@ int ftmac110_initialize(struct bd_info *bis) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = ftmac110_mdio_read; mdiodev->write = ftmac110_mdio_write; diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index 3f281a515c6a18ef3bdba1da2ad0810c9e6b34d0..1a5734343935451178c5f248282ce14acfc04471 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -638,7 +638,7 @@ int lpc32xx_eth_initialize(struct bd_info *bis) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = mii_reg_read; mdiodev->write = mii_reg_write; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 57ea45e2dc7fc253d53b51f3f69403b53452bf19..8151104acfc09adafe13c98e142722b97a063976 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1245,7 +1245,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); mdiodev->read = macb_miiphy_read; mdiodev->write = macb_miiphy_write; @@ -1403,7 +1403,7 @@ static int macb_eth_probe(struct udevice *dev) macb->bus = mdio_alloc(); if (!macb->bus) return -ENOMEM; - strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); + strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN); macb->bus->read = macb_miiphy_read; macb->bus->write = macb_miiphy_write; diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index 282c2599d3c48ab47b3595ab545c70c49a47a2d8..4eb826028111c47d2038246e26d649165e111182 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -160,7 +160,7 @@ int fec_initialize(struct bd_info *bis) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = fec8xx_miiphy_read; mdiodev->write = fec8xx_miiphy_write; diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index f20e84e0f10cf62598c3daba9115538e1c7e3efd..551fc2c9f9692c8f4571bb61e33015340a62b46b 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * Felix (VSC9959) Ethernet switch driver - * Copyright 2018-2021 NXP Semiconductors + * Copyright 2018-2021 NXP */ /* @@ -213,17 +213,16 @@ static void felix_start_pcs(struct udevice *dev, int port, bool autoneg = true; if (phy->phy_id == PHY_FIXED_ID || - phy->interface == PHY_INTERFACE_MODE_SGMII_2500) + phy->interface == PHY_INTERFACE_MODE_2500BASEX) autoneg = false; switch (phy->interface) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_QSGMII: felix_init_sgmii(imdio, port, autoneg); break; - case PHY_INTERFACE_MODE_XGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_USXGMII: if (felix_init_sxgmii(imdio, port)) dev_err(dev, "PCS reset timeout on port %d\n", port); @@ -233,7 +232,7 @@ static void felix_start_pcs(struct udevice *dev, int port, } } -void felix_init(struct udevice *dev) +static void felix_init(struct udevice *dev) { struct dsa_pdata *pdata = dev_get_uclass_plat(dev); struct felix_priv *priv = dev_get_priv(dev); @@ -258,7 +257,7 @@ void felix_init(struct udevice *dev) priv->imdio.read = felix_mdio_read; priv->imdio.write = felix_mdio_write; priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE; - strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); + strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); /* set up CPU port */ out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG, @@ -276,6 +275,7 @@ void felix_init(struct udevice *dev) static int felix_probe(struct udevice *dev) { struct felix_priv *priv = dev_get_priv(dev); + int err; if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) { @@ -300,11 +300,18 @@ static int felix_probe(struct udevice *dev) struct mii_dev *mii_bus; mii_bus = mdio_alloc(); + if (!mii_bus) + return -ENOMEM; + mii_bus->read = felix_mdio_read; mii_bus->write = felix_mdio_write; mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE; - strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN); - mdio_register(mii_bus); + strlcpy(mii_bus->name, dev->name, MDIO_NAME_LEN); + err = mdio_register(mii_bus); + if (err) { + mdio_free(mii_bus); + return err; + } } dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); @@ -317,10 +324,23 @@ static int felix_probe(struct udevice *dev) return 0; } +static int felix_port_probe(struct udevice *dev, int port, + struct phy_device *phy) +{ + int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; + struct felix_priv *priv = dev_get_priv(dev); + + phy->supported &= supported; + phy->advertising &= supported; + + felix_start_pcs(dev, port, phy, &priv->imdio); + + return phy_config(phy); +} + static int felix_port_enable(struct udevice *dev, int port, struct phy_device *phy) { - int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; struct felix_priv *priv = dev_get_priv(dev); void *base = priv->regs_base; @@ -339,15 +359,7 @@ static int felix_port_enable(struct udevice *dev, int port, FELIX_QSYS_SYSTEM_SW_PORT_LOSSY | FELIX_QSYS_SYSTEM_SW_PORT_SCH(1)); - felix_start_pcs(dev, port, phy, &priv->imdio); - - phy->supported &= supported; - phy->advertising &= supported; - phy_config(phy); - - phy_startup(phy); - - return 0; + return phy_startup(phy); } static void felix_port_disable(struct udevice *dev, int pidx, @@ -392,6 +404,7 @@ static int felix_rcv(struct udevice *dev, int *pidx, void *packet, int length) } static const struct dsa_ops felix_dsa_ops = { + .port_probe = felix_port_probe, .port_enable = felix_port_enable, .port_disable = felix_port_disable, .xmit = felix_xmit, diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index ce5b8eed64b4af9b0a2a97480b6f0b9c56fba3f9..954bf86121a4988197fd965f81e4af6d477ef4d5 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -883,7 +883,7 @@ int mvgbe_initialize(struct bd_info *bis) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = smi_reg_read; mdiodev->write = smi_reg_write; diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c index 96f8dc62b5693a6893720a3d1f5b3ef4a783ef76..6fb8a985d03732b7fea1de638458f7f1c291e02f 100644 --- a/drivers/net/mvmdio.c +++ b/drivers/net/mvmdio.c @@ -234,4 +234,3 @@ U_BOOT_DRIVER(mvmdio) = { .ops = &mvmdio_ops, .priv_auto = sizeof(struct mvmdio_priv), }; - diff --git a/drivers/net/octeontx/nic_main.c b/drivers/net/octeontx/nic_main.c index 8f05d4e720e3dd91637d25ae24179bf30d6e0eba..0f36f2586e6356037d30aa7310b0932cdefc723d 100644 --- a/drivers/net/octeontx/nic_main.c +++ b/drivers/net/octeontx/nic_main.c @@ -775,4 +775,3 @@ static struct pci_device_id octeontx_nic_supported[] = { }; U_BOOT_PCI_DEVICE(octeontx_nic, octeontx_nic_supported); - diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile index c9300727aefb2d5097d6b98f9199663ffe5ea499..dc14efd132f952075a75b44a49af0ceed243db0a 100644 --- a/drivers/net/octeontx2/Makefile +++ b/drivers/net/octeontx2/Makefile @@ -5,4 +5,3 @@ obj-$(CONFIG_NET_OCTEONTX2) += cgx.o nix_af.o nix.o rvu_pf.o \ rvu_af.o rvu_common.o - diff --git a/drivers/net/octeontx2/nix.c b/drivers/net/octeontx2/nix.c index 039c44b6540a152d9d487a35fbd3c2b8b05fd3c0..5954737b5c6d7e6dae17a8794a675e424681680e 100644 --- a/drivers/net/octeontx2/nix.c +++ b/drivers/net/octeontx2/nix.c @@ -828,4 +828,3 @@ void nix_print_mac_info(struct udevice *dev) printf(" CGX%d LMAC%d [%s]", lmac->cgx->cgx_id, lmac->lmac_id, lmac_type_to_str[lmac->lmac_type]); } - diff --git a/drivers/net/octeontx2/npc.h b/drivers/net/octeontx2/npc.h index 6e645cd32eac2f53db6cf906038ddd8eefd67b93..a20a1ba0671b7e5234f4fa365338428bbaf45262 100644 --- a/drivers/net/octeontx2/npc.h +++ b/drivers/net/octeontx2/npc.h @@ -87,4 +87,3 @@ struct npc { } #endif /* __NPC_H__ */ - diff --git a/drivers/net/octeontx2/rvu.h b/drivers/net/octeontx2/rvu.h index f455260a6fe51720992d4762939888a028b058f8..c0a834b89ada8eed85e7ce88c90275f639f38f27 100644 --- a/drivers/net/octeontx2/rvu.h +++ b/drivers/net/octeontx2/rvu.h @@ -116,4 +116,3 @@ void rvu_aq_free(struct admin_queue *aq); void rvu_get_lfid_for_pf(int pf, int *nixid, int *npaid); #endif /* __RVU_H__ */ - diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index 3228b8df49d4b4efe4c2564629fb00de93b06ba0..ae5b6fc2800a035cc8fa9d8e31ec05c27863bf94 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -161,7 +161,7 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv) int value, sgmii_2500 = 0; struct gemac_s *gem = priv->gem; - if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) + if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) sgmii_2500 = 1; @@ -220,7 +220,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id) /* Configure SGMII PCS */ if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII || - gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) { + gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) { out_be32(&scfg->mdioselcr, 0x00000000); pfe_configure_serdes(priv); } diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 64d5ddf238507b9c49c2b8ccdd40330dde80fd5b..68ee7d7a2dd09ca23714f151302d81e0c7274f57 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -71,7 +71,6 @@ menuconfig PHY_AQUANTIA config PHY_AQUANTIA_UPLOAD_FW bool "Aquantia firmware loading support" - default n depends on PHY_AQUANTIA help Aquantia PHYs use firmware which can be either loaded automatically @@ -102,7 +101,6 @@ config PHY_CORTINA config SYS_CORTINA_NO_FW_UPLOAD bool "Cortina firmware loading support" - default n depends on PHY_CORTINA help Cortina phy has provision to store phy firmware in attached dedicated @@ -250,7 +248,6 @@ config RTL8211X_PHY_FORCE_MASTER config RTL8211F_PHY_FORCE_EEE_RXC_ON bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" depends on PHY_REALTEK - default n help The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate transitions to/from a lower power consumption level (Low Power Idle diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index d3d35a75d065a11f6391f9a90ff731d61566f5d5..83075f78c9819c300bfa028123a586f432b5687b 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -308,9 +308,9 @@ struct { } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = { [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G, AQUANTIA_VND1_GSTART_RATE_1G}, - [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, + [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, AQUANTIA_VND1_GSTART_RATE_2_5G}, - [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, + [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, @@ -443,18 +443,18 @@ int aquantia_config(struct phy_device *phydev) return ret; } /* - * for backward compatibility convert XGMII into either XFI or USX based - * on FW config + * for backward compatibility convert XGMII into either 10GBase-R or + * USXGMII based on FW config */ if (interface == PHY_INTERFACE_MODE_XGMII) { - debug("use XFI or USXGMII SI protos, XGMII is not valid\n"); + debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n"); reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, AQUANTIA_SYSTEM_INTERFACE_SR); if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) interface = PHY_INTERFACE_MODE_USXGMII; else - interface = PHY_INTERFACE_MODE_XFI; + interface = PHY_INTERFACE_MODE_10GBASER; } /* @@ -494,7 +494,7 @@ int aquantia_config(struct phy_device *phydev) case PHY_INTERFACE_MODE_USXGMII: usx_an = 1; /* FALLTHROUGH */ - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: /* 10GBASE-T mode */ phydev->advertising = SUPPORTED_10000baseT_Full; phydev->supported = phydev->advertising; @@ -515,14 +515,14 @@ int aquantia_config(struct phy_device *phydev) phydev->dev->name); } else { reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; - debug("%s: system interface XFI\n", + debug("%s: system interface 10GBase-R\n", phydev->dev->name); } phy_write(phydev, MDIO_MMD_PHYXS, AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1); break; - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: /* 2.5GBASE-T mode */ phydev->advertising = SUPPORTED_1000baseT_Full; phydev->supported = phydev->advertising; diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index ffb1a61402e9940fcd173f44f96658379699a953..753ca7276869c2352fed010dd9f968599814f6b4 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -73,7 +73,7 @@ restart_aneg: if (!(wol & BIT(12)) || ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { - + /* Looks like aneg failed after all */ if (!retries) { printf("%s LPA corruption max attempts\n", diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 69acb694606193adfc3aeb6559d0df5c8427c639..c9fc20855ba1189e1b9835b367b69c367b979808 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -463,7 +463,7 @@ static struct phy_driver genphy_driver = { .shutdown = genphy_shutdown, }; -int genphy_init(void) +static int genphy_init(void) { return phy_register(&genphy_driver); } diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 3143a5813a6db4ea5c179922b1514de51771dab5..4055f07b2feb660a3e1e0852a61ff67abe34650b 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -657,7 +657,7 @@ int sh_eth_initialize(struct bd_info *bd) mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 4c3acba35a9d8729f6168b8b7565b7c93c5f2162..db324c17d67992b549210e66e10bd62acd57a6ac 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -251,18 +251,14 @@ struct smc91111_priv{ * We have only 16 Bit PCMCIA access on Socket 0 */ -#ifdef CONFIG_ADNPESC1 -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) -#elif CONFIG_ARM64 +#if CONFIG_ARM64 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) #else #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) #endif #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) -#ifdef CONFIG_ADNPESC1 -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) -#elif CONFIG_ARM64 +#if CONFIG_ARM64 #define SMC_outw(a, d, r) \ (*((volatile word*)((a)->iobase+((dword)(r)))) = d) #else @@ -439,11 +435,6 @@ struct smc91111_priv{ #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) /* buggy schematic: LEDa -> yellow, LEDb --> green */ -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ - | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ - | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) -#elif defined(CONFIG_ADNPESC1) -/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 8f420261fa8d9fdff694c99ab8488ec64006b214..5d9a73f23d750c13b1fddf56cd476fb3f43c97ea 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -425,7 +425,7 @@ static int smc911x_initialize_mii(struct smc911x_priv *priv) if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN); mdiodev->read = smc911x_miiphy_read; mdiodev->write = smc911x_miiphy_write; diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 0a27f3c43efb80905e720ab2405a11792e03e5c6..59018f00b29dd6660dfd263369324aa5f1acb948 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -13,9 +13,9 @@ /* Below are the register offsets and bit definitions * of the Lan911x memory space */ -#define RX_DATA_FIFO 0x00 +#define RX_DATA_FIFO 0x00 -#define TX_DATA_FIFO 0x20 +#define TX_DATA_FIFO 0x20 #define TX_CMD_A_INT_ON_COMP 0x80000000 #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index d7553fe1634b8b11e3339678fae3f8050620b17f..a6eb82bd1666c9f3a547914f03539106fa469a0f 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -403,7 +403,7 @@ static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev) } #define cache_clean_descriptor(desc) \ - flush_dcache_range((uintptr_t)(desc), \ + flush_dcache_range((uintptr_t)(desc), \ (uintptr_t)(desc) + sizeof(struct emac_dma_desc)) #define cache_inv_descriptor(desc) \ diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index bfe1b84cd566ba6f6c986ab5b67f344625ad7f23..2dfadbd82d5bcaf997e106817f590a3b6eb8b1f6 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -816,7 +816,7 @@ static int davinci_emac_probe(struct udevice *dev) struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); mdiodev->read = davinci_mii_phy_read; mdiodev->write = davinci_mii_phy_write; diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index ee820aae15efd1512de3349e5aabb52ecef47d53..0ce97656715f0e6a2dbdbf95542b436005556819 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -638,7 +638,7 @@ static int tsec_init(struct udevice *dev) return priv->phydev->link ? 0 : -1; } -static phy_interface_t tsec_get_interface(struct tsec_private *priv) +static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv) { struct tsec __iomem *regs = priv->regs; u32 ecntrl; @@ -701,8 +701,6 @@ static int init_phy(struct tsec_private *priv) /* Assign a Physical address to the TBI */ out_be32(®s->tbipa, priv->tbiaddr); - priv->interface = tsec_get_interface(priv); - if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv); @@ -886,12 +884,13 @@ int tsec_probe(struct udevice *dev) priv->tbiaddr = tbiaddr; phy_mode = dev_read_prop(dev, "phy-connection-type", NULL); + if (!phy_mode) + phy_mode = dev_read_prop(dev, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); - if (pdata->phy_interface == -1) { - printf("Invalid PHY interface '%s'\n", phy_mode); - return -EINVAL; - } + if (pdata->phy_interface == -1) + pdata->phy_interface = tsec_get_interface(priv); + priv->interface = pdata->phy_interface; /* Check for speed limit, default is 1000Mbps */ diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index 7bc2372e96d2d4350bc211b761c6a944af9902a4..af028f9cecad7ab6310ed585da209df03af0095d 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -66,7 +66,7 @@ int pch_ioctl(struct udevice *dev, ulong req, void *data, int size) UCLASS_DRIVER(pch) = { .id = UCLASS_PCH, .name = "pch", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index e4123ba820f9e32506c3623b410791832778ae25..cc139af6cb573f792687b82a2ca454a1146c1223 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -21,7 +21,6 @@ config DM_PCI_COMPAT config PCI_AARDVARK bool "Enable Aardvark PCIe driver" - default n depends on DM_GPIO depends on ARMADA_3700 help @@ -37,7 +36,6 @@ config PCI_PNP config PCI_REGION_MULTI_ENTRY bool "Enable Multiple entries of region type MEMORY in ranges for PCI" - default n help Enable PCI memory regions to be of multiple entry. Multiple entry here refers to allow more than one count of address ranges for MEMORY @@ -47,7 +45,6 @@ config PCI_REGION_MULTI_ENTRY config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" depends on MIPS - default n help Say Y if base address of system memory is being used as a virtual address instead of a physical address (e.g. on MIPS). The PCI core will then remap @@ -58,7 +55,6 @@ config PCI_MAP_SYSTEM_MEMORY config PCI_SRIOV bool "Enable Single Root I/O Virtualization support for PCI" - default n help Say Y here if you want to enable PCI Single Root I/O Virtualization capability support. This helps to enumerate Virtual Function devices @@ -67,7 +63,6 @@ config PCI_SRIOV config PCI_ARID bool "Enable Alternate Routing-ID support for PCI" - default n help Say Y here if you want to enable Alternate Routing-ID capability support on PCI devices. This helps to skip some devices in BDF @@ -75,14 +70,12 @@ config PCI_ARID config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" - default n help Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. config PCIE_ECAM_SYNQUACER bool "SynQuacer ECAM-based PCI host controller support" - default n select PCI_INIT_R select PCI_REGION_MULTI_ENTRY help @@ -186,7 +179,6 @@ config PCI_XILINX config PCIE_LAYERSCAPE bool - default n config PCIE_LAYERSCAPE_RC bool "Layerscape PCIe Root Complex mode support" diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index fc3327ec539cb51c717e5033cde1c2e0be3760ad..c544af2a0b7a29471872ae8c8d1ba9ccf636f086 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -885,7 +885,7 @@ int fsl_pcie_init_board(int busno) setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ #endif - return busno; + return busno; } #else int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index ce2eb5da2ca5153a0c199168b1ed479948282f77..044babee164f0cb35f494547b370ca6f748a521f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -304,8 +304,8 @@ int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32); } -int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, - enum pci_size_t size) +static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, + enum pci_size_t size) { struct udevice *bus; int ret; @@ -369,8 +369,8 @@ int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, return ops->read_config(bus, bdf, offset, valuep, size); } -int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, - enum pci_size_t size) +static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, + enum pci_size_t size) { struct udevice *bus; int ret; @@ -856,10 +856,7 @@ int pci_bind_bus_devices(struct udevice *bus) /* Check only the first access, we don't expect problems */ ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); - if (ret) - goto error; - - if (vendor == 0xffff || vendor == 0x0000) + if (ret || vendor == 0xffff || vendor == 0x0000) continue; pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, @@ -940,10 +937,6 @@ int pci_bind_bus_devices(struct udevice *bus) } return 0; -error: - printf("Cannot read bus configuration: %d\n", ret); - - return ret; } static void decode_regions(struct pci_controller *hose, ofnode parent_node, @@ -1433,9 +1426,9 @@ phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr, return phys_addr; } -int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, - unsigned long flags, unsigned long skip_mask, - pci_addr_t *ba) +static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, + unsigned long flags, unsigned long skip_mask, + pci_addr_t *ba) { struct pci_region *res; struct udevice *ctlr; diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index b128a05dd38042ea554c92bc8237fcf03fd0ffd5..08082460eb8631cc051b0d6983979f0951e5c0d1 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -12,6 +12,7 @@ #include <errno.h> #include <log.h> #include <pci.h> +#include "pci_internal.h" /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE @@ -165,6 +166,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_prefetch; struct pci_region *pci_io; u16 cmdstat, prefechable_64; + u8 io_32; struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); @@ -175,6 +177,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; + dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32); + io_32 &= PCI_IO_RANGE_TYPE_MASK; /* Configure bus number registers */ dm_pci_write_config8(dev, PCI_PRIMARY_BUS, @@ -191,7 +195,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) * I/O space */ dm_pci_write_config16(dev, PCI_MEMORY_BASE, - (pci_mem->bus_lower & 0xfff00000) >> 16); + ((pci_mem->bus_lower & 0xfff00000) >> 16) & + PCI_MEMORY_RANGE_MASK); cmdstat |= PCI_COMMAND_MEMORY; } @@ -205,7 +210,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) * I/O space */ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, - (pci_prefetch->bus_lower & 0xfff00000) >> 16); + (((pci_prefetch->bus_lower & 0xfff00000) >> 16) & + PCI_PREF_RANGE_MASK) | prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) #ifdef CONFIG_SYS_PCI_64BIT dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, @@ -217,8 +223,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ - dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); - dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 | + prefechable_64); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | + prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); @@ -230,8 +238,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_io, 0x1000); dm_pci_write_config8(dev, PCI_IO_BASE, - (pci_io->bus_lower & 0x0000f000) >> 8); - dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, + (((pci_io->bus_lower & 0x0000f000) >> 8) & + PCI_IO_RANGE_MASK) | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, (pci_io->bus_lower & 0xffff0000) >> 16); cmdstat |= PCI_COMMAND_IO; @@ -261,7 +271,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_mem, 0x100000); dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, - (pci_mem->bus_lower - 1) >> 16); + ((pci_mem->bus_lower - 1) >> 16) & + PCI_MEMORY_RANGE_MASK); } if (pci_prefetch) { @@ -275,7 +286,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_prefetch, 0x100000); dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, - (pci_prefetch->bus_lower - 1) >> 16); + (((pci_prefetch->bus_lower - 1) >> 16) & + PCI_PREF_RANGE_MASK) | prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) #ifdef CONFIG_SYS_PCI_64BIT dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, @@ -286,12 +298,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) } if (pci_io) { + u8 io_32; + + dm_pci_read_config8(dev, PCI_IO_LIMIT, + &io_32); + io_32 &= PCI_IO_RANGE_TYPE_MASK; + /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); dm_pci_write_config8(dev, PCI_IO_LIMIT, - ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); - dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, + ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) & + PCI_IO_RANGE_MASK) | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); } } diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index 12ce9d525ca86e272dee50f08ae0b58610855596..be03dcbd97c01d61ed94ea57603585d727b65d1c 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Broadcom + * Copyright (C) 2020-2021 Broadcom * */ @@ -12,6 +12,7 @@ #include <malloc.h> #include <asm/io.h> #include <dm/device_compat.h> +#include <linux/delay.h> #include <linux/log2.h> #define EP_PERST_SOURCE_SELECT_SHIFT 2 @@ -884,7 +885,7 @@ static int iproc_pcie_map_ranges(struct udevice *dev) for (i = 0; i < hose->region_count; i++) { if (hose->regions[i].flags == PCI_REGION_MEM || hose->regions[i].flags == PCI_REGION_PREFETCH) { - debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n", + debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n", i, &hose->regions[i].bus_start, &hose->regions[i].phys_start, hose->regions[i].size); @@ -1049,7 +1050,7 @@ static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) while (!pci_get_dma_regions(pcie->dev, ®ions, i)) { dev_dbg(pcie->dev, - "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n", + "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n", i, regions.bus_start, regions.phys_start, regions.size); /* Each range entry corresponds to an inbound mapping region */ diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index 8b924d404c2d61ada5644186a3a30d42e0bacf86..3216a20027a85ae8619224897c46addf5fa65add 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/soc.h> #include <linux/libfdt.h> +#include <fdt_support.h> #include "pcie_layerscape_fixup_common.h" void ft_pci_setup(void *blob, struct bd_info *bd) @@ -29,7 +30,7 @@ void ft_pci_setup(void *blob, struct bd_info *bd) } #if defined(CONFIG_FSL_LAYERSCAPE) -int lx2_board_fix_fdt(void *fdt) +static int lx2_board_fix_fdt(void *fdt) { char *reg_name, *old_str, *new_str; const char *reg_names; diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index bd2c19f7f0c9239624ec6fafe05f3d8b9f56e822..f50d6ef65396104735514eba6e2b292bcb349c85 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -143,8 +143,8 @@ static int ls_pcie_addr_valid(struct ls_pcie_rc *pcie_rc, pci_dev_t bdf) return 0; } -int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf, - uint offset, void **paddress) +static int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf, + uint offset, void **paddress) { struct ls_pcie_rc *pcie_rc = dev_get_priv(bus); struct ls_pcie *pcie = pcie_rc->pcie; diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 424002840359c7e869133829f26c15730baa0f72..b5f69c0a96d33a8f23a60a2cf86ec886b373409d 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -1,6 +1,5 @@ config MVEBU_COMPHY_SUPPORT bool "ComPhy SerDes driver" - default n help Choose this option to add support for Comphy driver. diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h index ba64491dfe11af82e2e90d833472bd2eaf7c16a1..9bbd7f8f35dcc98c108882f69ec1ae529ac486f4 100644 --- a/drivers/phy/marvell/comphy_core.h +++ b/drivers/phy/marvell/comphy_core.h @@ -141,4 +141,3 @@ void comphy_pcie_config_detect(u32 comphy_max_count, void comphy_pcie_unit_general_config(u32 pex_index); #endif /* _COMPHY_CORE_H_ */ - diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h index 8a570bae7390546f22a38923893a45babfa9a035..264d14b6041beb4b03e3268036cbfab827e40a71 100644 --- a/drivers/phy/marvell/utmi_phy.h +++ b/drivers/phy/marvell/utmi_phy.h @@ -98,4 +98,3 @@ (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET) #endif /* _UTMI_PHY_H_ */ - diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c index acaa55d2e7fe030a2336dd82ffe227274359c122..181a6ff27026c74d24634f25de4c7a61ca2fc554 100644 --- a/drivers/pinctrl/intel/pinctrl_apl.c +++ b/drivers/pinctrl/intel/pinctrl_apl.c @@ -155,7 +155,7 @@ static int apl_pinctrl_of_to_plat(struct udevice *dev) return intel_pinctrl_of_to_plat(dev, comm, 2); } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_gpio_ids[] = { { .compatible = "intel,apl-pinctrl"}, { } @@ -168,7 +168,7 @@ U_BOOT_DRIVER(intel_apl_pinctrl) = { .of_match = of_match_ptr(apl_gpio_ids), .probe = intel_pinctrl_probe, .ops = &intel_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .of_to_plat = apl_pinctrl_of_to_plat, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index b413a4c7e48b2e82bb167f5f5cb69062f0e70ee2..bf4e9a28e9d3cf9744b6e194ea11d95d53017bb1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -750,5 +750,3 @@ U_BOOT_DRIVER(mt7622_pinctrl) = { .probe = mtk_pinctrl_mt7622_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; - - diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index 5d234bca3d44a2cf2aa8ff7f3026517c2420bb84..820a6c9bb1aa2b5ca98e9f5c984d9aa4cce9808a 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -908,7 +908,7 @@ static struct meson_bank meson_axg_aobus_banks[] = { }; static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = { - /* name first last reg offset */ + /* name first last reg offset */ BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0), BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0), BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0), diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 8bd265ad952ac13c7fb52ca9a1a9d28208802b3e..90a4f8056cdb77e7a7614acf0accd1e9acf76a96 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1220,7 +1220,7 @@ static struct meson_bank meson_g12a_aobus_banks[] = { }; static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { - /* name first last reg offset */ + /* name first last reg offset */ BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 0x6, 0), BANK_PMX("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 0xb, 0), BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0x0, 0), diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index e6b10a377b6c12f65b8f405546e4e974dfb4f2f9..9a54b8bbe9028311dd1ee087864aac368a61a3f8 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -186,7 +186,7 @@ U_BOOT_DRIVER(fsl_imx23_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(mxs_pinctrl_match), .probe = mxs_pinctrl_probe, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .priv_auto = sizeof(struct mxs_pinctrl_priv), diff --git a/drivers/pinctrl/pinctrl-qe-io.c b/drivers/pinctrl/pinctrl-qe-io.c index e129ab2f8311639cfda4cdd3f4f159a858aa72fd..dc0be7ce3bd6d1a39b48cbdbff307a9fde8d7190 100644 --- a/drivers/pinctrl/pinctrl-qe-io.c +++ b/drivers/pinctrl/pinctrl-qe-io.c @@ -248,7 +248,7 @@ U_BOOT_DRIVER(par_io_pinctrl) = { .of_to_plat = qe_io_of_to_plat, .plat_auto = sizeof(struct qe_io_plat), .ops = &par_io_pinctrl_ops, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .flags = DM_FLAG_PRE_RELOC, #endif }; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index dfe60b6dadb29b3867f269d13c381bb229734ff0..4462ed20e2d36941f83031b5add8fb0299270277 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -421,7 +421,7 @@ static int __maybe_unused pinctrl_post_bind(struct udevice *dev) UCLASS_DRIVER(pinctrl) = { .id = UCLASS_PINCTRL, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = pinctrl_post_bind, #endif .flags = DM_UC_FLAG_SEQ_ALIAS, diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 4e6f406214dccf382bbe5677ad5b62ad410b9b04..8cf133a2baf4f3b5c765bad09fb95676d6efc94c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -161,7 +161,7 @@ #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 2d15500f0f0f0e5d64bb337c7b6de3e6e435919c..7cd4ef9830b4c1bbe11ca5f606b9b5f887bb98ea 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -88,7 +88,7 @@ #define GPSR1_0 F_(IRQ0, IP2_27_24) /* GPSR2 */ -#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) +#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) #define GPSR2_26 F_(SDA3, IP10_7_4) @@ -253,11 +253,11 @@ #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index 6058d0f4c13f4455d963c16aa27da03381f7514a..9de29c0b8b4332eafccb997c957252561454cf41 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -363,7 +363,7 @@ U_BOOT_DRIVER(pinctrl_px30) = { .of_match = px30_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 9ccee465b0f38be8374a94dfcce95d3f41abf9d3..afcd34396e277e4e770dd2fd2c91926e6a514558 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -103,7 +103,7 @@ U_BOOT_DRIVER(pinctrl_rockchip) = { .of_match = rk3036_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 85c2e611b6b21f1a09fceffbadacd930c8b6f656..e6dc1af86e960524f27cfae00fc4b6cc2d057326 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -205,7 +205,7 @@ U_BOOT_DRIVER(pinctrl_rk3128) = { .of_match = rk3128_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 06d53e22d27d649c3588fdd2ed6e6350325ceb65..9a982cbfad9ced0207080f7868b2e553364ecc78 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -126,7 +126,7 @@ U_BOOT_DRIVER(rockchip_rk3188_pinctrl) = { .of_match = rk3188_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index fe386933c585670288c8998e8b803dad9f8d8b74..7c58f40d93db86755934093e0bf59b93d62833f8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -292,7 +292,7 @@ U_BOOT_DRIVER(pinctrl_rk3228) = { .of_match = rk3228_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index fc2810248ba1f50ab3055cba162a0bddd3569312..5894f47f534b1c314fe04165482f623982e826b0 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -248,7 +248,7 @@ U_BOOT_DRIVER(rockchip_rk3288_pinctrl) = { .of_match = rk3288_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index a9b87b745718a2719e83a82a3fe161af066658ae..83186f40f6f089d2bfb04b771f0af56cc2417d28 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -459,7 +459,7 @@ U_BOOT_DRIVER(pinctrl_rk3308) = { .of_match = rk3308_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index aa8bd76d6fb5496f33d3729f3c34120124819f2f..1c3c5986a50458252ab0b5287400503c1f736d24 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -323,7 +323,7 @@ U_BOOT_DRIVER(rockchip_rk3328_pinctrl) = { .of_match = rk3328_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 18d3e3a9b5c55b6fa69188398505e4bfbe2fc9d5..ba867a891748741f788705b0bc94b1bf58b6f7d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -177,7 +177,7 @@ U_BOOT_DRIVER(rockchip_rk3368_pinctrl) = { .of_match = rk3368_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 0c1adc379465f9679244739251015883580036b2..caa92200c6eb9c36d5474b0585479663e70dbc24 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -317,7 +317,7 @@ U_BOOT_DRIVER(pinctrl_rk3399) = { .of_match = rk3399_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index d35425b5fa2a69c287670fa3c897deee1e1afaa4..5b70b503d2b12381194c1aa254c45c9b29eb3b19 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -291,7 +291,7 @@ U_BOOT_DRIVER(pinctrl_rv1108) = { .of_match = rv1108_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index c5fbf1f832a90219a02be2f83db82a19a1c9e342..2c20dc7c8318f2470326d9abd7553c6ccbb147f1 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,4 +1,46 @@ -menu "Power" +menuconfig POWER + bool "Power" + default y + help + Enable support for power control in U-Boot. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in U-Boot to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of a build. + +if POWER + +config POWER_LEGACY + bool "Legacy power support" + help + Note: This is a legacy option. Use DM_PMIC instead. + + Enable support for power control in U-Boot. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in U-Boot to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of a build. + +config SPL_POWER_LEGACY + bool "Legacy power support in SPL" + default y if POWER_LEGACY + help + Note: This is a legacy option. Use SPL_DM_PMIC instead. + + Enable support for power control in SPL. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in SPL to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of a build. source "drivers/power/acpi_pmc/Kconfig" @@ -248,7 +290,6 @@ endchoice config AXP_ALDO3_INRUSH_QUIRK bool "axp pmic (a)ldo3 inrush quirk" depends on AXP209_POWER - default n ---help--- The reference design denotes a value of 4.7 uF for the output capacitor of LDO3. Some boards have too high capacitance causing an inrush current @@ -357,7 +398,6 @@ config AXP_FLDO3_VOLT config AXP_SW_ON bool "axp pmic sw on" depends on AXP809_POWER || AXP818_POWER - default n ---help--- Enable to turn on axp pmic sw. @@ -385,4 +425,25 @@ config POWER_MT6323 This adds poweroff driver for mt6323 this pmic is used on mt7623 / Bananapi R2 -endmenu +config POWER_I2C + bool "I2C-based power control for legacy power" + depends on POWER_LEGACY + help + Enable this to use the I2C driver designed for the legacy PMIC + interface. + + Not to be used for new designs and existing ones should be moved to + the new PMIC interface based on driver model. + +config SPL_POWER_I2C + bool "I2C-based power control for legacy power" + depends on SPL_POWER_LEGACY + default y if POWER_I2C + help + Enable this to use the I2C driver designed for the legacy PMIC + interface. + + Not to be used for new designs and existing ones should be moved to + the new PMIC interface based on driver model. + +endif diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 0bef06920a7dcaca64de8e56b33bac42bdb2b770..f805027784db39ffcd9017385e4a02976b60c6cb 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -3,6 +3,14 @@ # Copyright (c) 2009 Wind River Systems, Inc. # Tom Rix <Tom.Rix at windriver.com> +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ +obj-y += battery/ +obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ +obj-y += fuel_gauge/ +obj-y += mfd/ +obj-y += pmic/ +obj-y += regulator/ + obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP221_POWER) += axp221.o @@ -16,9 +24,9 @@ obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_TWL6030_POWER) += twl6030.o obj-$(CONFIG_PALMAS_POWER) += palmas.o -obj-$(CONFIG_POWER) += power_core.o +obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o obj-$(CONFIG_DIALOG_POWER) += power_dialog.o obj-$(CONFIG_POWER_FSL) += power_fsl.o -obj-$(CONFIG_POWER_I2C) += power_i2c.o +obj-$(CONFIG_$(SPL_TPL_)POWER_I2C) += power_i2c.o obj-$(CONFIG_POWER_SPI) += power_spi.o obj-$(CONFIG_POWER_MT6323) += mt6323.o diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile index 115788f109aab21e38dcb12344685c680df430c7..0db52a6582440a1e65388978dbfaa96f14bdcb24 100644 --- a/drivers/power/acpi_pmc/Makefile +++ b/drivers/power/acpi_pmc/Makefile @@ -2,5 +2,5 @@ # # Copyright 2019 Google LLC -obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o +obj-y += acpi-pmc-uclass.o obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 00d1489ea20543b8522cc22a04faf427eb4b1315..33f9206bd09db5f93a516e03ddc0c1168265e2c9 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -112,7 +112,7 @@ int power_domain_off(struct power_domain *power_domain) return ops->off(power_domain); } -#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) +#if CONFIG_IS_ENABLED(OF_REAL) static int dev_power_domain_ctrl(struct udevice *dev, bool on) { struct power_domain pd; @@ -162,7 +162,7 @@ int dev_power_domain_off(struct udevice *dev) { return dev_power_domain_ctrl(dev, false); } -#endif +#endif /* OF_REAL */ UCLASS_DRIVER(power_domain) = { .id = UCLASS_POWER_DOMAIN, diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index fd6648b313ee14e3ff2605655a472bca3c5cc969..cf2a9b2c17e470245523b48f1233856944f4569e 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -10,6 +10,19 @@ config DM_PMIC - 'drivers/power/pmic/pmic-uclass.c' - 'include/power/pmic.h' +config SPL_DM_PMIC + bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" + depends on SPL_DM + default y if DM_PMIC + ---help--- + This config enables the driver-model PMIC support in SPL. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' + config PMIC_CHILDREN bool "Allow child devices for PMICs" depends on DM_PMIC @@ -205,6 +218,15 @@ config PMIC_RK8XX accessed via an I2C interface. The device is used with Rockchip SoCs. This driver implements register read/write operations. +config SPL_PMIC_RK8XX + bool "Enable support for Rockchip PMIC RK8XX" + depends on DM_PMIC + ---help--- + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. + config PMIC_S2MPS11 bool "Enable Driver Model for PMIC Samsung S2MPS11" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 5d1a97e5f6f5c2804178c0652731927fea7e200c..5250eac12f2d1274277f95b850236e8539ae88a6 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2012 Samsung Electronics # Lukasz Majewski <l.majewski@samsung.com> -obj-$(CONFIG_DM_PMIC) += pmic-uclass.o +obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o @@ -20,7 +20,7 @@ obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o -obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o +obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c index fcd0a654a889835d3f07aae84a3e0c99f9757b78..e3de73082150244ef58e92a633db596b486c25e8 100644 --- a/drivers/power/pmic/pmic_tps65910.c +++ b/drivers/power/pmic/pmic_tps65910.c @@ -51,7 +51,7 @@ int power_tps65910_init(unsigned char bus) /* * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C - * interface. + * interface. * @return: 0 on success, not 0 on failure */ int tps65910_set_i2c_control(void) diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 677134c822ccc8fad7f79399c2ee8195c9bb0cf6..4efb32a322825370a4375497f25d87d118cb6d8f 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o -obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o +obj-$(CONFIG_$(SPL_TPL_)REGULATOR_RK8XX) += rk8xx.o obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 03eeacc286d766ff2b9a2a1e073c7d7bcdb21b8f..2311910a636e91880bbd2e341deba31e49006f8d 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -401,7 +401,7 @@ static const struct pwm_ops meson_pwm_ops = { .set_invert = meson_pwm_set_invert, }; -#define XTAL -1 +#define XTAL -1 /* Local clock ids aliases to avoid define conflicts */ #define GXBB_CLKID_HDMI_PLL 2 diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 5da971ddc0afe8ff0cc9e677e5f4df875ae43f80..c4bd5c4a147f5ff1fc96f3558023c4e17c79c7ab 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1407,7 +1407,7 @@ int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info) if (!mdiodev) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); mdiodev->read = uec_miiphy_read; mdiodev->write = uec_miiphy_write; diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 049b9dc249282732d7df04d3a20be7e59ebb75a3..576d5af8688e8bc52e2a11290acfd604f6705c0a 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -3,7 +3,6 @@ if RAM || SPL_RAM config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on DM && OF_CONTROL && ARCH_ASPEED - default n help Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual @@ -42,14 +41,12 @@ endchoice config ASPEED_BYPASS_SELFTEST bool "bypass self test during DRAM initialization" - default n help Say Y here to bypass DRAM self test to speed up the boot time config ASPEED_ECC bool "aspeed SDRAM error correcting code" depends on DM && OF_CONTROL && ARCH_ASPEED - default n help enable SDRAM ECC function diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index cb8edcbc154ce985e53320b43d09e57b0f698288..95b5cf9128b0d9aea42779f6f13e33c465f8715b 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -27,8 +27,8 @@ #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0 -#define DDRSS_V2A_R1_MAT_REG 0x0020 -#define DDRSS_ECC_CTRL_REG 0x0120 +#define DDRSS_V2A_R1_MAT_REG 0x0020 +#define DDRSS_ECC_CTRL_REG 0x0120 struct k3_ddrss_desc { struct udevice *dev; diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig index eb5a1208edf87e4ca2d1e9b972aa33a49f996698..f19957293f95cfbe57dc5bea928ae6899cc0abe7 100644 --- a/drivers/ram/octeon/Kconfig +++ b/drivers/ram/octeon/Kconfig @@ -1,7 +1,6 @@ config RAM_OCTEON bool "Ram drivers for Octeon SoCs" depends on RAM && ARCH_OCTEON - default n help This enables support for RAM drivers for Octeon SoCs. @@ -9,7 +8,6 @@ if RAM_OCTEON config RAM_OCTEON_DDR4 bool "Octeon III DDR4 RAM support" - default n help This enables support for DDR4 RAM suppoort for Octeon III. This does not include support for Octeon CN70XX. diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index a9d051852a48b260073be21a526fe02db56132c4..69c454a4ba86b029a781d2b4f86c3d6e895c3275 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -883,13 +883,13 @@ static int rk3368_dmc_of_to_plat(struct udevice *dev) { int ret = 0; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3368_sdram_params *plat = dev_get_plat(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3368_sdram_params *plat = dev_get_plat(dev); - ret = regmap_init_mem(dev_ofnode(dev), &plat->map); - if (ret) - return ret; -#endif + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + return ret; + } return ret; } diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 25ae69e9acd1960b703a37aad7cf7cfa87d2c7a9..d9ed8adfcfd05a74b37e8a8abe1243957f67d306 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -816,10 +816,12 @@ static int setup_sdram(struct udevice *dev) static int rk3188_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3188_sdram_params *params = dev_get_plat(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + /* rk3188 supports only one-channel */ params->num_channels = 1; ret = dev_read_u32_array(dev, "rockchip,pctl-timing", @@ -846,7 +848,6 @@ static int rk3188_dmc_of_to_plat(struct udevice *dev) ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); if (ret) return ret; -#endif return 0; } diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 9057ccacd96e1fef2206bbd9ec8bcfa2c095b0b3..cd4234f389ebe4db08f26cea61114464c4fa4cd0 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -716,12 +716,14 @@ out: static int rk322x_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk322x_sdram_params *params = dev_get_plat(dev); const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + params->num_channels = 1; ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", @@ -748,7 +750,6 @@ static int rk322x_dmc_of_to_plat(struct udevice *dev) ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); if (ret) return ret; -#endif return 0; } @@ -852,4 +853,3 @@ U_BOOT_DRIVER(dmc_rk322x) = { .plat_auto = sizeof(struct rk322x_sdram_params), #endif }; - diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index a933abf0d459e2bd26ef5f63e39a5bad755ecd30..f3e4a2808ab7ca19876642fcbd335a6e44007e08 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -973,10 +973,12 @@ static int setup_sdram(struct udevice *dev) static int rk3288_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_sdram_params *params = dev_get_plat(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + /* Rk3288 supports dual-channel, set default channel num to 2 */ params->num_channels = 2; ret = dev_read_u32_array(dev, "rockchip,pctl-timing", @@ -1008,7 +1010,6 @@ static int rk3288_dmc_of_to_plat(struct udevice *dev) ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); if (ret) return ret; -#endif return 0; } diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 9af4c372d50b4f025282e2e3c6be4419c01fd74f..9c6798f816ac89b9a91b2de84e184fd06f15bf8a 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -517,7 +517,7 @@ static int rk3328_dmc_init(struct udevice *dev) struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct rk3328_sdram_params *params = &plat->sdram_params; #else struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; @@ -549,7 +549,7 @@ static int rk3328_dmc_init(struct udevice *dev) static int rk3328_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index a83a670b32203894957b3e4d1153164f07bcd5e8..c0a06dcaed04e2dfc11fbaa0f33baf726d51295f 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3013,10 +3013,12 @@ static int sdram_init(struct dram_info *dram, static int rk3399_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + ret = dev_read_u32_array(dev, "rockchip,sdram-params", (u32 *)&plat->sdram_params, sizeof(plat->sdram_params) / sizeof(u32)); @@ -3029,7 +3031,6 @@ static int rk3399_dmc_of_to_plat(struct udevice *dev) if (ret) printf("%s: regmap failed %d\n", __func__, ret); -#endif return 0; } @@ -3068,7 +3069,7 @@ static int rk3399_dmc_init(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct rk3399_sdram_params *params = &plat->sdram_params; #else struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; @@ -3106,7 +3107,7 @@ static int rk3399_dmc_init(struct udevice *dev) priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); #if CONFIG_IS_ENABLED(OF_PLATDATA) - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->ddr_clk); #else ret = clk_get_by_index(dev, 0, &priv->ddr_clk); #endif diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 3e25cc7a01844d1a34856b41929215da4300ccf6..47a930ee95409f37a425c561c76ed2e242f8949a 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -286,7 +286,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) } else { dev_dbg(dev, "cannot find st,mem_remap property\n"); } - + swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND); if (swp_fmc != NOT_FOUND) { /* set fmc swapping selection */ diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig index 2fd8c7b7e3b89a10f3ac6eedc1bd66a35cc4329b..1aaf064c30cf3a1e0e114d6b1da9d9321cb6f4ec 100644 --- a/drivers/ram/stm32mp1/Kconfig +++ b/drivers/ram/stm32mp1/Kconfig @@ -23,7 +23,6 @@ config STM32MP1_DDR_INTERACTIVE config STM32MP1_DDR_INTERACTIVE_FORCE bool "STM32MP1 DDR driver : force interactive mode" depends on STM32MP1_DDR_INTERACTIVE - default n help force interactive mode in STM32MP1 DDR controller driver skip the polling of character 'd' in console diff --git a/drivers/reboot-mode/Kconfig b/drivers/reboot-mode/Kconfig index ac67bfcef623ae76eb800a2bf58b92074b926b37..63ea18cdf095774e898de11e913ea1f1fb977171 100644 --- a/drivers/reboot-mode/Kconfig +++ b/drivers/reboot-mode/Kconfig @@ -9,7 +9,6 @@ menu "Reboot Mode Support" config DM_REBOOT_MODE bool "Enable reboot mode using Driver Model" depends on DM - default n help Enable support for reboot mode control. This will allow users to adjust the boot process based on reboot mode parameter @@ -18,7 +17,6 @@ config DM_REBOOT_MODE config DM_REBOOT_MODE_GPIO bool "Use GPIOs as reboot mode backend" depends on DM_REBOOT_MODE - default n help Use GPIOs to control the reboot mode. This will allow users to boot a device in a specific mode by using a GPIO that can be controlled @@ -27,7 +25,6 @@ config DM_REBOOT_MODE_GPIO config DM_REBOOT_MODE_RTC bool "Use RTC as reboot mode backend" depends on DM_REBOOT_MODE - default n help Use RTC non volatile memory to control the reboot mode. This will allow users to boot a device in a specific mode by using a register(s) that can be controlled diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index d4e0745d0e097ae6c80ed55981e3aba276451ffc..5896bcb421813198fe9fee55326b6a61eb72918b 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -70,16 +70,16 @@ struct reset_ops meson_reset_ops = { .rst_deassert = meson_reset_deassert, }; -static const struct udevice_id meson_reset_ids[] = { - { .compatible = "amlogic,meson-gxbb-reset" }, +static const struct udevice_id meson_reset_ids[] = { + { .compatible = "amlogic,meson-gxbb-reset" }, { .compatible = "amlogic,meson-axg-reset" }, - { } -}; + { } +}; static int meson_reset_probe(struct udevice *dev) { struct meson_reset_priv *priv = dev_get_priv(dev); - + return regmap_init_mem(dev_ofnode(dev), &priv->regmap); } diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c index e2d284e5aca5383a3f2ab12c02f1f59ffeb97457..6a80179b822d93edb629ddd5927b897378ff8690 100644 --- a/drivers/reset/reset-raspberrypi.c +++ b/drivers/reset/reset-raspberrypi.c @@ -57,4 +57,3 @@ U_BOOT_DRIVER(raspberrypi_reset) = { .of_match = raspberrypi_reset_ids, .ops = &raspberrypi_reset_ops, }; - diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index 94915d45b39225bde0d0f4d42b4660de6136c025..b1c5ab93d15dd21263309959fc5bb1800b1fa6f4 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -34,14 +34,12 @@ config RNG_MSM config RNG_STM32MP1 bool "Enable random number generator for STM32MP1" depends on ARCH_STM32MP - default n help Enable STM32MP1 rng driver. config RNG_ROCKCHIP bool "Enable random number generator for rockchip crypto rng" depends on ARCH_ROCKCHIP && DM_RNG - default n help Enable random number generator for rockchip.This driver is support rng module of crypto v1 and crypto v2. @@ -49,7 +47,6 @@ config RNG_ROCKCHIP config RNG_IPROC200 bool "Broadcom iProc RNG200 random number generator" depends on DM_RNG - default n help Enable random number generator for RPI4. endif diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index b6692e62df1c717b270272141c38f9f52fd34fc0..71777cdd05f796e5f5b7421b8d500851586f5ad3 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -136,6 +136,7 @@ config RTC_RX8010SJ config RTC_RX8025 bool "Enable RX8025 driver" + depends on DM_RTC help Support for Epson RX8025 Real Time Clock devices. diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 2015ce9bbcd4561b763504cc8f7e7792d8ce95b0..3be97c9d933fcc67308ccda07cb4d3923942103d 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -43,11 +43,21 @@ enum ds_type { #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ +/* DS1307-specific bits */ #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ +/* DS1337-specific bits */ +#define DS1337_CTL_BIT_RS1 0x08 /* Rate select 1 */ +#define DS1337_CTL_BIT_RS2 0x10 /* Rate select 2 */ +#define DS1337_CTL_BIT_EOSC 0x80 /* Enable Oscillator */ + +/* DS1340-specific bits */ +#define DS1340_SEC_BIT_EOSC 0x80 /* Enable Oscillator */ +#define DS1340_CTL_BIT_OUT 0x80 /* Output Control */ + /* MCP7941X-specific bits */ #define MCP7941X_BIT_ST 0x80 #define MCP7941X_BIT_VBATEN 0x08 @@ -261,9 +271,25 @@ read_rtc: buf[RTC_SEC_REG_ADDR]); return -1; } - } - - if (type == m41t11) { + } else if (type == ds_1337) { + if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the not oscillator enable (~EOSC) flag */ + buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC; + dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + buf[RTC_CTL_REG_ADDR]); + return -1; + } + } else if (type == ds_1340) { + if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the not oscillator enable (~EOSC) flag */ + buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC; + dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, + buf[RTC_SEC_REG_ADDR]); + return -1; + } + } else if (type == m41t11) { /* clock halted? turn it on, so clock can tick. */ if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) { buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH; @@ -273,9 +299,7 @@ read_rtc: buf[RTC_SEC_REG_ADDR]); goto read_rtc; } - } - - if (type == mcp794xx) { + } else if (type == mcp794xx) { /* make sure that the backup battery is enabled */ if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) { dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR, @@ -314,18 +338,37 @@ read_rtc: static int ds1307_rtc_reset(struct udevice *dev) { int ret; + enum ds_type type = dev_get_driver_data(dev); - /* clear Clock Halt */ + /* + * reset clock/oscillator in the seconds register: + * on DS1307 bit 7 enables Clock Halt (CH), + * on DS1340 bit 7 disables the oscillator (not EOSC) + * on MCP794xx bit 7 enables Start Oscillator (ST) + */ ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00); if (ret < 0) return ret; - ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, - RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | - RTC_CTL_BIT_RS0); - if (ret < 0) - return ret; - return 0; + if (type == ds_1307) { + /* Write control register in order to enable square-wave + * output (SQWE) and set a default rate of 32.768kHz (RS1|RS0). + */ + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | + RTC_CTL_BIT_RS0); + } else if (type == ds_1337) { + /* Write control register in order to enable oscillator output + * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1). + */ + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1); + } else if (type == ds_1340 || type == mcp794xx || type == m41t11) { + /* Reset clock calibration, frequency test and output level. */ + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0x00); + } + + return ret; } static int ds1307_probe(struct udevice *dev) diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 8f0e1ab5ac63ba69a2740b105cee094c849128b5..6f47d82522baf83d0041eb2cbbef29dd28e57cfb 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -9,8 +9,8 @@ #include <div64.h> #include <dm.h> #include <env.h> -#include <generated/timestamp_autogenerated.h> #include <rtc.h> +#include <timestamp.h> /** * struct emul_rtc - private data for emulated RTC driver diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index 321b8732ed9a238e9fd3050808631674f3ffd811..e5ae6ea4d5f3cf4aa55ed5c771c64f91e0f7db9e 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -177,7 +177,7 @@ UCLASS_DRIVER(rtc) = { .name = "rtc", .id = UCLASS_RTC, .flags = DM_UC_FLAG_SEQ_ALIAS, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index e717dcbbfe35385792576e01c1dfe2b4f9ae6a66..1394c2306a445f5326ba29446fe0589340f24859 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -24,22 +24,11 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#endif - -#ifdef CONFIG_DM_RTC -#define DEV_TYPE struct udevice -#else -/* Local udevice */ -struct ludevice { - u8 chip; +enum rx_model { + model_rx_8025, + model_rx_8035, }; -#define DEV_TYPE struct ludevice - -#endif - /* * RTC register addresses */ @@ -50,6 +39,7 @@ struct ludevice { #define RTC_DATE_REG_ADDR 0x04 #define RTC_MON_REG_ADDR 0x05 #define RTC_YR_REG_ADDR 0x06 +#define RTC_OFFSET_REG_ADDR 0x07 #define RTC_CTL1_REG_ADDR 0x0e #define RTC_CTL2_REG_ADDR 0x0f @@ -74,39 +64,36 @@ struct ludevice { * address in a first cycle that is terminated by * a STOP condition. The chips needs a 'restart' * sequence (start sequence without a prior stop). - * This driver has been written for a 4xx board. - * U-Boot's 4xx i2c driver is currently not capable - * to generate such cycles to some work arounds - * are used. */ -/* static uchar rtc_read (uchar reg); */ -#ifdef CONFIG_DM_RTC -/* - * on mpc85xx based board with DM and offset len 1 - * accessing rtc works fine. May we can drop this ? - */ #define rtc_read(reg) buf[(reg) & 0xf] -#else -#define rtc_read(reg) buf[((reg) + 1) & 0xf] -#endif -static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val); +static int rtc_write(struct udevice *dev, uchar reg, uchar val); + +static int rx8025_is_osc_stopped(enum rx_model model, int ctrl2) +{ + int xstp = ctrl2 & RTC_CTL2_BIT_XST; + /* XSTP bit has different polarity on RX-8025 vs RX-8035. + * RX-8025: 0 == oscillator stopped + * RX-8035: 1 == oscillator stopped + */ + + if (model == model_rx_8025) + xstp = !xstp; + + return xstp; +} /* * Get the current time from the RTC */ -static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) +static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp) { int rel = 0; uchar sec, min, hour, mday, wday, mon, year, ctl2; uchar buf[16]; -#ifdef CONFIG_DM_RTC if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { -#else - if (i2c_read(dev->chip, 0, 0, buf, 16)) { -#endif printf("Error reading from RTC\n"); return -EIO; } @@ -134,8 +121,7 @@ static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) printf("RTC: voltage drop detected\n"); rel = -1; } - - if (!(ctl2 & RTC_CTL2_BIT_XST)) { + if (rx8025_is_osc_stopped(dev->driver_data, ctl2)) { printf("RTC: oscillator stop detected\n"); rel = -1; } @@ -165,8 +151,21 @@ static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) /* * Set the RTC */ -static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) +static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp) { + /* To work around the read/write cycle issue mentioned + * at the top of this file, write all the time registers + * in one I2C transaction + */ + u8 write_op[8]; + + /* 2412 flag must be set before doing a RTC write, + * otherwise the seconds and minute register + * will be cleared when the flag is set + */ + if (rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412)) + return -EIO; + DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); @@ -174,50 +173,38 @@ static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) if (tmp->tm_year < 1970 || tmp->tm_year > 2069) printf("WARNING: year should be between 1970 and 2069!\n"); - if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100))) - return -EIO; - - if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon))) - return -EIO; - - if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday))) - return -EIO; - - if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday))) - return -EIO; + write_op[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec); + write_op[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min); + write_op[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour); + write_op[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday); + write_op[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday); + write_op[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon); + write_op[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100); + write_op[RTC_OFFSET_REG_ADDR] = 0; - if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour))) - return -EIO; - - if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min))) - return -EIO; - - if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec))) - return -EIO; - - return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); + return dm_i2c_write(dev, 0, &write_op[0], 8); } /* * Reset the RTC */ -static int rx8025_rtc_reset(DEV_TYPE *dev) +static int rx8025_rtc_reset(struct udevice *dev) { uchar buf[16]; uchar ctl2; -#ifdef CONFIG_DM_RTC if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { -#else - if (i2c_read(dev->chip, 0, 0, buf, 16)) { -#endif printf("Error reading from RTC\n"); return -EIO; } ctl2 = rtc_read(RTC_CTL2_REG_ADDR); ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); - ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; + + if (dev->driver_data == model_rx_8035) + ctl2 &= ~(RTC_CTL2_BIT_XST); + else + ctl2 |= RTC_CTL2_BIT_XST; return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2); } @@ -225,17 +212,16 @@ static int rx8025_rtc_reset(DEV_TYPE *dev) /* * Helper functions */ -static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) +static int rtc_write(struct udevice *dev, uchar reg, uchar val) { - uchar buf[2]; - buf[0] = reg << 4; - buf[1] = val; - -#ifdef CONFIG_DM_RTC - if (dm_i2c_write(dev, 0, buf, 2)) { -#else - if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) { -#endif + /* The RX8025/RX8035 uses the top 4 bits of the + * 'offset' byte as the start register address, + * and the bottom 4 bits as a 'transfer' mode setting + * (only applicable for reads) + */ + u8 offset = (reg << 4); + + if (dm_i2c_reg_write(dev, offset, val)) { printf("Error writing to RTC\n"); return -EIO; } @@ -243,7 +229,6 @@ static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) return 0; } -#ifdef CONFIG_DM_RTC static int rx8025_probe(struct udevice *dev) { uchar buf[16]; @@ -265,42 +250,15 @@ static const struct rtc_ops rx8025_rtc_ops = { }; static const struct udevice_id rx8025_rtc_ids[] = { - { .compatible = "epson,rx8025" }, + { .compatible = "epson,rx8025", .data = model_rx_8025 }, + { .compatible = "epson,rx8035", .data = model_rx_8035 }, { } }; -U_BOOT_DRIVER(rx8010sj_rtc) = { +U_BOOT_DRIVER(rx8025_rtc) = { .name = "rx8025_rtc", .id = UCLASS_RTC, .probe = rx8025_probe, .of_match = rx8025_rtc_ids, .ops = &rx8025_rtc_ops, }; -#else -int rtc_get(struct rtc_time *tm) -{ - struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, - }; - - return rx8025_rtc_get(&dev, tm); -} - -int rtc_set(struct rtc_time *tm) -{ - struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, - }; - - return rx8025_rtc_set(&dev, tm); -} - -void rtc_reset(void) -{ - struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, - }; - - rx8025_rtc_reset(&dev); -} -#endif diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index 6fc5f4a9f9c012ed722b6e0e7a4c234548af0a63..e9f848636c6ee4894656985acc852affdddb01fc 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_SCSI) += scsi.o endif ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_SATA_SUPPORT +ifdef CONFIG_SPL_SATA obj-$(CONFIG_DM_SCSI) += scsi-uclass.o obj-$(CONFIG_SCSI) += scsi.o endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 93348c0929cf52d2008b9be555a722a8c04b1321..3bb5b02eabb3e6d637303c87d0eb374f504f36fc 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -2,7 +2,18 @@ # Serial device configuration # -menu "Serial drivers" +menuconfig SERIAL + bool "Serial" + default y + help + Enable support for serial drivers. This allows use of a serial UART + for displaying messages while U-Boot is running. It also brings in + printf() and panic() functions. This should normally be enabled + unless there are space reasons not to. If you just need to disable + the console you can adjust the stdout environment variable or use + SILENT_CONSOLE. + +if SERIAL config BAUDRATE int "Default baudrate" @@ -137,7 +148,6 @@ config SERIAL_SEARCH_ALL config SERIAL_PROBE_ALL bool "Probe all available serial devices" depends on DM_SERIAL - default n help The serial subsystem only probes for a single serial device, but does not probe for other remaining serial devices. @@ -621,7 +631,6 @@ config FSL_LPUART config MVEBU_A3700_UART bool "UART support for Armada 3700" - default n help Choose this option to add support for UART driver on the Marvell Armada 3700 SoC. The base address is configured via DT. @@ -636,8 +645,7 @@ config MCFUART config MXC_UART bool "IMX serial port support" - depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \ - || MX5 || MX6 || MX7 || IMX8M + depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. @@ -939,4 +947,4 @@ config SYS_SDMR depends on MPC8XX_CONS default 0 -endmenu +endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index cc121eee277d8696c800542f6b9f8592fcb55323..796ff1658cd05d2e7e95cf801449bb8c4eaace2d 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif /* !CONFIG_DM_SERIAL */ -#if defined(CONFIG_SOC_KEYSTONE) +#if defined(CONFIG_ARCH_KEYSTONE) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) #undef UART_MCRVAL @@ -267,7 +267,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif -#if defined(CONFIG_SOC_KEYSTONE) +#if defined(CONFIG_ARCH_KEYSTONE) serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); #endif } @@ -533,7 +533,7 @@ enum { }; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int ns16550_serial_of_to_plat(struct udevice *dev) { struct ns16550_plat *plat = dev_get_plat(dev); @@ -588,7 +588,7 @@ const struct dm_serial_ops ns16550_serial_ops = { .getinfo = ns16550_serial_getinfo, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /* * Please consider existing compatible strings before adding a new * one to keep this table compact. Or you may add a generic "ns16550" @@ -602,7 +602,7 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, {} }; -#endif /* OF_CONTROL && !OF_PLATDATA */ +#endif /* OF_REAL */ #if CONFIG_IS_ENABLED(SERIAL_PRESENT) @@ -611,7 +611,7 @@ static const struct udevice_id ns16550_serial_ids[] = { U_BOOT_DRIVER(ns16550_serial) = { .name = "ns16550_serial", .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = ns16550_serial_ids, .of_to_plat = ns16550_serial_of_to_plat, .plat_auto = sizeof(struct ns16550_plat), diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index 5243c955fbf41c273905e4368aeecb8a6268e169..dbbcea5bb4db8d64526db7543089aaa22c1f946f 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -237,7 +237,7 @@ U_BOOT_DRIVER(sandbox_serial) = { .flags = DM_FLAG_PRE_RELOC, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct sandbox_serial_plat platdata_non_fdt = { .colour = -1, }; diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 8171b17faf88ccba60deb759e16973ac8f089d45..57a784844150b6377b2df8561a0a01628c39a60b 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; */ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; -#if !CONFIG_VAL(SYS_MALLOC_F_LEN) -#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work" -#endif - #if CONFIG_IS_ENABLED(SERIAL_PRESENT) static int serial_check_stdout(const void *blob, struct udevice **devp) { diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index ac4d0824b9843af7a6000605eec0f62a1f85ad4c..a22623c316ed12a65817d4964d1c2a3578d52b6b 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -233,7 +233,7 @@ static int msm_serial_of_to_plat(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE); return 0; diff --git a/drivers/serial/serial_mt7620.c b/drivers/serial/serial_mt7620.c index 826a14b49f8b95ccf905dfda915ef017e9df77ef..76ecc2b38ce6e7c8e63aa9178a36e3f61bcdc529 100644 --- a/drivers/serial/serial_mt7620.c +++ b/drivers/serial/serial_mt7620.c @@ -145,7 +145,7 @@ static int mt7620_serial_probe(struct udevice *dev) return 0; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mt7620_serial_of_to_plat(struct udevice *dev) { struct mt7620_serial_plat *plat = dev_get_plat(dev); @@ -200,7 +200,7 @@ static const struct dm_serial_ops mt7620_serial_ops = { U_BOOT_DRIVER(serial_mt7620) = { .name = "serial_mt7620", .id = UCLASS_SERIAL, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mt7620_serial_ids, .of_to_plat = mt7620_serial_of_to_plat, #endif diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 2b23ece442e5e6c4ded4fa168548622c207c9a34..ee938f67632b5f3e41b93361fd3ee0133f0f26d2 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -98,7 +98,7 @@ DEBUG_UART_FUNCS #if CONFIG_IS_ENABLED(DM_SERIAL) -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int omap_serial_of_to_plat(struct udevice *dev) { struct ns16550_plat *plat = dev_get_plat(dev); @@ -149,13 +149,13 @@ static const struct udevice_id omap_serial_ids[] = { { .compatible = "ti,am654-uart", }, {} }; -#endif /* OF_CONTROL && !OF_PLATDATA */ +#endif /* OF_REAL */ #if CONFIG_IS_ENABLED(SERIAL_PRESENT) U_BOOT_DRIVER(omap_serial) = { .name = "omap_serial", .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_serial_ids, .of_to_plat = omap_serial_of_to_plat, .plat_auto = sizeof(struct ns16550_plat), diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index 2cada4efbfc12e3335cc9f1132698a9de4306c15..40381b57b08e4188925d113d89b570a0620b0fcd 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -209,4 +209,3 @@ U_BOOT_DRIVER(serial_sti_asc) = { .probe = sti_asc_serial_probe, .priv_auto = sizeof(struct sti_asc_serial), }; - diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index e1d5b229bd7de123d9e7be7b8d3daf5cb4dd3379..ab318b06462bfd724bf010f4f94511b68c8b4c13 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -180,4 +180,3 @@ U_BOOT_DRIVER(serial_xen) = { .flags = DM_FLAG_PRE_RELOC, #endif }; - diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index fadc9f39657d45938be685e3e47fbde072a90c39..989679e881b5c28da24d45549a248fd34e913473 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -19,9 +19,7 @@ #define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) #define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) -#ifndef CONFIG_ALTERA_SPI_IDLE_VAL -#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff -#endif +#define ALTERA_SPI_IDLE_VAL 0xff struct altera_spi_regs { u32 rxdata; @@ -119,7 +117,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen, if (txp) data = *txp++; else - data = CONFIG_ALTERA_SPI_IDLE_VAL; + data = ALTERA_SPI_IDLE_VAL; debug("%s: tx:%x ", __func__, data); writel(data, ®s->txdata); diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 775b9ffc25955b97a50688dea3c91fa0125940a6..de9c14837cda8dc8bfb8df5dc2f7bcfffa7357c5 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -81,7 +81,7 @@ struct nds_spi_slave { unsigned int freq; ulong clock; unsigned int mode; - u8 num_cs; + u8 num_cs; unsigned int mtiming; size_t cmd_len; u8 cmd_buf[16]; diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 6511c0e0e541707bb853072f38fdc9d68e77c9e3..ea23357090fefbd9f2460a0b9c03631c96d343fa 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -384,7 +384,7 @@ static int coldfire_spi_probe(struct udevice *bus) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int coldfire_dspi_of_to_plat(struct udevice *bus) { fdt_addr_t addr; @@ -450,7 +450,7 @@ static const struct dm_spi_ops coldfire_spi_ops = { U_BOOT_DRIVER(coldfire_spi) = { .name = "spi_coldfire", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = coldfire_spi_ids, .of_to_plat = coldfire_dspi_of_to_plat, .plat_auto = sizeof(struct coldfire_spi_plat), diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 15557a62306a30c0e86120a11c829ab236e33880..0ee6171108a8772bbe4060f13c3ef3a09f05031b 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -391,7 +391,7 @@ static int davinci_spi_probe(struct udevice *bus) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int davinci_ofdata_to_platadata(struct udevice *bus) { struct davinci_spi_plat *plat = dev_get_plat(bus); @@ -418,7 +418,7 @@ static const struct udevice_id davinci_spi_ids[] = { U_BOOT_DRIVER(davinci_spi) = { .name = "davinci_spi", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = davinci_spi_ids, .of_to_plat = davinci_ofdata_to_platadata, .plat_auto = sizeof(struct davinci_spi_plat), diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 387b5471598ccce93d0f9445e4a730fbce0be819..c7a692623fb9d5a0d2ba1df68ee4f796dd9ee987 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -541,7 +541,7 @@ static const struct dm_spi_ops fsl_espi_ops = { .set_mode = fsl_espi_set_mode, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int fsl_espi_of_to_plat(struct udevice *bus) { fdt_addr_t addr; @@ -572,7 +572,7 @@ static const struct udevice_id fsl_espi_ids[] = { U_BOOT_DRIVER(fsl_espi) = { .name = "fsl_espi", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = fsl_espi_ids, .of_to_plat = fsl_espi_of_to_plat, #endif diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 08d54e86f45d7d27f57159adcb3a37002a2435e3..42071bb70c4ef1a519c6baba82d4edbe30cd2795 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -604,7 +604,7 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * ich_spi_get_basics() - Get basic information about the ICH device * @@ -672,7 +672,7 @@ static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep, uint *map_sizep, uint *offsetp) { pci_dev_t spi_bdf; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) if (device_is_on_pci_bus(bus)) { struct pci_child_plat *pplat; @@ -940,7 +940,7 @@ static int ich_spi_of_to_plat(struct udevice *dev) { struct ich_spi_plat *plat = dev_get_plat(dev); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct ich_spi_priv *priv = dev_get_priv(dev); int ret; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index a80c3e737dbd32ff4a96fd7e9f07b8d1805db618..3c53de165dd6e12621a85d55bb444227e0407b31 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; /* MX35 and older is CSPI */ -#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35) +#if defined(CONFIG_MX31) #define MXC_CSPI struct cspi_regs { u32 rxdata; @@ -48,17 +48,10 @@ struct cspi_regs { #define MXC_CSPICTRL_RXOVF BIT(6) #define MXC_CSPIPERIOD_32KHZ BIT(15) #define MAX_SPI_BYTES 4 -#if defined(CONFIG_MX25) || defined(CONFIG_MX35) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_TC BIT(7) -#define MXC_CSPICTRL_MAXBITS 0xfff -#else /* MX31 */ #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) #define MXC_CSPICTRL_TC BIT(8) #define MXC_CSPICTRL_MAXBITS 0x1f -#endif #else /* MX51 and newer is ECSPI */ #define MXC_ECSPI @@ -211,9 +204,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | MXC_CSPICTRL_DATARATE(div) | MXC_CSPICTRL_EN | -#ifdef CONFIG_MX35 - MXC_CSPICTRL_SSCTL | -#endif MXC_CSPICTRL_MODE; if (mode & SPI_CPHA) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index d41352a0bb8ce29d377dbe4dfa1a5ef14150e892..773e26bbed74ca3804986a3f960dd5fea2e57964 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -440,7 +440,7 @@ static const struct dm_spi_ops mxs_spi_ops = { */ }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mxs_of_to_plat(struct udevice *bus) { struct mxs_spi_plat *plat = dev_get_plat(bus); @@ -483,7 +483,7 @@ static const struct udevice_id mxs_spi_ids[] = { U_BOOT_DRIVER(fsl_imx23_spi) = { .name = "fsl_imx23_spi", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mxs_spi_ids, .of_to_plat = mxs_of_to_plat, #endif diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index c69f8fee6e5734f6162bb0f168450db18c9b844d..ea38a0ffbaf53eb33bffbe27cbcedd77f5477ca6 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -481,7 +481,7 @@ static const struct dm_spi_ops omap3_spi_ops = { */ }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static struct omap2_mcspi_platform_config omap2_pdata = { .regs_offset = 0, }; @@ -516,7 +516,7 @@ U_BOOT_DRIVER(omap3_spi) = { .name = "omap3_spi", .id = UCLASS_SPI, .flags = DM_FLAG_PRE_RELOC, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap3_spi_ids, .of_to_plat = omap3_spi_of_to_plat, .plat_auto = sizeof(struct omap3_spi_plat), diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index 9856a5669ca134e46347e8b7ca2911d442d92af5..ea1691438be6efd9a1235807d97b4872dd3e27ac 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -286,7 +286,7 @@ static const struct dm_spi_ops pl022_spi_ops = { .cs_info = pl022_cs_info, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int pl022_spi_of_to_plat(struct udevice *bus) { struct pl022_spi_pdata *plat = dev_get_plat(bus); @@ -315,7 +315,7 @@ static const struct udevice_id pl022_spi_ids[] = { U_BOOT_DRIVER(pl022_spi) = { .name = "pl022_spi", .id = UCLASS_SPI, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = pl022_spi_ids, .of_to_plat = pl022_spi_of_to_plat, #endif diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 40bd8851b7c071ec6de2c777ebc1b931d21f40f5..cb80be77ae9fc04910f460f95140336e4b20db2f 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -183,7 +183,7 @@ static int conv_of_plat(struct udevice *dev) plat->base = dtplat->reg[0]; plat->frequency = 20000000; - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); if (ret < 0) return ret; @@ -193,31 +193,31 @@ static int conv_of_plat(struct udevice *dev) static int rockchip_spi_of_to_plat(struct udevice *bus) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_spi_plat *plat = dev_get_plat(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); int ret; - plat->base = dev_read_addr(bus); + if (CONFIG_IS_ENABLED(OF_REAL)) { + plat->base = dev_read_addr(bus); - ret = clk_get_by_index(bus, 0, &priv->clk); - if (ret < 0) { - debug("%s: Could not get clock for %s: %d\n", __func__, - bus->name, ret); - return ret; - } + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) { + debug("%s: Could not get clock for %s: %d\n", __func__, + bus->name, ret); + return ret; + } - plat->frequency = - dev_read_u32_default(bus, "spi-max-frequency", 50000000); - plat->deactivate_delay_us = - dev_read_u32_default(bus, "spi-deactivate-delay", 0); - plat->activate_delay_us = - dev_read_u32_default(bus, "spi-activate-delay", 0); + plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", + 50000000); + plat->deactivate_delay_us = + dev_read_u32_default(bus, "spi-deactivate-delay", 0); + plat->activate_delay_us = + dev_read_u32_default(bus, "spi-activate-delay", 0); - debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", - __func__, (uint)plat->base, plat->frequency, - plat->deactivate_delay_us); -#endif + debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", + __func__, (uint)plat->base, plat->frequency, + plat->deactivate_delay_us); + } return 0; } diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index d867b278064f3f0dbaca04fd77cd8f0ab69016a2..f8ec312d715235669bf659bb7ead0188b6249ea1 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -162,7 +162,7 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); @@ -176,11 +176,11 @@ static int spi_child_post_bind(struct udevice *dev) static int spi_post_probe(struct udevice *bus) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct dm_spi_bus *spi = dev_get_uclass_priv(bus); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct dm_spi_bus *spi = dev_get_uclass_priv(bus); - spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); -#endif + spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + } #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_spi_ops *ops = spi_get_ops(bus); static int reloc_done; @@ -531,7 +531,7 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif .post_probe = spi_post_probe, @@ -539,7 +539,7 @@ UCLASS_DRIVER(spi) = { .per_device_auto = sizeof(struct dm_spi_bus), .per_child_auto = sizeof(struct spi_slave), .per_child_plat_auto = sizeof(struct dm_spi_slave_plat), -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .child_post_bind = spi_child_post_bind, #endif }; diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 08685823e99dffe0f1eca3a6156a687ba5a79b41..0ee286cbb34f1f44f6b2565227e80ce4d85164c5 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -133,7 +133,7 @@ U_BOOT_DRIVER(warm_sysreset_sandbox) = { .ops = &sandbox_warm_sysreset_ops, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /* This is here in case we don't have a device tree */ U_BOOT_DRVINFO(sysreset_sandbox_non_fdt) = { .name = "sysreset_sandbox", diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index 07766baf45a13df91a79e3cf05e0c8fb625a5da1..ca45abbb8e1d9b5c891cf19af24767c708592c38 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -22,8 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SITES_MAX 16 -#define FLAGS_VER2 0x1 -#define FLAGS_VER3 0x2 +#define FLAGS_VER2 0x1 +#define FLAGS_VER3 0x2 #define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c index 3178e58884afdc87623fad33043868e4d7bce211..5cf46f224ab00206283c9b55d65c15ade2172c5f 100644 --- a/drivers/timer/atmel_pit_timer.c +++ b/drivers/timer/atmel_pit_timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017 Microchip Corporation - * Wenyou.Yang <wenyou.yang@microchip.com> + * Wenyou.Yang <wenyou.yang@microchip.com> */ #include <common.h> diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 18c61450aff59a8677554ae2508187cbb92fd9e6..62eacb9868907dc391fc87bd137b00dc42d4348e 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -55,8 +55,7 @@ ulong timer_get_boot_us(void) /* The timer is available */ rate = timer_get_rate(gd->timer); timer_get_count(gd->timer, &ticks); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - } else if (ret == -EAGAIN) { + } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) { /* We have been called so early that the DM is not ready,... */ ofnode node = offset_to_ofnode(-1); struct rk_timer *timer = NULL; @@ -79,7 +78,6 @@ ulong timer_get_boot_us(void) debug("%s: could not read clock-frequency\n", __func__); return 0; } -#endif } else { return 0; } @@ -100,13 +98,13 @@ static u64 rockchip_timer_get_count(struct udevice *dev) static int rockchip_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rockchip_timer_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rockchip_timer_priv *priv = dev_get_priv(dev); - priv->timer = dev_read_addr_ptr(dev); - if (!priv->timer) - return -ENOENT; -#endif + priv->timer = dev_read_addr_ptr(dev); + if (!priv->timer) + return -ENOENT; + } return 0; } diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index e34f5202fc6804950bb8a4bbbca7c5af3e346b9f..f07251e54c018ecd61d926792c0e4a77fc96a2a3 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -135,4 +135,3 @@ U_BOOT_DRIVER(stm32_timer) = { .probe = stm32_timer_probe, .ops = &stm32_timer_ops, }; - diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index c8e8419b22e789a47bf218ef20310f4481c5616e..6ea9e39e126c517a5c9d734eb02fa18c9127ba26 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -50,27 +50,29 @@ unsigned long notrace timer_get_rate(struct udevice *dev) static int timer_pre_probe(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct clk timer_clk; - int err; - ulong ret; + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk timer_clk; + int err; + ulong ret; - /* It is possible that a timer device has a null ofnode */ - if (!dev_has_ofnode(dev)) - return 0; + /* + * It is possible that a timer device has a null ofnode + */ + if (!dev_has_ofnode(dev)) + return 0; - err = clk_get_by_index(dev, 0, &timer_clk); - if (!err) { - ret = clk_get_rate(&timer_clk); - if (IS_ERR_VALUE(ret)) - return ret; - uc_priv->clock_rate = ret; - } else { - uc_priv->clock_rate = - dev_read_u32_default(dev, "clock-frequency", 0); + err = clk_get_by_index(dev, 0, &timer_clk); + if (!err) { + ret = clk_get_rate(&timer_clk); + if (IS_ERR_VALUE(ret)) + return ret; + uc_priv->clock_rate = ret; + } else { + uc_priv->clock_rate = + dev_read_u32_default(dev, "clock-frequency", 0); + } } -#endif return 0; } @@ -136,23 +138,23 @@ int notrace dm_timer_init(void) if (gd->dm_root == NULL) return -EAGAIN; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - /* Check for a chosen timer to be used for tick */ - node = ofnode_get_chosen_node("tick-timer"); - - if (ofnode_valid(node) && - uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { - /* - * If the timer is not marked to be bound before - * relocation, bind it anyway. - */ - if (!lists_bind_fdt(dm_root(), node, &dev, false)) { - ret = device_probe(dev); - if (ret) - return ret; + if (CONFIG_IS_ENABLED(OF_REAL)) { + /* Check for a chosen timer to be used for tick */ + node = ofnode_get_chosen_node("tick-timer"); + + if (ofnode_valid(node) && + uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { + /* + * If the timer is not marked to be bound before + * relocation, bind it anyway. + */ + if (!lists_bind_fdt(dm_root(), node, &dev, false)) { + ret = device_probe(dev); + if (ret) + return ret; + } } } -#endif if (!dev) { /* Fall back to the first available timer */ diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index adef50c37440dacbeebe4e954f6a906405eb457a..192c7b71a5a386f6d7d62e47ca170b9747f90eff 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -479,7 +479,7 @@ static const struct timer_ops tsc_timer_ops = { .get_count = tsc_timer_get_count, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id tsc_timer_ids[] = { { .compatible = "x86,tsc-timer", }, { } diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index 35774a6289e986f38ed90c38b57ab233d41adc1e..f67fe1019b2ec63670958dde66f2cba6659c36eb 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -140,7 +140,7 @@ UCLASS_DRIVER(tpm) = { .id = UCLASS_TPM, .name = "tpm", .flags = DM_UC_FLAG_SEQ_ALIAS, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif .per_device_auto = sizeof(struct tpm_chip_priv), diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 4b33ac8fd3d953df7516da905d1733c10658143f..1d24d32d867e58f13a01f91744ee5f0fc3c089e4 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -589,18 +589,25 @@ static int tpm_tis_spi_probe(struct udevice *dev) if (CONFIG_IS_ENABLED(DM_GPIO)) { struct gpio_desc reset_gpio; - ret = gpio_request_by_name(dev, "gpio-reset", 0, + ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset_gpio, GPIOD_IS_OUT); if (ret) { - log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n", - __func__); - } else { - dm_gpio_set_value(&reset_gpio, 1); - mdelay(1); - dm_gpio_set_value(&reset_gpio, 0); + /* legacy reset */ + ret = gpio_request_by_name(dev, "gpio-reset", 0, + &reset_gpio, GPIOD_IS_OUT); + if (ret) { + log(LOGC_NONE, LOGL_NOTICE, + "%s: missing reset GPIO\n", __func__); + goto init; + } + log(LOGC_NONE, LOGL_NOTICE, + "%s: gpio-reset is deprecated\n", __func__); } + dm_gpio_set_value(&reset_gpio, 1); + mdelay(1); + dm_gpio_set_value(&reset_gpio, 0); } - +init: /* Ensure a minimum amount of time elapsed since reset of the TPM */ mdelay(drv_data->time_before_first_cmd_ms); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 44533fd7fed44491304f248697bd471ff6fe31bf..1502cb859a5b7c6d0916fff3118a280139726da0 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -691,8 +691,8 @@ struct dwc3_scratchpad_array { * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that * there's now way for software to detect this in runtime. * @is_utmi_l1_suspend: the core asserts output signal - * 0 - utmi_sleep_n - * 1 - utmi_l1_suspend_n + * 0 - utmi_sleep_n + * 1 - utmi_l1_suspend_n * @is_selfpowered: true when we are selfpowered * @is_fpga: true when we are using the FPGA board * @needs_fifo_resize: not all users might want fifo resizing, flag it @@ -713,10 +713,10 @@ struct dwc3_scratchpad_array { * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk * @tx_de_emphasis: Tx de-emphasis value - * 0 - -6dB de-emphasis - * 1 - -3.5dB de-emphasis - * 2 - No de-emphasis - * 3 - Reserved + * 0 - -6dB de-emphasis + * 1 - -3.5dB de-emphasis + * 2 - No de-emphasis + * 3 - Reserved * @index: index of _this_ controller * @list: to maintain the list of dwc3 controllers */ diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 08467d6210b688726870ab17bdf7700d5dce567b..7c26290c15c44bb4f2f0383ed4859194abfddccc 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -170,7 +170,7 @@ static int dwc3_meson_gxl_usb2_init(struct dwc3_meson_gxl *priv) static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv) { int ret; - + ret = dwc3_meson_gxl_usb2_init(priv); if (ret) return ret; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 4e68fb0a82f0d66525873b82e6e5906e73412c73..eb416b832aad53704e0b2597231eb2627cfdf365 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2209,7 +2209,7 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) * BESL value in the LPM token is less than or equal to LPM * NYET threshold. */ - if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum) + if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum) WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 4677da9f29311818b1cc548d5f905204c844d280..d21fc682b03cf027a59a8ce633d48dc3d0abcba8 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -1894,4 +1894,3 @@ static const struct usb_device_id r8152_eth_id_table[] = { U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); #endif /* CONFIG_DM_ETH */ - diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h index 668b8c4a7c63fc83b106af16dc4c55f0288ce6ad..e18de0e2f0cc8d264b82d24af355b84aefe288ee 100644 --- a/drivers/usb/gadget/at91_udc.h +++ b/drivers/usb/gadget/at91_udc.h @@ -35,7 +35,7 @@ #define AT91_UDP_ISR 0x1c /* Interrupt Status Register */ #define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */ -#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ +#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ #define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */ #define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */ #define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */ @@ -164,4 +164,3 @@ struct at91_request { #define DBG(stuff...) debug("udc: " stuff) #endif - diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c index bd846ce9a77bbc57f35ba9150697e38150593c5c..98a7ffa2a752cac0db3cc4c5e5c1010e28c8b578 100644 --- a/drivers/usb/gadget/f_rockusb.c +++ b/drivers/usb/gadget/f_rockusb.c @@ -17,7 +17,6 @@ #include <linux/usb/gadget.h> #include <linux/usb/composite.h> #include <linux/compiler.h> -#include <version.h> #include <g_dnl.h> #include <asm/arch-rockchip/f_rockusb.h> diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index ba362b8f2582a59582b9a1cb6d1b6692c4eacf65..583ceb4d55c62cff7ad9ba14aa6bc36ac709d571 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -472,7 +472,7 @@ void udc_irq(void) * so using '|=' isn't safe as it may ack an interrupt. */ #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) +#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) static inline void udc_set_mask_UDCCR(int mask) { diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 427b360af182fca323c78545d08cfe0110d3303c..10b0479a8a6a81a581d5286f913d92bb376b9e42 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -57,6 +57,16 @@ config USB_XHCI_OCTEON family SoCs. This is a driver for the dwc3 to provide the glue logic to configure the controller. +config USB_XHCI_OMAP + bool "Support for TI OMAP family xHCI USB controller" + depends on ARCH_OMAP2PLUS + help + Enables support for the on-chip xHCI controller found on some TI SoC + families. Note that some families have multiple contollers while + others only have something such as DesignWare-based controllers. + Consult the SoC documentation to determine if this option applies + to your hardware. + config USB_XHCI_PCI bool "Support for PCI-based xHCI USB controller" depends on DM_USB @@ -146,7 +156,6 @@ config USB_EHCI_MARVELL config USB_EHCI_MX5 bool "Support for i.MX5 on-chip EHCI USB controller" depends on ARCH_MX5 - default n help Enables support for the on-chip EHCI controller on i.MX5 SoCs. @@ -174,6 +183,40 @@ config USB_EHCI_OMAP Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. +if USB_EHCI_OMAP + +config HAS_OMAP_EHCI_PHY1_RESET_GPIO + bool "PHY #1 requires a GPIO hold to it in RESET while PHY settles" + help + Enable this to be able to configure the GPIO number used to hold the + PHY in RESET for enough time until the PHY is settled and ready. + +config OMAP_EHCI_PHY1_RESET_GPIO + int "GPIO number to hold PHY #1 in RESET" + depends on HAS_OMAP_EHCI_PHY1_RESET_GPIO + +config HAS_OMAP_EHCI_PHY2_RESET_GPIO + bool "PHY #2 requires a GPIO hold to it in RESET while PHY settles" + help + Enable this to be able to configure the GPIO number used to hold the + PHY in RESET for enough time until the PHY is settled and ready. + +config OMAP_EHCI_PHY2_RESET_GPIO + int "GPIO number to hold PHY #2 in RESET" + depends on HAS_OMAP_EHCI_PHY2_RESET_GPIO + +config HAS_OMAP_EHCI_PHY3_RESET_GPIO + bool "PHY #3 requires a GPIO hold to it in RESET while PHY settles" + help + Enable this to be able to configure the GPIO number used to hold the + PHY in RESET for enough time until the PHY is settled and ready. + +config OMAP_EHCI_PHY3_RESET_GPIO + int "GPIO number to hold PHY #3 in RESET" + depends on HAS_OMAP_EHCI_PHY3_RESET_GPIO + +endif + config USB_EHCI_VF bool "Support for Vybrid on-chip EHCI USB controller" depends on ARCH_VF610 @@ -195,7 +238,6 @@ config USB_EHCI_MSM depends on DM_USB select USB_ULPI_VIEWPORT select MSM8916_USB_PHY - default n ---help--- Enables support for the on-chip EHCI controller on Qualcomm Snapdragon SoCs. @@ -222,13 +264,11 @@ config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on DM_USB default ARCH_SUNXI - default n ---help--- Enables support for generic EHCI controller. config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" - default n select CONFIG_EHCI_HCD_INIT_AFTER_RESET ---help--- Enables support for the on-chip EHCI controller on FSL chips. diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 43cc2e04339cd895d6564d1a4fe7520340bd82ec..23060fc369c0c418faefdf551fbb872700b742c8 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -86,14 +86,14 @@ static void init_fslspclksel(struct dwc2_core_regs *regs) { uint32_t phyclk; -#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) +#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ #else /* High speed PHY running at full speed or high speed */ phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; #endif -#ifdef CONFIG_DWC2_ULPI_FS_LS +#ifdef DWC2_ULPI_FS_LS uint32_t hwcfg2 = readl(®s->ghwcfg2); uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; @@ -257,28 +257,28 @@ static void dwc_otg_core_host_init(struct udevice *dev, /* Initialize Host Configuration Register */ init_fslspclksel(regs); -#ifdef CONFIG_DWC2_DFLT_SPEED_FULL +#ifdef DWC2_DFLT_SPEED_FULL setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); #endif /* Configure data FIFO sizes */ -#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO +#ifdef DWC2_ENABLE_DYNAMIC_FIFO if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { /* Rx FIFO */ - writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); + writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); /* Non-periodic Tx FIFO */ - nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << + nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET; - nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << + nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE << DWC2_FIFOSIZE_STARTADDR_OFFSET; writel(nptxfifosize, ®s->gnptxfsiz); /* Periodic Tx FIFO */ - ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << + ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET; - ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + - CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << + ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE + + DWC2_HOST_NPERIO_TX_FIFO_SIZE) << DWC2_FIFOSIZE_STARTADDR_OFFSET; writel(ptxfifosize, ®s->hptxfsiz); } @@ -340,7 +340,7 @@ static void dwc_otg_core_init(struct udevice *dev) struct dwc2_core_regs *regs = priv->regs; uint32_t ahbcfg = 0; uint32_t usbcfg = 0; - uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; + uint8_t brst_sz = DWC2_DMA_BURST_SIZE; /* Common Initialization */ usbcfg = readl(®s->gusbcfg); @@ -357,7 +357,7 @@ static void dwc_otg_core_init(struct udevice *dev) } /* Set external TS Dline pulsing */ -#ifdef CONFIG_DWC2_TS_DLINE +#ifdef DWC2_TS_DLINE usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; #else usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; @@ -371,8 +371,8 @@ static void dwc_otg_core_init(struct udevice *dev) * This programming sequence needs to happen in FS mode before * any other programming occurs */ -#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ - (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) +#if defined(DWC2_DFLT_SPEED_FULL) && \ + (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) /* If FS mode with FS PHY */ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); @@ -387,7 +387,7 @@ static void dwc_otg_core_init(struct udevice *dev) if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) init_fslspclksel(regs); -#ifdef CONFIG_DWC2_I2C_ENABLE +#ifdef DWC2_I2C_ENABLE /* Program GUSBCFG.OtgUtmifsSel to I2C */ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); @@ -407,16 +407,16 @@ static void dwc_otg_core_init(struct udevice *dev) * immediately after setting phyif. */ usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); - usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; + usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ -#ifdef CONFIG_DWC2_PHY_ULPI_DDR +#ifdef DWC2_PHY_ULPI_DDR usbcfg |= DWC2_GUSBCFG_DDRSEL; #else usbcfg &= ~DWC2_GUSBCFG_DDRSEL; #endif } else { /* UTMI+ interface */ -#if (CONFIG_DWC2_UTMI_WIDTH == 16) +#if (DWC2_UTMI_WIDTH == 16) usbcfg |= DWC2_GUSBCFG_PHYIF; #endif } @@ -429,7 +429,7 @@ static void dwc_otg_core_init(struct udevice *dev) usbcfg = readl(®s->gusbcfg); usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); -#ifdef CONFIG_DWC2_ULPI_FS_LS +#ifdef DWC2_ULPI_FS_LS uint32_t hwcfg2 = readl(®s->ghwcfg2); uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; @@ -456,14 +456,14 @@ static void dwc_otg_core_init(struct udevice *dev) brst_sz >>= 1; } -#ifdef CONFIG_DWC2_DMA_ENABLE +#ifdef DWC2_DMA_ENABLE ahbcfg |= DWC2_GAHBCFG_DMAENABLE; #endif break; case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; -#ifdef CONFIG_DWC2_DMA_ENABLE +#ifdef DWC2_DMA_ENABLE ahbcfg |= DWC2_GAHBCFG_DMAENABLE; #endif break; @@ -476,7 +476,7 @@ static void dwc_otg_core_init(struct udevice *dev) if (!priv->hnp_srp_disable) usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; -#ifdef CONFIG_DWC2_IC_USB_CAP +#ifdef DWC2_IC_USB_CAP usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; #endif @@ -939,9 +939,9 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, in, len); - max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; - if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) - max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; + max_xfer_len = DWC2_MAX_PACKET_COUNT * max; + if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE) + max_xfer_len = DWC2_MAX_TRANSFER_SIZE; if (max_xfer_len > DWC2_DATA_BUF_SIZE) max_xfer_len = DWC2_DATA_BUF_SIZE; @@ -1198,7 +1198,7 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) return -ENODEV; } -#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS +#ifdef DWC2_PHY_ULPI_EXT_VBUS priv->ext_vbus = 1; #else priv->ext_vbus = 0; diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 97a06c48f21660569e255b2e8097a79c7d604a42..a6f562fe60e25f03d29ee0cf669ec5aaa6a52b3d 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -759,32 +759,32 @@ struct dwc2_core_regs { #define RH_B_PPCM 0xffff0000 /* port power control mask */ /* Default driver configuration */ -#define CONFIG_DWC2_DMA_ENABLE -#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ -#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ -#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ -#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) -#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ -#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ -#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535 -#define CONFIG_DWC2_MAX_PACKET_COUNT 511 +#define DWC2_DMA_ENABLE +#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ +#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ +#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ +#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */ +#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS) +#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ +#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ +#define DWC2_MAX_TRANSFER_SIZE 65535 +#define DWC2_MAX_PACKET_COUNT 511 #define DWC2_PHY_TYPE_FS 0 #define DWC2_PHY_TYPE_UTMI 1 #define DWC2_PHY_TYPE_ULPI 2 -#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ -#ifndef CONFIG_DWC2_UTMI_WIDTH -#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ +#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +#ifndef DWC2_UTMI_WIDTH +#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ #endif -#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ -#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ -#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ -#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ -#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ -#undef CONFIG_DWC2_THR_CTL /* Threshold control */ -#define CONFIG_DWC2_TX_THR_LENGTH 64 -#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ +#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ +#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ +#undef DWC2_I2C_ENABLE /* Enable I2C */ +#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */ +#undef DWC2_TS_DLINE /* External DLine pulsing */ +#undef DWC2_THR_CTL /* Threshold control */ +#define DWC2_TX_THR_LENGTH 64 +#undef DWC2_IC_USB_CAP /* IC Cap */ #endif /* __DWC2_H__ */ diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index d0b7ac512e804783e5e11ed9f7f514693b38e01e..1fb685e58d80f32f84e6dd8d0fc9b9522c94c877 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -67,56 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) unsigned int v; v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); -#if defined(CONFIG_MX25) - switch (port) { - case 0: /* OTG port */ - v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | - MX25_OTG_OCPOL_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_OTG_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_OTG_OCPOL_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | - MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | - MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | - MX25_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_H1_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_H1_OCPOL_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX25_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX25_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX25_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX25_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } -#elif defined(CONFIG_MX31) +#if defined(CONFIG_MX31) switch (port) { case 0: /* OTG port */ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); @@ -147,55 +98,6 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX31_H2_DT_BIT; - break; - default: - return -EINVAL; - } -#elif defined(CONFIG_MX35) - switch (port) { - case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | - MX35_OTG_OCPOL_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_OTG_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_OTG_OCPOL_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | - MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | - MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | - MX35_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_H1_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_H1_OCPOL_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX35_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX35_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX35_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX35_H1_IPPUE_UP_BIT; - break; default: return -EINVAL; @@ -230,10 +132,6 @@ int ehci_hcd_init(int index, enum usb_init_type init, setbits_le32(&ehci->usbmode, CM_HOST); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); -#ifdef CONFIG_MX35 - /* Workaround for ENGcm11601 */ - __raw_writel(0, &ehci->sbuscfg); -#endif udelay(10000); diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 12c422d811d18995cda4d717726a44f62c68c043..d5facf10e120a20f85deb7e94239f419a50b93d1 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -183,17 +183,8 @@ int omap_ehci_hcd_stop(void) * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 * See there for additional Copyrights. */ -#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL) - -int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); - *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); -#else int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata) { -#endif int ret; unsigned int i, reg = 0, rev = 0; @@ -304,8 +295,6 @@ int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata) return 0; } -#if CONFIG_IS_ENABLED(DM_USB) - static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -409,5 +398,3 @@ U_BOOT_DRIVER(usb_omap_ehci) = { .ops = &ehci_usb_ops, .flags = DM_FLAG_ALLOC_PRIV_DMA, }; - -#endif diff --git a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h index f0f48a3354c5751838e4d1b9f6be3ef71a6e9d07..8db88f0dcfa4273ee88199338ef6420d24ae6c71 100644 --- a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h +++ b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h @@ -40,7 +40,7 @@ * * To generate the content of the array below, use ie. the following command: * $ hexdump -v -e '/4 "0x%08x, "' r8a779x_usb3_v3.dlmem | \ - * sed "s@\(.\{47\}\) @\1\n@g" + * sed "s@\(.\{47\}\) @\1\n@g" * * [1] git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git */ diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index a9a7c2675ef1c6f302606a486cf59a4ebf5d2d71..6dd830cb73b21f0753da304f22fe7c051e3ebee2 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -34,7 +34,6 @@ config USB_MUSB_TI bool "Enable TI OTG USB controller" depends on AM33XX select USB_MUSB_DSPS - default n help Say y here to enable support for the dual role high speed USB controller based on the Mentor Graphics @@ -53,7 +52,6 @@ config USB_MUSB_DSPS config USB_MUSB_MT85XX bool "Enable Mediatek MT85XX DRC USB controller" depends on ARCH_MEDIATEK - default n help Say y to enable Mediatek MT85XX USB DRC controller support if it is available on your Mediatek MUSB IP based platform. diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index 5b149dac6dd67280b2b3b897e30403645dc0ed10..1fef00b292d6e75f1ad8d84d58752302956c9692 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -995,8 +995,8 @@ void musb_g_rx(struct musb *musb, u8 epnum) && (musb_ep->dma->actual_len == musb_ep->packet_sz)) { /* In double buffer case, continue to unload fifo if - * there is Rx packet in FIFO. - **/ + * there is Rx packet in FIFO. + **/ csr = musb_readw(epio, MUSB_RXCSR); if ((csr & MUSB_RXCSR_RXPKTRDY) && hw_ep->rx_double_buffered) diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index e9362f6def3300c641a30720734e5a13853decbc..9fd01fafdf7a15585d93eeef308b884a99149a8b 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -190,7 +190,7 @@ /* SUNXI has different reg addresses, but identical r/w functions */ -#ifndef CONFIG_ARCH_SUNXI +#ifndef CONFIG_ARCH_SUNXI /* * Common USB registers diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 8ac2f0a78adb9587b2e2c55e2271dd561932116e..61ff68def2faba53093e2e46832e1fd065a475b5 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -159,7 +159,7 @@ static struct int_queue *_musb_create_int_queue(struct musb_host_data *host, static int _musb_destroy_int_queue(struct musb_host_data *host, struct usb_device *dev, struct int_queue *queue) { - int index = usb_pipein(queue->urb.pipe) * 16 + + int index = usb_pipein(queue->urb.pipe) * 16 + usb_pipeendpoint(queue->urb.pipe); if (queue->urb.status == -EINPROGRESS) diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index e5d8ac7028827b0a5c1343e166bf125a3743b154..47b839c0835338bd5b7a3f7af8c50e2a05efc117 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -207,14 +207,14 @@ struct musb_regs { /* TxType/RxType */ #define MUSB_TYPE_SPEED 0xc0 #define MUSB_TYPE_SPEED_SHIFT 6 -#define MUSB_TYPE_SPEED_HIGH 1 -#define MUSB_TYPE_SPEED_FULL 2 +#define MUSB_TYPE_SPEED_HIGH 1 +#define MUSB_TYPE_SPEED_FULL 2 #define MUSB_TYPE_SPEED_LOW 3 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ #define MUSB_TYPE_PROTO_SHIFT 4 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ -#define MUSB_TYPE_PROTO_BULK 2 -#define MUSB_TYPE_PROTO_INTR 3 +#define MUSB_TYPE_PROTO_BULK 2 +#define MUSB_TYPE_PROTO_INTR 3 /* CONFIGDATA */ #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ @@ -304,7 +304,7 @@ struct musb_regs { * values are not supported */ struct musb_epinfo { - u8 epnum; /* endpoint number */ + u8 epnum; /* endpoint number */ u8 epdir; /* endpoint direction */ u16 epsize; /* endpoint FIFO size */ }; diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index afbc648883bc7df79a1148f95321094391622d5f..17901704f5212ee5ca0452979bee648d0e2b3b6f 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -14,7 +14,7 @@ #include "musb_hcd.h" /* MSC control transfers */ -#define USB_MSC_BBB_RESET 0xFF +#define USB_MSC_BBB_RESET 0xFF #define USB_MSC_BBB_GET_MAX_LUN 0xFE /* Endpoint configuration information */ @@ -327,7 +327,7 @@ static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) /* Set TXPKTRDY bit */ csr = readw(&musbr->txcsr); - + csr |= MUSB_CSR0_TXPKTRDY; csr |= MUSB_CSR0_H_DIS_PING; writew(csr, &musbr->txcsr); diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 8741553d09b2f8c2b746c8771cf694a980b72cb5..c505862f1e15ed1285fff8595e24508f70ccb575 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -8,8 +8,5 @@ comment "USB Phy" config TWL4030_USB bool "TWL4030 PHY" -config OMAP_USB_PHY - bool "OMAP PHY" - config ROCKCHIP_USB2_PHY bool "Rockchip USB2 PHY" diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 20f7edf48d74baa7b20a19c61cc7ae39c195294a..b67a70bbe8ed47b93f15d76caac09c504003bf0b 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -4,5 +4,4 @@ # Tom Rix <Tom.Rix@windriver.com> obj-$(CONFIG_TWL4030_USB) += twl4030.o -obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c deleted file mode 100644 index be733f39b23fa37c54786a9e85f2a28bc471e1e8..0000000000000000000000000000000000000000 --- a/drivers/usb/phy/omap_usb_phy.c +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * OMAP USB PHY Support - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * Author: Dan Murphy <dmurphy@ti.com> - */ - -#include <common.h> -#include <usb.h> -#include <dm/device_compat.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/omap_common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/sys_proto.h> - -#include <linux/compat.h> -#include <linux/usb/dwc3.h> -#include <linux/usb/xhci-omap.h> - -#include <usb/xhci.h> - -#ifdef CONFIG_OMAP_USB3PHY1_HOST -struct usb3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct usb3_dpll_map { - unsigned long rate; - struct usb3_dpll_params params; - struct usb3_dpll_map *dpll_map; -}; - -static struct usb3_dpll_map dpll_map_usb[] = { - {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ - {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ - {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ - {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ - {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ - {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -static struct usb3_dpll_params *omap_usb3_get_dpll_params(void) -{ - unsigned long rate; - struct usb3_dpll_map *dpll_map = dpll_map_usb; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); - - return NULL; -} - -static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) -{ - u32 val; - - writel(SET_PLL_GO, &phy_regs->pll_go); - do { - val = readl(&phy_regs->pll_status); - if (val & PLL_LOCK) - break; - } while (1); -} - -static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) -{ - struct usb3_dpll_params *dpll_params; - u32 val; - - dpll_params = omap_usb3_get_dpll_params(); - if (!dpll_params) - return; - - val = readl(&phy_regs->pll_config_1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - writel(val, &phy_regs->pll_config_1); - - val = readl(&phy_regs->pll_config_2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - writel(val, &phy_regs->pll_config_2); - - val = readl(&phy_regs->pll_config_1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - writel(val, &phy_regs->pll_config_1); - - val = readl(&phy_regs->pll_config_4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - writel(val, &phy_regs->pll_config_4); - - val = readl(&phy_regs->pll_config_3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - writel(val, &phy_regs->pll_config_3); - - omap_usb_dpll_relock(phy_regs); -} - -static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) -{ - u32 rate = get_sys_clk_freq()/1000000; - u32 val; - - val = readl((*ctrl)->control_phy_power_usb); - val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); - val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); - val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; - - writel(val, (*ctrl)->control_phy_power_usb); -} - -void usb_phy_power(int on) -{ - u32 val; - - val = readl((*ctrl)->control_phy_power_usb); - if (on) { - val &= ~USB3_PWRCTL_CLK_CMD_MASK; - val |= USB3_PHY_TX_RX_POWERON; - } else { - val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); - } - - writel(val, (*ctrl)->control_phy_power_usb); -} - -void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) -{ - omap_usb_dpll_lock(phy_regs); - usb3_phy_partial_powerup(phy_regs); - /* - * Give enough time for the PHY to partially power-up before - * powering it up completely. delay value suggested by the HW - * team. - */ - mdelay(100); -} - -static void omap_enable_usb3_phy(struct omap_xhci *omap) -{ - u32 val; - - val = (USBOTGSS_DMADISABLE | - USBOTGSS_STANDBYMODE_SMRT_WKUP | - USBOTGSS_IDLEMODE_NOIDLE); - writel(val, &omap->otg_wrapper->sysconfig); - - /* Clear the utmi OTG status */ - val = readl(&omap->otg_wrapper->utmi_otg_status); - writel(val, &omap->otg_wrapper->utmi_otg_status); - - /* Enable interrupts */ - writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0); - val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | - USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN | - USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN | - USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN | - USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN | - USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN | - USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN | - USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN | - USBOTGSS_IRQ_SET_1_OEVT_EN); - writel(val, &omap->otg_wrapper->irqenable_set_1); - - /* Clear the IRQ status */ - val = readl(&omap->otg_wrapper->irqstatus_1); - writel(val, &omap->otg_wrapper->irqstatus_1); - val = readl(&omap->otg_wrapper->irqstatus_0); - writel(val, &omap->otg_wrapper->irqstatus_0); -}; -#endif /* CONFIG_OMAP_USB3PHY1_HOST */ - -#ifdef CONFIG_OMAP_USB2PHY2_HOST -static void omap_enable_usb2_phy2(struct omap_xhci *omap) -{ - u32 reg, val; - - val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET); - writel(val, (*ctrl)->control_srcomp_north_side); - - setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, - (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K | - OTG_SS_CLKCTRL_MODULEMODE_HW)); - - /* This is an undocumented Reserved register */ - reg = 0x4a0086c0; - val = readl(reg); - val |= 0x100; - setbits_le32(reg, val); -} - -void usb_phy_power(int on) -{ - return; -} -#endif /* CONFIG_OMAP_USB2PHY2_HOST */ - -#ifdef CONFIG_AM437X_USB2PHY2_HOST -static void am437x_enable_usb2_phy2(struct omap_xhci *omap) -{ - const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN | - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - - writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL); - writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL); - - writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL); - writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL); -} - -void usb_phy_power(int on) -{ - u32 val; - - /* USB1_CTRL */ - val = readl(USB1_CTRL); - if (on) { - /* - * these bits are re-used on AM437x to power up/down the USB - * CM and OTG PHYs, if we don't toggle them, USB will not be - * functional on newer silicon revisions - */ - val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); - } else { - val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; - } - - writel(val, USB1_CTRL); -} -#endif /* CONFIG_AM437X_USB2PHY2_HOST */ - -void omap_enable_phy(struct omap_xhci *omap) -{ -#ifdef CONFIG_OMAP_USB2PHY2_HOST - omap_enable_usb2_phy2(omap); -#endif - -#ifdef CONFIG_AM437X_USB2PHY2_HOST - am437x_enable_usb2_phy2(omap); -#endif - -#ifdef CONFIG_OMAP_USB3PHY1_HOST - omap_enable_usb3_phy(omap); - omap_usb3_phy_init(omap->usb3_phy); -#endif -} diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8b940d70eb2122ca6e7b10b03419297092aac107..b1f8a9c1e6272fa2826906b900caf286543d54cf 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -259,7 +259,6 @@ config VIDEO_EFI config VIDEO_VESA bool "Enable VESA video driver support" - default n help Turn on this option to enable a very simple driver which uses vesa to discover the video mode and then provides a frame buffer for use @@ -406,7 +405,6 @@ config FRAMEBUFFER_VESA_MODE config VIDEO_LCD_ANX9804 bool "ANX9804 bridge chip" - default n ---help--- Support for the ANX9804 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fy into a DP @@ -416,7 +414,6 @@ config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" depends on DM_VIDEO select VIDEO_MIPI_DSI - default n help Say Y here if you want to enable support for Orise Technology otm8009a 480x800 dsi 2dl panel. @@ -425,14 +422,12 @@ config VIDEO_LCD_RAYDIUM_RM68200 bool "RM68200 DSI LCD panel support" depends on DM_VIDEO select VIDEO_MIPI_DSI - default n help Say Y here if you want to enable support for Raydium RM68200 720x1280 DSI video mode panel. config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" - default n ---help--- Support for the SSD2828 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fly into MIPI DSI @@ -463,14 +458,12 @@ config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" depends on DM_VIDEO select VIDEO_MIPI_DSI - default n help Say Y here if you want to enable support for TDO TL070WSH30 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - default n ---help--- Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is @@ -523,7 +516,6 @@ source "drivers/video/meson/Kconfig" config VIDEO_MVEBU bool "Armada XP LCD controller" - default n ---help--- Support for the LCD controller integrated in the Marvell Armada XP SoC. @@ -536,14 +528,12 @@ config VIDEO_OMAP3 config I2C_EDID bool "Enable EDID library" - default n help This enables library for accessing EDID data from an LCD panel. config DISPLAY bool "Enable Display support" depends on DM - default n select I2C_EDID help This supports drivers that provide a display, such as eDP (Embedded @@ -554,7 +544,6 @@ config DISPLAY config NXP_TDA19988 bool "Enable NXP TDA19988 support" depends on DISPLAY - default n help This enables support for the NXP TDA19988 HDMI encoder. This encoder will convert RGB data streams into HDMI-encoded signals. @@ -868,7 +857,6 @@ config VIDEO_MCDE_SIMPLE config OSD bool "Enable OSD support" depends on DM - default n help This supports drivers that provide a OSD (on-screen display), which is a (usually text-oriented) graphics buffer to show information on @@ -1008,7 +996,6 @@ config BMP_32BPP config VIDEO_VCXK bool "Enable VCXK video controller driver support" - default n help This enables VCXK driver which can be used with VC2K, VC4K and VC8K devices on various boards from BuS Elektronik GmbH. diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 7ae0ab2b35c35d08955d8e2f79521a6d1cbfd267..f6d07b343f0afba5f0405afa081cb1f09ea835e2 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -25,7 +25,6 @@ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ obj-y += ti/ -obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index b050c4292f6454bdc0918d7accdf959878abbd0c..3037ff39b41f7ad2daf727132858e83a141ffe1b 100644 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -67,11 +67,11 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) printf("Error anx9804 clock is not stable\n"); i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth); - + /* Set a bunch of analog related register values */ - i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07); - i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19); - i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9); + i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07); + i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19); + i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9); i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE); i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0); i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99); @@ -105,7 +105,7 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate); i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes); - /* Link training */ + /* Link training */ i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG, ANX9804_LINK_TRAINING_CTRL_EN); mdelay(5); diff --git a/drivers/video/ati_ids.h b/drivers/video/ati_ids.h deleted file mode 100644 index 3e72a7dd4c0d6426d10168ceca222e04d545b9d2..0000000000000000000000000000000000000000 --- a/drivers/video/ati_ids.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * ATI PCI IDs from XFree86, kept here to make sync'ing with - * XFree much simpler. Currently, this list is only used by - * radeonfb - */ - -#define PCI_CHIP_RV380_3150 0x3150 -#define PCI_CHIP_RV380_3151 0x3151 -#define PCI_CHIP_RV380_3152 0x3152 -#define PCI_CHIP_RV380_3153 0x3153 -#define PCI_CHIP_RV380_3154 0x3154 -#define PCI_CHIP_RV380_3156 0x3156 -#define PCI_CHIP_RV380_3E50 0x3E50 -#define PCI_CHIP_RV380_3E51 0x3E51 -#define PCI_CHIP_RV380_3E52 0x3E52 -#define PCI_CHIP_RV380_3E53 0x3E53 -#define PCI_CHIP_RV380_3E54 0x3E54 -#define PCI_CHIP_RV380_3E56 0x3E56 -#define PCI_CHIP_RS100_4136 0x4136 -#define PCI_CHIP_RS200_4137 0x4137 -#define PCI_CHIP_R300_AD 0x4144 -#define PCI_CHIP_R300_AE 0x4145 -#define PCI_CHIP_R300_AF 0x4146 -#define PCI_CHIP_R300_AG 0x4147 -#define PCI_CHIP_R350_AH 0x4148 -#define PCI_CHIP_R350_AI 0x4149 -#define PCI_CHIP_R350_AJ 0x414A -#define PCI_CHIP_R350_AK 0x414B -#define PCI_CHIP_RV350_AP 0x4150 -#define PCI_CHIP_RV350_AQ 0x4151 -#define PCI_CHIP_RV360_AR 0x4152 -#define PCI_CHIP_RV350_AS 0x4153 -#define PCI_CHIP_RV350_AT 0x4154 -#define PCI_CHIP_RV350_AV 0x4156 -#define PCI_CHIP_MACH32 0x4158 -#define PCI_CHIP_RS250_4237 0x4237 -#define PCI_CHIP_R200_BB 0x4242 -#define PCI_CHIP_R200_BC 0x4243 -#define PCI_CHIP_RS100_4336 0x4336 -#define PCI_CHIP_RS200_4337 0x4337 -#define PCI_CHIP_MACH64CT 0x4354 -#define PCI_CHIP_MACH64CX 0x4358 -#define PCI_CHIP_RS250_4437 0x4437 -#define PCI_CHIP_MACH64ET 0x4554 -#define PCI_CHIP_MACH64GB 0x4742 -#define PCI_CHIP_MACH64GD 0x4744 -#define PCI_CHIP_MACH64GI 0x4749 -#define PCI_CHIP_MACH64GL 0x474C -#define PCI_CHIP_MACH64GM 0x474D -#define PCI_CHIP_MACH64GN 0x474E -#define PCI_CHIP_MACH64GO 0x474F -#define PCI_CHIP_MACH64GP 0x4750 -#define PCI_CHIP_MACH64GQ 0x4751 -#define PCI_CHIP_MACH64GR 0x4752 -#define PCI_CHIP_MACH64GS 0x4753 -#define PCI_CHIP_MACH64GT 0x4754 -#define PCI_CHIP_MACH64GU 0x4755 -#define PCI_CHIP_MACH64GV 0x4756 -#define PCI_CHIP_MACH64GW 0x4757 -#define PCI_CHIP_MACH64GX 0x4758 -#define PCI_CHIP_MACH64GY 0x4759 -#define PCI_CHIP_MACH64GZ 0x475A -#define PCI_CHIP_RV250_Id 0x4964 -#define PCI_CHIP_RV250_Ie 0x4965 -#define PCI_CHIP_RV250_If 0x4966 -#define PCI_CHIP_RV250_Ig 0x4967 -#define PCI_CHIP_R420_JH 0x4A48 -#define PCI_CHIP_R420_JI 0x4A49 -#define PCI_CHIP_R420_JJ 0x4A4A -#define PCI_CHIP_R420_JK 0x4A4B -#define PCI_CHIP_R420_JL 0x4A4C -#define PCI_CHIP_R420_JM 0x4A4D -#define PCI_CHIP_R420_JN 0x4A4E -#define PCI_CHIP_R420_JP 0x4A50 -#define PCI_CHIP_MACH64LB 0x4C42 -#define PCI_CHIP_MACH64LD 0x4C44 -#define PCI_CHIP_RAGE128LE 0x4C45 -#define PCI_CHIP_RAGE128LF 0x4C46 -#define PCI_CHIP_MACH64LG 0x4C47 -#define PCI_CHIP_MACH64LI 0x4C49 -#define PCI_CHIP_MACH64LM 0x4C4D -#define PCI_CHIP_MACH64LN 0x4C4E -#define PCI_CHIP_MACH64LP 0x4C50 -#define PCI_CHIP_MACH64LQ 0x4C51 -#define PCI_CHIP_MACH64LR 0x4C52 -#define PCI_CHIP_MACH64LS 0x4C53 -#define PCI_CHIP_MACH64LT 0x4C54 -#define PCI_CHIP_RADEON_LW 0x4C57 -#define PCI_CHIP_RADEON_LX 0x4C58 -#define PCI_CHIP_RADEON_LY 0x4C59 -#define PCI_CHIP_RADEON_LZ 0x4C5A -#define PCI_CHIP_RV250_Ld 0x4C64 -#define PCI_CHIP_RV250_Le 0x4C65 -#define PCI_CHIP_RV250_Lf 0x4C66 -#define PCI_CHIP_RV250_Lg 0x4C67 -#define PCI_CHIP_RV250_Ln 0x4C6E -#define PCI_CHIP_RAGE128MF 0x4D46 -#define PCI_CHIP_RAGE128ML 0x4D4C -#define PCI_CHIP_R300_ND 0x4E44 -#define PCI_CHIP_R300_NE 0x4E45 -#define PCI_CHIP_R300_NF 0x4E46 -#define PCI_CHIP_R300_NG 0x4E47 -#define PCI_CHIP_R350_NH 0x4E48 -#define PCI_CHIP_R350_NI 0x4E49 -#define PCI_CHIP_R360_NJ 0x4E4A -#define PCI_CHIP_R350_NK 0x4E4B -#define PCI_CHIP_RV350_NP 0x4E50 -#define PCI_CHIP_RV350_NQ 0x4E51 -#define PCI_CHIP_RV350_NR 0x4E52 -#define PCI_CHIP_RV350_NS 0x4E53 -#define PCI_CHIP_RV350_NT 0x4E54 -#define PCI_CHIP_RV350_NV 0x4E56 -#define PCI_CHIP_RAGE128PA 0x5041 -#define PCI_CHIP_RAGE128PB 0x5042 -#define PCI_CHIP_RAGE128PC 0x5043 -#define PCI_CHIP_RAGE128PD 0x5044 -#define PCI_CHIP_RAGE128PE 0x5045 -#define PCI_CHIP_RAGE128PF 0x5046 -#define PCI_CHIP_RAGE128PG 0x5047 -#define PCI_CHIP_RAGE128PH 0x5048 -#define PCI_CHIP_RAGE128PI 0x5049 -#define PCI_CHIP_RAGE128PJ 0x504A -#define PCI_CHIP_RAGE128PK 0x504B -#define PCI_CHIP_RAGE128PL 0x504C -#define PCI_CHIP_RAGE128PM 0x504D -#define PCI_CHIP_RAGE128PN 0x504E -#define PCI_CHIP_RAGE128PO 0x504F -#define PCI_CHIP_RAGE128PP 0x5050 -#define PCI_CHIP_RAGE128PQ 0x5051 -#define PCI_CHIP_RAGE128PR 0x5052 -#define PCI_CHIP_RAGE128PS 0x5053 -#define PCI_CHIP_RAGE128PT 0x5054 -#define PCI_CHIP_RAGE128PU 0x5055 -#define PCI_CHIP_RAGE128PV 0x5056 -#define PCI_CHIP_RAGE128PW 0x5057 -#define PCI_CHIP_RAGE128PX 0x5058 -#define PCI_CHIP_RADEON_QD 0x5144 -#define PCI_CHIP_RADEON_QE 0x5145 -#define PCI_CHIP_RADEON_QF 0x5146 -#define PCI_CHIP_RADEON_QG 0x5147 -#define PCI_CHIP_R200_QH 0x5148 -#define PCI_CHIP_R200_QI 0x5149 -#define PCI_CHIP_R200_QJ 0x514A -#define PCI_CHIP_R200_QK 0x514B -#define PCI_CHIP_R200_QL 0x514C -#define PCI_CHIP_R200_QM 0x514D -#define PCI_CHIP_R200_QN 0x514E -#define PCI_CHIP_R200_QO 0x514F -#define PCI_CHIP_RV200_QW 0x5157 -#define PCI_CHIP_RV200_QX 0x5158 -#define PCI_CHIP_RV100_QY 0x5159 -#define PCI_CHIP_RV100_QZ 0x515A -#define PCI_CHIP_RN50 0x515E -#define PCI_CHIP_RAGE128RE 0x5245 -#define PCI_CHIP_RAGE128RF 0x5246 -#define PCI_CHIP_RAGE128RG 0x5247 -#define PCI_CHIP_RAGE128RK 0x524B -#define PCI_CHIP_RAGE128RL 0x524C -#define PCI_CHIP_RAGE128SE 0x5345 -#define PCI_CHIP_RAGE128SF 0x5346 -#define PCI_CHIP_RAGE128SG 0x5347 -#define PCI_CHIP_RAGE128SH 0x5348 -#define PCI_CHIP_RAGE128SK 0x534B -#define PCI_CHIP_RAGE128SL 0x534C -#define PCI_CHIP_RAGE128SM 0x534D -#define PCI_CHIP_RAGE128SN 0x534E -#define PCI_CHIP_RAGE128TF 0x5446 -#define PCI_CHIP_RAGE128TL 0x544C -#define PCI_CHIP_RAGE128TR 0x5452 -#define PCI_CHIP_RAGE128TS 0x5453 -#define PCI_CHIP_RAGE128TT 0x5454 -#define PCI_CHIP_RAGE128TU 0x5455 -#define PCI_CHIP_RV370_5460 0x5460 -#define PCI_CHIP_RV370_5461 0x5461 -#define PCI_CHIP_RV370_5462 0x5462 -#define PCI_CHIP_RV370_5463 0x5463 -#define PCI_CHIP_RV370_5464 0x5464 -#define PCI_CHIP_RV370_5465 0x5465 -#define PCI_CHIP_RV370_5466 0x5466 -#define PCI_CHIP_RV370_5467 0x5467 -#define PCI_CHIP_R423_UH 0x5548 -#define PCI_CHIP_R423_UI 0x5549 -#define PCI_CHIP_R423_UJ 0x554A -#define PCI_CHIP_R423_UK 0x554B -#define PCI_CHIP_R423_UQ 0x5551 -#define PCI_CHIP_R423_UR 0x5552 -#define PCI_CHIP_R423_UT 0x5554 -#define PCI_CHIP_MACH64VT 0x5654 -#define PCI_CHIP_MACH64VU 0x5655 -#define PCI_CHIP_MACH64VV 0x5656 -#define PCI_CHIP_RS300_5834 0x5834 -#define PCI_CHIP_RS300_5835 0x5835 -#define PCI_CHIP_RS300_5836 0x5836 -#define PCI_CHIP_RS300_5837 0x5837 -#define PCI_CHIP_RV370_5B60 0x5B60 -#define PCI_CHIP_RV370_5B61 0x5B61 -#define PCI_CHIP_RV370_5B62 0x5B62 -#define PCI_CHIP_RV370_5B63 0x5B63 -#define PCI_CHIP_RV370_5B64 0x5B64 -#define PCI_CHIP_RV370_5B65 0x5B65 -#define PCI_CHIP_RV370_5B66 0x5B66 -#define PCI_CHIP_RV370_5B67 0x5B67 -#define PCI_CHIP_RV280_5960 0x5960 -#define PCI_CHIP_RV280_5961 0x5961 -#define PCI_CHIP_RV280_5962 0x5962 -#define PCI_CHIP_RV280_5964 0x5964 -#define PCI_CHIP_RV280_5C61 0x5C61 -#define PCI_CHIP_RV280_5C63 0x5C63 -#define PCI_CHIP_R423_5D57 0x5D57 -#define PCI_CHIP_RS350_7834 0x7834 -#define PCI_CHIP_RS350_7835 0x7835 diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c deleted file mode 100644 index 383666781ccef580c9eca22dfa5dae4459805830..0000000000000000000000000000000000000000 --- a/drivers/video/ati_radeon_fb.c +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * ATI Radeon Video card Framebuffer driver. - * - * Copyright 2007 Freescale Semiconductor, Inc. - * Zhang Wei <wei.zhang@freescale.com> - * Jason Jin <jason.jin@freescale.com> - * - * Some codes of this file is partly ported from Linux kernel - * ATI video framebuffer driver. - * - * Now the driver is tested on below ATI chips: - * 9200 - * X300 - * X700 - */ - -#include <common.h> -#include <linux/delay.h> - -#include <command.h> -#include <bios_emul.h> -#include <env.h> -#include <pci.h> -#include <asm/processor.h> -#include <linux/errno.h> -#include <asm/io.h> -#include <malloc.h> -#include <video_fb.h> -#include "videomodes.h" - -#include <radeon.h> -#include "ati_ids.h" -#include "ati_radeon_fb.h" - -#undef DEBUG - -#ifdef DEBUG -#define DPRINT(x...) printf(x) -#else -#define DPRINT(x...) do{}while(0) -#endif - -#define MAX_MAPPED_VRAM (2048*2048*4) -#define MIN_MAPPED_VRAM (1024*768*1) - -#define RADEON_BUFFER_ALIGN 0x00000fff -#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ - & ~RADEON_BUFFER_ALIGN) - 1) -#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ - ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) - -#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ - (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) -#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ - (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) -#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ - ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) -#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ - ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) - -/*#define PCI_VENDOR_ID_ATI*/ -#define PCI_CHIP_RV280_5960 0x5960 -#define PCI_CHIP_RV280_5961 0x5961 -#define PCI_CHIP_RV280_5962 0x5962 -#define PCI_CHIP_RV280_5964 0x5964 -#define PCI_CHIP_RV280_5C63 0x5C63 -#define PCI_CHIP_RV370_5B60 0x5B60 -#define PCI_CHIP_RV380_5657 0x5657 -#define PCI_CHIP_R420_554d 0x554d - -static struct pci_device_id ati_radeon_pci_ids[] = { - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, - {0, 0} -}; - -static u16 ati_radeon_id_family_table[][2] = { - {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, - {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, - {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, - {0, 0} -}; - -u16 get_radeon_id_family(u16 device) -{ - int i; - for (i=0; ati_radeon_id_family_table[0][i]; i+=2) - if (ati_radeon_id_family_table[0][i] == device) - return ati_radeon_id_family_table[0][i + 1]; - return 0; -} - -struct radeonfb_info *rinfo; - -static void radeon_identify_vram(struct radeonfb_info *rinfo) -{ - u32 tmp; - - /* framebuffer size */ - if ((rinfo->family == CHIP_FAMILY_RS100) || - (rinfo->family == CHIP_FAMILY_RS200) || - (rinfo->family == CHIP_FAMILY_RS300)) { - u32 tom = INREG(NB_TOM); - tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); - - radeon_fifo_wait(6); - OUTREG(MC_FB_LOCATION, tom); - OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); - - /* This is supposed to fix the crtc2 noise problem. */ - OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); - - if ((rinfo->family == CHIP_FAMILY_RS100) || - (rinfo->family == CHIP_FAMILY_RS200)) { - /* This is to workaround the asic bug for RMX, some versions - of BIOS dosen't have this register initialized correctly. - */ - OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, - ~CRTC_H_CUTOFF_ACTIVE_EN); - } - } else { - tmp = INREG(CONFIG_MEMSIZE); - } - - /* mem size is bits [28:0], mask off the rest */ - rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; - - /* - * Hack to get around some busted production M6's - * reporting no ram - */ - if (rinfo->video_ram == 0) { - switch (rinfo->pdev.device) { - case PCI_CHIP_RADEON_LY: - case PCI_CHIP_RADEON_LZ: - rinfo->video_ram = 8192 * 1024; - break; - default: - break; - } - } - - /* - * Now try to identify VRAM type - */ - if ((rinfo->family >= CHIP_FAMILY_R300) || - (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) - rinfo->vram_ddr = 1; - else - rinfo->vram_ddr = 0; - - tmp = INREG(MEM_CNTL); - if (IS_R300_VARIANT(rinfo)) { - tmp &= R300_MEM_NUM_CHANNELS_MASK; - switch (tmp) { - case 0: rinfo->vram_width = 64; break; - case 1: rinfo->vram_width = 128; break; - case 2: rinfo->vram_width = 256; break; - default: rinfo->vram_width = 128; break; - } - } else if ((rinfo->family == CHIP_FAMILY_RV100) || - (rinfo->family == CHIP_FAMILY_RS100) || - (rinfo->family == CHIP_FAMILY_RS200)){ - if (tmp & RV100_MEM_HALF_MODE) - rinfo->vram_width = 32; - else - rinfo->vram_width = 64; - } else { - if (tmp & MEM_NUM_CHANNELS_MASK) - rinfo->vram_width = 128; - else - rinfo->vram_width = 64; - } - - /* This may not be correct, as some cards can have half of channel disabled - * ToDo: identify these cases - */ - - DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", - rinfo->video_ram / 1024, - rinfo->vram_ddr ? "DDR" : "SDRAM", - rinfo->vram_width); - -} - -static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) -{ - int i; - - radeon_fifo_wait(20); - -#if 0 - /* Workaround from XFree */ - if (rinfo->is_mobility) { - /* A temporal workaround for the occational blanking on certain laptop - * panels. This appears to related to the PLL divider registers - * (fail to lock?). It occurs even when all dividers are the same - * with their old settings. In this case we really don't need to - * fiddle with PLL registers. By doing this we can avoid the blanking - * problem with some panels. - */ - if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && - (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & - (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { - /* We still have to force a switch to selected PPLL div thanks to - * an XFree86 driver bug which will switch it away in some cases - * even when using UseFDev */ - OUTREGP(CLOCK_CNTL_INDEX, - mode->clk_cntl_index & PPLL_DIV_SEL_MASK, - ~PPLL_DIV_SEL_MASK); - radeon_pll_errata_after_index(rinfo); - radeon_pll_errata_after_data(rinfo); - return; - } - } -#endif - if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; - - /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ - OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); - - /* Reset PPLL & enable atomic update */ - OUTPLLP(PPLL_CNTL, - PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, - ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); - - /* Switch to selected PPLL divider */ - OUTREGP(CLOCK_CNTL_INDEX, - mode->clk_cntl_index & PPLL_DIV_SEL_MASK, - ~PPLL_DIV_SEL_MASK); - - /* Set PPLL ref. div */ - if (rinfo->family == CHIP_FAMILY_R300 || - rinfo->family == CHIP_FAMILY_RS300 || - rinfo->family == CHIP_FAMILY_R350 || - rinfo->family == CHIP_FAMILY_RV350) { - if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { - /* When restoring console mode, use saved PPLL_REF_DIV - * setting. - */ - OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); - } else { - /* R300 uses ref_div_acc field as real ref divider */ - OUTPLLP(PPLL_REF_DIV, - (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), - ~R300_PPLL_REF_DIV_ACC_MASK); - } - } else - OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); - - /* Set PPLL divider 3 & post divider*/ - OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); - OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); - - /* Write update */ - while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) - ; - OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); - - /* Wait read update complete */ - /* FIXME: Certain revisions of R300 can't recover here. Not sure of - the cause yet, but this workaround will mask the problem for now. - Other chips usually will pass at the very first test, so the - workaround shouldn't have any effect on them. */ - for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) - ; - - OUTPLL(HTOTAL_CNTL, 0); - - /* Clear reset & atomic update */ - OUTPLLP(PPLL_CNTL, 0, - ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); - - /* We may want some locking ... oh well */ - udelay(5000); - - /* Switch back VCLK source to PPLL */ - OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); -} - -typedef struct { - u16 reg; - u32 val; -} reg_val; - -#if 0 /* unused ? -> scheduled for removal */ -/* these common regs are cleared before mode setting so they do not - * interfere with anything - */ -static reg_val common_regs[] = { - { OVR_CLR, 0 }, - { OVR_WID_LEFT_RIGHT, 0 }, - { OVR_WID_TOP_BOTTOM, 0 }, - { OV0_SCALE_CNTL, 0 }, - { SUBPIC_CNTL, 0 }, - { VIPH_CONTROL, 0 }, - { I2C_CNTL_1, 0 }, - { GEN_INT_CNTL, 0 }, - { CAP0_TRIG_CNTL, 0 }, - { CAP1_TRIG_CNTL, 0 }, -}; -#endif /* 0 */ - -void radeon_setmode(void) -{ - struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); - - mode->crtc_gen_cntl = 0x03000200; - mode->crtc_ext_cntl = 0x00008048; - mode->dac_cntl = 0xff002100; - mode->crtc_h_total_disp = 0x4f0063; - mode->crtc_h_sync_strt_wid = 0x8c02a2; - mode->crtc_v_total_disp = 0x01df020c; - mode->crtc_v_sync_strt_wid = 0x8201ea; - mode->crtc_pitch = 0x00500050; - - OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); - OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, - ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); - OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); - OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); - OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); - OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); - OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); - OUTREG(CRTC_OFFSET, 0); - OUTREG(CRTC_OFFSET_CNTL, 0); - OUTREG(CRTC_PITCH, mode->crtc_pitch); - - mode->clk_cntl_index = 0x300; - mode->ppll_ref_div = 0xc; - mode->ppll_div_3 = 0x00030059; - - radeon_write_pll_regs(rinfo, mode); -} - -static void set_pal(void) -{ - int idx, val = 0; - - for (idx = 0; idx < 256; idx++) { - OUTREG8(PALETTE_INDEX, idx); - OUTREG(PALETTE_DATA, val); - val += 0x00010101; - } -} - -void radeon_setmode_9200(int vesa_idx, int bpp) -{ - struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); - - mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; - mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; - mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; - mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; - - switch (bpp) { - case 24: - mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ -#if defined(__BIG_ENDIAN) - mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; - mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; -#endif - break; - case 16: - mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ -#if defined(__BIG_ENDIAN) - mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; - mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; -#endif - break; - default: - mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ - mode->surface_cntl = 0x00000000; - break; - } - - switch (vesa_idx) { - case RES_MODE_1280x1024: - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); - mode->ppll_div_3 = 0x00010078; -#else /* default @ 60 Hz */ - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); - mode->ppll_div_3 = 0x00010060; -#endif - /* - * for this mode pitch expands to the same value for 32, 16 and 8 bpp, - * so we set it here once only. - */ - mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); - switch (bpp) { - case 24: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); - break; - case 16: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); - break; - default: /* 8 bpp */ - mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); - break; - } - break; - case RES_MODE_1024x768: -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); - mode->ppll_div_3 = 0x0002008c; -#else /* @ 60 Hz */ - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; - mode->ppll_div_3 = 0x00020074; -#endif - /* also same pitch value for 32, 16 and 8 bpp */ - mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); - switch (bpp) { - case 24: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); - break; - case 16: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); - break; - default: /* 8 bpp */ - mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); - break; - } - break; - case RES_MODE_800x600: - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); - mode->ppll_div_3 = 0x000300b0; -#else /* @ 60 Hz */ - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); - mode->ppll_div_3 = 0x0003008e; -#endif - switch (bpp) { - case 24: - mode->crtc_pitch = RADEON_CRT_PITCH(832,32); - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); - break; - case 16: - mode->crtc_pitch = RADEON_CRT_PITCH(896,16); - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); - break; - default: /* 8 bpp */ - mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); - mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); - break; - } - break; - default: /* RES_MODE_640x480 */ -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; - mode->ppll_div_3 = 0x00030070; -#else /* @ 60 Hz */ - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; - mode->ppll_div_3 = 0x00030059; -#endif - /* also same pitch value for 32, 16 and 8 bpp */ - mode->crtc_pitch = RADEON_CRT_PITCH(640,32); - switch (bpp) { - case 24: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); - break; - case 16: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); - break; - default: /* 8 bpp */ - mode->crtc_offset_cntl = 0x00000000; - break; - } - break; - } - - OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); - OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, - (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); - OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); - OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); - OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); - OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); - OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); - OUTREG(CRTC_OFFSET, 0); - OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); - OUTREG(CRTC_PITCH, mode->crtc_pitch); - OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); - - mode->clk_cntl_index = 0x300; - mode->ppll_ref_div = 0xc; - - radeon_write_pll_regs(rinfo, mode); - - OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, - ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); - OUTREG(SURFACE0_INFO, mode->surf_info[0]); - OUTREG(SURFACE0_LOWER_BOUND, 0); - OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); - OUTREG(SURFACE_CNTL, mode->surface_cntl); - - if (bpp > 8) - set_pal(); - - free(mode); -} - -#include "../bios_emulator/include/biosemu.h" - -int radeon_probe(struct radeonfb_info *rinfo) -{ - pci_dev_t pdev; - u16 did; - - pdev = pci_find_devices(ati_radeon_pci_ids, 0); - - if (pdev != -1) { - pci_read_config_word(pdev, PCI_DEVICE_ID, &did); - printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", - PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, - (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); - - strcpy(rinfo->name, "ATI Radeon"); - rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; - rinfo->pdev.device = did; - rinfo->family = get_radeon_id_family(rinfo->pdev.device); - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, - &rinfo->fb_base_bus); - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, - &rinfo->mmio_base_bus); - rinfo->fb_base_bus &= 0xfffff000; - rinfo->mmio_base_bus &= ~0x04; - - rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, - PCI_REGION_MEM, 0, MAP_NOCACHE); - DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", - rinfo->mmio_base, rinfo->mmio_base_bus); - rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; - DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); - /* PostBIOS with x86 emulater */ - if (!BootVideoCardBIOS(pdev, NULL, 0)) - return -1; - - /* - * Check for errata - * (These will be added in the future for the chipfamily - * R300, RV200, RS200, RV100, RS100.) - */ - - /* Get VRAM size and type */ - radeon_identify_vram(rinfo); - - rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, - rinfo->video_ram); - rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, - PCI_REGION_MEM, 0, MAP_NOCACHE); - DPRINT("Radeon: framebuffer base address 0x%08x, " - "bus address 0x%08x\n" - "MMIO base address 0x%08x, bus address 0x%08x, " - "framebuffer local base 0x%08x.\n ", - (u32)rinfo->fb_base, rinfo->fb_base_bus, - (u32)rinfo->mmio_base, rinfo->mmio_base_bus, - rinfo->fb_local_base); - return 0; - } - return -1; -} - -/* - * The Graphic Device - */ -GraphicDevice ctfb; - -#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ -#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ -#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ -#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ - -void *video_hw_init(void) -{ - GraphicDevice *pGD = (GraphicDevice *) & ctfb; - u32 *vm; - char *penv; - unsigned long t1, hsynch, vsynch; - int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; - struct ctfb_res_modes *res_mode; - struct ctfb_res_modes var_mode; - - rinfo = malloc(sizeof(struct radeonfb_info)); - - printf("Video: "); - if(radeon_probe(rinfo)) { - printf("No radeon video card found!\n"); - return NULL; - } - - tmp = 0; - - videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; - /* get video mode via environment */ - penv = env_get("videomode"); - if (penv) { - /* deceide if it is a string */ - if (penv[0] <= '9') { - videomode = (int)hextoul(penv, NULL); - tmp = 1; - } - } else { - tmp = 1; - } - if (tmp) { - /* parameter are vesa modes */ - /* search params */ - for (i = 0; i < VESA_MODES_COUNT; i++) { - if (vesa_modes[i].vesanr == videomode) - break; - } - if (i == VESA_MODES_COUNT) { - printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); - i = 0; - } - res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; - bits_per_pixel = vesa_modes[i].bits_per_pixel; - vesa_idx = vesa_modes[i].resindex; - } else { - res_mode = (struct ctfb_res_modes *) &var_mode; - bits_per_pixel = video_get_params (res_mode, penv); - } - - /* calculate hsynch and vsynch freq (info only) */ - t1 = (res_mode->left_margin + res_mode->xres + - res_mode->right_margin + res_mode->hsync_len) / 8; - t1 *= 8; - t1 *= res_mode->pixclock; - t1 /= 1000; - hsynch = 1000000000L / t1; - t1 *= (res_mode->upper_margin + res_mode->yres + - res_mode->lower_margin + res_mode->vsync_len); - t1 /= 1000; - vsynch = 1000000000L / t1; - - /* fill in Graphic device struct */ - sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, - res_mode->yres, bits_per_pixel, (hsynch / 1000), - (vsynch / 1000)); - printf ("%s\n", pGD->modeIdent); - pGD->winSizeX = res_mode->xres; - pGD->winSizeY = res_mode->yres; - pGD->plnSizeX = res_mode->xres; - pGD->plnSizeY = res_mode->yres; - - switch (bits_per_pixel) { - case 24: - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; - if (res_mode->xres == 800) { - pGD->winSizeX = 832; - pGD->plnSizeX = 832; - } - break; - case 16: - pGD->gdfBytesPP = 2; - pGD->gdfIndex = GDF_16BIT_565RGB; - if (res_mode->xres == 800) { - pGD->winSizeX = 896; - pGD->plnSizeX = 896; - } - break; - default: - if (res_mode->xres == 800) { - pGD->winSizeX = 1024; - pGD->plnSizeX = 1024; - } - pGD->gdfBytesPP = 1; - pGD->gdfIndex = GDF__8BIT_INDEX; - break; - } - - pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; - pGD->pciBase = (unsigned int)rinfo->fb_base; - pGD->frameAdrs = (unsigned int)rinfo->fb_base; - pGD->memSize = 64 * 1024 * 1024; - - /* Cursor Start Address */ - pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + - (unsigned int)rinfo->fb_base; - if ((pGD->dprBase & 0x0fff) != 0) { - /* allign it */ - pGD->dprBase &= 0xfffff000; - pGD->dprBase += 0x00001000; - } - DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, - PATTERN_ADR); - pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ - pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ - /* set up Hardware */ - - /* Clear video memory (only visible screen area) */ - i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; - vm = (unsigned int *) pGD->pciBase; - while (i--) - *vm++ = 0; - /*SetDrawingEngine (bits_per_pixel);*/ - - if (rinfo->family == CHIP_FAMILY_RV280) - radeon_setmode_9200(vesa_idx, bits_per_pixel); - else - radeon_setmode(); - - return ((void *) pGD); -} - -void video_set_lut (unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ) -{ - OUTREG(PALETTE_INDEX, index); - OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); -} diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h deleted file mode 100644 index 9dd638bb9e454da11d225bfd8b2b6d687a91fb57..0000000000000000000000000000000000000000 --- a/drivers/video/ati_radeon_fb.h +++ /dev/null @@ -1,282 +0,0 @@ -#ifndef __ATI_RADEON_FB_H -#define __ATI_RADEON_FB_H - -/*************************************************************** - * Most of the definitions here are adapted right from XFree86 * - ***************************************************************/ - -/* - * Chip families. Must fit in the low 16 bits of a long word - */ -enum radeon_family { - CHIP_FAMILY_UNKNOW, - CHIP_FAMILY_LEGACY, - CHIP_FAMILY_RADEON, - CHIP_FAMILY_RV100, - CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ - CHIP_FAMILY_RV200, - CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), - RS250 (IGP 7000) */ - CHIP_FAMILY_R200, - CHIP_FAMILY_RV250, - CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ - CHIP_FAMILY_RV280, - CHIP_FAMILY_R300, - CHIP_FAMILY_R350, - CHIP_FAMILY_RV350, - CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ - CHIP_FAMILY_R420, /* R420/R423/M18 */ - CHIP_FAMILY_LAST, -}; - -#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ - ((rinfo)->family == CHIP_FAMILY_RV200) || \ - ((rinfo)->family == CHIP_FAMILY_RS100) || \ - ((rinfo)->family == CHIP_FAMILY_RS200) || \ - ((rinfo)->family == CHIP_FAMILY_RV250) || \ - ((rinfo)->family == CHIP_FAMILY_RV280) || \ - ((rinfo)->family == CHIP_FAMILY_RS300)) - -#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ - ((rinfo)->family == CHIP_FAMILY_RV350) || \ - ((rinfo)->family == CHIP_FAMILY_R350) || \ - ((rinfo)->family == CHIP_FAMILY_RV380) || \ - ((rinfo)->family == CHIP_FAMILY_R420)) - -struct radeonfb_info { - char name[20]; - - struct pci_device_id pdev; - u16 family; - - u32 fb_base_bus; - u32 mmio_base_bus; - - void *mmio_base; - void *fb_base; - - u32 video_ram; - u32 mapped_vram; - int vram_width; - int vram_ddr; - - u32 fb_local_base; -}; - -#define INREG8(addr) readb((rinfo->mmio_base)+addr) -#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) -#define INREG16(addr) readw((rinfo->mmio_base)+addr) -#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) -#define INREG(addr) readl((rinfo->mmio_base)+addr) -#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) - -static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, - u32 val, u32 mask) -{ - unsigned int tmp; - - tmp = INREG(addr); - tmp &= (mask); - tmp |= (val); - OUTREG(addr, tmp); -} - -#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) - -/* - * 2D Engine helper routines - */ -static inline void radeon_engine_flush (struct radeonfb_info *rinfo) -{ - int i; - - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) - return; - udelay(1); - } - printf("radeonfb: Flush Timeout !\n"); -} - -static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) -{ - int i; - - for (i=0; i<2000000; i++) { - if ((INREG(RBBM_STATUS) & 0x7f) >= entries) - return; - udelay(1); - } - printf("radeonfb: FIFO Timeout !\n"); -} - -static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) -{ - int i; - - /* ensure FIFO is empty before waiting for idle */ - _radeon_fifo_wait (rinfo, 64); - - for (i=0; i<2000000; i++) { - if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { - radeon_engine_flush (rinfo); - return; - } - udelay(1); - } - printf("radeonfb: Idle Timeout !\n"); -} - -#define radeon_engine_idle() _radeon_engine_idle(rinfo) -#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) -#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) - -/* - * This structure contains the various registers manipulated by this - * driver for setting or restoring a mode. It's mostly copied from - * XFree's RADEONSaveRec structure. A few chip settings might still be - * tweaked without beeing reflected or saved in these registers though - */ -struct radeon_regs { - /* Common registers */ - u32 ovr_clr; - u32 ovr_wid_left_right; - u32 ovr_wid_top_bottom; - u32 ov0_scale_cntl; - u32 mpp_tb_config; - u32 mpp_gp_config; - u32 subpic_cntl; - u32 viph_control; - u32 i2c_cntl_1; - u32 gen_int_cntl; - u32 cap0_trig_cntl; - u32 cap1_trig_cntl; - u32 bus_cntl; - u32 surface_cntl; - u32 bios_5_scratch; - - /* Other registers to save for VT switches or driver load/unload */ - u32 dp_datatype; - u32 rbbm_soft_reset; - u32 clock_cntl_index; - u32 amcgpio_en_reg; - u32 amcgpio_mask; - - /* Surface/tiling registers */ - u32 surf_lower_bound[8]; - u32 surf_upper_bound[8]; - u32 surf_info[8]; - - /* CRTC registers */ - u32 crtc_gen_cntl; - u32 crtc_ext_cntl; - u32 dac_cntl; - u32 crtc_h_total_disp; - u32 crtc_h_sync_strt_wid; - u32 crtc_v_total_disp; - u32 crtc_v_sync_strt_wid; - u32 crtc_offset; - u32 crtc_offset_cntl; - u32 crtc_pitch; - u32 disp_merge_cntl; - u32 grph_buffer_cntl; - u32 crtc_more_cntl; - - /* CRTC2 registers */ - u32 crtc2_gen_cntl; - u32 dac2_cntl; - u32 disp_output_cntl; - u32 disp_hw_debug; - u32 disp2_merge_cntl; - u32 grph2_buffer_cntl; - u32 crtc2_h_total_disp; - u32 crtc2_h_sync_strt_wid; - u32 crtc2_v_total_disp; - u32 crtc2_v_sync_strt_wid; - u32 crtc2_offset; - u32 crtc2_offset_cntl; - u32 crtc2_pitch; - - /* Flat panel regs */ - u32 fp_crtc_h_total_disp; - u32 fp_crtc_v_total_disp; - u32 fp_gen_cntl; - u32 fp2_gen_cntl; - u32 fp_h_sync_strt_wid; - u32 fp2_h_sync_strt_wid; - u32 fp_horz_stretch; - u32 fp_panel_cntl; - u32 fp_v_sync_strt_wid; - u32 fp2_v_sync_strt_wid; - u32 fp_vert_stretch; - u32 lvds_gen_cntl; - u32 lvds_pll_cntl; - u32 tmds_crc; - u32 tmds_transmitter_cntl; - - /* Computed values for PLL */ - u32 dot_clock_freq; - int feedback_div; - int post_div; - - /* PLL registers */ - u32 ppll_div_3; - u32 ppll_ref_div; - u32 vclk_ecp_cntl; - u32 clk_cntl_index; - - /* Computed values for PLL2 */ - u32 dot_clock_freq_2; - int feedback_div_2; - int post_div_2; - - /* PLL2 registers */ - u32 p2pll_ref_div; - u32 p2pll_div_0; - u32 htotal_cntl2; - - /* Palette */ - int palette_valid; -}; - -static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) -{ - u32 data; - - OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); - /* radeon_pll_errata_after_index(rinfo); */ - data = INREG(CLOCK_CNTL_DATA); - /* radeon_pll_errata_after_data(rinfo); */ - return data; -} - -static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, - u32 val) -{ - - OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); - /* radeon_pll_errata_after_index(rinfo); */ - OUTREG(CLOCK_CNTL_DATA, val); - /* radeon_pll_errata_after_data(rinfo); */ -} - -static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, - u32 val, u32 mask) -{ - unsigned int tmp; - - tmp = __INPLL(rinfo, index); - tmp &= (mask); - tmp |= (val); - __OUTPLL(rinfo, index, tmp); -} - -#define INPLL(addr) __INPLL(rinfo, addr) -#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) -#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) - -#endif diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c index 2a72d23eb87b83b046a781a14fbcad345eb25ee6..3863662d9f6fa93e6941d7b0ea3fbe29382a36d4 100644 --- a/drivers/video/bus_vcxk.c +++ b/drivers/video/bus_vcxk.c @@ -63,8 +63,8 @@ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; #ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED #define VCXK_BWS(x, data) vcxk_bws[x] = data; - #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask; - #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask; + #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask; + #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask; #define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data; #else u_char double_bws[16384]; @@ -83,7 +83,7 @@ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; #endif #define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2] -#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2] +#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2] #define VC2K_Bright vcxk_bws[0x8000] #define VC8K_BrightH vcxk_bws[0xC000] #define VC8K_BrightL vcxk_bws[0xC001] @@ -263,7 +263,7 @@ void vcxk_clear(void) * set the display brightness * PARAMETER * side 1 set front side brightness - * 2 set back side brightness + * 2 set back side brightness * 3 set brightness for both sides * brightness 0..1000 *** @@ -276,7 +276,7 @@ void vcxk_setbrightness(unsigned int side, short brightness) VC4K16_Bright1 = brightness + 23; if ((side == 0) || (side & 0x2)) VC4K16_Bright2 = brightness + 23; - } else { + } else { VC2K_Bright = (brightness >> 4) + 2; VC8K_BrightH = (brightness + 23) >> 8; VC8K_BrightL = (brightness + 23) & 0xFF; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 5e1ee061e8e81af2ceef6b3f9373ae282b49eb58..566fc1e01a4676a24128ae3e7802357ed7797d27 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -71,10 +71,11 @@ #include <fdtdec.h> #include <gzip.h> #include <log.h> -#include <version.h> +#include <version_string.h> #include <malloc.h> #include <video.h> #include <asm/global_data.h> +#include <dm/ofnode.h> #include <linux/compiler.h> #if defined(CONFIG_VIDEO_MXS) @@ -108,7 +109,6 @@ * Console device */ -#include <version.h> #include <linux/types.h> #include <stdio_dev.h> #include <video_font.h> @@ -2138,8 +2138,7 @@ int drv_video_init(void) #if defined(CONFIG_VGA_AS_SINGLE_DEVICE) have_keyboard = false; #elif defined(CONFIG_OF_CONTROL) - have_keyboard = !fdtdec_get_config_bool(gd->fdt_blob, - "u-boot,no-keyboard"); + have_keyboard = !ofnode_conf_read_bool("u-boot,no-keyboard"); #else have_keyboard = true; #endif diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c index c56eadc8237bbe98d503b420b6122d15a480fefa..804fcd0b248486cc4404152e2f0b6eb39c09f1f2 100644 --- a/drivers/video/exynos/exynos_mipi_dsi.c +++ b/drivers/video/exynos/exynos_mipi_dsi.c @@ -288,8 +288,8 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt, dt->rx_timeout = fdtdec_get_int(blob, node, "samsung,dsim-config-rx-timeout", 0); - lcd_dt->name = fdtdec_get_config_string(blob, - "samsung,dsim-device-name"); + lcd_dt->name = fdt_getprop(blob, node, "samsung,dsim-device-name", + NULL); lcd_dt->id = fdtdec_get_int(blob, node, "samsung,dsim-device-id", 0); diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 523d8a8d98334fc7ab49a8c3c6bef47026574027..98d296571199f90f34443c0141f3633e5a51823c 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -54,7 +54,7 @@ __weak void mxsfb_system_setup(void) * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel: * setenv videomode * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851, - * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 + * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 */ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c index 67f5266164fa7b75f9c8f4d5ccf032b13bf8aef5..21ade8d93c4ade3d43681edebd02dafe293642c6 100644 --- a/drivers/video/pxa_lcd.c +++ b/drivers/video/pxa_lcd.c @@ -199,72 +199,6 @@ vidinfo_t panel_info = { /*----------------------------------------------------------------------*/ -#ifdef CONFIG_ACX517AKN - -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f9 -# define REG_LCCR3 0x03700006 - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 320, - .vl_width = 320, - .vl_height = 320, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 0x04, - .vl_blw = 0x1c, - .vl_elw = 0x08, - .vl_vpw = 0x01, - .vl_bfw = 0x07, - .vl_efw = 0x08, -}; -#endif /* CONFIG_ACX517AKN */ - -#ifdef CONFIG_ACX544AKN - -# define LCD_BPP LCD_COLOR16 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f9 -# define REG_LCCR3 0x04700007 /* 16bpp */ - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 320, - .vl_width = 320, - .vl_height = 320, - .vl_clkp = CONFIG_SYS_LOW, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 0, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 0x05, - .vl_blw = 0x13, - .vl_elw = 0x08, - .vl_vpw = 0x02, - .vl_bfw = 0x07, - .vl_efw = 0x05, -}; -#endif /* CONFIG_ACX544AKN */ - -/*----------------------------------------------------------------------*/ - #ifdef CONFIG_LQ038J7DH53 # define LCD_BPP LCD_COLOR8 @@ -295,7 +229,7 @@ vidinfo_t panel_info = { .vl_bfw = 0x04, .vl_efw = 0x01, }; -#endif /* CONFIG_ACX517AKN */ +#endif /* CONFIG_LQ038J7DH53 */ /*----------------------------------------------------------------------*/ diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 8813220671d80514d451773aca916779410a2664..f14cbc6dbf7f9606e01720adbbec63963ebc8519 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -328,4 +328,3 @@ int rk_mipi_phy_enable(struct udevice *dev) return 0; } - diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h index 5d00bff9fd02be58391ef7deec706fbb1fcc1dbb..26f4ac2ca8151152bf84c86bf7bedb6c6fc9d585 100644 --- a/drivers/video/stb_truetype.h +++ b/drivers/video/stb_truetype.h @@ -497,7 +497,6 @@ STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph, // // It's inefficient; you might want to c&p it and optimize it. - ////////////////////////////////////////////////////////////////////////////// // // NEW TEXTURE BAKING API diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c index 813b87a681739e1e9723db9298c2facb71f8d710..7ad0af73f05781a97a5232af8fdb038cac011bd5 100644 --- a/drivers/video/tdo-tl070wsh30.c +++ b/drivers/video/tdo-tl070wsh30.c @@ -118,7 +118,7 @@ static int tl070wsh30_panel_probe(struct udevice *dev) /* reset panel */ dm_gpio_set_value(&priv->reset, true); - + mdelay(10); dm_gpio_set_value(&priv->reset, false); diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index 031bab25aea077f81516a219ef43b70dba2f4759..0ffc1b6444b6ca2f9e6597f6a151e3f131ba7c9b 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -6,7 +6,6 @@ menu "1-Wire support" config W1 bool "Enable 1-wire controllers support" - default no depends on DM help Support for the Dallas 1-Wire bus. @@ -15,15 +14,13 @@ if W1 config W1_GPIO bool "Enable 1-wire GPIO bitbanging" - default no depends on DM_GPIO help Emulate a 1-wire bus using a GPIO. config W1_MXC bool "Enable 1-wire controller on i.MX processors" - default no - depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 + depends on ARCH_MX31 || ARCH_MX5 help Support the one wire controller found in some members of the NXP i.MX SoC family. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f0ff2612a6b3e37541387ab1206278ceeda70745..7d2d6ea5e90b9e4f96b937c980811a21e1f7bd7f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -24,7 +24,7 @@ config WATCHDOG_AUTOSTART config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" - default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 + default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SOCFPGA default 60000 @@ -147,6 +147,15 @@ config WDT_CORTINA This driver support all CPU ISAs supported by Cortina Access CAxxxx SoCs. +config WDT_GPIO + bool "External gpio watchdog support" + depends on WDT + depends on DM_GPIO + help + Support for external watchdog fed by toggling a gpio. See + doc/device-tree-bindings/watchdog/gpio-wdt.txt for + information on how to describe the watchdog in device tree. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx @@ -209,6 +218,26 @@ config WDT_K3_RTI Say Y here if you want to include support for the K3 watchdog timer (RTI module) available in the K3 generation of processors. +if WDT_K3_RTI + +config WDT_K3_RTI_LOAD_FW + bool "Load watchdog firmware" + depends on REMOTEPROC + help + Automatically load the specified firmware image into the MCU R5F + core 0. On the AM65x, this firmware is supposed to handle the expiry + of the watchdog timer, typically by resetting the system. + +config WDT_K3_RTI_FW_FILE + string "Watchdog firmware image file" + default "k3-rti-wdt.fw" + depends on WDT_K3_RTI_LOAD_FW + help + Firmware image to be embedded into U-Boot and loaded on watchdog + start. + +endif + config WDT_SANDBOX bool "Enable Watchdog Timer support for Sandbox" depends on SANDBOX && WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5c7ef593fe5325f0692d24bf15d0b6af67f69211..f14415bb8e3d861301cd4bcb48ef4fda9647d7a7 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o +obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..982a66b3f9d277f8ba53001445818fe0555e83f8 --- /dev/null +++ b/drivers/watchdog/gpio_wdt.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dm.h> +#include <dm/device_compat.h> +#include <wdt.h> +#include <asm/gpio.h> + +struct gpio_wdt_priv { + struct gpio_desc gpio; + bool always_running; + int state; +}; + +static int gpio_wdt_reset(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + + priv->state = !priv->state; + + return dm_gpio_set_value(&priv->gpio, priv->state); +} + +static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + + if (priv->always_running) + return 0; + + return -ENOSYS; +} + +static int dm_probe(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + int ret; + + priv->always_running = dev_read_bool(dev, "always-running"); + ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT); + if (ret < 0) { + dev_err(dev, "Request for wdt gpio failed: %d\n", ret); + return ret; + } + + if (priv->always_running) + ret = gpio_wdt_reset(dev); + + return ret; +} + +static const struct wdt_ops gpio_wdt_ops = { + .start = gpio_wdt_start, + .reset = gpio_wdt_reset, +}; + +static const struct udevice_id gpio_wdt_ids[] = { + { .compatible = "linux,wdt-gpio" }, + {} +}; + +U_BOOT_DRIVER(wdt_gpio) = { + .name = "wdt_gpio", + .id = UCLASS_WDT, + .of_match = gpio_wdt_ids, + .ops = &gpio_wdt_ops, + .probe = dm_probe, + .priv_auto = sizeof(struct gpio_wdt_priv), +}; diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index cebea426fbb618f9239b90227a900ec8655a9d61..c30ed8221740739281e149b3f64731118d6972d0 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -4,8 +4,8 @@ * Watchdog driver for Orion/Kirkwood processors * * Authors: Tomas Hlavacek <tmshlvck@gmail.com> - * Sylver Bruneau <sylver.bruneau@googlemail.com> - * Marek Behun <marek.behun@nic.cz> + * Sylver Bruneau <sylver.bruneau@googlemail.com> + * Marek Behun <marek.behun@nic.cz> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 8335b20ae8439acfd2d50ae8eafebc1909a166b8..253286d349b7fb85aa5cfa05322f57377dd5ccde 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -11,9 +11,11 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <dm/device_compat.h> #include <power-domain.h> #include <wdt.h> #include <asm/io.h> +#include <remoteproc.h> /* Timer register set definition */ #define RTIDWDCTRL 0x90 @@ -42,6 +44,88 @@ struct rti_wdt_priv { unsigned int clk_khz; }; +#ifdef CONFIG_WDT_K3_RTI_LOAD_FW +#define RTI_WDT_FIT_PATH "/fit-images/k3-rti-wdt-firmware" + +static int rti_wdt_load_fw(struct udevice *dev) +{ + struct udevice *rproc_dev; + int primary_core, ret; + u32 cluster_mode; + ofnode node; + u64 rti_wdt_fw; + u32 rti_wdt_fw_size; + + node = ofnode_path(RTI_WDT_FIT_PATH); + if (!ofnode_valid(node)) + goto fit_error; + + ret = ofnode_read_u64(node, "load", &rti_wdt_fw); + if (ret) + goto fit_error; + ret = ofnode_read_u32(node, "size", &rti_wdt_fw_size); + if (ret) + goto fit_error; + + node = ofnode_by_compatible(ofnode_null(), "ti,am654-r5fss"); + if (!ofnode_valid(node)) + goto dt_error; + + ret = ofnode_read_u32(node, "ti,cluster-mode", &cluster_mode); + if (ret) + cluster_mode = 1; + + node = ofnode_by_compatible(node, "ti,am654-r5f"); + if (!ofnode_valid(node)) + goto dt_error; + + ret = uclass_get_device_by_ofnode(UCLASS_REMOTEPROC, node, &rproc_dev); + if (ret) + return ret; + + primary_core = dev_seq(rproc_dev); + + ret = rproc_dev_init(primary_core); + if (ret) + goto fw_error; + + if (cluster_mode == 1) { + ret = rproc_dev_init(primary_core + 1); + if (ret) + goto fw_error; + } + + ret = rproc_load(primary_core, (ulong)rti_wdt_fw, + rti_wdt_fw_size); + if (ret) + goto fw_error; + + ret = rproc_start(primary_core); + if (ret) + goto fw_error; + + return 0; + +fit_error: + dev_err(dev, "No loadable firmware found under %s\n", RTI_WDT_FIT_PATH); + return -ENOENT; + +dt_error: + dev_err(dev, "No compatible firmware target processor found\n"); + return -ENODEV; + +fw_error: + dev_err(dev, "Failed to load watchdog firmware into remote processor %d\n", + primary_core); + return ret; +} +#else +static inline int rti_wdt_load_fw(struct udevice *dev) +{ + return 0; +} +#endif + static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct rti_wdt_priv *priv = dev_get_priv(dev); @@ -51,6 +135,10 @@ static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY) return -EBUSY; + ret = rti_wdt_load_fw(dev); + if (ret < 0) + return ret; + timer_margin = timeout_ms * priv->clk_khz / 1000; timer_margin >>= WDT_PRELOAD_SHIFT; if (timer_margin > WDT_PRELOAD_MAX) diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 17334dbda6c981f5a312f8dce432dcfd6986241b..7570710c4d91aa400af3243a92731a64d8c3bad5 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -20,53 +20,67 @@ DECLARE_GLOBAL_DATA_PTR; #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) -/* - * Reset every 1000ms, or however often is required as indicated by a - * hw_margin_ms property. - */ -static ulong reset_period = 1000; +struct wdt_priv { + /* Timeout, in seconds, to configure this device to. */ + u32 timeout; + /* + * Time, in milliseconds, between calling the device's ->reset() + * method from watchdog_reset(). + */ + ulong reset_period; + /* + * Next time (as returned by get_timer(0)) to call + * ->reset(). + */ + ulong next_reset; + /* Whether watchdog_start() has been called on the device. */ + bool running; +}; -int initr_watchdog(void) +static void init_watchdog_dev(struct udevice *dev) { - u32 timeout = WATCHDOG_TIMEOUT_SECS; + struct wdt_priv *priv; int ret; - /* - * Init watchdog: This will call the probe function of the - * watchdog driver, enabling the use of the device - */ - if (uclass_get_device_by_seq(UCLASS_WDT, 0, - (struct udevice **)&gd->watchdog_dev)) { - debug("WDT: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, - (struct udevice **)&gd->watchdog_dev)) { - printf("WDT: Not found!\n"); - return 0; - } - } - - if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { - timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec", - WATCHDOG_TIMEOUT_SECS); - reset_period = dev_read_u32_default(gd->watchdog_dev, - "hw_margin_ms", - 4 * reset_period) / 4; - } + priv = dev_get_uclass_priv(dev); if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) { - printf("WDT: Not starting\n"); - return 0; + printf("WDT: Not starting %s\n", dev->name); + return; } - ret = wdt_start(gd->watchdog_dev, timeout * 1000, 0); + ret = wdt_start(dev, priv->timeout * 1000, 0); if (ret != 0) { - printf("WDT: Failed to start\n"); + printf("WDT: Failed to start %s\n", dev->name); + return; + } + + printf("WDT: Started %s with%s servicing (%ds timeout)\n", dev->name, + IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", priv->timeout); +} + +int initr_watchdog(void) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_WDT, &uc); + if (ret) { + log_debug("Error getting UCLASS_WDT: %d\n", ret); return 0; } - printf("WDT: Started with%s servicing (%ds timeout)\n", - IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout); + uclass_foreach_dev(dev, uc) { + ret = device_probe(dev); + if (ret) { + log_debug("Error probing %s: %d\n", dev->name, ret); + continue; + } + init_watchdog_dev(dev); + } + gd->flags |= GD_FLG_WDT_READY; return 0; } @@ -79,8 +93,11 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) return -ENOSYS; ret = ops->start(dev, timeout_ms, flags); - if (ret == 0) - gd->flags |= GD_FLG_WDT_READY; + if (ret == 0) { + struct wdt_priv *priv = dev_get_uclass_priv(dev); + + priv->running = true; + } return ret; } @@ -94,8 +111,36 @@ int wdt_stop(struct udevice *dev) return -ENOSYS; ret = ops->stop(dev); - if (ret == 0) - gd->flags &= ~GD_FLG_WDT_READY; + if (ret == 0) { + struct wdt_priv *priv = dev_get_uclass_priv(dev); + + priv->running = false; + } + + return ret; +} + +int wdt_stop_all(void) +{ + struct wdt_priv *priv; + struct udevice *dev; + struct uclass *uc; + int ret, err; + + ret = uclass_get(UCLASS_WDT, &uc); + if (ret) + return ret; + + uclass_foreach_dev(dev, uc) { + if (!device_active(dev)) + continue; + priv = dev_get_uclass_priv(dev); + if (!priv->running) + continue; + err = wdt_stop(dev); + if (!ret) + ret = err; + } return ret; } @@ -120,10 +165,8 @@ int wdt_expire_now(struct udevice *dev, ulong flags) if (ops->expire_now) { return ops->expire_now(dev, flags); } else { - if (!ops->start) - return -ENOSYS; + ret = wdt_start(dev, 1, flags); - ret = ops->start(dev, 1, flags); if (ret < 0) return ret; @@ -141,18 +184,36 @@ int wdt_expire_now(struct udevice *dev, ulong flags) */ void watchdog_reset(void) { - static ulong next_reset; + struct wdt_priv *priv; + struct udevice *dev; + struct uclass *uc; ulong now; /* Exit if GD is not ready or watchdog is not initialized yet */ if (!gd || !(gd->flags & GD_FLG_WDT_READY)) return; - /* Do not reset the watchdog too often */ - now = get_timer(0); - if (time_after_eq(now, next_reset)) { - next_reset = now + reset_period; - wdt_reset(gd->watchdog_dev); + if (uclass_get(UCLASS_WDT, &uc)) + return; + + /* + * All devices bound to the wdt uclass should have been probed + * in initr_watchdog(). But just in case something went wrong, + * check device_active() before accessing the uclass private + * data. + */ + uclass_foreach_dev(dev, uc) { + if (!device_active(dev)) + continue; + priv = dev_get_uclass_priv(dev); + if (!priv->running) + continue; + /* Do not reset the watchdog too often */ + now = get_timer(0); + if (time_after_eq(now, priv->next_reset)) { + priv->next_reset = now + priv->reset_period; + wdt_reset(dev); + } } } #endif @@ -179,9 +240,38 @@ static int wdt_post_bind(struct udevice *dev) return 0; } +static int wdt_pre_probe(struct udevice *dev) +{ + u32 timeout = WATCHDOG_TIMEOUT_SECS; + /* + * Reset every 1000ms, or however often is required as + * indicated by a hw_margin_ms property. + */ + ulong reset_period = 1000; + struct wdt_priv *priv; + + if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { + timeout = dev_read_u32_default(dev, "timeout-sec", timeout); + reset_period = dev_read_u32_default(dev, "hw_margin_ms", + 4 * reset_period) / 4; + } + priv = dev_get_uclass_priv(dev); + priv->timeout = timeout; + priv->reset_period = reset_period; + /* + * Pretend this device was last reset "long" ago so the first + * watchdog_reset will actually call its ->reset method. + */ + priv->next_reset = get_timer(0); + + return 0; +} + UCLASS_DRIVER(wdt) = { - .id = UCLASS_WDT, - .name = "watchdog", - .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = wdt_post_bind, + .id = UCLASS_WDT, + .name = "watchdog", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .post_bind = wdt_post_bind, + .pre_probe = wdt_pre_probe, + .per_device_auto = sizeof(struct wdt_priv), }; diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index c8e6c60cdd2213fa8bf9d8810e8c1be441829b4c..d582e3cc8f41fd41e3b95550b249cba2480e2f0b 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -3,7 +3,7 @@ * Xilinx window watchdog timer driver. * * Author(s): Michal Simek <michal.simek@xilinx.com> - * Ashok Reddy Soma <ashokred@xilinx.com> + * Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> * * Copyright (c) 2020, Xilinx Inc. */ @@ -23,13 +23,22 @@ /* Generic Control/Status Register Masks */ #define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */ -/* Register offsets for the Wdt device */ -#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */ -#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */ -#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */ -#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */ -#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */ -#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */ +/* Register offsets for the WWDT device */ +#define XWT_WWDT_MWR_OFFSET 0x00 +#define XWT_WWDT_ESR_OFFSET 0x04 +#define XWT_WWDT_FCR_OFFSET 0x08 +#define XWT_WWDT_FWR_OFFSET 0x0c +#define XWT_WWDT_SWR_OFFSET 0x10 +#define XWT_WWDT_CNT_MIN 1 +#define XWT_WWDT_CNT_MAX 0xffffffff + +/* Master Write Control Register Masks */ +#define XWT_WWDT_MWR_MASK BIT(0) + +/* Enable and Status Register Masks */ +#define XWT_WWDT_ESR_WINT_MASK BIT(16) +#define XWT_WWDT_ESR_WSW_MASK BIT(8) +#define XWT_WWDT_ESR_WEN_MASK BIT(0) struct xlnx_wwdt_priv { bool enable_once; @@ -43,16 +52,23 @@ struct xlnx_wwdt_plat { static int xlnx_wwdt_reset(struct udevice *dev) { + u32 esr; struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); - regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK); + regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); + regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); + esr |= XWT_WWDT_ESR_WINT_MASK; + esr &= ~XWT_WWDT_ESR_WSW_MASK; + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); + regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); + esr |= XWT_WWDT_ESR_WSW_MASK; + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); return 0; } static int xlnx_wwdt_stop(struct udevice *dev) { - u32 csr; struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); if (wdt->enable_once) { @@ -60,10 +76,9 @@ static int xlnx_wwdt_stop(struct udevice *dev) return -EBUSY; } - /* Disable the generic watchdog timer */ - regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); - csr &= ~(XWT_WWCSR_GWEN_MASK); - regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + /* Disable the window watchdog timer */ + regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK); clk_disable(&wdt->clk); @@ -72,11 +87,11 @@ static int xlnx_wwdt_stop(struct udevice *dev) return 0; } -static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) +static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { int ret; - u32 csr; - u64 count; + u32 esr; + u64 count, timeout; unsigned long clock_f; struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); @@ -88,40 +103,52 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f); + /* Convert timeout from msec to sec */ + timeout = timeout_ms / 1000; + /* Calculate timeout count */ count = timeout * clock_f; + /* Count should be at least 1 */ + if (count < XWT_WWDT_CNT_MIN) { + debug("%s: watchdog won't fire with 0 ticks\n", __func__); + count = XWT_WWDT_CNT_MIN; + } + + /* Limit the count to maximum possible value */ + if (count > XWT_WWDT_CNT_MAX) { + debug("%s: maximum watchdog timeout exceeded\n", __func__); + count = XWT_WWDT_CNT_MAX; + } + ret = clk_enable(&wdt->clk); if (ret) { dev_err(dev, "failed to enable clock\n"); return ret; } - /* - * Timeout count is half as there are two windows - * first window overflow is ignored (interrupt), - * reset is only generated at second window overflow - */ - count = count >> 1; - - /* Disable the generic watchdog timer */ - regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); - csr &= ~(XWT_WWCSR_GWEN_MASK); - regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + /* Disable the window watchdog timer */ + regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK); - /* Set compare and offset registers for generic watchdog timeout */ - regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count); - regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0); - regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count); + /* Set first window and second window registers with timeout */ + regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */ + regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count); + regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0); - /* Enable the generic watchdog timer */ - regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); - csr |= (XWT_WWCSR_GWEN_MASK); - regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + /* Enable the window watchdog timer */ + regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); + esr |= XWT_WWDT_ESR_WEN_MASK; + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); return 0; } +static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags) +{ + return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags); +} + static int xlnx_wwdt_probe(struct udevice *dev) { int ret; @@ -160,6 +187,7 @@ static const struct wdt_ops xlnx_wwdt_ops = { .start = xlnx_wwdt_start, .reset = xlnx_wwdt_reset, .stop = xlnx_wwdt_stop, + .expire_now = xlnx_wwdt_expire_now, }; static const struct udevice_id xlnx_wwdt_ids[] = { diff --git a/drivers/xen/events.c b/drivers/xen/events.c index c490f87b2fca242ecf49bb8420f8789c9580faa7..5e90a6584640cf981e33e097d894d8495337c911 100644 --- a/drivers/xen/events.c +++ b/drivers/xen/events.c @@ -196,4 +196,3 @@ void fini_events(void) /* Dealloc all events */ unbind_all_ports(); } - diff --git a/drivers/xen/gnttab.c b/drivers/xen/gnttab.c index 778729d646e19f6b0a09e696dc74f5e36d72327c..31e96e2939c079c15e0641fc09ca184625e4d995 100644 --- a/drivers/xen/gnttab.c +++ b/drivers/xen/gnttab.c @@ -215,4 +215,3 @@ void fini_gnttab(void) setup.dom = DOMID_SELF; setup.nr_frames = 0; } - diff --git a/dts/Kconfig b/dts/Kconfig index dabe0080c1eff6e473e554bdc5cb10aa50b20a97..0cc562c626e0304c4215be5b4eec6a3cc5fa2ca1 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -44,10 +44,19 @@ config OF_CONTROL bool "Run-time configuration via Device Tree" select DTC select OF_LIBFDT if !OF_PLATDATA + select OF_REAL if !OF_PLATDATA help This feature provides for run-time configuration of U-Boot via a flattened device tree. +config OF_REAL + bool + help + Indicates that a real devicetree is available which can be accessed + at runtime. This means that dev_read_...() functions can be used to + read data from the devicetree for each device. This is true if + OF_CONTROL is enabled in U-Boot proper. + config OF_BOARD_FIXUP bool "Board-specific manipulation of Device Tree" help @@ -62,6 +71,7 @@ config SPL_OF_CONTROL bool "Enable run-time configuration via Device Tree in SPL" depends on SPL && OF_CONTROL select SPL_OF_LIBFDT if !SPL_OF_PLATDATA + select SPL_OF_REAL if !SPL_OF_PLATDATA help Some boards use device tree in U-Boot but only have 4KB of SRAM which is not enough to support device tree. Disable this option to @@ -71,6 +81,7 @@ config TPL_OF_CONTROL bool "Enable run-time configuration via Device Tree in TPL" depends on TPL && OF_CONTROL select TPL_OF_LIBFDT if !TPL_OF_PLATDATA + select TPL_OF_REAL if !TPL_OF_PLATDATA help Some boards use device tree in U-Boot but only have 4KB of SRAM which is not enough to support device tree. Enable this option to @@ -236,7 +247,7 @@ config MULTI_DTB_FIT config SPL_MULTI_DTB_FIT - depends on SPL_LOAD_FIT && SPL_OF_CONTROL && !SPL_OF_PLATDATA + depends on SPL_LOAD_FIT && SPL_OF_REAL bool "Support embedding several DTBs in a FIT image for the SPL" help This option provides the SPL with the ability to select its own @@ -374,6 +385,14 @@ config SPL_OF_PLATDATA compatible string, then adding platform data and U_BOOT_DRVINFO declarations for each node. See of-plat.txt for more information. +config SPL_OF_REAL + bool + help + Indicates that a real devicetree is available which can be accessed + at runtime. This means that dev_read_...() functions can be used to + read data from the devicetree for each device. This is true if + SPL_OF_CONTROL is enabled and not SPL_OF_PLATDATA + if SPL_OF_PLATDATA config SPL_OF_PLATDATA_PARENT @@ -421,6 +440,14 @@ config SPL_OF_PLATDATA_DRIVER_RT endif +config TPL_OF_REAL + bool + help + Indicates that a real devicetree is available which can be accessed + at runtime. This means that dev_read_...() functions can be used to + read data from the devicetree for each device. This is true if + TPL_OF_CONTROL is enabled and not TPL_OF_PLATDATA + config TPL_OF_PLATDATA bool "Generate platform data for use in TPL" depends on TPL_OF_CONTROL diff --git a/env/Kconfig b/env/Kconfig index c0dff1fd819546d3ac8a51ad57553d583053a142..f75f2b13536af6f1a059a10933f642e6ba10ea11 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -44,10 +44,6 @@ config ENV_IS_IN_EEPROM still be one byte because the extra address bits are hidden in the chip address. - - CONFIG_ENV_EEPROM_IS_ON_I2C - define this, if you have I2C and SPI activated, and your - EEPROM, which holds the environment, is on the I2C bus. - - CONFIG_I2C_ENV_EEPROM_BUS if you have an Environment on an EEPROM reached over I2C muxes, you can define here, how to reach this @@ -689,7 +685,6 @@ config ENV_FDT_PATH config ENV_APPEND bool "Always append the environment with new data" - default n help If defined, the environment hash table is only ever appended with new data, but the existing hash table can never be dropped and reloaded @@ -698,7 +693,6 @@ config ENV_APPEND config ENV_WRITEABLE_LIST bool "Permit write access only to listed variables" - default n help If defined, only environment variables which explicitly set the 'w' writeable flag can be written and modified at runtime. No variables @@ -706,7 +700,6 @@ config ENV_WRITEABLE_LIST config ENV_ACCESS_IGNORE_FORCE bool "Block forced environment operations" - default n help If defined, don't allow the -f switch to env set override variable access flags. diff --git a/env/eeprom.c b/env/eeprom.c index ba168014e24861f17bf9151890ed7d831a13b6f7..253bdf14284a36ef918fd635c275f29d63a2eed9 100644 --- a/env/eeprom.c +++ b/env/eeprom.c @@ -76,7 +76,7 @@ int env_eeprom_get_char(int index) if (gd->env_valid == ENV_REDUND) off = CONFIG_ENV_OFFSET_REDUND; #endif - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off + index + offsetof(env_t, data), &c, 1); return c; @@ -100,11 +100,11 @@ static int env_eeprom_load(void) for (i = 0; i < 2; i++) { /* read CRC */ - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off_env[i] + offsetof(env_t, crc), (uchar *)&crc[i], sizeof(ulong)); /* read FLAGS */ - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off_env[i] + offsetof(env_t, flags), (uchar *)&flags[i], sizeof(uchar)); @@ -114,7 +114,7 @@ static int env_eeprom_load(void) while (len > 0) { int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, rdbuf, n); crc_tmp = crc32(crc_tmp, rdbuf, n); @@ -156,7 +156,7 @@ static int env_eeprom_load(void) eeprom_init(-1); /* prepare for EEPROM read/write */ /* read old CRC */ - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_ENV_OFFSET + offsetof(env_t, crc), (uchar *)&crc, sizeof(ulong)); @@ -166,7 +166,7 @@ static int env_eeprom_load(void) while (len > 0) { int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_ENV_OFFSET + off, rdbuf, n); new = crc32(new, rdbuf, n); len -= n; @@ -186,7 +186,7 @@ static int env_eeprom_load(void) off = CONFIG_ENV_OFFSET_REDUND; #endif - eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, (uchar *)buf_env, CONFIG_ENV_SIZE); return env_import(buf_env, 1, H_EXTERNAL); @@ -215,12 +215,12 @@ static int env_eeprom_save(void) env_new.flags = ENV_REDUND_ACTIVE; #endif - rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR, + rc = eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR, off, (uchar *)&env_new, CONFIG_ENV_SIZE); #ifdef CONFIG_ENV_OFFSET_REDUND if (rc == 0) { - eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR, off_red + offsetof(env_t, flags), (uchar *)&flag_obsolete, 1); diff --git a/env/mmc.c b/env/mmc.c index 09e94f0bd3b182f991f8e307d9dd62b04b1fbe55..c4cb1639914be54199e1897ecd2f00320020a7ac 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -19,6 +19,7 @@ #include <part.h> #include <search.h> #include <errno.h> +#include <dm/ofnode.h> #define __STR(X) #X #define STR(X) __STR(X) @@ -73,7 +74,7 @@ static inline s64 mmc_offset(int copy) int err; /* look for the partition in mmc CONFIG_SYS_MMC_ENV_DEV */ - str = fdtdec_get_config_string(gd->fdt_blob, dt_prop.partition); + str = ofnode_conf_read_str(dt_prop.partition); if (str) { /* try to place the environment at end of the partition */ err = mmc_offset_try_partition(str, copy, &val); @@ -90,7 +91,7 @@ static inline s64 mmc_offset(int copy) propname = dt_prop.offset_redund; } #endif - return fdtdec_get_config_int(gd->fdt_blob, propname, defvalue); + return ofnode_conf_read_int(propname, defvalue); } #else static inline s64 mmc_offset(int copy) diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c index 52a243a659ffbb27af3982ec01d0c54aed881bf2..741c6e20f533cbe23a9256353c14d76ac19c284b 100644 --- a/fs/btrfs/btrfs.c +++ b/fs/btrfs/btrfs.c @@ -23,7 +23,7 @@ static int show_dir(struct btrfs_root *root, struct extent_buffer *eb, struct btrfs_key key; static const char* dir_item_str[] = { [BTRFS_FT_REG_FILE] = " ", - [BTRFS_FT_DIR] = "DIR", + [BTRFS_FT_DIR] = "DIR", [BTRFS_FT_CHRDEV] = "CHR", [BTRFS_FT_BLKDEV] = "BLK", [BTRFS_FT_FIFO] = "FIF", diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 12f9579fcf902a0d263682d853535bcac8b7d1dc..eb7736d53e11cfab4a70291162d8eb79eb305a1a 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -918,7 +918,11 @@ static int btrfs_scan_fs_devices(struct blk_desc *desc, ret = btrfs_scan_one_device(desc, part, fs_devices, &total_devs); if (ret) { - fprintf(stderr, "No valid Btrfs found\n"); + /* + * Avoid showing this when probing for a possible Btrfs + * + * fprintf(stderr, "No valid Btrfs found\n"); + */ return ret; } return 0; @@ -1007,7 +1011,7 @@ struct btrfs_fs_info *open_ctree_fs_info(struct blk_desc *desc, disk_super = fs_info->super_copy; ret = btrfs_read_dev_super(desc, part, disk_super); if (ret) { - printk("No valid btrfs found\n"); + debug("No valid btrfs found\n"); goto out_devices; } diff --git a/fs/btrfs/kernel-shared/btrfs_tree.h b/fs/btrfs/kernel-shared/btrfs_tree.h index 6a76d1e456fb3e9102143d376cd57bf08d0879d8..d8eff0b9122215b97dfe0f4a4f571545ef742d52 100644 --- a/fs/btrfs/kernel-shared/btrfs_tree.h +++ b/fs/btrfs/kernel-shared/btrfs_tree.h @@ -334,7 +334,6 @@ #define BTRFS_STRING_ITEM_KEY 253 - /* 32 bytes in various csum fields */ #define BTRFS_CSUM_SIZE 32 diff --git a/fs/jffs2/summary.h b/fs/jffs2/summary.h index 834933cd15846908e550793031bf8773282587f1..c8cba88529722ab959b6e5b9af2e329c5ba9956b 100644 --- a/fs/jffs2/summary.h +++ b/fs/jffs2/summary.h @@ -39,7 +39,7 @@ struct jffs2_sum_inode_flash __u32 inode; /* inode number */ __u32 version; /* inode version */ __u32 offset; /* offset on jeb */ - __u32 totlen; /* record length */ + __u32 totlen; /* record length */ } __attribute__((packed)); struct jffs2_sum_dirent_flash @@ -49,7 +49,7 @@ struct jffs2_sum_dirent_flash __u32 offset; /* offset on jeb */ __u32 pino; /* parent inode */ __u32 version; /* dirent version */ - __u32 ino; /* == zero for unlink */ + __u32 ino; /* == zero for unlink */ uint8_t nsize; /* dirent name size */ uint8_t type; /* dirent type */ uint8_t name[0]; /* dirent name */ @@ -94,7 +94,7 @@ struct jffs2_sum_inode_mem __u32 inode; /* inode number */ __u32 version; /* inode version */ __u32 offset; /* offset on jeb */ - __u32 totlen; /* record length */ + __u32 totlen; /* record length */ } __attribute__((packed)); struct jffs2_sum_dirent_mem @@ -105,7 +105,7 @@ struct jffs2_sum_dirent_mem __u32 offset; /* ofset on jeb */ __u32 pino; /* parent inode */ __u32 version; /* dirent version */ - __u32 ino; /* == zero for unlink */ + __u32 ino; /* == zero for unlink */ uint8_t nsize; /* dirent name size */ uint8_t type; /* dirent type */ uint8_t name[0]; /* dirent name */ @@ -155,7 +155,7 @@ struct jffs2_summary struct jffs2_sum_marker { __u32 offset; /* offset of the summary node in the jeb */ - __u32 magic; /* == JFFS2_SUM_MAGIC */ + __u32 magic; /* == JFFS2_SUM_MAGIC */ }; #define JFFS2_SUMMARY_FRAME_SIZE (sizeof(struct jffs2_raw_summary) + sizeof(struct jffs2_sum_marker)) diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 92ab8ac6310800a83ad3572c48d71d6ec008f8a9..e2d91c654cdfaf0e9106d2699e9f7066b51b3706 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -1090,7 +1090,7 @@ int sqfs_probe(struct blk_desc *fs_dev_desc, struct disk_partition *fs_partition /* Make sure it has a valid SquashFS magic number*/ if (get_unaligned_le32(&sblk->s_magic) != SQFS_MAGIC_NUMBER) { - printf("Bad magic number for SquashFS image.\n"); + debug("Bad magic number for SquashFS image.\n"); ret = -EINVAL; goto error; } diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 512fdaa1444d1155bcf260be3156c19ce65578d1..46dfbd0b5abaf1c8dab19a1a24096e18717cfcca 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -252,10 +252,10 @@ struct inode { }; struct super_operations { - struct inode *(*alloc_inode)(struct super_block *sb); + struct inode *(*alloc_inode)(struct super_block *sb); void (*destroy_inode)(struct inode *); - void (*dirty_inode) (struct inode *, int flags); + void (*dirty_inode) (struct inode *, int flags); int (*write_inode) (struct inode *, struct writeback_control *wbc); int (*drop_inode) (struct inode *); void (*evict_inode) (struct inode *); @@ -326,7 +326,7 @@ struct super_block { char s_id[32]; /* Informational name */ u8 s_uuid[16]; /* UUID */ - void *s_fs_info; /* Filesystem private info */ + void *s_fs_info; /* Filesystem private info */ unsigned int s_max_links; #ifndef __UBOOT__ fmode_t s_mode; @@ -431,7 +431,7 @@ struct file { #define f_dentry f_path.dentry #define f_vfsmnt f_path.mnt const struct file_operations *f_op; - unsigned int f_flags; + unsigned int f_flags; loff_t f_pos; unsigned int f_uid, f_gid; @@ -466,7 +466,7 @@ struct file { #if BITS_PER_LONG==32 #define MAX_LFS_FILESIZE (((u64)PAGE_CACHE_SIZE << (BITS_PER_LONG-1))-1) #elif BITS_PER_LONG==64 -#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL +#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL #endif /* diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e55070303fef18ad283ba73267d5973236ec386e..16fd305a65c1cd760202cd81b23563445469034c 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -277,7 +277,7 @@ struct global_data { */ void *trace_buff; #endif -#if defined(CONFIG_SYS_I2C_LEGACY) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) /** * @cur_i2c_bus: currently used I2C bus */ @@ -447,12 +447,6 @@ struct global_data { */ fdt_addr_t translation_offset; #endif -#if CONFIG_IS_ENABLED(WDT) - /** - * @watchdog_dev: watchdog device - */ - struct udevice *watchdog_dev; -#endif #ifdef CONFIG_GENERATE_ACPI_TABLE /** * @acpi_ctx: ACPI context pointer diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index e33cde7abdda95e4b797ef1316f1c267c399f837..6de13d925eb01b4cb7dfe191fbdf1adfe79cd1ca 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -608,6 +608,11 @@ int gpio_request_list_by_name(struct udevice *dev, const char *list_name, */ int dm_gpio_request(struct gpio_desc *desc, const char *label); +struct phandle_2_arg; +int gpio_request_by_phandle(struct udevice *dev, + const struct phandle_2_arg *cells, + struct gpio_desc *desc, int flags); + /** * gpio_get_list_count() - Returns the number of GPIOs in a list * diff --git a/include/atsha204a-i2c.h b/include/atsha204a-i2c.h index 344fd8ace7d4f992cf5b60ac6148186cecb761a6..39fc0e9ca7259ac5f9b4dcc1a1fe6c8c6382527e 100644 --- a/include/atsha204a-i2c.h +++ b/include/atsha204a-i2c.h @@ -2,8 +2,8 @@ * I2C Driver for Atmel ATSHA204 over I2C * * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com - * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com - * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com + * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as diff --git a/include/clk.h b/include/clk.h index f3c88fe68aa8303985a49ea1f95d026d37bb6b2f..a928879b12225ba5b3acd98ed6d8f900a8aaf01e 100644 --- a/include/clk.h +++ b/include/clk.h @@ -89,11 +89,36 @@ struct clk_bulk { #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) struct phandle_1_arg; -int clk_get_by_driver_info(struct udevice *dev, - struct phandle_1_arg *cells, struct clk *clk); +/** + * clk_get_by_phandle() - Get a clock by its phandle information (of-platadata) + * + * This function is used when of-platdata is enabled. + * + * This looks up a clock using the phandle info. With dtoc, each phandle in the + * 'clocks' property is transformed into an idx representing the device. For + * example: + * + * clocks = <&dpll_mpu_ck 23>; + * + * might result in: + * + * .clocks = {1, {23}},}, + * + * indicating that the clock is udevice idx 1 in dt-plat.c with an argument of + * 23. This function can return a valid clock given the above information. In + * this example it would return a clock containing the 'dpll_mpu_ck' device and + * the clock ID 23. + * + * @dev: Device containing the phandle + * @cells: Phandle info + * @clock: A pointer to a clock struct to initialise + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, + struct clk *clk); /** - * clk_get_by_index - Get/request a clock by integer index. + * clk_get_by_index() - Get/request a clock by integer index. * * This looks up and requests a clock. The index is relative to the client * device; each device is assumed to have n clocks associated with it somehow, @@ -300,9 +325,7 @@ enum clk_defaults_stage { CLK_DEFAULTS_POST_FORCE, }; -#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ - CONFIG_IS_ENABLED(CLK) - +#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(CLK) /** * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}' * properties to configure clocks diff --git a/include/clock_legacy.h b/include/clock_legacy.h index b0a8333ea6ebeb97f12292cc1ed995ffc7aa0181..29261b680d0025aad79dcb9f7b99ba68596bb1fb 100644 --- a/include/clock_legacy.h +++ b/include/clock_legacy.h @@ -11,4 +11,15 @@ int get_clocks(void); unsigned long get_bus_freq(unsigned long dummy); int get_serial_clock(void); +/* + * If we have CONFIG_DYNAMIC_DDR_CLK_FREQ then there will be an + * implentation of get_board_ddr_clk() somewhere. Otherwise we have + * a static value to use now. + */ +#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ +unsigned long get_board_ddr_clk(void); +#else +#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ +#endif + #endif diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index aaf016c0459c31f8d9748742d518e24c478e5139..167d44e400f305127bf5f24214942a1a3eb05d13 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -46,10 +46,4 @@ #define CONFIG_SYS_MAXARGS 16 #endif -#if CONFIG_IS_ENABLED(DM_I2C) -# ifdef CONFIG_SYS_I2C_LEGACY -# error "Cannot define CONFIG_SYS_I2C_LEGACY when CONFIG_DM_I2C is used" -# endif -#endif - #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 3ffc744928f3e987ec5bfa1128b3c894ffd61086..709a449e7966641de94043f995cb3cd80f11ec0f 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -57,10 +56,5 @@ * (which is common practice). */ -/* - * MISC - */ -#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 3f065ff315cd163483079986c269e27bfa4f22bc..f7ad7efb0dd04e28cee1680d4144191441977d5d 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -57,10 +56,5 @@ * (which is common practice). */ -/* - * MISC - */ -#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 1b8312bbc07db5489c66d52de2b787d35dc8771e..e0c8d361d161270c37ea4363c08bba4ad4a85f97 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -40,11 +40,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -71,8 +66,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ #define CONFIG_SYS_PLL_ODR 0x36 #define CONFIG_SYS_PLL_FDR 0x7D @@ -108,7 +101,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -138,7 +130,6 @@ env/embedded.o(.text*); /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index d061f4587082dfc2dc563f19b1c4b46542136b30..f983281cc1f0f1028edd30a602679ead57888815 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -49,11 +49,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_i2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) @@ -83,8 +78,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) - #define CONFIG_SYS_CLK 75000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 @@ -116,7 +109,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -154,7 +146,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 1a1a11076543f5f0aaa0c97e6023166cfdeff88c..7015f790dee5317882054a3b0711e4c8ed2f3f86 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -31,8 +31,6 @@ */ #undef CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - /* * Clock configuration: enable only one of the following options */ @@ -78,7 +76,6 @@ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -104,7 +101,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 8ac0086629dabbd6b43c4d6765c82e12725c9cad..d892cbb5085899e3ad66ffbc27d08178141a8d60 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -70,18 +70,11 @@ #define CONFIG_HOSTNAME "M5253DEMO" /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) #define CONFIG_SYS_I2C_PINMUX_SET (0) -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ #define CONFIG_SYS_FAST_CLK #ifdef CONFIG_SYS_FAST_CLK @@ -124,7 +117,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) /* @@ -160,7 +152,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 2cdd4369da002be3f4fcba53f0ec4e19f8f668ba..01c8ac6dd62a7402b9844d0cc6a9f38ffe8720f1 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -75,7 +75,6 @@ "save\0" \ "" -#define CONFIG_SYS_LOAD_ADDR 0x20000 #define CONFIG_SYS_CLK 66000000 /* @@ -111,7 +110,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -134,7 +132,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index eb7823a98a58e24734278b771935049f2b62ce0b..35048613b9f7e38831149a2469c19a7665a4454d 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -59,18 +59,11 @@ #endif /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) -#define CONFIG_SYS_LOAD_ADDR 0x800000 - #define CONFIG_BOOTCOMMAND "bootm ffe40000" #ifdef CONFIG_MCFFEC @@ -124,7 +117,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -147,7 +139,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 6a50a25d325431cdf8abbb284bf2eb6cec6a0a9a..fde108404458859ec520ee45d0c7d8ae345e53e7 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -72,8 +72,6 @@ "save\0" \ "" -#define CONFIG_SYS_LOAD_ADDR 0x20000 - #define CONFIG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ @@ -116,7 +114,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -142,7 +139,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index a063b92a643fdaa77f58cdfb6525a852e97753b9..2e5b82a5f53359f2f2f85d2d1832ffe2b55f101e 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -55,11 +55,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -86,8 +81,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 @@ -124,7 +117,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -158,7 +150,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 4fc6d38192497a04d1e8886bb6ded494a75b4fc9..e3e7d8b7e0eb0b40ae95bc888fec08da8daa778e 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -49,11 +49,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -80,8 +75,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 @@ -120,7 +113,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -165,7 +157,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 7a9240a5717111d12589e2ad61aef9a13dbf1c9a..256a66fb0575e3cbf8331e197af988da828df781 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -51,11 +51,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -82,8 +77,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 @@ -122,7 +115,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -167,7 +159,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 48e9ecdb80168f5ccecf760cd00285dd4c6b45d5..65c16380ee5203697edf57d1ea81fca3511ee120 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -60,8 +60,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 - #define CONFIG_SYS_HZ 1000 /* Definitions for initial stack pointer and data area (in DPRAM) */ @@ -86,7 +84,6 @@ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) #define CONFIG_SYS_MONITOR_LEN (320 << 10) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Environment Configuration */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h deleted file mode 100644 index b4e1cae893856b931ad81a7ab8abb186cc1d15a5..0000000000000000000000000000000000000000 --- a/include/configs/MPC8349EMDS.h +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * DDR Setup - */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver - * unselect it to use old spd_sdram.c - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#undef CONFIG_DDR_2T_TIMING - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif -#endif -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CONFIG_SYS_BCSR 0xE2400000 - /* Access window base at BCSR base */ - - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* SPI */ -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* USB */ -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_83XX_PCI_STREAMING - - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* - * System performance - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "mpc8349emds" -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc834x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h deleted file mode 100644 index 7924cbc8a3ee9de38c42ceb01dd4a836f84553a2..0000000000000000000000000000000000000000 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ /dev/null @@ -1,426 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * DDR Setup - */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver - * unselect it to use old spd_sdram.c - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#undef CONFIG_DDR_2T_TIMING - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif -#endif -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CONFIG_SYS_BCSR 0xE2400000 - /* Access window base at BCSR base */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. - */ - -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* SPI */ -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* USB */ -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_83XX_PCI_STREAMING - - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* - * System performance - */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "mpc8349emds" -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc834x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a13b178d6afece1e1fbab0fd759cc4dd3daaee12..72119a1cf04b711cfa4e0193a340ca0084ea94f2 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -66,9 +66,6 @@ #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ /* @@ -113,17 +110,9 @@ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ -#if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE \ - | SDRAM_CFG_2T_EN) - /* 0x43088000 */ -#else #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) @@ -147,7 +136,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -203,11 +191,6 @@ #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* @@ -329,7 +312,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -339,10 +321,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -361,9 +339,6 @@ #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_FDTFILE "mpc8379_rdb.dtb" - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" CONFIG_NETDEV "\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ @@ -390,7 +365,7 @@ "$netdev:off " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ "run setbootargs;" \ "run setipargs;" \ @@ -398,7 +373,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv rootdev /dev/ram;" \ "run setbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 549fbfa65c7b41aa7af68ce3e8640542ae397cfd..fe156e7815788e1fd661deff6bd764059b89fe3a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -61,7 +61,6 @@ /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -189,7 +188,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -205,11 +203,6 @@ /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* RapidIO MMU */ @@ -286,7 +279,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -296,10 +288,6 @@ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -321,8 +309,6 @@ #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ @@ -331,7 +317,7 @@ "fdtaddr=400000\0" \ "fdtfile=your.fdt.dtb\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -340,7 +326,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -348,6 +334,6 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d3e5da0c43ac81504df9911a1cf848345653387e..5c54bad4964f86d3c0bc1a899b27ba572e933c78 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -45,10 +45,7 @@ extern unsigned long get_clock_freq(void); /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ @@ -278,7 +275,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -295,23 +291,13 @@ extern unsigned long get_clock_freq(void); * I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #else #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 #endif -#define CONFIG_SYS_I2C_FSL /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_CCID -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * General PCI @@ -420,7 +406,6 @@ extern unsigned long get_clock_freq(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -430,10 +415,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -455,8 +436,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ @@ -478,7 +457,7 @@ extern unsigned long get_clock_freq(void); "fdtaddr=1e00000\0" \ "fdtfile=mpc8548cds.dtb\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -487,7 +466,7 @@ extern unsigned long get_clock_freq(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -495,6 +474,6 @@ extern unsigned long get_clock_freq(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 5254936a4b2646df0b72a7912d99ea5fc8b4e29f..3a9ea03292175e70ef6be44d7fa4b02000ab20cc 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -28,7 +28,6 @@ */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* @@ -62,7 +61,6 @@ /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -190,7 +188,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ @@ -202,11 +199,6 @@ /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* RapidIO MMU */ @@ -258,50 +250,6 @@ #endif /* CONFIG_TSEC_ENET */ -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ - -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - /* * Environment */ @@ -319,7 +267,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ @@ -331,14 +278,10 @@ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -355,8 +298,6 @@ #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyCPM\0" \ @@ -365,7 +306,7 @@ "fdtaddr=400000\0" \ "fdtfile=mpc8560ads.dtb\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -374,7 +315,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -382,6 +323,6 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b7e44d1737397e8e9933ba447cea2042a28a8c05..922f0661aba28cc3b39b6d22eec3fafeb8b5f038 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -153,7 +153,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ #define CONFIG_HWCONFIG @@ -168,7 +167,6 @@ /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 @@ -443,7 +441,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ /* * Config the L2 Cache as L2 SRAM @@ -497,38 +494,19 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif #define I2C_PCA9557_ADDR1 0x18 #define I2C_PCA9557_ADDR2 0x19 #define I2C_PCA9557_BUS_NUM 0 -#define CONFIG_SYS_I2C_FSL /* I2C EEPROM */ #if defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #endif -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ #endif /* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -632,7 +610,6 @@ extern unsigned long get_sdram_size(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -642,10 +619,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -660,9 +633,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ @@ -715,7 +685,7 @@ extern unsigned long get_sdram_size(void); "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" #endif -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs; " \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -723,7 +693,7 @@ extern unsigned long get_sdram_size(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#define CONFIG_BOOTCOMMAND RAMBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 4ef061343c1f89860033009f8748bb6a8833d30d..1e75066eb1c99809ad3f02776717a4fb434db70c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -14,8 +14,6 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -88,11 +86,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * DDR Setup @@ -104,8 +99,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -240,7 +233,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -259,19 +251,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* @@ -478,7 +457,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -488,10 +466,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -499,9 +473,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -525,14 +496,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); "fdtfile=p2041rdb/p2041rdb.dtb\0" \ "bdev=sda3\0" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -541,7 +512,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -549,7 +520,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#define CONFIG_BOOTCOMMAND HDBOOT #include <asm/fsl_secure_boot.h> diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index ded494cfa9b0dfac87a159deb59bcbbc2003c7e5..fc6167cf9699dd5c495b368c3e0b857488392f43 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -11,7 +11,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg /* additions for new ARM relocation support */ @@ -38,15 +37,6 @@ * for your console driver. */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" #define CONFIG_DOS_PARTITION @@ -60,13 +50,7 @@ */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ @@ -89,6 +73,4 @@ #define CONFIG_PHY_BASE_ADR 0x01 #endif /* CONFIG_CMD_NET */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - #endif /* _CONFIG_SBX81LIFKW_H */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 06bbd8642e3f51770630accc270ae781084f4215..06be63e2421e8c9a268e8927505b45d6b3c61776 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -11,7 +11,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg /* additions for new ARM relocation support */ @@ -38,15 +37,6 @@ * for your console driver. */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" #define CONFIG_DOS_PARTITION @@ -60,7 +50,6 @@ */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ /* * For booting Linux, the board info and command line data @@ -89,6 +78,4 @@ #define CONFIG_PHY_BASE_ADR 0x01 #endif /* CONFIG_CMD_NET */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - #endif /* _CONFIG_SBX81LIFXCAT_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 187304419e6f52d221100293b267b2712e5a9be5..e4629946ddb157675c3f7cbcb4c188a693fddc79 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -26,7 +26,6 @@ #endif #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -43,11 +42,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg -#endif #endif #ifdef CONFIG_SPIFLASH @@ -60,11 +54,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg -#endif #endif #ifdef CONFIG_SDCARD @@ -76,11 +65,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -134,11 +118,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 /* * These can be toggled for performance analysis, otherwise use default. @@ -147,9 +129,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -170,13 +150,8 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * DDR Setup @@ -187,7 +162,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -392,7 +366,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -422,20 +395,7 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20 @@ -615,7 +575,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -625,17 +584,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ #define __USB_PHY_TYPE utmi #ifdef CONFIG_ARCH_T1024 @@ -668,7 +622,7 @@ unsigned long get_board_ddr_clk(void); "fdtaddr=1e00000\0" \ "bdev=sda3\0" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -676,7 +630,7 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -685,7 +639,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index fb215bb05fbac357e59e1e7074e0681173b44c7c..7c48c3af71fcbddcbec54ea89a73ba9885cacb94 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -15,14 +15,6 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL - -#ifndef CONFIG_NXP_ESBC -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg -#else -#define CONFIG_SYS_FSL_PBL_PBI \ - $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg -#endif - #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -49,26 +41,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg -#endif #endif #ifdef CONFIG_SPIFLASH @@ -81,26 +53,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg -#endif #endif #ifdef CONFIG_SDCARD @@ -112,26 +64,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg -#endif #endif #endif @@ -164,7 +96,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66666666 /* * These can be toggled for performance analysis, otherwise use default. @@ -173,9 +104,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -211,8 +140,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -421,7 +348,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -452,26 +378,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C3_SPEED 400000 -#define CONFIG_SYS_FSL_I2C4_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 @@ -676,7 +583,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -686,10 +592,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Dynamic MTD Partition support with mtdparts */ @@ -701,9 +603,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" @@ -746,7 +645,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "fdtfile=" __stringify(FDTFILE) "\0" \ "bdev=sda3\0" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -754,14 +653,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -770,7 +669,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -778,7 +677,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f61b40fb3bd7e1d6959677050eee152de2d2d0d0..57640acfc90be4775eca1d2f931ab7a9e04f89f9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg - #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -47,9 +45,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#endif #endif #ifdef CONFIG_SPIFLASH @@ -62,9 +57,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#endif #endif #ifdef CONFIG_SDCARD @@ -76,9 +68,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -101,19 +90,15 @@ */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* * Config the L3 Cache as L3 SRAM @@ -130,11 +115,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* * DDR Setup @@ -144,7 +126,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -352,7 +333,6 @@ unsigned long get_board_ddr_clk(void); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * Serial Port @@ -370,23 +350,6 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#endif - -#define CONFIG_SYS_I2C_FSL #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ @@ -613,7 +576,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -623,11 +585,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* * Environment Configuration */ @@ -635,8 +592,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -664,7 +619,7 @@ unsigned long get_board_ddr_clk(void); * For emulation this causes u-boot to jump to the start of the * proof point app code automatically */ -#define CONFIG_PROOF_POINTS \ +#define PROOF_POINTS \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x29000000 - - -;" \ @@ -676,11 +631,11 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x29000000 - - -;" \ "go 0x29000000" -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_ALU \ +#define ALU \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x01000000 - - -;" \ @@ -692,7 +647,7 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x01000000 - - -;" \ "go 0x01000000" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -700,14 +655,14 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -716,7 +671,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -724,7 +679,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 601e67c80c308434d5405ac3970a9247f16270c4..6f27386d2bac9407bf22ab00bf056952b388cb88 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg - #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -42,7 +40,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg #endif #ifdef CONFIG_SPIFLASH @@ -55,7 +52,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg #endif #ifdef CONFIG_SDCARD @@ -67,7 +63,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -90,19 +85,15 @@ */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 66660000 -#define CONFIG_DDR_CLK_FREQ 133330000 /* * Config the L3 Cache as L3 SRAM @@ -119,11 +110,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * DDR Setup @@ -133,7 +121,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -304,7 +291,6 @@ unsigned long get_board_ddr_clk(void); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * Serial Port @@ -322,26 +308,6 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif - -#define CONFIG_SYS_I2C_FSL #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ @@ -565,7 +531,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -575,11 +540,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* * Environment Configuration */ @@ -587,8 +547,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -616,7 +574,7 @@ unsigned long get_board_ddr_clk(void); * For emulation this causes u-boot to jump to the start of the * proof point app code automatically */ -#define CONFIG_PROOF_POINTS \ +#define PROOF_POINTS \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x29000000 - - -;" \ @@ -628,11 +586,11 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x29000000 - - -;" \ "go 0x29000000" -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_ALU \ +#define ALU \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x01000000 - - -;" \ @@ -644,7 +602,7 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x01000000 - - -;" \ "go 0x01000000" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -652,14 +610,14 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -668,7 +626,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -676,7 +634,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index c796b1d7ed0552703dbe60dd3ccfaa472d4060b9..b7cbf87d3062c3a8b41288eaea827a50f9bff4c5 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -18,7 +18,6 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg #ifndef CONFIG_SDCARD #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc @@ -38,7 +37,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg #endif #ifdef CONFIG_SPL_BUILD @@ -50,8 +48,6 @@ #endif #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_DDR_ECC - /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ @@ -72,7 +68,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -102,8 +97,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD - /* * IFC Definitions */ @@ -135,7 +128,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -154,18 +146,6 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif - -#define CONFIG_SYS_I2C_FSL /* * General PCI @@ -225,7 +205,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -235,10 +214,6 @@ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -246,19 +221,14 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" #define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ 133333333 #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif /* @@ -429,8 +399,6 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ -#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ @@ -600,11 +568,11 @@ unsigned long get_board_ddr_clk(void); "fdtfile=t4240rdb/t4240rdb.dtb\0" \ "bdev=sda3\0" -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -612,14 +580,14 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -628,7 +596,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -636,7 +604,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index a7adb599cae4979d2c95515515b494d4cae80817..b6a78b1370efd4d714b3a9948f450d4825081da5 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -15,8 +15,6 @@ */ #define CONFIG_USE_INTERRUPT -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_SKIP_TRUNOFF_WATCHDOG #define CONFIG_ARCH_MAP_SYSMEM @@ -86,7 +84,6 @@ * Size of malloc() pool */ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* * Physical Memory Map @@ -104,14 +101,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ GENERATED_GBL_DATA_SIZE) -/* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ - /* * Static memory controller configuration */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index afec9ba24253fe21562240dbb4a9166512c11c6f..3e78d5ce17053a2ca56a857ce52f00354ed99f30 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -15,8 +15,6 @@ */ #define CONFIG_USE_INTERRUPT -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_ARCH_MAP_SYSMEM #define CONFIG_BOOTP_SERVERIP @@ -84,12 +82,6 @@ * Miscellaneous configurable options */ -/* - * Size of malloc() pool - */ -/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - /* * AHB Controller configuration */ @@ -216,14 +208,6 @@ GENERATED_GBL_DATA_SIZE) #endif /* CONFIG_MEM_REMAP */ -/* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ - /* * Static memory controller configuration */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ad5616d28fbd2f31349f0bfe1b8999170b83baf7..0f6ffd9ba7c2c2d7230af7e64a1d60f4841ff8fa 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_16M -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -168,10 +166,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* PMIC support */ #define CONFIG_POWER_TPS65217 #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index c161b9335235cae8cbe7ca22854279b58ef74c94..d93db09c9b5ef7d466642de8983b7e4288d142af 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -22,8 +22,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 387d50d51199bb4daa465266f76634b44c92e890..584b0250c4cca0c1f133f5b6017b6bdddfc01422 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -223,10 +223,4 @@ #endif #define CONFIG_NET_RETRY_COUNT 10 - -/* I2C configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 #endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 16849d8701149468858c4354258a557eb059e5df..dff946801c6f10aa59c453b6a7ed20dd6a0468c9 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) -/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -55,10 +53,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* PMIC support */ #define CONFIG_POWER_TPS65217 #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index a9c14a1ce28ba2fc5b668d79a1317347ce891320..e54708ccb5a1ff006882e882804822e9f6a3c1a2 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -14,23 +14,6 @@ #include <configs/ti_omap3_common.h> -#define CONFIG_REVISION_TAG - -/* Hardware drivers */ - -/* - * USB configuration - * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard - * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_USB_EHCI_OMAP -#else -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 -#endif - -/* I2C */ - /* Ethernet */ #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 31a1c7e392f275c1857c4df0fdb6868cd5fce9a1..00426597ee57a896b0c4d507cb5327f0c906efcc 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -21,15 +21,8 @@ #endif /* I2C Configuration */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Power */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#endif #define CONFIG_POWER_TPS65218 #define CONFIG_POWER_TPS62362 @@ -41,14 +34,6 @@ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* * When building U-Boot such that there is no previous loader * we need to call board_early_init_f. This is taken care of in @@ -69,12 +54,9 @@ #if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_AM437X_USB2PHY2_HOST #endif -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER) +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_GADGET) #undef CONFIG_USB_DWC3_PHY_OMAP #undef CONFIG_USB_DWC3_OMAP #undef CONFIG_USB_DWC3 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c47ffccff1597cbebaad8494cd29ad2bf458336b..956844414f86389e42bc45554db822dd248a94ff 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -22,10 +22,6 @@ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - #define CONFIG_SYS_OMAP_ABE_SYSCK #ifndef CONFIG_SPL_BUILD @@ -52,11 +48,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ -/* USB xHCI HOST */ -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_OMAP_USB3PHY1_HOST - /* SATA */ #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 57cd520234b524edc6e742e58d13eca6bdc101ff..99624081c3ed8f81f4c83f8f8ed3a2b7b1a4ca62 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -22,10 +22,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#ifndef CONFIG_CPU_V7R -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #if defined(CONFIG_TARGET_AM642_A53_EVM) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index d4514a0dbada7cca033b9c86977214c9cb024f24..55fa6419e33d4e9f1a12763bf1edcddc5fdfd48a 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -49,10 +49,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#ifndef CONFIG_CPU_V7R -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #define CONFIG_SYS_BOOTM_LEN SZ_64M diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 641d8fdbd53dbc8546ba1014796b7f094ab8b916..98ad047bc4cdf08198877c77646269208a5f6331 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -13,7 +13,6 @@ #define CONFIG_MCFTMR #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT 0 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_BOOTCOMMAND "bootm ffc20000" #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -28,10 +27,6 @@ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0" -/* undef to save memory */ - -#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ - #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 45000000 @@ -58,7 +53,6 @@ /* reserve 128-4KB */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) #define LDS_BOARD_TEXT \ @@ -75,7 +69,6 @@ * This is a single unified instruction/data cache. * sdram - single region - no masks */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) @@ -99,4 +92,3 @@ #define CONFIG_SYS_CS1_CTRL 0x0100 #endif /* __AMCORE_CONFIG_H */ - diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 4902d07247e69c7af123f804418b9bb3df77e518..f3fc53ba484f03091be01e51b139b16b7f500b56 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -12,20 +12,15 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} - #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ "bootm 0x9f650000" diff --git a/include/configs/ap143.h b/include/configs/ap143.h index c79e050dc9c5315096e834c67a6c86d9e508edbf..fa13a801b7716787b7aa93df06cf6a3534c57036 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -12,11 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 @@ -27,8 +25,6 @@ * Serial Port */ #define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 0d2c484bb9c1539a0008d9c684ee5e15d2c62d2e..3eaf19283bba6dbc37a82872da54bfc22b55d696 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -12,11 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 @@ -27,8 +25,6 @@ * Serial Port */ #define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index b04a03f76da048690379fc67c6520f2b9a8e24d8..80594548877beb2154850a63ede05702e7d02d75 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -18,8 +18,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Networking */ #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 @@ -70,9 +68,6 @@ "${blkcnt}; fi\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -83,9 +78,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h index 2ad4ca34188ce5510ae8eac4796dea4786c25798..cd002235ec4a0b0315d152c9e64b74cc33acc446 100644 --- a/include/configs/apalis-imx8x.h +++ b/include/configs/apalis-imx8x.h @@ -17,8 +17,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -97,9 +95,6 @@ "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x89000000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -112,9 +107,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 12de0105c6c73d8713283e7c7150887c2e66ebcd..23fca1e447be59b06687040d74fa400d1786a8e6 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -14,8 +14,6 @@ #undef CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MACH_TYPE 4886 - #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> @@ -23,25 +21,8 @@ #include "imx6_spl.h" #endif -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - #define CONFIG_MXC_UART_BASE UART1_BASE -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -80,8 +61,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_LOADADDR 0x12000000 - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -162,7 +141,7 @@ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" /* Miscellaneous configurable options */ @@ -171,8 +150,6 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 48 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 9e5f5236002aba6e9fc3d9c215ff74de78d45273..eab4f22be34e8dfe536e10b133fbcb103e00b0dc 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -23,8 +23,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 - /* PCI networking support */ #define CONFIG_E1000_NO_NVM diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 78fa1a969e7f953dc9aa6fe601374a984a853c7a..b73b0d5b92b3ea5130ae64a7f6cf3b1945b11c4e 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -28,7 +28,6 @@ #include "mx6_common.h" -#define CONFIG_MACH_TYPE 4501 #define CONFIG_MMCROOT "/dev/mmcblk0p1" /* MMC Configs */ @@ -93,13 +92,13 @@ #endif #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ +#define EXTRA_ENV_BOARD_SETTINGS \ "dead=while true; do; " \ "led led_red on; sleep 1;" \ "led led_red off; sleep 1;" \ "done\0" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ +#define EXTRA_ENV_BOARD_SETTINGS \ "dead=while true; do; " \ "led led_red on; led led_red2 on; sleep 1;" \ "led led_red off; led led_red2 off;; sleep 1;" \ @@ -414,7 +413,7 @@ "run main_rescue_boot;" \ "fi; \0"\ HAB_EXTRA_SETTINGS \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS + EXTRA_ENV_BOARD_SETTINGS #define CONFIG_ARP_TIMEOUT 200UL diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 06704e5e1971a9c4ced67996379eaa4f3669c37f..73f63c5a9f005f4d3573e765a1fba7cf73471fd3 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -44,12 +44,9 @@ #define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) #define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 64 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index df0f5d2e76f7995c2317eb58af88b5fdc1fa1f64..5177bf20fad4ccddf7387462a721a98d78131c81 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -13,9 +13,6 @@ #include <asm/arch/platform.h> /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG #define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE @@ -32,8 +29,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (32 << 20) - /* * NS16550 Configuration */ diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h deleted file mode 100644 index 88e1bf17753458d2a839e94524b8aaeff6f3320d..0000000000000000000000000000000000000000 --- a/include/configs/aspenite.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * Contributor: Mahavir Jain <mjain@marvell.com> - */ - -#ifndef __CONFIG_ASPENITE_H -#define __CONFIG_ASPENITE_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */ -#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) - -#include "mv-common.h" - -/* - * Environment variables configurations - */ - -#endif /* __CONFIG_ASPENITE_H */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 2ea33e5eff22db30c1627bef24d990c41e2983e7..077af08c2beab9ae336aecadbc334bdd30c5a7c4 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -22,17 +22,17 @@ * set the card type to actually compile for; either of * the possibilities listed below has to be used! */ -#define CONFIG_ASTRO_V532 1 +#define ASTRO_V532 1 -#if CONFIG_ASTRO_V532 +#if ASTRO_V532 #define ASTRO_ID 0xF8 -#elif CONFIG_ASTRO_V512 +#elif ASTRO_V512 #define ASTRO_ID 0xFA -#elif CONFIG_ASTRO_TWIN7S2 +#elif ASTRO_TWIN7S2 #define ASTRO_ID 0xF9 -#elif CONFIG_ASTRO_V912 +#elif ASTRO_V912 #define ASTRO_ID 0xFC -#elif CONFIG_ASTRO_COFDMDUOS2 +#elif ASTRO_COFDMDUOS2 #define ASTRO_ID 0xFB #else #error No card type defined! @@ -58,11 +58,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* @@ -149,7 +144,7 @@ #ifdef CONFIG_MONITOR_IS_IN_RAM #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ #else -#if CONFIG_ASTRO_V532 +#if ASTRO_V532 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ "run xilinxload&&run alteraload&&bootm 0x80000;"\ "update;reset" @@ -159,9 +154,6 @@ #endif #endif -/* default RAM address for user programs */ -#define CONFIG_SYS_LOAD_ADDR 0x20000 - #define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 @@ -240,8 +232,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -/* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* * For booting Linux, the board info and command line data @@ -272,7 +262,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index ba21149e43ca2c563fb4af39b1b0ee45d92959ce..9a73e3afca50a1b6adb6c1892681e3eb526fde8f 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -15,10 +15,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* * BOOTP options */ @@ -54,7 +50,4 @@ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 780bf0cce7a32bb6d60fc906f600ec44b0360457..d09a5dbf10f0cb7c3c3ed59bb86340de9085c209 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -35,10 +35,6 @@ #endif /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -68,24 +64,6 @@ (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -/* - * The (arm)linux board id set by generic code depending on configured board - * (see boards.cfg for different boards) - */ -#ifdef CONFIG_AT91SAM9G20 - /* the sam9g20 variants have two different board ids */ -# ifdef CONFIG_AT91SAM9G20EK_2MMC - /* we may be setup for the 2MMC variant of at91sam9g20ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC -# else - /* or the normal at91sam9g20ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK -# endif -#else - /* otherwise default to good old at91sam9260ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -106,8 +84,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -134,9 +110,4 @@ "fatload mmc 0:1 0x22000000 uImage; bootm" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index c3fe41636bfc517cea6e5e0aa42b7bd980163934..fb4695c1abf504853268eaa5e46969bf39a7450e 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -22,12 +22,6 @@ #include <asm/hardware.h> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_ATMEL_LEGACY /* @@ -93,8 +87,6 @@ #endif #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -115,9 +107,4 @@ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 51ecf4173b3cfa5e47c309aec792715ee276e698..e7fca468aa562ca3e527ba094369eadd7cd6e9a7 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -22,12 +22,7 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - #ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT #else #define CONFIG_SYS_USE_NORFLASH #endif @@ -91,7 +86,7 @@ (AT91_PMC_PLLAR_29 | \ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ AT91_PMC_PLLXR_PLLCOUNT(63) | \ - AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ @@ -101,7 +96,7 @@ /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ @@ -209,8 +204,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -224,9 +217,4 @@ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index b4aaf5995fb54c36a7813ee7b1d343eaf7e816e3..78ff57776707f3bc25924c4eef64847693111da9 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -18,11 +18,6 @@ #define CONFIG_AT91SAM9M10G45EK -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -67,8 +62,6 @@ #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env in nandflash */ @@ -83,11 +76,6 @@ "bootz 0x72000000 - 0x71000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE 0x010000 #define CONFIG_SPL_STACK 0x310000 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index fe99253e5a1ac16debd802c0a6b6cd63a65c3906..4ae6b66a3b26f35382d543ebcf4d137645a164f8 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT /* LCD */ #define LCD_BPP LCD_COLOR16 @@ -61,9 +57,6 @@ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" -/* Ethernet */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* USB host */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL @@ -102,11 +95,6 @@ #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x6000 #define CONFIG_SPL_STACK 0x308000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 92b87a2b492a485e06f1c758633afe6e461e598c..c703276bcbc09da4451ff63097f4d7f5fa623e09 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -16,12 +16,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - #define CONFIG_ATMEL_LEGACY /* @@ -62,10 +56,6 @@ /* Ethernet - not present */ -/* USB - not supported */ - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -87,10 +77,4 @@ "fatload mmc 0:1 0x22000000 zImage; " \ "bootz 0x22000000 - 0x21000000" #endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6a95b39cdb7907ac8539266269f7ee44726ed6a4..33481dc0459f2a6c81e0f0f85dc7e6f35d6f15fa 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -65,8 +60,6 @@ #endif #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_BOOTCOMMAND "nand read " \ @@ -85,11 +78,6 @@ "bootm 0x22000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x6000 #define CONFIG_SPL_STACK 0x308000 diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index bd9c371f83551a944c727ae5ab1f0c0d0ee91a09..bf3f34e428fc2380e19e7c896c5c63ed1e165029 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -12,7 +12,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0x04000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" #endif #endif @@ -47,12 +47,6 @@ */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* - * Size of malloc() pool - * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough - */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - /* DT blob (fdt) address */ #define CONFIG_SYS_FDT_BASE 0x800f0000 @@ -79,20 +73,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ GENERATED_GBL_DATA_SIZE) -/* - * Load address and memory test area should agree with - * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ - -/* - * memtest works on 512 MB in DRAM - */ - -/* - * FLASH and environment organization - */ - /* use CFI framework */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 0c5a3af4cc4e7e51f010d25f465fe21e75c67e3b..c02d25c03b7fb517b55b0d6f1825c4dbd269bca0 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -27,9 +27,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -63,7 +61,6 @@ * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* * Console configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 42a5abd1b41b829ab7c61bae5eeb770ee85219cb..2fe6c8639392096288d0464cc0f0a0f234d39165 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -19,8 +19,6 @@ #include <linux/sizes.h> #include <configs/ti_am335x_common.h> -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -204,10 +202,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index f72d62ec354139b5c51734307eba2f8b1448698d..d799ffd066e86742c3610cb99cc99501ab343bdd 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -15,8 +15,6 @@ #define CONFIG_SYS_TEXT_BASE 0x10100000 #define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 -#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */ - #include "bcmstb.h" #define BCMSTB_TIMER_LOW 0xf0412008 diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index ce865cb4564e29f236b9f2a4f8909cc255ce85c8..989482ef35a6875dce12c042c25c262b2e3f044a 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -15,8 +15,6 @@ #define CONFIG_SYS_TEXT_BASE 0x80100000 #define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 -#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */ - #include "bcmstb.h" #define BCMSTB_TIMER_LOW 0xf0412008 diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 14275abdc47a32a94281d1670b09fb84e65a4f12..be60fe78b202ce2376f04e9ee2069ba10deea5ec 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -16,7 +16,6 @@ #define PHYS_SDRAM_1 V2M_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000) /* * Initial SP before reloaction is placed at end of first DRAM bank, @@ -26,7 +25,6 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000) /* 12MB Malloc size */ -#define CONFIG_SYS_MALLOC_LEN (SZ_8M + SZ_4M) /* console configuration */ #define CONFIG_SYS_NS16550_CLK 25000000 diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index d7f9e5bc0639a14044682ec3eeb96cd3cc396b54..c3c28eadcb458fc92a63f482f85993094c9d4871 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -10,7 +10,6 @@ #ifndef __BCMSTB_H #define __BCMSTB_H -#include "version.h" #include <linux/sizes.h> #ifndef __ASSEMBLY__ @@ -36,7 +35,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * CPU configuration. */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* * Memory configuration. @@ -88,7 +86,6 @@ extern phys_addr_t prior_stage_fdt_address; #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. @@ -121,7 +118,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Informational display configuration. */ -#define CONFIG_REVISION_TAG /* * Command configuration. diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 0daa20ed5ce06c3559919f2b4d3b9ae64bca1d2e..8be491e60103153b611c8bb908df4cd99324cb74 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -20,8 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER - /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h deleted file mode 100644 index b5412363610010cc06ae06b7008ea70804fa4de8..0000000000000000000000000000000000000000 --- a/include/configs/bg0900.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIGS_BG0900_H__ -#define __CONFIGS_BG0900_H__ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_spi_firmware_filename=u-boot.sb\0" \ - "update_spi_firmware_maxsz=0x80000\0" \ - "update_spi_firmware=" /* Update the SPI flash firmware */ \ - "if sf probe 2:0 ; then " \ - "if tftp ${update_spi_firmware_filename} ; then " \ - "sf erase 0x0 +${filesize} ; " \ - "sf write ${loadaddr} 0x0 ${filesize} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_BG0900_H__ */ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 2abbe7b2ba8357ed4b932d0387002f466da0af22..84ea032e2fb73be0e2bf35af89c4e03bf193b862 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -60,14 +60,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -81,8 +73,6 @@ #define CONFIG_SYS_FSL_QSPI_LE #endif -#define CONFIG_LOADADDR 0x82000000 - /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 @@ -230,10 +220,6 @@ "source to NAND\0" \ "active_workset=1\0" -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical memory map */ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (SZ_512M) diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index 573ff3e40189add5b6eb7ad5279ac14eacb8ff74..66c23cd1d7a8e7cf07037890c10981df82081af8 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -15,10 +15,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 45eb931c257af38e729d3974cf49ea82eed7e4b7..412471a4aaa16368a372076793a3514d0fe1ab2d 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index eed321eb6fc8aca0d43cb46829f6d2760a322cd9..8caddf384628955e9a6ecb734298563a268764ae 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index c78099a49dcd09e42f01ccbb8a6426236d6db650..892a3e2c41e0d7d020a2b08e5da9de5992b2f158 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 38dd9e3af3aaf4841d286c6d1f03a996dd47f20a..6eaca1c31b5889a99cb805e707f940812d3215a5 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -15,10 +15,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index 547cf857ceb0a135deb257f12c4e76846bd518ae..5bfbcb779b4c72dc8176b3895aa3ca253fc121a6 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -22,10 +22,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 116e9705b6be7a8db1c405eef8f17795b0966d17..f8c81f698dc4b5939be3d8e433fbbdf56be8e69a 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index e5e8b15e18723a8dc57e8a8f30eb55f92c0bc396..92ab0ba7a2f0a47e72f11f5adcf18fd19c283685 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 4d4403f8d218d333aa2bac0e0b68ec8a6bf5af4d..7d321e14ff5e73feeb65b1e4fca02fce78fd0846 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index f1ff05414d55b93109b904b4504bacac0d548d2b..481dfc20b3c052274e8270a3a06a5d52ffd5089b 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -15,10 +15,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 3cb2d4050d09c4c696b6a8b62bf48462fa26307b..0f63239e5a557620c7b2394cd3e7050b439bf2b6 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -18,7 +18,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K #define CONFIG_SYS_CBSIZE SZ_512 diff --git a/include/configs/boston.h b/include/configs/boston.h index b9a9965eec32f372a1454ab5dfdd47a59d335aa3..cd70e7bd32bb61ecc7e765b04e6b4f13e06f05f7 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -33,10 +33,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) - -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) - /* * Console */ diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 238ae9c010e754b8e88eeb8bbd5ec803d49d4521..d9300de4783fcbce6e35066e644f2b4db8ac588a 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -14,7 +14,6 @@ 230400, 500000, 1500000 } /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) /* @@ -26,9 +25,6 @@ /* U-Boot */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -39,4 +35,3 @@ /* * bcm963158 */ - diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h index 77690ff40f73b07eb815d8f73a510382313947f0..66c12675e6d0f4789c10ea759a1631cdefda4e9f 100644 --- a/include/configs/broadcom_bcm968360bg.h +++ b/include/configs/broadcom_bcm968360bg.h @@ -14,7 +14,6 @@ 230400, 500000, 1500000 } /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* * 6858 @@ -25,9 +24,6 @@ /* U-Boot */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index febe6c0a04fc1ca6524faaf6d1231fc8127bfa12..26ba55a43a3fd4975e871c8c59a581ea563cec3e 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -14,7 +14,6 @@ 230400, 500000, 1500000 } /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* * 6858 @@ -25,9 +24,6 @@ /* U-Boot */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -38,4 +34,3 @@ /* * 968580xref */ - diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index f9a0632e543de52c9d07297ed893da5bb51ee935..9fb861b9a0d110d7e8e56328feb7b35446c912f4 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -16,7 +16,6 @@ #include <linux/stringify.h> /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN SZ_32M /* Clock Defines */ @@ -25,13 +24,6 @@ #define CONFIG_POWER_TPS65217 -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -/*#define CONFIG_MACH_TYPE 3589*/ -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ - /* * When we have NAND flash we expect to be making use of mtdparts, * both for ease of use in U-Boot and for passing information on to diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 333d3f44e2e943eb17c768a1a9ede1d52c3618b1..3f54bafdb88a61b7d3e0c3176c4cf07117ce70cb 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -20,20 +20,12 @@ #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_MXC_GPT_HCLK -#define CONFIG_LOADADDR 0x10700000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* MMC */ #define CONFIG_FSL_USDHC /* Boot */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* misc */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* Environment */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index d0cc08baa635e6999f2515cd21dc317876d37c78..f1e6dbf613583c39bde8c04374ec7a2e48a9be9c 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -18,15 +18,12 @@ /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_MACH_TYPE 3589 - #ifndef CONFIG_SPL_BUILD /* Default environment */ @@ -61,11 +58,6 @@ BUR_COMMON_ENV \ " bootm ${loadaddr} - ${dtbaddr}\0" #endif /* !CONFIG_SPL_BUILD*/ -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* SPI Flash */ /* Environment */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index d6a7af1a152616e540b9bd21b70cf1ad4c487ed9..d9179760b926567979b3d2ead1ff64d73a084124 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -18,14 +18,11 @@ #define LCD_BPP LCD_COLOR32 /* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_MACH_TYPE 3589 - #ifndef CONFIG_SPL_BUILD /* Default environment */ @@ -58,11 +55,6 @@ BUR_COMMON_ENV \ #define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* Environment */ #endif /* __CONFIG_BRXRE1_H__ */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 51585fcb3713bcccc475d698c6e2a9fe26fbc207..9b2e8b5c6ebb5b90eafd0c995496883220d6c85d 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_I2C_LEGACY - #endif /* CONFIG_DM */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ @@ -47,14 +45,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* !CONFIG_SPL_BUILD, ... */ -/* - * Our DDR memory always starts at 0x80000000 and U-Boot shall have - * relocated itself to higher in memory by the time this value is used. - */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* * ---------------------------------------------------------------------------- * DDR information. We say (for simplicity) that we have 1 bank, diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index b310e6c9e565e2413c14dc1d50088bfd3e9e6970..59e827e320a8c42531a1ceb7d347b9e965e917b2 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -51,7 +51,6 @@ /* I2C Configuration */ #ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_I2C_SPEED 400000 /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ #define EEPROM_I2C_ADDR 0x50 @@ -128,17 +127,12 @@ "reset;" /* Default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x80280000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 /* On CCP board, USDHC1 is for eMMC */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 8e8b1067b1dab868ae98480163d3f42910cbe273..f3416b534b230d0ab2498ee75fc1f4f9e78fd329 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU - /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 15c50279ad931e66205a8a8ac46e6c8f011510f7..4012814988d051a9d81aa2f953e72c40862ae5c2 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -50,8 +50,6 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Boot M4 */ #define M4_BOOT_ENV \ "m4_0_image=m4_0.bin\0" \ @@ -147,9 +145,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -158,18 +153,12 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ -/* Serial */ -#define CONFIG_BAUDRATE 115200 - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 6e46d29c855221f6e7bec6deefa72ed1f4559550..1d4503ba53122c3ef0802eaa29e824962fa10298 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_CI20_H__ #define __CONFIG_CI20_H__ -#define CONFIG_SKIP_LOWLEVEL_INIT - /* Ingenic JZ4780 clock configuration. */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_MHZ 1200 @@ -18,13 +16,10 @@ /* Memory configuration */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b8928ba6c41b6a9930972d2be27f6df1b467385d..ebfe356eee0dd86f7c3a7b55a6dc4ec88ad991c1 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -12,9 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* Network */ #define CONFIG_FEC_MXC #define CONFIG_FEC_XCV_TYPE RGMII @@ -25,22 +22,9 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define SYS_I2C_BUS_SOM 0 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM - #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } @@ -108,7 +92,6 @@ "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ "echo USB boot attempt ...; run usbbootscript; " -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index a496a80e02e5567acdfde6dff147fe044258cad1..d40c3a9c3e54fcefa5e5f1cc96386b0ce4caf409 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -14,7 +14,6 @@ /* Machine config */ #define CONFIG_SYS_LITTLE_ENDIAN -#define CONFIG_MACH_TYPE 4273 /* MMC */ #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -33,7 +32,6 @@ /* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} /* Environment */ @@ -43,9 +41,9 @@ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ "ramdisk_addr_r=0x13000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=undefined\0" \ "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ @@ -165,19 +163,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 - /* SATA */ #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_LBA48 @@ -186,10 +171,8 @@ /* Boot */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -#define CONFIG_SERIAL_TAG /* misc */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* SPL */ #include "imx6_spl.h" @@ -201,10 +184,5 @@ #define CONFIG_VIDEO_BMP_LOGO /* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 #endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 342cc7fddc7810da9d3176255d374911854d88e3..faeb903f359dcad2c71f3b5e27976309ca44c589 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -10,15 +10,11 @@ #ifndef __CONFIG_CM_T335_H #define __CONFIG_CM_T335_H -#define CONFIG_CM_T335 - #include <configs/ti_am335x_common.h> #undef CONFIG_MAX_RAM_BANK_SIZE #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ -#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 - /* Clock Defines */ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -83,9 +79,6 @@ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ /* I2C Configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 /* SPL */ @@ -128,11 +121,6 @@ /* Status LED polarity is inversed, so init it in the "off" state */ /* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 #ifndef CONFIG_SPL_BUILD /* @@ -145,4 +133,3 @@ #endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_CM_T335_H */ - diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 73205d0de6a5868532d4011bb29cb42284d8671f..6e5c26edc938d6562d66ef68a6caa5a1a61bdc53 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_CM_T43_H #define __CONFIG_CM_T43_H -#define CONFIG_CM_T43 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ @@ -45,13 +44,7 @@ /* CPSW Ethernet support */ #define CONFIG_SYS_RX_ETH_BUFFER 64 -/* USB support */ -#define CONFIG_USB_XHCI_OMAP -#define CONFIG_AM437X_USB2PHY2_HOST - /* Power */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_TPS65218 /* Enabling L2 Cache */ @@ -62,9 +55,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_HSMMC2_8BIT @@ -114,10 +104,5 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 #endif /* __CONFIG_CM_T43_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index c859616c68cb344273fcb58eb0afa2b861299836..efc6b5bd1be069ed689c889ec6e45bfc67790799 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -135,9 +135,6 @@ enter a valid image address in flash */ #endif -#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address -from which user programs will be started */ - /*---*/ /* @@ -217,7 +214,6 @@ from which user programs will be started */ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -237,7 +233,6 @@ from which user programs will be started */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2fa348517305420b25d389d509b33ceb05d2ccbf..d95c838eeb97cde5cc8abdc89a6255bd28641f48 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -15,9 +15,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* ENET1 */ #define IMX_FEC_BASE ENET2_BASE_ADDR @@ -25,9 +22,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* I2C configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -106,11 +100,10 @@ "fatload ${interface} 0:1 ${loadaddr} " \ "${board}/flash_blk.img && source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ "vidargs=video=mxsfb:640x480M-16@60" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index cb22b3c75a8ae66b065b75a846cce87f6fe8643c..e823497cb3965c20dab3c8f466a2840fba40b2ca 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -19,8 +19,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -102,9 +100,6 @@ "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -117,9 +112,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 804a144a03e1a9788c452fca1fb4a54ad4304df1..44135b2f2147a8f223e0fa89706df1cfdffac945 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -21,25 +21,8 @@ #include "imx6_spl.h" #endif -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - #define CONFIG_MXC_UART_BASE UART1_BASE -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -68,8 +51,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_LOADADDR 0x12000000 - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -142,7 +123,7 @@ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "vidargs=fbmem=8M\0" /* Miscellaneous configurable options */ @@ -151,8 +132,6 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 48 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 2fffaa39c02d23020a7684e5f7f6132d8feaf712..650936643966549f964ea102f7a26bd9921654d5 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -13,9 +13,6 @@ #include "mx7_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND @@ -24,10 +21,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -171,13 +164,12 @@ "fatload ${interface} 0:1 ${loadaddr} " \ "${board}/flash_blk.img && source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ "updlevel=2\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 6889e8b4e5581f749e98afa85ab8cfbba623195b..08786765d5af4bb3805314a6deb5f2084dc012b7 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -19,7 +19,6 @@ /* * Environment settings */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_BOOTCOMMAND \ "if fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ @@ -29,8 +28,6 @@ "fi; " \ "bootm 0xc0000;" #define CONFIG_TIMESTAMP -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS /* * Serial Console Configuration @@ -41,11 +38,10 @@ */ /* I2C support */ -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) #define CONFIG_SYS_I2C_PXA #define CONFIG_PXA_STD_I2C #define CONFIG_PXA_PWR_I2C -#define CONFIG_SYS_I2C_SPEED 100000 #endif /* LCD support */ @@ -83,7 +79,6 @@ #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 158bb09b37db83df6806f3c9eb9fcc505536fd0c..e947b58d96cea51ab758d05c47843ff5562a899b 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -15,8 +15,6 @@ #define CONFIG_TEGRA_UARTA_SDIO1 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2 - /* LCD support */ #define CONFIG_LCD_LOGO diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 30b48c5fd6a88dc88b605d8c345cdda3848d8980..324e607839a96020cb397cd47ba6f0ba067e5b38 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 - /* Increase console I/O buffer size */ #undef CONFIG_SYS_CBSIZE #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 5bd440f1db33e524c295cdd7b3603d84dd1d0912..f9d0d926eed9a68e99d82378a274b029152eb8a8 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT - #ifdef CONFIG_VIDEO_FSL_DCU_FB #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -27,9 +25,6 @@ #define DCU_LAYER_MAX_NUM 64 #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -38,7 +33,6 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_LOADADDR 0x80008000 #define CONFIG_FDTADDR 0x84000000 /* We boot from the gfxRAM area of the OCRAM. */ @@ -117,7 +111,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical memory map */ diff --git a/include/configs/comtrend_ar5315u.h b/include/configs/comtrend_ar5315u.h index 71a1af1cddceb25329d4663356acc5a8d3bf4d57..9f4b4e28045f87484569823abf52eeefe4837fcd 100644 --- a/include/configs/comtrend_ar5315u.h +++ b/include/configs/comtrend_ar5315u.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6318.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h index 7b195749ac4c28ca73f115106404c01ae0af4a81..888a6d8985992ad03e8b72c5a205fe5c059ac878 100644 --- a/include/configs/comtrend_ar5387un.h +++ b/include/configs/comtrend_ar5387un.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6328.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h index 2a28e6c624dc85639f3006be9926164786708d77..10e2969948039a5d31929d3fa0ddc251cbf234b8 100644 --- a/include/configs/comtrend_ct5361.h +++ b/include/configs/comtrend_ct5361.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6348.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/comtrend_wap5813n.h b/include/configs/comtrend_wap5813n.h index c8cddaf126e0371adb502edd93020efdc7306a98..f786c465baccfaf92bfb4f187b884a6ae5885d48 100644 --- a/include/configs/comtrend_wap5813n.h +++ b/include/configs/comtrend_wap5813n.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6368.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 3b17f75d209348197981e38dd2c7f937429096a8..efd04c6fb8ad9852a66ae5f52b51d22840aca6c9 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -12,16 +12,12 @@ */ #define CONFIG_CUSTOMER_BOARD_SUPPORT -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - /* * TEXT_BASE needs to be below 16MiB, since this area is scrubbed * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_LOADADDR 1000000 - /* * SATA/SCSI/AHCI configuration */ @@ -85,7 +81,7 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD /* SPL related MMC defines */ -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #ifdef CONFIG_SPL_BUILD #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #endif @@ -134,7 +130,7 @@ " gpio clear ${gpio1}; gpio set ${gpio2};" \ " fi; sleep 0.12; done\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ @@ -142,7 +138,7 @@ "tftpboot ${bootfile_addr} ${bootfile}; " \ "bootm ${bootfile_addr}" -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ "console=${consoledev},${baudrate} ${othbootargs}; " \ "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c877f3c725ec04c17d672fc8a824960c94cb408c..79fca968dc00a6ec621fde439cc7c356f563c8c5 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -25,16 +25,6 @@ #else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#if defined(CONFIG_TARGET_P3041DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg -#elif defined(CONFIG_TARGET_P4080DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg -#elif defined(CONFIG_TARGET_P5020DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg -#elif defined(CONFIG_TARGET_P5040DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg -#endif #endif #endif @@ -73,9 +63,7 @@ #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -101,11 +89,8 @@ #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* * DDR Setup @@ -117,8 +102,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -165,7 +148,7 @@ #define PIXIS_LBMAP_ALTBANK 0x40 #define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ @@ -250,7 +233,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -269,19 +251,6 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* * RapidIO @@ -488,7 +457,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -498,10 +466,6 @@ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -509,9 +473,6 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #ifdef CONFIG_TARGET_P4080DS #define __USB_PHY_TYPE ulpi #else @@ -539,14 +500,14 @@ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -555,7 +516,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -563,7 +524,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#define CONFIG_BOOTCOMMAND HDBOOT #include <asm/fsl_secure_boot.h> diff --git a/include/configs/corvus.h b/include/configs/corvus.h index bd4d6e8e39f441b7acad11bdd8ee30f7da3a1b6f..32f4a10cf56b525064946bfa4713a6fec89de883 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -29,11 +29,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ @@ -83,20 +78,12 @@ /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 - /* bootstrap + u-boot + env in nandflash */ #define CONFIG_BOOTCOMMAND \ "nand read 0x70000000 0x200000 0x300000;" \ "bootm 0x70000000" -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - SZ_4M, 0x1000) - /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) #define CONFIG_SPL_STACK (SZ_16K) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 883cbc95d239a4873d2c7c9e167e1f20b33ebe47..34683f60c7a8eb1e1628c45c875d6d0d87c630b6 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) @@ -31,7 +30,6 @@ /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -173,16 +171,12 @@ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTCOMMAND \ "run envboot; " \ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 18d9ba1784d926c8475a029f586ee67bc6d03c71..2a020e96c40581d1798222879bc06c5599780f46 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE - /* Environment in eMMC, at the end of 2nd "boot sector" */ /* SPI */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index dccfa034a4edb40c0b229bf49c92e91f2d9ff026..6f861a0998624a862635da42f5a043a26b451dd5 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -29,9 +29,6 @@ #endif #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Environment settings */ /* Environment in SD */ @@ -47,15 +44,9 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 18f4707e6be791dbf7a9e58b1404dfc15824ff7f..95f5cf005689bd8f458d3787545da2d5bbc0292a 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -17,11 +17,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 1ab42328fb6a14315cf7d852f847aad55a405cba..6bae063ae4809d41afcf53da49515b0b4b042425 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -11,11 +11,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* * SATA/SCSI/AHCI configuration diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index dd0c3cb7ad9cab1c7144a2cd0d3059feb1980d07..9f5e665e6f6673a03b8b6121283235af3a75069b 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -18,11 +18,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 33d71a7042ba58a4f15a50a44e61f0070ebf8ce8..c2340b2650757564a77164a4d538584b29b6b142 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -12,36 +12,18 @@ #include <linux/sizes.h> #include <asm/arch/cpu.h> -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* * Memory configurations */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - GENERATED_GBL_DATA_SIZE) /* * DMA */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_DMA_LPC32XX -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SPEED 100000 /* * GPIO @@ -125,14 +107,7 @@ * U-Boot Commands */ -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 /* * SPL specific defines diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 87da4410f5b17e95062dabd56bdfd3485f31d81f..a2a1d93faa916ab6a9049f34cb88aac0bb142170 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -15,7 +15,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -34,12 +33,6 @@ #include <configs/ti_omap3_common.h> -#define CONFIG_REVISION_TAG 1 - -/* Size of malloc() pool */ -#undef CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* Hardware drivers */ /* DM9000 */ #define CONFIG_NET_RETRY_COUNT 20 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index d9be1c38c44afbb00700382481be274d20d04530..7af8fceb71af9b84bf180e71f5dbb89c1948642c 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -27,14 +27,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) - /* Bootcounter */ #define CONFIG_SYS_BOOTCOUNT_BE @@ -81,9 +73,6 @@ #define CONFIG_HW_WATCHDOG #endif -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 40bb3b53a5a346ac3a25690235fbe500f273f63a..27854dfdf1e20cecd7e289c31ee86837d865c99f 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -47,14 +47,6 @@ #include "imx6_spl.h" -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - #define CONFIG_MXC_UART_BASE UART5_BASE /* I2C Configs */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 8990efb3f68b67422e579d52f2001c4dd68c364f..18ff1bb9e58aca67f28d352b6846ee78ed1dba06 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -12,17 +12,11 @@ #ifndef _CONFIG_DNS325_H #define _CONFIG_DNS325_H -/* - * Machine number definition - */ -#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 - /* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 04dd0f68c370bff3882c41d896cff0c059e73853..75a2476f5ef9a3de2366e794a82b62a5c817411e 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -16,7 +16,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index cc18bcece4d9e17dd865ce8c8cff1fe4990bbe38..361ee9663dbb9a090933a895d81d101bf1676e48 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -31,10 +31,6 @@ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - #define CONFIG_SYS_OMAP_ABE_SYSCK #ifndef CONFIG_SPL_BUILD @@ -78,11 +74,6 @@ /* SPI SPL */ -/* USB xHCI HOST */ -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_OMAP_USB2PHY2_HOST - /* SATA */ #define CONFIG_SCSI_AHCI_PLAT diff --git a/include/configs/draco.h b/include/configs/draco.h index 396eb7ded50040cb7b847fb44bea8d389a519707..29ce3a594045b385a65e8ad8deb542bf6fe503fb 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_DRACO_H #define __CONFIG_DRACO_H -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO - #include "siemens-am33x-common.h" #define DDR_PLL_FREQ 303 @@ -29,13 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - #define CONFIG_FACTORYSET /* Define own nand partitions */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 6474e57b29abdc44ae165d496dc1a2416a5f00bb..624f611c8ba07c9190969c07522b3528ebc1f5ce 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -20,7 +20,6 @@ #define PHYS_SDRAM_1_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) #define CONFIG_SYS_BOOTM_LEN SZ_64M /* UART */ @@ -82,9 +81,6 @@ REFLASH(dragonboard/u-boot.img, 8)\ "pxefile_addr_r=0x90100000\0"\ BOOTENV -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 64 /* max command args */ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 4256e6f06077efde2ade1214d3356dc86f920366..e71dd24a034d28b1bc4551f64f4b4f1572c255df 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Generic Timer Definitions */ @@ -50,9 +49,6 @@ "pxefile_addr_r=0x90100000\0"\ BOOTENV -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 65962ee73305604be5316c50c9e0a1dc2eb2f72b..5b71f70c94bfe1d5e8d09becdba283f47f8ac2bb 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -15,7 +15,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG #include "mv-plug-common.h" diff --git a/include/configs/ds109.h b/include/configs/ds109.h index f232abe430eda9cbe701c0b2ddf5fc60f27362c0..62fe1441210100f046143ce226453a1de2a2be13 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -11,9 +11,6 @@ #ifndef _CONFIG_DS109_H #define _CONFIG_DS109_H -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 527 - /* * High Level Configuration Options (easy to change) */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 5d401281c7e69da922fb1407b51748be4d8ed6d2..58ecc5f699d2fc98dcc543879a48017fa6e69250 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -6,9 +6,6 @@ #ifndef _CONFIG_SYNOLOGY_DS414_H #define _CONFIG_SYNOLOGY_DS414_H -/* Vendor kernel expects this MACH_TYPE */ -#define CONFIG_MACH_TYPE 3036 - /* * High Level Configuration Options (easy to change) */ @@ -20,11 +17,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* PCIe support */ #ifndef CONFIG_SPL_BUILD @@ -67,11 +60,7 @@ #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) -/* DS414 bus width is 32bits */ -#define CONFIG_DDR_32BIT - /* Default Environment */ -#define CONFIG_LOADADDR 0x80000 #define CONFIG_BOOTCOMMAND \ "sf probe; " \ "sf read ${loadaddr} 0xd0000 0x2d0000; " \ diff --git a/include/configs/durian.h b/include/configs/durian.h index fa48e5c0240077c4d7532bc5a8ef7eab178cb63a..1dec09b4cea88c987c089a5c1f096b88d401d6db 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -13,11 +13,6 @@ #define PHYS_SDRAM_1_SIZE 0x7B000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -/* Size of Malloc Pool */ -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) - #define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) /* PCI CONFIG */ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index c1a37c8a790eac3325ecf12e272b4cd1e766a3bb..220c3c44d6bce8515b4eb5a9ae2087279a6e1beb 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -13,20 +13,16 @@ /* * SoC and board defines */ -#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */ /* * RAM */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE /* * cmd */ -#define CONFIG_SYS_LOAD_ADDR 0x80100000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) /* diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 77584fa7a5d239dcf01e9c48408f4c41143df03f..6a5e1d3a7534e78b18d82f211843161821fdb8f5 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -47,8 +47,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x20000 - /*#define CONFIG_SYS_DRAM_TEST 1 */ #undef CONFIG_SYS_DRAM_TEST @@ -104,7 +102,6 @@ #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -135,7 +132,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) @@ -194,15 +190,8 @@ * I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL - -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0 - #ifdef CONFIG_CMD_DATE #define CONFIG_RTC_DS1338 #define CONFIG_I2C_RTC_ADDR 0x68 diff --git a/include/configs/edison.h b/include/configs/edison.h index 0e1205bdb54cb1ca86be827293cf474b37c9adc4..3ec35db4bcf1eda79264b08d17d6678acbb2e3bd 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Memory */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_PHYSMEM #define CONFIG_SYS_STACK_SIZE (32 * 1024) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 7e0a0ea89909afa4df47c8298cff7187187f02da..fbe468010bfc2a87ae5bbb02a4ea1277896572b4 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -94,15 +94,6 @@ /* auto boot */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ /* @@ -153,27 +144,17 @@ * I2C related stuff */ #ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 #endif /* * Environment variables configurations */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Enable command line editing */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index b11717637a17080a5b44e7654743c1e481749023..279d7122188a2c5c083a0010a5e27c4173bc989a 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -14,9 +14,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - #ifdef CONFIG_SPL #include "imx6_spl.h" #endif @@ -25,17 +22,7 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* I2C config */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 @@ -55,9 +42,9 @@ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 401b50d51be16d9b0c18c2fba2846ae5a7e579bd..9769155bca7be55b933a560cd5e8c13049b50104 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,17 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index a872d48154a4eff49747a911757314efb36f302e..2ceefed93400e329423d6af0c90509bd6f35b2f7 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -15,14 +15,10 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) -#define CONFIG_SYS_MALLOC_LEN SZ_64K -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - /* * Environment */ #define CONFIG_BOOTFILE "app.bin" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_image=u-boot.bin\0" \ @@ -33,4 +29,3 @@ "emsdp rom lock\0" #endif /* _CONFIG_EMSDP_H_ */ - diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 880149fb890298622610e3f7fe27fa8af8cee57f..7831687114b66b36cb52fd1859d1d2c01eaceac7 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -86,10 +86,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 @@ -110,7 +106,6 @@ #define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - #undef COMMON_ENV_DFU_ARGS #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs};" \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 3f266543b92bd87240d540191ba5ad5ec931c3e2..80108fc89957cd1b065409e1b02509ae90c7323b 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -14,10 +14,6 @@ /* The first stage boot loader expects u-boot running at this address. */ /* The first stage boot loader takes care of low level initialization. */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Set our official architecture number. */ -#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ @@ -34,9 +30,6 @@ /* 128MB SDRAM in 1 bank */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) /* 512kB on-chip NOR flash */ # define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -97,11 +90,6 @@ /* I2C */ #define CONFIG_SYS_MAX_I2C_BUS 1 -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 - #define I2C_SOFT_DECLARATIONS #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 @@ -131,9 +119,6 @@ /* File systems */ /* Boot command */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ "sf read 0x22000000 0xc6000 0x294000; " \ "bootm 0x22000000" diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index 0ff01af833b5837b620626cb942f3b4dd0e23891..dc032c1a419bb6be094953fbd16c2550a2931792 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -13,7 +13,4 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* Memory Info */ -#define CONFIG_SYS_LOAD_ADDR 0x83000000 - #endif /* __CONFIG_H */ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index e7975bf66d29b3cce2d7a554e7f413e8ca179ee3..177a52eb916b49d68f8a8c1f97da0657a0831705 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -10,7 +10,4 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* Memory Info */ -#define CONFIG_SYS_LOAD_ADDR 0x83000000 - #endif /* __CONFIG_H */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 8adaf297fe3649c3bfb9f33fd771af465e22af6d..95aaa747e4bea01cb2a82386f6e8497b7edf9642 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -16,21 +16,12 @@ #include <linux/sizes.h> #include <linux/stringify.h> -#define CONFIG_SKIP_LOWLEVEL_INIT - /* Keep L2 Cache Disabled */ /* input clock of PLL: 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - /* select serial console configuration */ /* PWM */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 5e2aca371e7e3432fe15de51b56641072b6c85e4..52dcf7a3bc429b57dc3043a2617cb9d355992158 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -14,8 +14,6 @@ #define CONFIG_BOARD_COMMON -#define CONFIG_REVISION_TAG - /* SD/MMC configuration */ #define CONFIG_MMC_DEFAULT_DEV 0 @@ -32,7 +30,7 @@ #define CONFIG_USB_GADGET_DWC2_OTG_PHY /* Common environment variables */ -#define CONFIG_EXTRA_ENV_ITB \ +#define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ "${kernelname}\0" \ "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 9297fbdc08176445baf2c00797edd7f3de0c7438..e4923964169f1a7180a56cf86eb528063a59ca64 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -45,12 +45,6 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -/* specific .lds file */ - -/* Boot Argument Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - #define CONFIG_RD_LVL #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE @@ -96,11 +90,6 @@ #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) -/* I2C */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 - /* SPI */ /* Ethernet Controllor Driver */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 65da3815fbd6f6f7b999a1275c2c9809f55ea664..36c3a613eb75322288d374ea16a69e00e120f48f 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 - #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) #define CONFIG_IRAM_STACK 0x02050000 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 2d362f3961519949a0b7fd0f945996a2ead90eae..7762c77164a387461fc3139a6226a2fab3774132 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -12,9 +12,6 @@ #define CONFIG_EXYNOS5_DT -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 8002 - #define CONFIG_VAR_SIZE_SPL #define CONFIG_IRAM_TOP 0x02074000 diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 6c0aa9bcd4a636226eb9309b67a91ed9d7dde2b0..4a1ecbb832c6d18ec465acfa26311367da6c73d2 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -16,9 +16,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ @@ -42,8 +39,6 @@ /* select serial console configuration */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 5ecbd1d3edd4a356dd76b3b41988a55d88f72908..67931febf84f2d71492ed408e88a4be0b9833982 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,14 +11,13 @@ #include "rcar-gen3-common.h" -/* Generic Interrupt Controller Definitions */ -#ifdef CONFIG_GICV2 -#undef CONFIG_GICV2 +/* + * Generic Interrupt Controller Definitions. Undefine v2 locations and define + * v3 locations. + */ #undef GICD_BASE #undef GICC_BASE #undef GICR_BASE -#endif -#define CONFIG_GICV3 #define GICD_BASE 0xF1000000 #define GICR_BASE 0xF1060000 diff --git a/include/configs/flea3.h b/include/configs/flea3.h deleted file mode 100644 index c345fb253d55ee38e9441b53c485de35bc64258d..0000000000000000000000000000000000000000 --- a/include/configs/flea3.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic <sbabic@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * Configuration for the flea3 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - - /* High Level Configuration Options */ -#define CONFIG_MX35 - -#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 - -/* Set TEXT at the beginning of the NOR flash */ - -/* This is required to setup the ESDC controller */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ -#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe - -/* - * UART (console) - */ -#define CONFIG_MXC_UART_BASE UART3_BASE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* Address and size of Redundant Environment Sector */ - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ - -/* - * NAND FLASH driver setup - */ -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "flea3" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc2,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 007cbb043a38d10aacfe892b85d0956fafa8c8f5..72852a0d91f2a8766597f1d5b28217c6dba6b9e4 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -17,11 +17,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -32,8 +27,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - /* NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -45,8 +38,6 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x7000 #define CONFIG_SPL_STACK 0x308000 diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 1b26466eda30e003823fb409f3a8246f091c923f..d287942b4784ca45bf166927b827325c45a41c99 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -12,14 +12,9 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 @@ -31,7 +26,7 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -46,7 +41,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 560d6a3d10a211dca28c67b66ac5ea7fbbf1074f..12d108d6d6d774dec6d2f7abe180100d413595a7 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -60,7 +59,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -84,8 +82,6 @@ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - /* TODO: Turn into string option and migrate to Kconfig */ #define CONFIG_HOSTNAME "gazerbeam" #define CONFIG_ROOTPATH "/opt/nfsroot" @@ -105,7 +101,7 @@ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -114,13 +110,13 @@ "tftp ${fdt_addr} $fdtfile;" \ "bootm ${kernel_addr} - ${fdt_addr}" -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ "console=$consoledev,$baudrate $othbootargs;" \ "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ "bootm ${kernel_addr} - ${fdt_addr}" -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 7db6afd88c23366377405a479b07474f7188483c..1a5db24800262711c28ee978d7d0e051c68836db 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -15,9 +15,6 @@ #include "imx6_spl.h" #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 5be3a49d05f7377fb582dee2b54a7e6b8547f7a6..0eeffd46377bfa8548a3b4da326ebe04dba9a28c 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -19,12 +19,6 @@ #include "mx6_common.h" #include <linux/sizes.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* SATA Configs */ #ifdef CONFIG_CMD_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 @@ -33,10 +27,6 @@ #define CONFIG_LBA48 #endif -/* Serial Flash */ - -#define CONFIG_LOADADDR 0x12000000 - #ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ @@ -53,7 +43,7 @@ "nfs ${loadaddr} /srv/nfs/fitImage; " \ "bootm ${loadaddr}\0" \ -#define CONFIG_NETWORKBOOTCOMMAND \ +#define NETWORKBOOTCOMMAND \ "run networkboot; " \ #else @@ -108,21 +98,16 @@ "run doboot; " \ "run failbootcmd\0" \ -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "run doquiet; " \ "run tryboot; " \ #ifdef CONFIG_CMD_NFS -#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NETWORKBOOTCOMMAND #else -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND #endif - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 2e89d72285d2dcf19124b3e111fe859f9cce4d5b..43027a506a5fab9f039f8217b3b86a1d4cd9c8a3 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -19,7 +19,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * Default GPIO configuration and LED status diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 4d5eab09f09bf9f02e481f67e4fbc67de20b5aa0..29a446c2f5d44837ccb3e27d4c75196c3994a4f1 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -13,18 +13,13 @@ /* Miscellaneous */ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_CMDLINE_TAG /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) -#define CONFIG_SYS_LOAD_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) -/* Malloc */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Network interface */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 4f2727363477d84ffaa78b7b27bc41a11d5d58cf..f0289582609f9584fc7471ebcbf35ada6ccdd905 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -24,14 +24,6 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" -#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ - -/* Serial ATAG */ -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* Serial */ #define CONFIG_MXC_UART_BASE UART2_BASE @@ -42,12 +34,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 #define CONFIG_I2C_EDID @@ -74,8 +60,6 @@ /* * PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define CONFIG_POWER_LTC3676 diff --git a/include/configs/harmony.h b/include/configs/harmony.h index b2464f90dea268a466e85c543342227cf70a348a..5a1e72c5373f50796f40a58486b68fc60bb301d8 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif -#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY - /* NAND support */ #define CONFIG_TEGRA_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/highbank.h b/include/configs/highbank.h index ff92c4f55407603e13740a431b39492b48ec6232..4ef3a46cfb97a7983ef132aff6ac51c07b3f534d 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) #define CONFIG_SYS_TIMER_COUNTS_DOWN -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - #define CONFIG_PL011_CLOCK 150000000 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ @@ -36,7 +31,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x800000 #define CONFIG_SYS_64BIT_LBA /* Environment data setup @@ -46,7 +40,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 659fbee052d5d6fabcf4a5f17ea63cd8adcbeb7a..387971c687b17c9cc97874e94d5fa6c31c8650d7 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -13,7 +13,6 @@ #include <linux/sizes.h> -#define CONFIG_POWER #define CONFIG_POWER_HI6553 #define CONFIG_REMAKE_ELF @@ -35,8 +34,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 19000000 @@ -44,13 +41,6 @@ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - -#ifdef CONFIG_USB_DWC2 -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO -#endif - #define CONFIG_HIKEY_GPIO /* BOOTP options */ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 04d458798a172573d8d61abacd94052d943af3ce..f446ecb86479a5278801d03f4f7b841e70ae4486 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 19000000 @@ -33,9 +31,6 @@ #define GICD_BASE 0xe82b1000 #define GICC_BASE 0xe82b2000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) #include <config_distro_bootcmd.h> diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 5678f0a77bb7eba2ce652f233c6b70cacf05cd0d..21a984a53d48f7924a8759ca43a579c7ab24e271 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -29,9 +29,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -107,7 +105,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* Cli configuration */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 3cc3b8c0ae2c0524302caceb3badfcffd48aaa3d..c8c28bb4f04013f708beb21a6c1c132fe6dec82e 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -28,9 +28,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -106,7 +104,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* Cli configuration */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h index 529fc9495ef4b938c8c5368bf233c230535a4ed9..7c88af0532d0280fe0a7b6ce8a823ecd95c158ba 100644 --- a/include/configs/huawei_hg556a.h +++ b/include/configs/huawei_hg556a.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6358.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index ba859a9a2499b7b333e3b83d64e39c4d96231119..4bd3494f1084cf583a23345adb286e5baafeb27b 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -13,7 +13,6 @@ */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index c99490b85dc65d9a93e381d33cb8bfe0548abf2b..1a716dfbe91d2676c6f3d8d18f8f9af984883b3f 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -13,12 +13,6 @@ */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Machine type - */ -#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT #include "mv-common.h" diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 19d3fbff9c2b08aa5ee4857b8d35bc8c5884ad74..e759db2ff2fbc1f1fed5cd5b8ad4baa253de214e 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -163,11 +163,6 @@ /* * I2C setup */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* @@ -217,7 +212,6 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) /* * Environment Configuration @@ -229,7 +223,6 @@ #define CONFIG_BOOTFILE "ids8313/uImage" #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" #define CONFIG_FDTFILE "ids8313/ids8313.dtb" -#define CONFIG_LOADADDR 0x400000 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" /* Initial Memory map for Linux*/ @@ -241,7 +234,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_LOADS_ECHO #define CONFIG_TIMESTAMP #define CONFIG_BOOTCOMMAND "run boot_cramfs" @@ -284,7 +276,7 @@ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ "run setipargs;run addmtd;" \ "tftp ${loadaddr} ${bootfile};" \ diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index fcf1b7f990e19cd65539fb093c543a03631bb8fa..fc27ca4fe6f0d359fbd9024d91b41b7bee2ac060 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -11,7 +11,6 @@ #define __XILFPGA_CONFIG_H /* BootROM + MIG is pretty smart. DDR and Cache initialized */ -#define CONFIG_SKIP_LOWLEVEL_INIT /*-------------------------------------------- * CPU configuration @@ -29,9 +28,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ /*---------------------------------------------------------------------- * Commands diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 8c5c06162088c40c4ca901ff273c1b1220096848..27aab38926d7137df1ed73f99f557f3afac4270b 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -15,10 +15,6 @@ #define CONFIG_MX27 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - /* * Lowlevel configuration */ @@ -67,8 +63,6 @@ /* * Memory Info */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) /* memtest start address */ #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ @@ -120,9 +114,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index bfe83b8cba530ba9cc65286aac06b8e10f1b0d0d..4b45e33ad1558d5052de3737a440e7818d959036 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -13,9 +13,6 @@ #include <linux/stringify.h> #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Total Size of Environment Sector */ /* Environment */ @@ -30,7 +27,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=uImage\0" \ "fit_image=fit.itb\0" \ "fdt_high=0xffffffff\0" \ @@ -103,13 +100,12 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 #ifdef CONFIG_MX6UL # define DRAM_OFFSET(x) 0x87##x # define FDT_ADDR __stringify(DRAM_OFFSET(800000)) -#else +#else # define DRAM_OFFSET(x) 0x1##x # define FDT_ADDR __stringify(DRAM_OFFSET(8000000)) #endif @@ -174,7 +170,7 @@ # ifdef CONFIG_ENV_IS_IN_NAND # define CONFIG_SPL_NAND_SUPPORT # else -# define CONFIG_SPL_MMC_SUPPORT +# define CONFIG_SPL_MMC # endif # include "imx6_spl.h" diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 6b992f9ab8bff8b9c11e39abb671284da9abf1e9..e49370305c6c355f1ba020320231f8a1ddbb8e62 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -17,9 +17,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -36,7 +33,7 @@ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x14000000\0" \ "ramdisk_addr_r=0x14080000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index ede81cca1f2e7a85ad7873bef4dd75563febfb60..234aacb3b9143267f51cae9946a1cadf7184e79e 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -54,12 +54,12 @@ #endif /* MMC support */ -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #endif /* SATA support */ -#if defined(CONFIG_SPL_SATA_SUPPORT) +#if defined(CONFIG_SPL_SATA) #define CONFIG_SPL_SATA_BOOT_DEVICE 0 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 #endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 4027f329d30bbafebe87014f19c09f66dc2c853e..367f78d125d4effbcf753d090d917dec66209c47 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -13,9 +13,6 @@ #include <linux/sizes.h> #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - /* Total Size of Environment Sector */ /* Environment */ @@ -65,7 +62,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 4a3706d9960c010447bc6aac0899972f747caf96..4d4c94b74eaa210288bcab59fcf58c2d3075edda 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,9 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - #define CONFIG_ETHPRIME "FEC" #undef CONFIG_SYS_AUTOLOAD @@ -23,9 +20,9 @@ /* * Use: - * boot-mode=mix - * boot-mode=sd - * boot-mode=net + * boot-mode=mix + * boot-mode=sd + * boot-mode=net */ #define MY_CONFIG_BOOT_MODE "boot-mode=sd\0" @@ -75,7 +72,6 @@ #define CONFIG_BOOTCOMMAND "run boot${boot-mode}" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index abf3dd57c847baa8ae8f4c8fbc71c06267e6e08e..01d1cd83b23719d86906fa60392a2022d63820c9 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -31,7 +31,7 @@ #define CONFIG_SPL_PAD_TO 0x11000 /* MMC support */ -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index faeee2178c2deffa4f4c23605e69ad43fa73a183..9b86e0a9a07752e8addb4c914679c845b6a59e00 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -140,9 +140,6 @@ #endif /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -153,9 +150,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -178,8 +172,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 94f4a1232fbf1d00f5b38a8b5183eb5c9de8fa8e..2bdcc0ab725bba84b3945228a2c4785ff8b95023 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -93,9 +93,6 @@ "fi;" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -104,9 +101,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -128,9 +122,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* FEC*/ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 8f3dd8fb61a30bad3e35593868470e92678db6ec..a03a7a72ec967aeb3460dd16c4b574df393f28ca 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -44,8 +44,8 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ "fdt_addr_r=0x43000000\0" \ @@ -57,9 +57,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -70,9 +67,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -94,8 +88,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index af5be6889dff237611a7420aba36bd0fd7563b97..4b22ba10a02c0c46b1a18094a72a354cf43870cc 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -56,8 +56,6 @@ BOOTENV /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M @@ -66,8 +64,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ @@ -94,7 +90,4 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - #endif /* __IMX8MM_ICORE_MX8MM_H */ diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 91669255e12a59fcaf82b05a36fbe084d5391d60..63f02bfd01e81acfe80bf0b7c28dee1a36a80a36 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -37,8 +37,6 @@ "scriptaddr=0x46000000\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Enable Distro Boot */ #ifndef CONFIG_SPL_BUILD @@ -87,8 +85,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ @@ -112,9 +108,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* FEC */ #define CONFIG_ETHPRIME "eth0" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 9ce60fd51b3ac556754afa20a5a2f8ee55fb4638..cb85c35e54b7c47b1243602d83505f4160842d03 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -108,9 +108,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -121,9 +118,6 @@ #define CONFIG_ENV_OVERWRITE -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 985bec803ad96ac5a78787d47c086a04b4b34b6c..1e18a87987777d2a62706498d6f8801f241a1d96 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -44,8 +44,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "console=ttymxc1,115200\0" \ "fdt_addr_r=0x43000000\0" \ "boot_fit=no\0" \ @@ -56,9 +56,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -69,9 +66,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -93,6 +87,4 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index a6569d5566ead61cb9b9f4dbcf450f138566a1cd..bec6c1d8e9c2051046416f21e241a50ebfb3655b 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -30,15 +30,9 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PCA9450 -#define CONFIG_SYS_I2C_LEGACY - #endif #if defined(CONFIG_CMD_NET) @@ -68,8 +62,8 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ "fdt_addr_r=0x43000000\0" \ @@ -81,9 +75,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -94,9 +85,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - /* Totally 6GB DDR */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -120,6 +108,4 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #endif diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 9db3bd5f58d6c6d270b91c1d5ce8fcf092d51544..9b786620ce376ce9c648df4c3552b798e9120cb1 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -65,9 +65,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -78,9 +75,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index af81a43cbc5bc26fd350ba51dae5fbf300d35c29..9b9d6fd6513836be76a52510b2e9bab15f4c4c7f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -28,7 +28,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -41,18 +41,7 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif @@ -99,9 +88,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -112,9 +98,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ @@ -139,13 +122,6 @@ #define CONFIG_MXC_GPIO -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_OF_SYSTEM_SETUP -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - #endif diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 8038abcba3839dad57598eb665aedd3b7c797717..0ec1f69fdbc3c119727201fea21748241ede5472 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -25,7 +25,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -38,18 +38,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 - -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C #endif #define CONFIG_REMAKE_ELF @@ -142,9 +130,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -155,9 +140,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ @@ -184,13 +166,6 @@ #define CONFIG_MXC_GPIO -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_OF_SYSTEM_SETUP -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - #endif diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 99e73a9446b6e3fbff318d8ad2c97a190f12cd95..152fa6f1c27ddd587681d1ac11c753469496d932 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -42,8 +42,6 @@ #define USDHC2_BASE_ADDR 0x5B020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -145,9 +143,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -159,9 +154,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index fcbf8eeb34aac1c31d2775018de0a316949a7cd6..89b45546adc2ce091fc9f2581bbda34a57535796 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -24,7 +24,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* FUSE command */ /* Boot M4 */ @@ -122,9 +121,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -146,9 +142,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index a7d623a9b9e358c97695aca89ec5344bcc566fdd..a7ca48f1f6b9440d511ef319b6dcebdb69c11e9f 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -41,8 +41,6 @@ #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -144,9 +142,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -158,9 +153,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 32f8773b241eda0bda9409ee819498d77e0cdb99..8e9a159e9b3776167a18a6f25a2812e6f0332c73 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -33,8 +33,6 @@ #endif -#define CONFIG_SERIAL_TAG - #define CONFIG_REMAKE_ELF #define CONFIG_BOARD_EARLY_INIT_F @@ -63,8 +61,8 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttyLP1,115200 earlycon\0" \ "fdt_addr_r=0x83000000\0" \ @@ -76,9 +74,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x80480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -88,9 +83,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_MMCROOT "/dev/mmcblk2p2" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index 4fb44774b0c1685ddda9a6371d5fa51f0e41a5e7..64c0f5eaf0bc26a81853ec2bec2335feb6432f0f 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -11,13 +11,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20240000 -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x20209000 -#else -#define CONFIG_SYS_LOAD_ADDR 0x80000000 -#define CONFIG_LOADADDR 0x80000000 -#endif - #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 @@ -31,7 +24,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) /* For SPL */ #ifdef CONFIG_SUPPORT_SPL diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index c8d661fb3ee118154d75854c021434f4a220e27d..1b6754299e7f978bdaa5d21606f04935e9c5deba 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -11,13 +11,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20280000 -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x20209000 -#else -#define CONFIG_SYS_LOAD_ADDR 0x80000000 -#define CONFIG_LOADADDR 0x80000000 -#endif - #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 @@ -42,7 +35,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) /* For SPL */ #ifdef CONFIG_SUPPORT_SPL diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 89ab0da50cdde9224b2baf36c2093dba99e31039..b573bdc64f65a4d85ba8bd8e684799bff600e05b 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -7,11 +7,6 @@ */ #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS /* * There are various dependencies on the core module (CM) fitted @@ -48,7 +43,6 @@ * image to run at reset/power up * e.g. whether the ARM Boot Monitor runs before U-Boot */ -/* #define CONFIG_SKIP_LOWLEVEL_INIT */ /* * The ARM boot monitor does not relocate U-Boot. diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h new file mode 100644 index 0000000000000000000000000000000000000000..ddb4cfcc8e24f8c8b58a9dd93b15f73762e36a83 --- /dev/null +++ b/include/configs/iot2050.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for IOT2050 + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin <le.jin@siemens.com> + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +#ifndef __CONFIG_IOT2050_H +#define __CONFIG_IOT2050_H + +#include <linux/sizes.h> + +/* SPL Loader Configuration */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* U-Boot general configuration */ +#define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ + "usb_pgood_delay=900\0" + +#ifndef CONFIG_SPL_BUILD + +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) \ + func(USB, usb, 0) \ + func(USB, usb, 1) \ + func(USB, usb, 2) +#else +# define BOOT_TARGET_USB(func) +#endif + +/* + * This defines all MMC devices, even if the basic variant has no mmc1. + * The non-supported device will be removed from the boot targets during + * runtime, when that board was detected. + */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_USB(func) + +#include <config_distro_bootcmd.h> + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + BOOTENV \ + EXTRA_ENV_IOT2050_BOARD_SETTINGS + +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_IOT2050_H */ diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index 1ba69d9a5d0de6019ea11fb6c6b7cd7667042074..a1b8c066228a3668480273a040ab1f76cfb10420 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -57,9 +57,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MALLOC_LEN SZ_64K #define CONFIG_SYS_BOOTM_LEN SZ_128K -#define CONFIG_SYS_LOAD_ADDR SRAM_BASE #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K @@ -75,6 +73,5 @@ * Environment */ #define CONFIG_BOOTFILE "app.bin" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 716ae3b0d4aa4ee4f14a197a4bd6f3d7dabd7c73..9b25c34982235f96752d802b2b1820e5f00ee766 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -11,9 +11,6 @@ #include <environment/ti/spi.h> -/* Platform type */ -#define CONFIG_SOC_K2E - #ifdef CONFIG_TI_SECURE_DEVICE #define DEFAULT_SEC_BOOT_ENV \ DEFAULT_FIT_TI_ARGS \ @@ -23,7 +20,7 @@ #endif /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ DEFAULT_SEC_BOOT_ENV \ "boot=ubi\0" \ @@ -47,6 +44,4 @@ #define CONFIG_KSNET_CPSW_NUM_PORTS 9 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -#define CONFIG_DDR_SPD - #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 4471eb4f6a8473daf8b258542a3e068aa5efa0e1..56dd9c72d9491e2cf88eb2ac86866b40caefef19 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -12,11 +12,8 @@ #include <environment/ti/mmc.h> #include <environment/ti/spi.h> -/* Platform type */ -#define CONFIG_SOC_K2G - /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_MMC_TI_ARGS \ DEFAULT_PMMC_BOOT_ENV \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index d90b2648185a8eb4fda96a3f02ca8384d7e2b940..cfc34c7da6d7334b130ec0d4d509c9736cbb14d6 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -11,9 +11,6 @@ #include <environment/ti/spi.h> -/* Platform type */ -#define CONFIG_SOC_K2HK - #ifdef CONFIG_TI_SECURE_DEVICE #define DEFAULT_SEC_BOOT_ENV \ DEFAULT_FIT_TI_ARGS \ @@ -23,7 +20,7 @@ #endif /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ DEFAULT_SEC_BOOT_ENV \ "boot=ubi\0" \ @@ -46,6 +43,4 @@ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 -#define CONFIG_DDR_SPD - #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 152cea01b55b807a574c0b4d66e1c08766267942..65988fff06ed3ae175d76cfee208aa1b0bbe40d5 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -11,9 +11,6 @@ #include <environment/ti/spi.h> -/* Platform type */ -#define CONFIG_SOC_K2L - #ifdef CONFIG_TI_SECURE_DEVICE #define DEFAULT_SEC_BOOT_ENV \ DEFAULT_FIT_TI_ARGS \ @@ -23,7 +20,7 @@ #endif /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ DEFAULT_SEC_BOOT_ENV \ "boot=ubi\0" \ diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h index e710c04493db4d112e5900b0344b151a6b5ab1bf..ff97c6cc791aa1c0be8639b1d9ef77b0274ed6e9 100644 --- a/include/configs/km/km-mpc8309.h +++ b/include/configs/km/km-mpc8309.h @@ -8,7 +8,6 @@ /* * System Clock Setup */ -#define CONFIG_83XX_CLKIN 66000000 #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 @@ -123,7 +122,6 @@ #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 /* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index 22dfb5da67b948aba0f4eb6fee7a5b502677e022..de6e7daf066dbf0fc6f20a38bdbbdc0bcf4a98a9 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -6,7 +6,6 @@ /* * System Clock Setup */ -#define CONFIG_83XX_CLKIN 66000000 #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 @@ -73,4 +72,3 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 798b1269605630a2a34ad42e03648351e98cc302..92e046d02d726f7b396bad73304e7f32bfaf78bc 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -67,7 +67,6 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 /* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * PAXE on the local bus CS3 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index ecf4378bf1cc381e7540b6058e9ad77b467e7afa..45db5cf873c78796d055a5c373791df51dad846e 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -18,7 +18,6 @@ /* * Manually set up DDR parameters */ -#define CONFIG_DDR_II #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ /* @@ -62,17 +61,8 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } /* I2C */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_NUM_I2C_BUSES 4 #define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 3be926c10311e6beaf1b17a0a4766b70a4965241..a9a6a41f6b782d221ef3f00f9744c32dfb7ec298 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -11,13 +11,6 @@ /* EEprom support 24C08, 24C16, 24C64 */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* Reserve 4 MB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Increase max size of compressed kernel */ #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 179e145b5ffc8b11dc7cbdc39b89bb50f0f08bdd..cca624ea3e116b2ba404f7a4563534c9513809a0 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -25,23 +25,16 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD - #define CONFIG_NAND_ECC_BCH /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -/* Reserve 4 MB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* Increase max size of compressed kernel */ #define CONFIG_SYS_BOOTM_LEN (32 << 20) #include "asm/arch/config.h" -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ - /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ "bootcountaddr=${bootcountaddr} ${mtdparts}" \ @@ -59,17 +52,6 @@ "appended one; fi\0" \ "" -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - /* * NAND Flash configuration */ @@ -90,8 +72,6 @@ * I2C related stuff */ #undef CONFIG_I2C_MVTWSI -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ @@ -125,16 +105,8 @@ extern void __set_direction(unsigned pin, int high); #define I2C_DELAY udelay(1) #define I2C_SOFT_DECLARATIONS -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 - /* EEprom support 24C128, 24C256 valid for environment eeprom */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * Environment variables configurations @@ -142,8 +114,6 @@ extern void __set_direction(unsigned pin, int high); #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ #else -#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 -#define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_EEPROM_WREN #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ #endif @@ -165,9 +135,9 @@ extern void __set_direction(unsigned pin, int high); "newenv=setenv addr 0x100000 && " \ "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ "mw.b ${addr} 0 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ + "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ + "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" #endif diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index a4cc4777290df352ca20c45db26c65a91479f674..75d109a88d401c233851df30b29b91b922f0c9e8 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -8,16 +8,9 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT - /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE @@ -26,12 +19,6 @@ CONFIG_KM_RESERVED_PRAM) >> 10) #define CONFIG_SYS_CLK_FREQ 66666666 -/* - * Take into account default implementation where DDR_FDBK_MULTI is consider as - * configured for DDR_PLL = 2*MEM_PLL_RAT. - * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT. - */ -#define CONFIG_DDR_CLK_FREQ (100000000 >> 1) #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) @@ -42,8 +29,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 @@ -191,9 +176,7 @@ /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1 @@ -224,8 +207,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 51a01d860f0e0e039774337005fa1206dfdbace6..bf876df554f9dc2218edc18c4c7e212379200e7f 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -177,21 +177,14 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DDR_CLK_FREQ 66666666 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /****************************************************************************** * (PRAM usage) * ... ------------------------------------------------------- @@ -366,8 +359,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* * Serial Port - controlled on board with jumper J8 * open - index 2 diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index cdfb280aeeee3dd9770a483fac0d35cac768323f..60fe4ae3839e970673694e3231bef78ddb9a4bd3 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -27,7 +27,6 @@ /* * System Clock Setup */ -#define CONFIG_83XX_CLKIN 66000000 #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index bfb4e67c8f45b431f904ec8843f743ad61cf16ed..6769592101def84235a220416555695c07bb21df 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -16,8 +16,6 @@ #endif /* DDR */ -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_VERY_BIG_RAM @@ -42,18 +40,13 @@ /* generic timer */ #define COUNTER_FREQUENCY 25000000 -/* size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* early heap for SPL DM */ #define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE /* serial port */ #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) /* ethernet */ @@ -71,7 +64,6 @@ /* environment */ /* see include/configs/ti_armv7_common.h */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 #define ENV_MEM_LAYOUT_SETTINGS \ "loadaddr=0x82000000\0" \ "kernel_addr_r=0x82000000\0" \ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c94882846efa4c581e01c6c1b07e4dd460a24c82..c1db6eace1aa583c800b04822b9be5f2f82fc81a 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -12,20 +12,11 @@ #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* Command definition */ -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ @@ -77,7 +68,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 749e880f36ff8aafac9ab43362c2e11b5a5d5a62..8471dffe832f700bea5a0561645a75d7edf211f1 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -16,13 +16,6 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ /* Miscellaneous configurable options */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) /* FEC ethernet */ #define CONFIG_ARP_TIMEOUT 200UL @@ -37,11 +30,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #endif -/* Watchdog */ - -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 059c54e21ed56e7b3c1d245fa321f76cc0123fcb..c3f690c7d70ee92a524fb8563c2a73b44b77e3e4 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -8,14 +8,9 @@ #define __KZM9G_H #define CONFIG_SH73A0 -#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G #include <asm/arch/rmobile.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* MEMORY */ #define KZM_SDRAM_BASE (0x40000000) #define PHYS_SDRAM KZM_SDRAM_BASE @@ -46,10 +41,8 @@ #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 @@ -82,23 +75,4 @@ #define CONFIG_NFS_TIMEOUT 10000UL -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 -#define CONFIG_SYS_I2C_SH_SPEED0 100000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 -#define CONFIG_SYS_I2C_SH_SPEED1 100000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 -#define CONFIG_SYS_I2C_SH_SPEED2 100000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 -#define CONFIG_SYS_I2C_SH_SPEED3 100000 -#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 -#define CONFIG_SYS_I2C_SH_SPEED4 100000 -#define CONFIG_SH_I2C_8BIT -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ - #endif /* __KZM9G_H */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 88f784f1f0fd587a309d5bc01bdf6f5d01841b9c..146d8ad63721cb67357a2e5478aa235689c2ec2b 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -6,27 +6,6 @@ #ifndef _CONFIG_LACIE_KW_H #define _CONFIG_LACIE_KW_H -/* - * Machine number definition - */ -#if defined(CONFIG_INETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 -#elif defined(CONFIG_NETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 -#elif defined(CONFIG_NETSPACE_LITE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 -#elif defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 -#elif defined(CONFIG_NETSPACE_MAX_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 -#elif defined(CONFIG_D2NET_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 -#elif defined(CONFIG_NET2BIG_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 -#else -#error "Unknown board" -#endif - /* * High Level Configuration Options (easy to change) */ @@ -37,7 +16,6 @@ #else #define CONFIG_KW88F6281 #endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * SDRAM configuration @@ -99,9 +77,6 @@ */ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ #if defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_I2C_G762_ADDR 0x3e #endif diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 8c2c8e110d807048da380cd9eead01c3969964e2..6928179201989f81af16cf5bdaacd755f64c8eb1 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -22,12 +22,10 @@ #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -47,7 +45,6 @@ /* * I2C Configuration */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ @@ -57,15 +54,12 @@ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_SETUP_INITRD_TAG #define CONFIG_BOOTCOMMAND \ "if mmc rescan; then " \ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index e7a7ae319897e6713fdfa6064c5e1e7e8c7d443a..aa2542fe35756b139271d97be7470651f520cc28 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -12,14 +12,9 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 @@ -31,7 +26,7 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -47,7 +42,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 5adbe1ca3916ab8cb719d633dd23cfca00eba2be..dc6f15a2a2282a8c270c13322fbb89a7242bca46 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -16,9 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -104,8 +101,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 670b55de26b1cbc84954184f15d9d28459380d6e..8a49f2d0075d5e76ec8382ff65354548d2058008 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -6,22 +6,17 @@ #ifndef __LS1012A_COMMON_H #define __LS1012A_COMMON_H -#define CONFIG_GICV2 - #include <asm/arch/config.h> #include <asm/arch/stream_id_lsch2.h> #include <linux/sizes.h> #define CONFIG_SYS_CLK_FREQ 125000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - #ifdef CONFIG_TFABOOT #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #endif -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -34,9 +29,6 @@ /* CSU */ #define CONFIG_LAYERSCAPE_NS_ACCESS -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M) - /* PFE */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 @@ -55,12 +47,6 @@ CONFIG_SYS_SCSI_MAX_LUN) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif /* GPIO */ #ifdef CONFIG_DM_GPIO @@ -73,8 +59,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - #define CONFIG_SYS_HZ 1000 #define CONFIG_HWCONFIG diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 3e5fdadc40db057962e589ee8fa1fbf1b954676e..a5900f226c9e8a30e39a111e1f72e0a0b891c34b 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -54,13 +54,8 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Voltage monitor on channel 2*/ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 4c448c6b64bab6acd191ad6e140f678cbe0878f9..7a7640a49c739944e6ff80d877df7668fa2d7ba9 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -11,16 +11,10 @@ #define CONFIG_SYS_FSL_CLK -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 /* * DDR: 800 MHz ( 1600 MT/s data rate ) @@ -53,21 +47,13 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1021aiot/ls102xa_pbi.cfg -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_I2C #define CONFIG_SPL_WATCHDOG -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -98,23 +84,9 @@ * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * MMC @@ -175,8 +147,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -#define CONFIG_CMDLINE_TAG - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -196,8 +166,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 598f6c67a1b21ddba783fd988975fbd2165e4ecd..a164796dd87a802a0710f084ef72edc81e21ad6c 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,45 +11,23 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_DEEP_SLEEP -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_QIXIS_I2C_ACCESS #else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg #endif #ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg -#endif - #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 @@ -63,8 +41,6 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg - #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 @@ -82,7 +58,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -95,9 +70,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -330,16 +303,6 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* GPIO */ #ifdef CONFIG_DM_GPIO @@ -349,13 +312,8 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * I2C bus multiplexer @@ -429,8 +387,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCI_SCAN_SHOW #endif -#define CONFIG_CMDLINE_TAG - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -461,8 +417,6 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 58c2d97a327f70dbd1b7daa48ebd9fc97a243b0c..f70b6e94c079808cf03f34151fa9ff4b13730e0f 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2019 NXP Semiconductors + * Copyright 2016-2019 NXP * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> */ @@ -12,9 +12,6 @@ #define CONFIG_DEEP_SLEEP -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE @@ -22,7 +19,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -51,15 +47,7 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - "board/freescale/ls1021atsn/ls102xa_pbi.cfg" -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ @@ -104,23 +92,10 @@ #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* QSPI */ #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -220,8 +195,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index ba308c514b9d806cc399f9f898b4eb977c733490..067d4f725d84fe6c5dbba3802795269f4265e575 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,19 +11,12 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_DEEP_SLEEP -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -52,19 +45,7 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg -#endif - #ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg -#endif - #ifdef CONFIG_NXP_ESBC /* * HDR would be appended at end of image and copied to DDR along @@ -208,16 +189,6 @@ /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* GPIO */ #ifdef CONFIG_DM_GPIO @@ -227,13 +198,8 @@ #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * MMC @@ -267,8 +233,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -#define CONFIG_CMDLINE_TAG - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -431,8 +395,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index cbcf30e9686f2dfe1f7cd77e8cb876d6e641a1cc..1401264f93164e8d94438175ec33275df2a4f540 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -16,8 +16,6 @@ /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -33,9 +31,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* GPIO */ #ifdef CONFIG_DM_GPIO #ifndef CONFIG_MPC8XXX_GPIO @@ -44,19 +39,13 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 @@ -103,13 +92,8 @@ #define I2C_MUX_CH_DEFAULT 0x8 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* DisplayPort */ #define DP_PWD_EN_DEFAULT_MASK 0x8 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 9ae37b96cebe0bcd4d36ddc1d1b5d9768bc4c2f9..fe20363e690f7e32de12ebbb6d6f93d112f10e47 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -9,7 +9,6 @@ #include "ls1028a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) /* DDR */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 1a80cb945dfb5329e2b346f6237f6fc518fd5082..348db1e2f8c160cffc350fdcf3c600e22f4cbd09 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -9,7 +9,6 @@ #include "ls1028a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) #define CONFIG_SYS_RTC_BUS_NUM 0 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 834c3e6780af1e9ed8aa26465b93f0c5e77c518f..fb697bdf1301a502275f69e9dcbcde9008caff9d 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -27,7 +27,6 @@ #endif #define CONFIG_REMAKE_ELF -#define CONFIG_GICV2 #include <asm/arch/stream_id_lsch2.h> #include <asm/arch/config.h> @@ -39,8 +38,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #endif -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -52,16 +49,11 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* SD boot SPL */ #ifdef CONFIG_SD_BOOT @@ -149,16 +141,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif /* PCIe */ #ifndef SPL_NO_PCIE @@ -217,7 +199,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -236,7 +217,7 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ + "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 1636f0bb8ff0f7f8d5fb4e1dad55609a12764b61..4ef4cacd97d34710ef78c1688afc2387c97a833a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -10,13 +10,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -24,13 +20,10 @@ unsigned long get_board_ddr_clk(void); /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -53,23 +46,6 @@ unsigned long get_board_ddr_clk(void); #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg -#endif -#endif - /* LPUART */ #ifdef CONFIG_LPUART #define CONFIG_LPUART_32B_REG @@ -79,13 +55,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SCSI_AHCI_PLAT /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -191,7 +162,6 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT #endif /* @@ -395,8 +365,6 @@ unsigned long get_board_ddr_clk(void); * Environment */ -#define CONFIG_CMDLINE_TAG - #include <asm/fsl_secure_boot.h> #endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 84b83e6259563aef0dd58d6cf18f3e6941ee1b51..906cd09f6ebbffd14755452e74fdd760fb6923a4 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,7 +9,6 @@ #include "ls1043a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -21,20 +20,10 @@ #ifndef CONFIG_SPL #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 @@ -228,13 +217,8 @@ /* EEPROM */ #ifndef SPL_NO_EEPROM -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif /* diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 289acc02d3807a2a92cc888c653c34b29a221bc8..f0bde08f2460957022608a9f0d7bfccb8a24f658 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -27,7 +27,6 @@ #endif #define CONFIG_REMAKE_ELF -#define CONFIG_GICV2 #include <asm/arch/config.h> #include <asm/arch/stream_id_lsch2.h> @@ -39,8 +38,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #endif -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -52,16 +49,11 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* SD boot SPL */ #ifdef CONFIG_SD_BOOT #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ @@ -108,7 +100,6 @@ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_WATCHDOG #define CONFIG_SPL_I2C -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_DRIVERS_MISC @@ -133,16 +124,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ @@ -195,7 +176,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index fade815f26088ba1b13be78466eb52fefffca48c..7da08605f5abf2feb84bdb2b6f4c63c43ab9a713 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -9,7 +9,6 @@ #include "ls1046a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -74,13 +73,8 @@ #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define I2C_RETIMER_ADDR 0x18 /* I2C bus multiplexer */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 9102c812b5bc887bf7a40cefff4d38e21e573005..b6bbc01304a7c378395034b0b25213c966790d36 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -10,13 +10,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -24,13 +20,10 @@ unsigned long get_board_ddr_clk(void); /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -55,26 +48,6 @@ unsigned long get_board_ddr_clk(void); #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046aqds/ls1046aqds_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg -#endif -#endif - /* IFC */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC @@ -103,13 +76,8 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * IFC Definitions @@ -209,7 +177,6 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT #endif /* @@ -410,8 +377,6 @@ unsigned long get_board_ddr_clk(void); * Environment */ -#define CONFIG_CMDLINE_TAG - #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index dddaa25417180bfe68d5c02ac4833ccd1615edfa..d3f5d8ce95ea1d21510af9e1a9ba226548001d96 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -10,7 +10,6 @@ #include "ls1046a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -18,27 +17,12 @@ /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg -#ifdef CONFIG_EMMC_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg -#endif -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg +#if defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_UBOOT_BASE 0x40100000 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #endif @@ -135,20 +119,11 @@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define I2C_RETIMER_ADDR 0x18 /* PMIC */ -#define CONFIG_POWER -#ifdef CONFIG_POWER -#define CONFIG_POWER_I2C -#endif /* * Environment diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 3f0679cf05ad7f11bb5b0803ebf4d2036a9a9255..9ae0b8e0ae4f227b6c28c00983da1c1b5fb29c69 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -37,8 +37,6 @@ /* Link Definitions */ #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -50,9 +48,6 @@ */ #define CPU_RELEASE_ADDR secondary_boot_addr -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* GPIO */ #ifdef CONFIG_DM_GPIO #ifndef CONFIG_MPC8XXX_GPIO @@ -61,9 +56,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* Serial Port */ @@ -71,8 +63,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) /* IFC */ #define CONFIG_FSL_IFC @@ -147,7 +137,6 @@ unsigned long long get_qixis_addr(void); #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* SATA */ #ifdef CONFIG_SCSI diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 78ccc2dc5bfc8e3d0a548be961816ac9c7c2829f..a7d8cb50fcc183338a7e9c5e838e5436d1fecb4f 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -11,7 +11,6 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_TFABOOT @@ -23,14 +22,9 @@ unsigned long get_board_ddr_clk(void); #define SYS_NO_FLASH #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #else #define CONFIG_QIXIS_I2C_ACCESS -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) @@ -38,9 +32,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -335,13 +326,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index ad3043bbdb3412284a64cb9a50cebb3b9173d338..4a61345db2e51729fd12fb53363f3d6d36e95f33 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -17,18 +17,12 @@ #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -#define CONFIG_DDR_SPD #ifdef CONFIG_EMU #define CONFIG_SYS_FSL_DDR_EMU -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 #else -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #define SPD_EEPROM_ADDRESS 0x51 @@ -241,13 +235,8 @@ #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 45273364cf39346ed90498c4203b44259827d048..6d9ae9d987ea6cbdcbf2403641e60344d8c8f16b 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -8,7 +8,6 @@ #define __LS2_COMMON_H #define CONFIG_REMAKE_ELF -#define CONFIG_GICV3 #include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h> @@ -24,8 +23,6 @@ /* Link Definitions */ -#define CONFIG_SKIP_LOWLEVEL_INIT - #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_DDR_RAW_TIMING #endif @@ -63,9 +60,6 @@ */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* GPIO */ #ifdef CONFIG_DM_GPIO #ifndef CONFIG_MPC8XXX_GPIO @@ -74,17 +68,12 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* IFC */ #define CONFIG_FSL_IFC @@ -157,7 +146,6 @@ unsigned long long get_qixis_addr(void); #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* Physical Memory Map */ /* fixme: these need to be checked against the board */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 8bfe4b9811c90872722c403cbad9b1884b35cf57..e831d3797d18e1aaa671d0a6c0952c6a2e447e26 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -11,25 +11,17 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FSL_QSPI #define CONFIG_QIXIS_I2C_ACCESS -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -304,13 +296,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index bfbde1da9785eb72b8c72997efffbe1ddb17b995..5568a48ced9ca32ca2a8c5fae50b3c27057b5030 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -13,9 +13,6 @@ #ifdef CONFIG_TARGET_LS2081ARDB #define CONFIG_QIXIS_I2C_ACCESS #endif -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #endif #define I2C_MUX_CH_VOL_MONITOR 0xa @@ -39,12 +36,8 @@ unsigned long get_board_sys_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -286,13 +279,8 @@ unsigned long get_board_sys_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index a4a4739d0dd7a910bc9e52de67ca0e4da1162f83..7294a3c20a5a4d4453d6ebc6a57a07327c8daf43 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -12,10 +12,8 @@ */ #if defined(CONFIG_LSCHLV2) #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg -#define CONFIG_MACH_TYPE 3006 #elif defined(CONFIG_LSXHL) #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg -#define CONFIG_MACH_TYPE 2663 #else #error "unknown board" #endif @@ -26,8 +24,6 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - #define CONFIG_KIRKWOOD_GPIO #include "mv-common.h" @@ -45,7 +41,6 @@ /* * Default environment variables */ -#define CONFIG_LOADADDR 0x00800000 #if defined(CONFIG_LSXHL) #define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1ae7d37dd9f665922b9f938edc842f3d68eafba1..dddac7b05c35036dae28a2f1ffcf033f59960a12 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -12,15 +12,12 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_MEMAC #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - /* DDR */ #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ @@ -30,9 +27,6 @@ #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 @@ -49,7 +43,6 @@ #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* SMP Definitinos */ #define CPU_RELEASE_ADDR secondary_boot_addr @@ -62,9 +55,6 @@ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* Serial Port */ #define CONFIG_PL01X_SERIAL #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) @@ -77,7 +67,6 @@ (void *)CONFIG_SYS_SERIAL1, \ (void *)CONFIG_SYS_SERIAL2, \ (void *)CONFIG_SYS_SERIAL3 } -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* MC firmware */ #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 @@ -110,13 +99,8 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Qixis */ #define CONFIG_FSL_QIXIS @@ -157,11 +141,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) #define CONFIG_HWCONFIG diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index ea1b1635fe9f909255911a48e8b5f81533beeb48..30b044bd00721406834fe19895fb7cfa3067ec04 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -34,13 +34,8 @@ u8 qixis_esdhc_detect_quirk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 097f1224c90fa157f57df41df3d7b405ddfa8073..ebe5004f440929d0039cbfcc14eaffb9a1be4749 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -30,13 +30,8 @@ #define I2C_EMC2305_PWM 0x80 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 847534c5505c64ec0d2484ea01105c93853c7456..7fa3c256302409c7eb2e2607b212fa3f6243a440 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -38,13 +38,8 @@ u8 qixis_esdhc_detect_quirk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index bd117daf063f9df24465160417e5dac9fcf296fa..813d326cdaf50042e77bcefa431e3e741215d266 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -11,7 +11,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_REVISION_TAG #define CONFIG_SYS_FSL_CLK #define CONFIG_TIMESTAMP /* Print image info with timestamp */ @@ -24,7 +23,6 @@ #define PHYS_SDRAM_2 CSD1_BASE_ADDR #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) @@ -84,17 +82,7 @@ #define CONFIG_ETHPRIME "FEC0" #endif -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ -#endif /* * RTC @@ -141,14 +129,8 @@ /* * Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTFILE "boot/fitImage" -#define CONFIG_LOADADDR 0x70800000 #define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* * NAND SPL diff --git a/include/configs/malta.h b/include/configs/malta.h index 9602773ff91f924d11b86a8d96159d39a2999cb2..8ace0ccd7eb8c22b345d1061f088c90aef795bc7 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -38,9 +38,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index fc2393204bec762223c54a95be49091d7c8fc570..53ba64909e1f3f57a1da736ec762a6e0b23d87c6 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -6,6 +6,8 @@ #ifndef _CONFIG_DB_MV7846MP_GP_H #define _CONFIG_DB_MV7846MP_GP_H +#include <linux/sizes.h> + /* * High Level Configuration Options (easy to change) */ @@ -17,11 +19,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* SPI NOR flash default params, used by sf commands */ @@ -65,7 +63,7 @@ /* SPL related SPI defines */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_SYS_SDRAM_SIZE SZ_1G #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 0c383e94cc0242fa69b52ed0ba124e6b6aef7f77..a0803227c88f8acefc7939cf5410aa37e1014e3f 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -25,9 +25,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index f43a8415e1aa854c603574e5e9930378722f75b9..ac9a75bf2dea11a53e04475d7bed25c0efa48e17 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -14,10 +14,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index bd4bac7aab38f7768ac9ed8c730016f68195ba51..3457c598857d6d59de6fe9e0742fa4a9a2a45b02 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -32,12 +32,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ /* Misc CPU related */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ /* * Hardware drivers @@ -58,8 +52,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) - /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, * leaving the correct space for initial global data structure above @@ -100,10 +92,4 @@ #define CONFIG_SYS_CBSIZE 512 -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128*1024, 0x1000) - #endif diff --git a/include/configs/meson64.h b/include/configs/meson64.h index f9bb0240d2c37a141494a3dd806946c9009aea3d..b779363b2b0831dcaee8729980f37448d64307f8 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -32,14 +32,10 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF #define CONFIG_SYS_MAXARGS 32 -#ifndef CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_MALLOC_LEN (32 << 20) -#endif #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 358e0a5c714aca2d852ea3d000cd70cd9ef4d392..fb3ccc329a7ec0f03a804b7532752d193eef3f98 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -11,8 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_MALLOC_LEN SZ_128M - #ifndef BOOT_PARTITION #define BOOT_PARTITION "boot" #endif diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 59b20cf116a838e6161dbbe5a57a68e0e4170bae..e7882fb60781f51c99c0f0709866b3372c7822d8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -24,8 +24,6 @@ /* setting reset address */ /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ -#define CONFIG_SYS_MALLOC_LEN 0xC0000 - /* Stack location before relocation */ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_F_LEN) @@ -55,8 +53,6 @@ #define CONFIG_SYS_CBSIZE 512 /* max number of command args */ #define CONFIG_SYS_MAXARGS 15 -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0 #define CONFIG_HOSTNAME "microblaze-generic" diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 24990370cf042a19565b778c5019567a77277392..655c8d6af5dab785c0573473e6e2dd3ebfe69998 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -12,10 +12,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 4d074a3688824bffb4a105f70e1f6f90b1250d2f..a2de03429218c1b90f9b883f3ec7a5b799ee7bb0 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -13,11 +13,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x100000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x80010000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 @@ -26,13 +24,7 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -/* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index f015d10d9bdb094cc567cb06185ccebc060726d1..97fcf2f87bdc6adfe09e48479aec026d5e5c4453 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_CBSIZE SZ_1K #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Uboot definition */ @@ -27,10 +25,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ GENERATED_GBL_DATA_SIZE) -/* UBoot -> Kernel */ -#define CONFIG_LOADADDR 0x4007ff28 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 9895279749db978dfb20dae0f75824ed9900e7c0..6023f8128efc78a4f5a7cd3fde73833f4cc668e5 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> /* Miscellaneous configurable options */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG #define CONFIG_SYS_MAXARGS 8 #define CONFIG_SYS_BOOTM_LEN SZ_64M @@ -22,8 +19,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ @@ -32,10 +27,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ GENERATED_GBL_DATA_SIZE) -/* UBoot -> Kernel */ -#define CONFIG_LOADADDR 0x84000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* MMC */ #define MMC_SUPPORTS_TUNING diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index c6752f4acb721b8c570f7de25fe957c4f862bc2e..e53e6a0d0a0e370fa1fe846805196f0a58fde72b 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -13,11 +13,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x100000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x80010000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 @@ -27,7 +25,7 @@ #define CONFIG_SYS_CBSIZE 1024 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -39,9 +37,6 @@ 230400, 460800, 921600 } /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 08a4d01f5524fd1f513f8662b68a2b936a588cb0..c58545be04b6d7b76fc3ef4a54528db9f918ef44 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> /* Miscellaneous configurable options */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG #define CONFIG_SYS_MAXARGS 8 #define CONFIG_SYS_BOOTM_LEN SZ_64M @@ -22,8 +19,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ @@ -43,8 +38,6 @@ /* UBoot -> Kernel */ #define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 -#define CONFIG_LOADADDR 0x42007f1c -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index 8e7afbb48a77632fe7909e1d213d09750542dd6f..ebd2b326ade0ef87264cdd9801ae4647c178a6ad 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -11,9 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN SZ_4M - #define CONFIG_CPU_ARMV8 #define COUNTER_FREQUENCY 13000000 diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 7cd388fa10115d0d9e2405a5d6cedb1d618abae6..8882a5a409703458f6dec262700770aa5cb97782 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -17,10 +17,6 @@ #define COUNTER_FREQUENCY 13000000 -#define CONFIG_SYS_LOAD_ADDR 0x41000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Uboot definition */ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index a1c5d8174be79448e485fdbfab0f3ec3e602eb7c..12840b883decf091aae89126633dbc343bfdb698 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -11,9 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN SZ_4M - #define CONFIG_CPU_ARMV8 #define COUNTER_FREQUENCY 13000000 diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 4e32442bb5a5ba64efe84db9f3ceaedcbeec97c6..593c6a11d7420662d75a80162f08d316546ca2d9 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -21,10 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_LOAD_ADDR 0x41000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Uboot definition */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6036bf4fa5d7b9c4b4b6c6a1c36c8784a8a8ca72..e460f69a08736a7769b0705675bef0ee54e3af20 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -50,26 +50,11 @@ /* auto boot */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h index 486650f183fbacbec306c13462e07865c6a8b4ea..d38d9872c006cd3911def960c2b459b3da28c484 100644 --- a/include/configs/mv-plug-common.h +++ b/include/configs/mv-plug-common.h @@ -11,7 +11,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index c8c34d7d92dd57625bfc476696d0d4426f3bec1b..755f59eee98755a6ced9e8e84e37f46aaecd9b0e 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -25,26 +25,11 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x06000000 /* default load adr */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ @@ -55,7 +40,6 @@ * I2C */ #define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 /* * Environment diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 493e3de9b9f852058cb7c78e2d58f54eebdb8b8d..beecf1838e475e44bb83bc43eab967707e9eb66a 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -19,26 +19,11 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 2ee41aeff1b7039ec394de2126232d8a3edddbbb..b0c78d3561cb9ffdd7a36683bb836408feb02248 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -5,9 +5,6 @@ #ifndef __CONFIGS_MX23_OLINUXINO_H__ #define __CONFIGS_MX23_OLINUXINO_H__ -/* System configurations */ -#define CONFIG_MACH_TYPE 4105 - /* U-Boot Commands */ /* Memory configuration */ @@ -27,8 +24,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 3f13e60531cfd7d746d5293a2465b7d301aebffb..1f40d98be003193c4a87da6ff79f81fc114d7647 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -8,9 +8,6 @@ #ifndef __CONFIGS_MX23EVK_H__ #define __CONFIGS_MX23EVK_H__ -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK - /* U-Boot Commands */ /* Memory configuration */ @@ -36,8 +33,6 @@ /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 21f3277d5c43c363c05db5f7ba4a08792086ee47..10292c86fac7d638421ed96eb4506a345d7f5445 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -10,9 +10,6 @@ #ifndef __CONFIGS_MX28EVK_H__ #define __CONFIGS_MX28EVK_H__ -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK - /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ @@ -50,8 +47,6 @@ /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3574d6545164a37bd3626e9a23e39c24d2ea67ae..9cc297da30ed3649daf57a57f27a2a9ccbe4e83e 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -16,17 +16,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - /* * Hardware drivers */ @@ -35,7 +24,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_POWER #define CONFIG_POWER_SPI #define CONFIG_POWER_FSL #define CONFIG_FSL_PMIC_BUS 0 @@ -61,8 +49,6 @@ #define CONFIG_ETHPRIME "FEC0" -#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -140,8 +126,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 93158fb464696623fbdf110d39a329c0ffd8a60b..f03e42529761cb288c16caa2a4aac3a84789828a 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -14,17 +14,8 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - #define CONFIG_MXC_UART_BASE UART2_BASE #define CONFIG_FPGA_COUNT 1 @@ -43,8 +34,6 @@ /* Command definition */ -#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ @@ -72,8 +61,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index e69130d520851862d73cc89fa20190cd4bbbda62..b026c6ff89f2d5b903ef627af888c2b4bd3a2da5 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -9,21 +9,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO - #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -35,16 +24,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - /* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_DIALOG_POWER #define CONFIG_POWER_FSL #define CONFIG_POWER_FSL_MC13892 @@ -56,8 +36,6 @@ #define CONFIG_ETHPRIME "FEC0" -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -132,8 +110,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b1e6a5638b6cc46237a327226ecbc5af5271d59d..b6232422567188015cabac05186e0d5150dab984 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -11,17 +11,8 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - /* USB Configs */ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX @@ -33,8 +24,6 @@ /* Command definition */ -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - #define PPD_CONFIG_NFS \ "nfsserver=192.168.252.95\0" \ "gatewayip=192.168.252.95\0" \ @@ -102,11 +91,11 @@ "video-mode=" \ "lcd:800x480-24@60,monitor=lcd\0" \ -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "run doquiet; " \ "run tryboot; " \ -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND #define CONFIG_ARP_TIMEOUT 200UL @@ -116,8 +105,6 @@ #define CONFIG_SYS_MAXARGS 48 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ /* Physical Memory Map */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index a4504ee27ae25366b65f1145cef092c4e5c9a005..5c0b729ccd971d1b1e6f979bb562b9e0edc57fb0 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -33,22 +33,6 @@ #define CONFIG_SYS_FSL_CLK -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Boot options */ -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ - defined(CONFIG_MX6SX) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_LOADADDR 0x82000000 -#else -#define CONFIG_LOADADDR 0x12000000 -#endif -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 32 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 9e5083b0d876e368a45f67057459f8f6e3e87125..da2533637b03b250cb49a2fa2b07d21e8a1a0041 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -13,8 +13,6 @@ #include "imx6_spl.h" -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -46,9 +44,9 @@ "fdtfile=undefined\0" \ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 120297dac8616f97ef971fbe96959a79583fc8fa..42d5e248ba16f6aa2d0a4c8b5df680838543c674 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -13,8 +13,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) - #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ac579f3338a360c22f6d0b5c8cf1509f4d92d2db..51f6b3ac462c4a31715ba13233664ca216ca1306 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -52,7 +49,7 @@ "dfu_alt_info=spl raw 0x400\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 626dbd55d7992c2ac2281ce91dd195c5da551323..5cd51a4af06fdab5df4b444c48183f1fce35e87d 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -12,7 +12,6 @@ #include "imx6_spl.h" #endif -#define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" @@ -50,14 +49,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -67,8 +58,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 9546887182bd1cb3133bca246b12aa929e0d1c7d..9a9f5884aacb9f22c9195436cf8a0897c127b947 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,7 +12,6 @@ #include "imx6_spl.h" #endif -#define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" @@ -37,17 +36,7 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ab32f4e151e8aa4cfa9377131a627bcf138437a5..e8fd2126f7b4b3e28a9b081f16de6fd0a21b3dee 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -14,23 +14,11 @@ #include "imx6_spl.h" #endif -#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index a38ce4d09777512512f20523cce990e791826070..f2bddd13bd039df816856d4848a0975d188561d5 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -10,20 +10,8 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE -/* I2C Configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 58cc3f0ee2b69251ffb7a10e12238756c85c2429..62b8de3c1aa4246d2c24474b97e65dff7494657d 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -10,9 +10,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -106,13 +103,6 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 036881f6ea3ec986fbc7efb4a2fc705a3b67ad16..1237ddef8e31b4c05857f58ee90ba9927b4a4c0c 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -16,9 +16,6 @@ #include "imx6_spl.h" #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX @@ -140,13 +137,6 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* Network */ #define CONFIG_FEC_MXC diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 7d36c1e4d90aecae5ec3f3080faf592f791a1f99..ff2ad094a7d34e4570f166c0ff6c96ff87945717 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -18,9 +18,6 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -36,14 +33,6 @@ #endif -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -56,7 +45,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ @@ -135,7 +124,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 23f6de9050cdf0e0b33619aaa0e5c85999d467c2..247d5e1bcc3a5d39de43d687530168a77d6c69bc 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -33,14 +30,6 @@ #endif #endif -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -132,7 +121,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 3d8769038276c69c61faec57e381920170d37f05..eeb535efa1b8cd103522cc2918136b52b8894c3f 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -28,8 +28,6 @@ /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR -#define CONFIG_LOADADDR 0x80800000 - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 32 @@ -49,10 +47,5 @@ * launched by OPTEE, because of that we shall skip all the low level * initialization since it was already done by ATF or OPTEE */ -#if (CONFIG_OPTEE_TZDRAM_SIZE != 0) -#ifndef CONFIG_OPTEE -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#endif #endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 5801da0cfac44df9ed1d309b3d36f105b3147b79..42b729b40bc8b401a0ebd2eeeac88d00f2743863 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -14,16 +14,9 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #ifdef CONFIG_IMX_BOOTAUX @@ -79,11 +72,11 @@ "fdtfile=imx7d-sdb.dtb\0" \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x83100000\0" \ "ramdiskaddr=0x83100000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ BOOTENV @@ -94,7 +87,6 @@ #include <config_distro_bootcmd.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 28672c4f94c493d5bf2b96ce848205382833df0a..48172de1d0fa2daa6e20381d9c403721dd940545 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -32,13 +32,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -47,8 +40,6 @@ #define PHYS_SDRAM 0x60000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_LOADADDR 0x60800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttyLP0\0" \ @@ -74,8 +65,6 @@ "run mmcboot; " \ "fi; " \ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 0c3103082cc8e830337f0893bcba1c3098558239..567a037089d7aa13832996a908757f2023c7c8a6 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -22,19 +22,9 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -/*#define CONFIG_REVISION_TAG*/ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - /* UART */ #define LPUART_BASE LPUART4_RBASE -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 512 @@ -47,8 +37,6 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_LOADADDR 0x60800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -125,7 +113,6 @@ "fi" #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 325c3ee00ce367837062ec8aac8c4212dc40f9c0..64f017ab77f89740337d34e43e798096006be2c3 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -50,7 +50,6 @@ #endif /* Memory sizes */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 @@ -85,10 +84,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot argument buffer size */ -/* Booting Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - /* * Drivers */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 5ef16fb278eec4f55d831ede558f1bb8a5d5c17d..04c9879ccca5bbbc6d5032ac9071b0396b127995 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -15,16 +15,12 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 1fd5471ac5ffe98af000b69b8e0d4107a639014a..16bbc9b049f2ff22efd1a68571149dc34e994711 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -11,17 +11,11 @@ #ifndef _CONFIG_NAS220_H #define _CONFIG_NAS220_H -/* - * Machine type ID - */ -#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS - /* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ #define CONFIG_KW88F6192 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* power-on led, regulator, sata0, sata1 */ #define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) @@ -87,4 +81,3 @@ #define CONFIG_KIRKWOOD_GPIO #endif /* _CONFIG_NAS220_H */ - diff --git a/include/configs/netgear_cg3100d.h b/include/configs/netgear_cg3100d.h index 8d2b3e73a0480e6ed96dedc6c1cbcae0b44707ee..59468a4c55907b5c8f9bff9389753e7bee90c304 100644 --- a/include/configs/netgear_cg3100d.h +++ b/include/configs/netgear_cg3100d.h @@ -5,4 +5,3 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm3380.h> - diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h index 779c20700a9a9ceb7e8b1fcee33c01b4266526f5..f14316c84564635b299cdba4ff8d365c483908af 100644 --- a/include/configs/netgear_dgnd3700v2.h +++ b/include/configs/netgear_dgnd3700v2.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6362.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 0c407503517dae9f1b7b64b6efb61b4fc7465801..cd53c498975d5c425a873fd7a035ee47ab495c0f 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,22 +11,11 @@ #include "mx6_common.h" -#define CONFIG_MACH_TYPE 3769 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - #define CONFIG_USBD_HS #define CONFIG_MXC_UART_BASE UART2_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID /* MMC Configs */ @@ -90,14 +79,6 @@ #define DISTRO_BOOT_DEV_DHCP(func) #endif - -#if defined(CONFIG_SABRELITE) -#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" -#else -/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ -#define FDTFILE -#endif - #define BOOT_TARGET_DEVICES(func) \ DISTRO_BOOT_DEV_MMC(func) \ DISTRO_BOOT_DEV_SATA(func) \ @@ -113,10 +94,10 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ - FDTFILE \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ "ip_dyn=yes\0" \ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 7ef25ea8389c8889957e78db760dbfa2273bd32a..b37e05406e92a4b5eb8c24fe72baabd9ca8a2ab9 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -23,8 +23,6 @@ */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ -#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> #include <asm/arch/mem.h> @@ -34,19 +32,7 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ - -#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ -#define CONFIG_INITRD_TAG /* enable passing initrd */ -#define CONFIG_REVISION_TAG /* enable passing revision tag*/ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -/* - * Size of malloc() pool - */ #define CONFIG_UBI_SIZE (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ - (128 << 10)) /* * Hardware drivers @@ -188,9 +174,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "run attachboot;" \ "echo" -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). diff --git a/include/configs/novena.h b/include/configs/novena.h index 3876412ee6eedd2a672ba4e9ad150a89496aa079..28fb1b8d7531c6499ce1e057686be24a7d04600d 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -41,8 +41,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) - /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ @@ -52,20 +50,10 @@ #endif /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ -#ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 -#endif /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -80,8 +68,6 @@ #endif /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 @@ -115,10 +101,10 @@ "bootdev=/dev/mmcblk0p1\0" \ "rootdev=/dev/mmcblk0p2\0" \ "netdev=eth0\0" \ - "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ - "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ - "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ - "ramdisk_addr_r=0x28000000\0" \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "pxefile_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "ramdisk_addr_r=0x28000000\0" \ "fdt_addr_r=0x18000000\0" \ "fdtfile=imx6q-novena.dtb\0" \ "stdout=serial,vidconsole\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 3be9b8ff55ffea11b5ce7629d5f8bb8253ce79ff..70e2898c14504f52b0fd4deead087097b7289593 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -15,9 +15,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* Size of malloc() poll */ -#define CONFIG_SYS_MALLOC_LEN SZ_2M - /* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE @@ -26,7 +23,6 @@ #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 23cf94ec99209378fd9f00d251497f935da81b4e..950549c31ca455df93554390513299e71079a3d7 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -13,7 +13,6 @@ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6192 1 /* SOC Name */ #define CONFIG_KW88F6702 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/nsim.h b/include/configs/nsim.h index 61217bbe7956d2c7757301a2251e5823b99aa6b6..62169af676f69518f8f44abdf58be747714005cc 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -20,15 +20,12 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_32M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* * Console configuration diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 394fb15f3136693781c97da3f6bf4557e9bcc730..3584d9ad90e1d327aceae08c3750bbe7a4a29de1 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -26,9 +26,6 @@ /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) -#undef CONFIG_LOADADDR -#define CONFIG_LOADADDR 0x82408000 - #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index b9746b9b1c5470361b9d83718873aed1bd0fd502..72515a32e16d3d243c606cd85837646b1c41cf86 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -6,7 +6,6 @@ #include "mx6_common.h" -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 109ef4064dec785ac5cf2b459952999eb88bc3a4..23bb4f676f8ec53f168882b283591fa6eb68d57f 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,19 +8,15 @@ #define __OCTEON_COMMON_H__ #if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_MALLOC_LEN (16 << 20) #define CONFIG_SYS_INIT_SP_OFFSET 0x20100000 #else /* No DDR init -> run in L2 cache with limited resources */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 #endif #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) - #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 280089617f10a754624fe70c2f058665b6f7027b..5e1c0073b0b3589d4696177e2e0557301a3780b3 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -18,11 +18,6 @@ /** Stack starting address */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) -/** Heap size for U-Boot */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - #define CONFIG_LAST_STAGE_INIT /* Allow environment variable to be overwritten */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 0e4a17684f91c88dc04e0690423e42036459cb82..3ceedef1c6ee5b6c4ffec6bf97e2fb6b3794c028 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -44,9 +44,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) /** Heap size for U-Boot */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Allow environment variable to be overwritten */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 1367d13891aaa5864b41a9a1602c353b7abc0b1b..281922af4a8de35a579690a72553c93e2c2405d7 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_MACH_TYPE 4289 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE @@ -28,9 +26,6 @@ #define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) #define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - #include <linux/sizes.h> #define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" @@ -174,6 +169,4 @@ */ #define CONFIG_MISC_COMMON -#undef CONFIG_REVISION_TAG - #endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index fc70dc6a7323475a12cb895f801c9033838482c2..70481b5d0c8c2485720f973035daa25749bb4cb3 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -75,7 +75,6 @@ /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ #define CONFIG_ODROID_REV_AIN 9 -#define CONFIG_REVISION_TAG /* * Need to override existing one (smdk5420) with odroid so set_board_info will diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 6563335f91db035d2d6da5d316a31a514e32765d..8c830d916c16901803686048cb41e687572a304a 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -18,11 +18,6 @@ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE @@ -46,9 +41,6 @@ #endif /* CONFIG_SPL_OS_BOOT */ #endif /* CONFIG_MTD_RAW_NAND */ -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 - /* Enable Multi Bus support for I2C */ #define CONFIG_I2C_MULTI_BUS @@ -211,7 +203,7 @@ "${defargs} " \ "${optargs} " \ "root=${ramroot} ramdisk_size=${ramdisk_size} " \ - "rootfstype=${ramrootfstype}\0" \ + "rootfstype=${ramrootfstype}\0" \ "ramboot=run mmcbootenv; " \ "if run loadimage && run loaddtb && run loadramdisk; then " \ "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 2ce3c867cb143e4016ebcef611349ff9258e5bb0..b12e3a40285730274bcd647e22f04bae0359936d 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -23,11 +23,6 @@ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 8dc30be8b72d26201931b3f60ba4bf70e6232bfe..0fee2ed921caabe093b55ccb74d6ec800d7c044f 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -16,8 +16,6 @@ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_REVISION_TAG 1 - /* TPS65950 */ #define PBIASLITEVMODE1 (1 << 8) diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index dd0ea2dbde2ab76ce51825c59b02479e96ff38eb..cac35ef0795ffe11e59d6afc29f4b6f9aad912d1 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -14,29 +14,6 @@ #include <configs/ti_omap3_common.h> -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in - * order to allow for BCH8 to fit in. - */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Hardware drivers */ - -/* I2C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_USB_EHCI_OMAP -#endif -#ifdef CONFIG_USB_EHCI_OMAP -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 -#endif - /* Board NAND Info. */ #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 14eb363816ae3fa5b5e33bf4852fc11b664f0f32..69749ab630221372c2f429c644c886b0fb2f9171 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -11,22 +11,6 @@ #ifndef __CONFIG_PANDA_H #define __CONFIG_PANDA_H -/* - * High Level Configuration Options - */ - -/* USB UHH support options */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 - -/* USB Networking options */ - -#define CONFIG_UBOOT_ENABLE_PADS_ALL - #include <configs/ti_omap4_common.h> -/* GPIO */ - -/* ENV related config options */ - #endif /* __CONFIG_PANDA_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 462aa4a5b902bc76c607182297145060279cebf0..fb210ce69b3c0a2949acb1b924b9d13d509d844b 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -15,7 +15,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP #include <configs/ti_omap4_common.h> diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index a1f1dafad79ba76c6ca3b4c1e2ddc8fe44d41675..188ab0bf365daceec926959d0673ca55a1365bf0 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -43,9 +43,6 @@ /* USB UHH support options */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 -#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 - /* Enabled commands */ /* USB Networking options */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index a37359e6c326b6b4514913f6cbeb86b5df5a1616..d20c9e238c30ab4c592d98938f286f60fc640e85 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -17,18 +17,15 @@ /* * SoC Configuration */ -#define CONFIG_MACH_OMAPL138_LCDK #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -161,7 +158,6 @@ #define CONFIG_BOOTFILE "zImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * USB Configs @@ -173,9 +169,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTCOMMAND \ "run envboot; " \ "run mmcboot; " diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 42c64f3ca5e66faebaf702bffe0ccc018c568dee..a24b13497516a7de265b0b0fe910623279fb49c8 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -16,8 +16,6 @@ /* Environment options */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) -#define CONFIG_SYS_LOAD_ADDR 0x87000000 -#define CONFIG_SYS_MALLOC_LEN SZ_256M #define CONFIG_SYS_BOOTM_LEN SZ_256M #ifdef CONFIG_SPL diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 03b9393c9b09ffcfa410813d900d8cdc492020a7..56bfe8747ef8e6df45da3e3a526db722fbc2f556 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -18,7 +18,6 @@ */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 2fb1634a7de4b2f4c8eb340ac098f4f98e184981..f9db8efd2fd27e14ca6bd47920222481582174eb 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -18,9 +18,6 @@ #endif #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - /* Miscellaneous configurable options */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR @@ -78,7 +75,7 @@ "mmcrootfstype=ext4 rootwait\0" \ "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ "splashpos=0,0\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ "check_env=if test -n ${flash_env_version}; " \ "then env default env_version; " \ diff --git a/include/configs/origen.h b/include/configs/origen.h index 8a0e145c76c613ad46a4847f980998d07fe9c3d6..881df2d3b0b7227feb5ae4f2759509e646715c19 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -19,11 +19,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN - #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ #define CONFIG_SYS_MONITOR_BASE 0x00000000 diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index 4ef9e8ed5d844f8d3b6d34a826866f88a716a700..96453214eeb98f2db5f0586ac294ae4f02511982 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -16,10 +16,7 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (24000000) /* 24MHz */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - /* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) /* * This is the initial SP which is used only briefly for relocating the u-boot diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 54c82b4f33525087138a3b077c32727a94a3260a..58336110568cbecee19f5e8e8bbe004e7ce86d31 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -157,7 +157,6 @@ #else #define CONFIG_SYS_CLK_FREQ 66666666 #endif -#define CONFIG_DDR_CLK_FREQ 66666666 #define CONFIG_HWCONFIG /* @@ -179,7 +178,6 @@ /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 @@ -346,7 +344,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ #define CONFIG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -464,36 +461,20 @@ /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 #endif -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ /* * I2C2 EEPROM */ -#undef CONFIG_ID_EEPROM #define CONFIG_RTC_PT7C4338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #if defined(CONFIG_PCI) /* @@ -607,7 +588,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -617,10 +597,6 @@ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - /* * Environment Configuration */ @@ -629,9 +605,6 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ @@ -691,7 +664,7 @@ __stringify(__SD_RST_CMD)"\0" \ __stringify(__NAND_RST_CMD)"\0" \ __stringify(__PCIE_RST_CMD)"\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -700,7 +673,7 @@ __stringify(__PCIE_RST_CMD)"\0" "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ "console=$consoledev,$baudrate $othbootargs;" \ "usb start;" \ @@ -733,7 +706,7 @@ __stringify(__PCIE_RST_CMD)"\0" "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ "bootm $norbootaddr - $norfdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs " \ "ramdisk_size=$ramdisk_size;" \ @@ -742,6 +715,6 @@ __stringify(__PCIE_RST_CMD)"\0" "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#define CONFIG_BOOTCOMMAND HDBOOT #endif /* __CONFIG_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 7a09ac0dee738afca0d30ddcec126e9ff502ea98..c12f4d0937d5124567446977ec3e70b040a6e0bd 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -19,8 +19,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 4f4d50131f5619fce60b52ee1150135d0b2a7617..f29f6dc5857e9f60eea8a80c6ccec2cf77b28f06 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE @@ -36,7 +33,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 6009521c9f727461a3b016e073b68c2266819713..c1da1a0119467de9c1c49bca6c042648168af069 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Environment settings */ /* Environment in SD */ @@ -36,14 +33,9 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 960ff982d8b7d9d99cd93fd36eccf13447e9a942..5b2e084a2245384569a67a01960197d1f7da457c 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -12,21 +12,11 @@ #include <linux/sizes.h> #include <linux/stringify.h> -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_LOADADDR 0x82000000 - /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 @@ -139,8 +129,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical memory map */ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index bc48e809498a6cda13a5f761a9f3500c0d73e00a..3ca03774506c8d818f13a3a2a039d62cbe1cf23c 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -14,9 +14,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - /* Enable NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 53342ce193a40648d152a2a0fe1fa65059d715a4..3d18747f9b65c2d05b9900f4b64e51079aea99cf 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -14,9 +14,6 @@ /* Using 32K of volatile storage for environment */ -#define MACH_TYPE_PDU001 5075 -#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 4a347fe154fadad0779a6a94827f4ffa9db8ba33..4925fcc8cfd069fce93e507bfde6537830e2b79d 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -14,8 +14,6 @@ #include <configs/ti_am335x_common.h> -#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X - #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index fd69dc41a86e9e7d063f6cb1390eedd29590ac90..8d1fd153f62f8909abe3389f694bf9e7c0ae00e3 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -82,8 +82,6 @@ "fi;" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K @@ -94,8 +92,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM SZ_1G @@ -117,9 +113,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* ENET1 */ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 58ead45941c5c9b795c007551f90126964b87790..874c94e01f917582f67e4bf94a242f2d8808b97d 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -29,12 +29,8 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PCA9450 -#define CONFIG_SYS_I2C_LEGACY - #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -84,8 +80,6 @@ "fi;" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K @@ -96,8 +90,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -117,7 +109,4 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - #endif /* __PHYCORE_IMX8MP_H */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index d50edc7715f5a4c46d53ca38634544bf7c649ed9..a83e49ff3ba91f4b226d2ea2ef3e992f63798f23 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -28,13 +28,11 @@ /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x88000000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) -#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ #define CONFIG_SYS_ENV_ADDR 0x88300000 #define CONFIG_SYS_FDT_ADDR 0x89d00000 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 6199f0d72e7625c0895153425d629d153e7e00a6..4e72caa45d7a21cbcda2fb302fb64b39e34747ee 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ @@ -94,11 +91,11 @@ "run base_boot;" \ "fi; \0" \ "base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 04a2531f744764c91dfe3bba1c3a883a16d82369..7e36ceed3fe89d8bfef7f071df166c971db51861 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -33,9 +33,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_FEC_XCV_TYPE RMII -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR /* MMC Configs */ @@ -82,11 +79,11 @@ BOOTMENU_ENV \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "mmcautodetect=yes\0" \ CONFIG_DFU_ENV_SETTINGS \ "findfdt=" \ @@ -111,7 +108,6 @@ #include <config_distro_bootcmd.h> #include <linux/stringify.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -126,10 +122,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - /* environment organization */ /* Environment starts at 768k = 768 * 1024 = 786432 */ /* diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index f5d2c23400da2b8d1e15d1b03ba938b5c8aae58c..36c57923dec52e9cbc26b04b26aede69b5909a58 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ @@ -74,7 +71,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -82,11 +79,11 @@ "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ CONFIG_DFU_ENV_SETTINGS \ "findfdt=" \ "if test $fdtfile = ask ; then " \ @@ -110,7 +107,6 @@ #include <config_distro_bootcmd.h> #include <linux/stringify.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -125,18 +121,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 89b3d27ffb4c4077eeb09df64374096f6725affc..d858a7edf8df7c38d294fea43100881cbcbdc239 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -25,7 +25,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -38,17 +38,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC - -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C #endif #define CONFIG_REMAKE_ELF @@ -121,9 +110,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -134,9 +120,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ @@ -163,15 +146,8 @@ #define CONFIG_MXC_GPIO -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_OF_SYSTEM_SETUP -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - #define CONFIG_SYS_BOOTM_LEN SZ_128M #endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 382d19a241b1bd0ecf5df5ad9c4fbde680a6c443..d5301071166627a05099e35c05dae3bbdff4405b 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -25,10 +25,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" - -#define CONFIG_MACH_TYPE MACH_TYPE_PM9261 - /* clocks */ /* CKGR_MOR - enable main osc. */ #define CONFIG_SYS_MOR_VAL \ @@ -128,12 +124,6 @@ AT91_WDT_MR_WDDIS | \ AT91_WDT_MR_WDD(0xfff)) -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#undef CONFIG_SKIP_LOWLEVEL_INIT - /* * Hardware drivers */ @@ -182,8 +172,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - #undef CONFIG_SYS_USE_DATAFLASH_CS0 #undef CONFIG_SYS_USE_NANDFLASH #define CONFIG_SYS_USE_FLASH 1 @@ -233,12 +221,6 @@ #error "Undefined memory device" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index e825270de8a25bb3d8a2163149fe3af054283f6b..c13f8de7c18e267bf9c0b7d1c0e8800434b288bc 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -25,10 +25,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" - -#define CONFIG_MACH_TYPE MACH_TYPE_PM9263 - /* clocks */ #define CONFIG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ @@ -140,11 +136,6 @@ AT91_WDT_MR_WDDIS | \ AT91_WDT_MR_WDD(0xfff)) -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#undef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_USER_LOWLEVEL_INIT 1 /* @@ -213,8 +204,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #define CONFIG_SYS_USE_FLASH 1 #undef CONFIG_SYS_USE_DATAFLASH #undef CONFIG_SYS_USE_NANDFLASH @@ -266,11 +255,6 @@ #error "Undefined memory device" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 452fbda0668d321cc1a003853293bdb6033b0b27..c22f698d31d7349f702e9d7ed0318d8888ea6780 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -19,11 +19,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -57,8 +52,6 @@ #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env in nandflash */ @@ -73,12 +66,6 @@ "bootz 0x72000000 - 0x71000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128 * 1024, 0x1000) - /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE 0x010000 #define CONFIG_SPL_STACK 0x310000 diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index cbe5022297e6b6ef7e4ac7f832925a8ef890e62e..f49bcfb6a2188285c2b6b0276a66e301cd7dd9f6 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -12,17 +12,11 @@ #ifndef _CONFIG_POGO_E02_H #define _CONFIG_POGO_E02_H -/* - * Machine type definition and ID - */ -#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 - /* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 9763218ecbb3011addd1611209da9b99b7b183cb..222a14bc8f8e5def95f33864c32f3c4788a1dc90 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -18,8 +18,6 @@ /* SYS */ #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SYS_INIT_SP_ADDR 0x200000 -#define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_SYS_MALLOC_LEN SZ_32M /* ATF bl33.bin load address (must match) */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 3f926212820afcbab8c5c2fbd966b8b18ec29d9d..8606eb1ee727b88a32c4d181c4085356297a3ae2 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -23,13 +23,9 @@ /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE * does not yet support DT. Thus define it here. */ -#define CONFIG_GICV2 #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - #define CONFIG_SYS_TIMER_BASE 0xf4321000 /* Use external clock source */ @@ -48,7 +44,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) #define CONFIG_LAST_STAGE_INIT /* SDRAM Bank #1 */ diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index f52ea014b5d6d760cc7340eac3815cd18b3218d6..23de326e7208dae13afdc9546a62ef4a9fb60ccf 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -10,6 +10,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_SERIAL_TAG - #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 76d6ab1c8b4e429b6ab2124f7b4df67d376d6e90..099238715711d5fe0eeff6aa1f7ca555706f5a59 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_NS16550_MEM32 @@ -20,7 +19,6 @@ #define CONFIG_IRAM_BASE 0xff020000 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0x00400000 #define CONFIG_SPL_MAX_SIZE 0x20000 #define CONFIG_SPL_BSS_START_ADDR 0x4000000 diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index 52d77e06acf46cd250b8df73f4baf1e6fac0aba0..7a78f98eb15fbb6bf713c21a1064ede8b6e17a47 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -8,13 +8,6 @@ #ifndef __CONFIG_PXA_COMMON_H__ #define __CONFIG_PXA_COMMON_H__ -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 -#endif - /* * OHCI USB */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 4673390c1a786fe41cfe8774b6faae07d844a6bf..a333326dff6c96993ccda8525fbfbc26aaecdd9c 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_PXM2_H #define __CONFIG_PXM2_H -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 - #include "siemens-am33x-common.h" #define DDR_IOCTRL_VAL 0x18b @@ -32,10 +30,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - #define CONFIG_FACTORYSET #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 273fa1a7d7b8c769446cf64bf65073b804f98899..bb4240a12848fee9ce2c0c2cef1f7a863402d669 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -14,8 +14,6 @@ /* The DTB generated by QEMU is placed at start of RAM, stay away from there */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_MALLOC_LEN SZ_16M #define CONFIG_SYS_BOOTM_LEN SZ_64M diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index b2e1204e0fadbe537159ba3c031856dd814250b1..f79e0fea4d5561feb1526cb0e84eaaaa3e9298a8 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -69,7 +69,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_LBA48 @@ -85,7 +84,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -102,9 +100,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define CONFIG_BOOTCOMMAND \ "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0" diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index bbeea96e271edc5f05929b90bf2b44670ada5a8f..ae57f681a530406962b9664bbcd7a3b1fe160f1c 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -21,10 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 61b6fb48465a5fbfca309e270a9fa9ff21bafdee..36930fa3f1a735eb5e9d1c1326f42ba1cfd14785 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -15,12 +15,9 @@ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 7f1284448cf71a4f84a8576d24f5d79613eb9888..de8ea8b850a097ede453bae089d1623e3c25072f 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -34,10 +34,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index f94e9d89799ff9438d29bb2a269ea11c13336311..595482c22e90e9eccc2f09fe0ada55108d754c9a 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,10 +10,6 @@ #include <asm/arch/rmobile.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #ifdef CONFIG_SPL #define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" #endif @@ -28,12 +24,9 @@ #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x50000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 99ef27bccd5decbcc5518c101fac592710cec4db..2b3e1bb0d1c401e0a6f345e553e2175a6567f78d 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -21,12 +21,7 @@ /* boot option */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 #define GICD_BASE 0xF1010000 #define GICC_BASE 0xF1020000 @@ -45,14 +40,11 @@ #define DRAM_RSV_SIZE 0x08000000 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x58000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* The HF/QSPI layout permits up to 1 MiB large bootloader blob */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 7f148eff87e56d376c74c51de138175a43f9478a..b133d8ec48b9ece48d435e25f3bd97420539f9aa 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 @@ -17,7 +16,6 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SPL_STACK 0x10081fff #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 7c064a0704b70393f3092b387b461e1a4d1af26e..8b7a0bbbca12953bd3cf118ec67e1ff51d4cd353 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 @@ -20,7 +19,6 @@ #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 3bcc04808a3c00d070c0ffd089201627f15d0093..e7c09645ec6b83f4df67d5d4e9ae5c19de2d07ed 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,19 +6,15 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_SYS_CBSIZE 1024 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ #endif #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 7e0c831174a33ac928c3fda117d04f9038e85639..a46b1ffe865c51b5166d1f6a30b706af8f4f2a0d 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,7 +8,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ @@ -18,7 +17,6 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x61100000 -#define CONFIG_SYS_LOAD_ADDR 0x61800800 #define CONFIG_SPL_MAX_SIZE 0x100000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index addad7a16ddf2c0aaafdc71d786acab5f9e44a8e..abbb27395e68185ae31741a97c4e20635438bf5b 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 @@ -23,7 +22,6 @@ /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #endif #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_IRAM_BASE 0xff700000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index bd9ac826f3df070e64aa664f3d2dea40fed979d6..edaf78a6e81af930c77bf789f7fab5a00143594c 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -25,7 +24,6 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 -#define CONFIG_SYS_LOAD_ADDR 0x00C00800 #define CONFIG_SPL_STACK 0x00400000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 0538da751f2385cd549b5b3a7ab858dcf48b7104..c1e26a019b57ee0c41df61693749315dcdde91c6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -14,10 +14,8 @@ #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0x00400000 #define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x2000000 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index fbbb8cf267e6586e051469d2b034d5490f63dca3..8b239ca07da85cf5bfd7961639d1c927e196eba8 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,15 +8,12 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 @@ -24,7 +21,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x400000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 6d710da901e8bf516e3d2a7598d93ce40b198d25..ed72c8bb6b110b2fbcf9ab088a9512916ba80507 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define COUNTER_FREQUENCY 24000000 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 @@ -17,7 +16,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index b6568917ea8f214b9350095cde6c780e304ceddd..afe5050e4d8084b4463dc0f74972224ea61c0629 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define COUNTER_FREQUENCY 24000000 #define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 @@ -17,7 +16,6 @@ #define CONFIG_IRAM_BASE 0xfdcc0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 -#define CONFIG_SYS_LOAD_ADDR 0x00c00800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 522b41c02db12d96100bb85cf0adc1dc86fbb6fe..55768a46da2c3476e32f066327b23d1b91bc13d3 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -13,10 +13,6 @@ #include <asm/arch/base.h> #endif -#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* Architecture, CPU, etc.*/ /* Use SoC timer for AArch32, but architected timer for AArch64 */ @@ -26,21 +22,6 @@ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) #endif -/* - * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, - * so 2708 has historically been used rather than a dedicated 2835 ID. - * - * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation - * chose to use someone else's previously registered machine ID (3139, MX51_GGC) - * rather than obtaining a valid ID:-/ - * - * For the bcm2837, hopefully a machine type is not needed, since everything - * is DT. - */ -#ifdef CONFIG_BCM2835 -#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 -#endif - /* Memory layout */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE @@ -54,8 +35,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_LOADADDR 0x00200000 #ifdef CONFIG_ARM64 #define CONFIG_SYS_BOOTM_LEN SZ_64M @@ -88,15 +67,9 @@ #define CONFIG_SYS_CBSIZE 1024 /* Environment */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* Shell */ -/* ATAGs support for bootm/bootz */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial,usbkbd\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index 66940033ab9840b58819a98565f1a47889700324..68d68d084d2ea90ea579ec46fe83e845c013504d 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_RUT_H #define __CONFIG_RUT_H -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT - #include "siemens-am33x-common.h" #define RUT_IOCTRL_VAL 0x18b @@ -23,14 +21,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ - #define CONFIG_FACTORYSET /* Watchdog */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 758e85e89df701dca3a14d0a603bab743e26c8f9..d0f70b04e750d24d0f9b0c17788193118c2f5991 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -11,7 +11,6 @@ #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ @@ -20,7 +19,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) /* rockchip ohci host driver */ #define CONFIG_USB_OHCI_NEW diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 1e2180b970d168722c660fef4aa1e7f5ab804949..21feba0569e4742e721166d89f5b79b85b4d41c3 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -60,12 +60,9 @@ */ #define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - #define BMP_LOAD_ADDR 0x78000000 /* kernel load address */ -#define CONFIG_SYS_LOAD_ADDR 0x71080000 #define INITRD_START 0x79000000 #define KERNEL_DTB_ADDR 0x7A000000 @@ -116,7 +113,6 @@ (void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART2, \ (void *)PHY_BASEADDR_UART3} -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /*----------------------------------------------------------------------- * PLL diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 6af6009e6126337aae911f7714ea54b1879539da..b4a3cc0445c3cfa57e10bd5d937e4083c5f2e30e 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -26,14 +26,6 @@ /* Text Base */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - /* MMC */ #define SDHCI_MAX_HOSTS 4 @@ -138,8 +130,6 @@ "dfu_alt_info=" CONFIG_DFU_ALT "\0" #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) /* Goni has 3 banks of DRAM, but swap the bank */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 0b679f437482f1f3df9a5066021fc64918eb0f00..ff29de0d060d119338e31e2225fff8a2f675d66c 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -31,9 +31,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ #define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT @@ -44,16 +41,6 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" -#define CONFIG_BOOTBLOCK "10" -#define CONFIG_UBIBLOCK "9" - -#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " -#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ - "${mtdparts}" - -#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" - #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ @@ -71,18 +58,20 @@ "lpj=lpj=3981312\0" \ "ubifsboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \ - CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ - CONFIG_ENV_COMMON_BOOT "; run bootk\0" \ + "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \ + "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \ + "${lcdinfo} ${console} ${meminfo}; run bootk\0" \ "tftpboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ - CONFIG_ENV_COMMON_BOOT \ + "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \ + "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \ + "${lcdinfo} ${console} ${meminfo}" \ "; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \ "nfsboot=" \ "set bootargs root=/dev/nfs rw " \ "nfsroot=${nfsroot},nolock,tcp " \ "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "${netmask}:generic:usb0:off ${console} ${meminfo}" \ "; run bootk\0" \ "ramfsboot=" \ "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ @@ -102,8 +91,8 @@ "mbrparts=" MBRPARTS_DEFAULT \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ - "bootblock=" CONFIG_BOOTBLOCK "\0" \ - "ubiblock=" CONFIG_UBIBLOCK" \0" \ + "bootblock=10\0" \ + "ubiblock=9\0" \ "ubi=enabled\0" \ "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ "mmcdev=0\0" \ diff --git a/include/configs/sagem_f@st1704.h b/include/configs/sagem_f@st1704.h index e5bb4e50d123e822865cab4db8f55164653e6fe6..d6d2014ef51ae3cfce60cbf71b4691d9ae337240 100644 --- a/include/configs/sagem_f@st1704.h +++ b/include/configs/sagem_f@st1704.h @@ -5,4 +5,3 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm6338.h> - diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 6a6f1de41d1ee23e057b45d99dc590ea93e3d500..774ecb419383b7d616920d7e7731a7a68d69732a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -14,11 +14,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ @@ -54,8 +49,6 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SD_BOOT /* bootstrap + u-boot + env + linux in sd card */ #define CONFIG_BOOTCOMMAND \ @@ -78,9 +71,4 @@ "bootz 0x22000000 - 0x21000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - #endif diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 8942d159349a0b5796468f73222992757cc9dab1..1c30e443923738a1d08a29592eb72c3c5dbba776 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -14,26 +14,20 @@ #undef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_SD_BOOT /* bootstrap + u-boot + env in sd card */ -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \ +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 " \ CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ - "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \ + "bootz 0x23000000 - 0x22000000" #endif /* SPL */ diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 8bea764582153e06e516cb7de443e53b14ca0899..09ebf488601037ee8cb230a7d4dc084ec92e116a 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -26,8 +26,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_TEXT_BASE 0x200000 #define CONFIG_SPL_MAX_SIZE 0x10000 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index 9be6d4f3381c6ffafe258efec0d21e2c4daec137..e7ccfeaef74c5f580948e3f12ba9293a8347eff1 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -27,8 +27,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND flash */ /* SPI flash */ diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index f42e26a0e07c30a2cf49ba0b223be5f8319d1947..1001bbcf930f70076eba59900525d4d6cc8c3bed 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND Flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 4f5ceca780a751404df250889800bcf538c89416..da573bc96a811ca6b5a0faf23b4d670e34942097 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -11,19 +11,13 @@ #include "at91-sama5_common.h" -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SerialFlash */ #ifdef CONFIG_SD_BOOT @@ -31,18 +25,18 @@ /* bootstrap + u-boot + env in sd card */ #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \ - "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \ + "bootz 0x23000000 - 0x22000000" #elif CONFIG_SPI_BOOT /* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */ #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \ - "ext4load mmc 0:1 0x22000000 /boot/zImage; " \ - "bootz 0x22000000 - 0x21000000" +#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; " \ + "ext4load mmc 0:1 0x23000000 /boot/zImage; " \ + "bootz 0x23000000 - 0x22000000" #endif @@ -51,9 +45,9 @@ #undef CONFIG_BOOTCOMMAND #define CONFIG_ENV_SPI_BUS 1 #define CONFIG_BOOTCOMMAND "sf probe 1:0; " \ - "sf read 0x21000000 0x180000 0x80000; " \ - "sf read 0x22000000 0x200000 0x600000; "\ - "bootz 0x22000000 - 0x21000000" + "sf read 0x22000000 0x180000 0x80000; " \ + "sf read 0x23000000 0x200000 0x600000; "\ + "bootz 0x23000000 - 0x22000000" #endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 4c25964b43a586f1c9c3768222bbe4b1483fd813..20d1d34044aa164c5fba8d8f6bd30b42f8aecd0b 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -56,8 +56,6 @@ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 44c1952b51e710001d1b004d3aaf6c5f1ee5bcc8..ac52e272174cd09ec469895ebb031a1cadb2decc 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -69,8 +69,6 @@ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 80809df638a5d8ad891a240cf1de34c8f197a75c..3032297731a097cd3fb0fd13b947b4bbacd9c705 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -22,8 +22,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 2fb4764f7ce5984f924dc30acb7740c2aae10f8f..4e8fe8693ccd25b944ef63afbc713acd6f180898 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -22,8 +22,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 96db82e9d463603e1d197028d8de349fd71dfe19..9b7cc2ce4d0c9b387f1a103b6196c89f7fb81bc4 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -24,9 +24,7 @@ GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x62000000 /* load address */ - -#undef CONFIG_BOOTCOMMAND +#ifndef CONFIG_BOOTCOMMAND #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ @@ -34,10 +32,11 @@ #define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \ "bootz 0x62000000 - 0x61000000" +#else +#define CONFIG_BOOTCOMMAND "Place your bootcommand here" #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#endif #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 8eeccdd4264fa77f0ecc93a508750e0c761fc377..24c9a84fa3584d4af354a4aea5f4aacc049f6764 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -24,11 +24,7 @@ #define CONFIG_HOST_MAX_DEVICES 4 -/* - * Size of malloc() pool, before and after relocation - */ #define CONFIG_MALLOC_F_ADDR 0x0010000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -38,8 +34,6 @@ #define CONFIG_I2C_EDID -/* Memory things - we don't really want a memory test */ -#define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_FDT_LOAD_ADDR 0x100 #define CONFIG_PHYSMEM diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 5b5aa1b2f2050101e46d535bd810d4b43c1d1b35..c51517a76bfc2496f28af5bed39f83747faad7da 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD - /* Environment in eMMC, at the end of 2nd "boot sector" */ /* NAND support */ diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h index 529fc9495ef4b938c8c5368bf233c230535a4ed9..7c88af0532d0280fe0a7b6ce8a823ecd95c158ba 100644 --- a/include/configs/sfr_nb4_ser.h +++ b/include/configs/sfr_nb4_ser.h @@ -7,4 +7,3 @@ #include <configs/bmips_bcm6358.h> #define CONFIG_REMAKE_ELF - diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index a4b4c48d4c4d45a62ddaceb5a06937a43dcbab87..6ccba95f3052b76e68f693db9c4b3fc958496955 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -18,15 +18,6 @@ #define CONFIG_DMA_COHERENT #define CONFIG_DMA_COHERENT_SIZE (1 << 20) -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) -#ifdef CONFIG_SIEMENS_MACH_TYPE -#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE -#endif - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* commands to include */ #ifndef CONFIG_SPL_BUILD @@ -53,8 +44,6 @@ * start addr of ram disk */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - /* Physical Memory Map */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ @@ -73,7 +62,6 @@ /* I2C Configuration */ -#define CONFIG_SYS_I2C_LEGACY /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ @@ -125,9 +113,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #ifndef CONFIG_SPL_BUILD /* diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index b6c29f8c6044cdc36924a320a0df24c8a5fc2319..85356789eff2869da7d1a65dd68d530136fd835d 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -28,10 +28,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index bea0eebe230685347147eedf3813bd8a76807ecc..f68d7d7676f2ea6f39c5c7ffbba50899757a7e42 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -28,18 +28,12 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 /* Environment options */ @@ -85,9 +79,5 @@ #endif /* CONFIG_SPL_BUILD */ #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 - -#define CONFIG_ID_EEPROM #endif /* __SIFIVE_UNMATCHED_H */ diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 0fbe8a59058ee209a5b3e05ffad7310bbe60efb9..1f74702ea7fc6cfc7257b499b8e3d5d785054ec9 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,11 +8,8 @@ #include <linux/sizes.h> -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* Start just below the second bank so we don't clobber it during reloc */ #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF -#define CONFIG_SYS_MALLOC_LEN SZ_128K -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE SZ_8M diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 5e8637e4948489a5010951403c5cb38ebf92063b..5bcc3a66d3a6b3da1e274e269236f1559372da9d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -40,16 +40,11 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ /* misc settings */ -#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ -#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ /* We set the max number of command args high to avoid HUSH bugs. */ #define CONFIG_SYS_MAXARGS 32 /* setting board specific options */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB #define CONFIG_SYS_AUTOLOAD "yes" #define CONFIG_RESET_TO_RETRY @@ -69,10 +64,6 @@ * till the beginning of the U-Boot position in RAM. */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000) - /* NAND flash settings */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 @@ -101,7 +92,7 @@ /* BOOTP and DHCP options */ #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv autoload yes; setenv autoboot yes; " \ "setenv bootargs ${basicargs} ${mtdparts} " \ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ @@ -129,12 +120,6 @@ #define CONFIG_BOOTCOMMAND "run flashboot" #define CONFIG_SYS_CBSIZE 512 -/* - * RAM Memory address where to put the - * Linux Kernel befor starting. - */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - /* * The NAND Flash partitions: */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 77773cdeaa5e7b5a767ac0cc9aedc459c8b61e10..a5edf04a432efcec732f5d6f3c390abc2ebf8329 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -29,16 +29,6 @@ /* Text Base */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - * 1MB = 0x100000, 0x100000 = 1024 * 1024 - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* * select serial console configuration */ @@ -105,8 +95,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index fc2f6ecf6be35a8cc9f4750e393e4df2e947bb28..4a6b6258ab7a8ec762530808630847ec7b4b31cc 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -12,14 +12,10 @@ #undef CONFIG_BOARD_COMMON #undef CONFIG_USB_GADGET_DWC2_OTG_PHY -#undef CONFIG_REVISION_TAG /* High Level Configuration Options */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ -/* Mach Type */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ @@ -28,14 +24,10 @@ #define S5P_CHECK_LPA 0xABAD0000 /* MMC SPL */ -#define CONFIG_SKIP_LOWLEVEL_INIT #define COPY_BL2_FNPTR_ADDR 0x00002488 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - /* SMDKV310 has 4 bank of DRAM */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 6f7b46e49b3fafa9436bb147397f5ead9a72ec3b..cf80801bd8418f4bf6753ef7194f00eead6a5543 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -14,9 +14,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -45,7 +42,6 @@ "run mmcboot; " \ "fi; " \ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 529976efee01d57f9b363ea4a1477edd4123f0bf..32abeb03fb4916d577482f702e2f4e912aba5699 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -20,11 +20,6 @@ /* CPU */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ @@ -73,10 +68,6 @@ #endif /* I2C - Bit-bashed */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F #define CONFIG_SOFT_I2C_READ_REPEATED_START #define I2C_INIT do { \ at91_set_gpio_output(AT91_PIN_PA23, 1); \ @@ -100,7 +91,6 @@ #define I2C_DELAY udelay(2) /* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 #define CONFIG_BOOTP_BOOTFILESIZE @@ -108,7 +98,4 @@ /* Console settings */ -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - #endif /* __CONFIG_H */ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 077e9d667a1e13aa82c71b3c69b7edccc2105d9e..b13584da51c8493bdbc81f80befae9d8960c61f4 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -19,10 +19,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 @@ -64,7 +60,6 @@ /* UARTs/Serial console */ /* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 #define CONFIG_BOOTP_BOOTFILESIZE @@ -92,7 +87,4 @@ /* Console settings */ -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - #endif /* __CONFIG_H */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 6ef96df0c0e844eefc6e0642864577ab4993ab2f..7c563b7b045c646c29cf284257c6c86e1f4926e7 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -11,16 +11,6 @@ #include <asm/arch/cpu.h> #include <asm/arch/omap.h> -/* - * CPU - */ - -#define CONFIG_ARM_ARCH_CP15_ERRATA - -/* - * Board - */ - /* * Clocks */ @@ -47,13 +37,10 @@ #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) - /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_I2C_MULTI_BUS /* @@ -111,22 +98,10 @@ "bootfile=/boot/extlinux/extlinux.conf\0" \ "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0" -/* - * ATAGs - */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - /* * Boot */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_BOOTCOMMAND \ "setenv boot_mmc_part ${kernel_mmc_part}; " \ "if test reboot-${reboot-mode} = reboot-r; then " \ diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 645e66e6b09fa53b11e453cf5f642d309c3fa7ea..ebb3e8c5732eb7830793b5f4b5daace6b608a3a8 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -8,10 +8,6 @@ #include <asm/arch/base_addr_a10.h> -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* * U-Boot general configurations */ diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index c25d6bd82be270cedfccd96f63539444aa848f12..0b37efeafa3c7b893ce60015bc21a0339a76b019 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -43,7 +43,6 @@ "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \ "saveenv && saveenv && boot;" -#define CONFIG_CMDLINE_TAG #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Environment settings */ @@ -57,9 +56,6 @@ #define CONFIG_BOOT_RETRY_TIME 45 #define CONFIG_RESET_TO_RETRY -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR - /* * FPGA Remote Update related environment * diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index af6137aeb16a01b61222729e9342814d70a92b59..ca2d7827447c1cf077d00d9518c6b3d2ff0654ef 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c5e4292f19642f616968201c4c2faf14cacee47f..ed3aac7f3acb61787432da0772c30137acdf9113 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -18,7 +18,6 @@ * Memory configurations */ #define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE @@ -186,7 +185,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 028db2a09ec14f13e6977eba25686e33a26bae63..c23ba2325b80f29be178273e9bf99408aafed197 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h index bffedcb75077627b2e5ce5743a24654f35e7b1f8..137da2f1fcf4800e37fbfc595644f05a3755a114 100644 --- a/include/configs/socfpga_dbm_soc1.h +++ b/include/configs/socfpga_dbm_soc1.h @@ -13,8 +13,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Environment is in MMC */ diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 21108e344756f649b1f87c40976af3e648cf1345..a5e6511b510df4976105280e382cc883b0066d7d 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h index d85f98fbd46cc02d6f631668a102302fd08b8858..dfc22cf6e273830126ca1391c8a4ccd386a58e16 100644 --- a/include/configs/socfpga_de10_nano.h +++ b/include/configs/socfpga_de10_nano.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index 9919d292dc7d3319957e9d1ced0b41a3ff71463d..4b58bc48c4460c32a8651f81f1f8147dc9e5d3ff 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index c4da5947f3253ac33e7bad32725fdd2192af32d0..06337d405c0478252cf3ef0dd46c419060080538 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -13,8 +13,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "zImage" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 50c59617037859db572251ea08e1e84b0907b6f7..14562143255e152cb1a5e893162a3b9202ad2e49 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -13,8 +13,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Environment is in MMC */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index a0453e562f55eb8f3adfadf497d4fcc07461fa8c..4a0235de8f5939e03c499efbaf06bb9ec34c4192 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -15,8 +15,6 @@ * U-Boot general configurations */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_LOADADDR 0x2000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_REMAKE_ELF /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ #define CPU_RELEASE_ADDR 0xFFD12210 @@ -47,7 +45,6 @@ + 0x100000) #endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) /* * U-Boot environment configurations @@ -115,11 +112,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "then source ${scriptaddr}; fi\0" \ "socfpga_legacy_reset_compat=1\0" -/* - * Generic Interrupt Controller Definitions - */ -#define CONFIG_GICV2 - /* * External memory configurations */ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 972999949a03734ab4523380cfc64b2dcbc250b0..a4aece954266c53de1aec257c35601620229e856 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 7faea150a9ef0a85967f5479454f3334d5b8f67c..f482005ce3126f0c1e1948f4cd0013de27b9ecab 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index ccaa050ae597324c0e767bbfae23111095c5be58..62c1bc7408a6c486d1b710ed4e47cd11c0e8454e 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Ethernet on SoC (EMAC) */ #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII /* The PHY is autodetected, so no MII PHY address is needed here */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 38a77535893642510ab39683674b9a1dc60b9409..d9d0a4af5ac009b07b928bf813d8992e13dd0921 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -14,8 +14,6 @@ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run selboot" #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" diff --git a/include/configs/socrates.h b/include/configs/socrates.h index da60546966cd8339550aa2def441c7254e537fba..454dbd30b612c40f41290962946d2f0c0c549e5f 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -57,9 +57,7 @@ /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 @@ -72,7 +70,6 @@ /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ /* Hardcoded values, to use instead of SPD */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f @@ -126,14 +123,13 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ /* FPGA and NAND */ #define CONFIG_SYS_FPGA_BASE 0xc0000000 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ #define CONFIG_SYS_HMI_BASE 0xc0010000 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ +#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -146,8 +142,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - /* * General PCI * Memory space is mapped 1-1. @@ -201,7 +195,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -210,11 +203,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#endif - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -254,17 +242,17 @@ "era fe000000 fe1dffff;" \ "cp.b 100000 fe000000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "update_fdt=tftp 100000 ${fdt_file};" \ + "update_fdt=tftp 100000 ${fdt_file};" \ "era fe1e0000 fe1fffff;" \ "cp.b 100000 fe1e0000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "update_initrd=tftp 100000 ${initrd_file};" \ + "update_initrd=tftp 100000 ${initrd_file};" \ "era fe200000 fe9fffff;" \ "cp.b 100000 fe200000 ${filesize};" \ "setenv filesize;saveenv\0" \ "clean_data=era fea00000 fff5ffff\0" \ - "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ - "load_usb=usb start;" \ + "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ + "load_usb=usb start;" \ "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ "boot_usb=run load_usb usbargs addcons;" \ "bootm ${kernel_addr_r} - ${fdt_addr};" \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 945d0ecc73749e9e2be295dbedacde88be4a01de..6af908afe6a7c41ba701c37f09b58a904784255b 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,9 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -71,7 +68,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index b94ef91c2ba3f57db1ebeaebbd6d963e0b8732c1..e5571b240dc15d91e18f63f4d54364b70c02d315 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -13,17 +13,37 @@ * low-level initialization and rely on configuration provided by the Samsung * bootloader. New images are loaded at the same address for compatibility. */ -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN SZ_2M /* FIXME: This should be loaded from device tree... */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0xa0412000 -/* Generate initrd atag for downstream kernel (others are copied in stemmy.c) */ -#define CONFIG_INITRD_TAG +/* Linux does not boot if FDT / initrd is loaded to end of RAM */ +#define BOOT_ENV \ + "fdt_high=0x6000000\0" \ + "initrd_high=0x6000000\0" + +#define CONSOLE_ENV \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define FASTBOOT_ENV \ + "fastboot_partition_alias_boot=Kernel\0" \ + "fastboot_partition_alias_recovery=Kernel2\0" \ + "fastboot_partition_alias_system=SYSTEM\0" \ + "fastboot_partition_alias_cache=CACHEFS\0" \ + "fastboot_partition_alias_hidden=HIDDEN\0" \ + "fastboot_partition_alias_userdata=DATAFS\0" + +#define BOOTCMD_ENV \ + "fastbootcmd=echo '*** FASTBOOT MODE ***'; fastboot usb 0\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOT_ENV \ + CONSOLE_ENV \ + FASTBOOT_ENV \ + BOOTCMD_ENV #endif diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 33b34ee0cd3b74faeda909d8c4c5dcaf297194c7..b1917c9d3f53def98e2aac57c1e0b229e45dfabd 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -13,7 +13,6 @@ #define PHYS_SDRAM_1 0x40000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ #define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ @@ -25,7 +24,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_BOOTM_LEN SZ_16M #define BOOT_TARGET_DEVICES(func) \ @@ -45,10 +43,6 @@ /* Extra Commands */ -#define CONFIG_SETUP_MEMORY_TAGS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN 0x1800000 #define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN - \ @@ -59,8 +53,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SKIP_LOWLEVEL_INIT - /* USB Configs */ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 9d029fbcc6f04f035315c7f6ea2ab7876958cb45..525a5277d86eb6de6f407ba7eaf6dbe6379608c3 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -14,8 +14,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_LOAD_ADDR 0x90400000 -#define CONFIG_LOADADDR 0x90400000 #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 @@ -27,15 +25,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (2 << 20) - #define CONFIG_BOOTCOMMAND \ "run bootcmd_romfs" diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index fefdb2dd152563702d60940277dce8fdba1228cf..609b4c2c3bebb0a11dc42dc7411909e873620f7c 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -19,8 +19,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 -#define CONFIG_LOADADDR 0x00400000 #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 @@ -29,15 +27,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index ba9f05a61b40dc0e20c340b02735d1a82d9e2bca..a8f6fbf9cff84ee9836b8fd0f4a6a3e189a353cb 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -19,8 +19,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 -#define CONFIG_LOADADDR 0x00400000 #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 @@ -29,15 +27,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 08d050adfa5178ed3d68ef0a3839caa4acc2aa6f..c76d290a57dee9cc14654bfd746f01f4a9505b07 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x08008000 -#else -#define CONFIG_SYS_LOAD_ADDR 0xC0400000 -#define CONFIG_LOADADDR 0xC0400000 -#endif - /* * Configuration of the external SDRAM memory */ @@ -36,15 +29,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index 6e10dbdfe945766f93e2418c63fe3c373883363b..c43b0d82853fb9e718ff76e22d4868c7bd0bc7ac 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -16,21 +16,9 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xD0400000 -#define CONFIG_LOADADDR 0xD0400000 - #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 268d39c7ad6a391c45f4c175e148f429bba2c1f2..d838449452a0955fcd1f6709088cb17927261986 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -16,21 +16,9 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xD0400000 -#define CONFIG_LOADADDR 0xD0400000 - #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index 3fd54611677c9e387d93b1839c440a7ff7e1b5c5..db17939a8c809a9219d823fd7bbb242eafce7b9d 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -16,21 +16,9 @@ #define CONFIG_SYS_FLASH_BASE 0x90000000 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xC1800000 -#define CONFIG_LOADADDR 0xC1800000 - #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index b372838be82f409ebe2173513223a63c4bd785ed..4ccaab5b47317c2d3d5c33559d63929b9707f0de 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -27,17 +27,6 @@ */ #define CONFIG_SYS_CBSIZE SZ_1K -/* - * default load address used for command tftp, bootm , loadb, ... - */ -#define CONFIG_LOADADDR 0xc2000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index da162cbb1140ba2dac75f3d6b6991a632bf9377c..a71de0545894ac656d70e7ae86208ecf84519a1d 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -12,7 +12,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT 0 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) @@ -73,7 +72,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) #define CONFIG_SYS_MBAR 0xFC000000 /* @@ -111,8 +109,6 @@ #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* * For booting Linux, the board info and command line data @@ -132,7 +128,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 0058dcd4bba53e73bb661a8896480a631ceca17a..d3808842bd5933cf0e539ce1919ae9cac6a3c25c 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -13,13 +13,10 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x00198000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) - /* user interface */ #define CONFIG_SYS_CBSIZE 1024 /* MISC */ -#define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 6033760583a176fcc696d86aa6f2624e25a72d2b..0e1baa91bb14e276c939d4fc49a00cacfc9671b3 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -16,6 +16,4 @@ */ #include <configs/sunxi-common.h> -#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - #endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index ee42af80d46973fe329b0e9c2ab938fccadbfdcc..ada18de75374bf9452a476498f8f042faf116acb 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -16,6 +16,4 @@ */ #include <configs/sunxi-common.h> -#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - #endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index d2fd5866723db4d8097489de8306d9a2e783715f..803a7514cc0691ff0a15b2d0f733f9907ceeb66f 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -20,6 +20,4 @@ */ #include <configs/sunxi-common.h> -#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 958b850da4a857f7da44f392481a4520da2e4439..f7d0a7ef95cc1b0a1b8f1d01924b652493a839df 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -15,22 +15,6 @@ #include <asm/arch/cpu.h> #include <linux/stringify.h> -#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT -/* - * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the - * expense of restricting some features, so the regular machine id values can - * be used. - */ -# define CONFIG_MACH_TYPE_COMPAT_REV 0 -#else -/* - * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. - * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass - * beyond the machine id check. - */ -# define CONFIG_MACH_TYPE_COMPAT_REV 1 -#endif - #ifdef CONFIG_ARM64 #define CONFIG_SYS_BOOTM_LEN (32 << 20) #endif @@ -61,7 +45,6 @@ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here * since it needs to fit in with the other values. By also #defining it * we get warnings if the Kconfig value mismatches. */ @@ -70,7 +53,6 @@ #else #define SDRAM_OFFSET(x) 0x4##x #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ /* V3s do not have enough memory to place code at 0x4a000000 */ /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here * since it needs to fit in with the other values. By also #defining it @@ -107,11 +89,6 @@ #define CONFIG_SYS_64BIT_LBA #endif -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG - #ifdef CONFIG_NAND_SUNXI #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SYS_NAND_ONFI_DETECTION @@ -137,14 +114,6 @@ #define CONFIG_SYS_MMC_MAX_DEVICE 4 #endif -#ifndef CONFIG_MACH_SUN8I_V3S -/* 64MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) -#else -/* 2MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) -#endif - /* * Miscellaneous configurable options */ @@ -194,21 +163,7 @@ /* I2C */ -#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ - defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ - defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE -#define CONFIG_SYS_I2C_MVTWSI -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#endif -#endif - -#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 +#if defined(CONFIG_VIDEO_LCD_PANEL_I2C) /* We use pin names in Kconfig and sunxi_name_to_gpio() */ #define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda #define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 4503cf3f6d0d0312c0bc6161a9b5ef6fd4f63759..13e9c64387ed30d3899ff7ff9d1677ad61c555b1 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -24,8 +24,6 @@ * Boot info */ #define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ -#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ /* * Hardware drivers support @@ -51,9 +49,6 @@ #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 41efb64752b183018ff8ff47e70a6ce3fe6d90a9..adbc2ae0c5dfa9783bf210c6b35a50b69117071b 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -20,16 +20,6 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ - 2 * 1024 * 1024) /* * DDR related */ @@ -53,12 +43,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -/* EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 /* @@ -78,10 +63,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command */ /* args */ -/* memtest works on */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ /* * AM3517 has 12 GP timers, they can be driven by the system clock @@ -249,7 +230,7 @@ struct tam3517_module_info { #define TAM3517_READ_EEPROM(info, ret) \ do { \ - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ (void *)info, sizeof(*info))) \ ret = 1; \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 6e869462f1e6e9ea5cfc94c84c7faf7c1771b919..23f1e378e62e15d4f53796bd0d94c4378b36ea96 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -33,11 +33,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -102,9 +97,6 @@ /* SPL related */ #endif -/* load address */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - /* bootstrap in spi flash , u-boot + env + linux in nandflash */ #ifndef CONFIG_SPL_BUILD @@ -157,11 +149,6 @@ "upgrade_available=0\0" #endif #endif /* #ifndef CONFIG_SPL_BUILD */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000) /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE (31 * SZ_512) diff --git a/include/configs/tb100.h b/include/configs/tb100.h index f42b0df1cf63f85e5d8c91bb77f5f7466498fdc4..6e31bd5ddb6086fd6ed7241c2fa3c920e2b8644a 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -20,9 +20,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_128K #define CONFIG_SYS_BOOTM_LEN SZ_32M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -51,7 +49,6 @@ * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* * Console configuration diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index a2e59ce6185feb4109f954e8edb98f7645e45c71..0438b5ae0c6d3dfb6911c19f50a9974ee84eb267 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -12,8 +12,6 @@ /* General configuration */ -#define CONFIG_MACH_TYPE 3980 - #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -26,8 +24,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - #define CONFIG_SYS_BOOTMAPSZ 0x10000000 /* Serial console */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 2bc531c463ef4506a56521e76dcffad03c2e002d..f8e741ab6fc11c3768fb7e2d5d63f2875aea78eb 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -22,11 +22,6 @@ #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH_SIZE (4 << 20) -/* Tag support */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index dd7a75ae4674f463c93ebb195186480ff1e84403..7cb8d64e44001c4dbc26037668ad3c8f9b44fa18 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -7,17 +7,6 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H -/* - * Size of malloc() pool - */ -#ifdef CONFIG_DFU_OVER_USB -#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ - CONFIG_SYS_DFU_DATA_BUF_SIZE + \ - CONFIG_SYS_DFU_MAX_FILE_SIZE) -#else -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#endif - #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ #ifndef CONFIG_SPL_BUILD @@ -81,8 +70,6 @@ #define BOARD_EXTRA_ENV_SETTINGS #endif -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #endif @@ -111,13 +98,6 @@ /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* remove I2C support */ -#ifdef CONFIG_SYS_I2C_TEGRA -#undef CONFIG_SYS_I2C_TEGRA -#endif - /* remove USB */ #ifdef CONFIG_USB_EHCI_TEGRA #undef CONFIG_USB_EHCI_TEGRA diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 432eceaf3513112b1960b7632a4cdd64ccf45d42..673056ce517d45ed828da9f87dbdba27f3a1f387 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ - /* Environment */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 9d751b6740433c2d3babbce185e853cd337a3593..f714c52bb53928d2e4ebedc27c2f150132d53f98 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -45,11 +45,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 0eb8f92809181df96277df40dc084e28a8f544d0..4a92954c9be8dc639257c0b7fa011da412724a3b 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -47,11 +47,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index d5f21e0907221dce60abe3abb20a9ca957dd27d4..968501602aaa42a65df37ff523a88b21c199ed48 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -17,9 +17,6 @@ * Physical Memory Map */ -/* Generic Interrupt Controller */ -#define CONFIG_GICV2 - #undef FDTFILE #define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ @@ -50,11 +47,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x80080000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index fdd89969554150ba235d2a34bd20d7f47f9ad91e..e99e65fd2f470e7de8a1bd2d6af972dacb5c9506 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -46,11 +46,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x01000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x03000000\0" \ "ramdisk_addr_r=0x03100000\0" diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 2226effe16ab2c258cae767afb203c06aca92cce..b9e04147be3048cee9545e1151713db784b0771f 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -14,9 +14,6 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Generic Interrupt Controller */ -#define CONFIG_GICV2 - /* * Memory layout for where various images get loaded by boot scripts: * @@ -41,11 +38,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x80080000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83200000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 6c5dc24b26664e6831ba27d93a42487310b5c26b..0ee13a226d948c5622267442ccfd1639504eacb2 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -42,11 +42,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 760713d3ef87ad988715db0878587cc53dc99672..64b7f2509201692f7627cfe4c129677b23251e92 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -6,6 +6,8 @@ #ifndef _CONFIG_THEADORABLE_H #define _CONFIG_THEADORABLE_H +#include <linux/sizes.h> + /* * High Level Configuration Options (easy to change) */ @@ -23,12 +25,8 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI @@ -93,6 +91,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ +#define CONFIG_SYS_SDRAM_SIZE SZ_2G #endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 15a8469feffbd9a3ee16e584cf0bb9bbd6167f9a..d45ff7d84da72b0de8edc9bce9c4049e0a442ccc 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -27,10 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 4d3c58d1e8f5d9125141e5452bcfb5d311187af2..1ce03473002b83a3ac5db7fcad00a627f15ce452 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -25,9 +25,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 @@ -42,7 +39,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) /* Physical Memory Map */ #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 67bcc0c21829eb9245dd4a375c2d784603c7db4a..ee63ce37cd99c54b040f74dc5cac7d0ae3e2d6cf 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -18,13 +18,6 @@ #include <asm/arch/omap.h> -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG /* for ramdisk support */ - /* commands to include */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -87,8 +80,6 @@ /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ - /** * Physical Memory Map */ @@ -137,9 +128,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* Ethernet */ #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 44fdc4c300257087a6e39d24d056818eeae5e7c7..cffa79416f9014e1b5912b554541a9ec0b5f1c96 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -12,8 +12,6 @@ #include <configs/ti_armv7_omap.h> #include <asm/arch/omap.h> -#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM - #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ @@ -92,9 +90,6 @@ /* Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* * Disable MMC DM for SPL build and can be re-enabled after adding diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index c57b20a06a3aef874075a6478251cef029535d29..10da1238134292803c173bfe1f17b7519331d80c 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -46,9 +46,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* * When building U-Boot such that there is no previous loader diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 4fcf741c0a0bd3fddb5c8d782c848714c784bc76..fa48cd2818ce7ee32baa230704879ce43f5bb958 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -16,19 +16,6 @@ #ifndef __CONFIG_TI_ARMV7_COMMON_H__ #define __CONFIG_TI_ARMV7_COMMON_H__ -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Our DDR memory always starts at 0x80000000 and U-Boot shall have - * relocated itself to higher in memory by the time this value is used. - * However, set this to a 32MB offset to allow for easier Linux kernel - * booting as the default is often used as the kernel load address. - */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - /* * We setup defaults based on constraints from the Linux kernel, which should * also be safe elsewhere. We have the default load at 32MB into DDR (for @@ -87,9 +74,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* If DM_I2C, enable non-DM I2C support */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* * The following are general good-enough settings for U-Boot. We set a @@ -100,7 +84,6 @@ * we are on so we do not need to rely on the command prompt. We set a * console baudrate of 115200 and use the default baud rate table. */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M /* As stated above, the following choices are optional. */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index cfc2be7b9f07ac3fed35d54df9a20319d5b06a44..a6d7b8a073989b85ec8e407cc58231d0b129a2af 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -9,10 +9,7 @@ #ifndef __CONFIG_KS2_EVM_H #define __CONFIG_KS2_EVM_H -#define CONFIG_SOC_KEYSTONE - /* U-Boot Build Configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ /* SoC Configuration */ #define CONFIG_SPL_TARGET "u-boot-spi.gph" @@ -71,37 +68,6 @@ #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 #define CONFIG_SYS_SGMII_RATESCALE 2 -/* Keyston Navigator Configuration */ -#define CONFIG_TI_KSNAV -#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS -#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE -#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE -#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE -#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE -#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE -#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE -#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE -#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE -#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE -#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE -#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE -#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM -#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM - -/* NETCP pktdma */ -#define CONFIG_KSNAV_PKTDMA_NETCP -#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE -#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE -#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM -#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE -#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM -#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE -#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE -#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM -#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE -#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE -#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE - /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE @@ -109,8 +75,6 @@ #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE - /* I2C Configuration */ #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ @@ -120,15 +84,8 @@ #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ /* EEPROM definitions */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_ENV_EEPROM_IS_ON_I2C /* NAND Configuration */ -#define CONFIG_KEYSTONE_RBL_NAND -#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET #define CONFIG_SYS_NAND_MASK_CLE 0x4000 #define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_CS 2 @@ -155,7 +112,6 @@ #define CONFIG_TIMESTAMP /* EDMA3 */ -#define CONFIG_TI_EDMA3 #define KERNEL_MTD_PARTS \ "mtdparts=" \ @@ -187,7 +143,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ - CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + ENV_KS2_BOARD_SETTINGS \ DFUARGS \ "bootdir=/boot\0" \ "tftp_root=/\0" \ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 1e6f03893b06ee377afaaa0116dcfccf012e67e8..b5ccfdcc6d46623147e2aa08613dacf4f6b83455 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -118,7 +118,6 @@ #ifdef CONFIG_SPL_BUILD /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ -#undef CONFIG_SYS_I2C_LEGACY #endif #endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index cc93f1930a1bcfb4a1cf868b2811c7d3f49e559e..bbeedaf841dfc67384e87d06be35fbf1a791682f 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -18,14 +18,10 @@ #define UART0_BASE 0x7ff80000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 7372800 /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x90000000 /* Physical Memory Map */ #define PHYS_SDRAM_1 0x80000000 @@ -34,9 +30,7 @@ #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_ARM_PL180_MMCI_BASE 0x001c050000 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 12000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index f25f6dccb5c37a378c2a4bde126d6e7dc20e8198..f9a0b7d1aaa89326407cf895f15eccdd3a36a28f 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -12,12 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0xa0000000 -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 @@ -28,8 +25,6 @@ * Serial Port */ #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} #define CONFIG_BOOTCOMMAND \ "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index b58c475c22478dae9fe5dc4c93abf60b230fe977..1efe9d57a84ee64e834a647e8e9acebdf90db9b9 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -36,17 +36,12 @@ /* I2C Configs */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C EEPROM (M24C64) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 @@ -65,9 +60,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - #if defined(CONFIG_TQMA6X_MMC_BOOT) #define TQMA6_UBOOT_OFFSET SZ_1K diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index aa98a51d961c0f94e28f27462dc43d9f69f858e3..e68e96de181e5ff554fc55ef79c177597269086a 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -30,6 +30,5 @@ #define CONFIG_SYS_BOOTCOUNT_BE /* I2C */ -#define CONFIG_SYS_I2C_LEGACY #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index a44792d857644ca6b7cc2767f3a32dedd8e04ea9..396e9f28100ed6d205d3ddd863bd65ad831731d1 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -26,11 +26,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS - #define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -40,9 +35,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_BOOTBLOCK "10" -#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" @@ -94,7 +86,7 @@ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=${nfsroot},nolock,tcp " \ "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "${netmask}:generic:usb0:off ${console} ${meminfo}" \ "; run bootk\0" \ "ramfsboot=" \ "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ @@ -112,7 +104,7 @@ "console=console=ttySAC2,115200n8\0" \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ - "bootblock=" CONFIG_BOOTBLOCK "\0" \ + "bootblock=10\0" \ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ "${fdtfile}\0" \ @@ -141,7 +133,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ - CONFIG_EXTRA_ENV_ITB \ + ENV_ITB \ "fdtaddr=40800000\0" \ /* Falcon mode definitions */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 4b1eff08f3b3054e3a159a82a027e0bd5184bd22..114dd8e56fae58c3432dbf23de48c16c5016c766 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) #define CONFIG_BOOTCOMMAND "run autoboot" @@ -125,7 +123,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ - CONFIG_EXTRA_ENV_ITB \ + ENV_ITB \ "fdtaddr=40800000\0" \ /* GPT */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b914e444b6e7cef49dc7da1566b3cd05f2d67a2e..b562d44a13ba159a13c3d268a98b7ae4b238aa37 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -18,8 +18,6 @@ #define CONFIG_TEGRA_UARTA_GPU #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE - /* SPI */ /* Environment in SPI */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 671283982356f9f4505f0fb8e3e83cd3ee248ff1..0bbc9847537c4df0186039eabaf84b9c2d459ba8 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -30,26 +30,11 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - /* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ @@ -60,7 +45,6 @@ * I2C */ #define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 /* Environment in SPI NOR flash */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 298369373ab3efd532bcb28ae97baef9ffaf4454..fe6ea68dd46191d74dc92c9473dc6156c652fe7d 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -12,12 +12,6 @@ #include "imx6_spl.h" -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 4800 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART2_BASE /* SATA Configs */ @@ -43,10 +37,10 @@ "setenv fdtfile imx6dl-udoo.dtb; fi; " \ "if test ${fdtfile} = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 813e743bb8dc16d0df7f501229a6d1830e712bb0..b06abc9286b15f404657555fadeee7d0287aadf1 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -14,9 +14,6 @@ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -45,10 +42,10 @@ "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ "if test $fdtfile = UNDEFINED; then " \ "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x84000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ @@ -70,15 +67,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 12028e53e94819212ed969181a65cc1dce44ace6..d419db1fa4bf57554ab1537463dbb2ab6c6b6443 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -39,8 +39,6 @@ #define BOOTENV #endif -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - #define CONFIG_TIMESTAMP #define CONFIG_SYS_MONITOR_BASE 0 @@ -69,7 +67,6 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_LOAD_ADDR 0x85000000 #define CONFIG_SYS_BOOTM_LEN (32 << 20) #if defined(CONFIG_ARM64) @@ -84,7 +81,7 @@ #endif #define CONFIG_ROOTPATH "/nfs/root/path" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs $bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 73bf2d19da6ffdc586cfc0452c3409b4412509d8..c12e53690d0fa3ec603f6e357347b04b3a37f744 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -20,14 +20,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT - /* * Hardware drivers */ @@ -71,16 +63,9 @@ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - /* bootstrap + u-boot + env + linux in dataflash on CS0 */ #define CONFIG_BOOTCOMMAND "nboot 21000000 0" #define CONFIG_EXTRA_ENV_SETTINGS \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 648232bad333dd8883e9d936017f906fe610c5ce..6f5a1c89e82b6d388e019098407919c3b8e4d780 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -31,19 +31,9 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ - /* Fuse */ #define CONFIG_FSL_IIM -/* U-Boot memory offsets */ -#define CONFIG_LOADADDR 0x72000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Linux boot */ #define CONFIG_HOSTNAME "usbarmory" #define CONFIG_BOOTCOMMAND \ @@ -89,6 +79,4 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 82a8fa7354ee11c5f4dd2b4e50de4f43ef9f6bd3..3b86309b13c995d7aeb621a15d864afab734986d 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,8 +10,6 @@ /* Onboard devices */ -#define CONFIG_SYS_MALLOC_LEN 0x1F0000 -#define CONFIG_SYS_LOAD_ADDR 0x00100000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 #if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL) diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 21f90f38fc9b3aa20ddaa0b2b051d0cf05ee0963..0bd5a1e8522889e3fc3654d3deec3ddccfed3633 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 7be5e5ddf11ffe768a2f6834bf8cdc72cb5bc0ad..50c808383db8038563e3f6dc3f5672e05904e10c 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -37,9 +37,6 @@ "ramdisk_addr_r=0x46400000\0" \ "scriptaddr=0x46000000\0" -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Enable Distro Boot */ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ @@ -88,8 +85,6 @@ /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ @@ -110,7 +105,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 /* ENET */ #define CONFIG_ETHPRIME "FEC" @@ -125,4 +119,3 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /*_VERDIN_IMX8MM_H */ - diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 54b5967a89dcbc7a76f53864b3d63a83c1130ac5..df22584d9abdb7dfb2ae9acfce5f7acb51d7c3d4 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -85,9 +85,6 @@ #endif #endif /* !CONFIG_GICV3 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - #ifndef CONFIG_TARGET_VEXPRESS64_JUNO /* The Vexpress64 simulators use SMSC91C111 */ #define CONFIG_SMC91111 1 @@ -105,7 +102,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h new file mode 100644 index 0000000000000000000000000000000000000000..ba3f9797a5b10dec1461dee243e53b3a585f6f88 --- /dev/null +++ b/include/configs/vexpress_ca9x4.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 Linaro + * Ryan Harkin, <ryan.harkin@linaro.org> + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + */ + +#ifndef __VEXPRESS_CA9X4_H +#define __VEXPRESS_CA9X4_H + +#define VEXPRESS_ORIGINAL_MEMORY_MAP +#include "vexpress_common.h" + +#endif /* VEXPRESS_CA9X4_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index b131480e5bc348cb7701f387ac3c62f2bdcf6473..990f5ed5470dd5ecd8b7de6f3218054d8373ac53 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -15,7 +15,7 @@ * Definitions copied from linux kernel: * arch/arm/mach-vexpress/include/mach/motherboard.h */ -#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +#ifdef VEXPRESS_ORIGINAL_MEMORY_MAP /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x40000000 #define V2M_PA_CS1 0x44000000 @@ -56,7 +56,6 @@ /* Common peripherals relative to CS7. */ #define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) -#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) #define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) #define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) @@ -109,15 +108,8 @@ /* Board info register */ #define SYS_ID V2M_SYSREGS -#define CONFIG_REVISION_TAG 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 -#define CONFIG_INITRD_TAG 1 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) @@ -131,19 +123,15 @@ #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1} -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_SERIAL0 V2M_UART0 #define CONFIG_SYS_SERIAL1 V2M_UART1 -#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) /* Physical Memory Map */ @@ -169,29 +157,10 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#define CONFIG_PLATFORM_ENV_SETTINGS \ - "loadaddr=0x80008000\0" \ - "ramdisk_addr_r=0x61000000\0" \ - "kernel_addr=0x44100000\0" \ - "ramdisk_addr=0x44800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0x88000000\0" \ - "scriptaddr=0x88000000\0" \ - "kernel_addr_r=0x80008000\0" -#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) -#define CONFIG_PLATFORM_ENV_SETTINGS \ - "loadaddr=0xa0008000\0" \ - "ramdisk_addr_r=0x81000000\0" \ - "kernel_addr=0x0c100000\0" \ - "ramdisk_addr=0x0c800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0xa8000000\0" \ - "scriptaddr=0xa8000000\0" \ - "kernel_addr_r=0xa0008000\0" -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS \ + "kernel_addr_r=0x60100000\0" \ + "fdt_addr_r=0x60000000\0" \ + "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \ BOOTENV \ "console=ttyAMA0,38400n8\0" \ "dram=1024M\0" \ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 4f11018e6d34c0e33ff4b2470987433f72720bdc..49053ce2d79eceaa04fab1654065074691bd998e 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -13,16 +13,6 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION @@ -42,15 +32,8 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_SPD_BUS_NUM 0 - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 496c228b58ea7245399493680fd6f03e6bb28b43..7397d3e8b3e723709b7b1e9ebd5fee1a6a95bbd4 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -30,8 +30,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SerialFlash */ #ifdef CONFIG_CMD_SF diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index e90eaf320387a24670ed625f973907e65836a28d..dcdaffc09b60380410f75d164a4f75d92f4080b2 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -14,9 +14,6 @@ #include "imx6_spl.h" #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ @@ -42,16 +39,7 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index dfdb8fcc0469ef8a8d348c3132557df280a2ed33..58888d4caf00722e3e1d5b1f8005f253152e400e 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -12,14 +12,9 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 @@ -41,7 +36,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index bd64893fc7799830f1a97483eab55dfd4b9ced02..ece762e512dff57761111136a10b73306447b076 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -12,11 +12,6 @@ #include "imx6_spl.h" -#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* SATA Configs */ @@ -45,7 +40,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=undefined\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -85,11 +80,11 @@ "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/warp.h b/include/configs/warp.h index e3beee0447bdecddec93304a8fe11922c8acf265..11a9b31671bca26aa985f08eebaa466c5ed67a52 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -14,9 +14,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ @@ -53,15 +50,8 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a5d52e3977fd359e8c47f84f1e8820fccf706284..0822eaf5557be9ebc601bcbee020c14e5ba4fe6d 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -13,17 +13,11 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* Switch on SERIAL_TAG */ -#define CONFIG_SERIAL_TAG - #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ @@ -107,7 +101,6 @@ "fi; " \ "fi" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -135,10 +128,6 @@ */ #define CONFIG_BOARD_SIZE_LIMIT 785408 -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - /* environment organization */ #define CONFIG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index f96178bce99b8f63d0dcb7198a5c3356137c1846..83b24a7dcc8fdcde144984658ece26f602715642 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -13,25 +13,12 @@ #include <linux/sizes.h> #include <asm/arch/cpu.h> -/* - * Define work_92105 machine type by hand -- done only for compatibility - * with original board code - */ -#define CONFIG_MACH_TYPE 736 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* * Memory configurations */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - GENERATED_GBL_DATA_SIZE) @@ -43,24 +30,6 @@ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ -/* - * I2C driver - */ - -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SPEED 350000 - -/* - * I2C EEPROM - */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * I2C RTC - */ - #define CONFIG_RTC_DS1374 /* @@ -105,12 +74,8 @@ /* * Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 /* * SPL diff --git a/include/configs/x530.h b/include/configs/x530.h index 64d68276234c28e4409a675677e2839fa4f7c6af..1e5d7381052a9ba1239eeca39dd4f624e3958765 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -61,8 +61,6 @@ /* NAND */ #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MALLOC_LEN (4 << 20) - #include <asm/arch/config.h> /* @@ -75,7 +73,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -#define CONFIG_SYS_LOAD_ADDR 0x1000000 #define CONFIG_UBI_PART user #define CONFIG_UBIFS_VOLUME user diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ab39b0bbbe8c75b5484b5f41492366bae05e8071..486b5ca77658b6159bb324a76c7bbefd34ed504f 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -44,24 +44,17 @@ "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" #endif -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#endif - /* * Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_LOAD_ADDR 0x20000000 - /*----------------------------------------------------------------------- * CPU Features */ #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x200000 /*----------------------------------------------------------------------- * Environment configuration @@ -82,7 +75,6 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_HOSTNAME "x86" #define CONFIG_BOOTFILE "bzImage" -#define CONFIG_LOADADDR 0x1000000 #define CONFIG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) #define CONFIG_OTHBOOTARGS "othbootargs=\0" @@ -109,7 +101,7 @@ "ramdiskfile=initramfs.gz\0" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ @@ -117,7 +109,7 @@ "tftpboot $ramdisk_addr_r $ramdiskfile;" \ "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ diff --git a/include/configs/xea.h b/include/configs/xea.h index 1207f75017b490e46cbb96fe08fe3f1d07eaa3d1..5081cc8691298389e7bbb4bb2a24edda6c8e6c03 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -43,8 +43,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_HOSTNAME "xea" diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index d76ce13d14e93a836593f8abc31252715d511f6f..c5e3d1678d08bcec3750e878ca8301edff675ad9 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -20,12 +20,8 @@ * This can be any arbitrary address as we are using PIE, but * please note, that CONFIG_SYS_TEXT_BASE must match the below. */ -#define CONFIG_SYS_LOAD_ADDR 0x40000000 #define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 62680ad2386c5783b5ba7c4ec4c3d70ca936bec6..43486457a45d52b0e017149461f302389c62e024 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -36,7 +36,6 @@ #define CONFIG_BOOTP_MAY_FAIL /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* Monitor Command Prompt */ /* Console I/O Buffer Size */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 42758ba75897a70eb0523ebfe9bafbef903a4b7a..e10d90cdc77bbcd24aafee0f6c00283cfdfc65f4 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -15,7 +15,6 @@ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 @@ -26,9 +25,6 @@ # define COUNTER_FREQUENCY 100000000 #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000) - /* Serial setup */ #define CONFIG_CPU_ARMV8 @@ -49,7 +45,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index ef9c768e48eb726e69f191fa06e6a294e6128785..c1064431d244709b7a1bcff37e6e0bcf5c2329d4 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -17,7 +17,6 @@ /* Undef unneeded configs */ #undef CONFIG_BOOTCOMMAND #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_MALLOC_LEN #undef CONFIG_SYS_INIT_SP_ADDR /* BOOTP options */ diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h index a7ae30d4d70d396d5728c005723cfa4342bafc5e..57c40d61020414edd1ae90b3ec9b64407719a1e1 100644 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ b/include/configs/xilinx_zynqmp_mini_emmc.h @@ -13,6 +13,5 @@ #include <configs/xilinx_zynqmp_mini.h> #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x800000 #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 692f6e5d1ae8ce4fd0314a3f3f389844fbc0d233..782e69616821af27234df61e51c1e5bef3a7a3b2 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -15,6 +15,5 @@ #define CONFIG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_SDRAM_BASE 0x0 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) -#define CONFIG_SYS_MALLOC_LEN 0x800000 #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h index 205ddb4ae097a5cf7d1dc84399811e403f93f364..3091bae051181a85cffb00de52f33d387e963ae2 100644 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ b/include/configs/xilinx_zynqmp_mini_qspi.h @@ -13,6 +13,5 @@ #include <configs/xilinx_zynqmp_mini.h> #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) -#define CONFIG_SYS_MALLOC_LEN 0x1a00 #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index c0cd72e5642a60460a9fa4b409e81075ae4274a9..6d5b81e05e161abb4fb7523cae9be187de33f229 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -17,12 +17,9 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Boot configuration */ -#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_MALLOC_LEN 0x1400000 - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ @@ -32,6 +29,4 @@ /* Extend size of kernel image for uncompression */ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) -#define CONFIG_SKIP_LOWLEVEL_INIT - #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index e4678e31dc9256816a0e67c1115d3a67843e17a1..1e2b6c09543e92f5dc5740f3b4e8d433e523644a 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -13,25 +13,13 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 516a6089f6d8d668e499b279b56268acd3b41ce8..ccc90a66f7d1b7e47b19de6bbb62b32809470883 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -65,8 +65,6 @@ # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ #endif -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ - /* Linux boot param area in RAM (used only when booting linux) */ #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) @@ -98,9 +96,6 @@ #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) -/* Used by tftpboot; env var 'loadaddr' */ -#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) - /*==============================*/ /* U-Boot general configuration */ /*==============================*/ @@ -175,7 +170,6 @@ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /*======================*/ /* Ethernet Driver Info */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h deleted file mode 100644 index 8b571da021a71fcdf34f4f0e2ba21bcada22bc3e..0000000000000000000000000000000000000000 --- a/include/configs/zmx25.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2011 Graf-Syteco, Matthias Weisser - * <weisserm@arcor.de> - * - * Configuation settings for the zmx25 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -#define CONFIG_SYS_TIMER_RATE 32768 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "gs_fast_boot=setenv bootdelay 5\0" \ - "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ - "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ - "bootm 0x81000000; bootelf 0x81000000\0" - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Hardware drivers - */ - -/* - * Serial - */ -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x00 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MXC -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC PORT_PTS_SERIAL -#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* SDRAM */ -#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xA0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -/* - * CFI FLASH driver setup - */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) - -#endif /* __CONFIG_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 7859b77603f113a08be7286a78e02b10402b1be7..9b4c54b5e6a0f8ce112784b116a351c6fdfd411a 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -65,7 +65,6 @@ /* enable preboot to be loaded before CONFIG_BOOTDELAY */ /* Boot configuration */ -#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ #ifdef CONFIG_SPL_BUILD #define BOOTENV diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 0491cf51361c9763248c3c6819913f4ca2a769c6..7eafdfd9a6536251dbab7b6c8480180c1d7a3879 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_ZYNQ_CSE_H #define __CONFIG_ZYNQ_CSE_H -#define CONFIG_SKIP_LOWLEVEL_INIT - #include <configs/zynq-common.h> /* Undef unneeded configs */ diff --git a/include/div64.h b/include/div64.h index 8b92d2b18347ec7ccb76fda0a38256513823b084..66a2af4df057a397394cedc30b3fb07aaf27a567 100644 --- a/include/div64.h +++ b/include/div64.h @@ -220,7 +220,7 @@ extern u32 __div64_32(u64 *dividend, u32 divisor); } else if (likely(((n) >> 32) == 0)) { \ __rem = (u32)(n) % __base; \ (n) = (u32)(n) / __base; \ - } else \ + } else \ __rem = __div64_32(&(n), __base); \ __rem; \ }) diff --git a/include/dm/device.h b/include/dm/device.h index 9d0ca6a550e5a46b8396e9670244ed1672959665..3028d002ab0dbda9eb25c23efe9ebb0acc256ca4 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -181,7 +181,7 @@ struct udevice { u32 flags_; #endif int seq_; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) ofnode node_; #endif #ifdef CONFIG_DEVRES @@ -243,7 +243,7 @@ static inline void dev_bic_flags(struct udevice *dev, u32 bic) */ static inline ofnode dev_ofnode(const struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) return dev->node_; #else return ofnode_null(); @@ -263,7 +263,7 @@ static inline ofnode dev_ofnode(const struct udevice *dev) static inline int dev_of_offset(const struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) return ofnode_to_offset(dev_ofnode(dev)); #else return -1; @@ -272,7 +272,7 @@ static inline int dev_of_offset(const struct udevice *dev) static inline bool dev_has_ofnode(const struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) return ofnode_valid(dev_ofnode(dev)); #else return false; @@ -281,7 +281,7 @@ static inline bool dev_has_ofnode(const struct udevice *dev) static inline void dev_set_ofnode(struct udevice *dev, ofnode node) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) dev->node_ = node; #endif } @@ -301,7 +301,7 @@ struct udevice_id { ulong data; }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) #define of_match_ptr(_ptr) (_ptr) #else #define of_match_ptr(_ptr) NULL @@ -739,7 +739,7 @@ int device_find_next_child(struct udevice **devp); * * @parent: Parent device to search * @uclass_id: Uclass to look for - * @devp: Returns device found, if any + * @devp: Returns device found, if any, else NULL * @return 0 if found, else -ENODEV */ int device_find_first_inactive_child(const struct udevice *parent, @@ -751,7 +751,7 @@ int device_find_first_inactive_child(const struct udevice *parent, * * @parent: Parent device to search * @uclass_id: Uclass to look for - * @devp: Returns first child device in that uclass, if any + * @devp: Returns first child device in that uclass, if any, else NULL * @return 0 if found, else -ENODEV */ int device_find_first_child_by_uclass(const struct udevice *parent, diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 4e1a8447e65ec07c41c00a35817dc2593f056289..6a714d0c7b503af20dbb0391fd901c917697856e 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1117,4 +1117,41 @@ int ofnode_write_string(ofnode node, const char *propname, const char *value); */ int ofnode_set_enabled(ofnode node, bool value); +/** + * ofnode_conf_read_bool() - Read a boolean value from the U-Boot config + * + * This reads a property from the /config node of the devicetree. + * + * See doc/config.txt for bindings + * + * @prop_name property name to look up + * @return true, if it exists, false if not + */ +bool ofnode_conf_read_bool(const char *prop_name); + +/** + * ofnode_conf_read_int() - Read an integer value from the U-Boot config + * + * This reads a property from the /config node of the devicetree. + * + * See doc/config.txt for bindings + * + * @prop_name: property name to look up + * @default_val: default value to return if the property is not found + * @return integer value, if found, or @default_val if not + */ +int ofnode_conf_read_int(const char *prop_name, int default_val); + +/** + * ofnode_conf_read_str() - Read a string value from the U-Boot config + * + * This reads a property from the /config node of the devicetree. + * + * See doc/config.txt for bindings + * + * @prop_name: property name to look up + * @return string value, if found, or NULL if not + */ +const char *ofnode_conf_read_str(const char *prop_name); + #endif diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h index da514bad0d3c942bb22f95464d4c26430ed9c8db..0d534b1d6654b2fbee7b3ab85ffc8edd2490a260 100644 --- a/include/dm/platform_data/spi_coldfire.h +++ b/include/dm/platform_data/spi_coldfire.h @@ -26,4 +26,3 @@ struct coldfire_spi_plat { }; #endif /* __spi_coldfire_h */ - diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index e7edd409f307fac7b87a0d6a205410dd4ffd9695..3768432b680b020eb40c679106dade99933ffdb6 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -54,6 +54,7 @@ enum uclass_id { UCLASS_FIRMWARE, /* Firmware */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_HASH, /* Hash device */ UCLASS_HWSPINLOCK, /* Hardware semaphores */ UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ diff --git a/include/dm/uclass.h b/include/dm/uclass.h index da0c1bfadb1efb02641d9febd7ad2c9e1f64cf55..15e5f9ef5bcd9a60a9f1e62d848d68bad599f78a 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -354,7 +354,7 @@ int uclass_next_device(struct udevice **devp); * The device returned is probed if necessary, and ready for use * * @devp: On entry, pointer to device to lookup. On exit, returns pointer - * to the next device in the uclass if no error occurred, or -ENODEV if + * to the next device in the uclass if no error occurred, or NULL if * there is no next device. * @return 0 if found, -ENODEV if not found, other -ve on error */ diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 22b8d08b6002c28809a4b5a733747349b5166d3f..76fcaff0e42e373d0517f9d360bfdb3263d356c0 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -268,4 +268,3 @@ #define CLK_SGMII_CDR_FB 3 #endif /* _DT_BINDINGS_CLK_MT7622_H */ - diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 8353a7874050bfa4d9840f4f5ee7ff45efc8f489..8a4924123881fd2b22ff5419078bc7e22e63bcf2 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -51,4 +51,3 @@ #define UTMI_PHY_INVALID 0xff #endif /* _COMPHY_DATA_H_ */ - diff --git a/include/dt-bindings/mfd/atmel-flexcom.h b/include/dt-bindings/mfd/atmel-flexcom.h new file mode 100644 index 0000000000000000000000000000000000000000..4e2fc32363946b6d261862f3c858d8916a5bd53c --- /dev/null +++ b/include/dt-bindings/mfd/atmel-flexcom.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides macros for Atmel Flexcom DT bindings. + * + * Copyright (C) 2015 Cyrille Pitchen <cyrille.pitchen@atmel.com> + */ + +#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ +#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ + +#define ATMEL_FLEXCOM_MODE_USART 1 +#define ATMEL_FLEXCOM_MODE_SPI 2 +#define ATMEL_FLEXCOM_MODE_TWI 3 + +#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h index 0404bcc47dd4f4688d94a0236e3b99544e6ad9d3..7266ae67b03a28c4f5a44d3080cebb1b078fac69 100644 --- a/include/dt-bindings/mfd/dbx500-prcmu.h +++ b/include/dt-bindings/mfd/dbx500-prcmu.h @@ -12,64 +12,64 @@ */ #define ARMCLK 0 #define PRCMU_ACLK 1 -#define PRCMU_SVAMMCSPCLK 2 -#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ -#define PRCMU_SIACLK 3 -#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ -#define PRCMU_SGACLK 4 -#define PRCMU_UARTCLK 5 -#define PRCMU_MSP02CLK 6 -#define PRCMU_MSP1CLK 7 -#define PRCMU_I2CCLK 8 -#define PRCMU_SDMMCCLK 9 -#define PRCMU_SLIMCLK 10 -#define PRCMU_CAMCLK 10 /* DBx540 only. */ -#define PRCMU_PER1CLK 11 -#define PRCMU_PER2CLK 12 -#define PRCMU_PER3CLK 13 -#define PRCMU_PER5CLK 14 -#define PRCMU_PER6CLK 15 -#define PRCMU_PER7CLK 16 -#define PRCMU_LCDCLK 17 -#define PRCMU_BMLCLK 18 -#define PRCMU_HSITXCLK 19 -#define PRCMU_HSIRXCLK 20 +#define PRCMU_SVAMMCSPCLK 2 +#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ +#define PRCMU_SIACLK 3 +#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ +#define PRCMU_SGACLK 4 +#define PRCMU_UARTCLK 5 +#define PRCMU_MSP02CLK 6 +#define PRCMU_MSP1CLK 7 +#define PRCMU_I2CCLK 8 +#define PRCMU_SDMMCCLK 9 +#define PRCMU_SLIMCLK 10 +#define PRCMU_CAMCLK 10 /* DBx540 only. */ +#define PRCMU_PER1CLK 11 +#define PRCMU_PER2CLK 12 +#define PRCMU_PER3CLK 13 +#define PRCMU_PER5CLK 14 +#define PRCMU_PER6CLK 15 +#define PRCMU_PER7CLK 16 +#define PRCMU_LCDCLK 17 +#define PRCMU_BMLCLK 18 +#define PRCMU_HSITXCLK 19 +#define PRCMU_HSIRXCLK 20 #define PRCMU_HDMICLK 21 -#define PRCMU_APEATCLK 22 -#define PRCMU_APETRACECLK 23 -#define PRCMU_MCDECLK 24 -#define PRCMU_IPI2CCLK 25 -#define PRCMU_DSIALTCLK 26 -#define PRCMU_DMACLK 27 -#define PRCMU_B2R2CLK 28 -#define PRCMU_TVCLK 29 -#define SPARE_UNIPROCLK 30 -#define PRCMU_SSPCLK 31 -#define PRCMU_RNGCLK 32 -#define PRCMU_UICCCLK 33 +#define PRCMU_APEATCLK 22 +#define PRCMU_APETRACECLK 23 +#define PRCMU_MCDECLK 24 +#define PRCMU_IPI2CCLK 25 +#define PRCMU_DSIALTCLK 26 +#define PRCMU_DMACLK 27 +#define PRCMU_B2R2CLK 28 +#define PRCMU_TVCLK 29 +#define SPARE_UNIPROCLK 30 +#define PRCMU_SSPCLK 31 +#define PRCMU_RNGCLK 32 +#define PRCMU_UICCCLK 33 #define PRCMU_G1CLK 34 /* DBx540 only. */ #define PRCMU_HVACLK 35 /* DBx540 only. */ -#define PRCMU_SPARE1CLK 36 -#define PRCMU_SPARE2CLK 37 +#define PRCMU_SPARE1CLK 36 +#define PRCMU_SPARE2CLK 37 -#define PRCMU_NUM_REG_CLOCKS 38 +#define PRCMU_NUM_REG_CLOCKS 38 -#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS -#define PRCMU_SYSCLK 39 -#define PRCMU_CDCLK 40 -#define PRCMU_TIMCLK 41 -#define PRCMU_PLLSOC0 42 -#define PRCMU_PLLSOC1 43 -#define PRCMU_ARMSS 44 -#define PRCMU_PLLDDR 45 +#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS +#define PRCMU_SYSCLK 39 +#define PRCMU_CDCLK 40 +#define PRCMU_TIMCLK 41 +#define PRCMU_PLLSOC0 42 +#define PRCMU_PLLSOC1 43 +#define PRCMU_ARMSS 44 +#define PRCMU_PLLDDR 45 /* DSI Clocks */ -#define PRCMU_PLLDSI 46 -#define PRCMU_DSI0CLK 47 -#define PRCMU_DSI1CLK 48 -#define PRCMU_DSI0ESCCLK 49 -#define PRCMU_DSI1ESCCLK 50 -#define PRCMU_DSI2ESCCLK 51 +#define PRCMU_PLLDSI 46 +#define PRCMU_DSI0CLK 47 +#define PRCMU_DSI1CLK 48 +#define PRCMU_DSI0ESCCLK 49 +#define PRCMU_DSI1ESCCLK 50 +#define PRCMU_DSI2ESCCLK 51 /* LCD DSI PLL - Ux540 only */ #define PRCMU_PLLDSI_LCD 52 @@ -79,6 +79,6 @@ #define PRCMU_DSI1ESCCLK_LCD 56 #define PRCMU_DSI2ESCCLK_LCD 57 -#define PRCMU_NUM_CLKS 58 +#define PRCMU_NUM_CLKS 58 #endif diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index cde5aa7e27d0c39e0f6e5f485d012548f5e75035..6fc4b445d3a1435d5b6cb9fc2286e8b72228f14e 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -1,7 +1,10 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* - * TI DP83867 PHY drivers + * Device Tree constants for the Texas Instruments DP83867 PHY * + * Author: Dan Murphy <dmurphy@ti.com> + * + * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H @@ -14,22 +17,22 @@ #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ -#define DP83867_RGMIIDCTL_250_PS 0x0 -#define DP83867_RGMIIDCTL_500_PS 0x1 -#define DP83867_RGMIIDCTL_750_PS 0x2 -#define DP83867_RGMIIDCTL_1_NS 0x3 -#define DP83867_RGMIIDCTL_1_25_NS 0x4 -#define DP83867_RGMIIDCTL_1_50_NS 0x5 -#define DP83867_RGMIIDCTL_1_75_NS 0x6 -#define DP83867_RGMIIDCTL_2_00_NS 0x7 -#define DP83867_RGMIIDCTL_2_25_NS 0x8 -#define DP83867_RGMIIDCTL_2_50_NS 0x9 -#define DP83867_RGMIIDCTL_2_75_NS 0xa -#define DP83867_RGMIIDCTL_3_00_NS 0xb -#define DP83867_RGMIIDCTL_3_25_NS 0xc -#define DP83867_RGMIIDCTL_3_50_NS 0xd -#define DP83867_RGMIIDCTL_3_75_NS 0xe -#define DP83867_RGMIIDCTL_4_00_NS 0xf +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index 18ec5df5a5812a9f037247b6c95de1d15fba2546..b543eebd2f0af39cddbd27ff9ca7a4c5936d290a 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -77,4 +77,3 @@ #define A_DELAY_PS(val) ((val) & 0xffff) #define G_DELAY_PS(val) ((val) & 0xffff) #endif - diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e6cb1d0540e60f06954c2a7225d9630a8daac20f..e085f102b2839a0c7b45678b1f10bead1ba21a26 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -1,36 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This header provides constants for TI K3-AM65 pinctrl bindings. + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. * - * Copyright (C) 2018-2021 Texas Instruments + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H -#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_200MHZ 0 -#define SLEWCTRL_150MHZ (1 << 19) -#define SLEWCTRL_100MHZ (2 << 19) -#define SLEWCTRL_50MHZ (3 << 19) -#define TX_DIS (1 << 21) -#define ISO_OVR (1 << 22) -#define ISO_BYPASS (1 << 23) -#define DS_EN (1 << 24) -#define DS_INPUT (1 << 25) -#define DS_FORCE_OUT_HIGH (1 << 26) -#define DS_PULL_UP_DOWN_EN 0 -#define DS_PULL_UP_DOWN_DIS (1 << 27) -#define DS_PULL_UP_SEL (1 << 28) -#define WAKEUP_ENABLE (1 << 29) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H +#define _DT_BINDINGS_PINCTRL_TI_K3_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) #define PIN_INPUT (INPUT_EN | PULL_DISABLE) #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index f48245ff87e5f189611e4c72bbce9ad84b704e12..4c060ee0e0ad13b411cffc6d38ae392dd0cf1de6 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -89,4 +89,3 @@ #define OMAP4_UART4_RX 0x11c #endif - diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4d395184a33b900a43c2566cc6cc76..e6e0780789427b93142f479e8ebdb9a1c0824772 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -39,4 +39,3 @@ #define STM32MP_PKG_AD 0x8 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ - diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h index bc7babb1a67cd4910f3bc9c54eefff2a574591b7..7871e5f52b1cf47f836d0b1557843dda975e9650 100644 --- a/include/dt-bindings/thermal/thermal.h +++ b/include/dt-bindings/thermal/thermal.h @@ -13,4 +13,3 @@ #define THERMAL_NO_LIMIT (~0) #endif - diff --git a/include/dt-structs.h b/include/dt-structs.h index f9ccaf56a465316f7c656ca146c53d8146b091ef..fa1622cb1dc12ef87ee20818e38e90295f7b9892 100644 --- a/include/dt-structs.h +++ b/include/dt-structs.h @@ -10,16 +10,43 @@ #if CONFIG_IS_ENABLED(OF_PLATDATA) struct driver_info; +/** + * struct phandle_0_arg - hold a phandle record with no arguments + * + * This holds a phandle pointing to another device. See 'Indexes' in the + * of-plat-rst documentation. + * + * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST) + * @arg: arguments + */ struct phandle_0_arg { uint idx; int arg[0]; }; +/** + * struct phandle_2_arg - hold a phandle record with up to one argument + * + * This holds a phandle pointing to another device. See 'Indexes' in the + * of-plat-rst documentation. + * + * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST) + * @arg: arguments + */ struct phandle_1_arg { uint idx; int arg[1]; }; +/** + * struct phandle_2_arg - hold a phandle record with up to two arguments + * + * This holds a phandle pointing to another device. See 'Indexes' in the + * of-plat-rst documentation. + * + * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST) + * @arg: arguments + */ struct phandle_2_arg { uint idx; int arg[2]; diff --git a/include/eeprom.h b/include/eeprom.h index 6820844cea3ae2bdfbdba0e72f29bb168741235c..f9c6542ba762b51c7b6f592d72715bfa837f1a82 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -21,8 +21,4 @@ int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); #define eeprom_write(dev_addr, offset, buffer, cnt) (-ENOSYS) #endif -#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) -# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR -#endif - #endif diff --git a/include/env_default.h b/include/env_default.h index 1ddd64ba8ffe20fed953586ea10cf18ce9e9715b..66e203eb6e4e3c7b63024f345566dff894fedb74 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -82,8 +82,8 @@ const uchar default_environment[] = { #ifdef CONFIG_BOOTFILE "bootfile=" CONFIG_BOOTFILE "\0" #endif -#ifdef CONFIG_LOADADDR - "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" +#ifdef CONFIG_SYS_LOAD_ADDR + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0" #endif #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" diff --git a/include/environment/distro/sf.h b/include/environment/distro/sf.h index e793be06c6ff99dd26f9709b1f586bbcc9ee083b..62624d553c04ee287ac51666c0d0047f3f27a3dd 100644 --- a/include/environment/distro/sf.h +++ b/include/environment/distro/sf.h @@ -10,16 +10,16 @@ #if CONFIG_IS_ENABLED(CMD_SF) #define BOOTENV_SHARED_SF(devtypel) \ - #devtypel "_boot=" \ + #devtypel "_boot=" \ "if " #devtypel " probe ${busnum}; then " \ - "devtype=" #devtypel "; " \ - "run scan_sf_for_scripts; " \ + "devtype=" #devtypel "; " \ + "run scan_sf_for_scripts; " \ "fi\0" -#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "busnum=" #instance "; " \ +#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "busnum=" #instance "; " \ "run " #devtypel "_boot\0" -#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \ +#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \ #devtypel #instance " " #else #define BOOTENV_SHARED_SF(devtypel) diff --git a/include/environment/ti/nand.h b/include/environment/ti/nand.h index f2482e8c35ef26030876ee1c7f097837a2eac9b6..11dcefcc41caddd65596b806dcb7e8fb265fcda5 100644 --- a/include/environment/ti/nand.h +++ b/include/environment/ti/nand.h @@ -23,4 +23,3 @@ #else #define NANDARGS "" #endif - diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h index 8fc81f902db92e8e493a182e11a1ab997f9173fa..ccb7805375e96157f262164e18196cc4d30f38f2 100644 --- a/include/faraday/ftpmu010.h +++ b/include/faraday/ftpmu010.h @@ -137,7 +137,7 @@ struct ftpmu010 { * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: * Datasheet indicated it starts at bit #21 which was wrong. * 2. FTPMU010_PDLLCR0_DLLFRAG: - * Datasheet indicated it has 2 bit which was wrong. + * Datasheet indicated it has 2 bit which was wrong. */ #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) diff --git a/include/fdt_support.h b/include/fdt_support.h index f6f46bb8e9ce3fca01097c312a8997d81cda489e..72a5b90c97ca0d42a490144d578fced2b8771623 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -203,8 +203,6 @@ char *board_fdt_chosen_bootargs(void); * called at the end of the image_setup_libfdt() is to do that convertion. */ void ft_board_setup_ex(void *blob, struct bd_info *bd); -void ft_cpu_setup(void *blob, struct bd_info *bd); -void ft_pci_setup(void *blob, struct bd_info *bd); /** * Add system-specific data to the FDT before booting the OS. diff --git a/include/fdtdec.h b/include/fdtdec.h index 8ac20c9a64f754c58c252fac12862ce17976c5b5..23efbe710cb52f47756008e74a3e546d19481a13 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -746,39 +746,6 @@ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); */ int fdtdec_get_child_count(const void *blob, int node); -/** - * Look in the FDT for a config item with the given name and return its value - * as a 32-bit integer. The property must have at least 4 bytes of data. The - * value of the first cell is returned. - * - * @param blob FDT blob to use - * @param prop_name Node property name - * @param default_val default value to return if the property is not found - * @return integer value, if found, or default_val if not - */ -int fdtdec_get_config_int(const void *blob, const char *prop_name, - int default_val); - -/** - * Look in the FDT for a config item with the given name - * and return whether it exists. - * - * @param blob FDT blob - * @param prop_name property name to look up - * @return 1, if it exists, or 0 if not - */ -int fdtdec_get_config_bool(const void *blob, const char *prop_name); - -/** - * Look in the FDT for a config item with the given name and return its value - * as a string. - * - * @param blob FDT blob - * @param prop_name property name to look up - * @returns property string, NULL on error. - */ -char *fdtdec_get_config_string(const void *blob, const char *prop_name); - /* * Look up a property in a node and return its contents in a byte * array of given length. The property must have at least enough data for diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index 96d81d9934917254e021b33bc58d888fb1d03ee3..e5e7338192f64c0a9cddb0877ded3cb3dc0fb184 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -173,8 +173,6 @@ do { \ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ } while (0) - - /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ do { \ diff --git a/include/fsl_qe.h b/include/fsl_qe.h index cd8fca95b4a0649209978591cf9c32d53e6bc230..48accb8d8918c72e90581af0ce91f15d38ee8660 100644 --- a/include/fsl_qe.h +++ b/include/fsl_qe.h @@ -40,7 +40,7 @@ typedef struct qe_snum { #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ -#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ QE_RISC_ALLOCATION_RISC2) #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ QE_RISC_ALLOCATION_RISC2 | \ diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h index 655f22ed9ac6771af3e93e76bfa41822e0c4f916..29f00d3b9f8aedaaf9b03b904c4af1811093ff99 100644 --- a/include/fsl_wdog.h +++ b/include/fsl_wdog.h @@ -14,6 +14,6 @@ struct watchdog_regs { #define WCR_WDE 0x04 #define WCR_WDT 0x08 #define WCR_SRS 0x10 -#define WCR_WDA 0x20 +#define WCR_WDA 0x20 #define SET_WCR_WT(x) (x << 8) #define WCR_WT_MSK SET_WCR_WT(0xFF) diff --git a/include/generic-phy.h b/include/generic-phy.h index a17d900e4bd21f81401149ea9f4bb8110c7c62a0..9a11659640cc806cb9d032d88485270af3cfc3b0 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -201,7 +201,7 @@ int generic_phy_power_off(struct phy *phy); * generic_phy_configure() - configure a PHY device * * @phy: PHY port to be configured - * @params: PHY Parameters, underlying data is specific to the PHY function + * @params: PHY Parameters, underlying data is specific to the PHY function * @return 0 if OK, or a negative error code */ int generic_phy_configure(struct phy *phy, void *params); diff --git a/include/i2c.h b/include/i2c.h index 3d9ecaba0b6e293e6a145c1b0232ed88a188a47a..a35e99bf87e8d0cfb8698b3361aebce1d9c30df8 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -610,6 +610,10 @@ extern struct acpi_ops i2c_acpi_ops; */ int acpi_i2c_of_to_plat(struct udevice *dev); +#ifdef CONFIG_SYS_I2C_EARLY_INIT +void i2c_early_init_f(void); +#endif + #if !CONFIG_IS_ENABLED(DM_I2C) /* @@ -742,27 +746,14 @@ extern struct i2c_bus_hose i2c_bus[]; # endif #endif -/* - * Many boards/controllers/drivers don't support an I2C slave interface so - * provide a default slave address for them for use in common code. A real - * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does - * support a slave interface. - */ -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - /* * Initialization, must be called once on start up, may be called * repeatedly to change the speed and slave addresses. */ -#ifdef CONFIG_SYS_I2C_EARLY_INIT -void i2c_early_init_f(void); -#endif void i2c_init(int speed, int slaveaddr); void i2c_init_board(void); -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) /* * i2c_get_bus_num: * @@ -942,7 +933,7 @@ unsigned int i2c_get_bus_speed(void); * only for backwardcompatibility, should go away if we switched * completely to new multibus support. */ -#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) # if !defined(CONFIG_SYS_MAX_I2C_BUS) # define CONFIG_SYS_MAX_I2C_BUS 2 # endif diff --git a/include/i8042.h b/include/i8042.h index 8d69fa13bc2a8ee150058644e528e3ee904c80af..687632058c951450e70c3fe1eaec06a60c05df96 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -20,12 +20,12 @@ #define STATUS_IBF (1 << 1) /* Configuration byte bit defines */ -#define CONFIG_KIRQ_EN (1 << 0) -#define CONFIG_MIRQ_EN (1 << 1) -#define CONFIG_SET_BIST (1 << 2) -#define CONFIG_KCLK_DIS (1 << 4) -#define CONFIG_MCLK_DIS (1 << 5) -#define CONFIG_AT_TRANS (1 << 6) +#define CFG_KIRQ_EN (1 << 0) +#define CFG_MIRQ_EN (1 << 1) +#define CFG_SET_BIST (1 << 2) +#define CFG_KCLK_DIS (1 << 4) +#define CFG_MCLK_DIS (1 << 5) +#define CFG_AT_TRANS (1 << 6) /* i8042 commands */ #define CMD_RD_CONFIG 0x20 /* read configuration byte */ diff --git a/include/imximage.h b/include/imximage.h index 1ed3284f15404741d9598d364a83e67dfe41707a..5a812f5a10c2ba7debf5a73061ae8d4bc4ddc6d6 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -124,7 +124,7 @@ typedef struct { } flash_header_v1_t; typedef struct { - uint32_t length; /* Length of data to be read from flash */ + uint32_t length; /* Length of data to be read from flash */ } flash_cfg_parms_t; typedef struct { diff --git a/include/irq.h b/include/irq.h index 8527e4dd797bfcf5555b29e90f8e7c41c72d7ebf..a0965e442092ea97977efb96ff4b1071e4a622c7 100644 --- a/include/irq.h +++ b/include/irq.h @@ -200,6 +200,35 @@ int irq_restore_polarities(struct udevice *dev); */ int irq_read_and_clear(struct irq *irq); +struct phandle_2_arg; +/** + * irq_get_by_phandle() - Get an irq by its phandle information (of-platadata) + * + * This function is used when of-platdata is enabled. + * + * This looks up an irq using the phandle info. With dtoc, each phandle in the + * 'interrupts-extended ' property is transformed into an idx representing the + * device. For example: + * + * interrupts-extended = <&acpi_gpe 0x3c 0>; + * + * might result in: + * + * .interrupts_extended = {6, {0x3c, 0}},}, + * + * indicating that the irq is udevice idx 6 in dt-plat.c with a arguments of + * 0x3c and 0.This function can return a valid irq given the above + * information. In this example it would return an irq containing the + * 'acpi_gpe' device and the irq ID 0x3c. + * + * @dev: Device containing the phandle + * @cells: Phandle info + * @irq: A pointer to a irq struct to initialise + * @return 0 if OK, or a negative error code + */ +int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells, + struct irq *irq); + /** * irq_get_by_index - Get/request an irq by integer index. * diff --git a/include/linux/apm_bios.h b/include/linux/apm_bios.h index 3dabc3f7704819f6db695ab7360cbc805c79a4cb..32d14017701a8280d16af572658093b38a2b07fd 100644 --- a/include/linux/apm_bios.h +++ b/include/linux/apm_bios.h @@ -34,7 +34,7 @@ struct apm_bios_info { #define APM_16_BIT_SUPPORT 0x0001 #define APM_32_BIT_SUPPORT 0x0002 #define APM_IDLE_SLOWS_CLOCK 0x0004 -#define APM_BIOS_DISABLED 0x0008 +#define APM_BIOS_DISABLED 0x0008 #define APM_BIOS_DISENGAGED 0x0010 /* diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 98dd3fc4cc2863463b1b604738b407123fac3a2d..09cea0e95e23d474eece8a98ef79b808caa93eb0 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -203,7 +203,7 @@ void __read_once_size(const volatile void *p, void *res, int size) /* * We can't declare function 'inline' because __no_sanitize_address confilcts * with inlining. Attempt to inline it may cause a build failure. - * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 * '__maybe_unused' allows us to avoid defined-but-not-used warnings. */ # define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 7129504e053d29c722706990059c77596f3e7c2d..85288c3729af253a589e7909a30095e042ab9b9b 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -63,7 +63,7 @@ struct resource_list { #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) #define IORESOURCE_IRQ_LOWLEVEL (1<<3) #define IORESOURCE_IRQ_SHAREABLE (1<<4) -#define IORESOURCE_IRQ_OPTIONAL (1<<5) +#define IORESOURCE_IRQ_OPTIONAL (1<<5) /* PnP DMA specific bits (IORESOURCE_BITS) */ #define IORESOURCE_DMA_TYPE_MASK (3<<0) diff --git a/include/linux/list.h b/include/linux/list.h index f62afa092c630bbd79e7f585a441dc6618a5c9b5..3eacf68e3a7010330cdecc548ed76c280ab01308 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -456,7 +456,7 @@ static inline void list_splice_tail_init(struct list_head *list, * Continue to iterate over list of given type, continuing after * the current position. */ -#define list_for_each_entry_continue(pos, head, member) \ +#define list_for_each_entry_continue(pos, head, member) \ for (pos = list_entry(pos->member.next, typeof(*pos), member); \ prefetch(pos->member.next), &pos->member != (head); \ pos = list_entry(pos->member.next, typeof(*pos), member)) @@ -510,7 +510,7 @@ static inline void list_splice_tail_init(struct list_head *list, * Iterate over list of given type, continuing after current point, * safe against removal of list entry. */ -#define list_for_each_entry_safe_continue(pos, n, head, member) \ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ for (pos = list_entry(pos->member.next, typeof(*pos), member), \ n = list_entry(pos->member.next, typeof(*pos), member); \ &pos->member != (head); \ diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index d57f8da81042bb98d54f4796b054e694e6824f90..a72cb7d20b7dec19e2652fe2332f93e660153997 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -54,7 +54,7 @@ #define DoC_Mplus_Configuration 0x100a #define DoC_Mplus_OutputControl 0x100c #define DoC_Mplus_FlashControl 0x1020 -#define DoC_Mplus_FlashSelect 0x1022 +#define DoC_Mplus_FlashSelect 0x1022 #define DoC_Mplus_FlashCmd 0x1024 #define DoC_Mplus_FlashAddress 0x1026 #define DoC_Mplus_FlashData0 0x1028 @@ -62,14 +62,14 @@ #define DoC_Mplus_ReadPipeInit 0x102a #define DoC_Mplus_LastDataRead 0x102c #define DoC_Mplus_LastDataRead1 0x102d -#define DoC_Mplus_WritePipeTerm 0x102e +#define DoC_Mplus_WritePipeTerm 0x102e #define DoC_Mplus_ECCSyndrome0 0x1040 #define DoC_Mplus_ECCSyndrome1 0x1041 #define DoC_Mplus_ECCSyndrome2 0x1042 #define DoC_Mplus_ECCSyndrome3 0x1043 #define DoC_Mplus_ECCSyndrome4 0x1044 #define DoC_Mplus_ECCSyndrome5 0x1045 -#define DoC_Mplus_ECCConf 0x1046 +#define DoC_Mplus_ECCConf 0x1046 #define DoC_Mplus_Toggle 0x1046 #define DoC_Mplus_DownloadStatus 0x1074 #define DoC_Mplus_CtrlConfirm 0x1076 diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h index 666480db931252baf71ec78eb9e12efc617aa74e..265e89f02b60767074892b8ae579a0eada8f5bf2 100644 --- a/include/linux/mtd/flashchip.h +++ b/include/linux/mtd/flashchip.h @@ -52,7 +52,6 @@ typedef enum { } flstate_t; - /* NOTE: confusingly, this can be used to refer to more than one chip at a time, if they're interleaved. This can even refer to individual partitions on the same physical chip when present. */ diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index 3822237f2ad6193781e7b2657a226803f1140fe9..0f5a2332663c38a1daad13c729581950d34bcc59 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -21,16 +21,16 @@ * For each partition, these fields are available: * name: string that will be used to label the partition's MTD device. * size: the partition size; if defined as MTDPART_SIZ_FULL, the partition - * will extend to the end of the master MTD device. + * will extend to the end of the master MTD device. * offset: absolute starting position within the master MTD device; if - * defined as MTDPART_OFS_APPEND, the partition will start where the + * defined as MTDPART_OFS_APPEND, the partition will start where the * previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block; * if MTDPART_OFS_RETAIN, consume as much as possible, leaving size * after the end of partition. * mask_flags: contains flags that have to be masked (removed) from the - * master MTD flag set for the corresponding MTD partition. - * For example, to force a read-only partition, simply adding - * MTD_WRITEABLE to the mask_flags will do the trick. + * master MTD flag set for the corresponding MTD partition. + * For example, to force a read-only partition, simply adding + * MTD_WRITEABLE to the mask_flags will do the trick. * * Note: writeable partitions require their size and offset be * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK). diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 2fba9dc317e3c8bdbe665fad36118e9aaee69dfa..3417ca2a0d2eb5230f62dfc058900a2a5aecc4dc 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -945,7 +945,7 @@ struct nand_chip { int jedec_version; struct nand_onfi_params onfi_params; struct nand_jedec_params jedec_params; - + struct nand_data_interface *data_interface; int read_retries; diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h index 899fbb487c94e5cb2385ff90ab86f0b8985aa435..46e7fff899fb7175b187045631c3e12f99da83a2 100644 --- a/include/linux/screen_info.h +++ b/include/linux/screen_info.h @@ -47,7 +47,7 @@ struct screen_info { } __attribute__((packed)); #define VIDEO_TYPE_MDA 0x10 /* Monochrome Text Display */ -#define VIDEO_TYPE_CGA 0x11 /* CGA Display */ +#define VIDEO_TYPE_CGA 0x11 /* CGA Display */ #define VIDEO_TYPE_EGAM 0x20 /* EGA/VGA in Monochrome Mode */ #define VIDEO_TYPE_EGAC 0x21 /* EGA in Color Mode */ #define VIDEO_TYPE_VGAC 0x22 /* VGA+ in Color Mode */ @@ -74,7 +74,7 @@ extern struct screen_info screen_info; #define ORIG_X (screen_info.orig_x) #define ORIG_Y (screen_info.orig_y) #define ORIG_VIDEO_MODE (screen_info.orig_video_mode) -#define ORIG_VIDEO_COLS (screen_info.orig_video_cols) +#define ORIG_VIDEO_COLS (screen_info.orig_video_cols) #define ORIG_VIDEO_EGA_BX (screen_info.orig_video_ega_bx) #define ORIG_VIDEO_LINES (screen_info.orig_video_lines) #define ORIG_VIDEO_ISVGA (screen_info.orig_video_isVGA) diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 29c3b5b9a530e50847b2d1a933bae2909f4e5c81..061371773c0fea38914f1cd715624293bdbf6a32 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -3,7 +3,7 @@ * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. - * + * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). @@ -88,7 +88,7 @@ #define UART_LCR 3 /* Out: Line Control Register */ /* - * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ @@ -257,7 +257,7 @@ */ #define UART_ASR 0x01 /* Additional Status Register */ #define UART_RFL 0x03 /* Receiver FIFO level */ -#define UART_TFL 0x04 /* Transmitter FIFO level */ +#define UART_TFL 0x04 /* Transmitter FIFO level */ #define UART_ICR 0x05 /* Index Control Register */ /* The 16950 ICR registers */ @@ -288,7 +288,6 @@ #define UART_ACR_ASREN 0x80 /* Additional status enable */ - /* * These definitions are for the RSA-DV II/S card, from * @@ -384,4 +383,3 @@ #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ #endif /* _LINUX_SERIAL_REG_H */ - diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 7e6d329e5427cbf9cbc732a6a02588a9909ce86e..b3f4b8d134c155f5550f7e881cbfc965596f9f24 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -160,14 +160,14 @@ struct usb_ep_caps { * endpoint. It's set once by UDC driver when endpoint is initialized, and * should not be changed. Should not be confused with maxpacket. * @max_streams: The maximum number of streams supported - * by this EP (0 - 16, actual number is 2^n) + * by this EP (0 - 16, actual number is 2^n) * @maxburst: the maximum number of bursts supported by this EP (for usb3) * @driver_data:for use by the gadget driver. all other fields are * read-only to gadget drivers. * @desc: endpoint descriptor. This pointer is set before the endpoint is - * enabled and remains valid until the endpoint is disabled. + * enabled and remains valid until the endpoint is disabled. * @comp_desc: In case of SuperSpeed support, this is the endpoint companion - * descriptor that is used to configure the endpoint + * descriptor that is used to configure the endpoint * * the bus controller driver lists all the general purpose endpoints in * gadget->ep_list. the control endpoint (gadget->ep0) is not in that list, diff --git a/include/lmb.h b/include/lmb.h index 3c4afdf9f0641879873e5c2e144b50ec24503fed..198429113224bd43955e56cc7476110edcb72b03 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -122,6 +122,7 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) void board_lmb_reserve(struct lmb *lmb); void arch_lmb_reserve(struct lmb *lmb); +void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align); /* Low level functions */ diff --git a/include/mc13783.h b/include/mc13783.h index 47345f006fecfbf8bc64204c3cfc5e4b80f021e9..c7ee03b0f9f953da97485249092a0c84bbd9e81a 100644 --- a/include/mc13783.h +++ b/include/mc13783.h @@ -18,7 +18,7 @@ #define VIOLOEN (1 << 6) #define VIOLOSTBY (1 << 7) #define VIOLOMODE (1 << 8) -#define VDIGEN (1 << 9) +#define VDIGEN (1 << 9) #define VDIGSTBY (1 << 10) #define VDIGMODE (1 << 11) #define VGENEN (1 << 12) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 71cffa1b0fc86cad445943bf9ccc2e6b1cb05761..0275b3184ea36cdd6cd44747a0c9238b5a964c77 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1372,7 +1372,7 @@ #endif /* !CONFIG_MPC83XX_SDRAM */ /* - * CONFIG_ADDRESS - PCI Config Address Register + * PCI_CONFIG_ADDRESS - PCI Config Address Register */ #define PCI_CONFIG_ADDRESS_EN 0x80000000 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 3753e47edfb5336ecd371028dea708b961854bc9..ce6d083effa051b2730de9c711d55a4f6cceaa20 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -42,7 +42,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT #endif #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH @@ -54,14 +54,14 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT #endif #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ CONFIG_SYS_CCSRBAR_PHYS_LOW) #ifndef CONFIG_SYS_IMMR -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR #endif #endif /* __MPC85xx_H__ */ diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index 8d9761050f0ba636ca662f751afec2318c867eb2..ea244fbaeb0f98bb8a7aa583e06be79382e5846b 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -106,7 +106,7 @@ struct mtd_write_req { #define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode) #define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme #define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read) -#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default +#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default /* OTP mode selection */ #define MTD_OTP_OFF 0 diff --git a/include/mvmfp.h b/include/mvmfp.h index 16f26841e2000c703e2aef78d50f13ccd479bee5..de86ffd5e2de4a386610b1e4e486b25e04208c37 100644 --- a/include/mvmfp.h +++ b/include/mvmfp.h @@ -45,7 +45,7 @@ /* * to facilitate the definition, the following macros are provided * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF + * offset, pull,pF, drv,dF, edge,eF ,afn,aF */ #define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) #define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) diff --git a/include/net/dsa.h b/include/net/dsa.h index 0f31a908c9d139ac707399c2f60f49f229ea9e26..a339a49730335623a4ecd0c3b0d049702c06b9f7 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ #ifndef __DSA_H__ @@ -57,7 +57,8 @@ /** * struct dsa_ops - DSA operations * - * @port_enable: Initialize a switch port for I/O. + * @port_probe: Initialize a switch port. + * @port_enable: Enable I/O for a port. * @port_disable: Disable I/O for a port. * @xmit: Insert the DSA tag for transmission. * DSA drivers receive a copy of the packet with headroom and @@ -69,6 +70,8 @@ * master including any additional headers. */ struct dsa_ops { + int (*port_probe)(struct udevice *dev, int port, + struct phy_device *phy); int (*port_enable)(struct udevice *dev, int port, struct phy_device *phy); void (*port_disable)(struct udevice *dev, int port, diff --git a/include/netdev.h b/include/netdev.h index 00a0993a8356d4c74a276913fe1b5be91cdf9c87..fb18f09893c1b202b6c58a8bfad8d69381129dbc 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -29,7 +29,6 @@ int board_interface_eth_init(struct udevice *dev, int cpu_eth_init(struct bd_info *bis); /* Driver initialization prototypes */ -int at91emac_register(struct bd_info *bis, unsigned long iobase); int ax88180_initialize(struct bd_info *bis); int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num); int bfin_EMAC_initialize(struct bd_info *bis); diff --git a/include/os.h b/include/os.h index 7b20d606dd04371c30e2f94edae322b286cddaba..770d76e02f7e1aa02219ec61aa71cce0ce0fc5a4 100644 --- a/include/os.h +++ b/include/os.h @@ -51,6 +51,14 @@ off_t os_lseek(int fd, off_t offset, int whence); #define OS_SEEK_CUR 1 #define OS_SEEK_END 2 +/** + * os_filesize() - Calculate the size of a file + * + * @fd: File descriptor as returned by os_open() + * Return: file size or negative error code + */ +int os_filesize(int fd); + /** * Access to the OS open() system call * @@ -398,6 +406,19 @@ int os_write_file(const char *name, const void *buf, int size); */ int os_read_file(const char *name, void **bufp, int *sizep); +/** + * os_map_file() - Map a file from the host filesystem into memory + * + * This can be useful when to provide a backing store for an emulated device + * + * @pathname: File pathname to map + * @os_flags: Flags, like OS_O_RDONLY, OS_O_RDWR + * @bufp: Returns buffer containing the file + * @sizep: Returns size of data + * Return: 0 if OK, -ve on error + */ +int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep); + /* * os_find_text_base() - Find the text section in this running process * diff --git a/include/part.h b/include/part.h index 419c85970886041bf5b5b31947c69cec627ce2a0..b66b07a1f04be8db4d754da6f8dbc23c3cfd2125 100644 --- a/include/part.h +++ b/include/part.h @@ -75,7 +75,7 @@ struct disk_partition { char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */ #endif #ifdef CONFIG_DOS_PARTITION - uchar sys_ind; /* partition type */ + uchar sys_ind; /* partition type */ #endif }; diff --git a/include/pci.h b/include/pci.h index 0fc22adffd00eec7c22279e0272ab9c13f770c4f..11009a2f787a22da435f86132a1ff85fbec39c3d 100644 --- a/include/pci.h +++ b/include/pci.h @@ -724,6 +724,7 @@ void pciauto_config_init(struct pci_controller *hose); */ int pciauto_region_allocate(struct pci_region *res, pci_size_t size, pci_addr_t *bar, bool supports_64bit); +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); #if defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, @@ -741,7 +742,6 @@ extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern struct pci_controller *pci_get_hose_head(void); -extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); diff --git a/include/phy.h b/include/phy.h index 6b928636b6d7e879b06dec67359c8c9977b61666..c66fd43ea887d5b4ab6a20ac624b7df6f2afdb78 100644 --- a/include/phy.h +++ b/include/phy.h @@ -368,7 +368,7 @@ static inline int is_10g_interface(phy_interface_t interface) { return interface == PHY_INTERFACE_MODE_XGMII || interface == PHY_INTERFACE_MODE_USXGMII || - interface == PHY_INTERFACE_MODE_XFI; + interface == PHY_INTERFACE_MODE_10GBASER; } #endif @@ -575,8 +575,8 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) } /* PHY UIDs for various PHYs that are referenced in external code */ -#define PHY_UID_CS4340 0x13e51002 -#define PHY_UID_CS4223 0x03e57003 +#define PHY_UID_CS4340 0x13e51002 +#define PHY_UID_CS4223 0x03e57003 #define PHY_UID_TN2020 0x00a19410 #define PHY_UID_IN112525_S03 0x02107440 diff --git a/include/phy_interface.h b/include/phy_interface.h index ebb18ecd40c027b7de10e3f349cc1ea4a8a81776..f075abe9c9c0cd7a13cbdb9bf4ed8e4cb5cf8c1d 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -37,7 +37,7 @@ typedef enum { PHY_INTERFACE_MODE_CAUI2, PHY_INTERFACE_MODE_CAUI4, PHY_INTERFACE_MODE_NCSI, - PHY_INTERFACE_MODE_XFI, + PHY_INTERFACE_MODE_10GBASER, PHY_INTERFACE_MODE_USXGMII, PHY_INTERFACE_MODE_NONE, /* Must be last */ @@ -69,7 +69,7 @@ static const char * const phy_interface_strings[] = { [PHY_INTERFACE_MODE_CAUI2] = "caui2", [PHY_INTERFACE_MODE_CAUI4] = "caui4", [PHY_INTERFACE_MODE_NCSI] = "NC-SI", - [PHY_INTERFACE_MODE_XFI] = "xfi", + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", [PHY_INTERFACE_MODE_NONE] = "", }; diff --git a/include/power-domain.h b/include/power-domain.h index 72ff2ff25ba2b0d747d9f29d2c35e450b4d555a5..62ff19948f9abeb41505e45465fd835e8f02f6f5 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -162,8 +162,7 @@ static inline int power_domain_off(struct power_domain *power_domain) * * @return 0 if OK, or a negative error code. */ -#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ - CONFIG_IS_ENABLED(POWER_DOMAIN) +#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(POWER_DOMAIN) int dev_power_domain_on(struct udevice *dev); #else static inline int dev_power_domain_on(struct udevice *dev) @@ -179,8 +178,7 @@ static inline int dev_power_domain_on(struct udevice *dev) * * @return 0 if OK, or a negative error code. */ -#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ - CONFIG_IS_ENABLED(POWER_DOMAIN) +#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(POWER_DOMAIN) int dev_power_domain_off(struct udevice *dev); #else static inline int dev_power_domain_off(struct udevice *dev) diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index 82fe3509a0b7a94d0e371c78d0f223aec6e88108..cf476c85ab3c011a5ce7eb71255ee6ce201ad33a 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -154,7 +154,7 @@ enum { OPMODE_ON, }; -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); diff --git a/include/power/pmic.h b/include/power/pmic.h index be9de6b4de7e610516171386c3272440dfc9f52a..97f855ce398b0aeb809804f56bdd1b3df26ea5ea 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -17,7 +17,8 @@ enum { PMIC_I2C, PMIC_SPI, PMIC_NONE}; -#ifdef CONFIG_POWER +/* TODO: Change to !CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ +#if CONFIG_IS_ENABLED(POWER_LEGACY) enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; @@ -82,8 +83,9 @@ struct pmic { struct pmic *parent; struct list_head list; }; -#endif /* CONFIG_POWER */ +#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ +/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ #ifdef CONFIG_DM_PMIC /** * U-Boot PMIC Framework @@ -306,9 +308,12 @@ struct uc_pmic_priv { uint trans_len; }; -#endif /* CONFIG_DM_PMIC */ +#endif /* DM_PMIC */ -#ifdef CONFIG_POWER +/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ +#if CONFIG_IS_ENABLED(POWER_LEGACY) + +/* Legacy API, do not use */ int pmic_init(unsigned char bus); int power_init_board(void); int pmic_dialog_init(unsigned char bus); @@ -319,7 +324,7 @@ int pmic_probe(struct pmic *p); int pmic_reg_read(struct pmic *p, u32 reg, u32 *val); int pmic_reg_write(struct pmic *p, u32 reg, u32 val); int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on); -#endif +#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ #define pmic_i2c_addr (p->hw.i2c.addr) #define pmic_i2c_tx_num (p->hw.i2c.tx_num) diff --git a/include/radeon.h b/include/radeon.h deleted file mode 100644 index da6c26bbe3bf4d4e7c9bdb813b42f2009467a502..0000000000000000000000000000000000000000 --- a/include/radeon.h +++ /dev/null @@ -1,1988 +0,0 @@ -#ifndef _RADEON_H -#define _RADEON_H - - -#define RADEON_REGSIZE 0x4000 - - -#define MM_INDEX 0x0000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -#define I2C_CNTL_1 0x0094 -#define CONFIG_CNTL 0x00E0 -#define CONFIG_MEMSIZE 0x00F8 -#define CONFIG_APER_0_BASE 0x0100 -#define CONFIG_APER_1_BASE 0x0104 -#define CONFIG_APER_SIZE 0x0108 -#define CONFIG_REG_1_BASE 0x010C -#define CONFIG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define PAD_CTLR_MISC 0x0aa0 -#define AGP_CNTL 0x0174 -#define BM_STATUS 0x0160 -#define CAP0_TRIG_CNTL 0x0950 -#define CAP1_TRIG_CNTL 0x09c0 -#define VIPH_CONTROL 0x0C40 -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define BASE_CODE 0x0F0B -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -#define AGP_COMMAND 0x0F60 -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -#define DAC_CNTL2 0x007c -#define CRTC_GEN_CNTL 0x0050 -#define MEM_CNTL 0x0140 -#define MC_CNTL 0x0140 -#define EXT_MEM_CNTL 0x0144 -#define MC_TIMING_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_REFRESH_CNTL 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MC_INIT_GFX_LAT_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#define MEM_IO_CNTL_A1 0x017C -#define MC_READ_CNTL_AB 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MC_INIT_MISC_LAT_TIMER 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_IOPAD_CNTL 0x0184 -#define MC_DEBUG 0x0188 -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_CHIP_IO_OE_CNTL_AB 0x018C -#define MC_FB_LOCATION 0x0148 -/* #define MC_FB_LOCATION 0x0188 */ -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define CRTC2_GEN_CNTL 0x03f8 -#define CRTC2_DISPLAY_BASE_ADDR 0x033c -#define SURFACE_CNTL 0x0B00 -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -#define CRTC_EXT_CNTL 0x0054 -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define GPIO_CRT2_DDC 0x006c -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -#define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_H_SYNC_POL (1 << 23) -#define CRTC_V_TOTAL_DISP 0x0208 -#define CRTC_V_SYNC_STRT_WID 0x020C -#define CRTC_V_SYNC_POL (1 << 23) -#define CRTC_VLINE_CRNT_VLINE 0x0210 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC_DEBUG 0x021C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC_OFFSET_CNTL 0x0228 -#define CRTC_PITCH 0x022C -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -#define FP_HORZ_STRETCH 0x028C -#define FP_VERT_STRETCH 0x0290 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -/* #define DDA_CONFIG 0x02e0 */ -/* #define DDA_ON_OFF 0x02e4 */ -#define DVI_I2C_CNTL_1 0x02e4 -#define GRPH_BUFFER_CNTL 0x02F0 -#define GRPH2_BUFFER_CNTL 0x03F0 -#define VGA_BUFFER_CNTL 0x02F4 -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_REG_LOAD_CNTL 0x0410 -#define OV0_SCALE_CNTL 0x0420 -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -#define OV0_P23_V_ACCUM_INIT 0x042C -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -#define OV0_BASE_ADDR 0x043C -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -#define OV0_VID_BUF3_BASE_ADRS 0x044C -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTRL 0x0470 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -#define OV0_FOUR_TAP_COEF_0 0x04B0 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -#define OV0_FOUR_TAP_COEF_3 0x04BC -#define OV0_FOUR_TAP_COEF_4 0x04C0 -#define OV0_FLAG_CNTRL 0x04DC -#define OV0_SLICE_CNTL 0x04E0 -#define OV0_VID_KEY_CLR_LOW 0x04E4 -#define OV0_VID_KEY_CLR_HIGH 0x04E8 -#define OV0_GRPH_KEY_CLR_LOW 0x04EC -#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -#define OV0_TEST 0x04F8 -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 -#define DISP_MISC_CNTL 0x0D00 -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 -#define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#define DST_OFFSET 0x1404 -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -#define DP_DATATYPE 0x16C4 -#define DP_MIX 0x16C8 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -#define DEFAULT_SC_TOP_LEFT 0x16EC -#define SRC_PITCH_OFFSET 0x1428 -#define DST_PITCH_OFFSET 0x142C -#define DP_GUI_MASTER_CNTL 0x146C -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT 0x342C -#define LVDS_GEN_CNTL 0x02d0 -#define LVDS_PLL_CNTL 0x02d4 -#define FP2_GEN_CNTL 0x0288 -#define TMDS_CNTL 0x0294 -#define TMDS_CRC 0x02a0 -#define TMDS_TRANSMITTER_CNTL 0x02a4 -#define MPP_TB_CONFIG 0x01c0 -#define PAMAC0_DLY_CNTL 0x0a94 -#define PAMAC1_DLY_CNTL 0x0a98 -#define PAMAC2_DLY_CNTL 0x0a9c -#define FW_CNTL 0x0118 -#define FCP_CNTL 0x0910 -#define VGA_DDA_ON_OFF 0x02ec -#define TV_MASTER_CNTL 0x0800 - -/* #define BASE_CODE 0x0f0b */ -#define BIOS_0_SCRATCH 0x0010 -#define BIOS_1_SCRATCH 0x0014 -#define BIOS_2_SCRATCH 0x0018 -#define BIOS_3_SCRATCH 0x001c -#define BIOS_4_SCRATCH 0x0020 -#define BIOS_5_SCRATCH 0x0024 -#define BIOS_6_SCRATCH 0x0028 -#define BIOS_7_SCRATCH 0x002c - -#define HDP_SOFT_RESET (1 << 26) - -#define TV_DAC_CNTL 0x088c -#define GPIOPAD_MASK 0x0198 -#define GPIOPAD_A 0x019c -#define GPIOPAD_EN 0x01a0 -#define GPIOPAD_Y 0x01a4 -#define ZV_LCDPAD_MASK 0x01a8 -#define ZV_LCDPAD_A 0x01ac -#define ZV_LCDPAD_EN 0x01b0 -#define ZV_LCDPAD_Y 0x01b4 - -/* PLL Registers */ -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -#define PPLL_REF_DIV 0x0003 -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MDLL_CKO 0x000f -#define MDLL_RDCKA 0x0010 -#define MCLK_CNTL 0x0012 -#define AGP_PLL_CNTL 0x000b -#define PLL_TEST_CNTL 0x0013 -#define CLK_PWRMGT_CNTL 0x0014 -#define PLL_PWRMGT_CNTL 0x0015 -#define MCLK_MISC 0x001f -#define P2PLL_CNTL 0x002a -#define P2PLL_REF_DIV 0x002b -#define PIXCLKS_CNTL 0x002d -#define SCLK_MORE_CNTL 0x0035 - -/* MCLK_CNTL bit constants */ -#define FORCEON_MCLKA (1 << 16) -#define FORCEON_MCLKB (1 << 17) -#define FORCEON_YCLKA (1 << 18) -#define FORCEON_YCLKB (1 << 19) -#define FORCEON_MC (1 << 20) -#define FORCEON_AIC (1 << 21) - -/* SCLK_CNTL bit constants */ -#define DYN_STOP_LAT_MASK 0x00007ff8 -#define CP_MAX_DYN_STOP_LAT 0x0008 -#define SCLK_FORCEON_MASK 0xffff8000 - -/* SCLK_MORE_CNTL bit constants */ -#define SCLK_MORE_FORCEON 0x0700 - -/* BUS_CNTL bit constants */ -#define BUS_DBL_RESYNC 0x00000001 -#define BUS_MSTR_RESET 0x00000002 -#define BUS_FLUSH_BUF 0x00000004 -#define BUS_STOP_REQ_DIS 0x00000008 -#define BUS_ROTATION_DIS 0x00000010 -#define BUS_MASTER_DIS 0x00000040 -#define BUS_ROM_WRT_EN 0x00000080 -#define BUS_DIS_ROM 0x00001000 -#define BUS_PCI_READ_RETRY_EN 0x00002000 -#define BUS_AGP_AD_STEPPING_EN 0x00004000 -#define BUS_PCI_WRT_RETRY_EN 0x00008000 -#define BUS_MSTR_RD_MULT 0x00100000 -#define BUS_MSTR_RD_LINE 0x00200000 -#define BUS_SUSPEND 0x00400000 -#define LAT_16X 0x00800000 -#define BUS_RD_DISCARD_EN 0x01000000 -#define BUS_RD_ABORT_EN 0x02000000 -#define BUS_MSTR_WS 0x04000000 -#define BUS_PARKING_DIS 0x08000000 -#define BUS_MSTR_DISCONNECT_EN 0x10000000 -#define BUS_WRT_BURST 0x20000000 -#define BUS_READ_BURST 0x40000000 -#define BUS_RDY_READ_DLY 0x80000000 - -/* PIXCLKS_CNTL */ -#define PIX2CLK_SRC_SEL_MASK 0x03 -#define PIX2CLK_SRC_SEL_CPUCLK 0x00 -#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 -#define PIX2CLK_SRC_SEL_BYTECLK 0x02 -#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -#define PIX2CLK_ALWAYS_ONb (1<<6) -#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) -#define PIXCLK_TV_SRC_SEL (1 << 8) -#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) - - -/* CLOCK_CNTL_INDEX bit constants */ -#define PLL_WR_EN 0x00000080 - -/* CONFIG_CNTL bit constants */ -#define CONFIG_SYS_VGA_RAM_EN 0x00000100 -#define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16) -#define CONFIG_SYS_ATI_REV_A11 (0 << 16) -#define CONFIG_SYS_ATI_REV_A12 (1 << 16) -#define CONFIG_SYS_ATI_REV_A13 (2 << 16) - -/* CRTC_EXT_CNTL bit constants */ -#define VGA_ATI_LINEAR 0x00000008 -#define VGA_128KAP_PAGING 0x00000010 -#define XCRT_CNT_EN (1 << 6) -#define CRTC_HSYNC_DIS (1 << 8) -#define CRTC_VSYNC_DIS (1 << 9) -#define CRTC_DISPLAY_DIS (1 << 10) -#define CRTC_CRT_ON (1 << 15) - - -/* DSTCACHE_CTLSTAT bit constants */ -#define RB2D_DC_FLUSH (3 << 0) -#define RB2D_DC_FLUSH_ALL 0xf -#define RB2D_DC_BUSY (1 << 31) - - -/* CRTC_GEN_CNTL bit constants */ -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_CUR_EN 0x00010000 -#define CRTC_INTERLACE_EN (1 << 1) -#define CRTC_BYPASS_LUT_EN (1 << 14) -#define CRTC_EXT_DISP_EN (1 << 24) -#define CRTC_EN (1 << 25) -#define CRTC_DISP_REQ_EN_B (1 << 26) - -/* CRTC_STATUS bit constants */ -#define CRTC_VBLANK 0x00000001 - -/* CRTC2_GEN_CNTL bit constants */ -#define CRT2_ON (1 << 7) -#define CRTC2_DISPLAY_DIS (1 << 23) -#define CRTC2_EN (1 << 25) -#define CRTC2_DISP_REQ_EN_B (1 << 26) - -/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -#define CUR_LOCK 0x80000000 - -/* GPIO bit constants */ -#define GPIO_A_0 (1 << 0) -#define GPIO_A_1 (1 << 1) -#define GPIO_Y_0 (1 << 8) -#define GPIO_Y_1 (1 << 9) -#define GPIO_EN_0 (1 << 16) -#define GPIO_EN_1 (1 << 17) -#define GPIO_MASK_0 (1 << 24) -#define GPIO_MASK_1 (1 << 25) -#define VGA_DDC_DATA_OUTPUT GPIO_A_0 -#define VGA_DDC_CLK_OUTPUT GPIO_A_1 -#define VGA_DDC_DATA_INPUT GPIO_Y_0 -#define VGA_DDC_CLK_INPUT GPIO_Y_1 -#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 -#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 - - -/* FP bit constants */ -#define FP_CRTC_H_TOTAL_MASK 000003ff -#define FP_CRTC_H_DISP_MASK 0x01ff0000 -#define FP_CRTC_V_TOTAL_MASK 0x00000fff -#define FP_CRTC_V_DISP_MASK 0x0fff0000 -#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -#define FP_H_SYNC_WID_MASK 0x003f0000 -#define FP_V_SYNC_STRT_MASK 0x00000fff -#define FP_V_SYNC_WID_MASK 0x001f0000 -#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_H_DISP_SHIFT 0x00000010 -#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_V_DISP_SHIFT 0x00000010 -#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -#define FP_H_SYNC_WID_SHIFT 0x00000010 -#define FP_V_SYNC_STRT_SHIFT 0x00000000 -#define FP_V_SYNC_WID_SHIFT 0x00000010 - -/* FP_GEN_CNTL bit constants */ -#define FP_FPON (1 << 0) -#define FP_TMDS_EN (1 << 2) -#define FP_PANEL_FORMAT (1 << 3) -#define FP_EN_TMDS (1 << 7) -#define FP_DETECT_SENSE (1 << 8) -#define R200_FP_SOURCE_SEL_MASK (3 << 10) -#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -#define R200_FP_SOURCE_SEL_RMX (2 << 10) -#define R200_FP_SOURCE_SEL_TRANS (3 << 10) -#define FP_SEL_CRTC1 (0 << 13) -#define FP_SEL_CRTC2 (1 << 13) -#define FP_USE_VGA_HSYNC (1 << 14) -#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -#define FP_CRTC_USE_SHADOW_VEND (1 << 18) -#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -#define FP_DFP_SYNC_SEL (1 << 21) -#define FP_CRTC_LOCK_8DOT (1 << 22) -#define FP_CRT_SYNC_SEL (1 << 23) -#define FP_USE_SHADOW_EN (1 << 24) -#define FP_CRT_SYNC_ALT (1 << 26) - -/* FP2_GEN_CNTL bit constants */ -#define FP2_BLANK_EN (1 << 1) -#define FP2_ON (1 << 2) -#define FP2_PANEL_FORMAT (1 << 3) -#define FP2_SOURCE_SEL_MASK (3 << 10) -#define FP2_SOURCE_SEL_CRTC2 (1 << 10) -#define FP2_SRC_SEL_MASK (3 << 13) -#define FP2_SRC_SEL_CRTC2 (1 << 13) -#define FP2_FP_POL (1 << 16) -#define FP2_LP_POL (1 << 17) -#define FP2_SCK_POL (1 << 18) -#define FP2_LCD_CNTL_MASK (7 << 19) -#define FP2_PAD_FLOP_EN (1 << 22) -#define FP2_CRC_EN (1 << 23) -#define FP2_CRC_READ_EN (1 << 24) -#define FP2_DV0_EN (1 << 25) -#define FP2_DV0_RATE_SEL_SDR (1 << 26) - - -/* LVDS_GEN_CNTL bit constants */ -#define LVDS_ON (1 << 0) -#define LVDS_DISPLAY_DIS (1 << 1) -#define LVDS_PANEL_TYPE (1 << 2) -#define LVDS_PANEL_FORMAT (1 << 3) -#define LVDS_EN (1 << 7) -#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 -#define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN (1 << 16) -#define LVDS_DIGON (1 << 18) -#define LVDS_BLON (1 << 19) -#define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_STATE_MASK \ - (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) - -/* LVDS_PLL_CNTL bit constatns */ -#define HSYNC_DELAY_SHIFT 0x1c -#define HSYNC_DELAY_MASK (0xf << 0x1c) - -/* TMDS_TRANSMITTER_CNTL bit constants */ -#define TMDS_PLL_EN (1 << 0) -#define TMDS_PLLRST (1 << 1) -#define TMDS_RAN_PAT_RST (1 << 7) -#define TMDS_ICHCSEL (1 << 28) - -/* FP_HORZ_STRETCH bit constants */ -#define HORZ_STRETCH_RATIO_MASK 0xffff -#define HORZ_STRETCH_RATIO_MAX 4096 -#define HORZ_PANEL_SIZE (0x1ff << 16) -#define HORZ_PANEL_SHIFT 16 -#define HORZ_STRETCH_PIXREP (0 << 25) -#define HORZ_STRETCH_BLEND (1 << 26) -#define HORZ_STRETCH_ENABLE (1 << 25) -#define HORZ_AUTO_RATIO (1 << 27) -#define HORZ_FP_LOOP_STRETCH (0x7 << 28) -#define HORZ_AUTO_RATIO_INC (1 << 31) - - -/* FP_VERT_STRETCH bit constants */ -#define VERT_STRETCH_RATIO_MASK 0xfff -#define VERT_STRETCH_RATIO_MAX 4096 -#define VERT_PANEL_SIZE (0xfff << 12) -#define VERT_PANEL_SHIFT 12 -#define VERT_STRETCH_LINREP (0 << 26) -#define VERT_STRETCH_BLEND (1 << 26) -#define VERT_STRETCH_ENABLE (1 << 25) -#define VERT_AUTO_RATIO_EN (1 << 27) -#define VERT_FP_LOOP_STRETCH (0x7 << 28) -#define VERT_STRETCH_RESERVED 0xf1000000 - -/* DAC_CNTL bit constants */ -#define DAC_8BIT_EN 0x00000100 -#define DAC_4BPP_PIX_ORDER 0x00000200 -#define DAC_CRC_EN 0x00080000 -#define DAC_MASK_ALL (0xff << 24) -#define DAC_PDWN (1 << 15) -#define DAC_EXPAND_MODE (1 << 14) -#define DAC_VGA_ADR_EN (1 << 13) -#define DAC_RANGE_CNTL (3 << 0) -#define DAC_RANGE_CNTL_MASK 0x03 -#define DAC_BLANKING (1 << 2) -#define DAC_CMP_EN (1 << 3) -#define DAC_CMP_OUTPUT (1 << 7) - -/* DAC_CNTL2 bit constants */ -#define DAC2_EXPAND_MODE (1 << 14) -#define DAC2_CMP_EN (1 << 7) -#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) - -/* DAC_EXT_CNTL bit constants */ -#define DAC_FORCE_BLANK_OFF_EN (1 << 4) -#define DAC_FORCE_DATA_EN (1 << 5) -#define DAC_FORCE_DATA_SEL_MASK (3 << 6) -#define DAC_FORCE_DATA_MASK 0x0003ff00 -#define DAC_FORCE_DATA_SHIFT 8 - -/* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 - -/* MEM_CNTL bit constants */ -#define MEM_CTLR_STATUS_IDLE 0x00000000 -#define MEM_CTLR_STATUS_BUSY 0x00100000 -#define MEM_SEQNCR_STATUS_IDLE 0x00000000 -#define MEM_SEQNCR_STATUS_BUSY 0x00200000 -#define MEM_ARBITER_STATUS_IDLE 0x00000000 -#define MEM_ARBITER_STATUS_BUSY 0x00400000 -#define MEM_REQ_UNLOCK 0x00000000 -#define MEM_REQ_LOCK 0x00800000 -#define MEM_NUM_CHANNELS_MASK 0x00000001 -#define MEM_USE_B_CH_ONLY 0x00000002 -#define RV100_MEM_HALF_MODE 0x00000008 -#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 -#define R300_MEM_USE_CD_CH_ONLY 0x00000004 - - -/* RBBM_SOFT_RESET bit constants */ -#define SOFT_RESET_CP (1 << 0) -#define SOFT_RESET_HI (1 << 1) -#define SOFT_RESET_SE (1 << 2) -#define SOFT_RESET_RE (1 << 3) -#define SOFT_RESET_PP (1 << 4) -#define SOFT_RESET_E2 (1 << 5) -#define SOFT_RESET_RB (1 << 6) -#define SOFT_RESET_HDP (1 << 7) - -/* SURFACE_CNTL bit consants */ -#define SURF_TRANSLATION_DIS (1 << 8) -#define NONSURF_AP0_SWP_16BPP (1 << 20) -#define NONSURF_AP0_SWP_32BPP (1 << 21) -#define NONSURF_AP1_SWP_16BPP (1 << 22) -#define NONSURF_AP1_SWP_32BPP (1 << 23) - -#define R200_SURF_TILE_COLOR_MACRO (1 << 16) - -/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) - -/* MM_INDEX bit constants */ -#define MM_APER 0x80000000 - -/* CLR_CMP_CNTL bit constants */ -#define COMPARE_SRC_FALSE 0x00000000 -#define COMPARE_SRC_TRUE 0x00000001 -#define COMPARE_SRC_NOT_EQUAL 0x00000004 -#define COMPARE_SRC_EQUAL 0x00000005 -#define COMPARE_SRC_EQUAL_FLIP 0x00000007 -#define COMPARE_DST_FALSE 0x00000000 -#define COMPARE_DST_TRUE 0x00000100 -#define COMPARE_DST_NOT_EQUAL 0x00000400 -#define COMPARE_DST_EQUAL 0x00000500 -#define COMPARE_DESTINATION 0x00000000 -#define COMPARE_SOURCE 0x01000000 -#define COMPARE_SRC_AND_DST 0x02000000 - - -/* DP_CNTL bit constants */ -#define DST_X_RIGHT_TO_LEFT 0x00000000 -#define DST_X_LEFT_TO_RIGHT 0x00000001 -#define DST_Y_BOTTOM_TO_TOP 0x00000000 -#define DST_Y_TOP_TO_BOTTOM 0x00000002 -#define DST_X_MAJOR 0x00000000 -#define DST_Y_MAJOR 0x00000004 -#define DST_X_TILE 0x00000008 -#define DST_Y_TILE 0x00000010 -#define DST_LAST_PEL 0x00000020 -#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -#define DST_BRES_SIGN 0x00000100 -#define DST_HOST_BIG_ENDIAN_EN 0x00000200 -#define DST_POLYLINE_NONLAST 0x00008000 -#define DST_RASTER_STALL 0x00010000 -#define DST_POLY_EDGE 0x00040000 - - -/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ -#define DST_X_MAJOR_S 0x00000000 -#define DST_Y_MAJOR_S 0x00000001 -#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -#define DST_X_RIGHT_TO_LEFT_S 0x00000000 -#define DST_X_LEFT_TO_RIGHT_S 0x80000000 - - -/* DP_DATATYPE bit constants */ -#define DST_8BPP 0x00000002 -#define DST_15BPP 0x00000003 -#define DST_16BPP 0x00000004 -#define DST_24BPP 0x00000005 -#define DST_32BPP 0x00000006 -#define DST_8BPP_RGB332 0x00000007 -#define DST_8BPP_Y8 0x00000008 -#define DST_8BPP_RGB8 0x00000009 -#define DST_16BPP_VYUY422 0x0000000b -#define DST_16BPP_YVYU422 0x0000000c -#define DST_32BPP_AYUV444 0x0000000e -#define DST_16BPP_ARGB4444 0x0000000f -#define BRUSH_SOLIDCOLOR 0x00000d00 -#define SRC_MONO 0x00000000 -#define SRC_MONO_LBKGD 0x00010000 -#define SRC_DSTCOLOR 0x00030000 -#define BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define BYTE_ORDER_LSB_TO_MSB 0x40000000 -#define DP_CONVERSION_TEMP 0x80000000 -#define HOST_BIG_ENDIAN_EN (1 << 29) - - -/* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_SRC_CLIP_LEAVE 0x00000004 -#define GMC_DST_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_LEAVE 0x00000008 -#define GMC_BRUSH_8x8MONO 0x00000000 -#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -#define GMC_BRUSH_8x1MONO 0x00000020 -#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -#define GMC_BRUSH_1x8MONO 0x00000040 -#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -#define GMC_BRUSH_32x1MONO 0x00000060 -#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -#define GMC_BRUSH_32x32MONO 0x00000080 -#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -#define GMC_BRUSH_8x8COLOR 0x000000a0 -#define GMC_BRUSH_8x1COLOR 0x000000b0 -#define GMC_BRUSH_1x8COLOR 0x000000c0 -#define GMC_BRUSH_SOLID_COLOR 0x000000d0 -#define GMC_DST_8BPP 0x00000200 -#define GMC_DST_15BPP 0x00000300 -#define GMC_DST_16BPP 0x00000400 -#define GMC_DST_24BPP 0x00000500 -#define GMC_DST_32BPP 0x00000600 -#define GMC_DST_8BPP_RGB332 0x00000700 -#define GMC_DST_8BPP_Y8 0x00000800 -#define GMC_DST_8BPP_RGB8 0x00000900 -#define GMC_DST_16BPP_VYUY422 0x00000b00 -#define GMC_DST_16BPP_YVYU422 0x00000c00 -#define GMC_DST_32BPP_AYUV444 0x00000e00 -#define GMC_DST_16BPP_ARGB4444 0x00000f00 -#define GMC_SRC_MONO 0x00000000 -#define GMC_SRC_MONO_LBKGD 0x00001000 -#define GMC_SRC_DSTCOLOR 0x00003000 -#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_DP_SRC_HOST 0x03000000 -#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -#define GMC_3D_FCN_EN_CLR 0x00000000 -#define GMC_3D_FCN_EN_SET 0x08000000 -#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -#define GMC_AUX_CLIP_LEAVE 0x00000000 -#define GMC_AUX_CLIP_CLEAR 0x20000000 -#define GMC_WRITE_MASK_LEAVE 0x00000000 -#define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_CLR_CMP_CNTL_DIS (1 << 28) -#define GMC_SRC_DATATYPE_COLOR (3 << 12) -#define ROP3_S 0x00cc0000 -#define ROP3_SRCCOPY 0x00cc0000 -#define ROP3_P 0x00f00000 -#define ROP3_PATCOPY 0x00f00000 -#define DP_SRC_SOURCE_MASK (7 << 24) -#define GMC_BRUSH_NONE (15 << 4) -#define DP_SRC_SOURCE_MEMORY (2 << 24) -#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 - -/* DP_MIX bit constants */ -#define DP_SRC_RECT 0x00000200 -#define DP_SRC_HOST 0x00000300 -#define DP_SRC_HOST_BYTEALIGN 0x00000400 - -/* MPLL_CNTL bit constants */ -#define MPLL_RESET 0x00000001 - -/* MDLL_CKO bit constants */ -#define MCKOA_SLEEP 0x00000001 -#define MCKOA_RESET 0x00000002 -#define MCKOA_REF_SKEW_MASK 0x00000700 -#define MCKOA_FB_SKEW_MASK 0x00007000 - -/* MDLL_RDCKA bit constants */ -#define MRDCKA0_SLEEP 0x00000001 -#define MRDCKA0_RESET 0x00000002 -#define MRDCKA1_SLEEP 0x00010000 -#define MRDCKA1_RESET 0x00020000 - -/* VCLK_ECP_CNTL constants */ -#define VCLK_SRC_SEL_MASK 0x03 -#define VCLK_SRC_SEL_CPUCLK 0x00 -#define VCLK_SRC_SEL_PSCANCLK 0x01 -#define VCLK_SRC_SEL_BYTECLK 0x02 -#define VCLK_SRC_SEL_PPLLCLK 0x03 -#define PIXCLK_ALWAYS_ONb 0x00000040 -#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 - -/* BUS_CNTL1 constants */ -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 -#define BUS_CNTL1_AGPCLK_VALID 0x80000000 - -/* PLL_PWRMGT_CNTL constants */ -#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 -#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 -#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 -#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 -#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 -#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 -#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 - -/* TV_DAC_CNTL constants */ -#define TV_DAC_CNTL_BGSLEEP 0x00000040 -#define TV_DAC_CNTL_DETECT 0x00000010 -#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 -#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 -#define TV_DAC_CNTL_BGADJ__SHIFT 16 -#define TV_DAC_CNTL_DACADJ__SHIFT 20 -#define TV_DAC_CNTL_RDACPD 0x01000000 -#define TV_DAC_CNTL_GDACPD 0x02000000 -#define TV_DAC_CNTL_BDACPD 0x04000000 - -/* DISP_MISC_CNTL constants */ -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) -#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) -#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) -#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) -#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) - -/* DISP_PWR_MAN constants */ -#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) -#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) -#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) -#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) -#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) -#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) -#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) -#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) -#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) -#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) -#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) -#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) -#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) - -/* masks */ - -#define CONFIG_MEMSIZE_MASK 0x1f000000 -#define MEM_CFG_TYPE 0x40000000 -#define DST_OFFSET_MASK 0x003fffff -#define DST_PITCH_MASK 0x3fc00000 -#define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_RESET 0x00000001 -#define PPLL_SLEEP 0x00000002 -#define PPLL_ATOMIC_UPDATE_EN 0x00010000 -#define PPLL_REF_DIV_MASK 0x000003ff -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 -#define PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 -#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) -#define R300_PPLL_REF_DIV_ACC_SHIFT 18 - -#define GUI_ACTIVE 0x80000000 - - -#define MC_IND_INDEX 0x01F8 -#define MC_IND_DATA 0x01FC - -/* PAD_CTLR_STRENGTH */ -#define PAD_MANUAL_OVERRIDE 0x80000000 - -/* pllCLK_PIN_CNTL */ -#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L -#define CLK_PIN_CNTL__OSC_EN 0x00000001L -#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L -#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L -#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L -#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L -#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L -#define CLK_PIN_CNTL__CG_SPARE 0x00004000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L -#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L -#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L - -/* pllCLK_PWRMGT_CNTL */ -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 -#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 -#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f -#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 -#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 -#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 -#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 -#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f - -/* pllP2PLL_CNTL */ -#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L -#define P2PLL_CNTL__P2PLL_RESET 0x00000001L -#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L -#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L -#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L -#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L -#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L -#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L -#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L -#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L -#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L -#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L -#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L - -/* pllPIXCLKS_CNTL */ -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 -#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f - - -/* pllPIXCLKS_CNTL */ -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L -#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L -#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) -#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) -#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) - - -/* pllP2PLL_DIV_0 */ -#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L -#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L - -/* pllSCLK_CNTL */ -#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L -#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L -#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L -#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L -#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L -#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L -#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L -#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L -#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L -#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L -#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L -#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L -#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L -#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 -#define SCLK_CNTL__FORCE_DISP2 0x00008000L -#define SCLK_CNTL__FORCE_CP 0x00010000L -#define SCLK_CNTL__FORCE_HDP 0x00020000L -#define SCLK_CNTL__FORCE_DISP1 0x00040000L -#define SCLK_CNTL__FORCE_TOP 0x00080000L -#define SCLK_CNTL__FORCE_E2 0x00100000L -#define SCLK_CNTL__FORCE_SE 0x00200000L -#define SCLK_CNTL__FORCE_IDCT 0x00400000L -#define SCLK_CNTL__FORCE_VIP 0x00800000L -#define SCLK_CNTL__FORCE_RE 0x01000000L -#define SCLK_CNTL__FORCE_PB 0x02000000L -#define SCLK_CNTL__FORCE_TAM 0x04000000L -#define SCLK_CNTL__FORCE_TDM 0x08000000L -#define SCLK_CNTL__FORCE_RB 0x10000000L -#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L -#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L -#define SCLK_CNTL__FORCE_OV0 0x80000000L -#define SCLK_CNTL__R300_FORCE_VAP (1<<21) -#define SCLK_CNTL__R300_FORCE_SR (1<<25) -#define SCLK_CNTL__R300_FORCE_PX (1<<26) -#define SCLK_CNTL__R300_FORCE_TX (1<<27) -#define SCLK_CNTL__R300_FORCE_US (1<<28) -#define SCLK_CNTL__R300_FORCE_SU (1<<30) -#define SCLK_CNTL__FORCEON_MASK 0xffff8000L - -/* pllSCLK_CNTL2 */ -#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) -#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) -#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) -#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) -#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) -#define SCLK_CNTL2__R300_FORCE_GA (1<<15) - -/* SCLK_MORE_CNTL */ -#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L -#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L -#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L -#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L -#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L -#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L -#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L -#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L -#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L -#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L -#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L -#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L -#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L -#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L -#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L -#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L -#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L -#define SCLK_MORE_CNTL__FORCEON 0x00000700L - -/* MCLK_CNTL */ -#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L -#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L -#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L -#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L -#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L -#define MCLK_CNTL__FORCE_MCLKA 0x00010000L -#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L -#define MCLK_CNTL__FORCE_MCLKB 0x00020000L -#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L -#define MCLK_CNTL__FORCE_YCLKA 0x00040000L -#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L -#define MCLK_CNTL__FORCE_YCLKB 0x00080000L -#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L -#define MCLK_CNTL__FORCE_MC 0x00100000L -#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L -#define MCLK_CNTL__FORCE_AIC 0x00200000L -#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L -#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L -#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L -#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L -#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) -#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) - -/* MCLK_MISC */ -#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L -#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L -#define MCLK_MISC__DLL_READY_LAT 0x00000100L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L -#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L -#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L -#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L -#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L -#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L - -/* VCLK_ECP_CNTL */ -#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L -#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L -#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L -#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L -#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L -#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L -#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L -#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) - -/* PLL_PWRMGT_CNTL */ -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L -#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L -#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L -#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L -#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L -#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L -#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L - -/* CLK_PWRMGT_CNTL */ -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L -#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L -#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L -#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L -#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L -#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L -#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L -#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L -#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L -#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L -#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L -#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L -#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L - -/* BUS_CNTL1 */ -#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L -#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L -#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L -#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L -#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L -#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L -#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L -#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L -#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L -#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L -#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L -#define BUS_CNTL1__AGPCLK_VALID 0x80000000L - -/* BUS_CNTL1 */ -#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 -#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 -#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 -#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b -#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a -#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c -#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f - -/* CRTC_OFFSET_CNTL */ -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L - -/* CRTC_GEN_CNTL */ -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L -#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L -#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L -#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L -#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L - -/* CRTC2_GEN_CNTL */ -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L -#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L -#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L - -/* AGP_CNTL */ -#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL -#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L -#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L -#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L -#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L -#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L -#define AGP_CNTL__EN_2X_STBB 0x00000400L -#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L -#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L -#define AGP_CNTL__SBA_DIS_MASK 0x00001000L -#define AGP_CNTL__SBA_DIS 0x00001000L -#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L -#define AGP_CNTL__AGP_REV_ID 0x00002000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L -#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L -#define AGP_CNTL__FORCE_INT_VREF 0x00010000L -#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L -#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L -#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L -#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L -#define AGP_CNTL__EN_RBFCALM 0x00800000L -#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L -#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L -#define AGP_CNTL__DIS_RBF_MASK 0x02000000L -#define AGP_CNTL__DIS_RBF 0x02000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L -#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L - -/* AGP_CNTL */ -#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 -#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 -#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 -#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a -#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b -#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c -#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d -#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f -#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 -#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 -#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 -#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 -#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 -#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 -#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 -#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a -#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b -#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e - -/* DISP_MISC_CNTL */ -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L -#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L -#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L - -/* DISP_PWR_MAN */ -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L -#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L -#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L -#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L -#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L -#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L -#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L - -/* MC_IND_INDEX */ -#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL -#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L -#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L - -/* MC_IND_DATA */ -#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL - -/* MC_CHP_IO_CNTL_A1 */ -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f - -/* MC_CHP_IO_CNTL_B1 */ -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f - -/* MC_CHP_IO_CNTL_A1 */ -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L - -/* MC_CHP_IO_CNTL_B1 */ -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L - -/* MEM_SDRAM_MODE_REG */ -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L - -/* MEM_SDRAM_MODE_REG */ -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f - -/* MEM_REFRESH_CNTL */ -#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L -#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L - -/* MC_STATUS */ -#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L -#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L -#define MC_STATUS__MC_IDLE_MASK 0x00000004L -#define MC_STATUS__MC_IDLE 0x00000004L -#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L -#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L -#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L -#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L -#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L -#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L -#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L -#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L - -/* MDLL_CKO */ -#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L -#define MDLL_CKO__MCKOA_SLEEP 0x00000001L -#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L -#define MDLL_CKO__MCKOA_RESET 0x00000002L -#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL -#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L -#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L -#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L -#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L -#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L -#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L -#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L -#define MDLL_CKO__MCKOB_SLEEP 0x00010000L -#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L -#define MDLL_CKO__MCKOB_RESET 0x00020000L -#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L -#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L -#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L -#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L -#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L -#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L -#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L - -/* MDLL_RDCKA */ -#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L -#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L -#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L -#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L -#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L -#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L - -/* MDLL_RDCKB */ -#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L -#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L -#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L -#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L -#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L -#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L - -#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L -#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L -#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L -#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L -#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L -#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L -#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L -#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L - -#define pllCLK_PIN_CNTL 0x0001 -#define pllPPLL_CNTL 0x0002 -#define pllPPLL_REF_DIV 0x0003 -#define pllPPLL_DIV_0 0x0004 -#define pllPPLL_DIV_1 0x0005 -#define pllPPLL_DIV_2 0x0006 -#define pllPPLL_DIV_3 0x0007 -#define pllVCLK_ECP_CNTL 0x0008 -#define pllHTOTAL_CNTL 0x0009 -#define pllM_SPLL_REF_FB_DIV 0x000A -#define pllAGP_PLL_CNTL 0x000B -#define pllSPLL_CNTL 0x000C -#define pllSCLK_CNTL 0x000D -#define pllMPLL_CNTL 0x000E -#define pllMDLL_CKO 0x000F -#define pllMDLL_RDCKA 0x0010 -#define pllMDLL_RDCKB 0x0011 -#define pllMCLK_CNTL 0x0012 -#define pllPLL_TEST_CNTL 0x0013 -#define pllCLK_PWRMGT_CNTL 0x0014 -#define pllPLL_PWRMGT_CNTL 0x0015 -#define pllCG_TEST_MACRO_RW_WRITE 0x0016 -#define pllCG_TEST_MACRO_RW_READ 0x0017 -#define pllCG_TEST_MACRO_RW_DATA 0x0018 -#define pllCG_TEST_MACRO_RW_CNTL 0x0019 -#define pllDISP_TEST_MACRO_RW_WRITE 0x001A -#define pllDISP_TEST_MACRO_RW_READ 0x001B -#define pllDISP_TEST_MACRO_RW_DATA 0x001C -#define pllDISP_TEST_MACRO_RW_CNTL 0x001D -#define pllSCLK_CNTL2 0x001E -#define pllMCLK_MISC 0x001F -#define pllTV_PLL_FINE_CNTL 0x0020 -#define pllTV_PLL_CNTL 0x0021 -#define pllTV_PLL_CNTL1 0x0022 -#define pllTV_DTO_INCREMENTS 0x0023 -#define pllSPLL_AUX_CNTL 0x0024 -#define pllMPLL_AUX_CNTL 0x0025 -#define pllP2PLL_CNTL 0x002A -#define pllP2PLL_REF_DIV 0x002B -#define pllP2PLL_DIV_0 0x002C -#define pllPIXCLKS_CNTL 0x002D -#define pllHTOTAL2_CNTL 0x002E -#define pllSSPLL_CNTL 0x0030 -#define pllSSPLL_REF_DIV 0x0031 -#define pllSSPLL_DIV_0 0x0032 -#define pllSS_INT_CNTL 0x0033 -#define pllSS_TST_CNTL 0x0034 -#define pllSCLK_MORE_CNTL 0x0035 - -#define ixMC_PERF_CNTL 0x0000 -#define ixMC_PERF_SEL 0x0001 -#define ixMC_PERF_REGION_0 0x0002 -#define ixMC_PERF_REGION_1 0x0003 -#define ixMC_PERF_COUNT_0 0x0004 -#define ixMC_PERF_COUNT_1 0x0005 -#define ixMC_PERF_COUNT_2 0x0006 -#define ixMC_PERF_COUNT_3 0x0007 -#define ixMC_PERF_COUNT_MEMCH_A 0x0008 -#define ixMC_PERF_COUNT_MEMCH_B 0x0009 -#define ixMC_IMP_CNTL 0x000A -#define ixMC_CHP_IO_CNTL_A0 0x000B -#define ixMC_CHP_IO_CNTL_A1 0x000C -#define ixMC_CHP_IO_CNTL_B0 0x000D -#define ixMC_CHP_IO_CNTL_B1 0x000E -#define ixMC_IMP_CNTL_0 0x000F -#define ixTC_MISMATCH_1 0x0010 -#define ixTC_MISMATCH_2 0x0011 -#define ixMC_BIST_CTRL 0x0012 -#define ixREG_COLLAR_WRITE 0x0013 -#define ixREG_COLLAR_READ 0x0014 -#define ixR300_MC_IMP_CNTL 0x0018 -#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 -#define ixR300_MC_CHP_IO_CNTL_A1 0x001a -#define ixR300_MC_CHP_IO_CNTL_B0 0x001b -#define ixR300_MC_CHP_IO_CNTL_B1 0x001c -#define ixR300_MC_CHP_IO_CNTL_C0 0x001d -#define ixR300_MC_CHP_IO_CNTL_C1 0x001e -#define ixR300_MC_CHP_IO_CNTL_D0 0x001f -#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 -#define ixR300_MC_IMP_CNTL_0 0x0021 -#define ixR300_MC_ELPIDA_CNTL 0x0022 -#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 -#define ixR300_MC_READ_CNTL_CD 0x0024 -#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 -#define ixR300_MC_DEBUG_CNTL 0x0026 -#define ixR300_MC_BIST_CNTL_0 0x0028 -#define ixR300_MC_BIST_CNTL_1 0x0029 -#define ixR300_MC_BIST_CNTL_2 0x002a -#define ixR300_MC_BIST_CNTL_3 0x002b -#define ixR300_MC_BIST_CNTL_4 0x002c -#define ixR300_MC_BIST_CNTL_5 0x002d -#define ixR300_MC_IMP_STATUS 0x002e -#define ixR300_MC_DLL_CNTL 0x002f -#define NB_TOM 0x15C - -#endif /* _RADEON_H */ diff --git a/include/smem.h b/include/smem.h index 598799d3a0cf89d75dc73e3dd339bc1ab8b204d7..83da9e177e2e660498da61f8dfdefcd256d91975 100644 --- a/include/smem.h +++ b/include/smem.h @@ -88,4 +88,3 @@ void *smem_get(struct udevice *dev, unsigned int host, unsigned int item, size_t int smem_get_free_space(struct udevice *dev, unsigned int host); #endif /* _smem_h_ */ - diff --git a/include/st_logo_data.h b/include/st_logo_data.h index d8d1fd3b035f311b2baaceaa92749320376ad1e9..b53fa1c38b19c9dca83a2621944e1496315fdcb4 100644 --- a/include/st_logo_data.h +++ b/include/st_logo_data.h @@ -3263,4 +3263,3 @@ unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = { 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x01 }; - diff --git a/include/stdio.h b/include/stdio.h index 039f7df6892ff93af753275d1593f6c69390c09d..1939a48f0fb61fc5b86a1c806e6e5b0801b22c95 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -10,9 +10,9 @@ int tstc(void); /* stdout */ #if !defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \ + (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL)) || \ (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \ - defined(CONFIG_SPL_SERIAL_SUPPORT)) + defined(CONFIG_SPL_SERIAL)) void putc(const char c); void puts(const char *s); int __printf(1, 2) printf(const char *fmt, ...); diff --git a/include/test/ut.h b/include/test/ut.h index 656e25fe57406dd97e811863679a9217f28abfe5..fb2e5fcff2c3dc7b13c9410834f6aa3c91369dd6 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -82,6 +82,21 @@ int ut_check_console_linen(struct unit_test_state *uts, const char *fmt, ...) */ int ut_check_skipline(struct unit_test_state *uts); +/** + * ut_check_skip_to_line() - skip output until a line is found + * + * This creates a string and then checks it against the following lines of + * console output obtained with console_record_readline() until it is found. + * + * After the function returns, uts->expect_str holds the expected string and + * uts->actual_str holds the actual string read from the console. + * + * @uts: Test state + * @fmt: printf() format string to look for, followed by args + * @return 0 if OK, -ENOENT if not found, other value on error + */ +int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...); + /** * ut_check_console_end() - Check there is no more console output * @@ -286,6 +301,15 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes); return CMD_RET_FAILURE; \ } \ +/* Assert that a following console output line matches */ +#define ut_assert_skip_to_line(fmt, args...) \ + if (ut_check_skip_to_line(uts, fmt, ##args)) { \ + ut_failf(uts, __FILE__, __LINE__, __func__, \ + "console", "\nExpected '%s',\n got to '%s'", \ + uts->expect_str, uts->actual_str); \ + return CMD_RET_FAILURE; \ + } \ + /* Assert that there is no more console output */ #define ut_assert_console_end() \ if (ut_check_console_end(uts)) { \ diff --git a/include/tsec.h b/include/tsec.h index 5433cfd96610472c3927d4183e972e2c76c58044..c301c28d3d51f92f94f1331505e9e2e057a1583e 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -25,7 +25,7 @@ #define TSEC_SIZE 0x40000 #define TSEC_MDIO_OFFSET 0x40000 #else -#define TSEC_SIZE 0x01000 +#define TSEC_SIZE 0x01000 #define TSEC_MDIO_OFFSET 0x01000 #endif diff --git a/include/u-boot/hash.h b/include/u-boot/hash.h new file mode 100644 index 0000000000000000000000000000000000000000..f9d47a99a77de1213e11fa7b899a05d81fd6463c --- /dev/null +++ b/include/u-boot/hash.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 ASPEED Technology Inc. + */ +#ifndef _UBOOT_HASH_H +#define _UBOOT_HASH_H + +enum HASH_ALGO { + HASH_ALGO_CRC16_CCITT, + HASH_ALGO_CRC32, + HASH_ALGO_MD5, + HASH_ALGO_SHA1, + HASH_ALGO_SHA256, + HASH_ALGO_SHA384, + HASH_ALGO_SHA512, + + HASH_ALGO_NUM, + + HASH_ALGO_INVALID = 0xffffffff, +}; + +/* general APIs for hash algo information */ +enum HASH_ALGO hash_algo_lookup_by_name(const char *name); +ssize_t hash_algo_digest_size(enum HASH_ALGO algo); +const char *hash_algo_name(enum HASH_ALGO algo); + +/* device-dependent APIs */ +int hash_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf); +int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz); +int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); +int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); +int hash_finish(struct udevice *dev, void *ctx, void *obuf); + +/* + * struct hash_ops - Driver model for Hash operations + * + * The uclass interface is implemented by all hash devices + * which use driver model. + */ +struct hash_ops { + /* progressive operations */ + int (*hash_init)(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); + int (*hash_update)(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); + int (*hash_finish)(struct udevice *dev, void *ctx, void *obuf); + + /* all-in-one operation */ + int (*hash_digest)(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf); + + /* all-in-one operation with watchdog triggering every chunk_sz */ + int (*hash_digest_wd)(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz); +}; + +#endif diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index 6d48592aa64d27ad6cf1c0ffd41aa7654b5dfd54..d61364c0ae3e64e0d7934d0e5d1d90fe2b0e8795 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -19,6 +19,10 @@ struct MD5Context { }; }; +void MD5Init(struct MD5Context *ctx); +void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *ctx); + /* * Calculate and store in 'output' the MD5 digest of 'len' bytes at * 'input'. 'output' must have enough space to hold 16 bytes. diff --git a/include/version.h b/include/version.h index 2d24451569d551de337cbde956d388c6a598ff9e..5955b21e89043a342ed139dc0bf13bfd08debbd1 100644 --- a/include/version.h +++ b/include/version.h @@ -7,16 +7,8 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#include <timestamp.h> - #ifndef DO_DEPS_ONLY #include "generated/version_autogenerated.h" #endif -#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING - -#ifndef __ASSEMBLY__ -extern const char version_string[]; -#endif /* __ASSEMBLY__ */ #endif /* __VERSION_H__ */ diff --git a/include/version_string.h b/include/version_string.h new file mode 100644 index 0000000000000000000000000000000000000000..a89a6e43705e4e2cd3abce3002279aaa91b205de --- /dev/null +++ b/include/version_string.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __VERSION_STRING_H__ +#define __VERSION_STRING_H__ + +extern const char version_string[]; + +#endif /* __VERSION_STRING_H__ */ diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h index 64c5ed2eda41ef793c1840b4a2de432a211ffc65..c7e6351b64c03bd21bdaeedc6a3170afdfc9a420 100644 --- a/include/video_font_4x6.h +++ b/include/video_font_4x6.h @@ -49,7 +49,7 @@ __END__; static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { /*{*/ - /* Char 0: ' ' */ + /* Char 0: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -58,7 +58,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 1: ' ' */ + /* Char 1: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -67,7 +67,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 2: ' ' */ + /* Char 2: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -76,7 +76,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 3: ' ' */ + /* Char 3: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -85,7 +85,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 4: ' ' */ + /* Char 4: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -94,7 +94,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 5: ' ' */ + /* Char 5: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -103,7 +103,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 6: ' ' */ + /* Char 6: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -112,7 +112,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 7: ' ' */ + /* Char 7: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -121,7 +121,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 8: ' ' */ + /* Char 8: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -130,7 +130,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 9: ' ' */ + /* Char 9: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -139,7 +139,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 10: '' */ + /* Char 10: '' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -148,7 +148,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 11: ' ' */ + /* Char 11: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -157,7 +157,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 12: ' ' */ + /* Char 12: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -166,7 +166,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 13: ' ' */ + /* Char 13: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -175,7 +175,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 14: ' ' */ + /* Char 14: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -184,7 +184,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 15: ' ' */ + /* Char 15: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -193,7 +193,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 16: ' ' */ + /* Char 16: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -202,7 +202,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 17: ' ' */ + /* Char 17: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -211,7 +211,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 18: ' ' */ + /* Char 18: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -220,7 +220,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 19: ' ' */ + /* Char 19: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -229,7 +229,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 20: ' ' */ + /* Char 20: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -238,7 +238,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 21: ' ' */ + /* Char 21: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -247,7 +247,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 22: ' ' */ + /* Char 22: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -256,7 +256,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 23: ' ' */ + /* Char 23: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -265,7 +265,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 24: ' ' */ + /* Char 24: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -274,7 +274,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 25: ' ' */ + /* Char 25: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -283,7 +283,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 26: ' ' */ + /* Char 26: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -292,7 +292,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 27: ' ' */ + /* Char 27: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -301,7 +301,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 28: ' ' */ + /* Char 28: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -310,7 +310,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 29: ' ' */ + /* Char 29: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -319,7 +319,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 30: ' ' */ + /* Char 30: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -328,7 +328,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 31: ' ' */ + /* Char 31: ' ' */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -337,7 +337,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 32: ' ' */ + /* Char 32: ' ' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ @@ -346,7 +346,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 33: '!' */ + /* Char 33: '!' */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -355,7 +355,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 34: '"' */ + /* Char 34: '"' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ @@ -364,7 +364,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 35: '#' */ + /* Char 35: '#' */ 0xaa, /*= [* * ] */ 0xff, /*= [****] */ 0xff, /*= [****] */ @@ -373,7 +373,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 36: '$' */ + /* Char 36: '$' */ 0x44, /*= [ * ] */ 0x66, /*= [ ** ] */ 0xee, /*= [*** ] */ @@ -382,7 +382,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 37: '%' */ + /* Char 37: '%' */ 0xaa, /*= [* * ] */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -391,7 +391,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 38: '&' */ + /* Char 38: '&' */ 0x66, /*= [ ** ] */ 0x99, /*= [* *] */ 0x66, /*= [ ** ] */ @@ -400,7 +400,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 39: ''' */ + /* Char 39: ''' */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ 0x00, /*= [ ] */ @@ -409,7 +409,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 40: '(' */ + /* Char 40: '(' */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -418,7 +418,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 41: ')' */ + /* Char 41: ')' */ 0x44, /*= [ * ] */ 0x22, /*= [ * ] */ 0x22, /*= [ * ] */ @@ -427,7 +427,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 42: '*' */ + /* Char 42: '*' */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -436,7 +436,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 43: '+' */ + /* Char 43: '+' */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ 0xee, /*= [*** ] */ @@ -445,7 +445,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 44: ',' */ + /* Char 44: ',' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ @@ -454,7 +454,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 45: '-' */ + /* Char 45: '-' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ @@ -463,7 +463,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 46: '.' */ + /* Char 46: '.' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ @@ -472,7 +472,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 47: '/' */ + /* Char 47: '/' */ 0x00, /*= [ ] */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -481,7 +481,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 48: '0' */ + /* Char 48: '0' */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -490,7 +490,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 49: '1' */ + /* Char 49: '1' */ 0x44, /*= [ * ] */ 0xcc, /*= [** ] */ 0x44, /*= [ * ] */ @@ -499,7 +499,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 50: '2' */ + /* Char 50: '2' */ 0xcc, /*= [** ] */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -508,7 +508,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ /*}*/ /*{*/ - /* Char 51: '3' */ + /* Char 51: '3' */ 0xee, /*= [*** ] */ 0x22, /*= [ * ] */ 0x66, /*= [ ** ] */ @@ -516,7 +516,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 52: '4' */ + /*{*/ /* Char 52: '4' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -524,7 +524,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x22, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 53: '5' */ + /*{*/ /* Char 53: '5' */ 0xee, /*= [*** ] */ 0x88, /*= [* ] */ 0xee, /*= [*** ] */ @@ -532,7 +532,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 54: '6' */ + /*{*/ /* Char 54: '6' */ 0xee, /*= [*** ] */ 0x88, /*= [* ] */ 0xee, /*= [*** ] */ @@ -540,7 +540,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 55: '7' */ + /*{*/ /* Char 55: '7' */ 0xee, /*= [*** ] */ 0x22, /*= [ * ] */ 0x22, /*= [ * ] */ @@ -548,7 +548,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x22, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 56: '8' */ + /*{*/ /* Char 56: '8' */ 0xee, /*= [*** ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -556,7 +556,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 57: '9' */ + /*{*/ /* Char 57: '9' */ 0xee, /*= [*** ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -564,7 +564,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x22, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 58: ':' */ + /*{*/ /* Char 58: ':' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ @@ -572,7 +572,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 59: ';' */ + /*{*/ /* Char 59: ';' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ @@ -580,7 +580,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x88, /*= [* ] */ /*}*/ - /*{*/ /* Char 60: '<' */ + /*{*/ /* Char 60: '<' */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ 0x88, /*= [* ] */ @@ -588,7 +588,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x22, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 61: '=' */ + /*{*/ /* Char 61: '=' */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ 0x00, /*= [ ] */ @@ -596,7 +596,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 62: '>' */ + /*{*/ /* Char 62: '>' */ 0x88, /*= [* ] */ 0x44, /*= [ * ] */ 0x22, /*= [ * ] */ @@ -604,7 +604,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 63: '?' */ + /*{*/ /* Char 63: '?' */ 0xee, /*= [*** ] */ 0x22, /*= [ * ] */ 0x66, /*= [ ** ] */ @@ -612,7 +612,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 64: '@' */ + /*{*/ /* Char 64: '@' */ 0x44, /*= [ * ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -620,7 +620,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 65: 'A' */ + /*{*/ /* Char 65: 'A' */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -628,7 +628,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 66: 'B' */ + /*{*/ /* Char 66: 'B' */ 0xcc, /*= [** ] */ 0xaa, /*= [* * ] */ 0xcc, /*= [** ] */ @@ -636,7 +636,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 67: 'C' */ + /*{*/ /* Char 67: 'C' */ 0x66, /*= [ ** ] */ 0x88, /*= [* ] */ 0x88, /*= [* ] */ @@ -644,7 +644,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 68: 'D' */ + /*{*/ /* Char 68: 'D' */ 0xcc, /*= [** ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -652,7 +652,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 69: 'E' */ + /*{*/ /* Char 69: 'E' */ 0xee, /*= [*** ] */ 0x88, /*= [* ] */ 0xee, /*= [*** ] */ @@ -660,7 +660,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 70: 'F' */ + /*{*/ /* Char 70: 'F' */ 0xee, /*= [*** ] */ 0x88, /*= [* ] */ 0xee, /*= [*** ] */ @@ -668,7 +668,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 71: 'G' */ + /*{*/ /* Char 71: 'G' */ 0x66, /*= [ ** ] */ 0x88, /*= [* ] */ 0xee, /*= [*** ] */ @@ -676,7 +676,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 72: 'H' */ + /*{*/ /* Char 72: 'H' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -684,7 +684,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 73: 'I' */ + /*{*/ /* Char 73: 'I' */ 0xee, /*= [*** ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -692,7 +692,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 74: 'J' */ + /*{*/ /* Char 74: 'J' */ 0x22, /*= [ * ] */ 0x22, /*= [ * ] */ 0x22, /*= [ * ] */ @@ -700,7 +700,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 75: 'K' */ + /*{*/ /* Char 75: 'K' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0xcc, /*= [** ] */ @@ -708,7 +708,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 76: 'L' */ + /*{*/ /* Char 76: 'L' */ 0x88, /*= [* ] */ 0x88, /*= [* ] */ 0x88, /*= [* ] */ @@ -716,7 +716,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 77: 'M' */ + /*{*/ /* Char 77: 'M' */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -724,7 +724,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 78: 'N' */ + /*{*/ /* Char 78: 'N' */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -732,7 +732,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 79: 'O' */ + /*{*/ /* Char 79: 'O' */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -740,7 +740,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 80: 'P' */ + /*{*/ /* Char 80: 'P' */ 0xcc, /*= [** ] */ 0xaa, /*= [* * ] */ 0xcc, /*= [** ] */ @@ -748,7 +748,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 81: 'Q' */ + /*{*/ /* Char 81: 'Q' */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -756,7 +756,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 82: 'R' */ + /*{*/ /* Char 82: 'R' */ 0xcc, /*= [** ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -764,7 +764,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 83: 'S' */ + /*{*/ /* Char 83: 'S' */ 0x66, /*= [ ** ] */ 0x88, /*= [* ] */ 0x44, /*= [ * ] */ @@ -772,7 +772,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 84: 'T' */ + /*{*/ /* Char 84: 'T' */ 0xee, /*= [*** ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -780,7 +780,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 85: 'U' */ + /*{*/ /* Char 85: 'U' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -788,7 +788,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 86: 'V' */ + /*{*/ /* Char 86: 'V' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -796,7 +796,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 87: 'W' */ + /*{*/ /* Char 87: 'W' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0xee, /*= [*** ] */ @@ -804,7 +804,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 88: 'X' */ + /*{*/ /* Char 88: 'X' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0x44, /*= [ * ] */ @@ -812,7 +812,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 89: 'Y' */ + /*{*/ /* Char 89: 'Y' */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ 0x44, /*= [ * ] */ @@ -820,7 +820,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 90: 'Z' */ + /*{*/ /* Char 90: 'Z' */ 0xee, /*= [*** ] */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -828,7 +828,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 91: '[' */ + /*{*/ /* Char 91: '[' */ 0x66, /*= [ ** ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -836,7 +836,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 92: '\' */ + /*{*/ /* Char 92: '\' */ 0x00, /*= [ ] */ 0x88, /*= [* ] */ 0x44, /*= [ * ] */ @@ -844,7 +844,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 93: ']' */ + /*{*/ /* Char 93: ']' */ 0x66, /*= [ ** ] */ 0x22, /*= [ * ] */ 0x22, /*= [ * ] */ @@ -852,7 +852,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 94: '^' */ + /*{*/ /* Char 94: '^' */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ @@ -860,7 +860,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 95: '_' */ + /*{*/ /* Char 95: '_' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ @@ -868,7 +868,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0xff, /*= [****] */ /*}*/ - /*{*/ /* Char 96: '`' */ + /*{*/ /* Char 96: '`' */ 0x88, /*= [* ] */ 0x44, /*= [ * ] */ 0x00, /*= [ ] */ @@ -876,7 +876,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 97: 'a' */ + /*{*/ /* Char 97: 'a' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ @@ -884,7 +884,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 98: 'b' */ + /*{*/ /* Char 98: 'b' */ 0x88, /*= [* ] */ 0x88, /*= [* ] */ 0xcc, /*= [** ] */ @@ -892,7 +892,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 99: 'c' */ + /*{*/ /* Char 99: 'c' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ @@ -900,7 +900,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 100: 'd' */ + /*{*/ /* Char 100: 'd' */ 0x22, /*= [ * ] */ 0x22, /*= [ * ] */ 0x66, /*= [ ** ] */ @@ -908,7 +908,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 101: 'e' */ + /*{*/ /* Char 101: 'e' */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -916,7 +916,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 102: 'f' */ + /*{*/ /* Char 102: 'f' */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ 0xee, /*= [*** ] */ @@ -924,7 +924,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 103: 'g' */ + /*{*/ /* Char 103: 'g' */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ 0xaa, /*= [* * ] */ @@ -932,7 +932,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 104: 'h' */ + /*{*/ /* Char 104: 'h' */ 0x88, /*= [* ] */ 0x88, /*= [* ] */ 0xcc, /*= [** ] */ @@ -940,7 +940,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 105: 'i' */ + /*{*/ /* Char 105: 'i' */ 0x44, /*= [ * ] */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ @@ -948,7 +948,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 106: 'j' */ + /*{*/ /* Char 106: 'j' */ 0x44, /*= [ * ] */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ @@ -956,7 +956,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 107: 'k' */ + /*{*/ /* Char 107: 'k' */ 0x00, /*= [ ] */ 0x88, /*= [* ] */ 0xaa, /*= [* * ] */ @@ -964,7 +964,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 108: 'l' */ + /*{*/ /* Char 108: 'l' */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ 0x44, /*= [ * ] */ @@ -972,7 +972,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 109: 'm' */ + /*{*/ /* Char 109: 'm' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ @@ -980,7 +980,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 110: 'n' */ + /*{*/ /* Char 110: 'n' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ @@ -988,7 +988,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 111: 'o' */ + /*{*/ /* Char 111: 'o' */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ @@ -996,7 +996,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 112: 'p' */ + /*{*/ /* Char 112: 'p' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ @@ -1004,7 +1004,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0x88, /*= [* ] */ /*}*/ - /*{*/ /* Char 113: 'q' */ + /*{*/ /* Char 113: 'q' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ @@ -1012,7 +1012,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x22, /*= [ * ] */ /*}*/ - /*{*/ /* Char 114: 'r' */ + /*{*/ /* Char 114: 'r' */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ 0xaa, /*= [* * ] */ @@ -1020,7 +1020,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 115: 's' */ + /*{*/ /* Char 115: 's' */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ 0xcc, /*= [** ] */ @@ -1028,7 +1028,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 116: 't' */ + /*{*/ /* Char 116: 't' */ 0x00, /*= [ ] */ 0x44, /*= [ * ] */ 0xee, /*= [*** ] */ @@ -1036,7 +1036,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 117: 'u' */ + /*{*/ /* Char 117: 'u' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xaa, /*= [* * ] */ @@ -1044,7 +1044,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 118: 'v' */ + /*{*/ /* Char 118: 'v' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xaa, /*= [* * ] */ @@ -1052,7 +1052,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 119: 'w' */ + /*{*/ /* Char 119: 'w' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xaa, /*= [* * ] */ @@ -1060,7 +1060,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 120: 'x' */ + /*{*/ /* Char 120: 'x' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xaa, /*= [* * ] */ @@ -1068,7 +1068,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 121: 'y' */ + /*{*/ /* Char 121: 'y' */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xaa, /*= [* * ] */ @@ -1076,7 +1076,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x22, /*= [ * ] */ 0xcc, /*= [** ] */ /*}*/ - /*{*/ /* Char 122: 'z' */ + /*{*/ /* Char 122: 'z' */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ 0x66, /*= [ ** ] */ @@ -1084,7 +1084,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 123: '{' */ + /*{*/ /* Char 123: '{' */ 0x22, /*= [ * ] */ 0x44, /*= [ * ] */ 0xcc, /*= [** ] */ @@ -1092,7 +1092,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x22, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 124: '|' */ + /*{*/ /* Char 124: '|' */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -1100,7 +1100,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 125: '}' */ + /*{*/ /* Char 125: '}' */ 0x88, /*= [* ] */ 0x44, /*= [ * ] */ 0x66, /*= [ ** ] */ @@ -1108,7 +1108,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 126: '~' */ + /*{*/ /* Char 126: '~' */ 0x55, /*= [ * *] */ 0xaa, /*= [* * ] */ 0x00, /*= [ ] */ @@ -1116,7 +1116,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 127: '' */ + /*{*/ /* Char 127: '' */ 0x44, /*= [ * ] */ 0xaa, /*= [* * ] */ 0xaa, /*= [* * ] */ @@ -1124,7 +1124,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 128: */ + /*{*/ /* Char 128: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1132,7 +1132,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 129: */ + /*{*/ /* Char 129: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1140,7 +1140,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 130: */ + /*{*/ /* Char 130: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1148,7 +1148,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 131: */ + /*{*/ /* Char 131: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1156,7 +1156,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 132: */ + /*{*/ /* Char 132: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1164,7 +1164,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 133: */ + /*{*/ /* Char 133: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1172,7 +1172,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 134: */ + /*{*/ /* Char 134: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1180,7 +1180,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 135: */ + /*{*/ /* Char 135: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1188,7 +1188,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 136: */ + /*{*/ /* Char 136: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1196,7 +1196,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 137: */ + /*{*/ /* Char 137: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1204,7 +1204,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 138: */ + /*{*/ /* Char 138: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1212,7 +1212,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 139: */ + /*{*/ /* Char 139: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1220,7 +1220,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 140: */ + /*{*/ /* Char 140: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1228,7 +1228,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 141: */ + /*{*/ /* Char 141: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1236,7 +1236,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 142: */ + /*{*/ /* Char 142: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1244,7 +1244,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 143: */ + /*{*/ /* Char 143: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1252,7 +1252,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 144: */ + /*{*/ /* Char 144: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1260,7 +1260,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 145: */ + /*{*/ /* Char 145: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1268,7 +1268,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 146: */ + /*{*/ /* Char 146: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1276,7 +1276,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 147: */ + /*{*/ /* Char 147: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1284,7 +1284,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 148: */ + /*{*/ /* Char 148: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1292,7 +1292,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 149: */ + /*{*/ /* Char 149: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1300,7 +1300,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 150: */ + /*{*/ /* Char 150: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1308,7 +1308,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 151: */ + /*{*/ /* Char 151: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1316,7 +1316,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 152: */ + /*{*/ /* Char 152: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1324,7 +1324,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 153: */ + /*{*/ /* Char 153: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1332,7 +1332,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 154: */ + /*{*/ /* Char 154: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1340,7 +1340,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 155: */ + /*{*/ /* Char 155: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1348,7 +1348,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 156: */ + /*{*/ /* Char 156: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1356,7 +1356,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 157: */ + /*{*/ /* Char 157: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1364,7 +1364,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 158: */ + /*{*/ /* Char 158: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1372,7 +1372,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 159: */ + /*{*/ /* Char 159: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1380,7 +1380,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 160: */ + /*{*/ /* Char 160: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1388,7 +1388,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 161: */ + /*{*/ /* Char 161: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1396,7 +1396,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 162: */ + /*{*/ /* Char 162: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1404,7 +1404,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 163: */ + /*{*/ /* Char 163: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1412,7 +1412,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 164: */ + /*{*/ /* Char 164: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1420,7 +1420,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 165: */ + /*{*/ /* Char 165: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1428,7 +1428,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 166: */ + /*{*/ /* Char 166: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1436,7 +1436,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 167: */ + /*{*/ /* Char 167: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1444,7 +1444,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 168: */ + /*{*/ /* Char 168: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1452,7 +1452,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 169: */ + /*{*/ /* Char 169: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1460,7 +1460,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 170: */ + /*{*/ /* Char 170: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1468,7 +1468,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 171: */ + /*{*/ /* Char 171: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1476,7 +1476,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 172: */ + /*{*/ /* Char 172: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1484,7 +1484,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 173: */ + /*{*/ /* Char 173: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1492,7 +1492,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 174: */ + /*{*/ /* Char 174: */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ 0xcc, /*= [** ] */ @@ -1500,7 +1500,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 175: */ + /*{*/ /* Char 175: */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ 0x66, /*= [ ** ] */ @@ -1508,7 +1508,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 176: */ + /*{*/ /* Char 176: */ 0x88, /*= [* ] */ 0x22, /*= [ * ] */ 0x88, /*= [* ] */ @@ -1516,7 +1516,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x88, /*= [* ] */ 0x22, /*= [ * ] */ /*}*/ - /*{*/ /* Char 177: */ + /*{*/ /* Char 177: */ 0xaa, /*= [* * ] */ 0x55, /*= [ * *] */ 0xaa, /*= [* * ] */ @@ -1524,7 +1524,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xaa, /*= [* * ] */ 0x55, /*= [ * *] */ /*}*/ - /*{*/ /* Char 178: */ + /*{*/ /* Char 178: */ 0xdd, /*= [** *] */ 0xbb, /*= [* **] */ 0xdd, /*= [** *] */ @@ -1532,7 +1532,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xdd, /*= [** *] */ 0xbb, /*= [* **] */ /*}*/ - /*{*/ /* Char 179: */ + /*{*/ /* Char 179: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ @@ -1540,7 +1540,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 180: */ + /*{*/ /* Char 180: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xcc, /*= [** ] */ @@ -1548,7 +1548,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 181: */ + /*{*/ /* Char 181: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xcc, /*= [** ] */ @@ -1556,7 +1556,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 182: */ + /*{*/ /* Char 182: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xee, /*= [*** ] */ @@ -1564,7 +1564,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 183: */ + /*{*/ /* Char 183: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ @@ -1572,7 +1572,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 184: */ + /*{*/ /* Char 184: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ @@ -1580,7 +1580,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 185: */ + /*{*/ /* Char 185: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xee, /*= [*** ] */ @@ -1588,7 +1588,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 186: */ + /*{*/ /* Char 186: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ @@ -1596,7 +1596,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 187: */ + /*{*/ /* Char 187: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xee, /*= [*** ] */ @@ -1604,7 +1604,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 188: */ + /*{*/ /* Char 188: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xee, /*= [*** ] */ @@ -1612,7 +1612,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 189: */ + /*{*/ /* Char 189: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xee, /*= [*** ] */ @@ -1620,7 +1620,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 190: */ + /*{*/ /* Char 190: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xcc, /*= [** ] */ @@ -1628,7 +1628,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 191: */ + /*{*/ /* Char 191: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xcc, /*= [** ] */ @@ -1636,7 +1636,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 192: */ + /*{*/ /* Char 192: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x77, /*= [ ***] */ @@ -1644,7 +1644,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 193: */ + /*{*/ /* Char 193: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xff, /*= [****] */ @@ -1652,7 +1652,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 194: */ + /*{*/ /* Char 194: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xff, /*= [****] */ @@ -1660,7 +1660,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 195: */ + /*{*/ /* Char 195: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x77, /*= [ ***] */ @@ -1668,7 +1668,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 196: */ + /*{*/ /* Char 196: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xff, /*= [****] */ @@ -1676,7 +1676,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 197: */ + /*{*/ /* Char 197: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xff, /*= [****] */ @@ -1684,7 +1684,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 198: */ + /*{*/ /* Char 198: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x77, /*= [ ***] */ @@ -1692,7 +1692,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 199: */ + /*{*/ /* Char 199: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0x77, /*= [ ***] */ @@ -1700,7 +1700,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 200: */ + /*{*/ /* Char 200: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0x77, /*= [ ***] */ @@ -1708,7 +1708,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 201: */ + /*{*/ /* Char 201: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x77, /*= [ ***] */ @@ -1716,7 +1716,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 202: */ + /*{*/ /* Char 202: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xff, /*= [****] */ @@ -1724,7 +1724,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 203: */ + /*{*/ /* Char 203: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xff, /*= [****] */ @@ -1732,7 +1732,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 204: */ + /*{*/ /* Char 204: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0x77, /*= [ ***] */ @@ -1740,7 +1740,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 205: */ + /*{*/ /* Char 205: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xff, /*= [****] */ @@ -1748,7 +1748,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 206: */ + /*{*/ /* Char 206: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xff, /*= [****] */ @@ -1756,7 +1756,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 207: */ + /*{*/ /* Char 207: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xff, /*= [****] */ @@ -1764,7 +1764,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 208: */ + /*{*/ /* Char 208: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xff, /*= [****] */ @@ -1772,7 +1772,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 209: */ + /*{*/ /* Char 209: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xff, /*= [****] */ @@ -1780,7 +1780,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 210: */ + /*{*/ /* Char 210: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0xff, /*= [****] */ @@ -1788,7 +1788,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 211: */ + /*{*/ /* Char 211: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0x77, /*= [ ***] */ @@ -1796,7 +1796,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 212: */ + /*{*/ /* Char 212: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0x77, /*= [ ***] */ @@ -1804,7 +1804,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 213: */ + /*{*/ /* Char 213: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x77, /*= [ ***] */ @@ -1812,7 +1812,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 214: */ + /*{*/ /* Char 214: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x77, /*= [ ***] */ @@ -1820,7 +1820,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 215: */ + /*{*/ /* Char 215: */ 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ 0xff, /*= [****] */ @@ -1828,7 +1828,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x66, /*= [ ** ] */ 0x66, /*= [ ** ] */ /*}*/ - /*{*/ /* Char 216: */ + /*{*/ /* Char 216: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xff, /*= [****] */ @@ -1836,7 +1836,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 217: */ + /*{*/ /* Char 217: */ 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ 0xcc, /*= [** ] */ @@ -1844,7 +1844,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 218: */ + /*{*/ /* Char 218: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x77, /*= [ ***] */ @@ -1852,7 +1852,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x44, /*= [ * ] */ 0x44, /*= [ * ] */ /*}*/ - /*{*/ /* Char 219: */ + /*{*/ /* Char 219: */ 0xff, /*= [****] */ 0xff, /*= [****] */ 0xff, /*= [****] */ @@ -1860,7 +1860,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xff, /*= [****] */ 0xff, /*= [****] */ /*}*/ - /*{*/ /* Char 220: */ + /*{*/ /* Char 220: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ @@ -1868,7 +1868,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xff, /*= [****] */ 0xff, /*= [****] */ /*}*/ - /*{*/ /* Char 221: */ + /*{*/ /* Char 221: */ 0xcc, /*= [** ] */ 0xcc, /*= [** ] */ 0xcc, /*= [** ] */ @@ -1876,7 +1876,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xcc, /*= [** ] */ 0xcc, /*= [** ] */ /*}*/ - /*{*/ /* Char 222: */ + /*{*/ /* Char 222: */ 0x33, /*= [ **] */ 0x33, /*= [ **] */ 0x33, /*= [ **] */ @@ -1884,7 +1884,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x33, /*= [ **] */ 0x33, /*= [ **] */ /*}*/ - /*{*/ /* Char 223: */ + /*{*/ /* Char 223: */ 0xff, /*= [****] */ 0xff, /*= [****] */ 0xff, /*= [****] */ @@ -1892,7 +1892,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 224: */ + /*{*/ /* Char 224: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1900,7 +1900,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 225: */ + /*{*/ /* Char 225: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1908,7 +1908,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 226: */ + /*{*/ /* Char 226: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1916,7 +1916,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 227: */ + /*{*/ /* Char 227: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1924,7 +1924,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 228: */ + /*{*/ /* Char 228: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1932,7 +1932,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 229: */ + /*{*/ /* Char 229: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1940,7 +1940,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 230: */ + /*{*/ /* Char 230: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1948,7 +1948,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 231: */ + /*{*/ /* Char 231: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1956,7 +1956,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 232: */ + /*{*/ /* Char 232: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1964,7 +1964,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 233: */ + /*{*/ /* Char 233: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1972,7 +1972,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 234: */ + /*{*/ /* Char 234: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1980,7 +1980,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 235: */ + /*{*/ /* Char 235: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1988,7 +1988,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 236: */ + /*{*/ /* Char 236: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -1996,7 +1996,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 237: */ + /*{*/ /* Char 237: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2004,7 +2004,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 238: */ + /*{*/ /* Char 238: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2012,7 +2012,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 239: */ + /*{*/ /* Char 239: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2020,7 +2020,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 240: */ + /*{*/ /* Char 240: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2028,7 +2028,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 241: */ + /*{*/ /* Char 241: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2036,7 +2036,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 242: */ + /*{*/ /* Char 242: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2044,7 +2044,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 243: */ + /*{*/ /* Char 243: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2052,7 +2052,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 244: */ + /*{*/ /* Char 244: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2060,7 +2060,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 245: */ + /*{*/ /* Char 245: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2068,7 +2068,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 246: */ + /*{*/ /* Char 246: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2076,7 +2076,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 247: */ + /*{*/ /* Char 247: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2084,7 +2084,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 248: */ + /*{*/ /* Char 248: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2092,7 +2092,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 249: */ + /*{*/ /* Char 249: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2100,7 +2100,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 250: */ + /*{*/ /* Char 250: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2108,7 +2108,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 251: */ + /*{*/ /* Char 251: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2116,7 +2116,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 252: */ + /*{*/ /* Char 252: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2124,7 +2124,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 253: */ + /*{*/ /* Char 253: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ @@ -2132,7 +2132,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0xee, /*= [*** ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 254: */ + /*{*/ /* Char 254: */ 0x00, /*= [ ] */ 0x00, /*= [ ] */ 0x66, /*= [ ** ] */ @@ -2140,7 +2140,7 @@ static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { 0x00, /*= [ ] */ 0x00, /*= [ ] */ /*}*/ - /*{*/ /* Char 255: */ + /*{*/ /* Char 255: */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ 0xee, /*= [*** ] */ diff --git a/include/wdt.h b/include/wdt.h index bc242c2eb26d49e0e883f19a986daec4251ea9a1..baaa9db08a004933e44bd62967d145df61dff8df 100644 --- a/include/wdt.h +++ b/include/wdt.h @@ -37,6 +37,14 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags); */ int wdt_stop(struct udevice *dev); +/* + * Stop all registered watchdog devices. + * + * @return: 0 if ok, first error encountered otherwise (but wdt_stop() + * is still called on following devices) + */ +int wdt_stop_all(void); + /* * Reset the timer, typically restoring the counter to * the value configured by start() diff --git a/lib/Kconfig b/lib/Kconfig index 130fa0630ac39a12dff0e000fb2fb0766e6b5b9f..034af724b5db5b243d0eab7964c594b280a43cb3 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -92,7 +92,6 @@ config TPL_SPRINTF config SSCANF bool - default n config STRTO bool @@ -348,7 +347,6 @@ menu "Android Verified Boot" config LIBAVB bool "Android Verified Boot 2.0 support" depends on ANDROID_BOOT_IMAGE - default n help This enables support of Android Verified Boot 2.0 which can be used to assure the end user of the integrity of the software running on a @@ -769,7 +767,6 @@ endmenu config PHANDLE_CHECK_SEQ bool "Enable phandle check while getting sequence number" - default n help When there are multiple device tree nodes with same name, enable this config option to distinguish them using diff --git a/lib/Makefile b/lib/Makefile index 93be86c34a0195c2c0735d1bd6ebe81efd967f1c..09e380eb66c48395544bb387ca1a092e9154b060 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -80,14 +80,12 @@ obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o obj-$(CONFIG_LIBAVB) += libavb/ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ -ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) -obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o -obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o -endif +obj-$(CONFIG_$(SPL_TPL_)OF_REAL) += fdtdec_common.o fdtdec.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o obj-$(CONFIG_$(SPL_TPL_)HASH) += crc16.o +obj-$(CONFIG_MMC_SPI_CRC_ON) += crc16.o obj-y += net_utils.o endif obj-$(CONFIG_ADDR_MAP) += addr_map.o diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 2f07741784121cc638e52f10d329cc35d3802c32..7ea4b2e87eea0b0c7fd84f7d9fe2ecde5b886517 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -11,6 +11,7 @@ #include <log.h> #include <mapmem.h> #include <tables_csum.h> +#include <timestamp.h> #include <version.h> #include <acpi/acpi_table.h> #include <asm/global_data.h> diff --git a/lib/crc32.c b/lib/crc32.c index f2acc107fe4c102b63c612724545355308d606fd..5a3127e03adad2cb77449696452d11d283df5563 100644 --- a/lib/crc32.c +++ b/lib/crc32.c @@ -84,7 +84,7 @@ static void __efi_runtime make_crc_table(void) } crc_table_empty = 0; } -#else +#elif !defined(CONFIG_ARM64_CRC32) /* ======================================================================== * Table of CRC-32's of all single-byte values (made by make_crc_table) */ @@ -184,6 +184,12 @@ const uint32_t * ZEXPORT get_crc_table() */ uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len) { +#ifdef CONFIG_ARM64_CRC32 + crc = cpu_to_le32(crc); + while (len--) + crc = __builtin_aarch64_crc32b(crc, *buf++); + return le32_to_cpu(crc); +#else const uint32_t *tab = crc_table; const uint32_t *b =(const uint32_t *)buf; size_t rem_len; @@ -221,6 +227,7 @@ uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len) } return le32_to_cpu(crc); +#endif } #undef DO_CRC diff --git a/lib/display_options.c b/lib/display_options.c index 4da1f5244f3958d06aac045cd6b8e2e1b3d71e0f..360b01bcf5ffd62e2f821a7bf83478426171293a 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -8,7 +8,7 @@ #include <compiler.h> #include <console.h> #include <div64.h> -#include <version.h> +#include <version_string.h> #include <linux/ctype.h> #include <asm/io.h> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index f48d9e8b513d23202b4cc59f7fcd7afe68d1cd5e..3d5a5cd189e9a435938c152c1bf384d74151714e 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -39,7 +39,6 @@ config CMD_BOOTEFI_BOOTMGR config EFI_SETUP_EARLY bool - default n choice prompt "Store for non-volatile UEFI variables" @@ -113,7 +112,6 @@ config EFI_SET_TIME bool "SetTime() runtime service" depends on EFI_GET_TIME default y if ARCH_QEMU || SANDBOX - default n help Provide the SetTime() runtime service at boottime. This service can be used by an EFI application to adjust the real time clock. @@ -123,7 +121,6 @@ config EFI_HAVE_CAPSULE_SUPPORT config EFI_RUNTIME_UPDATE_CAPSULE bool "UpdateCapsule() runtime service" - default n select EFI_HAVE_CAPSULE_SUPPORT help Select this option if you want to use UpdateCapsule and @@ -132,7 +129,6 @@ config EFI_RUNTIME_UPDATE_CAPSULE config EFI_CAPSULE_ON_DISK bool "Enable capsule-on-disk support" select EFI_HAVE_CAPSULE_SUPPORT - default n help Select this option if you want to use capsule-on-disk feature, that is, capsules can be fetched and executed from files @@ -142,7 +138,6 @@ config EFI_CAPSULE_ON_DISK config EFI_IGNORE_OSINDICATIONS bool "Ignore OsIndications for CapsuleUpdate on-disk" depends on EFI_CAPSULE_ON_DISK - default n help There are boards where U-Boot does not support SetVariable at runtime. Select this option if you want to use the capsule-on-disk feature @@ -152,7 +147,6 @@ config EFI_IGNORE_OSINDICATIONS config EFI_CAPSULE_ON_DISK_EARLY bool "Initiate capsule-on-disk at U-Boot boottime" depends on EFI_CAPSULE_ON_DISK - default n select EFI_SETUP_EARLY help Normally, without this option enabled, capsules will be @@ -163,7 +157,6 @@ config EFI_CAPSULE_ON_DISK_EARLY config EFI_CAPSULE_FIRMWARE bool - default n config EFI_CAPSULE_FIRMWARE_MANAGEMENT bool "Capsule: Firmware Management Protocol" @@ -210,7 +203,6 @@ config EFI_CAPSULE_AUTHENTICATE select PKCS7_VERIFY select IMAGE_SIGN_INFO select EFI_SIGNATURE_SUPPORT - default n help Select this option if you want to enable capsule authentication @@ -271,7 +263,6 @@ endif config EFI_LOADER_BOUNCE_BUFFER bool "EFI Applications use bounce buffers for DMA operations" depends on ARM64 - default n help Some hardware does not support DMA to full 64bit addresses. For this hardware we can create a bounce buffer so that payloads don't have to @@ -357,7 +348,6 @@ config EFI_SECURE_BOOT select PKCS7_MESSAGE_PARSER select PKCS7_VERIFY select EFI_SIGNATURE_SUPPORT - default n help Select this option to enable EFI secure boot support. Once SecureBoot mode is enforced, any EFI binary can run only if diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index d3b8f93f14892afd9cc86becaa86c62be215d618..74f0bef23965c7b752c04c974d433336bf958b9a 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -14,7 +14,7 @@ #include <efi_tcg2.h> #include <log.h> #include <malloc.h> -#include <version.h> +#include <version_string.h> #include <tpm-v2.h> #include <u-boot/hash-checksum.h> #include <u-boot/sha1.h> @@ -1343,10 +1343,11 @@ out: */ static efi_status_t efi_append_scrtm_version(struct udevice *dev) { - u8 ver[] = U_BOOT_VERSION_STRING; efi_status_t ret; - ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION, sizeof(ver), ver); + ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION, + strlen(version_string) + 1, + (u8 *)version_string); return ret; } diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 7358cb6dd1684ccc562d945f72ba42e5880d991d..af92e65bde6dac3a3cf5ab9221ab6a6d316337b6 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -870,50 +870,6 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node, return cell; } -int fdtdec_get_config_int(const void *blob, const char *prop_name, - int default_val) -{ - int config_node; - - debug("%s: %s\n", __func__, prop_name); - config_node = fdt_path_offset(blob, "/config"); - if (config_node < 0) - return default_val; - return fdtdec_get_int(blob, config_node, prop_name, default_val); -} - -int fdtdec_get_config_bool(const void *blob, const char *prop_name) -{ - int config_node; - const void *prop; - - debug("%s: %s\n", __func__, prop_name); - config_node = fdt_path_offset(blob, "/config"); - if (config_node < 0) - return 0; - prop = fdt_get_property(blob, config_node, prop_name, NULL); - - return prop != NULL; -} - -char *fdtdec_get_config_string(const void *blob, const char *prop_name) -{ - const char *nodep; - int nodeoffset; - int len; - - debug("%s: %s\n", __func__, prop_name); - nodeoffset = fdt_path_offset(blob, "/config"); - if (nodeoffset < 0) - return NULL; - - nodep = fdt_getprop(blob, nodeoffset, prop_name, &len); - if (!nodep) - return NULL; - - return (char *)nodep; -} - u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells) { u64 number = 0; diff --git a/lib/hang.c b/lib/hang.c index 578ac78d45306f949d9ee237c27b17e164c5d317..2735774f9a4061c8252cc735ce66558c3ac5f4bc 100644 --- a/lib/hang.c +++ b/lib/hang.c @@ -24,7 +24,7 @@ void hang(void) { #if !defined(CONFIG_SPL_BUILD) || \ (CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \ - CONFIG_IS_ENABLED(SERIAL_SUPPORT)) + CONFIG_IS_ENABLED(SERIAL)) puts("### ERROR ### Please RESET the board ###\n"); #endif bootstage_error(BOOTSTAGE_ID_NEED_RESET); diff --git a/lib/lmb.c b/lib/lmb.c index 7bd1255f7a4c14cd8d0f6000c176b9151d98df0d..793647724c310ebb68dcb03ef847fa3004e00538 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -12,6 +12,10 @@ #include <log.h> #include <malloc.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + #define LMB_ALLOC_ANYWHERE 0 static void lmb_dump_region(struct lmb_region *rgn, char *name) @@ -113,6 +117,37 @@ void lmb_init(struct lmb *lmb) lmb->reserved.cnt = 0; } +void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align) +{ + ulong bank_end; + int bank; + + /* + * Reserve memory from aligned address below the bottom of U-Boot stack + * until end of U-Boot area using LMB to prevent U-Boot from overwriting + * that memory. + */ + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 4K to be safe */ + sp -= align; + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (!gd->bd->bi_dram[bank].size || + sp < gd->bd->bi_dram[bank].start) + continue; + /* Watch out for RAM at end of address space! */ + bank_end = gd->bd->bi_dram[bank].start + + gd->bd->bi_dram[bank].size - 1; + if (sp > bank_end) + continue; + if (bank_end > end) + bank_end = end - 1; + + lmb_reserve(lmb, sp, bank_end - sp + 1); + break; + } +} + static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob) { arch_lmb_reserve(lmb); diff --git a/lib/md5.c b/lib/md5.c index e2ba622ea4e84a2de61a1e4d17dfc25e017d0329..9d34465564e34ce48131eb5deb92e5489cd1b2a9 100644 --- a/lib/md5.c +++ b/lib/md5.c @@ -55,7 +55,7 @@ byteReverse(unsigned char *buf, unsigned longs) * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious * initialization constants. */ -static void +void MD5Init(struct MD5Context *ctx) { ctx->buf[0] = 0x67452301; @@ -71,7 +71,7 @@ MD5Init(struct MD5Context *ctx) * Update context to reflect the concatenation of another buffer full * of bytes. */ -static void +void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len) { register __u32 t; @@ -120,7 +120,7 @@ MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len) * Final wrapup - pad to 64-byte boundary with the bit pattern * 1 0* (64-bit count of bits processed, MSB-first) */ -static void +void MD5Final(unsigned char digest[16], struct MD5Context *ctx) { unsigned int count; diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig index c398f9b953577f7575b9c629a70d3ba1048bb065..3290b6656d923f02cf7b7cd72bb614f5b6abaed1 100644 --- a/lib/optee/Kconfig +++ b/lib/optee/Kconfig @@ -34,7 +34,6 @@ config BOOTM_OPTEE bool "Support OPTEE bootm command" select BOOTM_LINUX depends on OPTEE - default n help Select this command to enable chain-loading of a Linux kernel via an OPTEE firmware. diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 0e0a890fd153f2b0197492bb1b4725307aaecd21..c27a784c4298d7043801052632aeb2cd319773c7 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -19,24 +19,6 @@ #include <openssl/evp.h> #include <openssl/engine.h> -#if OPENSSL_VERSION_NUMBER >= 0x10000000L -#define HAVE_ERR_REMOVE_THREAD_STATE -#endif - -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) -static void RSA_get0_key(const RSA *r, - const BIGNUM **n, const BIGNUM **e, const BIGNUM **d) -{ - if (n != NULL) - *n = r->n; - if (e != NULL) - *e = r->e; - if (d != NULL) - *d = r->d; -} -#endif - static int rsa_err(const char *msg) { unsigned long sslErr = ERR_get_error(); @@ -272,7 +254,7 @@ static int rsa_engine_get_priv_key(const char *keydir, const char *name, else if (name) snprintf(key_id, sizeof(key_id), "%s", - name); + name ? name : ""); else if (keyfile) snprintf(key_id, sizeof(key_id), "%s", keyfile); else @@ -314,24 +296,11 @@ static int rsa_init(void) { int ret; -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - ret = SSL_library_init(); -#else ret = OPENSSL_init_ssl(0, NULL); -#endif if (!ret) { fprintf(stderr, "Failure to init SSL library\n"); return -1; } -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - SSL_load_error_strings(); - - OpenSSL_add_all_algorithms(); - OpenSSL_add_all_digests(); - OpenSSL_add_all_ciphers(); -#endif return 0; } @@ -347,8 +316,7 @@ static int rsa_engine_init(const char *engine_id, ENGINE **pe) e = ENGINE_by_id(engine_id); if (!e) { fprintf(stderr, "Engine isn't available\n"); - ret = -1; - goto err_engine_by_id; + return -1; } if (!ENGINE_init(e)) { @@ -381,29 +349,9 @@ err_set_rsa: ENGINE_finish(e); err_engine_init: ENGINE_free(e); -err_engine_by_id: -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - ENGINE_cleanup(); -#endif return ret; } -static void rsa_remove(void) -{ -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - CRYPTO_cleanup_all_ex_data(); - ERR_free_strings(); -#ifdef HAVE_ERR_REMOVE_THREAD_STATE - ERR_remove_thread_state(NULL); -#else - ERR_remove_state(0); -#endif - EVP_cleanup(); -#endif -} - static void rsa_engine_remove(ENGINE *e) { if (e) { @@ -476,12 +424,7 @@ static int rsa_sign_with_key(EVP_PKEY *pkey, struct padding_algo *padding_algo, goto err_sign; } - #if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - EVP_MD_CTX_cleanup(context); - #else - EVP_MD_CTX_reset(context); - #endif + EVP_MD_CTX_reset(context); EVP_MD_CTX_destroy(context); debug("Got signature: %zu bytes, expected %d\n", size, EVP_PKEY_size(pkey)); @@ -513,7 +456,7 @@ int rsa_sign(struct image_sign_info *info, if (info->engine_id) { ret = rsa_engine_init(info->engine_id, &e); if (ret) - goto err_engine; + return ret; } ret = rsa_get_priv_key(info->keydir, info->keyname, info->keyfile, @@ -528,7 +471,6 @@ int rsa_sign(struct image_sign_info *info, EVP_PKEY_free(pkey); if (info->engine_id) rsa_engine_remove(e); - rsa_remove(); return ret; @@ -537,8 +479,6 @@ err_sign: err_priv: if (info->engine_id) rsa_engine_remove(e); -err_engine: - rsa_remove(); return ret; } @@ -686,12 +626,8 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) ret = rsa_get_pub_key(info->keydir, info->keyname, e, &pkey); if (ret) goto err_get_pub_key; -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - rsa = EVP_PKEY_get1_RSA(pkey); -#else + rsa = EVP_PKEY_get0_RSA(pkey); -#endif ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); if (ret) goto err_get_params; @@ -761,10 +697,6 @@ done: if (ret) ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; err_get_params: -#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ - (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) - RSA_free(rsa); -#endif EVP_PKEY_free(pkey); err_get_pub_key: if (info->engine_id) diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index 89aaa8547710b3d970d78174a95c1746213297f4..f661fc65054ae88e60684c235d689053c84de85c 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -48,7 +48,7 @@ static void div_out(struct printf_info *info, unsigned long *num, out_dgt(info, dgt); } -#ifdef CONFIG_SPL_NET_SUPPORT +#ifdef CONFIG_SPL_NET static void string(struct printf_info *info, char *s) { char ch; @@ -178,7 +178,7 @@ static void __maybe_unused pointer(struct printf_info *info, const char *fmt, } break; #endif -#ifdef CONFIG_SPL_NET_SUPPORT +#ifdef CONFIG_SPL_NET case 'm': return mac_address_string(info, ptr, false); case 'M': @@ -270,7 +270,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) } break; case 'p': - if (CONFIG_IS_ENABLED(NET_SUPPORT) || _DEBUG) { + if (CONFIG_IS_ENABLED(NET) || _DEBUG) { pointer(info, fmt, va_arg(va, void *)); /* * Skip this because it pulls in _ctype which is diff --git a/net/Kconfig b/net/Kconfig index ba0ca813ce5245fa6918e9905de992c7f6e86e15..7a2d145018815c622dec7d37fba3753a3819dc46 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -40,7 +40,6 @@ config NETCONSOLE config IP_DEFRAG bool "Support IP datagram reassembly" - default n help Selecting this will enable IP datagram reassembly according to the algorithm in RFC815. diff --git a/net/cdp.c b/net/cdp.c index fac02046819492673f5b669cc49230e5fbdddb09..a8f890e75226f4b4198046fca67acd17ea8c2019 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -11,9 +11,6 @@ #include <common.h> #include <net.h> -#if defined(CONFIG_CDP_VERSION) -#include <timestamp.h> -#endif #include "cdp.h" diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c index 694664d81bbb3abc53cf1714ba3c436ab43552e4..bf762cd2a8c40d84e5319a4eeec0819cdd21f2ea 100644 --- a/net/dsa-uclass.c +++ b/net/dsa-uclass.c @@ -100,7 +100,7 @@ static void dsa_port_stop(struct udevice *pdev) port_pdata = dev_get_parent_plat(pdev); ops->port_disable(dev, port_pdata->index, port_pdata->phy); - ops->port_disable(dev, priv->cpu_port, NULL); + ops->port_disable(dev, priv->cpu_port, priv->cpu_port_fixed_phy); } eth_get_ops(master)->stop(master); @@ -199,9 +199,7 @@ static int dsa_port_free_pkt(struct udevice *pdev, uchar *packet, int length) static int dsa_port_of_to_pdata(struct udevice *pdev) { struct dsa_port_pdata *port_pdata; - struct dsa_pdata *dsa_pdata; struct eth_pdata *eth_pdata; - struct udevice *dev; const char *label; u32 index; int err; @@ -213,15 +211,12 @@ static int dsa_port_of_to_pdata(struct udevice *pdev) if (err) return err; - dev = dev_get_parent(pdev); - dsa_pdata = dev_get_uclass_plat(dev); - port_pdata = dev_get_parent_plat(pdev); port_pdata->index = index; label = ofnode_read_string(dev_ofnode(pdev), "label"); if (label) - strncpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH); + strlcpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH); eth_pdata = dev_get_plat(pdev); eth_pdata->priv_pdata = port_pdata; @@ -240,18 +235,42 @@ static const struct eth_ops dsa_port_ops = { .free_pkt = dsa_port_free_pkt, }; -static int dsa_port_probe(struct udevice *pdev) +/* + * Inherit port's hwaddr from the DSA master, unless the port already has a + * unique MAC address specified in the environment. + */ +static void dsa_port_set_hwaddr(struct udevice *pdev, struct udevice *master) { - struct udevice *dev = dev_get_parent(pdev); struct eth_pdata *eth_pdata, *master_pdata; unsigned char env_enetaddr[ARP_HLEN]; + + eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr); + if (!is_zero_ethaddr(env_enetaddr)) { + /* individual port mac addrs require master to be promisc */ + struct eth_ops *eth_ops = eth_get_ops(master); + + if (eth_ops->set_promisc) + eth_ops->set_promisc(master, 1); + + return; + } + + master_pdata = dev_get_plat(master); + eth_pdata = dev_get_plat(pdev); + memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN); + eth_env_set_enetaddr_by_index("eth", dev_seq(pdev), + master_pdata->enetaddr); +} + +static int dsa_port_probe(struct udevice *pdev) +{ + struct udevice *dev = dev_get_parent(pdev); + struct dsa_ops *ops = dsa_get_ops(dev); struct dsa_port_pdata *port_pdata; - struct dsa_priv *dsa_priv; struct udevice *master; - int ret; + int err; port_pdata = dev_get_parent_plat(pdev); - dsa_priv = dev_get_uclass_priv(dev); port_pdata->phy = dm_eth_phy_connect(pdev); if (!port_pdata->phy) @@ -268,42 +287,25 @@ static int dsa_port_probe(struct udevice *pdev) * TODO: we assume the master device is always there and doesn't get * removed during runtime. */ - ret = device_probe(master); - if (ret) - return ret; - - /* - * Inherit port's hwaddr from the DSA master, unless the port already - * has a unique MAC address specified in the environment. - */ - eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr); - if (!is_zero_ethaddr(env_enetaddr)) { - /* individual port mac addrs require master to be promisc */ - struct eth_ops *eth_ops = eth_get_ops(master); + err = device_probe(master); + if (err) + return err; - if (eth_ops->set_promisc) - eth_ops->set_promisc(master, 1); + dsa_port_set_hwaddr(pdev, master); - return 0; + if (ops->port_probe) { + err = ops->port_probe(dev, port_pdata->index, + port_pdata->phy); + if (err) + return err; } - master_pdata = dev_get_plat(master); - eth_pdata = dev_get_plat(pdev); - memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN); - eth_env_set_enetaddr_by_index("eth", dev_seq(pdev), - master_pdata->enetaddr); - return 0; } static int dsa_port_remove(struct udevice *pdev) { - struct udevice *dev = dev_get_parent(pdev); - struct dsa_port_pdata *port_pdata; - struct dsa_priv *dsa_priv; - - port_pdata = dev_get_parent_plat(pdev); - dsa_priv = dev_get_uclass_priv(dev); + struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev); port_pdata->phy = NULL; @@ -419,7 +421,7 @@ static int dsa_post_bind(struct udevice *dev) struct dsa_port_pdata *port_pdata; port_pdata = dev_get_parent_plat(pdev); - strncpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH); + strlcpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH); pdev->name = port_pdata->name; } diff --git a/net/eth_common.c b/net/eth_common.c index 58f899a02405597673450630eaffd2ab6d8365ba..82d527abba67f3a49771dd9582e7cc83bbab0b69 100644 --- a/net/eth_common.c +++ b/net/eth_common.c @@ -32,6 +32,7 @@ int eth_env_set_enetaddr_by_index(const char *base_name, int index, void eth_common_init(void) { bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); +#if CONFIG_IS_ENABLED(ETH) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_init(); #endif @@ -39,6 +40,7 @@ void eth_common_init(void) #ifdef CONFIG_PHYLIB phy_init(); #endif +#endif } int eth_mac_skip(int index) diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 1b687765b8ca2263d927d27e054c748833a908d7..e74e34f78f9cd1d689e2df0fc013ec57fa0ea055 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -101,7 +101,7 @@ static int dm_mdio_post_probe(struct udevice *dev) pdata->mii_bus->write = mdio_write; pdata->mii_bus->reset = mdio_reset; pdata->mii_bus->priv = dev; - strncpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN - 1); + strlcpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN); return mdio_register(pdata->mii_bus); } diff --git a/net/tftp.c b/net/tftp.c index 5baf528f4ecdf5c1e922b1cd6bfcb95edce5402e..87392014d58e0c9ab6aa2ee4d6ba4b3046c66856 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -925,4 +925,3 @@ void tftp_start_server(void) memset(net_server_ethaddr, 0, 6); } #endif /* CONFIG_CMD_TFTPSRV */ - diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index cc971a8909784c9d4be997a14e422716b4d631b5..f88eff8998f9184085b83a396df6f82c820a1348 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -70,10 +70,6 @@ int ecc_post_test(int flags) int_state = disable_interrupts(); icache_enable(); -#ifdef CONFIG_DDR_32BIT - /* It seems like no one really uses the CONFIG_DDR_32BIT mode */ -#error "Add ECC POST support for CONFIG_DDR_32BIT here!" -#else for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0; addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { @@ -138,7 +134,6 @@ int ecc_post_test(int flags) errbit %= 63; } -#endif /* !CONFIG_DDR_32BIT */ ecc_clear(ddr); diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 25a3e7fa52e998b596558c3e81a0c41274e7d1b4..6f26eb1fa1f45c14feff9a2bba2cbbb535e597bb 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -108,7 +108,7 @@ libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/cdns3/ libs-y += dts/ libs-y += fs/ libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ -libs-$(CONFIG_SPL_NET_SUPPORT) += net/ +libs-$(CONFIG_SPL_NET) += net/ libs-$(CONFIG_SPL_UNIT_TEST) += test/ head-y := $(addprefix $(obj)/,$(head-y)) @@ -295,18 +295,15 @@ else FINAL_DTB_CONTAINER = $(obj)/$(SPL_BIN).multidtb.fit endif -# Build the .dtb file if: -# - we are not using OF_PLATDATA -# - we are using OF_CONTROL +# Build the .dtb file if needed +# - OF_REAL is enabled # - we have either OF_SEPARATE or OF_HOSTFILE build_dtb := -ifeq ($(CONFIG_$(SPL_TPL_)OF_PLATDATA),) -ifneq ($(CONFIG_$(SPL_TPL_)OF_CONTROL),) +ifneq ($(CONFIG_$(SPL_TPL_)OF_REAL),) ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_OF_HOSTFILE),y) build_dtb := y endif endif -endif ifneq ($(build_dtb),) $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ diff --git a/scripts/basic/Makefile b/scripts/basic/Makefile index 092a8876d6028bd6b6ab8169b79b6782a56631bd..848f16d3c4dae1a652db17bb6e63e43ddcdc657f 100644 --- a/scripts/basic/Makefile +++ b/scripts/basic/Makefile @@ -7,7 +7,7 @@ # when kernel configuration changes (which is what happens when # .config is included by main Makefile. # --------------------------------------------------------------------------- -# fixdep: Used to generate dependency information during build process +# fixdep: Used to generate dependency information during build process hostprogs-y := fixdep always := $(hostprogs-y) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 08a827535aaff828043a667100eeee67ce061f54..5696d3a5f3b4f087f7c9dc4bfa4f5df338afda85 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -23,6 +23,9 @@ my $V = '0.32'; use Getopt::Long qw(:config no_auto_abbrev); my $quiet = 0; +my $verbose = 0; +my %verbose_messages = (); +my %verbose_emitted = (); my $tree = 1; my $chk_signoff = 1; my $chk_patch = 1; @@ -43,6 +46,8 @@ my $list_types = 0; my $fix = 0; my $fix_inplace = 0; my $root; +my $gitroot = $ENV{'GIT_DIR'}; +$gitroot = ".git" if !defined($gitroot); my %debug; my %camelcase = (); my %use_type = (); @@ -59,13 +64,15 @@ my $spelling_file = "$D/spelling.txt"; my $codespell = 0; my $codespellfile = "/usr/share/codespell/dictionary.txt"; my $conststructsfile = "$D/const_structs.checkpatch"; -my $typedefsfile = ""; my $u_boot = 0; +my $docsfile = "$D/../doc/develop/checkpatch.rst"; +my $typedefsfile; my $color = "auto"; my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE # git output parsing needs US English output, so first set backtick child process LANGUAGE my $git_command ='export LANGUAGE=en_US.UTF-8; git'; my $tabsize = 8; +my ${CONFIG_} = "CONFIG_"; sub help { my ($exitcode) = @_; @@ -76,6 +83,7 @@ Version: $V Options: -q, --quiet quiet + -v, --verbose verbose mode --no-tree run without a kernel tree --no-signoff do not check for 'Signed-off-by' line --patch treat FILE as patchfile (default) @@ -129,6 +137,8 @@ Options: --color[=WHEN] Use colors 'always', 'never', or only when output is a terminal ('auto'). Default is 'auto'. --u-boot Run additional checks for U-Boot + --kconfig-prefix=WORD use WORD as a prefix for Kconfig symbols (default + ${CONFIG_}) -h, --help, --version display this help and exit When FILE is - read standard input. @@ -155,15 +165,51 @@ sub list_types { my $text = <$script>; close($script); - my @types = (); + my %types = (); # Also catch when type or level is passed through a variable - for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { - push (@types, $_); + while ($text =~ /(?:(\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { + if (defined($1)) { + if (exists($types{$2})) { + $types{$2} .= ",$1" if ($types{$2} ne $1); + } else { + $types{$2} = $1; + } + } else { + $types{$2} = "UNDETERMINED"; + } } - @types = sort(uniq(@types)); + print("#\tMessage type\n\n"); - foreach my $type (@types) { + if ($color) { + print(" ( Color coding: "); + print(RED . "ERROR" . RESET); + print(" | "); + print(YELLOW . "WARNING" . RESET); + print(" | "); + print(GREEN . "CHECK" . RESET); + print(" | "); + print("Multiple levels / Undetermined"); + print(" )\n\n"); + } + + foreach my $type (sort keys %types) { + my $orig_type = $type; + if ($color) { + my $level = $types{$type}; + if ($level eq "ERROR") { + $type = RED . $type . RESET; + } elsif ($level eq "WARN") { + $type = YELLOW . $type . RESET; + } elsif ($level eq "CHK") { + $type = GREEN . $type . RESET; + } + } print(++$count . "\t" . $type . "\n"); + if ($verbose && exists($verbose_messages{$orig_type})) { + my $message = $verbose_messages{$orig_type}; + $message =~ s/\n/\n\t/g; + print("\t" . $message . "\n\n"); + } } exit($exitcode); @@ -195,6 +241,46 @@ if (-f $conf) { unshift(@ARGV, @conf_args) if @conf_args; } +sub load_docs { + open(my $docs, '<', "$docsfile") + or warn "$P: Can't read the documentation file $docsfile $!\n"; + + my $type = ''; + my $desc = ''; + my $in_desc = 0; + + while (<$docs>) { + chomp; + my $line = $_; + $line =~ s/\s+$//; + + if ($line =~ /^\s*\*\*(.+)\*\*$/) { + if ($desc ne '') { + $verbose_messages{$type} = trim($desc); + } + $type = $1; + $desc = ''; + $in_desc = 1; + } elsif ($in_desc) { + if ($line =~ /^(?:\s{4,}|$)/) { + $line =~ s/^\s{4}//; + $desc .= $line; + $desc .= "\n"; + } else { + $verbose_messages{$type} = trim($desc); + $type = ''; + $desc = ''; + $in_desc = 0; + } + } + } + + if ($desc ne '') { + $verbose_messages{$type} = trim($desc); + } + close($docs); +} + # Perl's Getopt::Long allows options to take optional arguments after a space. # Prevent --color by itself from consuming other arguments foreach (@ARGV) { @@ -205,6 +291,7 @@ foreach (@ARGV) { GetOptions( 'q|quiet+' => \$quiet, + 'v|verbose!' => \$verbose, 'tree!' => \$tree, 'signoff!' => \$chk_signoff, 'patch!' => \$chk_patch, @@ -238,12 +325,29 @@ GetOptions( 'color=s' => \$color, 'no-color' => \$color, #keep old behaviors of -nocolor 'nocolor' => \$color, #keep old behaviors of -nocolor + 'kconfig-prefix=s' => \${CONFIG_}, 'h|help' => \$help, 'version' => \$help ) or help(1); help(0) if ($help); +die "$P: --git cannot be used with --file or --fix\n" if ($git && ($file || $fix)); +die "$P: --verbose cannot be used with --terse\n" if ($verbose && $terse); + +if ($color =~ /^[01]$/) { + $color = !$color; +} elsif ($color =~ /^always$/i) { + $color = 1; +} elsif ($color =~ /^never$/i) { + $color = 0; +} elsif ($color =~ /^auto$/i) { + $color = (-t STDOUT); +} else { + die "$P: Invalid color mode: $color\n"; +} + +load_docs() if ($verbose); list_types(0) if ($list_types); $fix = 1 if ($fix_inplace); @@ -263,20 +367,8 @@ if ($#ARGV < 0) { push(@ARGV, '-'); } -if ($color =~ /^[01]$/) { - $color = !$color; -} elsif ($color =~ /^always$/i) { - $color = 1; -} elsif ($color =~ /^never$/i) { - $color = 0; -} elsif ($color =~ /^auto$/i) { - $color = (-t STDOUT); -} else { - die "Invalid color mode: $color\n"; -} - # skip TAB size 1 to avoid additional checks on $tabsize - 1 -die "Invalid TAB size: $tabsize\n" if ($tabsize < 2); +die "$P: Invalid TAB size: $tabsize\n" if ($tabsize < 2); sub hash_save_array_words { my ($hashRef, $arrayRef) = @_; @@ -377,6 +469,7 @@ our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeIni # We need \b after 'init' otherwise 'initconst' will cause a false positive in a check our $Attribute = qr{ const| + volatile| __percpu| __nocast| __safe| @@ -483,7 +576,7 @@ our $logFunctions = qr{(?x: our $allocFunctions = qr{(?x: (?:(?:devm_)? - (?:kv|k|v)[czm]alloc(?:_node|_array)? | + (?:kv|k|v)[czm]alloc(?:_array)?(?:_node)? | kstrdup(?:_const)? | kmemdup(?:_nul)?) | (?:\w+)?alloc_skb(?:_ip_align)? | @@ -503,6 +596,88 @@ our $signature_tags = qr{(?xi: Cc: )}; +our $tracing_logging_tags = qr{(?xi: + [=-]*> | + <[=-]* | + \[ | + \] | + start | + called | + entered | + entry | + enter | + in | + inside | + here | + begin | + exit | + end | + done | + leave | + completed | + out | + return | + [\.\!:\s]* +)}; + +sub edit_distance_min { + my (@arr) = @_; + my $len = scalar @arr; + if ((scalar @arr) < 1) { + # if underflow, return + return; + } + my $min = $arr[0]; + for my $i (0 .. ($len-1)) { + if ($arr[$i] < $min) { + $min = $arr[$i]; + } + } + return $min; +} + +sub get_edit_distance { + my ($str1, $str2) = @_; + $str1 = lc($str1); + $str2 = lc($str2); + $str1 =~ s/-//g; + $str2 =~ s/-//g; + my $len1 = length($str1); + my $len2 = length($str2); + # two dimensional array storing minimum edit distance + my @distance; + for my $i (0 .. $len1) { + for my $j (0 .. $len2) { + if ($i == 0) { + $distance[$i][$j] = $j; + } elsif ($j == 0) { + $distance[$i][$j] = $i; + } elsif (substr($str1, $i-1, 1) eq substr($str2, $j-1, 1)) { + $distance[$i][$j] = $distance[$i - 1][$j - 1]; + } else { + my $dist1 = $distance[$i][$j - 1]; #insert distance + my $dist2 = $distance[$i - 1][$j]; # remove + my $dist3 = $distance[$i - 1][$j - 1]; #replace + $distance[$i][$j] = 1 + edit_distance_min($dist1, $dist2, $dist3); + } + } + } + return $distance[$len1][$len2]; +} + +sub find_standard_signature { + my ($sign_off) = @_; + my @standard_signature_tags = ( + 'Signed-off-by:', 'Co-developed-by:', 'Acked-by:', 'Tested-by:', + 'Reviewed-by:', 'Reported-by:', 'Suggested-by:' + ); + foreach my $signature (@standard_signature_tags) { + return $signature if (get_edit_distance($sign_off, $signature) <= 2); + } + + return ""; +} + our @typeListMisordered = ( qr{char\s+(?:un)?signed}, qr{int\s+(?:(?:un)?signed\s+)?short\s}, @@ -591,6 +766,8 @@ our @mode_permission_funcs = ( ["__ATTR", 2], ); +my $word_pattern = '\b[A-Z]?[a-z]{2,}\b'; + #Create a search pattern for all these functions to speed up a loop below our $mode_perms_search = ""; foreach my $entry (@mode_permission_funcs) { @@ -759,7 +936,7 @@ sub read_words { next; } - $$wordsRef .= '|' if ($$wordsRef ne ""); + $$wordsRef .= '|' if (defined $$wordsRef); $$wordsRef .= $line; } close($file); @@ -769,16 +946,18 @@ sub read_words { return 0; } -my $const_structs = ""; -read_words(\$const_structs, $conststructsfile) - or warn "No structs that should be const will be found - file '$conststructsfile': $!\n"; +my $const_structs; +if (show_type("CONST_STRUCT")) { + read_words(\$const_structs, $conststructsfile) + or warn "No structs that should be const will be found - file '$conststructsfile': $!\n"; +} -my $typeOtherTypedefs = ""; -if (length($typedefsfile)) { +if (defined($typedefsfile)) { + my $typeOtherTypedefs; read_words(\$typeOtherTypedefs, $typedefsfile) or warn "No additional types will be considered - file '$typedefsfile': $!\n"; + $typeTypedefs .= '|' . $typeOtherTypedefs if (defined $typeOtherTypedefs); } -$typeTypedefs .= '|' . $typeOtherTypedefs if ($typeOtherTypedefs ne ""); sub build_types { my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)"; @@ -843,10 +1022,16 @@ our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)}; our $declaration_macros = qr{(?x: (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(| (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(| - (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(| (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\( )}; +our %allow_repeated_words = ( + add => '', + added => '', + bad => '', + be => '', +); + sub deparenthesize { my ($string) = @_; return "" if (!defined($string)); @@ -904,7 +1089,7 @@ sub is_maintained_obsolete { sub is_SPDX_License_valid { my ($license) = @_; - return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$root/.git")); + return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$gitroot")); my $root_path = abs_path($root); my $status = `cd "$root_path"; echo "$license" | python scripts/spdxcheck.py -`; @@ -922,7 +1107,7 @@ sub seed_camelcase_includes { $camelcase_seeded = 1; - if (-e ".git") { + if (-e "$gitroot") { my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`; chomp $git_last_include_commit; $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; @@ -950,7 +1135,7 @@ sub seed_camelcase_includes { return; } - if (-e ".git") { + if (-e "$gitroot") { $files = `${git_command} ls-files "include/*.h"`; @include_files = split('\n', $files); } @@ -970,10 +1155,20 @@ sub seed_camelcase_includes { } } +sub git_is_single_file { + my ($filename) = @_; + + return 0 if ((which("git") eq "") || !(-e "$gitroot")); + + my $output = `${git_command} ls-files -- $filename 2>/dev/null`; + my $count = $output =~ tr/\n//; + return $count eq 1 && $output =~ m{^${filename}$}; +} + sub git_commit_info { my ($commit, $id, $desc) = @_; - return ($id, $desc) if ((which("git") eq "") || !(-e ".git")); + return ($id, $desc) if ((which("git") eq "") || !(-e "$gitroot")); my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`; $output =~ s/^\s*//gm; @@ -1012,7 +1207,7 @@ my $fixlinenr = -1; # If input is git commits, extract all commits from the commit expressions. # For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'. -die "$P: No git repository found\n" if ($git && !-e ".git"); +die "$P: No git repository found\n" if ($git && !-e "$gitroot"); if ($git) { my @commits = (); @@ -1043,6 +1238,9 @@ my $vname; $allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"}; for my $filename (@ARGV) { my $FILE; + my $is_git_file = git_is_single_file($filename); + my $oldfile = $file; + $file = 1 if ($is_git_file); if ($git) { open($FILE, '-|', "git format-patch -M --stdout -1 $filename") || die "$P: $filename: git format-patch failed - $!\n"; @@ -1065,6 +1263,7 @@ for my $filename (@ARGV) { while (<$FILE>) { chomp; push(@rawlines, $_); + $vname = qq("$1") if ($filename eq '-' && $_ =~ m/^Subject:\s+(.+)/i); } close($FILE); @@ -1086,6 +1285,7 @@ for my $filename (@ARGV) { @modifierListFile = (); @typeListFile = (); build_types(); + $file = $oldfile if ($is_git_file); } if (!$quiet) { @@ -1131,6 +1331,7 @@ sub parse_email { my ($formatted_email) = @_; my $name = ""; + my $quoted = ""; my $name_comment = ""; my $address = ""; my $comment = ""; @@ -1162,14 +1363,20 @@ sub parse_email { } } - $name = trim($name); - $name =~ s/^\"|\"$//g; - $name =~ s/(\s*\([^\)]+\))\s*//; - if (defined($1)) { - $name_comment = trim($1); + # Extract comments from names excluding quoted parts + # "John D. (Doe)" - Do not extract + if ($name =~ s/\"(.+)\"//) { + $quoted = $1; + } + while ($name =~ s/\s*($balanced_parens)\s*/ /) { + $name_comment .= trim($1); } + $name =~ s/^[ \"]+|[ \"]+$//g; + $name = trim("$quoted $name"); + $address = trim($address); $address =~ s/^\<|\>$//g; + $comment = trim($comment); if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(?<!\\)"/\\"/g; ##escape quotes @@ -1180,25 +1387,30 @@ sub parse_email { } sub format_email { - my ($name, $address) = @_; + my ($name, $name_comment, $address, $comment) = @_; my $formatted_email; - $name = trim($name); - $name =~ s/^\"|\"$//g; + $name =~ s/^[ \"]+|[ \"]+$//g; $address = trim($address); + $address =~ s/(?:\.|\,|\")+$//; ##trailing commas, dots or quotes if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(?<!\\)"/\\"/g; ##escape quotes $name = "\"$name\""; } + $name_comment = trim($name_comment); + $name_comment = " $name_comment" if ($name_comment ne ""); + $comment = trim($comment); + $comment = " $comment" if ($comment ne ""); + if ("$name" eq "") { $formatted_email = "$address"; } else { - $formatted_email = "$name <$address>"; + $formatted_email = "$name$name_comment <$address>"; } - + $formatted_email .= "$comment"; return $formatted_email; } @@ -1206,7 +1418,7 @@ sub reformat_email { my ($email) = @_; my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); - return format_email($email_name, $email_address); + return format_email($email_name, $name_comment, $email_address, $comment); } sub same_email_addresses { @@ -1216,7 +1428,9 @@ sub same_email_addresses { my ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2); return $email1_name eq $email2_name && - $email1_address eq $email2_address; + $email1_address eq $email2_address && + $name1_comment eq $name2_comment && + $comment1 eq $comment2; } sub which { @@ -1681,8 +1895,16 @@ sub ctx_statement_level { sub ctx_locate_comment { my ($first_line, $end_line) = @_; + # If c99 comment on the current line, or the line before or after + my ($current_comment) = ($rawlines[$end_line - 1] =~ m@^\+.*(//.*$)@); + return $current_comment if (defined $current_comment); + ($current_comment) = ($rawlines[$end_line - 2] =~ m@^[\+ ].*(//.*$)@); + return $current_comment if (defined $current_comment); + ($current_comment) = ($rawlines[$end_line] =~ m@^[\+ ].*(//.*$)@); + return $current_comment if (defined $current_comment); + # Catch a comment on the end of the line itself. - my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); return $current_comment if (defined $current_comment); # Look through the context and try and figure out if there is a @@ -2076,7 +2298,16 @@ sub report { splice(@lines, 1, 1); $output = join("\n", @lines); } - $output = (split('\n', $output))[0] . "\n" if ($terse); + + if ($terse) { + $output = (split('\n', $output))[0] . "\n"; + } + + if ($verbose && exists($verbose_messages{$type}) && + !exists($verbose_emitted{$type})) { + $output .= $verbose_messages{$type} . "\n\n"; + $verbose_emitted{$type} = 1; + } push(our @report, $output); @@ -2425,6 +2656,15 @@ sub u_boot_line { "DEVICE_PLAT_AUTO", $herecurr); } +sub exclude_global_initialisers { + my ($realfile) = @_; + + # Do not check for BPF programs (tools/testing/selftests/bpf/progs/*.c, samples/bpf/*_kern.c, *.bpf.c). + return $realfile =~ m@^tools/testing/selftests/bpf/progs/.*\.c$@ || + $realfile =~ m@^samples/bpf/.*_kern\.c$@ || + $realfile =~ m@/bpf/.*\.bpf\.c$@; +} + sub process { my $filename = shift; @@ -2443,6 +2683,7 @@ sub process { my $signoff = 0; my $author = ''; my $authorsignoff = 0; + my $author_sob = ''; my $is_patch = 0; my $is_binding_patch = -1; my $in_header_lines = $file ? 0 : 1; @@ -2506,7 +2747,7 @@ sub process { if ($rawline=~/^\+\+\+\s+(\S+)/) { $setup_docs = 0; - if ($1 =~ m@Documentation/admin-guide/kernel-parameters.rst$@) { + if ($1 =~ m@Documentation/admin-guide/kernel-parameters.txt$@) { $setup_docs = 1; } #next; @@ -2706,7 +2947,7 @@ sub process { if (($last_binding_patch != -1) && ($last_binding_patch ^ $is_binding_patch)) { WARN("DT_SPLIT_BINDING_PATCH", - "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt\n"); + "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst\n"); } } @@ -2735,8 +2976,8 @@ sub process { # Check if the commit log has what seems like a diff which can confuse patch if ($in_commit_log && !$commit_log_has_diff && - (($line =~ m@^\s+diff\b.*a/[\w/]+@ && - $line =~ m@^\s+diff\b.*a/([\w/]+)\s+b/$1\b@) || + (($line =~ m@^\s+diff\b.*a/([\w/]+)@ && + $line =~ m@^\s+diff\b.*a/[\w/]+\s+b/$1\b@) || $line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ || $line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) { ERROR("DIFF_IN_COMMIT_MSG", @@ -2757,6 +2998,10 @@ sub process { # Check the patch for a From: if (decode("MIME-Header", $line) =~ /^From:\s*(.*)/) { $author = $1; + my $curline = $linenr; + while(defined($rawlines[$curline]) && ($rawlines[$curline++] =~ /^[ \t]\s*(.*)/)) { + $author .= $1; + } $author = encode("utf8", $author) if ($line =~ /=\?utf-8\?/i); $author =~ s/"//g; $author = reformat_email($author); @@ -2766,9 +3011,37 @@ sub process { if ($line =~ /^\s*signed-off-by:\s*(.*)/i) { $signoff++; $in_commit_log = 0; - if ($author ne '') { + if ($author ne '' && $authorsignoff != 1) { if (same_email_addresses($1, $author)) { $authorsignoff = 1; + } else { + my $ctx = $1; + my ($email_name, $email_comment, $email_address, $comment1) = parse_email($ctx); + my ($author_name, $author_comment, $author_address, $comment2) = parse_email($author); + + if ($email_address eq $author_address && $email_name eq $author_name) { + $author_sob = $ctx; + $authorsignoff = 2; + } elsif ($email_address eq $author_address) { + $author_sob = $ctx; + $authorsignoff = 3; + } elsif ($email_name eq $author_name) { + $author_sob = $ctx; + $authorsignoff = 4; + + my $address1 = $email_address; + my $address2 = $author_address; + + if ($address1 =~ /(\S+)\+\S+(\@.*)/) { + $address1 = "$1$2"; + } + if ($address2 =~ /(\S+)\+\S+(\@.*)/) { + $address2 = "$1$2"; + } + if ($address1 eq $address2) { + $authorsignoff = 5; + } + } } } } @@ -2795,8 +3068,17 @@ sub process { my $ucfirst_sign_off = ucfirst(lc($sign_off)); if ($sign_off !~ /$signature_tags/) { - WARN("BAD_SIGN_OFF", - "Non-standard signature: $sign_off\n" . $herecurr); + my $suggested_signature = find_standard_signature($sign_off); + if ($suggested_signature eq "") { + WARN("BAD_SIGN_OFF", + "Non-standard signature: $sign_off\n" . $herecurr); + } else { + if (WARN("BAD_SIGN_OFF", + "Non-standard signature: '$sign_off' - perhaps '$suggested_signature'?\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/$sign_off/$suggested_signature/; + } + } } if (defined $space_before && $space_before ne "") { if (WARN("BAD_SIGN_OFF", @@ -2825,7 +3107,7 @@ sub process { } my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); - my $suggested_email = format_email(($email_name, $email_address)); + my $suggested_email = format_email(($email_name, $name_comment, $email_address, $comment)); if ($suggested_email eq "") { ERROR("BAD_SIGN_OFF", "Unrecognized email address: '$email'\n" . $herecurr); @@ -2836,8 +3118,76 @@ sub process { # Don't force email to have quotes # Allow just an angle bracketed address if (!same_email_addresses($email, $suggested_email)) { + if (WARN("BAD_SIGN_OFF", + "email address '$email' might be better as '$suggested_email'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email\E/$suggested_email/; + } + } + + # Address part shouldn't have comments + my $stripped_address = $email_address; + $stripped_address =~ s/\([^\(\)]*\)//g; + if ($email_address ne $stripped_address) { + if (WARN("BAD_SIGN_OFF", + "address part of email should not have comments: '$email_address'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email_address\E/$stripped_address/; + } + } + + # Only one name comment should be allowed + my $comment_count = () = $name_comment =~ /\([^\)]+\)/g; + if ($comment_count > 1) { WARN("BAD_SIGN_OFF", - "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); + "Use a single name comment in email: '$email'\n" . $herecurr); + } + + + # stable@vger.kernel.org or stable@kernel.org shouldn't + # have an email name. In addition comments should strictly + # begin with a # + if ($email =~ /^.*stable\@(?:vger\.)?kernel\.org/i) { + if (($comment ne "" && $comment !~ /^#.+/) || + ($email_name ne "")) { + my $cur_name = $email_name; + my $new_comment = $comment; + $cur_name =~ s/[a-zA-Z\s\-\"]+//g; + + # Remove brackets enclosing comment text + # and # from start of comments to get comment text + $new_comment =~ s/^\((.*)\)$/$1/; + $new_comment =~ s/^\[(.*)\]$/$1/; + $new_comment =~ s/^[\s\#]+|\s+$//g; + + $new_comment = trim("$new_comment $cur_name") if ($cur_name ne $new_comment); + $new_comment = " # $new_comment" if ($new_comment ne ""); + my $new_email = "$email_address$new_comment"; + + if (WARN("BAD_STABLE_ADDRESS_STYLE", + "Invalid email format for stable: '$email', prefer '$new_email'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/; + } + } + } elsif ($comment ne "" && $comment !~ /^(?:#.+|\(.+\))$/) { + my $new_comment = $comment; + + # Extract comment text from within brackets or + # c89 style /*...*/ comments + $new_comment =~ s/^\[(.*)\]$/$1/; + $new_comment =~ s/^\/\*(.*)\*\/$/$1/; + + $new_comment = trim($new_comment); + $new_comment =~ s/^[^\w]$//; # Single lettered comment with non word character is usually a typo + $new_comment = "($new_comment)" if ($new_comment ne ""); + my $new_email = format_email($email_name, $name_comment, $email_address, $new_comment); + + if (WARN("BAD_SIGN_OFF", + "Unexpected content after email: '$email', should be: '$new_email'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/; + } } } @@ -2860,7 +3210,7 @@ sub process { } if (!defined $lines[$linenr]) { WARN("BAD_SIGN_OFF", - "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline); + "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline); } elsif ($rawlines[$linenr] !~ /^\s*signed-off-by:\s*(.*)/i) { WARN("BAD_SIGN_OFF", "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]); @@ -2880,8 +3230,11 @@ sub process { # Check for Gerrit Change-Ids not in any patch context if ($realfile eq '' && !$has_patch_separator && $line =~ /^\s*change-id:/i) { - ERROR("GERRIT_CHANGE_ID", - "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr); + if (ERROR("GERRIT_CHANGE_ID", + "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } } # Check if the commit log is in a possible stack dump @@ -2903,8 +3256,8 @@ sub process { # file delta changes $line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ || # filename then : - $line =~ /^\s*(?:Fixes:|Link:)/i || - # A Fixes: or Link: line + $line =~ /^\s*(?:Fixes:|Link:|$signature_tags)/i || + # A Fixes: or Link: line or signature tag line $commit_log_possible_stack_dump)) { WARN("COMMIT_LOG_LONG_LINE", "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr); @@ -2917,6 +3270,15 @@ sub process { $commit_log_possible_stack_dump = 0; } +# Check for lines starting with a # + if ($in_commit_log && $line =~ /^#/) { + if (WARN("COMMIT_COMMENT_SYMBOL", + "Commit log lines starting with '#' are dropped by git as comments\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^/ /; + } + } + # Check for git id commit length and improperly formed commit descriptions if ($in_commit_log && !$commit_log_possible_stack_dump && $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i && @@ -2993,7 +3355,7 @@ sub process { ($line =~ /^new file mode\s*\d+\s*$/) && ($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) { WARN("DT_SCHEMA_BINDING_PATCH", - "DT bindings should be in DT schema format. See: Documentation/devicetree/writing-schema.rst\n"); + "DT bindings should be in DT schema format. See: Documentation/devicetree/bindings/writing-schema.rst\n"); } # Check for wrappage within a valid hunk of the file @@ -3057,15 +3419,18 @@ sub process { # Check for various typo / spelling mistakes if (defined($misspellings) && ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) { - while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\b|$|[^a-z@])/gi) { + while ($rawline =~ /(?:^|[^\w\-'`])($misspellings)(?:[^\w\-'`]|$)/gi) { my $typo = $1; + my $blank = copy_spacing($rawline); + my $ptr = substr($blank, 0, $-[1]) . "^" x length($typo); + my $hereptr = "$hereline$ptr\n"; my $typo_fix = $spelling_fix{lc($typo)}; $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/); $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/); my $msg_level = \&WARN; $msg_level = \&CHK if ($file); if (&{$msg_level}("TYPO_SPELLING", - "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) && + "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $hereptr) && $fix) { $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/; } @@ -3083,6 +3448,60 @@ sub process { } } +# check for repeated words separated by a single space +# avoid false positive from list command eg, '-rw-r--r-- 1 root root' + if (($rawline =~ /^\+/ || $in_commit_log) && + $rawline !~ /[bcCdDlMnpPs\?-][rwxsStT-]{9}/) { + pos($rawline) = 1 if (!$in_commit_log); + while ($rawline =~ /\b($word_pattern) (?=($word_pattern))/g) { + + my $first = $1; + my $second = $2; + my $start_pos = $-[1]; + my $end_pos = $+[2]; + if ($first =~ /(?:struct|union|enum)/) { + pos($rawline) += length($first) + length($second) + 1; + next; + } + + next if (lc($first) ne lc($second)); + next if ($first eq 'long'); + + # check for character before and after the word matches + my $start_char = ''; + my $end_char = ''; + $start_char = substr($rawline, $start_pos - 1, 1) if ($start_pos > ($in_commit_log ? 0 : 1)); + $end_char = substr($rawline, $end_pos, 1) if ($end_pos < length($rawline)); + + next if ($start_char =~ /^\S$/); + next if (index(" \t.,;?!", $end_char) == -1); + + # avoid repeating hex occurrences like 'ff ff fe 09 ...' + if ($first =~ /\b[0-9a-f]{2,}\b/i) { + next if (!exists($allow_repeated_words{lc($first)})); + } + + if (WARN("REPEATED_WORD", + "Possible repeated word: '$first'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$first $second\b/$first/; + } + } + + # if it's a repeated word on consecutive lines in a comment block + if ($prevline =~ /$;+\s*$/ && + $prevrawline =~ /($word_pattern)\s*$/) { + my $last_word = $1; + if ($rawline =~ /^\+\s*\*\s*$last_word /) { + if (WARN("REPEATED_WORD", + "Possible repeated word: '$last_word'\n" . $hereprev) && + $fix) { + $fixed[$fixlinenr] =~ s/(\+\s*\*\s*)$last_word /$1/; + } + } + } + } + # ignore non-hunk lines and lines being removed next if (!$hunk_line || $line =~ /^-/); @@ -3141,11 +3560,7 @@ sub process { if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) { $is_start = 1; - } elsif ($lines[$ln - 1] =~ /^\+\s*(?:help|---help---)\s*$/) { - if ($lines[$ln - 1] =~ "---help---") { - WARN("CONFIG_DESCRIPTION", - "prefer 'help' over '---help---' for new help texts\n" . $herecurr); - } + } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) { $length = -1; } @@ -3172,22 +3587,44 @@ sub process { #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; } -# check for MAINTAINERS entries that don't have the right form - if ($realfile =~ /^MAINTAINERS$/ && - $rawline =~ /^\+[A-Z]:/ && - $rawline !~ /^\+[A-Z]:\t\S/) { - if (WARN("MAINTAINERS_STYLE", - "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/; +# check MAINTAINERS entries + if ($realfile =~ /^MAINTAINERS$/) { +# check MAINTAINERS entries for the right form + if ($rawline =~ /^\+[A-Z]:/ && + $rawline !~ /^\+[A-Z]:\t\S/) { + if (WARN("MAINTAINERS_STYLE", + "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/; + } + } +# check MAINTAINERS entries for the right ordering too + my $preferred_order = 'MRLSWQBCPTFXNK'; + if ($rawline =~ /^\+[A-Z]:/ && + $prevrawline =~ /^[\+ ][A-Z]:/) { + $rawline =~ /^\+([A-Z]):\s*(.*)/; + my $cur = $1; + my $curval = $2; + $prevrawline =~ /^[\+ ]([A-Z]):\s*(.*)/; + my $prev = $1; + my $prevval = $2; + my $curindex = index($preferred_order, $cur); + my $previndex = index($preferred_order, $prev); + if ($curindex < 0) { + WARN("MAINTAINERS_STYLE", + "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr); + } else { + if ($previndex >= 0 && $curindex < $previndex) { + WARN("MAINTAINERS_STYLE", + "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev); + } elsif ((($prev eq 'F' && $cur eq 'F') || + ($prev eq 'X' && $cur eq 'X')) && + ($prevval cmp $curval) > 0) { + WARN("MAINTAINERS_STYLE", + "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev); + } + } } - } - -# discourage the use of boolean for type definition attributes of Kconfig options - if ($realfile =~ /Kconfig/ && - $line =~ /^\+\s*\bboolean\b/) { - WARN("CONFIG_TYPE_BOOLEAN", - "Use of boolean is deprecated, please use bool instead.\n" . $herecurr); } if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && @@ -3284,6 +3721,12 @@ sub process { } } +# check for embedded filenames + if ($rawline =~ /^\+.*\Q$realfile\E/) { + WARN("EMBEDDED_FILENAME", + "It's generally not useful to have the filename in the file\n" . $herecurr); + } + # check we are in a valid source file if not then ignore this hunk next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/); @@ -3361,8 +3804,18 @@ sub process { # check for adding lines without a newline. if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { - WARN("MISSING_EOF_NEWLINE", - "adding a line without newline at end of file\n" . $herecurr); + if (WARN("MISSING_EOF_NEWLINE", + "adding a line without newline at end of file\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr+1, "No newline at end of file"); + } + } + +# check for .L prefix local symbols in .S files + if ($realfile =~ /\.S$/ && + $line =~ /^\+\s*(?:[A-Z]+_)?SYM_[A-Z]+_(?:START|END)(?:_[A-Z_]+)?\s*\(\s*\.L/) { + WARN("AVOID_L_PREFIX", + "Avoid using '.L' prefixed local symbol names for denoting a range of code via 'SYM_*_START/END' annotations; see Documentation/asm-annotations.rst\n" . $herecurr); } if ($u_boot) { @@ -3400,14 +3853,28 @@ sub process { # check for assignments on the start of a line if ($sline =~ /^\+\s+($Assignment)[^=]/) { - CHK("ASSIGNMENT_CONTINUATIONS", - "Assignment operator '$1' should be on the previous line\n" . $hereprev); + my $operator = $1; + if (CHK("ASSIGNMENT_CONTINUATIONS", + "Assignment operator '$1' should be on the previous line\n" . $hereprev) && + $fix && $prevrawline =~ /^\+/) { + # add assignment operator to the previous line, remove from current line + $fixed[$fixlinenr - 1] .= " $operator"; + $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//; + } } # check for && or || at the start of a line if ($rawline =~ /^\+\s*(&&|\|\|)/) { - CHK("LOGICAL_CONTINUATIONS", - "Logical continuations should be on the previous line\n" . $hereprev); + my $operator = $1; + if (CHK("LOGICAL_CONTINUATIONS", + "Logical continuations should be on the previous line\n" . $hereprev) && + $fix && $prevrawline =~ /^\+/) { + # insert logical operator at last non-comment, non-whitepsace char on previous line + $prevline =~ /[\s$;]*$/; + my $line_end = substr($prevrawline, $-[0]); + $fixed[$fixlinenr - 1] =~ s/\Q$line_end\E$/ $operator$line_end/; + $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//; + } } # check indentation starts on a tab stop @@ -3475,7 +3942,7 @@ sub process { if ($realfile =~ m@^(drivers/net/|net/)@ && $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && $rawline =~ /^\+[ \t]*\*/ && - $realline > 2) { + $realline > 3) { # Do not warn about the initial copyright comment block after SPDX-License-Identifier WARN("NETWORKING_BLOCK_COMMENT_STYLE", "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); } @@ -3557,43 +4024,48 @@ sub process { } # check for missing blank lines after declarations - if ($sline =~ /^\+\s+\S/ && #Not at char 1 - # actual declarations - ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || +# (declarations must have the same indentation and not be at the start of line) + if (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/) { + # use temporaries + my $sl = $sline; + my $pl = $prevline; + # remove $Attribute/$Sparse uses to simplify comparisons + $sl =~ s/\b(?:$Attribute|$Sparse)\b//g; + $pl =~ s/\b(?:$Attribute|$Sparse)\b//g; + if (($pl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || # function pointer declarations - $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || # foo bar; where foo is some local typedef or #define - $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + $pl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || # known declaration macros - $prevline =~ /^\+\s+$declaration_macros/) && + $pl =~ /^\+\s+$declaration_macros/) && # for "else if" which can look like "$Ident $Ident" - !($prevline =~ /^\+\s+$c90_Keywords\b/ || + !($pl =~ /^\+\s+$c90_Keywords\b/ || # other possible extensions of declaration lines - $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || + $pl =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || # not starting a section or a macro "\" extended line - $prevline =~ /(?:\{\s*|\\)$/) && + $pl =~ /(?:\{\s*|\\)$/) && # looks like a declaration - !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + !($sl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || # function pointer declarations - $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || # foo bar; where foo is some local typedef or #define - $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + $sl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || # known declaration macros - $sline =~ /^\+\s+$declaration_macros/ || + $sl =~ /^\+\s+$declaration_macros/ || # start of struct or union or enum - $sline =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || + $sl =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || # start or end of block or continuation of declaration - $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || + $sl =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || # bitfield continuation - $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || + $sl =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || # other possible extensions of declaration lines - $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) && - # indentation of previous and current line are the same - (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) { - if (WARN("LINE_SPACING", - "Missing a blank line after declarations\n" . $hereprev) && - $fix) { - fix_insert_line($fixlinenr, "\+"); + $sl =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/)) { + if (WARN("LINE_SPACING", + "Missing a blank line after declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } } } @@ -3646,12 +4118,16 @@ sub process { } # check indentation of a line with a break; -# if the previous line is a goto or return and is indented the same # of tabs +# if the previous line is a goto, return or break +# and is indented the same # of tabs if ($sline =~ /^\+([\t]+)break\s*;\s*$/) { my $tabs = $1; - if ($prevline =~ /^\+$tabs(?:goto|return)\b/) { - WARN("UNNECESSARY_BREAK", - "break is not useful after a goto or return\n" . $hereprev); + if ($prevline =~ /^\+$tabs(goto|return|break)\b/) { + if (WARN("UNNECESSARY_BREAK", + "break is not useful after a $1\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } } } @@ -3934,6 +4410,17 @@ sub process { #ignore lines not being added next if ($line =~ /^[^\+]/); +# check for self assignments used to avoid compiler warnings +# e.g.: int foo = foo, *bar = NULL; +# struct foo bar = *(&(bar)); + if ($line =~ /^\+\s*(?:$Declare)?([A-Za-z_][A-Za-z\d_]*)\s*=/) { + my $var = $1; + if ($line =~ /^\+\s*(?:$Declare)?$var\s*=\s*(?:$var|\*\s*\(?\s*&\s*\(?\s*$var\s*\)?\s*\)?)\s*[;,]/) { + WARN("SELF_ASSIGNMENT", + "Do not use self-assignments to avoid compiler warnings\n" . $herecurr); + } + } + # check for dereferences that span multiple lines if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ && $line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) { @@ -4049,8 +4536,7 @@ sub process { if (defined $realline_next && exists $lines[$realline_next - 1] && !defined $suppress_export{$realline_next} && - ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/)) { # Handle definitions which produce identifiers with # a prefix: # XXX(foo); @@ -4077,8 +4563,7 @@ sub process { } if (!defined $suppress_export{$linenr} && $prevline =~ /^.\s*$/ && - ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + ($line =~ /EXPORT_SYMBOL.*\((.*)\)/)) { #print "FOO B <$lines[$linenr - 1]>\n"; $suppress_export{$linenr} = 2; } @@ -4089,7 +4574,8 @@ sub process { } # check for global initialisers. - if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/) { + if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/ && + !exclude_global_initialisers($realfile)) { if (ERROR("GLOBAL_INITIALISERS", "do not initialise globals to $1\n" . $herecurr) && $fix) { @@ -4168,12 +4654,24 @@ sub process { } } +# check for const static or static <non ptr type> const declarations +# prefer 'static const <foo>' over 'const static <foo>' and 'static <foo> const' + if ($sline =~ /^\+\s*const\s+static\s+($Type)\b/ || + $sline =~ /^\+\s*static\s+($BasicType)\s+const\b/) { + if (WARN("STATIC_CONST", + "Move const after static - use 'static const $1'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bconst\s+static\b/static const/; + $fixed[$fixlinenr] =~ s/\bstatic\s+($BasicType)\s+const\b/static const $1/; + } + } + # check for non-global char *foo[] = {"bar", ...} declarations. if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) { WARN("STATIC_CONST_CHAR_ARRAY", "char * array declaration might be better as static const\n" . $herecurr); - } + } # check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo) if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) { @@ -4290,16 +4788,23 @@ sub process { "printk() should include KERN_<LEVEL> facility level\n" . $herecurr); } - if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { - my $orig = $1; +# prefer variants of (subsystem|netdev|dev|pr)_<level> to printk(KERN_<LEVEL> + if ($line =~ /\b(printk(_once|_ratelimited)?)\s*\(\s*KERN_([A-Z]+)/) { + my $printk = $1; + my $modifier = $2; + my $orig = $3; + $modifier = "" if (!defined($modifier)); my $level = lc($orig); $level = "warn" if ($level eq "warning"); my $level2 = $level; $level2 = "dbg" if ($level eq "debug"); + $level .= $modifier; + $level2 .= $modifier; WARN("PREFER_PR_LEVEL", - "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); + "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to $printk(KERN_$orig ...\n" . $herecurr); } +# prefer dev_<level> to dev_printk(KERN_<LEVEL> if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { my $orig = $1; my $level = lc($orig); @@ -4309,6 +4814,12 @@ sub process { "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); } +# trace_printk should not be used in production code. + if ($line =~ /\b(trace_printk|trace_puts|ftrace_vprintk)\s*\(/) { + WARN("TRACE_PRINTK", + "Do not use $1() in production code (this can be ignored if built only with a debug config option)\n" . $herecurr); + } + # ENOSYS means "bad syscall nr" and nothing else. This will have a small # number of false positives, but assembly files are not checked, so at # least the arch entry code will not trigger this warning. @@ -4317,6 +4828,17 @@ sub process { "ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr); } +# ENOTSUPP is not a standard error code and should be avoided in new patches. +# Folks usually mean EOPNOTSUPP (also called ENOTSUP), when they type ENOTSUPP. +# Similarly to ENOSYS warning a small number of false positives is expected. + if (!$file && $line =~ /\bENOTSUPP\b/) { + if (WARN("ENOTSUPP", + "ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bENOTSUPP\b/EOPNOTSUPP/; + } + } + # function brace can't be on same line, except for #defines of do while, # or if closed on same line if ($perl_version_ok && @@ -4328,7 +4850,7 @@ sub process { $fix) { fix_delete_line($fixlinenr, $rawline); my $fixed_line = $rawline; - $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*){(.*)$/; + $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*)\{(.*)$/; my $line1 = $1; my $line2 = $2; fix_insert_line($fixlinenr, ltrim($line1)); @@ -4739,7 +5261,7 @@ sub process { # A colon needs no spaces before when it is # terminating a case value or a label. } elsif ($opv eq ':C' || $opv eq ':L') { - if ($ctx =~ /Wx./) { + if ($ctx =~ /Wx./ and $realfile !~ m@.*\.lds\.h$@) { if (ERROR("SPACING", "space prohibited before that '$op' $at\n" . $hereptr)) { $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); @@ -4823,7 +5345,7 @@ sub process { ## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { ## ## # Remove any bracketed sections to ensure we do not -## # falsly report the parameters of functions. +## # falsely report the parameters of functions. ## my $ln = $line; ## while ($ln =~ s/\([^\(\)]*\)//g) { ## } @@ -4964,6 +5486,17 @@ sub process { } } +# check if a statement with a comma should be two statements like: +# foo = bar(), /* comma should be semicolon */ +# bar = baz(); + if (defined($stat) && + $stat =~ /^\+\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*,\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*;\s*$/) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + WARN("SUSPECT_COMMA_SEMICOLON", + "Possible comma where semicolon could be used\n" . $herectx); + } + # return is not a function if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { my $spacing = $1; @@ -4991,7 +5524,7 @@ sub process { $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) { WARN("RETURN_VOID", "void function return statements are not generally useful\n" . $hereprev); - } + } # if statements using unnecessary parentheses - ie: if ((foo == bar)) if ($perl_version_ok && @@ -5084,8 +5617,30 @@ sub process { my ($s, $c) = ($stat, $cond); if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { - ERROR("ASSIGN_IN_IF", - "do not use assignment in if condition\n" . $herecurr); + if (ERROR("ASSIGN_IN_IF", + "do not use assignment in if condition\n" . $herecurr) && + $fix && $perl_version_ok) { + if ($rawline =~ /^\+(\s+)if\s*\(\s*(\!)?\s*\(\s*(($Lval)\s*=\s*$LvalOrFunc)\s*\)\s*(?:($Compare)\s*($FuncArg))?\s*\)\s*(\{)?\s*$/) { + my $space = $1; + my $not = $2; + my $statement = $3; + my $assigned = $4; + my $test = $8; + my $against = $9; + my $brace = $15; + fix_delete_line($fixlinenr, $rawline); + fix_insert_line($fixlinenr, "$space$statement;"); + my $newline = "${space}if ("; + $newline .= '!' if defined($not); + $newline .= '(' if (defined $not && defined($test) && defined($against)); + $newline .= "$assigned"; + $newline .= " $test $against" if (defined($test) && defined($against)); + $newline .= ')' if (defined $not && defined($test) && defined($against)); + $newline .= ')'; + $newline .= " {" if (defined($brace)); + fix_insert_line($fixlinenr + 1, $newline); + } + } } # Find out what is on the end of the line after the @@ -5206,6 +5761,8 @@ sub process { #CamelCase if ($var !~ /^$Constant$/ && $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && +#Ignore some autogenerated defines and enum values + $var !~ /^(?:[A-Z]+_){1,5}[A-Z]{1,3}[a-z]/ && #Ignore Page<foo> variants $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && #Ignore SI style variants like nS, mV and dB @@ -5301,9 +5858,9 @@ sub process { $dstat =~ s/\s*$//s; # Flatten any parentheses and braces - while ($dstat =~ s/\([^\(\)]*\)/1/ || - $dstat =~ s/\{[^\{\}]*\}/1/ || - $dstat =~ s/.\[[^\[\]]*\]/1/) + while ($dstat =~ s/\([^\(\)]*\)/1u/ || + $dstat =~ s/\{[^\{\}]*\}/1u/ || + $dstat =~ s/.\[[^\[\]]*\]/1u/) { } @@ -5344,6 +5901,7 @@ sub process { $dstat !~ /^\.$Ident\s*=/ && # .foo = $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) + $dstat !~ /^while\s*$Constant\s*$Constant\s*$/ && # while (...) {...} $dstat !~ /^for\s*$Constant$/ && # for (...) $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() $dstat !~ /^do\s*{/ && # do {... @@ -5385,7 +5943,7 @@ sub process { next if ($arg =~ /\.\.\./); next if ($arg =~ /^type$/i); my $tmp_stmt = $define_stmt; - $tmp_stmt =~ s/\b(sizeof|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g; + $tmp_stmt =~ s/\b(__must_be_array|offsetof|sizeof|sizeof_field|__stringify|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g; $tmp_stmt =~ s/\#+\s*$arg\b//g; $tmp_stmt =~ s/\b$arg\s*\#\#//g; my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g; @@ -5662,6 +6220,17 @@ sub process { "Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr); } +# check for unnecessary function tracing like uses +# This does not use $logFunctions because there are many instances like +# 'dprintk(FOO, "%s()\n", __func__);' which do not match $logFunctions + if ($rawline =~ /^\+.*\([^"]*"$tracing_logging_tags{0,3}%s(?:\s*\(\s*\)\s*)?$tracing_logging_tags{0,3}(?:\\n)?"\s*,\s*__func__\s*\)\s*;/) { + if (WARN("TRACING_LOGGING", + "Unnecessary ftrace-like logging - prefer using ftrace\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + } + # check for spaces before a quoted newline if ($rawline =~ /^.*\".*\s\\n/) { if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", @@ -5808,6 +6377,28 @@ sub process { "Avoid logging continuation uses where feasible\n" . $herecurr); } +# check for unnecessary use of %h[xudi] and %hh[xudi] in logging functions + if (defined $stat && + $line =~ /\b$logFunctions\s*\(/ && + index($stat, '"') >= 0) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + pos($stat_real) = index($stat_real, '"'); + while ($stat_real =~ /[^\"%]*(%[\#\d\.\*\-]*(h+)[idux])/g) { + my $pspec = $1; + my $h = $2; + my $lineoff = substr($stat_real, 0, $-[1]) =~ tr@\n@@; + if (WARN("UNNECESSARY_MODIFIER", + "Integer promotion: Using '$h' in '$pspec' is unnecessary\n" . "$here\n$stat_real\n") && + $fix && $fixed[$fixlinenr + $lineoff] =~ /^\+/) { + my $nspec = $pspec; + $nspec =~ s/h//g; + $fixed[$fixlinenr + $lineoff] =~ s/\Q$pspec\E/$nspec/; + } + } + } + # check for mask then right shift without a parentheses if ($perl_version_ok && $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ && @@ -5966,8 +6557,7 @@ sub process { my $barriers = qr{ mb| rmb| - wmb| - read_barrier_depends + wmb }x; my $barrier_stems = qr{ mb__before_atomic| @@ -6008,10 +6598,12 @@ sub process { } } -# check for smp_read_barrier_depends and read_barrier_depends - if (!$file && $line =~ /\b(smp_|)read_barrier_depends\s*\(/) { - WARN("READ_BARRIER_DEPENDS", - "$1read_barrier_depends should only be used in READ_ONCE or DEC Alpha code\n" . $herecurr); +# check for data_race without a comment. + if ($line =~ /\bdata_race\s*\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("DATA_RACE", + "data_race without comment\n" . $herecurr); + } } # check of hardware specific defines @@ -6053,50 +6645,68 @@ sub process { } } -# Check for __attribute__ packed, prefer __packed - if ($realfile !~ m@\binclude/uapi/@ && - $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { - WARN("PREFER_PACKED", - "__packed is preferred over __attribute__((packed))\n" . $herecurr); - } - -# Check for __attribute__ aligned, prefer __aligned - if ($realfile !~ m@\binclude/uapi/@ && - $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { - WARN("PREFER_ALIGNED", - "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); - } - -# Check for __attribute__ section, prefer __section - if ($realfile !~ m@\binclude/uapi/@ && - $line =~ /\b__attribute__\s*\(\s*\(.*_*section_*\s*\(\s*("[^"]*")/) { - my $old = substr($rawline, $-[1], $+[1] - $-[1]); - my $new = substr($old, 1, -1); - if (WARN("PREFER_SECTION", - "__section(\"$new\") is preferred over __attribute__((section($old)))\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/; - } - } - -# Check for __attribute__ format(printf, prefer __printf +# Check for compiler attributes if ($realfile !~ m@\binclude/uapi/@ && - $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { - if (WARN("PREFER_PRINTF", - "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex; - + $rawline =~ /\b__attribute__\s*\(\s*($balanced_parens)\s*\)/) { + my $attr = $1; + $attr =~ s/\s*\(\s*(.*)\)\s*/$1/; + + my %attr_list = ( + "alias" => "__alias", + "aligned" => "__aligned", + "always_inline" => "__always_inline", + "assume_aligned" => "__assume_aligned", + "cold" => "__cold", + "const" => "__attribute_const__", + "copy" => "__copy", + "designated_init" => "__designated_init", + "externally_visible" => "__visible", + "format" => "printf|scanf", + "gnu_inline" => "__gnu_inline", + "malloc" => "__malloc", + "mode" => "__mode", + "no_caller_saved_registers" => "__no_caller_saved_registers", + "noclone" => "__noclone", + "noinline" => "noinline", + "nonstring" => "__nonstring", + "noreturn" => "__noreturn", + "packed" => "__packed", + "pure" => "__pure", + "section" => "__section", + "used" => "__used", + "weak" => "__weak" + ); + + while ($attr =~ /\s*(\w+)\s*(${balanced_parens})?/g) { + my $orig_attr = $1; + my $params = ''; + $params = $2 if defined($2); + my $curr_attr = $orig_attr; + $curr_attr =~ s/^[\s_]+|[\s_]+$//g; + if (exists($attr_list{$curr_attr})) { + my $new = $attr_list{$curr_attr}; + if ($curr_attr eq "format" && $params) { + $params =~ /^\s*\(\s*(\w+)\s*,\s*(.*)/; + $new = "__$1\($2"; + } else { + $new = "$new$params"; + } + if (WARN("PREFER_DEFINED_ATTRIBUTE_MACRO", + "Prefer $new over __attribute__(($orig_attr$params))\n" . $herecurr) && + $fix) { + my $remove = "\Q$orig_attr\E" . '\s*' . "\Q$params\E" . '(?:\s*,\s*)?'; + $fixed[$fixlinenr] =~ s/$remove//; + $fixed[$fixlinenr] =~ s/\b__attribute__/$new __attribute__/; + $fixed[$fixlinenr] =~ s/\}\Q$new\E/} $new/; + $fixed[$fixlinenr] =~ s/ __attribute__\s*\(\s*\(\s*\)\s*\)//; + } + } } - } -# Check for __attribute__ format(scanf, prefer __scanf - if ($realfile !~ m@\binclude/uapi/@ && - $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { - if (WARN("PREFER_SCANF", - "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex; + # Check for __attribute__ unused, prefer __always_unused or __maybe_unused + if ($attr =~ /^_*unused/) { + WARN("PREFER_DEFINED_ATTRIBUTE_MACRO", + "__always_unused or __maybe_unused is preferred over __attribute__((__unused__))\n" . $herecurr); } } @@ -6132,18 +6742,18 @@ sub process { if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) { my $cast = $1; my $const = $2; + my $suffix = ""; + my $newconst = $const; + $newconst =~ s/${Int_type}$//; + $suffix .= 'U' if ($cast =~ /\bunsigned\b/); + if ($cast =~ /\blong\s+long\b/) { + $suffix .= 'LL'; + } elsif ($cast =~ /\blong\b/) { + $suffix .= 'L'; + } if (WARN("TYPECAST_INT_CONSTANT", - "Unnecessary typecast of c90 int constant\n" . $herecurr) && + "Unnecessary typecast of c90 int constant - '$cast$const' could be '$const$suffix'\n" . $herecurr) && $fix) { - my $suffix = ""; - my $newconst = $const; - $newconst =~ s/${Int_type}$//; - $suffix .= 'U' if ($cast =~ /\bunsigned\b/); - if ($cast =~ /\blong\s+long\b/) { - $suffix .= 'LL'; - } elsif ($cast =~ /\blong\b/) { - $suffix .= 'L'; - } $fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/; } } @@ -6203,9 +6813,11 @@ sub process { $specifier = $1; $extension = $2; $qualifier = $3; - if ($extension !~ /[SsBKRraEehMmIiUDdgVCbGNOxtf]/ || + if ($extension !~ /[4SsBKRraEehMmIiUDdgVCbGNOxtf]/ || ($extension eq "f" && - defined $qualifier && $qualifier !~ /^w/)) { + defined $qualifier && $qualifier !~ /^w/) || + ($extension eq "4" && + defined $qualifier && $qualifier !~ /^cc/)) { $bad_specifier = $specifier; last; } @@ -6385,8 +6997,7 @@ sub process { if (defined $cond) { substr($s, 0, length($cond), ''); } - if ($s =~ /^\s*;/ && - $function_name ne 'uninitialized_var') + if ($s =~ /^\s*;/) { WARN("AVOID_EXTERNS", "externs should be avoided in .c files\n" . $herecurr); @@ -6405,17 +7016,13 @@ sub process { } # check for function declarations that have arguments without identifier names -# while avoiding uninitialized_var(x) if (defined $stat && - $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:($Ident)|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && - (!defined($1) || - (defined($1) && $1 ne "uninitialized_var")) && - $2 ne "void") { - my $args = trim($2); + $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && + $1 ne "void") { + my $args = trim($1); while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) { my $arg = trim($1); - if ($arg =~ /^$Type$/ && - $arg !~ /enum\s+$Ident$/) { + if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) { WARN("FUNCTION_ARGUMENTS", "function definition argument '$arg' should also have an identifier name\n" . $herecurr); } @@ -6451,7 +7058,7 @@ sub process { if (!grep(/$name/, @setup_docs)) { CHK("UNDOCUMENTED_SETUP", - "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.rst\n" . $herecurr); + "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.txt\n" . $herecurr); } } @@ -6507,7 +7114,7 @@ sub process { } # check for alloc argument mismatch - if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { + if ($line =~ /\b((?:devm_)?(?:kcalloc|kmalloc_array))\s*\(\s*sizeof\b/) { WARN("ALLOC_ARRAY_ARGS", "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); } @@ -6533,41 +7140,22 @@ sub process { } } +# check for IS_ENABLED() without CONFIG_<FOO> ($rawline for comments too) + if ($rawline =~ /\bIS_ENABLED\s*\(\s*(\w+)\s*\)/ && $1 !~ /^${CONFIG_}/) { + WARN("IS_ENABLED_CONFIG", + "IS_ENABLED($1) is normally used as IS_ENABLED(${CONFIG_}$1)\n" . $herecurr); + } + # check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE - if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { + if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(${CONFIG_}[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { my $config = $1; if (WARN("PREFER_IS_ENABLED", - "Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE\n" . $herecurr) && + "Prefer IS_ENABLED(<FOO>) to ${CONFIG_}<FOO> || ${CONFIG_}<FOO>_MODULE\n" . $herecurr) && $fix) { $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)"; } } -# check for case / default statements not preceded by break/fallthrough/switch - if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { - my $has_break = 0; - my $has_statement = 0; - my $count = 0; - my $prevline = $linenr; - while ($prevline > 1 && ($file || $count < 3) && !$has_break) { - $prevline--; - my $rline = $rawlines[$prevline - 1]; - my $fline = $lines[$prevline - 1]; - last if ($fline =~ /^\@\@/); - next if ($fline =~ /^\-/); - next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/); - $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i); - next if ($fline =~ /^.[\s$;]*$/); - $has_statement = 1; - $count++; - $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|exit\s*\(\b|return\b|goto\b|continue\b)/); - } - if (!$has_break && $has_statement) { - WARN("MISSING_BREAK", - "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr); - } - } - # check for /* fallthrough */ like comment, prefer fallthrough; my @fallthroughs = ( 'fallthrough', @@ -6683,7 +7271,8 @@ sub process { # check for various structs that are normally const (ops, kgdb, device_tree) # and avoid what seem like struct definitions 'struct foo {' - if ($line !~ /\bconst\b/ && + if (defined($const_structs) && + $line !~ /\bconst\b/ && $line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) { WARN("CONST_STRUCT", "struct $1 should normally be const\n" . $herecurr); @@ -6691,12 +7280,14 @@ sub process { # use of NR_CPUS is usually wrong # ignore definitions of NR_CPUS and usage to define arrays as likely right +# ignore designated initializers using NR_CPUS if ($line =~ /\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && - $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) + $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/ && + $line !~ /^.\s*\.\w+\s*=\s*.*\bNR_CPUS\b/) { WARN("NR_CPUS", "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); @@ -6715,6 +7306,17 @@ sub process { "Using $1 should generally have parentheses around the comparison\n" . $herecurr); } +# return sysfs_emit(foo, fmt, ...) fmt without newline + if ($line =~ /\breturn\s+sysfs_emit\s*\(\s*$FuncArg\s*,\s*($String)/ && + substr($rawline, $-[6], $+[6] - $-[6]) !~ /\\n"$/) { + my $offset = $+[6] - 1; + if (WARN("SYSFS_EMIT", + "return sysfs_emit(...) formats should include a terminating newline\n" . $herecurr) && + $fix) { + substr($fixed[$fixlinenr], $offset, 0) = '\\n'; + } + } + # nested likely/unlikely calls if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) { WARN("LIKELY_MISUSE", @@ -6732,12 +7334,6 @@ sub process { } } -# check for mutex_trylock_recursive usage - if ($line =~ /mutex_trylock_recursive/) { - ERROR("LOCKING", - "recursive locking is bad, do not use this ever.\n" . $herecurr); - } - # check for lockdep_set_novalidate_class if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ || $line =~ /__lockdep_no_validate__\s*\)/ ) { @@ -6900,7 +7496,7 @@ sub process { exit(0); } - # This is not a patch, and we are are in 'no-patch' mode so + # This is not a patch, and we are in 'no-patch' mode so # just keep quiet. if (!$chk_patch && !$is_patch) { exit(0); @@ -6914,9 +7510,33 @@ sub process { if ($signoff == 0) { ERROR("MISSING_SIGN_OFF", "Missing Signed-off-by: line(s)\n"); - } elsif (!$authorsignoff) { - WARN("NO_AUTHOR_SIGN_OFF", - "Missing Signed-off-by: line by nominal patch author '$author'\n"); + } elsif ($authorsignoff != 1) { + # authorsignoff values: + # 0 -> missing sign off + # 1 -> sign off identical + # 2 -> names and addresses match, comments mismatch + # 3 -> addresses match, names different + # 4 -> names match, addresses different + # 5 -> names match, addresses excluding subaddress details (refer RFC 5233) match + + my $sob_msg = "'From: $author' != 'Signed-off-by: $author_sob'"; + + if ($authorsignoff == 0) { + ERROR("NO_AUTHOR_SIGN_OFF", + "Missing Signed-off-by: line by nominal patch author '$author'\n"); + } elsif ($authorsignoff == 2) { + CHK("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email comments mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 3) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email name mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 4) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email address mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 5) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email subaddress mismatch: $sob_msg\n"); + } } } diff --git a/scripts/coccinelle/net/mdio_register.cocci b/scripts/coccinelle/net/mdio_register.cocci index 100f10293610950cdc484c6d1457e427ca7790d0..7d11281f4678bd3b98b648228553a5333992f7f4 100644 --- a/scripts/coccinelle/net/mdio_register.cocci +++ b/scripts/coccinelle/net/mdio_register.cocci @@ -16,12 +16,12 @@ identifier readfunc, writefunc; - miiphy_register(devname, readfunc, writefunc); + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; -+ strncpy(mdiodev->name, devname, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, devname, MDIO_NAME_LEN); + mdiodev->read = readfunc; + mdiodev->write = writefunc; + + retval = mdio_register(mdiodev); -+ if (retval < 0) return retval; ++ if (retval < 0) { mdio_free(mdiodev); return retval; } @ update_read_sig @ identifier mii_reg.readfunc; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a9c2380d17e287d624506a9c294278d61503b529..5bcd2c26c4175c4724dfac4cf7bd85c8d36f34ab 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,34 +1,16 @@ -CONFIG_16BIT CONFIG_64BIT_PHYS_ADDR -CONFIG_8349_CLKIN CONFIG_83XX -CONFIG_83XX_CLKIN -CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES CONFIG_83XX_PCICLK -CONFIG_83XX_PCI_STREAMING CONFIG_88F5182 CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND -CONFIG_ACX517AKN -CONFIG_ACX544AKN -CONFIG_ADDRESS -CONFIG_ADDR_AUTO_INCR_BIT -CONFIG_ADNPESC1 CONFIG_AEABI -CONFIG_AEMIF_CNTRL_BASE -CONFIG_ALTERA_SPI_IDLE_VAL -CONFIG_ALU CONFIG_AM335X_USB0 CONFIG_AM335X_USB0_MODE CONFIG_AM335X_USB1 CONFIG_AM335X_USB1_MODE -CONFIG_AM437X_USB2PHY2_HOST CONFIG_ANDES_PCU CONFIG_ANDES_PCU_BASE -CONFIG_APER_0_BASE -CONFIG_APER_1_BASE -CONFIG_APER_SIZE -CONFIG_APUS_FAST_EXCEPT CONFIG_ARCH_ADPAG101P CONFIG_ARCH_HAS_ILOG2_U32 CONFIG_ARCH_HAS_ILOG2_U64 @@ -37,22 +19,12 @@ CONFIG_ARCH_OMAP4 CONFIG_ARCH_RMOBILE_EXTRAM_BOOT CONFIG_ARCH_USE_BUILTIN_BSWAP CONFIG_ARC_MMU_VER -CONFIG_ARMADA100 -CONFIG_ARMADA168 CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE CONFIG_ARMV7_SECURE_RESERVE_SIZE CONFIG_ARMV8_SWITCH_TO_EL1 -CONFIG_ARM_ARCH_CP15_ERRATA CONFIG_ARM_GIC_BASE_ADDRESS -CONFIG_ARM_PL180_MMCI_BASE -CONFIG_ARM_PL180_MMCI_CLOCK_FREQ CONFIG_ARP_TIMEOUT -CONFIG_ASTRO_COFDMDUOS2 -CONFIG_ASTRO_TWIN7S2 -CONFIG_ASTRO_V512 -CONFIG_ASTRO_V532 -CONFIG_ASTRO_V912 CONFIG_AT91C_PQFP_UHPBUG CONFIG_AT91RESET_EXTRST CONFIG_AT91RM9200 @@ -77,7 +49,6 @@ CONFIG_ATMEL_LCD_RGB565 CONFIG_ATMEL_LEGACY CONFIG_ATMEL_MCI_8BIT CONFIG_ATMEL_SPI0 -CONFIG_AT_TRANS CONFIG_AUTO_ZRELADDR CONFIG_BACKSIDE_L2_CACHE CONFIG_BCH_CONST_M @@ -101,7 +72,6 @@ CONFIG_BOARD_NAME CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_SIZE_LIMIT CONFIG_BOOGER -CONFIG_BOOTBLOCK CONFIG_BOOTFILE CONFIG_BOOTMODE CONFIG_BOOTP_ @@ -119,7 +89,6 @@ CONFIG_BOOTSCRIPT_ADDR CONFIG_BOOTSCRIPT_COPY_RAM CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BOOTSCRIPT_KEY_HASH -CONFIG_BOOT_MODE_BIT CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME CONFIG_BPTR_VIRT_ADDR @@ -132,7 +101,6 @@ CONFIG_BS_HDR_ADDR_RAM CONFIG_BS_HDR_SIZE CONFIG_BS_SIZE CONFIG_BTB -CONFIG_BUFNO_AUTO_INCR_BIT CONFIG_BUILD_ENVCRC CONFIG_BUS_WIDTH CONFIG_CDP_APPLIANCE_VLAN_TYPE @@ -166,16 +134,11 @@ CONFIG_CLOCKS CONFIG_CLOCK_SYNTHESIZER CONFIG_CM922T_XA10 CONFIG_CMDLINE_PS_SUPPORT -CONFIG_CMDLINE_TAG CONFIG_CM_INIT CONFIG_CM_MULTIPLE_SSRAM CONFIG_CM_REMAP CONFIG_CM_SPD_DETECT -CONFIG_CM_T335 -CONFIG_CM_T3X -CONFIG_CM_T43 CONFIG_CM_TCRAM -CONFIG_CNTL CONFIG_COLDFIRE CONFIG_COMMANDS CONFIG_COMMON_BOOT @@ -222,20 +185,6 @@ CONFIG_DB_784MP_GP CONFIG_DCACHE CONFIG_DCACHE_OFF CONFIG_DCFG_ADDR -CONFIG_DDR3 -CONFIG_DDR_2T_TIMING -CONFIG_DDR_32BIT -CONFIG_DDR_64BIT -CONFIG_DDR_CLK_FREQ -CONFIG_DDR_DEFAULT_CL -CONFIG_DDR_ECC -CONFIG_DDR_ECC_CMD -CONFIG_DDR_ECC_INIT_VIA_DMA -CONFIG_DDR_FIXED_SIZE -CONFIG_DDR_II -CONFIG_DDR_LOG_LEVEL -CONFIG_DDR_MB -CONFIG_DDR_SPD CONFIG_DEBUG CONFIG_DEBUG_FS CONFIG_DEBUG_LED @@ -266,38 +215,14 @@ CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT CONFIG_DMA_COHERENT CONFIG_DMA_COHERENT_SIZE -CONFIG_DMA_LPC32XX CONFIG_DMA_NONCOHERENT -CONFIG_DMA_REQ_BIT CONFIG_DNET_AUTONEG_TIMEOUT CONFIG_DP_DDR_CTRL CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR CONFIG_DP_DDR_NUM_CTRLS CONFIG_DRAM_TIMINGS_ -CONFIG_DRIVER_AT91EMAC_PHYADDR -CONFIG_DRIVER_AT91EMAC_QUIET CONFIG_DRIVER_DM9000 CONFIG_DSP_CLUSTER_START -CONFIG_DWC2_DFLT_SPEED_FULL -CONFIG_DWC2_DMA_BURST_SIZE -CONFIG_DWC2_DMA_ENABLE -CONFIG_DWC2_ENABLE_DYNAMIC_FIFO -CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE -CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE -CONFIG_DWC2_HOST_RX_FIFO_SIZE -CONFIG_DWC2_I2C_ENABLE -CONFIG_DWC2_IC_USB_CAP -CONFIG_DWC2_MAX_CHANNELS -CONFIG_DWC2_MAX_PACKET_COUNT -CONFIG_DWC2_MAX_TRANSFER_SIZE -CONFIG_DWC2_PHY_TYPE -CONFIG_DWC2_PHY_ULPI_DDR -CONFIG_DWC2_PHY_ULPI_EXT_VBUS -CONFIG_DWC2_THR_CTL -CONFIG_DWC2_TS_DLINE -CONFIG_DWC2_TX_THR_LENGTH -CONFIG_DWC2_ULPI_FS_LS -CONFIG_DWC2_UTMI_WIDTH CONFIG_DWCDDR21MCTL CONFIG_DWCDDR21MCTL_BASE CONFIG_DWC_AHSATA_BASE_ADDR @@ -312,12 +237,6 @@ CONFIG_E1000_NO_NVM CONFIG_E300 CONFIG_E5500 CONFIG_ECC -CONFIG_ECC_INIT_VIA_DDRCONTROLLER -CONFIG_ECC_MODE_MASK -CONFIG_ECC_MODE_SHIFT -CONFIG_ECC_SRAM_ADDR_MASK -CONFIG_ECC_SRAM_ADDR_SHIFT -CONFIG_ECC_SRAM_REQ_BIT CONFIG_EDB9301 CONFIG_EDB93XX_INDUSTRIAL CONFIG_EDB93XX_SDCS0 @@ -338,11 +257,8 @@ CONFIG_ENABLE_MUST_CHECK CONFIG_ENV_ADDR_FLEX CONFIG_ENV_CALLBACK_LIST_DEFAULT CONFIG_ENV_CALLBACK_LIST_STATIC -CONFIG_ENV_COMMON_BOOT -CONFIG_ENV_EEPROM_IS_ON_I2C CONFIG_ENV_FLAGS_LIST_DEFAULT CONFIG_ENV_FLAGS_LIST_STATIC -CONFIG_ENV_FLASHBOOT CONFIG_ENV_IS_EMBEDDED CONFIG_ENV_IS_IN_ CONFIG_ENV_MAX_ENTRIES @@ -358,8 +274,6 @@ CONFIG_ENV_SETTINGS_V2 CONFIG_ENV_SIZE_FLEX CONFIG_ENV_SROM_BANK CONFIG_ENV_TOTAL_SIZE -CONFIG_ENV_UBIFS_OPTION -CONFIG_ENV_UBI_MTD CONFIG_ENV_VERSION CONFIG_EPH_POWER_EN CONFIG_EPOLL @@ -372,20 +286,11 @@ CONFIG_ESPRESSO7420 CONFIG_ET1100_BASE CONFIG_ETHADDR CONFIG_ETHBASE -CONFIG_ETHER_INDEX -CONFIG_ETHER_NONE -CONFIG_ETHER_ON_FCC -CONFIG_ETHER_ON_FCC1 -CONFIG_ETHER_ON_FCC2 -CONFIG_ETHER_ON_FCC3 CONFIG_ETHPRIME CONFIG_ETH_BUFSIZE CONFIG_ETH_RXSIZE CONFIG_EXTRA_CLOCK CONFIG_EXTRA_ENV -CONFIG_EXTRA_ENV_BOARD_SETTINGS -CONFIG_EXTRA_ENV_ITB -CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS_COMMON CONFIG_EXT_AHB2AHB_BASE @@ -410,7 +315,6 @@ CONFIG_EXYNOS_RELOCATE_CODE_BASE CONFIG_EXYNOS_SPL CONFIG_EXYNOS_TMU CONFIG_FACTORYSET -CONFIG_FAST_FLASH_BIT CONFIG_FB_ADDR CONFIG_FB_BACKLIGHT CONFIG_FB_DEFERRED_IO @@ -455,7 +359,6 @@ CONFIG_FSL_DEEP_SLEEP CONFIG_FSL_DEVICE_DISABLE CONFIG_FSL_DIU_CH7301 CONFIG_FSL_DIU_FB -CONFIG_FSL_DMA CONFIG_FSL_DSPI1 CONFIG_FSL_ESDHC_PIN_MUX CONFIG_FSL_FIXED_MMC_LOCATION @@ -520,7 +423,6 @@ CONFIG_FTWDT010_BASE CONFIG_FTWDT010_WATCHDOG CONFIG_FZOTG266HD0A_BASE CONFIG_GATEWAYIP -CONFIG_GICV2 CONFIG_GLOBAL_DATA_NOT_REG10 CONFIG_GLOBAL_TIMER CONFIG_GMII @@ -541,7 +443,6 @@ CONFIG_HAS_ETH3 CONFIG_HAS_FEC CONFIG_HAS_FSL_DR_USB CONFIG_HAS_FSL_MPH_USB -CONFIG_HDBOOT CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_HETROGENOUS_CLUSTERS CONFIG_HIDE_LOGO_VERSION @@ -694,7 +595,6 @@ CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP CONFIG_HSMMC2_8BIT CONFIG_HUSH_INIT_VAR -CONFIG_HVBOOT CONFIG_HWCONFIG CONFIG_HW_ENV_SETTINGS CONFIG_I2C_ENV_EEPROM_BUS @@ -718,15 +618,12 @@ CONFIG_ICS307_REFCLK_HZ CONFIG_IDE_PREINIT CONFIG_IDE_RESET CONFIG_IDE_SWAP_IO -CONFIG_ID_EEPROM CONFIG_IMA CONFIG_IMX CONFIG_IMX6_PWM_PER_CLK CONFIG_IMX_HDMI -CONFIG_IMX_NAND CONFIG_IMX_VIDEO_SKIP CONFIG_INETSPACE_V2 -CONFIG_INITRD_TAG CONFIG_INIT_IGNORE_ERROR CONFIG_INI_ALLOW_MULTILINE CONFIG_INI_CASE_INSENSITIVE @@ -757,20 +654,13 @@ CONFIG_JFFS2_PART_SIZE CONFIG_JFFS2_SUMMARY CONFIG_JRSTARTR_JR0 CONFIG_JTAG_CONSOLE -CONFIG_KCLK_DIS CONFIG_KEEP_SERVERADDR CONFIG_KEYBOARD -CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE -CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE -CONFIG_KEYSTONE_RBL_NAND CONFIG_KEY_REVOCATION -CONFIG_KGDB_BAUDRATE -CONFIG_KGDB_SER_INDEX CONFIG_KIRKWOOD_EGIGA_INIT CONFIG_KIRKWOOD_GPIO CONFIG_KIRKWOOD_PCIE_INIT CONFIG_KIRKWOOD_RGMII_PAD_1V8 -CONFIG_KIRQ_EN CONFIG_KM8321 CONFIG_KMTEGR1 CONFIG_KM_BOARD_EXTRA_ENV @@ -800,32 +690,6 @@ CONFIG_KM_UBI_PARTITION_NAME_BOOT CONFIG_KM_UBI_PART_BOOT_OPTS CONFIG_KM_UIMAGE_NAME CONFIG_KM_UPDATE_UBOOT -CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE -CONFIG_KSNAV_NETCP_PDMA_RX_BASE -CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM -CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE -CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM -CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE -CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE -CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE -CONFIG_KSNAV_NETCP_PDMA_TX_BASE -CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM -CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE -CONFIG_KSNAV_PKTDMA_NETCP -CONFIG_KSNAV_QM_BASE_ADDRESS -CONFIG_KSNAV_QM_CONF_BASE -CONFIG_KSNAV_QM_DESC_SETUP_BASE -CONFIG_KSNAV_QM_INTD_CONF_BASE -CONFIG_KSNAV_QM_LINK_RAM_BASE -CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE -CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE -CONFIG_KSNAV_QM_PDSP1_CMD_BASE -CONFIG_KSNAV_QM_PDSP1_CTRL_BASE -CONFIG_KSNAV_QM_PDSP1_IRAM_BASE -CONFIG_KSNAV_QM_QPOOL_NUM -CONFIG_KSNAV_QM_QUEUE_STATUS_BASE -CONFIG_KSNAV_QM_REGION_NUM -CONFIG_KSNAV_QM_STATUS_RAM_BASE CONFIG_KSNET_CPSW_NUM_PORTS CONFIG_KSNET_MAC_ID_BASE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE @@ -856,10 +720,8 @@ CONFIG_LCD_MENU CONFIG_LD9040 CONFIG_LEGACY CONFIG_LEGACY_BOOTCMD_ENV -CONFIG_LINUX CONFIG_LITTLETON_LCD CONFIG_LMS283GF05 -CONFIG_LOADADDR CONFIG_LOADS_ECHO CONFIG_LOWPOWER_ADDR CONFIG_LOWPOWER_FLAG @@ -895,14 +757,10 @@ CONFIG_M41T94_SPI_CS CONFIG_M520x CONFIG_M5301x CONFIG_MACB_SEARCH_PHY -CONFIG_MACH_OMAPL138_LCDK -CONFIG_MACH_TYPE -CONFIG_MACH_TYPE_COMPAT_REV CONFIG_MACRESET_TIMEOUT CONFIG_MALLOC_F_ADDR CONFIG_MALTA CONFIG_MARCO_MEMSET -CONFIG_MARVELL_MFP CONFIG_MASK_AER_AO CONFIG_MAX_DSP_CPUS CONFIG_MAX_FPGA_DEVICES @@ -913,11 +771,8 @@ CONFIG_MCF5249 CONFIG_MCF5253 CONFIG_MCFRTC CONFIG_MCFTMR -CONFIG_MCLK_DIS CONFIG_MDIO_TIMEOUT -CONFIG_MEMSIZE CONFIG_MEMSIZE_IN_BYTES -CONFIG_MEMSIZE_MASK CONFIG_MEM_HOLE_16M CONFIG_MEM_INIT_VALUE CONFIG_MEM_REMAP @@ -926,13 +781,11 @@ CONFIG_MII_DEFAULT_TSEC CONFIG_MII_INIT CONFIG_MIPS_HUGE_TLB_SUPPORT CONFIG_MIPS_MT_FPAFF -CONFIG_MIRQ_EN CONFIG_MISC_COMMON CONFIG_MIU_1BIT_INTERLEAVED CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED CONFIG_MIU_LINEAR -CONFIG_MMCBOOTCOMMAND CONFIG_MMCROOT CONFIG_MMC_DEFAULT_DEV CONFIG_MMC_RPMB_TRACE @@ -945,7 +798,6 @@ CONFIG_MPC83XX_GPIO_0_INIT_VALUE CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN CONFIG_MPC83XX_GPIO_1_INIT_VALUE -CONFIG_MPC83XX_PCI2 CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME CONFIG_MPC8xxx_DISABLE_BPTR @@ -973,15 +825,10 @@ CONFIG_MVS CONFIG_MV_ETH_RXQ CONFIG_MV_I2C_NUM CONFIG_MV_I2C_REG -CONFIG_MX25_CLK32 -CONFIG_MX25_HCLK_FREQ CONFIG_MX27 CONFIG_MX27_CLK32 CONFIG_MX27_TIMER_HIGH_PRECISION CONFIG_MX28_FEC_MAC_IN_OCOTP -CONFIG_MX35 -CONFIG_MX35_CLK32 -CONFIG_MX35_HCLK_FREQ CONFIG_MXC_EPDC CONFIG_MXC_GPT_HCLK CONFIG_MXC_NAND_HWECC @@ -1046,16 +893,9 @@ CONFIG_NUM_PAMU CONFIG_ODROID_REV_AIN CONFIG_OFF_PADCONF CONFIG_OF_ -CONFIG_OMAP_EHCI_PHY1_RESET_GPIO -CONFIG_OMAP_EHCI_PHY2_RESET_GPIO -CONFIG_OMAP_EHCI_PHY3_RESET_GPIO -CONFIG_OMAP_USB2PHY2_HOST -CONFIG_OMAP_USB3PHY1_HOST CONFIG_ORIGEN CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_PAGE_CNT_MASK -CONFIG_PAGE_CNT_SHIFT CONFIG_PALMAS_AUDPWR CONFIG_PALMAS_POWER CONFIG_PALMAS_SMPS7_FPWM @@ -1073,7 +913,6 @@ CONFIG_PCIE4 CONFIG_PCIE_IMX CONFIG_PCIE_IMX_PERST_GPIO CONFIG_PCIE_IMX_POWER_GPIO -CONFIG_PCISLAVE CONFIG_PCI_BOOTDELAY CONFIG_PCI_CLK_FREQ CONFIG_PCI_CONFIG_HOST_BRIDGE @@ -1110,7 +949,6 @@ CONFIG_PIXIS_SGMII_CMD CONFIG_PL011_CLOCK CONFIG_PL011_SERIAL_RLCR CONFIG_PL01x_PORTS -CONFIG_PLATFORM_ENV_SETTINGS CONFIG_PM CONFIG_PMC_BR_PRELIM CONFIG_PMC_OR_PRELIM @@ -1129,11 +967,9 @@ CONFIG_POST_EXTERNAL_WORD_FUNCS CONFIG_POST_SKIP_ENV_FLAGS CONFIG_POST_UART CONFIG_POST_WATCHDOG -CONFIG_POWER CONFIG_POWER_FSL CONFIG_POWER_FSL_MC13892 CONFIG_POWER_HI6553 -CONFIG_POWER_I2C CONFIG_POWER_LTC3676 CONFIG_POWER_LTC3676_I2C_ADDR CONFIG_POWER_MAX77696_I2C_ADDR @@ -1155,7 +991,6 @@ CONFIG_PRINTK CONFIG_PROC_FS CONFIG_PROFILE_ALL_BRANCHES CONFIG_PROFILING -CONFIG_PROOF_POINTS CONFIG_PSRAM_SCFG CONFIG_PWM CONFIG_PXA_LCD @@ -1169,7 +1004,6 @@ CONFIG_QSPI CONFIG_QUOTA CONFIG_RAMBOOTCOMMAND CONFIG_RAMBOOT_NAND -CONFIG_RAMBOOT_PBL CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RAMDISKFILE @@ -1180,11 +1014,9 @@ CONFIG_REALMODE_DEBUG CONFIG_RED_LED CONFIG_REG CONFIG_REG_0 -CONFIG_REG_1_BASE CONFIG_REG_2 CONFIG_REG_3 CONFIG_REG_8 -CONFIG_REG_APER_SIZE CONFIG_REMAKE_ELF CONFIG_REQ CONFIG_RESERVED_01_BASE @@ -1196,7 +1028,6 @@ CONFIG_RESET_TO_RETRY CONFIG_RESET_VECTOR_ADDRESS CONFIG_RESTORE_FLASH CONFIG_RES_BLOCK_SIZE -CONFIG_REVISION_TAG CONFIG_RMII CONFIG_RMSTP0_ENA CONFIG_RMSTP10_ENA @@ -1237,7 +1068,6 @@ CONFIG_S5PC100 CONFIG_S5PC110 CONFIG_S5P_PA_SYSRAM CONFIG_S6E8AX0 -CONFIG_SABRELITE CONFIG_SAMA5D3_LCD_BASE CONFIG_SAMSUNG CONFIG_SAMSUNG_ONENAND @@ -1270,21 +1100,16 @@ CONFIG_SERIAL_FLASH CONFIG_SERIAL_HW_FLOW_CONTROL CONFIG_SERIAL_MULTI CONFIG_SERIAL_SOFTWARE_FIFO -CONFIG_SERIAL_TAG CONFIG_SERIRQ_CONTINUOUS_MODE CONFIG_SERVERIP CONFIG_SETUP_INITRD_TAG -CONFIG_SETUP_MEMORY_TAGS -CONFIG_SET_BIST CONFIG_SET_BOOTARGS CONFIG_SET_DFU_ALT_BUF_LEN -CONFIG_SFIO CONFIG_SGI_IP28 CONFIG_SH73A0 CONFIG_SH7751_PCI CONFIG_SHARP_LM8V31 CONFIG_SHEEVA_88SV131 -CONFIG_SHEEVA_88SV331xV5 CONFIG_SH_CMT_CLK_FREQ CONFIG_SH_DSP CONFIG_SH_ETHER_ALIGNE_SIZE @@ -1296,19 +1121,12 @@ CONFIG_SH_ETHER_PHY_MODE CONFIG_SH_ETHER_SH7734_MII CONFIG_SH_ETHER_USE_PORT CONFIG_SH_GPIO_PFC -CONFIG_SH_I2C_8BIT -CONFIG_SH_I2C_CLOCK -CONFIG_SH_I2C_DATA_HIGH -CONFIG_SH_I2C_DATA_LOW CONFIG_SH_MMCIF_CLK CONFIG_SH_QSPI_BASE CONFIG_SH_SCIF_CLK_FREQ CONFIG_SH_SDHI_FREQ CONFIG_SH_SDRAM_OFFSET -CONFIG_SIEMENS_MACH_TYPE CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION -CONFIG_SKIP_LOWLEVEL_INIT -CONFIG_SKIP_LOWLEVEL_INIT_ONLY CONFIG_SKIP_TRUNOFF_WATCHDOG CONFIG_SLIC CONFIG_SLTTMR @@ -1335,11 +1153,6 @@ CONFIG_SMSTP7_ENA CONFIG_SMSTP8_ENA CONFIG_SMSTP9_ENA CONFIG_SOCRATES -CONFIG_SOC_K2E -CONFIG_SOC_K2G -CONFIG_SOC_K2HK -CONFIG_SOC_K2L -CONFIG_SOC_KEYSTONE CONFIG_SOC_OMAP3430 CONFIG_SOFT_I2C_GPIO_SCL CONFIG_SOFT_I2C_GPIO_SDA @@ -1446,7 +1259,6 @@ CONFIG_SYS_AMASK4 CONFIG_SYS_AMASK5 CONFIG_SYS_AMASK6 CONFIG_SYS_AMASK7 -CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK CONFIG_SYS_AT91_PLLA CONFIG_SYS_AT91_PLLB @@ -1459,10 +1271,6 @@ CONFIG_SYS_ATA_IDE1_OFFSET CONFIG_SYS_ATA_PORT_ADDR CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_STRIDE -CONFIG_SYS_ATI_REV_A11 -CONFIG_SYS_ATI_REV_A12 -CONFIG_SYS_ATI_REV_A13 -CONFIG_SYS_ATI_REV_ID_MASK CONFIG_SYS_ATMEL_CPU_NAME CONFIG_SYS_AUTOLOAD CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION @@ -1528,12 +1336,6 @@ CONFIG_SYS_CMD_EL CONFIG_SYS_CMD_IAS CONFIG_SYS_CMD_INT CONFIG_SYS_CMD_SUSPEND -CONFIG_SYS_CMXFCR_MASK1 -CONFIG_SYS_CMXFCR_MASK2 -CONFIG_SYS_CMXFCR_MASK3 -CONFIG_SYS_CMXFCR_VALUE1 -CONFIG_SYS_CMXFCR_VALUE2 -CONFIG_SYS_CMXFCR_VALUE3 CONFIG_SYS_CORE_SRAM CONFIG_SYS_CORE_SRAM_SIZE CONFIG_SYS_CPC_REINIT_F @@ -1548,7 +1350,6 @@ CONFIG_SYS_CPLD_FTIM1 CONFIG_SYS_CPLD_FTIM2 CONFIG_SYS_CPLD_FTIM3 CONFIG_SYS_CPLD_SIZE -CONFIG_SYS_CPMFCR_RAMTYPE CONFIG_SYS_CPM_INTERRUPT CONFIG_SYS_CPRI CONFIG_SYS_CPRI_CLK @@ -1800,7 +1601,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_ADDR CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_VIDEO_MODE -CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_DIALOG_PMIC_I2C_ADDR CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_SYS_DIRECT_FLASH_NFS @@ -1846,7 +1646,6 @@ CONFIG_SYS_EXCEPTION_VECTORS_HIGH CONFIG_SYS_FAST_CLK CONFIG_SYS_FAULT_ECHO_LINK_DOWN CONFIG_SYS_FAULT_MII_ADDR -CONFIG_SYS_FCC_PSMR CONFIG_SYS_FDT_BASE CONFIG_SYS_FDT_LOAD_ADDR CONFIG_SYS_FDT_PAD @@ -1862,12 +1661,10 @@ CONFIG_SYS_FLASH1 CONFIG_SYS_FLASH1_BASE_PHYS CONFIG_SYS_FLASH1_BASE_PHYS_EARLY CONFIG_SYS_FLASHBOOT -CONFIG_SYS_FLASH_ADDR_BASE CONFIG_SYS_FLASH_AMD_CHECK_DQ7 CONFIG_SYS_FLASH_AUTOPROTECT_LIST CONFIG_SYS_FLASH_BANKS_LIST CONFIG_SYS_FLASH_BANKS_SIZES -CONFIG_SYS_FLASH_BANK_SIZE CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0 CONFIG_SYS_FLASH_BASE1 @@ -2074,18 +1871,6 @@ CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET CONFIG_SYS_FSL_FMAN_ADDR CONFIG_SYS_FSL_GUTS_ADDR CONFIG_SYS_FSL_I2C -CONFIG_SYS_FSL_I2C2_OFFSET -CONFIG_SYS_FSL_I2C2_SLAVE -CONFIG_SYS_FSL_I2C2_SPEED -CONFIG_SYS_FSL_I2C3_OFFSET -CONFIG_SYS_FSL_I2C3_SLAVE -CONFIG_SYS_FSL_I2C3_SPEED -CONFIG_SYS_FSL_I2C4_OFFSET -CONFIG_SYS_FSL_I2C4_SLAVE -CONFIG_SYS_FSL_I2C4_SPEED -CONFIG_SYS_FSL_I2C_OFFSET -CONFIG_SYS_FSL_I2C_SLAVE -CONFIG_SYS_FSL_I2C_SPEED CONFIG_SYS_FSL_IFC_BASE CONFIG_SYS_FSL_IFC_BASE1 CONFIG_SYS_FSL_IFC_BASE2 @@ -2113,8 +1898,6 @@ CONFIG_SYS_FSL_OCRAM_BASE CONFIG_SYS_FSL_OCRAM_SIZE CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS CONFIG_SYS_FSL_PAMU_OFFSET -CONFIG_SYS_FSL_PBL_PBI -CONFIG_SYS_FSL_PBL_RCW CONFIG_SYS_FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCI_VER_3_X CONFIG_SYS_FSL_PEBUF_BASE @@ -2298,10 +2081,8 @@ CONFIG_SYS_I2C_CLK_OFFSET CONFIG_SYS_I2C_DIRECT_BUS CONFIG_SYS_I2C_DVI_ADDR CONFIG_SYS_I2C_DVI_BUS_NUM -CONFIG_SYS_I2C_EARLY_INIT CONFIG_SYS_I2C_EEPROM_CCID CONFIG_SYS_I2C_EEPROM_NXID -CONFIG_SYS_I2C_EEPROM_NXID_MAC CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS CONFIG_SYS_I2C_EXPANDER_ADDR @@ -2309,41 +2090,12 @@ CONFIG_SYS_I2C_FPGA_ADDR CONFIG_SYS_I2C_FRAM CONFIG_SYS_I2C_G762_ADDR CONFIG_SYS_I2C_IFDR_DIV -CONFIG_SYS_I2C_IHS_CH0 -CONFIG_SYS_I2C_IHS_CH1 -CONFIG_SYS_I2C_IHS_CH2 -CONFIG_SYS_I2C_IHS_CH3 -CONFIG_SYS_I2C_IHS_DUAL -CONFIG_SYS_I2C_IHS_SLAVE_0 -CONFIG_SYS_I2C_IHS_SLAVE_0_1 -CONFIG_SYS_I2C_IHS_SLAVE_1 -CONFIG_SYS_I2C_IHS_SLAVE_1_1 -CONFIG_SYS_I2C_IHS_SLAVE_2 -CONFIG_SYS_I2C_IHS_SLAVE_2_1 -CONFIG_SYS_I2C_IHS_SLAVE_3 -CONFIG_SYS_I2C_IHS_SLAVE_3_1 -CONFIG_SYS_I2C_IHS_SPEED_0 -CONFIG_SYS_I2C_IHS_SPEED_0_1 -CONFIG_SYS_I2C_IHS_SPEED_1 -CONFIG_SYS_I2C_IHS_SPEED_1_1 -CONFIG_SYS_I2C_IHS_SPEED_2 -CONFIG_SYS_I2C_IHS_SPEED_2_1 -CONFIG_SYS_I2C_IHS_SPEED_3 -CONFIG_SYS_I2C_IHS_SPEED_3_1 CONFIG_SYS_I2C_INIT_BOARD CONFIG_SYS_I2C_LDI_ADDR -CONFIG_SYS_I2C_LEGACY CONFIG_SYS_I2C_LPC32XX_SLAVE CONFIG_SYS_I2C_LPC32XX_SPEED -CONFIG_SYS_I2C_MAC1_BUS -CONFIG_SYS_I2C_MAC1_CHIP_ADDR -CONFIG_SYS_I2C_MAC1_DATA_ADDR -CONFIG_SYS_I2C_MAC2_BUS -CONFIG_SYS_I2C_MAC2_CHIP_ADDR -CONFIG_SYS_I2C_MAC2_DATA_ADDR CONFIG_SYS_I2C_MAX_HOPS CONFIG_SYS_I2C_NOPROBES -CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_WIDTH CONFIG_SYS_I2C_PCA9557_ADDR @@ -2353,53 +2105,6 @@ CONFIG_SYS_I2C_PINMUX_SET CONFIG_SYS_I2C_PXA CONFIG_SYS_I2C_QIXIS_ADDR CONFIG_SYS_I2C_RTC_ADDR -CONFIG_SYS_I2C_S3C24X0_SLAVE -CONFIG_SYS_I2C_S3C24X0_SPEED -CONFIG_SYS_I2C_SH -CONFIG_SYS_I2C_SH_BASE0 -CONFIG_SYS_I2C_SH_BASE1 -CONFIG_SYS_I2C_SH_BASE2 -CONFIG_SYS_I2C_SH_BASE3 -CONFIG_SYS_I2C_SH_BASE4 -CONFIG_SYS_I2C_SH_NUM_CONTROLLERS -CONFIG_SYS_I2C_SH_SPEED0 -CONFIG_SYS_I2C_SH_SPEED1 -CONFIG_SYS_I2C_SH_SPEED2 -CONFIG_SYS_I2C_SH_SPEED3 -CONFIG_SYS_I2C_SH_SPEED4 -CONFIG_SYS_I2C_SLAVE -CONFIG_SYS_I2C_SLAVE1 -CONFIG_SYS_I2C_SLAVE2 -CONFIG_SYS_I2C_SLAVE3 -CONFIG_SYS_I2C_SOFT -CONFIG_SYS_I2C_SOFT_SLAVE -CONFIG_SYS_I2C_SOFT_SLAVE_10 -CONFIG_SYS_I2C_SOFT_SLAVE_11 -CONFIG_SYS_I2C_SOFT_SLAVE_12 -CONFIG_SYS_I2C_SOFT_SLAVE_2 -CONFIG_SYS_I2C_SOFT_SLAVE_3 -CONFIG_SYS_I2C_SOFT_SLAVE_4 -CONFIG_SYS_I2C_SOFT_SLAVE_5 -CONFIG_SYS_I2C_SOFT_SLAVE_6 -CONFIG_SYS_I2C_SOFT_SLAVE_7 -CONFIG_SYS_I2C_SOFT_SLAVE_8 -CONFIG_SYS_I2C_SOFT_SLAVE_9 -CONFIG_SYS_I2C_SOFT_SPEED -CONFIG_SYS_I2C_SOFT_SPEED_10 -CONFIG_SYS_I2C_SOFT_SPEED_11 -CONFIG_SYS_I2C_SOFT_SPEED_12 -CONFIG_SYS_I2C_SOFT_SPEED_2 -CONFIG_SYS_I2C_SOFT_SPEED_3 -CONFIG_SYS_I2C_SOFT_SPEED_4 -CONFIG_SYS_I2C_SOFT_SPEED_5 -CONFIG_SYS_I2C_SOFT_SPEED_6 -CONFIG_SYS_I2C_SOFT_SPEED_7 -CONFIG_SYS_I2C_SOFT_SPEED_8 -CONFIG_SYS_I2C_SOFT_SPEED_9 -CONFIG_SYS_I2C_SPEED -CONFIG_SYS_I2C_SPEED1 -CONFIG_SYS_I2C_SPEED2 -CONFIG_SYS_I2C_SPEED3 CONFIG_SYS_I2C_TCA642X_ADDR CONFIG_SYS_I2C_TCA642X_BUS_NUM CONFIG_SYS_IBAT0L @@ -2484,7 +2189,6 @@ CONFIG_SYS_LIME_BASE CONFIG_SYS_LIME_SIZE CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE CONFIG_SYS_LOADS_BAUD_CHANGE -CONFIG_SYS_LOAD_ADDR CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LOW_RES_TIMER @@ -2760,14 +2464,6 @@ CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_OBIR CONFIG_SYS_OHCI_BE_CONTROLLER CONFIG_SYS_OHCI_SWAP_REG_ACCESS -CONFIG_SYS_OMAP24_I2C_SLAVE1 -CONFIG_SYS_OMAP24_I2C_SLAVE2 -CONFIG_SYS_OMAP24_I2C_SLAVE3 -CONFIG_SYS_OMAP24_I2C_SLAVE4 -CONFIG_SYS_OMAP24_I2C_SPEED1 -CONFIG_SYS_OMAP24_I2C_SPEED2 -CONFIG_SYS_OMAP24_I2C_SPEED3 -CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP_ABE_SYSCK CONFIG_SYS_ONENAND_BASE CONFIG_SYS_ONENAND_BLOCK_SIZE @@ -2808,19 +2504,7 @@ CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCI1_MEM_VIRT -CONFIG_SYS_PCI1_MMIO_BASE -CONFIG_SYS_PCI1_MMIO_PHYS -CONFIG_SYS_PCI1_MMIO_SIZE CONFIG_SYS_PCI2_ADDR -CONFIG_SYS_PCI2_IO_BASE -CONFIG_SYS_PCI2_IO_PHYS -CONFIG_SYS_PCI2_IO_SIZE -CONFIG_SYS_PCI2_MEM_BASE -CONFIG_SYS_PCI2_MEM_PHYS -CONFIG_SYS_PCI2_MEM_SIZE -CONFIG_SYS_PCI2_MMIO_BASE -CONFIG_SYS_PCI2_MMIO_PHYS -CONFIG_SYS_PCI2_MMIO_SIZE CONFIG_SYS_PCI64_MEMORY_BUS CONFIG_SYS_PCIE CONFIG_SYS_PCIE1_ADDR @@ -3002,7 +2686,6 @@ CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE -CONFIG_SYS_RCWH_PCIHOST CONFIG_SYS_READ_SPD CONFIG_SYS_RESET_ADDR CONFIG_SYS_RESET_ADDRESS @@ -3133,8 +2816,6 @@ CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL CONFIG_SYS_SPCR_OPT -CONFIG_SYS_SPCR_TSEC1EP -CONFIG_SYS_SPCR_TSEC2EP CONFIG_SYS_SPD_BUS_NUM CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE @@ -3186,9 +2867,7 @@ CONFIG_SYS_TMRINTR_PEND CONFIG_SYS_TMRINTR_PRI CONFIG_SYS_TMRPND_REG CONFIG_SYS_TMR_BASE -CONFIG_SYS_TSEC1 CONFIG_SYS_TSEC1_OFFSET -CONFIG_SYS_TSEC2 CONFIG_SYS_TSEC2_OFFSET CONFIG_SYS_TSEC3_OFFSET CONFIG_SYS_TX_ETH_BUFFER @@ -3231,7 +2910,6 @@ CONFIG_SYS_USE_DATAFLASH_CS3 CONFIG_SYS_USE_FLASH CONFIG_SYS_USE_MAIN_OSCILLATOR CONFIG_SYS_USE_MMC -CONFIG_SYS_USE_MPC834XSYS_USB_PHY CONFIG_SYS_USE_NAND CONFIG_SYS_USE_NANDFLASH CONFIG_SYS_USE_NORFLASH @@ -3255,7 +2933,6 @@ CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VCXK_RESET_DDR CONFIG_SYS_VCXK_RESET_PIN CONFIG_SYS_VCXK_RESET_PORT -CONFIG_SYS_VGA_RAM_EN CONFIG_SYS_VIDEO_LOGO_MAX_SIZE CONFIG_SYS_VSC7385_BASE CONFIG_SYS_VSC7385_BASE_PHYS @@ -3269,7 +2946,6 @@ CONFIG_SYS_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR CONFIG_SYS_XIMG_LEN -CONFIG_SYS_i2C_FSL CONFIG_TAM3517_SETTINGS CONFIG_TCA642X CONFIG_TEGRA_BOARD_STRING @@ -3298,7 +2974,6 @@ CONFIG_THOR_RESET_OFF CONFIG_THUNDERX CONFIG_TIMESTAMP CONFIG_TIZEN -CONFIG_TI_KSNAV CONFIG_TMU_TIMER CONFIG_TPL_PAD_TO CONFIG_TPM_TIS_BASE_ADDRESS @@ -3319,12 +2994,10 @@ CONFIG_TSEC_TBICR_SETTINGS CONFIG_TWL6030_POWER CONFIG_TX_DESCR_NUM CONFIG_TZSW_RESERVED_DRAM_SIZE -CONFIG_UBIBLOCK CONFIG_UBIFS_VOLUME CONFIG_UBI_PART CONFIG_UBI_SIZE CONFIG_UBOOTPATH -CONFIG_UBOOT_ENABLE_PADS_ALL CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_UDP_CHECKSUM @@ -3374,7 +3047,6 @@ CONFIG_USB_EHCI_BASE_LIST CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY CONFIG_USB_EHCI_KIRKWOOD -CONFIG_USB_EHCI_MXC CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_ETH_QMULT @@ -3413,7 +3085,6 @@ CONFIG_USB_TTY CONFIG_USB_TUSB_OMAP_DMA CONFIG_USB_ULPI_TIMEOUT CONFIG_USB_XHCI_EXYNOS -CONFIG_USB_XHCI_OMAP CONFIG_USER_LOWLEVEL_INIT CONFIG_USE_INTERRUPT CONFIG_USE_ONENAND_BOARD_INIT @@ -3423,7 +3094,6 @@ CONFIG_U_BOOT_HDR_SIZE CONFIG_VAL CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM -CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP CONFIG_VIDEO_BCM2835 CONFIG_VIDEO_BMP_LOGO CONFIG_VIDEO_DA8XX diff --git a/scripts/dtc/treesource.c b/scripts/dtc/treesource.c index 2461a3d068a0d1d73169dafa7598e455dda8738b..b36cb41902a437304051d1b8ec3d45dfc0ea000f 100644 --- a/scripts/dtc/treesource.c +++ b/scripts/dtc/treesource.c @@ -281,4 +281,3 @@ void dt_to_source(FILE *f, struct dt_info *dti) write_tree_source_node(f, dti->dt, 0); } - diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index d52128425ce259c7ca2d1d001dc4b4ecfbe9e4b3..12e525ee31f181a871d1bb356f6595c676f3f9aa 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -50,7 +50,7 @@ build_xconfig: $(obj)/qconf localyesconfig localmodconfig: $(obj)/conf $(Q)perl $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config - $(Q)if [ -f .config ]; then \ + $(Q)if [ -f .config ]; then \ cmp -s .tmp.config .config || \ (mv -f .config .config.old.1; \ mv -f .tmp.config .config; \ diff --git a/scripts/kconfig/expr.c b/scripts/kconfig/expr.c index e1a39e90841d809451517c7dc2b8b51cf424c329..9f79bdfaaa5d752acc4b76018bf77e5f0148e6d7 100644 --- a/scripts/kconfig/expr.c +++ b/scripts/kconfig/expr.c @@ -894,7 +894,7 @@ bool expr_depends_symbol(struct expr *dep, struct symbol *sym) default: ; } - return false; + return false; } /* diff --git a/scripts/kconfig/gconf.c b/scripts/kconfig/gconf.c index a9e48cc7b50a3630e1230d487e513831d65b873f..2ec7419301ded8a4d5193d536d338347d112dd97 100644 --- a/scripts/kconfig/gconf.c +++ b/scripts/kconfig/gconf.c @@ -639,7 +639,7 @@ on_set_option_mode3_activate(GtkMenuItem *menuitem, gpointer user_data) void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data) { GtkWidget *dialog; - const gchar *intro_text = + const gchar *intro_text = "Welcome to gkc, the GTK+ graphical configuration tool\n" "For each option, a blank box indicates the feature is disabled, a\n" "check indicates it is enabled, and a dot indicates that it is to\n" diff --git a/scripts/kconfig/list.h b/scripts/kconfig/list.h index 45cb237ab7ef7a9f17779647220da6a30afd06fc..06e8d555d8b06485aca1166989f58cce30f117aa 100644 --- a/scripts/kconfig/list.h +++ b/scripts/kconfig/list.h @@ -48,7 +48,7 @@ struct list_head { */ #define list_for_each_entry(pos, head, member) \ for (pos = list_entry((head)->next, typeof(*pos), member); \ - &pos->member != (head); \ + &pos->member != (head); \ pos = list_entry(pos->member.next, typeof(*pos), member)) /** diff --git a/scripts/spdxcheck.py b/scripts/spdxcheck.py new file mode 100755 index 0000000000000000000000000000000000000000..3e784cf9f401fd480db03e03e7f43ee5d5d8e12b --- /dev/null +++ b/scripts/spdxcheck.py @@ -0,0 +1,296 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0 +# Copyright Thomas Gleixner <tglx@linutronix.de> + +from argparse import ArgumentParser +from ply import lex, yacc +import locale +import traceback +import sys +import git +import re +import os + +class ParserException(Exception): + def __init__(self, tok, txt): + self.tok = tok + self.txt = txt + +class SPDXException(Exception): + def __init__(self, el, txt): + self.el = el + self.txt = txt + +class SPDXdata(object): + def __init__(self): + self.license_files = 0 + self.exception_files = 0 + self.licenses = [ ] + self.exceptions = { } + +# Read the spdx data from the LICENSES directory +def read_spdxdata(repo): + + # The subdirectories of LICENSES in the kernel source + # Note: exceptions needs to be parsed as last directory. + license_dirs = [ "preferred", "dual", "deprecated", "exceptions" ] + lictree = repo.head.commit.tree['LICENSES'] + + spdx = SPDXdata() + + for d in license_dirs: + for el in lictree[d].traverse(): + if not os.path.isfile(el.path): + continue + + exception = None + for l in open(el.path).readlines(): + if l.startswith('Valid-License-Identifier:'): + lid = l.split(':')[1].strip().upper() + if lid in spdx.licenses: + raise SPDXException(el, 'Duplicate License Identifier: %s' %lid) + else: + spdx.licenses.append(lid) + + elif l.startswith('SPDX-Exception-Identifier:'): + exception = l.split(':')[1].strip().upper() + spdx.exceptions[exception] = [] + + elif l.startswith('SPDX-Licenses:'): + for lic in l.split(':')[1].upper().strip().replace(' ', '').replace('\t', '').split(','): + if not lic in spdx.licenses: + raise SPDXException(None, 'Exception %s missing license %s' %(exception, lic)) + spdx.exceptions[exception].append(lic) + + elif l.startswith("License-Text:"): + if exception: + if not len(spdx.exceptions[exception]): + raise SPDXException(el, 'Exception %s is missing SPDX-Licenses' %exception) + spdx.exception_files += 1 + else: + spdx.license_files += 1 + break + return spdx + +class id_parser(object): + + reserved = [ 'AND', 'OR', 'WITH' ] + tokens = [ 'LPAR', 'RPAR', 'ID', 'EXC' ] + reserved + + precedence = ( ('nonassoc', 'AND', 'OR'), ) + + t_ignore = ' \t' + + def __init__(self, spdx): + self.spdx = spdx + self.lasttok = None + self.lastid = None + self.lexer = lex.lex(module = self, reflags = re.UNICODE) + # Initialize the parser. No debug file and no parser rules stored on disk + # The rules are small enough to be generated on the fly + self.parser = yacc.yacc(module = self, write_tables = False, debug = False) + self.lines_checked = 0 + self.checked = 0 + self.spdx_valid = 0 + self.spdx_errors = 0 + self.curline = 0 + self.deepest = 0 + + # Validate License and Exception IDs + def validate(self, tok): + id = tok.value.upper() + if tok.type == 'ID': + if not id in self.spdx.licenses: + raise ParserException(tok, 'Invalid License ID') + self.lastid = id + elif tok.type == 'EXC': + if id not in self.spdx.exceptions: + raise ParserException(tok, 'Invalid Exception ID') + if self.lastid not in self.spdx.exceptions[id]: + raise ParserException(tok, 'Exception not valid for license %s' %self.lastid) + self.lastid = None + elif tok.type != 'WITH': + self.lastid = None + + # Lexer functions + def t_RPAR(self, tok): + r'\)' + self.lasttok = tok.type + return tok + + def t_LPAR(self, tok): + r'\(' + self.lasttok = tok.type + return tok + + def t_ID(self, tok): + r'[A-Za-z.0-9\-+]+' + + if self.lasttok == 'EXC': + print(tok) + raise ParserException(tok, 'Missing parentheses') + + tok.value = tok.value.strip() + val = tok.value.upper() + + if val in self.reserved: + tok.type = val + elif self.lasttok == 'WITH': + tok.type = 'EXC' + + self.lasttok = tok.type + self.validate(tok) + return tok + + def t_error(self, tok): + raise ParserException(tok, 'Invalid token') + + def p_expr(self, p): + '''expr : ID + | ID WITH EXC + | expr AND expr + | expr OR expr + | LPAR expr RPAR''' + pass + + def p_error(self, p): + if not p: + raise ParserException(None, 'Unfinished license expression') + else: + raise ParserException(p, 'Syntax error') + + def parse(self, expr): + self.lasttok = None + self.lastid = None + self.parser.parse(expr, lexer = self.lexer) + + def parse_lines(self, fd, maxlines, fname): + self.checked += 1 + self.curline = 0 + try: + for line in fd: + line = line.decode(locale.getpreferredencoding(False), errors='ignore') + self.curline += 1 + if self.curline > maxlines: + break + self.lines_checked += 1 + if line.find("SPDX-License-Identifier:") < 0: + continue + expr = line.split(':')[1].strip() + # Remove trailing comment closure + if line.strip().endswith('*/'): + expr = expr.rstrip('*/').strip() + # Remove trailing xml comment closure + if line.strip().endswith('-->'): + expr = expr.rstrip('-->').strip() + # Special case for SH magic boot code files + if line.startswith('LIST \"'): + expr = expr.rstrip('\"').strip() + self.parse(expr) + self.spdx_valid += 1 + # + # Should we check for more SPDX ids in the same file and + # complain if there are any? + # + break + + except ParserException as pe: + if pe.tok: + col = line.find(expr) + pe.tok.lexpos + tok = pe.tok.value + sys.stdout.write('%s: %d:%d %s: %s\n' %(fname, self.curline, col, pe.txt, tok)) + else: + sys.stdout.write('%s: %d:0 %s\n' %(fname, self.curline, col, pe.txt)) + self.spdx_errors += 1 + +def scan_git_tree(tree): + for el in tree.traverse(): + # Exclude stuff which would make pointless noise + # FIXME: Put this somewhere more sensible + if el.path.startswith("LICENSES"): + continue + if el.path.find("license-rules.rst") >= 0: + continue + if not os.path.isfile(el.path): + continue + with open(el.path, 'rb') as fd: + parser.parse_lines(fd, args.maxlines, el.path) + +def scan_git_subtree(tree, path): + for p in path.strip('/').split('/'): + tree = tree[p] + scan_git_tree(tree) + +if __name__ == '__main__': + + ap = ArgumentParser(description='SPDX expression checker') + ap.add_argument('path', nargs='*', help='Check path or file. If not given full git tree scan. For stdin use "-"') + ap.add_argument('-m', '--maxlines', type=int, default=15, + help='Maximum number of lines to scan in a file. Default 15') + ap.add_argument('-v', '--verbose', action='store_true', help='Verbose statistics output') + args = ap.parse_args() + + # Sanity check path arguments + if '-' in args.path and len(args.path) > 1: + sys.stderr.write('stdin input "-" must be the only path argument\n') + sys.exit(1) + + try: + # Use git to get the valid license expressions + repo = git.Repo(os.getcwd()) + assert not repo.bare + + # Initialize SPDX data + spdx = read_spdxdata(repo) + + # Initialize the parser + parser = id_parser(spdx) + + except SPDXException as se: + if se.el: + sys.stderr.write('%s: %s\n' %(se.el.path, se.txt)) + else: + sys.stderr.write('%s\n' %se.txt) + sys.exit(1) + + except Exception as ex: + sys.stderr.write('FAIL: %s\n' %ex) + sys.stderr.write('%s\n' %traceback.format_exc()) + sys.exit(1) + + try: + if len(args.path) and args.path[0] == '-': + stdin = os.fdopen(sys.stdin.fileno(), 'rb') + parser.parse_lines(stdin, args.maxlines, '-') + else: + if args.path: + for p in args.path: + if os.path.isfile(p): + parser.parse_lines(open(p, 'rb'), args.maxlines, p) + elif os.path.isdir(p): + scan_git_subtree(repo.head.reference.commit.tree, p) + else: + sys.stderr.write('path %s does not exist\n' %p) + sys.exit(1) + else: + # Full git tree scan + scan_git_tree(repo.head.commit.tree) + + if args.verbose: + sys.stderr.write('\n') + sys.stderr.write('License files: %12d\n' %spdx.license_files) + sys.stderr.write('Exception files: %12d\n' %spdx.exception_files) + sys.stderr.write('License IDs %12d\n' %len(spdx.licenses)) + sys.stderr.write('Exception IDs %12d\n' %len(spdx.exceptions)) + sys.stderr.write('\n') + sys.stderr.write('Files checked: %12d\n' %parser.checked) + sys.stderr.write('Lines checked: %12d\n' %parser.lines_checked) + sys.stderr.write('Files with SPDX: %12d\n' %parser.spdx_valid) + sys.stderr.write('Files with errors: %12d\n' %parser.spdx_errors) + + sys.exit(0) + + except Exception as ex: + sys.stderr.write('FAIL: %s\n' %ex) + sys.stderr.write('%s\n' %traceback.format_exc()) + sys.exit(1) diff --git a/test/bloblist.c b/test/bloblist.c index 4104e6a92f6f7ff529be162373701a0198284fa3..b48be38dc3e2334763268c971ba96908513aec82 100644 --- a/test/bloblist.c +++ b/test/bloblist.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -/* Declare a new compression test */ +/* Declare a new bloblist test */ #define BLOBLIST_TEST(_name, _flags) \ UNIT_TEST(_name, _flags, bloblist_test) diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2edab7be544580787e7efc71c899b547613bffc5..6f0025814ed139881cbec273a31ba25ac01ac882 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -11,6 +11,7 @@ #include <dm.h> #include <malloc.h> #include <mapmem.h> +#include <timestamp.h> #include <version.h> #include <tables_csum.h> #include <version.h> diff --git a/test/dm/cpu.c b/test/dm/cpu.c index ed12cafee2b9cc44b05cfb4d02b4082a56cd1bdd..d7e596ee3965e2c191612f1ed2733f753841709c 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -27,7 +27,7 @@ static int dm_test_cpu(struct unit_test_state *uts) uclass_find_next_device(&dev)) ut_assert(dev_get_flags(dev) & DM_FLAG_ACTIVATED); - ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu-test1", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu@1", &dev)); ut_asserteq_ptr(cpu_get_current_dev(), dev); ut_asserteq(cpu_is_current(dev), 1); diff --git a/test/dm/dsa.c b/test/dm/dsa.c index 18c1776460dac4d33056b5615eba416363e7b849..c857106eaf4a77b6815a1d28b58c1b95e79a87b8 100644 --- a/test/dm/dsa.c +++ b/test/dm/dsa.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020-2021 NXP Semiconductors + * Copyright 2020-2021 NXP */ #include <net/dsa.h> diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c index 0463cf0b433c34c84dd66372777aaf2b0e56aeef..ec41087a558c41a06a1a969ce3455b16e2e24908 100644 --- a/test/dm/of_platdata.c +++ b/test/dm/of_platdata.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ #include <common.h> +#include <clk.h> #include <dm.h> #include <dt-structs.h> +#include <irq.h> #include <dm/test.h> #include <test/test.h> #include <test/ut.h> +#include <asm-generic/gpio.h> #include <asm/global_data.h> /* Test that we can find a device using of-platdata */ @@ -27,11 +30,9 @@ static int dm_test_of_plat_props(struct unit_test_state *uts) struct udevice *dev; int i; - /* Skip the clock */ - ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev)); - ut_asserteq_str("sandbox_clk_test", dev->name); + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_spl_test", + &dev)); - ut_assertok(uclass_next_device_err(&dev)); plat = dev_get_plat(dev); ut_assert(plat->boolval); ut_asserteq(1, plat->intval); @@ -222,3 +223,59 @@ static int dm_test_of_plat_parent(struct unit_test_state *uts) } DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA); #endif + +/* Test clocks with of-platdata */ +static int dm_test_of_plat_clk(struct unit_test_state *uts) +{ + struct dtd_sandbox_clk_test *plat; + struct udevice *dev; + struct clk clk; + + ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev)); + ut_asserteq_str("sandbox_clk_test", dev->name); + plat = dev_get_plat(dev); + + ut_assertok(clk_get_by_phandle(dev, &plat->clocks[0], &clk)); + ut_asserteq_str("sandbox_fixed_clock", clk.dev->name); + + return 0; +} +DM_TEST(dm_test_of_plat_clk, UT_TESTF_SCAN_PDATA); + +/* Test irqs with of-platdata */ +static int dm_test_of_plat_irq(struct unit_test_state *uts) +{ + struct dtd_sandbox_irq_test *plat; + struct udevice *dev; + struct irq irq; + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_irq_test", + &dev)); + plat = dev_get_plat(dev); + + ut_assertok(irq_get_by_phandle(dev, &plat->interrupts_extended[0], + &irq)); + ut_asserteq_str("sandbox_irq", irq.dev->name); + + return 0; +} +DM_TEST(dm_test_of_plat_irq, UT_TESTF_SCAN_PDATA); + +/* Test GPIOs with of-platdata */ +static int dm_test_of_plat_gpio(struct unit_test_state *uts) +{ + struct dtd_sandbox_gpio_test *plat; + struct udevice *dev; + struct gpio_desc desc; + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_gpio_test", + &dev)); + plat = dev_get_plat(dev); + + ut_assertok(gpio_request_by_phandle(dev, &plat->test_gpios[0], &desc, + GPIOD_IS_OUT)); + ut_asserteq_str("sandbox_gpio", desc.dev->name); + + return 0; +} +DM_TEST(dm_test_of_plat_gpio, UT_TESTF_SCAN_PDATA); diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 44e51de0854f106299d5f2dbc0e48b58cca3cf80..49efabe871c03daa8760bc1965be3db441236776 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -318,3 +318,18 @@ static int dm_test_ofnode_get_path(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +static int dm_test_ofnode_conf(struct unit_test_state *uts) +{ + ut_assert(!ofnode_conf_read_bool("missing")); + ut_assert(ofnode_conf_read_bool("testing-bool")); + + ut_asserteq(123, ofnode_conf_read_int("testing-int", 0)); + ut_asserteq(6, ofnode_conf_read_int("missing", 6)); + + ut_assertnull(ofnode_conf_read_str("missing")); + ut_asserteq_str("testing", ofnode_conf_read_str("testing-str")); + + return 0; +} +DM_TEST(dm_test_ofnode_conf, 0); diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c index 9b03b8bae36d40c2020b8180f114972f808b6149..9941abd4cebc9cbf531cd45178d7bdf0e29e51d6 100644 --- a/test/dm/pci_ep.c +++ b/test/dm/pci_ep.c @@ -62,4 +62,3 @@ static int dm_test_pci_ep_base(struct unit_test_state *uts) } DM_TEST(dm_test_pci_ep_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); - diff --git a/test/dm/smem.c b/test/dm/smem.c index a797026cb5e145b5648a0f3336e180a3c3f94db6..289fb59ba1367b44a97a95e200d95ab9c2db3c9e 100644 --- a/test/dm/smem.c +++ b/test/dm/smem.c @@ -25,4 +25,3 @@ static int dm_test_smem_base(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_smem_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); - diff --git a/test/dm/timer.c b/test/dm/timer.c index 70043b9eeed4d4559ce56765cbcc3b167544f72a..9f94d47692003f0b45afdf98035fe93dfe9566c0 100644 --- a/test/dm/timer.c +++ b/test/dm/timer.c @@ -33,16 +33,16 @@ static int dm_test_timer_timebase_fallback(struct unit_test_state *uts) { struct udevice *dev; - cpu_sandbox_set_current("cpu-test1"); + cpu_sandbox_set_current("cpu@1"); ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev)); ut_asserteq(3000000, timer_get_rate(dev)); ut_assertok(device_remove(dev, DM_REMOVE_NORMAL)); - cpu_sandbox_set_current("cpu-test2"); + cpu_sandbox_set_current("cpu@2"); ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev)); ut_asserteq(2000000, timer_get_rate(dev)); - cpu_sandbox_set_current("cpu-test1"); + cpu_sandbox_set_current("cpu@1"); return 0; } diff --git a/test/dm/wdt.c b/test/dm/wdt.c index 24b991dff622d6a4030f6dba89aca6ced0510073..ee615f0e1487b86098313c0483ed288e7a85a0c7 100644 --- a/test/dm/wdt.c +++ b/test/dm/wdt.c @@ -6,11 +6,14 @@ #include <common.h> #include <dm.h> #include <wdt.h> +#include <asm/gpio.h> #include <asm/state.h> #include <asm/test.h> #include <dm/test.h> #include <test/test.h> #include <test/ut.h> +#include <linux/delay.h> +#include <watchdog.h> /* Test that watchdog driver functions are called */ static int dm_test_wdt_base(struct unit_test_state *uts) @@ -19,7 +22,8 @@ static int dm_test_wdt_base(struct unit_test_state *uts) struct udevice *dev; const u64 timeout = 42; - ut_assertok(uclass_get_device(UCLASS_WDT, 0, &dev)); + ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, + DM_DRIVER_GET(wdt_sandbox), &dev)); ut_assertnonnull(dev); ut_asserteq(0, state->wdt.counter); ut_asserteq(false, state->wdt.running); @@ -39,3 +43,87 @@ static int dm_test_wdt_base(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +static int dm_test_wdt_gpio(struct unit_test_state *uts) +{ + /* + * The sandbox wdt gpio is "connected" to gpio bank a, offset + * 7. Use the sandbox back door to verify that the gpio-wdt + * driver behaves as expected. + */ + struct udevice *wdt, *gpio; + const u64 timeout = 42; + const int offset = 7; + int val; + + ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, + DM_DRIVER_GET(wdt_gpio), &wdt)); + ut_assertnonnull(wdt); + + ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio)); + ut_assertnonnull(gpio); + ut_assertok(wdt_start(wdt, timeout, 0)); + + val = sandbox_gpio_get_value(gpio, offset); + ut_assertok(wdt_reset(wdt)); + ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset)); + ut_assertok(wdt_reset(wdt)); + ut_asserteq(val, sandbox_gpio_get_value(gpio, offset)); + + ut_asserteq(-ENOSYS, wdt_stop(wdt)); + + return 0; +} +DM_TEST(dm_test_wdt_gpio, UT_TESTF_SCAN_FDT); + +static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts) +{ + struct sandbox_state *state = state_get_current(); + struct udevice *gpio_wdt, *sandbox_wdt; + struct udevice *gpio; + const u64 timeout = 42; + const int offset = 7; + uint reset_count; + int val; + + ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, + DM_DRIVER_GET(wdt_gpio), &gpio_wdt)); + ut_assertnonnull(gpio_wdt); + ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, + DM_DRIVER_GET(wdt_sandbox), &sandbox_wdt)); + ut_assertnonnull(sandbox_wdt); + ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio)); + ut_assertnonnull(gpio); + + /* Neither device should be "started", so watchdog_reset() should be a no-op. */ + reset_count = state->wdt.reset_count; + val = sandbox_gpio_get_value(gpio, offset); + watchdog_reset(); + ut_asserteq(reset_count, state->wdt.reset_count); + ut_asserteq(val, sandbox_gpio_get_value(gpio, offset)); + + /* Start both devices. */ + ut_assertok(wdt_start(gpio_wdt, timeout, 0)); + ut_assertok(wdt_start(sandbox_wdt, timeout, 0)); + + /* Make sure both devices have just been pinged. */ + timer_test_add_offset(100); + watchdog_reset(); + reset_count = state->wdt.reset_count; + val = sandbox_gpio_get_value(gpio, offset); + + /* The gpio watchdog should be pinged, the sandbox one not. */ + timer_test_add_offset(30); + watchdog_reset(); + ut_asserteq(reset_count, state->wdt.reset_count); + ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset)); + + /* After another ~30ms, both devices should get pinged. */ + timer_test_add_offset(30); + watchdog_reset(); + ut_asserteq(reset_count + 1, state->wdt.reset_count); + ut_asserteq(val, sandbox_gpio_get_value(gpio, offset)); + + return 0; +} +DM_TEST(dm_test_wdt_watchdog_reset, UT_TESTF_SCAN_FDT); diff --git a/test/print_ut.c b/test/print_ut.c index e2bcfbef00781fa779c609b9c22a290b9725b9f6..11d8580e55c560a38b893d28472d4498234a4435 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -9,7 +9,7 @@ #include <display_options.h> #include <log.h> #include <mapmem.h> -#include <version.h> +#include <version_string.h> #include <test/suites.h> #include <test/test.h> #include <test/ut.h> diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 1db5da4c1e10c8c1214f97828ad13eae77f2057d..384fd53c653fe46ccf94ddd230c1d5ddda381d57 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -351,13 +351,13 @@ class ConsoleBase(object): self.p.logfile_read = self.logstream bcfg = self.config.buildconfig config_spl = bcfg.get('config_spl', 'n') == 'y' - config_spl_serial_support = bcfg.get('config_spl_serial_support', + config_spl_serial = bcfg.get('config_spl_serial', 'n') == 'y' env_spl_skipped = self.config.env.get('env__spl_skipped', False) env_spl2_skipped = self.config.env.get('env__spl2_skipped', True) - if config_spl and config_spl_serial_support and not env_spl_skipped: + if config_spl and config_spl_serial and not env_spl_skipped: m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns) if m != 0: diff --git a/test/ut.c b/test/ut.c index 1eec2a57dff344c177b0abfa68aa40af85c644a2..28da417686e497c7178bc033c2e8fe79bb684c66 100644 --- a/test/ut.c +++ b/test/ut.c @@ -121,6 +121,32 @@ int ut_check_skipline(struct unit_test_state *uts) return 0; } +int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...) +{ + va_list args; + int len; + int ret; + + va_start(args, fmt); + len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); + va_end(args); + if (len >= sizeof(uts->expect_str)) { + ut_fail(uts, __FILE__, __LINE__, __func__, + "unit_test_state->expect_str too small"); + return -EOVERFLOW; + } + while (1) { + if (!console_record_avail()) + return -ENOENT; + ret = readline_check(uts); + if (ret < 0) + return ret; + + if (!strcmp(uts->expect_str, uts->actual_str)) + return 0; + } +} + int ut_check_console_end(struct unit_test_state *uts) { int ret; diff --git a/tools/asn1_compiler.c b/tools/asn1_compiler.c index adabd41452640991ed86d1557ac32012042ce4e0..03fb7e03758f64b72f3707d49283109776a3c0cf 100644 --- a/tools/asn1_compiler.c +++ b/tools/asn1_compiler.c @@ -427,7 +427,7 @@ static void tokenise(char *buffer, char *end) } memcpy(tokens[tix].content, start, tokens[tix].size); tokens[tix].content[tokens[tix].size] = 0; - + /* If it begins with a lowercase letter then * it's an element name */ diff --git a/tools/binman/control.py b/tools/binman/control.py index dcba02ff7f8a863d219b05b4933cd5475be59636..0dbcbc28e991d5aca90c4e3d843d9f67901fff86 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -565,12 +565,9 @@ def Binman(args): global state if args.full_help: - pager = os.getenv('PAGER') - if not pager: - pager = 'more' - fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), - 'README.rst') - command.Run(pager, fname) + tools.PrintFullHelp( + os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README.rst') + ) return 0 # Put these here so that we can import this module without libfdt diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help index f7bc80ea83092a7b6d591b4b285556a09a00fea5..dc2d9c98111a972af0235e434217dd99ee128391 100644 --- a/tools/binman/missing-blob-help +++ b/tools/binman/missing-blob-help @@ -17,3 +17,8 @@ board/sunxi/README.sunxi64 scp-sunxi: SCP firmware is required for system suspend, but is otherwise optional. Please read the section on SCP firmware in board/sunxi/README.sunxi64 + +k3-rti-wdt-firmware: +If CONFIG_WDT_K3_RTI_LOAD_FW is enabled, a firmware image is needed for +the R5F core(s) to trigger the system reset. One possible source is +https://github.com/siemens/k3-rti-wdt. diff --git a/tools/buildman/README b/tools/buildman/README index ec2d4e7c6f581e0d96e1997c1478986d4945e7cf..ce277884326218768c301b27a00281dede7c0a1f 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -1010,13 +1010,13 @@ For example: ... 43: Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig arm: - + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 - + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 - + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 + + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 + + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 + + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 am335x_evm_usbspl : - + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 - + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 - + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 + + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 + + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 + + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 44: Convert CONFIG_SPL_USB_HOST to Kconfig ... diff --git a/tools/buildman/control.py b/tools/buildman/control.py index a98d1b4c06f3805d484d558b2517675a37721242..fd9664c85d881bff6625d2f48888c0e0a19ff8ec 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -16,6 +16,7 @@ from patman import command from patman import gitutil from patman import patchstream from patman import terminal +from patman import tools from patman.terminal import Print def GetPlural(count): @@ -133,12 +134,9 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, global builder if options.full_help: - pager = os.getenv('PAGER') - if not pager: - pager = 'more' - fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), - 'README') - command.Run(pager, fname) + tools.PrintFullHelp( + os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README') + ) return 0 gitutil.Setup() diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 0195456dfeca9d656ab26b24630b6c4b72a195e0..92113dcb72f9caf7df7e2c986a388e20df6d9e74 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:focal-20210723 +FROM ubuntu:focal-20210827 MAINTAINER Tom Rini <trini@konsulko.com> LABEL Description=" This image is for building U-Boot inside a container" @@ -60,6 +60,7 @@ RUN apt-get update && apt-get install -y \ iasl \ imagemagick \ iputils-ping \ + libconfuse-dev \ libgit2-dev \ libguestfs-tools \ liblz4-tool \ @@ -76,6 +77,7 @@ RUN apt-get update && apt-get install -y \ mount \ mtd-utils \ mtools \ + ninja-build \ openssl \ picocom \ parted \ @@ -166,11 +168,24 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ RUN git clone git://git.qemu.org/qemu.git /tmp/qemu && \ cd /tmp/qemu && \ git submodule update --init dtc && \ - git checkout v4.2.0 && \ + git checkout v6.1.0 && \ + # config user.name and user.email to make 'git am' happy + git config user.name u-boot && \ + git config user.email u-boot@denx.de && \ + # manually apply the bug fix for QEMU 6.1.0 Xilinx Zynq UART emulation codes + wget -O - http://patchwork.ozlabs.org/project/qemu-devel/patch/20210823020813.25192-2-bmeng.cn@gmail.com/mbox/ | git am && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu +# Build genimage (required by some targets to generate disk images) +RUN wget -O - https://github.com/pengutronix/genimage/releases/download/v14/genimage-14.tar.xz | tar -C /tmp -xJ && \ + cd /tmp/genimage-14 && \ + ./configure && \ + make -j$(nproc) && \ + make install && \ + rm -rf /tmp/genimage-14 + # Create our user/group RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot RUN useradd -m -U uboot diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py index 869c92b49bfcc4ebbf9a763c197bdd12e8b20f5e..3bb5c680f2e1703a6da40cf6a01b819be3444968 100644 --- a/tools/dtoc/dtb_platdata.py +++ b/tools/dtoc/dtb_platdata.py @@ -62,6 +62,7 @@ VAL_PREFIX = 'dtv_' # a phandle property. PHANDLE_PROPS = { 'clocks': '#clock-cells', + 'interrupts-extended': '#interrupt-cells', 'gpios': '#gpio-cells', 'sandbox,emul': '#emul-cells', } diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 2a61a5d6f04982708e9c814a10ee9d2774645c10..e39c39e23a175786b905e736b0f7cb97cd07b7ec 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -951,21 +951,23 @@ static int flash_read_buf(int dev, int fd, void *buf, size_t count, DEVNAME(dev), strerror(errno)); return -1; } - if (rc != readlen) { - fprintf(stderr, - "Read error on %s: Attempted to read %zd bytes but got %d\n", - DEVNAME(dev), readlen, rc); - return -1; - } #ifdef DEBUG fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n", rc, (unsigned long long)blockstart + block_seek, DEVNAME(dev)); #endif - processed += readlen; - readlen = min(blocklen, count - processed); - block_seek = 0; - blockstart += blocklen; + processed += rc; + if (rc != readlen) { + fprintf(stderr, + "Warning on %s: Attempted to read %zd bytes but got %d\n", + DEVNAME(dev), readlen, rc); + readlen -= rc; + block_seek += rc; + } else { + blockstart += blocklen; + readlen = min(blocklen, count - processed); + block_seek = 0; + } } return processed; diff --git a/tools/kwbimage.c b/tools/kwbimage.c index d200ff242508786c2e668713534cc4f611a51e9a..77bf4dd8865e8e26ff2e482925fca439b577639e 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Image manipulator for Marvell SoCs - * supports Kirkwood, Dove, Armada 370, Armada XP, and Armada 38x + * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and + * Armada 39x * * (C) Copyright 2013 Thomas Petazzoni * <thomas.petazzoni@free-electrons.com> @@ -280,14 +281,6 @@ static uint8_t image_checksum8(void *start, uint32_t len) return csum; } -size_t kwbimage_header_size(unsigned char *ptr) -{ - if (image_version((void *)ptr) == 0) - return sizeof(struct main_hdr_v0); - else - return KWBHEADER_V1_SIZE((struct main_hdr_v1 *)ptr); -} - /* * Verify checksum over a complete header that includes the checksum field. * Return 1 when OK, otherwise 0. @@ -298,7 +291,7 @@ static int main_hdr_checksum_ok(void *hdr) struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr; uint8_t checksum; - checksum = image_checksum8(hdr, kwbimage_header_size(hdr)); + checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr)); /* Calculated checksum includes the header checksum field. Compensate * for that. */ @@ -542,7 +535,7 @@ static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1 *dst, FILE *hashf, } if (4 + size_seq > sizeof(dst->key)) { - fprintf(stderr, "export pk failed: seq too large (%d, %lu)\n", + fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n", 4 + size_seq, sizeof(dst->key)); fprintf(stderr, errmsg, keyname); return -ENOBUFS; @@ -1618,34 +1611,20 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd, static void kwbimage_print_header(const void *ptr) { struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr; + struct opt_hdr_v1 *ohdr; printf("Image Type: MVEBU Boot from %s Image\n", image_boot_mode_name(mhdr->blockid)); - printf("Image version:%d\n", image_version((void *)ptr)); - if (image_version((void *)ptr) == 1) { - struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; + printf("Image version:%d\n", kwbimage_version(ptr)); - if (mhdr->ext & 0x1) { - struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *) - ((uint8_t *)ptr + - sizeof(*mhdr)); - - while (1) { - uint32_t ohdr_size; - - ohdr_size = (ohdr->headersz_msb << 16) | - le16_to_cpu(ohdr->headersz_lsb); - if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) { - printf("BIN Hdr Size: "); - genimg_print_size(ohdr_size - 12 - 4 * ohdr->data[0]); - } - if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1)) - break; - ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr + - ohdr_size); - } + for_each_opt_hdr_v1 (ohdr, mhdr) { + if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) { + printf("BIN Hdr Size: "); + genimg_print_size(opt_hdr_v1_size(ohdr) - 12 - + 4 * ohdr->data[0]); } } + printf("Data Size: "); genimg_print_size(mhdr->blocksize - sizeof(uint32_t)); printf("Load Address: %08x\n", mhdr->destaddr); @@ -1663,8 +1642,8 @@ static int kwbimage_check_image_types(uint8_t type) static int kwbimage_verify_header(unsigned char *ptr, int image_size, struct image_tool_params *params) { - uint8_t checksum; - size_t header_size = kwbimage_header_size(ptr); + size_t header_size = kwbheader_size(ptr); + uint8_t csum; if (header_size > image_size) return -FDT_ERR_BADSTRUCTURE; @@ -1673,52 +1652,27 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, return -FDT_ERR_BADSTRUCTURE; /* Only version 0 extended header has checksum */ - if (image_version((void *)ptr) == 0) { + if (kwbimage_version(ptr) == 0) { struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr; if (mhdr->ext & 0x1) { - struct ext_hdr_v0 *ext_hdr; - - if (header_size + sizeof(*ext_hdr) > image_size) - return -FDT_ERR_BADSTRUCTURE; + struct ext_hdr_v0 *ext_hdr = (void *)(mhdr + 1); - ext_hdr = (struct ext_hdr_v0 *) - (ptr + sizeof(struct main_hdr_v0)); - checksum = image_checksum8(ext_hdr, - sizeof(struct ext_hdr_v0) - - sizeof(uint8_t)); - if (checksum != ext_hdr->checksum) + csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1); + if (csum != ext_hdr->checksum) return -FDT_ERR_BADSTRUCTURE; } - } else if (image_version((void *)ptr) == 1) { + } else if (kwbimage_version(ptr) == 1) { struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; + const uint8_t *mhdr_end; + struct opt_hdr_v1 *ohdr; uint32_t offset; uint32_t size; - if (mhdr->ext & 0x1) { - uint32_t ohdr_size; - struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *) - (ptr + sizeof(*mhdr)); - - while (1) { - if ((uint8_t *)ohdr + sizeof(*ohdr) > - (uint8_t *)mhdr + header_size) - return -FDT_ERR_BADSTRUCTURE; - - ohdr_size = (ohdr->headersz_msb << 16) | - le16_to_cpu(ohdr->headersz_lsb); - - if (ohdr_size < 8 || - (uint8_t *)ohdr + ohdr_size > - (uint8_t *)mhdr + header_size) - return -FDT_ERR_BADSTRUCTURE; - - if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1)) - break; - ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr + - ohdr_size); - } - } + mhdr_end = (uint8_t *)mhdr + header_size; + for_each_opt_hdr_v1 (ohdr, ptr) + if (!opt_hdr_v1_valid_size(ohdr, mhdr_end)) + return -FDT_ERR_BADSTRUCTURE; offset = le32_to_cpu(mhdr->srcaddr); @@ -1864,37 +1818,25 @@ static int kwbimage_generate(struct image_tool_params *params, static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params) { struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; - size_t header_size = kwbimage_header_size(ptr); + size_t header_size = kwbheader_size(ptr); + struct opt_hdr_v1 *ohdr; int idx = params->pflag; int cur_idx = 0; uint32_t offset; ulong image; ulong size; - if (image_version((void *)ptr) == 1 && (mhdr->ext & 0x1)) { - struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *) - ((uint8_t *)ptr + - sizeof(*mhdr)); + for_each_opt_hdr_v1 (ohdr, ptr) { + if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE) + continue; - while (1) { - uint32_t ohdr_size = (ohdr->headersz_msb << 16) | - le16_to_cpu(ohdr->headersz_lsb); - - if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) { - if (idx == cur_idx) { - image = (ulong)&ohdr->data[4 + - 4 * ohdr->data[0]]; - size = ohdr_size - 12 - - 4 * ohdr->data[0]; - goto extract; - } - ++cur_idx; - } - if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1)) - break; - ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr + - ohdr_size); + if (idx == cur_idx) { + image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]]; + size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0]; + goto extract; } + + ++cur_idx; } if (idx != cur_idx) { diff --git a/tools/kwbimage.h b/tools/kwbimage.h index e063e3e41eb747aad5117e3bf46dcc580dc299b6..126d482fe72240fabeed8e8bd1be7ae5e05b1dec 100644 --- a/tools/kwbimage.h +++ b/tools/kwbimage.h @@ -23,8 +23,8 @@ /* NAND ECC Mode */ #define IBR_HDR_ECC_DEFAULT 0x00 #define IBR_HDR_ECC_FORCED_HAMMING 0x01 -#define IBR_HDR_ECC_FORCED_RS 0x02 -#define IBR_HDR_ECC_DISABLED 0x03 +#define IBR_HDR_ECC_FORCED_RS 0x02 +#define IBR_HDR_ECC_DISABLED 0x03 /* Boot Type - block ID */ #define IBR_HDR_I2C_ID 0x4D @@ -69,12 +69,7 @@ struct ext_hdr_v0 { uint8_t checksum; } __packed; -struct kwb_header { - struct main_hdr_v0 kwb_hdr; - struct ext_hdr_v0 kwb_exthdr; -} __packed; - -/* Structure of the main header, version 1 (Armada 370/38x/XP) */ +/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */ struct main_hdr_v1 { uint8_t blockid; /* 0x0 */ uint8_t flags; /* 0x1 */ @@ -108,7 +103,7 @@ struct main_hdr_v1 { #define MAIN_HDR_V1_OPT_BAUD_115200 0x7 /* - * Header for the optional headers, version 1 (Armada 370, Armada XP) + * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x) */ struct opt_hdr_v1 { uint8_t headertype; @@ -132,7 +127,7 @@ struct sig_v1 { } __packed; /* - * Structure of secure header (Armada 38x) + * Structure of secure header (Armada XP/375/38x/39x) */ struct secure_hdr_v1 { uint8_t headertype; /* 0x0 */ @@ -195,9 +190,6 @@ struct register_set_hdr_v1 { #define OPT_HDR_V1_BINARY_TYPE 0x2 #define OPT_HDR_V1_REGISTER_TYPE 0x3 -#define KWBHEADER_V1_SIZE(hdr) \ - (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb)) - enum kwbimage_cmd { CMD_INVALID, CMD_BOOT_FROM, @@ -225,10 +217,91 @@ void init_kwb_image_type (void); * header, byte 8 was reserved, and always set to 0. In the v1 header, * byte 8 has been changed to a proper field, set to 1. */ -static inline unsigned int image_version(void *header) +static inline unsigned int kwbimage_version(const void *header) { - unsigned char *ptr = header; + const unsigned char *ptr = header; return ptr[8]; } +static inline size_t kwbheader_size(const void *header) +{ + if (kwbimage_version(header) == 0) { + const struct main_hdr_v0 *hdr = header; + + return sizeof(*hdr) + + (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0; + } else { + const struct main_hdr_v1 *hdr = header; + + return (hdr->headersz_msb << 16) | + le16_to_cpu(hdr->headersz_lsb); + } +} + +static inline size_t kwbheader_size_for_csum(const void *header) +{ + if (kwbimage_version(header) == 0) + return sizeof(struct main_hdr_v0); + else + return kwbheader_size(header); +} + +static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr) +{ + return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb); +} + +static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr, + const void *mhdr_end) +{ + uint32_t ohdr_size; + + if ((void *)(ohdr + 1) > mhdr_end) + return 0; + + ohdr_size = opt_hdr_v1_size(ohdr); + if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end) + return 0; + + return 1; +} + +static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) { + struct main_hdr_v1 *mhdr; + + if (kwbimage_version(img) != 1) + return NULL; + + mhdr = img; + if (mhdr->ext & 0x1) + return (struct opt_hdr_v1 *)(mhdr + 1); + else + return NULL; +} + +static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur) +{ + uint32_t size = opt_hdr_v1_size(cur); + + return (uint8_t *)cur + size - 4; +} + +static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur) +{ + return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur)); +} + +static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur) +{ + if (*opt_hdr_v1_ext(cur) & 0x1) + return _opt_hdr_v1_next(cur); + else + return NULL; +} + +#define for_each_opt_hdr_v1(ohdr, img) \ + for ((ohdr) = opt_hdr_v1_first((img)); \ + (ohdr) != NULL; \ + (ohdr) = opt_hdr_v1_next((ohdr))) + #endif /* _KWBIMAGE_H_ */ diff --git a/tools/kwboot.c b/tools/kwboot.c index 7feeaa45a22da97fed413bdf8a67862708f8d849..6a1a030308e722fe58c764e7456bb257061ca2f5 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -1,8 +1,11 @@ /* * Boot a Marvell SoC, with Xmodem over UART0. - * supports Kirkwood, Dove, Armada 370, Armada XP + * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and + * Armada 39x * * (c) 2012 Daniel Stodden <daniel.stodden@gmail.com> + * (c) 2021 Pali Rohár <pali@kernel.org> + * (c) 2021 Marek Behún <marek.behun@nic.cz> * * References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281 * Integrated Controller: Functional Specifications" December 2, @@ -11,6 +14,7 @@ #include "kwbimage.h" #include "mkimage.h" +#include "version.h" #include <stdlib.h> #include <stdio.h> @@ -22,10 +26,15 @@ #include <errno.h> #include <unistd.h> #include <stdint.h> -#include <termios.h> -#include <sys/mman.h> +#include <time.h> #include <sys/stat.h> +#ifdef __linux__ +#include "termios_linux.h" +#else +#include <termios.h> +#endif + /* * Marvell BootROM UART Sensing */ @@ -56,15 +65,199 @@ static unsigned char kwboot_msg_debug[] = { #define NAK 21 /* target block negative ack */ #define CAN 24 /* target/sender transfer cancellation */ +#define KWBOOT_XM_BLKSZ 128 /* xmodem block size */ + struct kwboot_block { uint8_t soh; uint8_t pnum; uint8_t _pnum; - uint8_t data[128]; + uint8_t data[KWBOOT_XM_BLKSZ]; uint8_t csum; } __packed; #define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */ +#define KWBOOT_HDR_RSP_TIMEO 10000 /* ms */ + +/* ARM code making baudrate changing function return to original exec address */ +static unsigned char kwboot_pre_baud_code[] = { + /* exec_addr: */ + 0x00, 0x00, 0x00, 0x00, /* .word 0 */ + 0x0c, 0xe0, 0x1f, 0xe5, /* ldr lr, exec_addr */ +}; + +/* ARM code for binary header injection to change baudrate */ +static unsigned char kwboot_baud_code[] = { + /* ; #define UART_BASE 0xd0012000 */ + /* ; #define THR 0x00 */ + /* ; #define DLL 0x00 */ + /* ; #define DLH 0x04 */ + /* ; #define LCR 0x0c */ + /* ; #define DLAB 0x80 */ + /* ; #define LSR 0x14 */ + /* ; #define THRE 0x20 */ + /* ; #define TEMT 0x40 */ + /* ; #define DIV_ROUND(a, b) ((a + b/2) / b) */ + /* ; */ + /* ; u32 set_baudrate(u32 old_b, u32 new_b) { */ + /* ; const u8 *str = "$baudratechange"; */ + /* ; u8 c; */ + /* ; do { */ + /* ; c = *str++; */ + /* ; writel(UART_BASE + THR, c); */ + /* ; } while (c); */ + /* ; while */ + /* ; (!(readl(UART_BASE + LSR) & TEMT)); */ + /* ; u32 lcr = readl(UART_BASE + LCR); */ + /* ; writel(UART_BASE + LCR, lcr | DLAB); */ + /* ; u8 old_dll = readl(UART_BASE + DLL); */ + /* ; u8 old_dlh = readl(UART_BASE + DLH); */ + /* ; u16 old_dl = old_dll | (old_dlh << 8); */ + /* ; u32 clk = old_b * old_dl; */ + /* ; u16 new_dl = DIV_ROUND(clk, new_b); */ + /* ; u8 new_dll = new_dl & 0xff; */ + /* ; u8 new_dlh = (new_dl >> 8) & 0xff; */ + /* ; writel(UART_BASE + DLL, new_dll); */ + /* ; writel(UART_BASE + DLH, new_dlh); */ + /* ; writel(UART_BASE + LCR, lcr & ~DLAB); */ + /* ; msleep(1); */ + /* ; return 0; */ + /* ; } */ + + 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */ + + /* ; r0 = UART_BASE */ + 0x02, 0x0a, 0xa0, 0xe3, /* mov r0, #0x2000 */ + 0x01, 0x00, 0x4d, 0xe3, /* movt r0, #0xd001 */ + + /* ; r2 = address of preamble string */ + 0xd0, 0x20, 0x8f, 0xe2, /* adr r2, preamble */ + + /* ; Send preamble string over UART */ + /* .Lloop_preamble: */ + /* */ + /* ; Wait until Transmitter Holding is Empty */ + /* .Lloop_thre: */ + /* ; r1 = UART_BASE[LSR] & THRE */ + 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */ + 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */ + 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */ + + /* ; Put character into Transmitter FIFO */ + /* ; r1 = *r2++ */ + 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */ + /* ; UART_BASE[THR] = r1 */ + 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */ + + /* ; Loop until end of preamble string */ + 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */ + 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */ + + /* ; Wait until Transmitter FIFO is Empty */ + /* .Lloop_txempty: */ + /* ; r1 = UART_BASE[LSR] & TEMT */ + 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */ + 0x40, 0x00, 0x11, 0xe3, /* tst r1, #0x40 */ + 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_txempty */ + + /* ; Set Divisor Latch Access Bit */ + /* ; UART_BASE[LCR] |= DLAB */ + 0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */ + 0x80, 0x10, 0x81, 0xe3, /* orr r1, r1, #0x80 */ + 0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */ + + /* ; Read current Divisor Latch */ + /* ; r1 = UART_BASE[DLH]<<8 | UART_BASE[DLL] */ + 0x00, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x00] */ + 0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */ + 0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */ + 0x04, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x04] */ + 0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */ + 0x41, 0x14, 0xa0, 0xe1, /* asr r1, r1, #8 */ + 0x02, 0x10, 0x81, 0xe1, /* orr r1, r1, r2 */ + + /* ; Read old baudrate value */ + /* ; r2 = old_baudrate */ + 0x8c, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */ + + /* ; Calculate base clock */ + /* ; r1 = r2 * r1 */ + 0x92, 0x01, 0x01, 0xe0, /* mul r1, r2, r1 */ + + /* ; Read new baudrate value */ + /* ; r2 = baudrate */ + 0x88, 0x20, 0x9f, 0xe5, /* ldr r2, baudrate */ + + /* ; Calculate new Divisor Latch */ + /* ; r1 = DIV_ROUND(r1, r2) = */ + /* ; = (r1 + r2/2) / r2 */ + 0xa2, 0x10, 0x81, 0xe0, /* add r1, r1, r2, lsr #1 */ + 0x02, 0x40, 0xa0, 0xe1, /* mov r4, r2 */ + 0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */ + /* .Lloop_div1: */ + 0x84, 0x40, 0xa0, 0x91, /* movls r4, r4, lsl #1 */ + 0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */ + 0xfc, 0xff, 0xff, 0x9a, /* bls .Lloop_div1 */ + 0x00, 0x30, 0xa0, 0xe3, /* mov r3, #0 */ + /* .Lloop_div2: */ + 0x04, 0x00, 0x51, 0xe1, /* cmp r1, r4 */ + 0x04, 0x10, 0x41, 0x20, /* subhs r1, r1, r4 */ + 0x03, 0x30, 0xa3, 0xe0, /* adc r3, r3, r3 */ + 0xa4, 0x40, 0xa0, 0xe1, /* mov r4, r4, lsr #1 */ + 0x02, 0x00, 0x54, 0xe1, /* cmp r4, r2 */ + 0xf9, 0xff, 0xff, 0x2a, /* bhs .Lloop_div2 */ + 0x03, 0x10, 0xa0, 0xe1, /* mov r1, r3 */ + + /* ; Set new Divisor Latch Low */ + /* ; UART_BASE[DLL] = r1 & 0xff */ + 0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */ + 0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */ + 0x00, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x00] */ + + /* ; Set new Divisor Latch High */ + /* ; UART_BASE[DLH] = r1>>8 & 0xff */ + 0x41, 0x24, 0xa0, 0xe1, /* asr r2, r1, #8 */ + 0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */ + 0x04, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x04] */ + + /* ; Clear Divisor Latch Access Bit */ + /* ; UART_BASE[LCR] &= ~DLAB */ + 0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */ + 0x80, 0x10, 0xc1, 0xe3, /* bic r1, r1, #0x80 */ + 0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */ + + /* ; Sleep 1ms ~~ 600000 cycles at 1200 MHz */ + /* ; r1 = 600000 */ + 0x9f, 0x1d, 0xa0, 0xe3, /* mov r1, #0x27c0 */ + 0x09, 0x10, 0x40, 0xe3, /* movt r1, #0x0009 */ + /* .Lloop_sleep: */ + 0x01, 0x10, 0x41, 0xe2, /* sub r1, r1, #1 */ + 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */ + 0xfc, 0xff, 0xff, 0x1a, /* bne .Lloop_sleep */ + + /* ; Return 0 - no error */ + 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */ + 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */ + + /* ; Preamble string */ + /* preamble: */ + 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */ + 0x64, 0x72, 0x61, 0x74, + 0x65, 0x63, 0x68, 0x61, + 0x6e, 0x67, 0x65, 0x00, + + /* ; Placeholder for old baudrate value */ + /* old_baudrate: */ + 0x00, 0x00, 0x00, 0x00, /* .word 0 */ + + /* ; Placeholder for new baudrate value */ + /* new_baudrate: */ + 0x00, 0x00, 0x00, 0x00, /* .word 0 */ +}; + +#define KWBOOT_BAUDRATE_BIN_HEADER_SZ (sizeof(kwboot_baud_code) + \ + sizeof(struct opt_hdr_v1) + 8) + +static const char kwb_baud_magic[16] = "$baudratechange"; static int kwboot_verbose; @@ -72,6 +265,23 @@ static int msg_req_delay = KWBOOT_MSG_REQ_DELAY; static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO; static int blk_rsp_timeo = KWBOOT_BLK_RSP_TIMEO; +static ssize_t +kwboot_write(int fd, const char *buf, size_t len) +{ + size_t tot = 0; + + while (tot < len) { + ssize_t wr = write(fd, buf + tot, len - tot); + + if (wr < 0) + return -1; + + tot += wr; + } + + return tot; +} + static void kwboot_printv(const char *fmt, ...) { @@ -122,12 +332,14 @@ __progress(int pct, char c) fputc(c, stdout); nl = "]\n"; - pos++; + pos = (pos + 1) % width; if (pct == 100) { - while (pos++ < width) + while (pos && pos++ < width) fputc(' ', stdout); fputs(nl, stdout); + nl = ""; + pos = 0; } fflush(stdout); @@ -144,6 +356,9 @@ kwboot_progress(int _pct, char c) if (kwboot_verbose) __progress(pct, c); + + if (pct == 100) + pct = 0; } static int @@ -191,26 +406,13 @@ out: static int kwboot_tty_send(int fd, const void *buf, size_t len) { - int rc; - ssize_t n; - if (!buf) return 0; - rc = -1; - - do { - n = write(fd, buf, len); - if (n < 0) - goto out; - - buf = (char *)buf + n; - len -= n; - } while (len > 0); + if (kwboot_write(fd, buf, len) < 0) + return -1; - rc = tcdrain(fd); -out: - return rc; + return tcdrain(fd); } static int @@ -220,51 +422,260 @@ kwboot_tty_send_char(int fd, unsigned char c) } static speed_t -kwboot_tty_speed(int baudrate) +kwboot_tty_baudrate_to_speed(int baudrate) { switch (baudrate) { +#ifdef B4000000 + case 4000000: + return B4000000; +#endif +#ifdef B3500000 + case 3500000: + return B3500000; +#endif +#ifdef B3000000 + case 3000000: + return B3000000; +#endif +#ifdef B2500000 + case 2500000: + return B2500000; +#endif +#ifdef B2000000 + case 2000000: + return B2000000; +#endif +#ifdef B1500000 + case 1500000: + return B1500000; +#endif +#ifdef B1152000 + case 1152000: + return B1152000; +#endif +#ifdef B1000000 + case 1000000: + return B1000000; +#endif +#ifdef B921600 + case 921600: + return B921600; +#endif +#ifdef B614400 + case 614400: + return B614400; +#endif +#ifdef B576000 + case 576000: + return B576000; +#endif +#ifdef B500000 + case 500000: + return B500000; +#endif +#ifdef B460800 + case 460800: + return B460800; +#endif +#ifdef B307200 + case 307200: + return B307200; +#endif +#ifdef B230400 + case 230400: + return B230400; +#endif +#ifdef B153600 + case 153600: + return B153600; +#endif +#ifdef B115200 case 115200: return B115200; +#endif +#ifdef B76800 + case 76800: + return B76800; +#endif +#ifdef B57600 case 57600: return B57600; +#endif +#ifdef B38400 case 38400: return B38400; +#endif +#ifdef B19200 case 19200: return B19200; +#endif +#ifdef B9600 case 9600: return B9600; +#endif +#ifdef B4800 + case 4800: + return B4800; +#endif +#ifdef B2400 + case 2400: + return B2400; +#endif +#ifdef B1800 + case 1800: + return B1800; +#endif +#ifdef B1200 + case 1200: + return B1200; +#endif +#ifdef B600 + case 600: + return B600; +#endif +#ifdef B300 + case 300: + return B300; +#endif +#ifdef B200 + case 200: + return B200; +#endif +#ifdef B150 + case 150: + return B150; +#endif +#ifdef B134 + case 134: + return B134; +#endif +#ifdef B110 + case 110: + return B110; +#endif +#ifdef B75 + case 75: + return B75; +#endif +#ifdef B50 + case 50: + return B50; +#endif + default: +#ifdef BOTHER + return BOTHER; +#else + return B0; +#endif } +} + +static int +_is_within_tolerance(int value, int reference, int tolerance) +{ + return 100 * value >= reference * (100 - tolerance) && + 100 * value <= reference * (100 + tolerance); +} +static int +kwboot_tty_change_baudrate(int fd, int baudrate) +{ + struct termios tio; + speed_t speed; + int rc; + + rc = tcgetattr(fd, &tio); + if (rc) + return rc; + + speed = kwboot_tty_baudrate_to_speed(baudrate); + if (speed == B0) { + errno = EINVAL; + return -1; + } + +#ifdef BOTHER + if (speed == BOTHER) + tio.c_ospeed = tio.c_ispeed = baudrate; +#endif + + rc = cfsetospeed(&tio, speed); + if (rc) + return rc; + + rc = cfsetispeed(&tio, speed); + if (rc) + return rc; + + rc = tcsetattr(fd, TCSANOW, &tio); + if (rc) + return rc; + + rc = tcgetattr(fd, &tio); + if (rc) + return rc; + + if (cfgetospeed(&tio) != speed || cfgetispeed(&tio) != speed) + goto baud_fail; + +#ifdef BOTHER + /* + * Check whether set baudrate is within 3% tolerance. + * If BOTHER is defined, Linux always fills out c_ospeed / c_ispeed + * with real values. + */ + if (!_is_within_tolerance(tio.c_ospeed, baudrate, 3)) + goto baud_fail; + + if (!_is_within_tolerance(tio.c_ispeed, baudrate, 3)) + goto baud_fail; +#endif + + return 0; + +baud_fail: + fprintf(stderr, "Could not set baudrate to requested value\n"); + errno = EINVAL; return -1; } static int -kwboot_open_tty(const char *path, speed_t speed) +kwboot_open_tty(const char *path, int baudrate) { - int rc, fd; + int rc, fd, flags; struct termios tio; rc = -1; - fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY); + fd = open(path, O_RDWR | O_NOCTTY | O_NDELAY); if (fd < 0) goto out; - memset(&tio, 0, sizeof(tio)); - - tio.c_iflag = 0; - tio.c_cflag = CREAD|CLOCAL|CS8; + rc = tcgetattr(fd, &tio); + if (rc) + goto out; + cfmakeraw(&tio); + tio.c_cflag |= CREAD | CLOCAL; tio.c_cc[VMIN] = 1; - tio.c_cc[VTIME] = 10; - - cfsetospeed(&tio, speed); - cfsetispeed(&tio, speed); + tio.c_cc[VTIME] = 0; rc = tcsetattr(fd, TCSANOW, &tio); if (rc) goto out; + flags = fcntl(fd, F_GETFL); + if (flags < 0) + goto out; + + rc = fcntl(fd, F_SETFL, flags & ~O_NDELAY); + if (rc) + goto out; + + rc = kwboot_tty_change_baudrate(fd, baudrate); + if (rc) + goto out; + rc = fd; out: if (rc < 0) { @@ -342,21 +753,19 @@ kwboot_debugmsg(int tty, void *msg) return rc; } -static int +static size_t kwboot_xm_makeblock(struct kwboot_block *block, const void *data, size_t size, int pnum) { - const size_t blksz = sizeof(block->data); - size_t n; - int i; + size_t i, n; block->soh = SOH; block->pnum = pnum; block->_pnum = ~block->pnum; - n = size < blksz ? size : blksz; + n = size < KWBOOT_XM_BLKSZ ? size : KWBOOT_XM_BLKSZ; memcpy(&block->data[0], data, n); - memset(&block->data[n], 0, blksz - n); + memset(&block->data[n], 0, KWBOOT_XM_BLKSZ - n); block->csum = 0; for (i = 0; i < n; i++) @@ -365,34 +774,36 @@ kwboot_xm_makeblock(struct kwboot_block *block, const void *data, return n; } -static int -kwboot_xm_sendblock(int fd, struct kwboot_block *block) +static uint64_t +_now(void) { - int rc, retries; - char c; + struct timespec ts; - retries = 16; - do { - rc = kwboot_tty_send(fd, block, sizeof(*block)); - if (rc) - break; + if (clock_gettime(CLOCK_MONOTONIC, &ts)) { + static int err_print; - do { - rc = kwboot_tty_recv(fd, &c, 1, blk_rsp_timeo); - if (rc) - break; - - if (c != ACK && c != NAK && c != CAN) - printf("%c", c); + if (!err_print) { + perror("clock_gettime() does not work"); + err_print = 1; + } - } while (c != ACK && c != NAK && c != CAN); + /* this will just make the timeout not work */ + return -1ULL; + } - if (c != ACK) - kwboot_progress(-1, '+'); + return ts.tv_sec * 1000ULL + (ts.tv_nsec + 500000) / 1000000; +} - } while (c == NAK && retries-- > 0); +static int +_is_xm_reply(char c) +{ + return c == ACK || c == NAK || c == CAN; +} - rc = -1; +static int +_xm_reply_to_error(int c) +{ + int rc = -1; switch (c) { case ACK: @@ -413,56 +824,269 @@ kwboot_xm_sendblock(int fd, struct kwboot_block *block) } static int -kwboot_xmodem(int tty, const void *_data, size_t size) +kwboot_baud_magic_handle(int fd, char c, int baudrate) { - const uint8_t *data = _data; - int rc, pnum, N, err; + static size_t rcv_len; + + if (rcv_len < sizeof(kwb_baud_magic)) { + /* try to recognize whole magic word */ + if (c == kwb_baud_magic[rcv_len]) { + rcv_len++; + } else { + printf("%.*s%c", (int)rcv_len, kwb_baud_magic, c); + fflush(stdout); + rcv_len = 0; + } + } - pnum = 1; - N = 0; + if (rcv_len == sizeof(kwb_baud_magic)) { + /* magic word received */ + kwboot_printv("\nChanging baudrate to %d Bd\n", baudrate); - kwboot_printv("Sending boot image...\n"); + return kwboot_tty_change_baudrate(fd, baudrate) ? : 1; + } else { + return 0; + } +} - sleep(2); /* flush isn't effective without it */ - tcflush(tty, TCIOFLUSH); +static int +kwboot_xm_recv_reply(int fd, char *c, int allow_non_xm, int *non_xm_print, + int baudrate, int *baud_changed) +{ + int timeout = allow_non_xm ? KWBOOT_HDR_RSP_TIMEO : blk_rsp_timeo; + uint64_t recv_until = _now() + timeout; + int rc; + + if (non_xm_print) + *non_xm_print = 0; + if (baud_changed) + *baud_changed = 0; + while (1) { + rc = kwboot_tty_recv(fd, c, 1, timeout); + if (rc) { + if (errno != ETIMEDOUT) + return rc; + else if (allow_non_xm && *non_xm_print) + return -1; + else + *c = NAK; + } + + /* If received xmodem reply, end. */ + if (_is_xm_reply(*c)) + break; + + /* + * If receiving/printing non-xmodem text output is allowed and + * such a byte was received, we want to increase receiving time + * and either: + * - print the byte, if it is not part of baudrate change magic + * sequence while baudrate change was requested (-B option) + * - change baudrate + * Otherwise decrease timeout by time elapsed. + */ + if (allow_non_xm) { + recv_until = _now() + timeout; + + if (baudrate && !*baud_changed) { + rc = kwboot_baud_magic_handle(fd, *c, baudrate); + if (rc == 1) + *baud_changed = 1; + else if (!rc) + *non_xm_print = 1; + else + return rc; + } else if (!baudrate || !*baud_changed) { + putchar(*c); + fflush(stdout); + *non_xm_print = 1; + } + } else { + timeout = recv_until - _now(); + if (timeout < 0) { + errno = ETIMEDOUT; + return -1; + } + } + } + + return 0; +} + +static int +kwboot_xm_sendblock(int fd, struct kwboot_block *block, int allow_non_xm, + int *done_print, int baudrate) +{ + int non_xm_print, baud_changed; + int rc, err, retries; + char c; + + *done_print = 0; + + retries = 16; do { - struct kwboot_block block; - int n; + rc = kwboot_tty_send(fd, block, sizeof(*block)); + if (rc) + return rc; - n = kwboot_xm_makeblock(&block, - data + N, size - N, - pnum++); - if (n < 0) + if (allow_non_xm && !*done_print) { + kwboot_progress(100, '.'); + kwboot_printv("Done\n"); + *done_print = 1; + } + + rc = kwboot_xm_recv_reply(fd, &c, allow_non_xm, &non_xm_print, + baudrate, &baud_changed); + if (rc) goto can; - if (!n) - break; + if (!allow_non_xm && c != ACK) + kwboot_progress(-1, '+'); + } while (c == NAK && retries-- > 0); + + if (non_xm_print) + kwboot_printv("\n"); + + if (allow_non_xm && baudrate && !baud_changed) { + fprintf(stderr, "Baudrate was not changed\n"); + rc = -1; + errno = EPROTO; + goto can; + } + + return _xm_reply_to_error(c); +can: + err = errno; + kwboot_tty_send_char(fd, CAN); + kwboot_printv("\n"); + errno = err; + return rc; +} + +static int +kwboot_xm_finish(int fd) +{ + int rc, retries; + char c; - rc = kwboot_xm_sendblock(tty, &block); + kwboot_printv("Finishing transfer\n"); + + retries = 16; + do { + rc = kwboot_tty_send_char(fd, EOT); + if (rc) + return rc; + + rc = kwboot_xm_recv_reply(fd, &c, 0, NULL, 0, NULL); + if (rc) + return rc; + } while (c == NAK && retries-- > 0); + + return _xm_reply_to_error(c); +} + +static int +kwboot_xmodem_one(int tty, int *pnum, int header, const uint8_t *data, + size_t size, int baudrate) +{ + int done_print = 0; + size_t sent, left; + int rc; + + kwboot_printv("Sending boot image %s (%zu bytes)...\n", + header ? "header" : "data", size); + + left = size; + sent = 0; + + while (sent < size) { + struct kwboot_block block; + int last_block; + size_t blksz; + + blksz = kwboot_xm_makeblock(&block, data, left, (*pnum)++); + data += blksz; + + last_block = (left <= blksz); + + rc = kwboot_xm_sendblock(tty, &block, header && last_block, + &done_print, baudrate); if (rc) goto out; - N += n; - kwboot_progress(N * 100 / size, '.'); - } while (1); + sent += blksz; + left -= blksz; - rc = kwboot_tty_send_char(tty, EOT); + if (!done_print) + kwboot_progress(sent * 100 / size, '.'); + } + + if (!done_print) + kwboot_printv("Done\n"); + return 0; out: + kwboot_printv("\n"); return rc; +} -can: - err = errno; - kwboot_tty_send_char(tty, CAN); - errno = err; - goto out; +static int +kwboot_xmodem(int tty, const void *_img, size_t size, int baudrate) +{ + const uint8_t *img = _img; + int rc, pnum; + size_t hdrsz; + + hdrsz = kwbheader_size(img); + + kwboot_printv("Waiting 2s and flushing tty\n"); + sleep(2); /* flush isn't effective without it */ + tcflush(tty, TCIOFLUSH); + + pnum = 1; + + rc = kwboot_xmodem_one(tty, &pnum, 1, img, hdrsz, baudrate); + if (rc) + return rc; + + img += hdrsz; + size -= hdrsz; + + rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0); + if (rc) + return rc; + + rc = kwboot_xm_finish(tty); + if (rc) + return rc; + + if (baudrate) { + char buf[sizeof(kwb_baud_magic)]; + + /* Wait 1s for baudrate change magic */ + rc = kwboot_tty_recv(tty, buf, sizeof(buf), 1000); + if (rc) + return rc; + + if (memcmp(buf, kwb_baud_magic, sizeof(buf))) { + errno = EPROTO; + return -1; + } + + kwboot_printv("\nChanging baudrate back to 115200 Bd\n\n"); + rc = kwboot_tty_change_baudrate(tty, 115200); + if (rc) + return rc; + } + + return 0; } static int -kwboot_term_pipe(int in, int out, char *quit, int *s) +kwboot_term_pipe(int in, int out, const char *quit, int *s) { - ssize_t nin, nout; + ssize_t nin; char _buf[128], *buf = _buf; nin = read(in, buf, sizeof(_buf)); @@ -480,22 +1104,15 @@ kwboot_term_pipe(int in, int out, char *quit, int *s) buf++; nin--; } else { - while (*s > 0) { - nout = write(out, quit, *s); - if (nout <= 0) - return -1; - (*s) -= nout; - } + if (kwboot_write(out, quit, *s) < 0) + return -1; + *s = 0; } } } - while (nin > 0) { - nout = write(out, buf, nin); - if (nout <= 0) - return -1; - nin -= nout; - } + if (kwboot_write(out, buf, nin) < 0) + return -1; return 0; } @@ -504,7 +1121,7 @@ static int kwboot_terminal(int tty) { int rc, in, s; - char *quit = "\34c"; + const char *quit = "\34c"; struct termios otio, tio; rc = -1; @@ -523,7 +1140,7 @@ kwboot_terminal(int tty) } kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n", - quit[0]|0100, quit[1]); + quit[0] | 0100, quit[1]); } else in = -1; @@ -552,7 +1169,7 @@ kwboot_terminal(int tty) break; } - if (FD_ISSET(in, &rfds)) { + if (in >= 0 && FD_ISSET(in, &rfds)) { rc = kwboot_term_pipe(in, tty, quit, &s); if (rc) break; @@ -567,11 +1184,12 @@ out: } static void * -kwboot_mmap_image(const char *path, size_t *size, int prot) +kwboot_read_image(const char *path, size_t *size, size_t reserve) { - int rc, fd, flags; + int rc, fd; struct stat st; void *img; + off_t tot; rc = -1; img = NULL; @@ -584,19 +1202,30 @@ kwboot_mmap_image(const char *path, size_t *size, int prot) if (rc) goto out; - flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED; - - img = mmap(NULL, st.st_size, prot, flags, fd, 0); - if (img == MAP_FAILED) { - img = NULL; + img = malloc(st.st_size + reserve); + if (!img) goto out; + + tot = 0; + while (tot < st.st_size) { + ssize_t rd = read(fd, img + tot, st.st_size - tot); + + if (rd < 0) + goto out; + + tot += rd; + + if (!rd && tot < st.st_size) { + errno = EIO; + goto out; + } } rc = 0; *size = st.st_size; out: if (rc && img) { - munmap(img, st.st_size); + free(img); img = NULL; } if (fd >= 0) @@ -606,9 +1235,13 @@ out: } static uint8_t -kwboot_img_csum8(void *_data, size_t size) +kwboot_hdr_csum8(const void *hdr) { - uint8_t *data = _data, csum; + const uint8_t *data = hdr; + uint8_t csum; + size_t size; + + size = kwbheader_size_for_csum(hdr); for (csum = 0; size-- > 0; data++) csum += *data; @@ -617,80 +1250,299 @@ kwboot_img_csum8(void *_data, size_t size) } static int -kwboot_img_patch_hdr(void *img, size_t size) +kwboot_img_is_secure(void *img) +{ + struct opt_hdr_v1 *ohdr; + + for_each_opt_hdr_v1 (ohdr, img) + if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE) + return 1; + + return 0; +} + +static void * +kwboot_img_grow_data_left(void *img, size_t *size, size_t grow) +{ + uint32_t hdrsz, datasz, srcaddr; + struct main_hdr_v1 *hdr = img; + uint8_t *data; + + srcaddr = le32_to_cpu(hdr->srcaddr); + + hdrsz = kwbheader_size(hdr); + data = (uint8_t *)img + srcaddr; + datasz = *size - srcaddr; + + /* only move data if there is not enough space */ + if (hdrsz + grow > srcaddr) { + size_t need = hdrsz + grow - srcaddr; + + /* move data by enough bytes */ + memmove(data + need, data, datasz); + *size += need; + srcaddr += need; + } + + srcaddr -= grow; + hdr->srcaddr = cpu_to_le32(srcaddr); + hdr->destaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) - grow); + hdr->blocksize = cpu_to_le32(le32_to_cpu(hdr->blocksize) + grow); + + return (uint8_t *)img + srcaddr; +} + +static void +kwboot_img_grow_hdr(void *img, size_t *size, size_t grow) +{ + uint32_t hdrsz, datasz, srcaddr; + struct main_hdr_v1 *hdr = img; + uint8_t *data; + + srcaddr = le32_to_cpu(hdr->srcaddr); + + hdrsz = kwbheader_size(img); + data = (uint8_t *)img + srcaddr; + datasz = *size - srcaddr; + + /* only move data if there is not enough space */ + if (hdrsz + grow > srcaddr) { + size_t need = hdrsz + grow - srcaddr; + + /* move data by enough bytes */ + memmove(data + need, data, datasz); + + hdr->srcaddr = cpu_to_le32(srcaddr + need); + *size += need; + } + + if (kwbimage_version(img) == 1) { + hdrsz += grow; + hdr->headersz_msb = hdrsz >> 16; + hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff); + } +} + +static void * +kwboot_add_bin_ohdr_v1(void *img, size_t *size, uint32_t binsz) +{ + struct main_hdr_v1 *hdr = img; + struct opt_hdr_v1 *ohdr; + uint32_t ohdrsz; + + ohdrsz = binsz + 8 + sizeof(*ohdr); + kwboot_img_grow_hdr(img, size, ohdrsz); + + if (hdr->ext & 0x1) { + for_each_opt_hdr_v1 (ohdr, img) + if (opt_hdr_v1_next(ohdr) == NULL) + break; + + *opt_hdr_v1_ext(ohdr) |= 1; + ohdr = opt_hdr_v1_next(ohdr); + } else { + hdr->ext |= 1; + ohdr = (void *)(hdr + 1); + } + + ohdr->headertype = OPT_HDR_V1_BINARY_TYPE; + ohdr->headersz_msb = ohdrsz >> 16; + ohdr->headersz_lsb = cpu_to_le16(ohdrsz & 0xffff); + + memset(&ohdr->data[0], 0, ohdrsz - sizeof(*ohdr)); + + return &ohdr->data[4]; +} + +static void +_copy_baudrate_change_code(struct main_hdr_v1 *hdr, void *dst, int pre, + int old_baud, int new_baud) +{ + size_t codesz = sizeof(kwboot_baud_code); + uint8_t *code = dst; + + if (pre) { + size_t presz = sizeof(kwboot_pre_baud_code); + + /* + * We need to prepend code that loads lr register with original + * value of hdr->execaddr. We do this by putting the original + * exec address before the code that loads it relatively from + * it's beginning. + * Afterwards we change the exec address to this code (which is + * at offset 4, because the first 4 bytes contain the original + * exec address). + */ + memcpy(code, kwboot_pre_baud_code, presz); + *(uint32_t *)code = hdr->execaddr; + + hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + 4); + + code += presz; + } + + memcpy(code, kwboot_baud_code, codesz - 8); + *(uint32_t *)(code + codesz - 8) = cpu_to_le32(old_baud); + *(uint32_t *)(code + codesz - 4) = cpu_to_le32(new_baud); +} + +static int +kwboot_img_patch(void *img, size_t *size, int baudrate) { - int rc; struct main_hdr_v1 *hdr; + uint32_t srcaddr; uint8_t csum; - size_t hdrsz = sizeof(*hdr); + size_t hdrsz; int image_ver; + int is_secure; - rc = -1; hdr = img; - if (size < hdrsz) { - errno = EINVAL; - goto out; - } + if (*size < sizeof(struct main_hdr_v1)) + goto err; - image_ver = image_version(img); + image_ver = kwbimage_version(img); if (image_ver != 0 && image_ver != 1) { fprintf(stderr, "Invalid image header version\n"); - errno = EINVAL; - goto out; + goto err; } - if (image_ver == 0) - hdrsz = sizeof(*hdr); - else - hdrsz = KWBHEADER_V1_SIZE(hdr); + hdrsz = kwbheader_size(hdr); - if (size < hdrsz) { - errno = EINVAL; - goto out; + if (*size < hdrsz) + goto err; + + csum = kwboot_hdr_csum8(hdr) - hdr->checksum; + if (csum != hdr->checksum) + goto err; + + if (image_ver == 0) { + struct main_hdr_v0 *hdr_v0 = img; + + hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED; + hdr_v0->nandpagesize = 0; } - csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checksum; - if (csum != hdr->checksum) { - errno = EINVAL; - goto out; + srcaddr = le32_to_cpu(hdr->srcaddr); + + switch (hdr->blockid) { + case IBR_HDR_SATA_ID: + if (srcaddr < 1) + goto err; + + hdr->srcaddr = cpu_to_le32((srcaddr - 1) * 512); + break; + + case IBR_HDR_SDIO_ID: + hdr->srcaddr = cpu_to_le32(srcaddr * 512); + break; + + case IBR_HDR_PEX_ID: + if (srcaddr == 0xFFFFFFFF) + hdr->srcaddr = cpu_to_le32(hdrsz); + break; + + case IBR_HDR_SPI_ID: + if (hdr->destaddr == cpu_to_le32(0xFFFFFFFF)) { + kwboot_printv("Patching destination and execution addresses from SPI/NOR XIP area to DDR area 0x00800000\n"); + hdr->destaddr = cpu_to_le32(0x00800000); + hdr->execaddr = cpu_to_le32(0x00800000); + } + break; } - if (hdr->blockid == IBR_HDR_UART_ID) { - rc = 0; - goto out; + if (hdrsz > le32_to_cpu(hdr->srcaddr) || + *size < le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize)) + goto err; + + is_secure = kwboot_img_is_secure(img); + + if (hdr->blockid != IBR_HDR_UART_ID) { + if (is_secure) { + fprintf(stderr, + "Image has secure header with signature for non-UART booting\n"); + goto err; + } + + kwboot_printv("Patching image boot signature to UART\n"); + hdr->blockid = IBR_HDR_UART_ID; } - hdr->blockid = IBR_HDR_UART_ID; + if (baudrate) { + uint32_t codesz = sizeof(kwboot_baud_code); + void *code; - if (image_ver == 0) { - struct main_hdr_v0 *hdr_v0 = img; + if (image_ver == 0) { + fprintf(stderr, + "Cannot inject code for changing baudrate into v0 image header\n"); + goto err; + } - hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED; - hdr_v0->nandpagesize = 0; + if (is_secure) { + fprintf(stderr, + "Cannot inject code for changing baudrate into image with secure header\n"); + goto err; + } - hdr_v0->srcaddr = hdr_v0->ext - ? sizeof(struct kwb_header) - : sizeof(*hdr_v0); + /* + * First inject code that changes the baudrate from the default + * value of 115200 Bd to requested value. This code is inserted + * as a new opt hdr, so it is executed by BootROM after the + * header part is received. + */ + kwboot_printv("Injecting binary header code for changing baudrate to %d Bd\n", + baudrate); + + code = kwboot_add_bin_ohdr_v1(img, size, codesz); + _copy_baudrate_change_code(hdr, code, 0, 115200, baudrate); + + /* + * Now inject code that changes the baudrate back to 115200 Bd. + * This code is prepended to the data part of the image, so it + * is executed before U-Boot proper. + */ + kwboot_printv("Injecting code for changing baudrate back\n"); + + codesz += sizeof(kwboot_pre_baud_code); + code = kwboot_img_grow_data_left(img, size, codesz); + _copy_baudrate_change_code(hdr, code, 1, baudrate, 115200); + + /* recompute header size */ + hdrsz = kwbheader_size(hdr); } - hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum; + if (hdrsz % KWBOOT_XM_BLKSZ) { + size_t offset = (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) % + KWBOOT_XM_BLKSZ; - rc = 0; -out: - return rc; + if (is_secure) { + fprintf(stderr, "Cannot align image with secure header\n"); + goto err; + } + + kwboot_printv("Aligning image header to Xmodem block size\n"); + kwboot_img_grow_hdr(img, size, offset); + } + + hdr->checksum = kwboot_hdr_csum8(hdr) - csum; + + *size = le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize); + return 0; +err: + errno = EINVAL; + return -1; } static void kwboot_usage(FILE *stream, char *progname) { + fprintf(stream, "kwboot version %s\n", PLAIN_VERSION); fprintf(stream, "Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n", progname); fprintf(stream, "\n"); fprintf(stream, " -b <image>: boot <image> with preamble (Kirkwood, Armada 370/XP)\n"); - fprintf(stream, " -p: patch <image> to type 0x69 (uart boot)\n"); fprintf(stream, " -D <image>: boot <image> without preamble (Dove)\n"); fprintf(stream, " -d: enter debug mode\n"); @@ -710,12 +1562,13 @@ int main(int argc, char **argv) { const char *ttypath, *imgpath; - int rv, rc, tty, term, prot, patch; + int rv, rc, tty, term; void *bootmsg; void *debugmsg; void *img; size_t size; - speed_t speed; + size_t after_img_rsv; + int baudrate; rv = 1; tty = -1; @@ -724,9 +1577,9 @@ main(int argc, char **argv) imgpath = NULL; img = NULL; term = 0; - patch = 0; size = 0; - speed = B115200; + after_img_rsv = KWBOOT_XM_BLKSZ; + baudrate = 115200; kwboot_verbose = isatty(STDOUT_FILENO); @@ -751,7 +1604,7 @@ main(int argc, char **argv) break; case 'p': - patch = 1; + /* nop, for backward compatibility */ break; case 't': @@ -776,9 +1629,7 @@ main(int argc, char **argv) break; case 'B': - speed = kwboot_tty_speed(atoi(optarg)); - if (speed == -1) - goto usage; + baudrate = atoi(optarg); break; case 'h': @@ -791,32 +1642,34 @@ main(int argc, char **argv) if (!bootmsg && !term && !debugmsg) goto usage; - if (patch && !imgpath) - goto usage; - if (argc - optind < 1) goto usage; ttypath = argv[optind++]; - tty = kwboot_open_tty(ttypath, speed); + tty = kwboot_open_tty(ttypath, imgpath ? 115200 : baudrate); if (tty < 0) { perror(ttypath); goto out; } - if (imgpath) { - prot = PROT_READ | (patch ? PROT_WRITE : 0); + if (baudrate == 115200) + /* do not change baudrate during Xmodem to the same value */ + baudrate = 0; + else + /* ensure we have enough space for baudrate change code */ + after_img_rsv += KWBOOT_BAUDRATE_BIN_HEADER_SZ + + sizeof(kwboot_pre_baud_code) + + sizeof(kwboot_baud_code); - img = kwboot_mmap_image(imgpath, &size, prot); + if (imgpath) { + img = kwboot_read_image(imgpath, &size, after_img_rsv); if (!img) { perror(imgpath); goto out; } - } - if (patch) { - rc = kwboot_img_patch_hdr(img, size); + rc = kwboot_img_patch(img, &size, baudrate); if (rc) { fprintf(stderr, "%s: Invalid image.\n", imgpath); goto out; @@ -838,7 +1691,7 @@ main(int argc, char **argv) } if (img) { - rc = kwboot_xmodem(tty, img, size); + rc = kwboot_xmodem(tty, img, size, baudrate); if (rc) { perror("xmodem"); goto out; @@ -859,7 +1712,7 @@ out: close(tty); if (img) - munmap(img, size); + free(img); return rv; diff --git a/tools/mkimage.c b/tools/mkimage.c index 302bfcf971fd83c43f7a28fd07945d9be428dd78..fbe883ce3620e1d31a1d8435498542ac543f0971 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -732,6 +732,12 @@ copy_file (int ifd, const char *datafile, int pad) exit (EXIT_FAILURE); } + if (sbuf.st_size == 0) { + fprintf (stderr, "%s: Input file %s is empty, bailing out\n", + params.cmdname, datafile); + exit (EXIT_FAILURE); + } + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); if (ptr == MAP_FAILED) { fprintf (stderr, "%s: Can't read %s: %s\n", diff --git a/tools/patman/main.py b/tools/patman/main.py index 04e37a5931394d18691eb451512a3bbba9134196..e5be28e3316cf6392ae2690725efe11b1d221264 100755 --- a/tools/patman/main.py +++ b/tools/patman/main.py @@ -28,6 +28,7 @@ from patman import settings from patman import terminal from patman import test_util from patman import test_checkpatch +from patman import tools epilog = '''Create patches from commits in a branch, check them and email them as specified by tags you place in the commits. Use -n to do a dry run first.''' @@ -170,14 +171,9 @@ elif args.cmd == 'send': fd.close() elif args.full_help: - pager = os.getenv('PAGER') - if not pager: - pager = shutil.which('less') - if not pager: - pager = 'more' - fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), - 'README') - command.Run(pager, fname) + tools.PrintFullHelp( + os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README') + ) else: # If we are not processing tags, no need to warning about bad ones diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt index b238a8b4bab1bdc7450b806016233e30f4d4c447..de2d9e4d2846745df8714954beb5b4ae5f20649a 100644 --- a/tools/patman/test/test01.txt +++ b/tools/patman/test/test01.txt @@ -3,15 +3,15 @@ Author: Simon Glass <sjg@chromium.org> Date: Sat Apr 15 15:39:08 2017 -0600 pci: Correct cast for sandbox - + This gives a warning with some native compilers: - + cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘u64 {aka long unsigned int}’ [-Wformat=] - + Fix it with a cast. - + Signed-off-by: Simon Glass <sjg@chromium.org> Commit-changes: 2 - second revision change @@ -21,7 +21,7 @@ Date: Sat Apr 15 15:39:08 2017 -0600 about some things from the first commit END - + Commit-notes: Some notes about the first commit @@ -32,15 +32,15 @@ Author: Simon Glass <sjg@chromium.org> Date: Sat Apr 15 15:39:08 2017 -0600 fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() - + This gives a warning with some native compilers: - + lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Wformat=] - + Fix it with a cast. - + Signed-off-by: Simon Glass <sjg@chromium.org> Series-to: u-boot Series-prefix: RFC @@ -60,7 +60,7 @@ Date: Sat Apr 15 15:39:08 2017 -0600 Cover-changes: 4 - Some notes for the cover letter - + Cover-letter: test: A test patch series This is a test of how the cover diff --git a/tools/patman/tools.py b/tools/patman/tools.py index 877e37cd8da1b25d9899e753012e07e2737fb6b8..710f1fdcd361e4820a56c62ef37a3dbf77b3e88e 100644 --- a/tools/patman/tools.py +++ b/tools/patman/tools.py @@ -5,6 +5,7 @@ import glob import os +import shlex import shutil import struct import sys @@ -581,3 +582,17 @@ def ToHexSize(val): hex value of size, or 'None' if the value is None """ return 'None' if val is None else '%#x' % len(val) + +def PrintFullHelp(fname): + """Print the full help message for a tool using an appropriate pager. + + Args: + fname: Path to a file containing the full help message + """ + pager = shlex.split(os.getenv('PAGER', '')) + if not pager: + lesspath = shutil.which('less') + pager = [lesspath] if lesspath else None + if not pager: + pager = ['more'] + command.Run(*pager, fname) diff --git a/tools/termios_linux.h b/tools/termios_linux.h new file mode 100644 index 0000000000000000000000000000000000000000..d73989b625a28ae3ac75520e3d739145967c6f3a --- /dev/null +++ b/tools/termios_linux.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * termios fuctions to support arbitrary baudrates (on Linux) + * + * Copyright (c) 2021 Pali Rohár <pali@kernel.org> + * Copyright (c) 2021 Marek Behún <marek.behun@nic.cz> + */ + +#ifndef _TERMIOS_LINUX_H_ +#define _TERMIOS_LINUX_H_ + +/* + * We need to use raw TCGETS2/TCSETS2 or TCGETS/TCSETS ioctls with the BOTHER + * flag in struct termios2/termios, defined in Linux headers <asm/ioctls.h> + * (included by <sys/ioctl.h>) and <asm/termbits.h>. Since these headers + * conflict with glibc's header file <termios.h>, it is not possible to use + * libc's termios functions and we need to reimplement them via ioctl() calls. + * + * An arbitrary baudrate is supported when the macro BOTHER is defined. The + * baudrate value itself is then stored into the c_ospeed and c_ispeed members. + * If ioctls TCGETS2/TCSETS2 are defined and supported then these fields are + * present in struct termios2, otherwise these fields are present in struct + * termios. + * + * Note that the Bnnn constants from <termios.h> need not be compatible with Bnnn + * constants from <asm/termbits.h>. + */ + +#include <errno.h> +#include <sys/ioctl.h> +#include <sys/types.h> +#include <asm/termbits.h> + +#if defined(BOTHER) && defined(TCGETS2) +#define termios termios2 +#endif + +static inline int tcgetattr(int fd, struct termios *t) +{ +#if defined(BOTHER) && defined(TCGETS2) + return ioctl(fd, TCGETS2, t); +#else + return ioctl(fd, TCGETS, t); +#endif +} + +static inline int tcsetattr(int fd, int a, const struct termios *t) +{ + int cmd; + + switch (a) { +#if defined(BOTHER) && defined(TCGETS2) + case TCSANOW: + cmd = TCSETS2; + break; + case TCSADRAIN: + cmd = TCSETSW2; + break; + case TCSAFLUSH: + cmd = TCSETSF2; + break; +#else + case TCSANOW: + cmd = TCSETS; + break; + case TCSADRAIN: + cmd = TCSETSW; + break; + case TCSAFLUSH: + cmd = TCSETSF; + break; +#endif + default: + errno = EINVAL; + return -1; + } + + return ioctl(fd, cmd, t); +} + +static inline int tcdrain(int fd) +{ + return ioctl(fd, TCSBRK, 1); +} + +static inline int tcflush(int fd, int q) +{ + return ioctl(fd, TCFLSH, q); +} + +static inline int tcsendbreak(int fd, int d) +{ + return ioctl(fd, TCSBRK, d); +} + +static inline int tcflow(int fd, int a) +{ + return ioctl(fd, TCXONC, a); +} + +static inline pid_t tcgetsid(int fd) +{ + pid_t sid; + + if (ioctl(fd, TIOCGSID, &sid) < 0) + return (pid_t)-1; + + return sid; +} + +static inline speed_t cfgetospeed(const struct termios *t) +{ + return t->c_cflag & CBAUD; +} + +static inline int cfsetospeed(struct termios *t, speed_t s) +{ + if (s & ~CBAUD) { + errno = EINVAL; + return -1; + } + + t->c_cflag &= ~CBAUD; + t->c_cflag |= s; + + return 0; +} + +#ifdef IBSHIFT +static inline speed_t cfgetispeed(const struct termios *t) +{ + speed_t s = (t->c_cflag >> IBSHIFT) & CBAUD; + + if (s == B0) + return cfgetospeed(t); + else + return s; +} + +static inline int cfsetispeed(struct termios *t, speed_t s) +{ + if (s == 0) + s = B0; + + if (s & ~CBAUD) { + errno = EINVAL; + return -1; + } + + t->c_cflag &= ~(CBAUD << IBSHIFT); + t->c_cflag |= s << IBSHIFT; + + return 0; +} +#else /* !IBSHIFT */ +static inline speed_t cfgetispeed(const struct termios *t) +{ + return cfgetospeed(t); +} + +static inline int cfsetispeed(struct termios *t, speed_t s) +{ + return cfsetospeed(t, s); +} +#endif /* !IBSHIFT */ + +static inline int cfsetspeed(struct termios *t, speed_t s) +{ + if (cfsetospeed(t, s)) + return -1; +#ifdef IBSHIFT + if (cfsetispeed(t, s)) + return -1; +#endif + + return 0; +} + +static void cfmakeraw(struct termios *t) +{ + t->c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR | + ICRNL | IXON); + t->c_oflag &= ~OPOST; + t->c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); + t->c_cflag &= ~(CSIZE | PARENB); + t->c_cflag |= CS8; +} + +#endif /* _TERMIOS_LINUX_H_ */