Skip to content
Commit 49fb28a4 authored by Bin Meng's avatar Bin Meng Committed by Tom Rini
Browse files

azure/gitlab/travis: Add RISC-V SPL testing



This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
we test SPL running in M-mode and U-Boot proper running in S-mode,
with a 4-core SMP configuration.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
parent b2c26081
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment