Loading arch/arm/mach-pxa/standby.S +41 −41 Original line number Original line Diff line number Diff line Loading @@ -35,20 +35,20 @@ ENTRY(pxa_cpu_standby) #ifdef CONFIG_PXA3xx #ifdef CONFIG_PXA3xx #define MDCNFG 0x0000 #define PXA3_MDCNFG 0x0000 #define MDCNFG_DMCEN (1 << 30) #define PXA3_MDCNFG_DMCEN (1 << 30) #define DDR_HCAL 0x0060 #define PXA3_DDR_HCAL 0x0060 #define DDR_HCAL_HCRNG 0x1f #define PXA3_DDR_HCAL_HCRNG 0x1f #define DDR_HCAL_HCPROG (1 << 28) #define PXA3_DDR_HCAL_HCPROG (1 << 28) #define DDR_HCAL_HCEN (1 << 31) #define PXA3_DDR_HCAL_HCEN (1 << 31) #define DMCIER 0x0070 #define PXA3_DMCIER 0x0070 #define DMCIER_EDLP (1 << 29) #define PXA3_DMCIER_EDLP (1 << 29) #define DMCISR 0x0078 #define PXA3_DMCISR 0x0078 #define RCOMP 0x0100 #define PXA3_RCOMP 0x0100 #define RCOMP_SWEVAL (1 << 31) #define PXA3_RCOMP_SWEVAL (1 << 31) ENTRY(pm_enter_standby_start) ENTRY(pm_enter_standby_start) mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG) add r1, r1, #0x00100000 add r1, r1, #0x00100000 /* /* Loading @@ -59,54 +59,54 @@ ENTRY(pm_enter_standby_start) * This also means that only the dynamic memory controller * This also means that only the dynamic memory controller * can be reliably accessed in the code following standby. * can be reliably accessed in the code following standby. */ */ ldr r2, [r1] @ Dummy read MDCNFG ldr r2, [r1] @ Dummy read PXA3_MDCNFG mcr p14, 0, r0, c7, c0, 0 mcr p14, 0, r0, c7, c0, 0 .rept 8 .rept 8 nop nop .endr .endr ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN bic r0, r0, #DDR_HCAL_HCEN bic r0, r0, #PXA3_DDR_HCAL_HCEN str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL] 1: ldr r0, [r1, #DDR_HCAL] 1: ldr r0, [r1, #PXA3_DDR_HCAL] tst r0, #DDR_HCAL_HCEN tst r0, #PXA3_DDR_HCAL_HCEN bne 1b bne 1b ldr r0, [r1, #RCOMP] @ Initiate RCOMP ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP orr r0, r0, #RCOMP_SWEVAL orr r0, r0, #PXA3_RCOMP_SWEVAL str r0, [r1, #RCOMP] str r0, [r1, #PXA3_RCOMP] mov r0, #~0 @ Clear interrupts mov r0, #~0 @ Clear interrupts str r0, [r1, #DMCISR] str r0, [r1, #PXA3_DMCISR] ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP] orr r0, r0, #DMCIER_EDLP orr r0, r0, #PXA3_DMCIER_EDLP str r0, [r1, #DMCIER] str r0, [r1, #PXA3_DMCIER] ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN bic r0, r0, #DDR_HCAL_HCRNG bic r0, r0, #PXA3_DDR_HCAL_HCRNG orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL] 1: ldr r0, [r1, #DMCISR] 1: ldr r0, [r1, #PXA3_DMCISR] tst r0, #DMCIER_EDLP tst r0, #PXA3_DMCIER_EDLP beq 1b beq 1b ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN] orr r0, r0, #MDCNFG_DMCEN orr r0, r0, #PXA3_MDCNFG_DMCEN str r0, [r1, #MDCNFG] str r0, [r1, #PXA3_MDCNFG] 1: ldr r0, [r1, #MDCNFG] 1: ldr r0, [r1, #PXA3_MDCNFG] tst r0, #MDCNFG_DMCEN tst r0, #PXA3_MDCNFG_DMCEN beq 1b beq 1b ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG] orr r0, r0, #2 @ HCRNG orr r0, r0, #2 @ HCRNG str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL] ldr r0, [r1, #DMCIER] @ Clear the interrupt ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt bic r0, r0, #0x20000000 bic r0, r0, #0x20000000 str r0, [r1, #DMCIER] str r0, [r1, #PXA3_DMCIER] mov pc, lr mov pc, lr ENTRY(pm_enter_standby_end) ENTRY(pm_enter_standby_end) Loading Loading
arch/arm/mach-pxa/standby.S +41 −41 Original line number Original line Diff line number Diff line Loading @@ -35,20 +35,20 @@ ENTRY(pxa_cpu_standby) #ifdef CONFIG_PXA3xx #ifdef CONFIG_PXA3xx #define MDCNFG 0x0000 #define PXA3_MDCNFG 0x0000 #define MDCNFG_DMCEN (1 << 30) #define PXA3_MDCNFG_DMCEN (1 << 30) #define DDR_HCAL 0x0060 #define PXA3_DDR_HCAL 0x0060 #define DDR_HCAL_HCRNG 0x1f #define PXA3_DDR_HCAL_HCRNG 0x1f #define DDR_HCAL_HCPROG (1 << 28) #define PXA3_DDR_HCAL_HCPROG (1 << 28) #define DDR_HCAL_HCEN (1 << 31) #define PXA3_DDR_HCAL_HCEN (1 << 31) #define DMCIER 0x0070 #define PXA3_DMCIER 0x0070 #define DMCIER_EDLP (1 << 29) #define PXA3_DMCIER_EDLP (1 << 29) #define DMCISR 0x0078 #define PXA3_DMCISR 0x0078 #define RCOMP 0x0100 #define PXA3_RCOMP 0x0100 #define RCOMP_SWEVAL (1 << 31) #define PXA3_RCOMP_SWEVAL (1 << 31) ENTRY(pm_enter_standby_start) ENTRY(pm_enter_standby_start) mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG) add r1, r1, #0x00100000 add r1, r1, #0x00100000 /* /* Loading @@ -59,54 +59,54 @@ ENTRY(pm_enter_standby_start) * This also means that only the dynamic memory controller * This also means that only the dynamic memory controller * can be reliably accessed in the code following standby. * can be reliably accessed in the code following standby. */ */ ldr r2, [r1] @ Dummy read MDCNFG ldr r2, [r1] @ Dummy read PXA3_MDCNFG mcr p14, 0, r0, c7, c0, 0 mcr p14, 0, r0, c7, c0, 0 .rept 8 .rept 8 nop nop .endr .endr ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN bic r0, r0, #DDR_HCAL_HCEN bic r0, r0, #PXA3_DDR_HCAL_HCEN str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL] 1: ldr r0, [r1, #DDR_HCAL] 1: ldr r0, [r1, #PXA3_DDR_HCAL] tst r0, #DDR_HCAL_HCEN tst r0, #PXA3_DDR_HCAL_HCEN bne 1b bne 1b ldr r0, [r1, #RCOMP] @ Initiate RCOMP ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP orr r0, r0, #RCOMP_SWEVAL orr r0, r0, #PXA3_RCOMP_SWEVAL str r0, [r1, #RCOMP] str r0, [r1, #PXA3_RCOMP] mov r0, #~0 @ Clear interrupts mov r0, #~0 @ Clear interrupts str r0, [r1, #DMCISR] str r0, [r1, #PXA3_DMCISR] ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP] orr r0, r0, #DMCIER_EDLP orr r0, r0, #PXA3_DMCIER_EDLP str r0, [r1, #DMCIER] str r0, [r1, #PXA3_DMCIER] ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN bic r0, r0, #DDR_HCAL_HCRNG bic r0, r0, #PXA3_DDR_HCAL_HCRNG orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL] 1: ldr r0, [r1, #DMCISR] 1: ldr r0, [r1, #PXA3_DMCISR] tst r0, #DMCIER_EDLP tst r0, #PXA3_DMCIER_EDLP beq 1b beq 1b ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN] orr r0, r0, #MDCNFG_DMCEN orr r0, r0, #PXA3_MDCNFG_DMCEN str r0, [r1, #MDCNFG] str r0, [r1, #PXA3_MDCNFG] 1: ldr r0, [r1, #MDCNFG] 1: ldr r0, [r1, #PXA3_MDCNFG] tst r0, #MDCNFG_DMCEN tst r0, #PXA3_MDCNFG_DMCEN beq 1b beq 1b ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG] orr r0, r0, #2 @ HCRNG orr r0, r0, #2 @ HCRNG str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL] ldr r0, [r1, #DMCIER] @ Clear the interrupt ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt bic r0, r0, #0x20000000 bic r0, r0, #0x20000000 str r0, [r1, #DMCIER] str r0, [r1, #PXA3_DMCIER] mov pc, lr mov pc, lr ENTRY(pm_enter_standby_end) ENTRY(pm_enter_standby_end) Loading