Commit ffd6cc92 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Bjorn Andersson
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arm64: dts: qcom: sm8250: add description of dcvsh interrupts 



The change adds SM8250 cpufreq-epss controller interrupts for each
CPU core cluster.

Signed-off-by: default avatarVladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211223075640.2924569-1-vladimir.zapolskiy@linaro.org
parent 3b87b01d

arch/arm64/boot/dts/qcom/sm8250.dtsi

+4 −1
Original line number Original line Diff line number Diff line
@@ -4571,7 +4571,10 @@ 




			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

			clock-names = "xo", "alternate";

			clock-names = "xo", "alternate";



			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";

			#freq-domain-cells = <1>;

			#freq-domain-cells = <1>;

		};

		};

	};

	};