Unverified Commit ffb7ca54 authored by Serge Semin's avatar Serge Semin Committed by Mark Brown
Browse files

spi: dw: Add KeemBay Master capability 



In a further commit we'll have to get rid of the update_cr0() callback and
define a DW SSI capability instead. Since Keem Bay master/slave
functionality is controller by the CTRL0 register bitfield, we need to
first move the master mode selection into the internal corresponding
update_cr0 method, which would be activated by means of the dedicated
DW_SPI_CAP_KEEMBAY_MST capability setup.

Note this will be also useful if the driver will be ever altered to
support the DW SPI slave interface.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20200920112914.26501-11-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent cc760f31

drivers/spi/spi-dw-core.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -258,6 +258,7 @@ u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, 
			     struct spi_device *spi,

			     struct spi_device *spi,

			     struct spi_transfer *transfer)

			     struct spi_transfer *transfer)

{

{

	struct dw_spi *dws = spi_controller_get_devdata(master);

	struct chip_data *chip = spi_get_ctldata(spi);

	struct chip_data *chip = spi_get_ctldata(spi);

	u32 cr0;

	u32 cr0;
@@ -281,6 +282,9 @@ u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, 
	/* CTRLR0[13] Shift Register Loop */

	/* CTRLR0[13] Shift Register Loop */

	cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET;

	cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET;





	if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)

		cr0 |= DWC_SSI_CTRLR0_KEEMBAY_MST;



	return cr0;

	return cr0;

}

}

EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a);

EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a);

drivers/spi/spi-dw-mmio.c

+3 −17
Original line number Original line Diff line number Diff line
@@ -48,13 +48,6 @@ struct dw_spi_mmio { 
#define SPARX5_FORCE_ENA			0xa4

#define SPARX5_FORCE_ENA			0xa4

#define SPARX5_FORCE_VAL			0xa8

#define SPARX5_FORCE_VAL			0xa8





/*

 * For Keem Bay, CTRLR0[31] is used to select controller mode.

 * 0: SSI is slave

 * 1: SSI is master

 */

#define KEEMBAY_CTRLR0_SSIC_IS_MST		BIT(31)



struct dw_spi_mscc {

struct dw_spi_mscc {

	struct regmap       *syscon;

	struct regmap       *syscon;

	void __iomem        *spi_mst; /* Not sparx5 */

	void __iomem        *spi_mst; /* Not sparx5 */
@@ -234,20 +227,13 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev, 
	return 0;

	return 0;

}

}





static u32 dw_spi_update_cr0_keembay(struct spi_controller *master,

				     struct spi_device *spi,

				     struct spi_transfer *transfer)

{

	u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer);



	return cr0 | KEEMBAY_CTRLR0_SSIC_IS_MST;

}



static int dw_spi_keembay_init(struct platform_device *pdev,

static int dw_spi_keembay_init(struct platform_device *pdev,

			       struct dw_spi_mmio *dwsmmio)

			       struct dw_spi_mmio *dwsmmio)

{

{

	dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;



	/* Register hook to configure CTRLR0 */

	/* Register hook to configure CTRLR0 */

	dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay;

	dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;





	return 0;

	return 0;

}

}

drivers/spi/spi-dw.h

+8 −0
Original line number Original line Diff line number Diff line
@@ -71,6 +71,13 @@ 
#define DWC_SSI_CTRLR0_FRF_OFFSET	6

#define DWC_SSI_CTRLR0_FRF_OFFSET	6

#define DWC_SSI_CTRLR0_DFS_OFFSET	0

#define DWC_SSI_CTRLR0_DFS_OFFSET	0





/*

 * For Keem Bay, CTRLR0[31] is used to select controller mode.

 * 0: SSI is slave

 * 1: SSI is master

 */

#define DWC_SSI_CTRLR0_KEEMBAY_MST	BIT(31)



/* Bit fields in SR, 7 bits */

/* Bit fields in SR, 7 bits */

#define SR_MASK				0x7f		/* cover 7 bits */

#define SR_MASK				0x7f		/* cover 7 bits */

#define SR_BUSY				(1 << 0)

#define SR_BUSY				(1 << 0)
@@ -101,6 +108,7 @@ enum dw_ssi_type { 




/* DW SPI capabilities */

/* DW SPI capabilities */

#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)

#define DW_SPI_CAP_CS_OVERRIDE		BIT(0)

#define DW_SPI_CAP_KEEMBAY_MST		BIT(1)





struct dw_spi;

struct dw_spi;

struct dw_spi_dma_ops {

struct dw_spi_dma_ops {