Commit ffb4d94b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-10-01' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Daniel Vetter:
 "Some last minute amd fixes:

   - VCN 4.x and GC 11.x fixes, mostly around fw"

* tag 'drm-fixes-2022-10-01' of git://anongit.freedesktop.org/drm/drm:
  drm/amdgpu/gfx11: switch to amdgpu_gfx_rlc_init_microcode
  drm/amdgpu: add helper to init rlc firmware
  drm/amdgpu: add helper to init rlc fw in header v2_4
  drm/amdgpu: add helper to init rlc fw in header v2_3
  drm/amdgpu: add helper to init rlc fw in header v2_2
  drm/amdgpu: add helper to init rlc fw in header v2_1
  drm/amdgpu: add helper to init rlc fw in header v2_0
  drm/amdgpu: save rlcv/rlcp ucode version in amdgpu_gfx
  drm/amdgpu: Enable sram on vcn_4_0_2
  drm/amdgpu: Enable VCN DPG for GC11_0_1
parents e5fa173f 414208e4

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+4 −0
Original line number Diff line number Diff line
@@ -304,6 +304,10 @@ struct amdgpu_gfx { 
	uint32_t			rlc_srlg_feature_version;

	uint32_t			rlc_srls_fw_version;

	uint32_t			rlc_srls_feature_version;

	uint32_t			rlcp_ucode_version;

	uint32_t			rlcp_ucode_feature_version;

	uint32_t			rlcv_ucode_version;

	uint32_t			rlcv_ucode_feature_version;

	uint32_t			mec_feature_version;

	uint32_t			mec2_feature_version;

	bool				mec_fw_write_wait;

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c

+264 −0
Original line number Diff line number Diff line
@@ -272,3 +272,267 @@ void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev) 
			      &adev->gfx.rlc.cp_table_gpu_addr,

			      (void **)&adev->gfx.rlc.cp_table_ptr);

}



static int amdgpu_gfx_rlc_init_microcode_v2_0(struct amdgpu_device *adev)

{

	const struct common_firmware_header *common_hdr;

	const struct rlc_firmware_header_v2_0 *rlc_hdr;

	struct amdgpu_firmware_info *info;

	unsigned int *tmp;

	unsigned int i;



	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;



	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);

	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);

	adev->gfx.rlc.save_and_restore_offset =

		le32_to_cpu(rlc_hdr->save_and_restore_offset);

	adev->gfx.rlc.clear_state_descriptor_offset =

		le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);

	adev->gfx.rlc.avail_scratch_ram_locations =

		le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);

	adev->gfx.rlc.reg_restore_list_size =

		le32_to_cpu(rlc_hdr->reg_restore_list_size);

	adev->gfx.rlc.reg_list_format_start =

		le32_to_cpu(rlc_hdr->reg_list_format_start);

	adev->gfx.rlc.reg_list_format_separate_start =

		le32_to_cpu(rlc_hdr->reg_list_format_separate_start);

	adev->gfx.rlc.starting_offsets_start =

		le32_to_cpu(rlc_hdr->starting_offsets_start);

	adev->gfx.rlc.reg_list_format_size_bytes =

		le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);

	adev->gfx.rlc.reg_list_size_bytes =

		le32_to_cpu(rlc_hdr->reg_list_size_bytes);

	adev->gfx.rlc.register_list_format =

		kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +

			adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);

	if (!adev->gfx.rlc.register_list_format) {

		dev_err(adev->dev, "failed to allocate memory for rlc register_list_format\n");

		return -ENOMEM;

	}



	tmp = (unsigned int *)((uintptr_t)rlc_hdr +

			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));

	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)

		adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);



	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;



	tmp = (unsigned int *)((uintptr_t)rlc_hdr +

			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));

	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)

		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];

		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;

		info->fw = adev->gfx.rlc_fw;

		if (info->fw) {

			common_hdr = (const struct common_firmware_header *)info->fw->data;

			adev->firmware.fw_size +=

				ALIGN(le32_to_cpu(common_hdr->ucode_size_bytes), PAGE_SIZE);

		}

	}



	return 0;

}



static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_1 *rlc_hdr;

	struct amdgpu_firmware_info *info;



	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);

	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);

	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);

	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);

	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);

	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);

	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);

	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);

	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);

	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);

	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);

	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);

	adev->gfx.rlc.reg_list_format_direct_reg_list_length =

		le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.save_restore_list_srm_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);

		}

	}

}



static void amdgpu_gfx_rlc_init_microcode_v2_2(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_2 *rlc_hdr;

	struct amdgpu_firmware_info *info;



	rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);

	adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);

	adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);

	adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (adev->gfx.rlc.rlc_iram_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.rlc_dram_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);

		}

	}

}



static void amdgpu_gfx_rlc_init_microcode_v2_3(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_3 *rlc_hdr;

	struct amdgpu_firmware_info *info;



	rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version);

	adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version);

	adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes);

	adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes);



	adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version);

	adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version);

	adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes);

	adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (adev->gfx.rlc.rlcp_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_P;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.rlcv_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V];

			info->ucode_id = AMDGPU_UCODE_ID_RLC_V;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE);

		}

	}

}



static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev)

{

	const struct rlc_firmware_header_v2_4 *rlc_hdr;

	struct amdgpu_firmware_info *info;



	rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);

	adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);

	adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}

	}

}



int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,

				  uint16_t version_major,

				  uint16_t version_minor)

{

	int err;



	if (version_major < 2) {

		/* only support rlc_hdr v2.x and onwards */

		dev_err(adev->dev, "unsupported rlc fw hdr\n");

		return -EINVAL;

	}



	/* is_rlc_v2_1 is still used in APU code path */

	if (version_major == 2 && version_minor == 1)

		adev->gfx.rlc.is_rlc_v2_1 = true;



	if (version_minor >= 0) {

		err = amdgpu_gfx_rlc_init_microcode_v2_0(adev);

		if (err) {

			dev_err(adev->dev, "fail to init rlc v2_0 microcode\n");

			return err;

		}

	}

	if (version_minor >= 1)

		amdgpu_gfx_rlc_init_microcode_v2_1(adev);

	if (version_minor >= 2)

		amdgpu_gfx_rlc_init_microcode_v2_2(adev);

	if (version_minor == 3)

		amdgpu_gfx_rlc_init_microcode_v2_3(adev);

	if (version_minor == 4)

		amdgpu_gfx_rlc_init_microcode_v2_4(adev);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

+3 −1
Original line number Diff line number Diff line
@@ -267,5 +267,7 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev); 
int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);

void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);

void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);



int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,

				  uint16_t version_major,

				  uint16_t version_minor);

#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+4 −0
Original line number Diff line number Diff line
@@ -260,8 +260,12 @@ struct rlc_firmware_header_v2_2 { 
/* version_major=2, version_minor=3 */

struct rlc_firmware_header_v2_3 {

    struct rlc_firmware_header_v2_2 v2_2;

    uint32_t rlcp_ucode_version;

    uint32_t rlcp_ucode_feature_version;

    uint32_t rlcp_ucode_size_bytes;

    uint32_t rlcp_ucode_offset_bytes;

    uint32_t rlcv_ucode_version;

    uint32_t rlcv_ucode_feature_version;

    uint32_t rlcv_ucode_size_bytes;

    uint32_t rlcv_ucode_offset_bytes;

};

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+1 −1
Original line number Diff line number Diff line
@@ -191,7 +191,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
		fw_name = FIRMWARE_VCN4_0_2;

		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&

			(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))

			adev->vcn.indirect_sram = false;

			adev->vcn.indirect_sram = true;

		break;

	case IP_VERSION(4, 0, 4):

		fw_name = FIRMWARE_VCN4_0_4;