Commit ffb20c2e authored by Zhang Rui's avatar Zhang Rui Committed by Peter Zijlstra
Browse files

perf/x86/rapl: Add msr mask support 



In some cases, when probing a perf MSR, we're probing certain bits of the
MSR instead of the whole register, thus only these bits should be checked.

For example, for RAPL ENERGY_STATUS MSR, only the lower 32 bits represents
the energy counter, and the higher 32bits are reserved.

Introduce a new mask field in struct perf_msr to allow probing certain
bits of a MSR.

This change is transparent to the current perf_msr_probe() users.

Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20210204161816.12649-1-rui.zhang@intel.com
parent b3c3361f

arch/x86/events/probe.c

+6 −1
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data) 
	for (bit = 0; bit < cnt; bit++) {

		if (!msr[bit].no_check) {

			struct attribute_group *grp = msr[bit].grp;

			u64 mask;



			/* skip entry with no group */

			if (!grp)
@@ -44,8 +45,12 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data) 
			/* Virt sucks; you cannot tell if a R/O MSR is present :/ */

			if (rdmsrl_safe(msr[bit].msr, &val))

				continue;



			mask = msr[bit].mask;

			if (!mask)

				mask = ~0ULL;

			/* Disable zero counters if requested. */

			if (!zero && !val)

			if (!zero && !(val & mask))

				continue;



			grp->is_visible = NULL;

arch/x86/events/probe.h

+4 −3
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ struct perf_msr { 
	struct attribute_group	*grp;

	bool			(*test)(int idx, void *data);

	bool			no_check;

	u64			mask;

};



unsigned long