Commit ff8be964 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_updates_for_v5.17_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras 

Pull EDAC updates from Borislav Petkov:

 - Add support for version 3 of the Synopsys DDR controller to
   synopsys_edac

 - Add support for DRR5 and new models 0x10-0x1f and 0x50-0x5f of AMD
   family 0x19 CPUs to amd64_edac

 - The usual set of fixes and cleanups

* tag 'edac_updates_for_v5.17_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/amd64: Add support for family 19h, models 50h-5fh
  EDAC/sb_edac: Remove redundant initialization of variable rc
  RAS/CEC: Remove a repeated 'an' in a comment
  EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh
  EDAC: Add RDDR5 and LRDDR5 memory types
  EDAC/sifive: Fix non-kernel-doc comment
  dt-bindings: memory: Add entry for version 3.80a
  EDAC/synopsys: Enable the driver on Intel's N5X platform
  EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR
  EDAC/synopsys: Use the quirk for version instead of ddr version
parents 7e740ae6 da0119a9

Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ properties: 
    enum:

      - xlnx,zynq-ddrc-a05

      - xlnx,zynqmp-ddrc-2.40a

      - snps,ddrc-3.80a



  interrupts:

    maxItems: 1

drivers/edac/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -484,7 +484,7 @@ config EDAC_ARMADA_XP 


config EDAC_SYNOPSYS

	tristate "Synopsys DDR Memory Controller"

	depends on ARCH_ZYNQ || ARCH_ZYNQMP

	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA

	help

	  Support for error detection and correction on the Synopsys DDR

	  memory controller.

drivers/edac/amd64_edac.c

+35 −1
Original line number Diff line number Diff line
@@ -2925,6 +2925,26 @@ static struct amd64_family_type family_types[] = { 
			.dbam_to_cs		= f17_addr_mask_to_cs_size,

		}

	},

	[F19_M10H_CPUS] = {

		.ctl_name = "F19h_M10h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6,

		.max_mcs = 12,

		.ops = {

			.early_channel_count	= f17_early_channel_count,

			.dbam_to_cs		= f17_addr_mask_to_cs_size,

		}

	},

	[F19_M50H_CPUS] = {

		.ctl_name = "F19h_M50h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,

		.f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,

			.dbam_to_cs		= f17_addr_mask_to_cs_size,

		}

	},

};



/*
@@ -3962,11 +3982,25 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) 
		break;



	case 0x19:

		if (pvt->model >= 0x20 && pvt->model <= 0x2f) {

		if (pvt->model >= 0x10 && pvt->model <= 0x1f) {

			fam_type = &family_types[F19_M10H_CPUS];

			pvt->ops = &family_types[F19_M10H_CPUS].ops;

			break;

		} else if (pvt->model >= 0x20 && pvt->model <= 0x2f) {

			fam_type = &family_types[F17_M70H_CPUS];

			pvt->ops = &family_types[F17_M70H_CPUS].ops;

			fam_type->ctl_name = "F19h_M20h";

			break;

		} else if (pvt->model >= 0x50 && pvt->model <= 0x5f) {

			fam_type = &family_types[F19_M50H_CPUS];

			pvt->ops = &family_types[F19_M50H_CPUS].ops;

			fam_type->ctl_name = "F19h_M50h";

			break;

		} else if (pvt->model >= 0xa0 && pvt->model <= 0xaf) {

			fam_type = &family_types[F19_M10H_CPUS];

			pvt->ops = &family_types[F19_M10H_CPUS].ops;

			fam_type->ctl_name = "F19h_MA0h";

			break;

		}

		fam_type	= &family_types[F19_CPUS];

		pvt->ops	= &family_types[F19_CPUS].ops;

drivers/edac/amd64_edac.h

+7 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ 
/* Hardware limit on ChipSelect rows per MC and processors per system */

#define NUM_CHIPSELECTS			8

#define DRAM_RANGES			8

#define NUM_CONTROLLERS			8

#define NUM_CONTROLLERS			12



#define ON true

#define OFF false
@@ -126,6 +126,10 @@ 
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446

#define PCI_DEVICE_ID_AMD_19H_DF_F0	0x1650

#define PCI_DEVICE_ID_AMD_19H_DF_F6	0x1656

#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad

#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3

#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a

#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670



/*

 * Function 1 - Address Map
@@ -298,6 +302,8 @@ enum amd_families { 
	F17_M60H_CPUS,

	F17_M70H_CPUS,

	F19_CPUS,

	F19_M10H_CPUS,

	F19_M50H_CPUS,

	NUM_FAMILIES,

};

drivers/edac/edac_mc.c

+2 −0
Original line number Diff line number Diff line
@@ -162,6 +162,8 @@ const char * const edac_mem_types[] = { 
	[MEM_LPDDR4]	= "Low-Power-DDR4-RAM",

	[MEM_LRDDR4]	= "Load-Reduced-DDR4-RAM",

	[MEM_DDR5]	= "Unbuffered-DDR5",

	[MEM_RDDR5]	= "Registered-DDR5",

	[MEM_LRDDR5]	= "Load-Reduced-DDR5-RAM",

	[MEM_NVDIMM]	= "Non-volatile-RAM",

	[MEM_WIO2]	= "Wide-IO-2",

	[MEM_HBM2]	= "High-bandwidth-memory-Gen2",