Commit ff1c42cd authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64: Explicitly document boot requirements for SVE 



We do not currently document the requirements for configuration of the
SVE system registers when booting the kernel, let's do so for completeness.

We don't have a hard requirement that the vector lengths configured on
different CPUs on initial boot be consistent since we have logic to
constrain to the minimum supported value but we will reject any late CPUs
which can't support the current maximum and introducing the concept of
late CPUs seemed more complex than was useful so we require that all CPUs
use the same value.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210412151955.16078-4-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b30dbf4d

Documentation/arm64/booting.rst

+18 −0
Original line number Diff line number Diff line
@@ -287,6 +287,24 @@ Before jumping into the kernel, the following conditions must be met: 


    - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.



  For CPUs with the Scalable Vector Extension (FEAT_SVE) present:



  - if EL3 is present:



    - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.



    - ZCR_EL3.LEN must be initialised to the same value for all CPUs the

      kernel is executed on.



  - If the kernel is entered at EL1 and EL2 is present:



    - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.



    - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.



    - ZCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.  Where the values documented