Merge tag 'arm-boardfile-remove-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

.. SPDX-License-Identifier: GPL-2.0

The VPBE V4L2 driver design

===========================

Functional partitioning

-----------------------

Consists of the following:

 1. V4L2 display driver

    Implements creation of video2 and video3 device nodes and

    provides v4l2 device interface to manage VID0 and VID1 layers.

 2. Display controller

    Loads up VENC, OSD and external encoders such as ths8200. It provides

    a set of API calls to V4L2 drivers to set the output/standards

    in the VENC or external sub devices. It also provides

    a device object to access the services from OSD subdevice

    using sub device ops. The connection of external encoders to VENC LCD

    controller port is done at init time based on default output and standard

    selection or at run time when application change the output through

    V4L2 IOCTLs.

    When connected to an external encoder, vpbe controller is also responsible

    for setting up the interface between VENC and external encoders based on

    board specific settings (specified in board-xxx-evm.c). This allows

    interfacing external encoders such as ths8200. The setup_if_config()

    is implemented for this as well as configure_venc() (part of the next patch)

    API to set timings in VENC for a specific display resolution. As of this

    patch series, the interconnection and enabling and setting of the external

    encoders is not present, and would be a part of the next patch series.

 3. VENC subdevice module

    Responsible for setting outputs provided through internal DACs and also

    setting timings at LCD controller port when external encoders are connected

    at the port or LCD panel timings required. When external encoder/LCD panel

    is connected, the timings for a specific standard/preset is retrieved from

    the board specific table and the values are used to set the timings in

    venc using non-standard timing mode.

    Support LCD Panel displays using the VENC. For example to support a Logic

    PD display, it requires setting up the LCD controller port with a set of

    timings for the resolution supported and setting the dot clock. So we could

    add the available outputs as a board specific entry (i.e add the "LogicPD"

    output name to board-xxx-evm.c). A table of timings for various LCDs

    supported can be maintained in the board specific setup file to support

    various LCD displays.As of this patch a basic driver is present, and this

    support for external encoders and displays forms a part of the next

    patch series.

 4. OSD module

    OSD module implements all OSD layer management and hardware specific

    features. The VPBE module interacts with the OSD for enabling and

    disabling appropriate features of the OSD.

Current status

--------------

A fully functional working version of the V4L2 driver is available. This

driver has been tested with NTSC and PAL standards and buffer streaming.

video-mux          Video Multiplexer

vpif_display       TI DaVinci VPIF V4L2-Display

vpif_capture       TI DaVinci VPIF video capture

vpss               TI DaVinci VPBE V4L2-Display

vsp1               Renesas VSP1 Video Processing Engine

xilinx-tpg         Xilinx Video Test Pattern Generator

xilinx-video       Xilinx Video IP (EXPERIMENTAL)

	cafe_ccic

	cpia2

	cx88

	davinci-vpbe

	fimc

	imx

	imx7

   sunxi

   samsung/index

   samsung-s3c24xx/index

   sunxi/clocks

.. SPDX-License-Identifier: GPL-2.0-only

=======================

S3C24XX CPUfreq support

=======================

Introduction

------------

 The S3C24XX series support a number of power saving systems, such as

 the ability to change the core, memory and peripheral operating

 frequencies. The core control is exported via the CPUFreq driver

 which has a number of different manual or automatic controls over the

 rate the core is running at.

 There are two forms of the driver depending on the specific CPU and

 how the clocks are arranged. The first implementation used as single

 PLL to feed the ARM, memory and peripherals via a series of dividers

 and muxes and this is the implementation that is documented here. A

 newer version where there is a separate PLL and clock divider for the

 ARM core is available as a separate driver.

Layout

------

 The code core manages the CPU specific drivers, any data that they

 need to register and the interface to the generic drivers/cpufreq

 system. Each CPU registers a driver to control the PLL, clock dividers

 and anything else associated with it. Any board that wants to use this

 framework needs to supply at least basic details of what is required.

 The core registers with drivers/cpufreq at init time if all the data

 necessary has been supplied.

CPU support

-----------

 The support for each CPU depends on the facilities provided by the

 SoC and the driver as each device has different PLL and clock chains

 associated with it.

Slow Mode

---------

 The SLOW mode where the PLL is turned off altogether and the

 system is fed by the external crystal input is currently not

 supported.

sysfs

-----

 The core code exports extra information via sysfs in the directory

 devices/system/cpu/cpu0/arch-freq.

Board Support

-------------

 Each board that wants to use the cpufreq code must register some basic

 information with the core driver to provide information about what the

 board requires and any restrictions being placed on it.

 The board needs to supply information about whether it needs the IO bank

 timings changing, any maximum frequency limits and information about the

 SDRAM refresh rate.

Document Author

---------------

Ben Dooks, Copyright 2009 Simtec Electronics