Unverified Commit fed14be4 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
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RISC-V: simplify register width check in ISA string parsing 



Saving off the `isa` pointer to a temp variable, followed by checking if
it has been incremented is a bit of an odd pattern. Perhaps it was done
to avoid a funky looking if statement mixed with the ifdeffery.

Now that we use IS_ENABLED() here just return from the parser as soon as
we detect a mismatch between the string and the currently running
kernel.

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarSunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-splatter-bacterium-a75bb9f0d0b7@spud


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 748462b5

arch/riscv/kernel/cpufeature.c

+7 −8
Original line number Diff line number Diff line
@@ -126,7 +126,6 @@ void __init riscv_fill_hwcap(void) 
	for_each_possible_cpu(cpu) {

		unsigned long this_hwcap = 0;

		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);

		const char *temp;



		if (acpi_disabled) {

			node = of_cpu_device_node_get(cpu);
@@ -149,14 +148,14 @@ void __init riscv_fill_hwcap(void) 
			}

		}



		temp = isa;

		if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4))

			isa += 4;

		else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4))

			isa += 4;

		/* The riscv,isa DT property must start with rv64 or rv32 */

		if (temp == isa)

		if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4))

			continue;



		if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4))

			continue;



		isa += 4;



		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);

		for (; *isa; ++isa) {

			const char *ext = isa++;