Commit febe950d authored by Peter Zijlstra's avatar Peter Zijlstra
Browse files

arch: Remove cmpxchg_double 



No moar users, remove the monster.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarHeiko Carstens <hca@linux.ibm.com>
Tested-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20230531132323.991907085@infradead.org
parent 6801be4f

Documentation/core-api/this_cpu_ops.rst

+0 −2
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ preemption and interrupts:: 
	this_cpu_add_return(pcp, val)

	this_cpu_xchg(pcp, nval)

	this_cpu_cmpxchg(pcp, oval, nval)

	this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

	this_cpu_sub(pcp, val)

	this_cpu_inc(pcp)

	this_cpu_dec(pcp)
@@ -242,7 +241,6 @@ safe:: 
	__this_cpu_add_return(pcp, val)

	__this_cpu_xchg(pcp, nval)

	__this_cpu_cmpxchg(pcp, oval, nval)

	__this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

	__this_cpu_sub(pcp, val)

	__this_cpu_inc(pcp)

	__this_cpu_dec(pcp)

arch/arm64/include/asm/atomic_ll_sc.h

+0 −33
Original line number Diff line number Diff line
@@ -294,39 +294,6 @@ __CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L) 


#undef __CMPXCHG_CASE



#define __CMPXCHG_DBL(name, mb, rel, cl)				\

static __always_inline long						\

__ll_sc__cmpxchg_double##name(unsigned long old1,			\

				      unsigned long old2,		\

				      unsigned long new1,		\

				      unsigned long new2,		\

				      volatile void *ptr)		\

{									\

	unsigned long tmp, ret;						\

									\

	asm volatile("// __cmpxchg_double" #name "\n"			\

	"	prfm	pstl1strm, %2\n"				\

	"1:	ldxp	%0, %1, %2\n"					\

	"	eor	%0, %0, %3\n"					\

	"	eor	%1, %1, %4\n"					\

	"	orr	%1, %0, %1\n"					\

	"	cbnz	%1, 2f\n"					\

	"	st" #rel "xp	%w0, %5, %6, %2\n"			\

	"	cbnz	%w0, 1b\n"					\

	"	" #mb "\n"						\

	"2:"								\

	: "=&r" (tmp), "=&r" (ret), "+Q" (*(__uint128_t *)ptr)		\

	: "r" (old1), "r" (old2), "r" (new1), "r" (new2)		\

	: cl);								\

									\

	return ret;							\

}



__CMPXCHG_DBL(   ,        ,  ,         )

__CMPXCHG_DBL(_mb, dmb ish, l, "memory")



#undef __CMPXCHG_DBL



union __u128_halves {

	u128 full;

	struct {

arch/arm64/include/asm/atomic_lse.h

+0 −36
Original line number Diff line number Diff line
@@ -281,42 +281,6 @@ __CMPXCHG_CASE(x, , mb_, 64, al, "memory") 


#undef __CMPXCHG_CASE



#define __CMPXCHG_DBL(name, mb, cl...)					\

static __always_inline long						\

__lse__cmpxchg_double##name(unsigned long old1,				\

					 unsigned long old2,		\

					 unsigned long new1,		\

					 unsigned long new2,		\

					 volatile void *ptr)		\

{									\

	unsigned long oldval1 = old1;					\

	unsigned long oldval2 = old2;					\

	register unsigned long x0 asm ("x0") = old1;			\

	register unsigned long x1 asm ("x1") = old2;			\

	register unsigned long x2 asm ("x2") = new1;			\

	register unsigned long x3 asm ("x3") = new2;			\

	register unsigned long x4 asm ("x4") = (unsigned long)ptr;	\

									\

	asm volatile(							\

	__LSE_PREAMBLE							\

	"	casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\

	"	eor	%[old1], %[old1], %[oldval1]\n"			\

	"	eor	%[old2], %[old2], %[oldval2]\n"			\

	"	orr	%[old1], %[old1], %[old2]"			\

	: [old1] "+&r" (x0), [old2] "+&r" (x1),				\

	  [v] "+Q" (*(__uint128_t *)ptr)				\

	: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4),		\

	  [oldval1] "r" (oldval1), [oldval2] "r" (oldval2)		\

	: cl);								\

									\

	return x0;							\

}



__CMPXCHG_DBL(   ,   )

__CMPXCHG_DBL(_mb, al, "memory")



#undef __CMPXCHG_DBL



#define __CMPXCHG128(name, mb, cl...)					\

static __always_inline u128						\

__lse__cmpxchg128##name(volatile u128 *ptr, u128 old, u128 new)		\

arch/arm64/include/asm/cmpxchg.h

+0 −46
Original line number Diff line number Diff line
@@ -130,22 +130,6 @@ __CMPXCHG_CASE(mb_, 64) 


#undef __CMPXCHG_CASE



#define __CMPXCHG_DBL(name)						\

static inline long __cmpxchg_double##name(unsigned long old1,		\

					 unsigned long old2,		\

					 unsigned long new1,		\

					 unsigned long new2,		\

					 volatile void *ptr)		\

{									\

	return __lse_ll_sc_body(_cmpxchg_double##name, 			\

				old1, old2, new1, new2, ptr);		\

}



__CMPXCHG_DBL(   )

__CMPXCHG_DBL(_mb)



#undef __CMPXCHG_DBL



#define __CMPXCHG128(name)						\

static inline u128 __cmpxchg128##name(volatile u128 *ptr,		\

				      u128 old, u128 new)		\
@@ -211,36 +195,6 @@ __CMPXCHG_GEN(_mb) 
#define arch_cmpxchg64			arch_cmpxchg

#define arch_cmpxchg64_local		arch_cmpxchg_local



/* cmpxchg_double */

#define system_has_cmpxchg_double()     1



#define __cmpxchg_double_check(ptr1, ptr2)					\

({										\

	if (sizeof(*(ptr1)) != 8)						\

		BUILD_BUG();							\

	VM_BUG_ON((unsigned long *)(ptr2) - (unsigned long *)(ptr1) != 1);	\

})



#define arch_cmpxchg_double(ptr1, ptr2, o1, o2, n1, n2)				\

({										\

	int __ret;								\

	__cmpxchg_double_check(ptr1, ptr2);					\

	__ret = !__cmpxchg_double_mb((unsigned long)(o1), (unsigned long)(o2),	\

				     (unsigned long)(n1), (unsigned long)(n2),	\

				     ptr1);					\

	__ret;									\

})



#define arch_cmpxchg_double_local(ptr1, ptr2, o1, o2, n1, n2)			\

({										\

	int __ret;								\

	__cmpxchg_double_check(ptr1, ptr2);					\

	__ret = !__cmpxchg_double((unsigned long)(o1), (unsigned long)(o2),	\

				  (unsigned long)(n1), (unsigned long)(n2),	\

				  ptr1);					\

	__ret;									\

})



/* cmpxchg128 */

#define system_has_cmpxchg128()		1

arch/arm64/include/asm/percpu.h

+0 −10
Original line number Diff line number Diff line
@@ -145,16 +145,6 @@ PERCPU_RET_OP(add, add, ldadd) 
 * preemption point when TIF_NEED_RESCHED gets set while preemption is

 * disabled.

 */

#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2)		\

({									\

	int __ret;							\

	preempt_disable_notrace();					\

	__ret = cmpxchg_double_local(	raw_cpu_ptr(&(ptr1)),		\

					raw_cpu_ptr(&(ptr2)),		\

					o1, o2, n1, n2);		\

	preempt_enable_notrace();					\

	__ret;								\

})



#define _pcp_protect(op, pcp, ...)					\

({									\