Commit fe8a5005 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: cpu-8996: support using GPLL0 as SMUX input 



In some cases the driver might need using GPLL0 to drive CPU clocks.
Bring it in through the sys_apcs_aux clock.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-6-dmitry.baryshkov@linaro.org
parent be4e65d1

drivers/clk/qcom/clk-cpu-8996.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -12,6 +12,8 @@ 
 *                              +-------+

 *                              +-------+

 *               XO             |       |

 *               XO             |       |

 *           +------------------>0      |

 *           +------------------>0      |

 *               SYS_APCS_AUX   |       |

 *           +------------------>3      |

 *                              |       |

 *                              |       |

 *                    PLL/2     | SMUX  +----+

 *                    PLL/2     | SMUX  +----+

 *                      +------->1      |    |

 *                      +------->1      |    |
@@ -310,20 +312,29 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = { 
	.determine_rate = clk_cpu_8996_pmux_determine_rate,

	.determine_rate = clk_cpu_8996_pmux_determine_rate,

};

};





static const struct parent_map smux_parent_map[] = {

	{ .cfg = 0, }, /* xo */

	{ .cfg = 1, }, /* pll */

	{ .cfg = 3, }, /* sys_apcs_aux */

};



static const struct clk_parent_data pwrcl_smux_parents[] = {

static const struct clk_parent_data pwrcl_smux_parents[] = {

	{ .fw_name = "xo" },

	{ .fw_name = "xo" },

	{ .hw = &pwrcl_pll_postdiv.hw },

	{ .hw = &pwrcl_pll_postdiv.hw },

	{ .fw_name = "sys_apcs_aux" },

};

};





static const struct clk_parent_data perfcl_smux_parents[] = {

static const struct clk_parent_data perfcl_smux_parents[] = {

	{ .fw_name = "xo" },

	{ .fw_name = "xo" },

	{ .hw = &perfcl_pll_postdiv.hw },

	{ .hw = &perfcl_pll_postdiv.hw },

	{ .fw_name = "sys_apcs_aux" },

};

};





static struct clk_regmap_mux pwrcl_smux = {

static struct clk_regmap_mux pwrcl_smux = {

	.reg = PWRCL_REG_OFFSET + MUX_OFFSET,

	.reg = PWRCL_REG_OFFSET + MUX_OFFSET,

	.shift = 2,

	.shift = 2,

	.width = 2,

	.width = 2,

	.parent_map = smux_parent_map,

	.clkr.hw.init = &(struct clk_init_data) {

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "pwrcl_smux",

		.name = "pwrcl_smux",

		.parent_data = pwrcl_smux_parents,

		.parent_data = pwrcl_smux_parents,
@@ -337,6 +348,7 @@ static struct clk_regmap_mux perfcl_smux = { 
	.reg = PERFCL_REG_OFFSET + MUX_OFFSET,

	.reg = PERFCL_REG_OFFSET + MUX_OFFSET,

	.shift = 2,

	.shift = 2,

	.width = 2,

	.width = 2,

	.parent_map = smux_parent_map,

	.clkr.hw.init = &(struct clk_init_data) {

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "perfcl_smux",

		.name = "perfcl_smux",

		.parent_data = perfcl_smux_parents,

		.parent_data = perfcl_smux_parents,