Commit fe6dd2a4 authored by Yong Wu's avatar Yong Wu Committed by Krzysztof Kozlowski
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memory: mtk-smi: mt8195: Add initial setting for smi-larb 



To improve the performance, We add some initial setting for smi larbs.
there are two part:
1), Each port has the special ostd(outstanding) value in each larb.
2), Two general settings for each larb.
   a. THRT_UPDATE: the value in bits[7:4] of 0x24 is not so good.
   The HW default is 4, and we expect it is 5, thus, add a flag to update
   it. This is only a DE recommendatory value, not a actual issue.
   The register name(THRT_CON) means: throttling control, and the field
   RD_NU_LMT means: Read Non-ultra commands limit.
   This change means update the Read non-ultra command from 4 to 5 here.

   b. SW_FLAG: Set 1 to the FLAG register. this is only for helping
   debug. We could confirm if the larb is reset from this value is 1 or 0.

In some SoC, this setting maybe changed dynamically for some special case
like 4K, and this initial setting is enough in mt8195.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Link: https://lore.kernel.org/r/20210914113703.31466-13-yong.wu@mediatek.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
parent 431e9cab

drivers/memory/mtk-smi.c

+78 −1
Original line number Diff line number Diff line
@@ -32,6 +32,15 @@ 
#define SMI_DUMMY			0x444



/* SMI LARB */

#define SMI_LARB_CMD_THRT_CON		0x24

#define SMI_LARB_THRT_RD_NU_LMT_MSK	GENMASK(7, 4)

#define SMI_LARB_THRT_RD_NU_LMT		(5 << 4)



#define SMI_LARB_SW_FLAG		0x40

#define SMI_LARB_SW_FLAG_1		0x1



#define SMI_LARB_OSTDL_PORT		0x200

#define SMI_LARB_OSTDL_PORTx(id)	(SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))



/* Below are about mmu enable registers, they are different in SoCs */

/* gen1: mt2701 */
@@ -68,6 +77,11 @@ 
})



#define SMI_COMMON_INIT_REGS_NR		6

#define SMI_LARB_PORT_NR_MAX		32



#define MTK_SMI_FLAG_THRT_UPDATE	BIT(0)

#define MTK_SMI_FLAG_SW_FLAG		BIT(1)

#define MTK_SMI_CAPS(flags, _x)		(!!((flags) & (_x)))



struct mtk_smi_reg_pair {

	unsigned int		offset;
@@ -108,6 +122,8 @@ struct mtk_smi_larb_gen { 
	int port_in_larb[MTK_LARB_NR_MAX + 1];

	void (*config_port)(struct device *dev);

	unsigned int			larb_direct_to_common_mask;

	unsigned int			flags_general;

	const u8			(*ostd)[SMI_LARB_PORT_NR_MAX];

};



struct mtk_smi {
@@ -224,12 +240,26 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) 
static void mtk_smi_larb_config_port_gen2_general(struct device *dev)

{

	struct mtk_smi_larb *larb = dev_get_drvdata(dev);

	u32 reg;

	u32 reg, flags_general = larb->larb_gen->flags_general;

	const u8 *larbostd = larb->larb_gen->ostd[larb->larbid];

	int i;



	if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)

		return;



	if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {

		reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);

		reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;

		reg |= SMI_LARB_THRT_RD_NU_LMT;

		writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);

	}



	if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))

		writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);



	for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)

		writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));



	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {

		reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));

		reg |= F_MMU_EN;
@@ -238,6 +268,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 
	}

}



static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {

	[0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */

	[1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */

	[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},      /* ... */

	[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},

	[4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},

	[5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},

	[6] = {0x06, 0x01, 0x06, 0x0a,},

	[7] = {0x0c, 0x0c, 0x12,},

	[8] = {0x0c, 0x0c, 0x12,},

	[9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,

		0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},

	[10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,

		0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,

		0x0d, 0x06, 0x10, 0x10,},

	[11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},

	[12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},

	[13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},

	[14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,

		0x01, 0x02, 0x02, 0x08, 0x02,},

	[15] = {},

	[16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,

		0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},

	[17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},

	[18] = {0x12, 0x06, 0x12, 0x06,},

	[19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,

		0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,

		0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},

	[20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,

		0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,

		0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},

	[21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},

	[22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},

	[23] = {0x18, 0x01,},

	[24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,

		0x01, 0x01,},

	[25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,

		0x02, 0x01,},

	[26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,

		0x02, 0x01,},

	[27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,

		0x02, 0x01,},

	[28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},

};



static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {

	.port_in_larb = {

		LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
@@ -280,6 +355,8 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 


static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {

	.config_port                = mtk_smi_larb_config_port_gen2_general,

	.flags_general	            = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG,

	.ostd		            = mtk_smi_larb_mt8195_ostd,

};



static const struct of_device_id mtk_smi_larb_of_ids[] = {