Commit fe5fc987 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.20' of... 

Merge tag 'phy-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

Vinod writes:

phy-for-5.20

  - New support:
        - Samsung FSD ufs phy
	- Mediatek MT8365 dsi and tphy support
	- Amlogic G12A Analog D-PHY driver
	- Mediatek MT8188 tphy support
	- Mediatek PCIe phy driver
	- Cadence J721e DPHY support
	- Qualcomm IPQ8074 PCIe Gen3 PHY support
	- Nvidia Tegra PCIe PIPE2UPHY support

  - Updates:
	- Split of Qualcomm combo qmp phy driver to ufs, usb, pcie phy
	  drivers and associated cleanup of these drivers

* tag 'phy-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (115 commits)
  dt-bindings: phy: mediatek: tphy: add compatible for mt8188
  phy: rockchip-inno-usb2: Ignore OTG IRQs in host mode
  phy: qcom-qmp-usb: statify qmp_phy_vreg_l
  phy: stm32: fix error return in stm32_usbphyc_phy_init
  phy: phy-mtk-dp: change mtk_dp_phy_driver to static
  phy: freescale: Add i.MX8qm Mixel LVDS PHY support
  dt-bindings: phy: Add Freescale i.MX8qm Mixel LVDS PHY binding
  dt-bindings: vendor-prefixes: Add prefix for Mixel, Inc.
  phy: cadence-torrent: Remove unused `regmap` field from state struct
  phy: cadence: Sierra: Remove unused `regmap` field from state struct
  phy: samsung-ufs: ufs: change phy on/off control
  phy: samsung-ufs: convert phy clk usage to clk_bulk API
  phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register
  phy: qcom-qmp-usb: replace FLL layout writes for msm8996
  phy: qcom-qmp: pcs-pcie-v4: add missing registers
  phy: qcom-qmp: pcs-v3: add missing registers
  phy: qcom-qmp: qserdes-com-v5: add missing registers
  phy: qcom-qmp: qserdes-com-v4: add missing registers
  phy: qcom-qmp: qserdes-com-v3: add missing registers
  phy: qcom-qmp: qserdes-com: add missing registers
  ...
parents e0e1824b 08680588

Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Amlogic G12A MIPI analog PHY



maintainers:

  - Neil Armstrong <narmstrong@baylibre.com>



properties:

  compatible:

    const: amlogic,g12a-mipi-dphy-analog



  "#phy-cells":

    const: 0



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    phy@0 {

          compatible = "amlogic,g12a-mipi-dphy-analog";

          reg = <0x0 0xc>;

          #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/cdns,dphy.yaml

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@@ -11,8 +11,9 @@ maintainers: 


properties:

  compatible:

    items:

      - const: cdns,dphy

    enum:

      - cdns,dphy

      - ti,j721e-dphy



  reg:

    maxItems: 1

Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mixel LVDS PHY for Freescale i.MX8qm SoC



maintainers:

  - Liu Ying <victor.liu@nxp.com>



description: |

  The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.

  It converts two groups of four 7/10 bits of CMOS data into two

  groups of four data lanes of LVDS data streams. A phase-locked

  transmit clock is transmitted in parallel with each group of

  data streams over a fifth LVDS link. Every cycle of the transmit

  clock, 56/80 bits of input data are sampled and transmitted

  through the two groups of LVDS data streams. Together with the

  transmit clocks, the two groups of LVDS data streams form two

  LVDS channels.



  The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled

  by Control and Status Registers(CSR) module in the SoC. The CSR

  module, as a system controller, contains the PHY's registers.



properties:

  compatible:

    enum:

      - fsl,imx8qm-lvds-phy

      - mixel,28fdsoi-lvds-1250-8ch-tx-pll



  "#phy-cells":

    const: 1

    description: |

      Cell allows setting the LVDS channel index of the PHY.

      Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.



  clocks:

    maxItems: 1



  power-domains:

    maxItems: 1



required:

  - compatible

  - "#phy-cells"

  - clocks

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/firmware/imx/rsrc.h>

    phy {

        compatible = "fsl,imx8qm-lvds-phy";

        #phy-cells = <1>;

        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;

        power-domains = <&pd IMX_SC_R_LVDS_0>;

    };

Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml

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@@ -24,6 +24,10 @@ properties: 
          - enum:

              - mediatek,mt7623-mipi-tx

          - const: mediatek,mt2701-mipi-tx

      - items:

          - enum:

              - mediatek,mt8365-mipi-tx

          - const: mediatek,mt8183-mipi-tx

      - const: mediatek,mt2701-mipi-tx

      - const: mediatek,mt8173-mipi-tx

      - const: mediatek,mt8183-mipi-tx

Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek PCIe PHY



maintainers:

  - Jianjun Wang <jianjun.wang@mediatek.com>



description: |

  The PCIe PHY supports physical layer functionality for PCIe Gen3 port.



properties:

  compatible:

    const: mediatek,mt8195-pcie-phy



  reg:

    maxItems: 1



  reg-names:

    items:

      - const: sif



  "#phy-cells":

    const: 0



  nvmem-cells:

    maxItems: 7

    description:

      Phandles to nvmem cell that contains the efuse data, if unspecified,

      default value is used.



  nvmem-cell-names:

    items:

      - const: glb_intr

      - const: tx_ln0_pmos

      - const: tx_ln0_nmos

      - const: rx_ln0

      - const: tx_ln1_pmos

      - const: tx_ln1_nmos

      - const: rx_ln1



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    phy@11e80000 {

        compatible = "mediatek,mt8195-pcie-phy";

        #phy-cells = <0>;

        reg = <0x11e80000 0x10000>;

        reg-names = "sif";

        nvmem-cells = <&pciephy_glb_intr>,

                      <&pciephy_tx_ln0_pmos>,

                      <&pciephy_tx_ln0_nmos>,

                      <&pciephy_rx_ln0>,

                      <&pciephy_tx_ln1_pmos>,

                      <&pciephy_tx_ln1_nmos>,

                      <&pciephy_rx_ln1>;

        nvmem-cell-names = "glb_intr", "tx_ln0_pmos",

                           "tx_ln0_nmos", "rx_ln0",

                           "tx_ln1_pmos", "tx_ln1_nmos",

                           "rx_ln1";

        power-domains = <&spm 2>;

    };