Commit fe1939bb authored by Radha Mohan Chintakuntla's avatar Radha Mohan Chintakuntla Committed by David S. Miller
Browse files

octeontx2-af: Add SDP interface support 



Added support for packet IO via SDK links which is used when
Octeon is connected as a end-point. Traffic host to end-point
and vice versa flow through SDP links. This patch also support
dual SDP blocks supported in 98xx silicon.

Signed-off-by: default avatarRadha Mohan Chintakuntla <radhac@marvell.com>
Signed-off-by: default avatarNalla Pradeep <pnalla@marvell.com>
Signed-off-by: default avatarSubrahmanyam Nilla <snilla@marvell.com>
Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent aefaa8c7

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -10,4 +10,5 @@ obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o 
rvu_mbox-y := mbox.o rvu_trace.o

rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o
 
		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \

		  rvu_sdp.o

drivers/net/ethernet/marvell/octeontx2/af/common.h

+4 −1
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ enum nix_scheduler { 


#define NIX_INTF_TYPE_CGX		0

#define NIX_INTF_TYPE_LBK		1

#define NIX_INTF_TYPE_SDP		2



#define MAX_LMAC_PKIND			12

#define NIX_LINK_CGX_LMAC(a, b)		(0 + 4 * (a) + (b))
@@ -192,6 +193,8 @@ enum nix_scheduler { 
#define NIX_CHAN_CGX_LMAC_CHX(a, b, c)	(0x800 + 0x100 * (a) + 0x10 * (b) + (c))

#define NIX_CHAN_LBK_CHX(a, b)		(0 + 0x100 * (a) + (b))

#define NIX_CHAN_SDP_CH_START          (0x700ull)

#define NIX_CHAN_SDP_CHX(a)            (NIX_CHAN_SDP_CH_START + (a))

#define NIX_CHAN_SDP_NUM_CHANS		256



/* The mask is to extract lower 10-bits of channel number

 * which CPT will pass to X2P.

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+24 −0
Original line number Diff line number Diff line
@@ -191,6 +191,9 @@ M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 
M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)	\

M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \

			       msg_rsp)                                 \

/* SDP mbox IDs (range 0x1000 - 0x11FF) */				\

M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \

M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \

/* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\

M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\

				npc_mcam_alloc_entry_rsp)		\
@@ -1446,6 +1449,27 @@ struct cpt_rxc_time_cfg_req { 
	u16 active_limit;

};



struct sdp_node_info {

	/* Node to which this PF belons to */

	u8 node_id;

	u8 max_vfs;

	u8 num_pf_rings;

	u8 pf_srn;

#define SDP_MAX_VFS	128

	u8 vf_rings[SDP_MAX_VFS];

};



struct sdp_chan_info_msg {

	struct mbox_msghdr hdr;

	struct sdp_node_info info;

};



struct sdp_get_chan_info_msg {

	struct mbox_msghdr hdr;

	u16 chan_base;

	u16 num_chan;

};



/* CGX mailbox error codes

 * Range 1101 - 1200.

 */

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

+12 −1
Original line number Diff line number Diff line
@@ -1118,6 +1118,12 @@ static int rvu_setup_hw_resources(struct rvu *rvu) 
		goto nix_err;

	}



	err = rvu_sdp_init(rvu);

	if (err) {

		dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);

		goto nix_err;

	}



	rvu_program_channels(rvu);



	return 0;
@@ -1370,9 +1376,10 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 
	int blkaddr = BLKADDR_NIX0, vf;

	struct rvu_pfvf *pf;



	pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);



	/* All CGX mapped PFs are set with assigned NIX block during init */

	if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {

		pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);

		blkaddr = pf->nix_blkaddr;

	} else if (is_afvf(pcifunc)) {

		vf = pcifunc - 1;
@@ -1385,6 +1392,10 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 
			blkaddr = BLKADDR_NIX0;

	}



	/* if SDP1 then the blkaddr is NIX1 */

	if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)

		blkaddr = BLKADDR_NIX1;



	switch (blkaddr) {

	case BLKADDR_NIX1:

		pfvf->nix_blkaddr = BLKADDR_NIX1;

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

+19 −1
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@ struct rvu_pfvf { 
	u8	lbkid;	     /* NIX0/1 lbk link ID */

	u64     lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/

	unsigned long flags;

	struct  sdp_node_info *sdp_info;

};



enum rvu_pfvf_flags {
@@ -597,6 +598,16 @@ static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 
	return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;

}



static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)

{

	struct rvu_hwinfo *hw = rvu->hw;



	if (!hw->cap.programmable_chans)

		return NIX_CHAN_SDP_CHX(chan);



	return hw->sdp_chan_base + chan;

}



static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)

{

	return rvu->hw->cpt_chan_base + chan;
@@ -659,10 +670,17 @@ int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 
		 int qsize, int inst_size, int res_size);

void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);



/* SDP APIs */

int rvu_sdp_init(struct rvu *rvu);

bool is_sdp_pfvf(u16 pcifunc);

bool is_sdp_pf(u16 pcifunc);

bool is_sdp_vf(u16 pcifunc);



/* CGX APIs */

static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)

{

	return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);

	return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&

		!is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);

}



static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)