Commit fdd056ff authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Use DBI accessors 

Convert the remaining cases of register accesses using dbi_base rather
than dw_pcie_(read|write)[bwl]_dbi accessors.

Link: https://lore.kernel.org/r/20200821035420.380495-41-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org
parent aeaa0bfe

drivers/pci/controller/dwc/pcie-spear13xx.c

+4 −4
Original line number Diff line number Diff line
@@ -86,12 +86,12 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) 
	 * default value in capability register is 512 bytes. So force

	 * it to 128 here.

	 */

	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);

	val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL);

	val &= ~PCI_EXP_DEVCTL_READRQ;

	dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);

	dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val);



	dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);

	dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);

	dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A);

	dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80);



	/* enable ltssm */

	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)

drivers/pci/controller/dwc/pcie-tegra194.c

+4 −6
Original line number Diff line number Diff line
@@ -816,26 +816,24 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) 


	/* Program init preset */

	for (i = 0; i < pcie->num_lanes; i++) {

		dw_pcie_read(pci->dbi_base + CAP_SPCIE_CAP_OFF

				 + (i * 2), 2, &val);

		val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));

		val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;

		val |= GEN3_GEN4_EQ_PRESET_INIT;

		val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;

		val |= (GEN3_GEN4_EQ_PRESET_INIT <<

			   CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);

		dw_pcie_write(pci->dbi_base + CAP_SPCIE_CAP_OFF

				 + (i * 2), 2, val);

		dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);



		offset = dw_pcie_find_ext_capability(pci,

						     PCI_EXT_CAP_ID_PL_16GT) +

				PCI_PL_16GT_LE_CTRL;

		dw_pcie_read(pci->dbi_base + offset + i, 1, &val);

		val = dw_pcie_readb_dbi(pci, offset + i);

		val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;

		val |= GEN3_GEN4_EQ_PRESET_INIT;

		val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;

		val |= (GEN3_GEN4_EQ_PRESET_INIT <<

			PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);

		dw_pcie_write(pci->dbi_base + offset + i, 1, val);

		dw_pcie_writeb_dbi(pci, offset + i, val);

	}



	val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);