Commit fdcccbd8 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Warren
Browse files

clk: tegra: Workaround for Tegra114 MSENC problem 



Workaround a hardware bug in MSENC during clock enable.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent a26a0298

drivers/clk/tegra/clk-periph-gate.c

+9 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock); 


#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))



#define LVL2_CLK_GATE_OVRE 0x554



/* Peripheral gate clock ops */

static int clk_periph_is_enabled(struct clk_hw *hw)

{
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw) 
		}

	}



	if (gate->flags & TEGRA_PERIPH_WAR_1005168) {

		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);

		writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);

		udelay(1);

		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);

	}



	spin_unlock_irqrestore(&periph_ref_lock, flags);



	return 0;

drivers/clk/tegra/clk.h

+2 −0
Original line number Diff line number Diff line
@@ -358,6 +358,7 @@ struct tegra_clk_periph_regs { 
 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the

 *     bus to flush the write operation in apb bus. This flag indicates

 *     that this peripheral is in apb bus.

 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug

 */

struct tegra_clk_periph_gate {

	u32			magic;
@@ -377,6 +378,7 @@ struct tegra_clk_periph_gate { 
#define TEGRA_PERIPH_NO_RESET BIT(0)

#define TEGRA_PERIPH_MANUAL_RESET BIT(1)

#define TEGRA_PERIPH_ON_APB BIT(2)

#define TEGRA_PERIPH_WAR_1005168 BIT(3)



void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);

extern const struct clk_ops tegra_clk_periph_gate_ops;