Commit fdbec9ff authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files
parent b409db08
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+1 −2
Original line number Diff line number Diff line
@@ -1302,8 +1302,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
#define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)

/* ilk does support rc6, but we do not implement [power] contexts */
#define HAS_RC6(dev_priv)		 (GRAPHICS_VER(dev_priv) >= 6)
#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */

+8 −0
Original line number Diff line number Diff line
@@ -376,6 +376,8 @@ static const struct intel_device_info gm45_info = {
	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
	.has_snoop = true, \
	.has_coherent_ggtt = true, \
	/* ilk does support rc6, but we do not implement [power] contexts */ \
	.has_rc6 = 0, \
	.dma_mask_size = 36, \
	I9XX_PIPE_OFFSETS, \
	I9XX_CURSOR_OFFSETS, \
@@ -405,6 +407,7 @@ static const struct intel_device_info ilk_m_info = {
	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
	.has_coherent_ggtt = true, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_rps = true, \
	.dma_mask_size = 40, \
@@ -455,6 +458,7 @@ static const struct intel_device_info snb_m_gt2_info = {
	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
	.has_coherent_ggtt = true, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_reset_engine = true, \
	.has_rps = true, \
@@ -514,6 +518,7 @@ static const struct intel_device_info vlv_info = {
	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
	.has_runtime_pm = 1,
	.has_rc6 = 1,
	.has_reset_engine = true,
	.has_rps = true,
	.display.has_gmch = 1,
@@ -612,6 +617,7 @@ static const struct intel_device_info chv_info = {
	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
	.has_64bit_reloc = 1,
	.has_runtime_pm = 1,
	.has_rc6 = 1,
	.has_rps = true,
	.has_logical_ring_contexts = 1,
	.display.has_gmch = 1,
@@ -694,6 +700,7 @@ static const struct intel_device_info skl_gt4_info = {
	.display.has_psr_hw_tracking = 1, \
	.has_runtime_pm = 1, \
	.display.has_dmc = 1, \
	.has_rc6 = 1, \
	.has_rps = true, \
	.display.has_dp_mst = 1, \
	.has_logical_ring_contexts = 1, \
@@ -1003,6 +1010,7 @@ static const struct intel_device_info adl_p_info = {
	.has_logical_ring_contexts = 1, \
	.has_logical_ring_elsq = 1, \
	.has_mslices = 1, \
	.has_rc6 = 1, \
	.has_reset_engine = 1, \
	.has_rps = 1, \
	.has_runtime_pm = 1, \
+1 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ enum intel_ppgtt_type {
	func(has_mslices); \
	func(has_pooled_eu); \
	func(has_pxp); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_rps); \
	func(has_runtime_pm); \