Commit fda29dba authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Greg Kroah-Hartman
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iio: adc: meson-saradc: fix the clock frequency on Meson8 and Meson8b 



GX SoCs use a 1.2 MHz ADC clock, while the older SoCs use a 1.14 MHz
clock.

A comment in the driver from Amlogic's GPL kernel says that it's
running at 1.28 MHz. However, it's actually programming a divider of
20 + 1. With a XTAL clock of 24 MHz this results in a frequency of
1.14 MHz. (their calculation might be based on a 27 MHz XTAL clock,
but this is not what we have on the Meson8 and Meson8b SoCs).

The ADC was still working with the 1.2MHz clock. In my own tests I did
not see a difference between 1.2 and 1.14 MHz (regardless of the clock
frequency used, the ADC results were identical).

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b9a35893

drivers/iio/adc/meson_saradc.c

+7 −1
Original line number Diff line number Diff line
@@ -221,6 +221,7 @@ enum meson_sar_adc_chan7_mux_sel { 


struct meson_sar_adc_data {

	bool					has_bl30_integration;

	unsigned long				clock_rate;

	u32					bandgap_reg;

	unsigned int				resolution;

	const char				*name;
@@ -683,7 +684,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) 
		return ret;

	}



	ret = clk_set_rate(priv->adc_clk, 1200000);

	ret = clk_set_rate(priv->adc_clk, priv->data->clock_rate);

	if (ret) {

		dev_err(indio_dev->dev.parent,

			"failed to set adc clock rate\n");
@@ -856,6 +857,7 @@ static const struct iio_info meson_sar_adc_iio_info = { 


static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {

	.has_bl30_integration = false,

	.clock_rate = 1150000,

	.bandgap_reg = MESON_SAR_ADC_DELTA_10,

	.regmap_config = &meson_sar_adc_regmap_config_meson8,

	.resolution = 10,
@@ -864,6 +866,7 @@ static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { 


static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {

	.has_bl30_integration = false,

	.clock_rate = 1150000,

	.bandgap_reg = MESON_SAR_ADC_DELTA_10,

	.regmap_config = &meson_sar_adc_regmap_config_meson8,

	.resolution = 10,
@@ -872,6 +875,7 @@ static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { 


static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {

	.has_bl30_integration = true,

	.clock_rate = 1200000,

	.bandgap_reg = MESON_SAR_ADC_REG11,

	.regmap_config = &meson_sar_adc_regmap_config_gxbb,

	.resolution = 10,
@@ -880,6 +884,7 @@ static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { 


static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {

	.has_bl30_integration = true,

	.clock_rate = 1200000,

	.bandgap_reg = MESON_SAR_ADC_REG11,

	.regmap_config = &meson_sar_adc_regmap_config_gxbb,

	.resolution = 12,
@@ -888,6 +893,7 @@ static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { 


static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {

	.has_bl30_integration = true,

	.clock_rate = 1200000,

	.bandgap_reg = MESON_SAR_ADC_REG11,

	.regmap_config = &meson_sar_adc_regmap_config_gxbb,

	.resolution = 12,