Commit fd8c0b5a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-starfive-for-6.6' of... 

Merge tag 'clk-starfive-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into clk-starfive

Pull StarFive clk driver updates from Conor Dooley:

Add support for the System-Top-Group, Image-Signal-Process, Video-Output
and PLL clocks on the JH7110 SoC. These drivers come with their
associate dt-bindings & the obligatory headers containing defines of
clock indices.

To maintain backwards compatibility, the PLL driver will fall back to
using the fixed factor clocks that were merged for v6.4. The binding has
been updated to only permit sourcing the PLL clocks from the PLL's clock
controller.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'clk-starfive-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  clk: starfive: Add StarFive JH7110 Video-Output clock driver
  clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
  clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
  clk: starfive: jh7110-sys: Add PLL clocks source from DTS
  clk: starfive: Add StarFive JH7110 PLL clock driver
  dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
  dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
  dt-bindings: soc: starfive: Add StarFive syscon module
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator
parents 06c2afb8 dae5448a

Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-ispcrg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: ISP Top core

      - description: ISP Top Axi

      - description: NOC ISP Bus

      - description: external DVP



  clock-names:

    items:

      - const: isp_top_core

      - const: isp_top_axi

      - const: noc_bus_isp_axi

      - const: dvp_clk



  resets:

    items:

      - description: ISP Top core

      - description: ISP Top Axi

      - description: NOC ISP Bus



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



  power-domains:

    maxItems: 1

    description:

      ISP domain power



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - '#clock-cells'

  - '#reset-cells'

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>

    #include <dt-bindings/power/starfive,jh7110-pmu.h>

    #include <dt-bindings/reset/starfive,jh7110-crg.h>



    ispcrg: clock-controller@19810000 {

        compatible = "starfive,jh7110-ispcrg";

        reg = <0x19810000 0x10000>;

        clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,

                 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,

                 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,

                 <&dvp_clk>;

        clock-names = "isp_top_core", "isp_top_axi",

                      "noc_bus_isp_axi", "dvp_clk";

        resets = <&syscrg JH7110_SYSRST_ISP_TOP>,

                 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,

                 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        power-domains = <&pwrc JH7110_PD_ISP>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 PLL Clock Generator



description:

  These PLLs are high speed, low jitter frequency synthesizers in the JH7110.

  Each PLL works in integer mode or fraction mode, with configuration

  registers in the sys syscon. So the PLLs node should be a child of

  SYS-SYSCON node.

  The formula for calculating frequency is

  Fvco = Fref * (NI + NF) / M / Q1



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-pll



  clocks:

    maxItems: 1

    description: Main Oscillator (24 MHz)



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller {

      compatible = "starfive,jh7110-pll";

      clocks = <&osc>;

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 System-Top-Group Clock and Reset Generator



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-stgcrg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Main Oscillator (24 MHz)

      - description: HIFI4 core

      - description: STG AXI/AHB

      - description: USB (125 MHz)

      - description: CPU Bus

      - description: HIFI4 Axi

      - description: NOC STG Bus

      - description: APB Bus



  clock-names:

    items:

      - const: osc

      - const: hifi4_core

      - const: stg_axiahb

      - const: usb_125m

      - const: cpu_bus

      - const: hifi4_axi

      - const: nocstg_bus

      - const: apb_bus



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>



    stgcrg: clock-controller@10230000 {

        compatible = "starfive,jh7110-stgcrg";

        reg = <0x10230000 0x10000>;

        clocks = <&osc>,

                 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,

                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,

                 <&syscrg JH7110_SYSCLK_USB_125M>,

                 <&syscrg JH7110_SYSCLK_CPU_BUS>,

                 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,

                 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,

                 <&syscrg JH7110_SYSCLK_APB_BUS>;

        clock-names = "osc", "hifi4_core",

                      "stg_axiahb", "usb_125m",

                      "cpu_bus", "hifi4_axi",

                      "nocstg_bus", "apb_bus";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

+16 −2
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ properties: 
          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock

          - description: PLL0

          - description: PLL1

          - description: PLL2



      - items:

          - description: Main Oscillator (24 MHz)
@@ -38,6 +41,9 @@ properties: 
          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock

          - description: PLL0

          - description: PLL1

          - description: PLL2



  clock-names:

    oneOf:
@@ -52,6 +58,9 @@ properties: 
          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext

          - const: pll0_out

          - const: pll1_out

          - const: pll2_out



      - items:

          - const: osc
@@ -63,6 +72,9 @@ properties: 
          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext

          - const: pll0_out

          - const: pll1_out

          - const: pll2_out



  '#clock-cells':

    const: 1
@@ -93,12 +105,14 @@ examples: 
                 <&gmac1_rgmii_rxin>,

                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

                 <&tdm_ext>, <&mclk_ext>;

                 <&tdm_ext>, <&mclk_ext>,

                 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;

        clock-names = "osc", "gmac1_rmii_refin",

                      "gmac1_rgmii_rxin",

                      "i2stx_bclk_ext", "i2stx_lrck_ext",

                      "i2srx_bclk_ext", "i2srx_lrck_ext",

                      "tdm_ext", "mclk_ext";

                      "tdm_ext", "mclk_ext",

                      "pll0_out", "pll1_out", "pll2_out";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Video-Output Clock and Reset Generator



maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-voutcrg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Vout Top core

      - description: Vout Top Ahb

      - description: Vout Top Axi

      - description: Vout Top HDMI MCLK

      - description: I2STX0 BCLK

      - description: external HDMI pixel



  clock-names:

    items:

      - const: vout_src

      - const: vout_top_ahb

      - const: vout_top_axi

      - const: vout_top_hdmitx0_mclk

      - const: i2stx0_bclk

      - const: hdmitx0_pixelclk



  resets:

    maxItems: 1

    description: Vout Top core



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



  power-domains:

    maxItems: 1

    description:

      Vout domain power



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - '#clock-cells'

  - '#reset-cells'

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>

    #include <dt-bindings/power/starfive,jh7110-pmu.h>

    #include <dt-bindings/reset/starfive,jh7110-crg.h>



    voutcrg: clock-controller@295C0000 {

        compatible = "starfive,jh7110-voutcrg";

        reg = <0x295C0000 0x10000>;

        clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,

                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,

                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,

                 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,

                 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,

                 <&hdmitx0_pixelclk>;

        clock-names = "vout_src", "vout_top_ahb",

                      "vout_top_axi", "vout_top_hdmitx0_mclk",

                      "i2stx0_bclk", "hdmitx0_pixelclk";

        resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        power-domains = <&pwrc JH7110_PD_VOUT>;

    };