Commit fd8a5b27 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/bios: fill in DSC rc_model_size from VBT 



The VBT fields match the DPCD data, so use the same helper.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/43fba75d89525413aed0bdbb082c26b09458bd46.1607429866.git.jani.nikula@intel.com
parent a8f65ba3

drivers/gpu/drm/i915/display/intel_bios.c

+3 −8
Original line number Diff line number Diff line
@@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, 
			      crtc_state->dsc.slice_count);



	/*

	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the

	 * implementation specific physical rate buffer size. Currently we use

	 * the required rate buffer model size calculated in

	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.

	 *

	 * The VBT rc_buffer_block_size and rc_buffer_size definitions

	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC

	 * implementation should also use the DPCD (or perhaps VBT for eDP)

	 * provided value for the buffer size.

	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.

	 */

	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,

							    dsc->rc_buffer_size);



	/* FIXME: DSI spec says bpc + 1 for this one */

	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);