Commit fd79882f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v6.1-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull pci fixes from Bjorn Helgaas:

 - Revert a simplification that broke pci-tegra due to a masking error

 - Update MAINTAINERS for Kishon's email address change and TI
   DRA7XX/J721E maintainer change

* tag 'pci-v6.1-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  MAINTAINERS: Update Kishon's email address in PCI endpoint subsystem
  MAINTAINERS: Add Vignesh Raghavendra as maintainer of TI DRA7XX/J721E PCI driver
  Revert "PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro"
parents 3272eb1a e6aa4edd

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -15849,7 +15849,7 @@ F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml 
F:	drivers/pci/controller/dwc/*designware*









PCI DRIVER FOR TI DRA7XX/J721E









M:	Kishon Vijay Abraham I <kishon@ti.com>









M:	Vignesh Raghavendra <vigneshr@ti.com>









L:	linux-omap@vger.kernel.org









L:	linux-pci@vger.kernel.org









L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)








@@ -15866,10 +15866,10 @@ F:	Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt







F:	drivers/pci/controller/pci-v3-semi.c

















PCI ENDPOINT SUBSYSTEM









M:	Kishon Vijay Abraham I <kishon@ti.com>









M:	Lorenzo Pieralisi <lpieralisi@kernel.org>









R:	Krzysztof Wilczyński <kw@linux.com>









R:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>









R:	Kishon Vijay Abraham I <kishon@kernel.org>









L:	linux-pci@vger.kernel.org









S:	Supported









Q:	https://patchwork.kernel.org/project/linux-pci/list/
































drivers/pci/controller/pci-tegra.c



+8
−3






























Original line number
Diff line number
Diff line







@@ -415,6 +415,13 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)







 * address (access to which generates correct config transaction) falls in









 * this 4 KiB region.









 */









static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,









					   unsigned int where)









{









	return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |









	       (PCI_FUNC(devfn) << 8) | (where & 0xff);









}



















static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,









					unsigned int devfn,









					int where)








@@ -436,9 +443,7 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,







		unsigned int offset;









		u32 base;



















		offset = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),









					       PCI_FUNC(devfn), where) &









			 ~PCI_CONF1_ENABLE;









		offset = tegra_pcie_conf_offset(bus->number, devfn, where);



















		/* move 4 KiB window to offset within the FPCI region */









		base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);