Commit fd5ac974 authored by Fabrice Gasnier's avatar Fabrice Gasnier Committed by William Breathitt Gray
Browse files

counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update 



The ARR (auto reload register) and CMP (compare) registers are
successively written. The status bits to check the update of these
registers are polled together with regmap_read_poll_timeout().
The condition to end the loop may become true, even if one of the register
isn't correctly updated.
So ensure both status bits are set before clearing them.

Fixes: d8958824 ("iio: counter: Add support for STM32 LPTimer")
Signed-off-by: default avatarFabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/


Signed-off-by: default avatarWilliam Breathitt Gray <william.gray@linaro.org>
parent 30a0b95b

drivers/counter/stm32-lptimer-cnt.c

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv, 


	/* ensure CMP & ARR registers are properly written */

	ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,

				       (val & STM32_LPTIM_CMPOK_ARROK),

				       (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,

				       100, 1000);

	if (ret)

		return ret;