Commit fd5abfad authored by Youling Tang's avatar Youling Tang Committed by Hongchen Zhang
Browse files

LoongArch: Use la.pcrel instead of la.abs when it's trivially possible 

LoongArch inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I736HO



--------------------------------

Let's start to kill la.abs in preparation for the subsequent support of
the PIE kernel.

BTW, Re-tab the indention in arch/loongarch/kernel/entry.S for alignment.

Signed-off-by: default avatarXi Ruoyao <xry111@xry111.site>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
Signed-off-by: default avatarYouling Tang <tangyouling@loongson.cn>
Change-Id: Ia36815100690c2272528843870fa626221a5640f
parent 05a63c8b

arch/loongarch/include/asm/stackframe.h

+1 −1
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ 
	.endm



	.macro	set_saved_sp stackp temp temp2

	la.abs	  \temp, kernelsp

	la.pcrel  \temp, kernelsp

#ifdef CONFIG_SMP

	LONG_ADD  \temp, \temp, u0

#endif

arch/loongarch/include/asm/uaccess.h

+0 −1
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
extern u64 __ua_limit;



#define __UA_ADDR	".dword"

#define __UA_LA		"la.abs"

#define __UA_LIMIT	__ua_limit



/*

arch/loongarch/kernel/head.S

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ SYM_CODE_START(smpboot_entry) 
	li.w		t0, 0x00		# FPE=0, SXE=0, ASXE=0, BTE=0

	csrwr		t0, LOONGARCH_CSR_EUEN



	la.abs		t0, cpuboot_data

	la.pcrel	t0, cpuboot_data

	ld.d		sp, t0, CPU_BOOT_STACK

	ld.d		tp, t0, CPU_BOOT_TINFO

arch/loongarch/mm/tlbex.S

+1 −2
Original line number Diff line number Diff line
@@ -17,8 +17,7 @@ 
	move	a0, sp

	REG_S	a2, sp, PT_BVADDR

	li.w	a1, \write

	la.abs	t0, do_page_fault

	jirl	ra, t0, 0

	bl	do_page_fault

	RESTORE_ALL_AND_RET

	SYM_FUNC_END(tlb_do_page_fault_\write)

	.endm