Commit fd5803e5 authored by Ramalingam C's avatar Ramalingam C
Browse files

drm/i915/gt: use engine instance directly for offset 



To make it uniform across copy and clear, use the engine offset directly
to calculate the offset in the cmd forming for emit_clear.

Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarThomas Hellstrom <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220405150840.29351-2-ramalingam.c@intel.com
parent c16c8bfa

drivers/gpu/drm/i915/gt/intel_migrate.c

+4 −7
Original line number Diff line number Diff line
@@ -613,15 +613,13 @@ intel_context_migrate_copy(struct intel_context *ce, 
	return err;

}



static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value)

static int emit_clear(struct i915_request *rq, u32 offset, int size, u32 value)

{

	const int ver = GRAPHICS_VER(rq->engine->i915);

	u32 *cs;



	GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);



	offset += (u64)rq->engine->instance << 32;



	cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6);

	if (IS_ERR(cs))

		return PTR_ERR(cs);
@@ -631,17 +629,16 @@ static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value) 
		*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;

		*cs++ = 0;

		*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

		*cs++ = lower_32_bits(offset);

		*cs++ = upper_32_bits(offset);

		*cs++ = offset;

		*cs++ = rq->engine->instance;

		*cs++ = value;

		*cs++ = MI_NOOP;

	} else {

		GEM_BUG_ON(upper_32_bits(offset));

		*cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);

		*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;

		*cs++ = 0;

		*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

		*cs++ = lower_32_bits(offset);

		*cs++ = offset;

		*cs++ = value;

	}