Commit fd4d7904 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Matt Roper
Browse files

drm/i915: rework some irq functions to take intel_gt as argument 



We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.

In this commit we start passing intel_gt instead of dev_priv for the
functions that are related to Xe_HP irq handling. Right now we're still
passing tile 0 everywhere, but in later patches we'll start actually
passing the correct tile.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Co-authored-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211029032817.3747750-2-matthew.d.roper@intel.com
parent 9030e39c

drivers/gpu/drm/i915/i915_irq.c

+15 −11
Original line number Diff line number Diff line
@@ -2772,7 +2772,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) 
{

	struct drm_i915_private * const i915 = arg;

	struct intel_gt *gt = &i915->gt;

	void __iomem * const regs = i915->uncore.regs;

	void __iomem * const regs = gt->uncore->regs;

	u32 master_tile_ctl, master_ctl;

	u32 gu_misc_iir;
@@ -3173,11 +3173,12 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 


static void gen11_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_gt *gt = &dev_priv->gt;

	struct intel_uncore *uncore = gt->uncore;



	gen11_master_intr_disable(dev_priv->uncore.regs);



	gen11_gt_irq_reset(&dev_priv->gt);

	gen11_gt_irq_reset(gt);

	gen11_display_irq_reset(dev_priv);



	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3186,11 +3187,12 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv) 


static void dg1_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_gt *gt = &dev_priv->gt;

	struct intel_uncore *uncore = gt->uncore;



	dg1_master_intr_disable(dev_priv->uncore.regs);



	gen11_gt_irq_reset(&dev_priv->gt);

	gen11_gt_irq_reset(gt);

	gen11_display_irq_reset(dev_priv);



	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3869,13 +3871,14 @@ static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv) 


static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_gt *gt = &dev_priv->gt;

	struct intel_uncore *uncore = gt->uncore;

	u32 gu_misc_masked = GEN11_GU_MISC_GSE;



	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)

		icp_irq_postinstall(dev_priv);



	gen11_gt_irq_postinstall(&dev_priv->gt);

	gen11_gt_irq_postinstall(gt);

	gen11_de_irq_postinstall(dev_priv);



	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3886,10 +3889,11 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 


static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_gt *gt = &dev_priv->gt;

	struct intel_uncore *uncore = gt->uncore;

	u32 gu_misc_masked = GEN11_GU_MISC_GSE;



	gen11_gt_irq_postinstall(&dev_priv->gt);

	gen11_gt_irq_postinstall(gt);



	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3900,8 +3904,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) 
				   GEN11_DISPLAY_IRQ_ENABLE);

	}



	dg1_master_intr_enable(dev_priv->uncore.regs);

	intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);

	dg1_master_intr_enable(uncore->regs);

	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);

}



static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)