Commit fd2ed6db authored by Xi Pardee's avatar Xi Pardee Committed by Hans de Goede
Browse files

platform/x86: intel/pmc: Relocate Ice Lake PCH support 



Create icl.c for Ice Lake PCH specific structures and init().
This file supports Ice Lake, Ice Lake NNPI and Jasper Lake platforms.
There are no functional changes involved.

Cc: David E Box <david.e.box@linux.intel.com>
Reviewed-by: default avatar"David E. Box" <david.e.box@linux.intel.com>
Signed-off-by: default avatarXi Pardee <xi.pardee@intel.com>
Signed-off-by: default avatar"David E. Box" <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20221114183257.2067662-6-gayatri.kammela@linux.intel.com


Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent d6cd0cc8

drivers/platform/x86/intel/pmc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
# Intel x86 Platform-Specific Drivers

#



intel_pmc_core-y			:= core.o spt.o cnp.o

intel_pmc_core-y			:= core.o spt.o cnp.o icl.o

obj-$(CONFIG_INTEL_PMC_CORE)		+= intel_pmc_core.o

intel_pmc_core_pltdrv-y			:= pltdrv.o

obj-$(CONFIG_INTEL_PMC_CORE)		+= intel_pmc_core_pltdrv.o

drivers/platform/x86/intel/pmc/core.c

+0 −45
Original line number Diff line number Diff line
@@ -60,28 +60,6 @@ const struct pmc_bit_map msr_map[] = { 
	{}

};



static const struct pmc_bit_map icl_pfear_map[] = {

	{"RES_65",		BIT(0)},

	{"RES_66",		BIT(1)},

	{"RES_67",		BIT(2)},

	{"TAM",			BIT(3)},

	{"GBETSN",		BIT(4)},

	{"TBTLSX",		BIT(5)},

	{"RES_71",		BIT(6)},

	{"RES_72",		BIT(7)},

	{}

};



static const struct pmc_bit_map *ext_icl_pfear_map[] = {

	/*

	 * Check intel_pmc_core_ids[] users of icl_reg_map for

	 * a list of core SoCs using this.

	 */

	cnp_pfear_map,

	icl_pfear_map,

	NULL

};



static const struct pmc_bit_map tgl_pfear_map[] = {

	{"PSF9",		BIT(0)},

	{"RES_66",		BIT(1)},
@@ -103,24 +81,6 @@ static const struct pmc_bit_map *ext_tgl_pfear_map[] = { 
	NULL

};



static const struct pmc_reg_map icl_reg_map = {

	.pfear_sts = ext_icl_pfear_map,

	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,

	.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,

	.slps0_dbg_maps = cnp_slps0_dbg_maps,

	.ltr_show_sts = cnp_ltr_show_map,

	.msr_sts = msr_map,

	.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,

	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,

	.regmap_length = CNP_PMC_MMIO_REG_LEN,

	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,

	.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,

	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,

	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,

	.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,

	.etr3_offset = ETR3_OFFSET,

};



static const struct pmc_bit_map tgl_clocksource_status_map[] = {

	{"USB2PLL_OFF_STS",			BIT(18)},

	{"PCIe/USB3.1_Gen2PLL_OFF_STS",		BIT(19)},
@@ -1589,11 +1549,6 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) 
	}

}



void icl_core_init(struct pmc_dev *pmcdev)

{

	pmcdev->map = &icl_reg_map;

}



void tgl_core_configure(struct pmc_dev *pmcdev)

{

	pmc_core_get_tgl_lpm_reqs(pmcdev->pdev);

drivers/platform/x86/intel/pmc/core.h

+3 −0
Original line number Diff line number Diff line
@@ -351,6 +351,9 @@ extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; 
extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];

extern const struct pmc_bit_map cnp_ltr_show_map[];

extern const struct pmc_reg_map cnp_reg_map;

extern const struct pmc_bit_map icl_pfear_map[];

extern const struct pmc_bit_map *ext_icl_pfear_map[];

extern const struct pmc_reg_map icl_reg_map;



void spt_core_init(struct pmc_dev *pmcdev);

void cnp_core_init(struct pmc_dev *pmcdev);

drivers/platform/x86/intel/pmc/icl.c

0 → 100644
+56 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * This file contains platform specific structure definitions

 * and init function used by Ice Lake PCH.

 *

 * Copyright (c) 2022, Intel Corporation.

 * All Rights Reserved.

 *

 */



#include "core.h"



const struct pmc_bit_map icl_pfear_map[] = {

	{"RES_65",		BIT(0)},

	{"RES_66",		BIT(1)},

	{"RES_67",		BIT(2)},

	{"TAM",			BIT(3)},

	{"GBETSN",		BIT(4)},

	{"TBTLSX",		BIT(5)},

	{"RES_71",		BIT(6)},

	{"RES_72",		BIT(7)},

	{}

};



const struct pmc_bit_map *ext_icl_pfear_map[] = {

	/*

	 * Check intel_pmc_core_ids[] users of icl_reg_map for

	 * a list of core SoCs using this.

	 */

	cnp_pfear_map,

	icl_pfear_map,

	NULL

};



const struct pmc_reg_map icl_reg_map = {

	.pfear_sts = ext_icl_pfear_map,

	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,

	.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,

	.slps0_dbg_maps = cnp_slps0_dbg_maps,

	.ltr_show_sts = cnp_ltr_show_map,

	.msr_sts = msr_map,

	.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,

	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,

	.regmap_length = CNP_PMC_MMIO_REG_LEN,

	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,

	.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,

	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,

	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,

	.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,

	.etr3_offset = ETR3_OFFSET,

};



void icl_core_init(struct pmc_dev *pmcdev)

{

	pmcdev->map = &icl_reg_map;

}