Commit fcfe55f2 authored by Anusha Srivatsa's avatar Anusha Srivatsa
Browse files

drm/i915/display: Move squash_ctl register programming to its own function 



No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.

v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221025223042.138810-4-anusha.srivatsa@intel.com
parent 6688b6b1

drivers/gpu/drm/i915/display/intel_cdclk.c

+14 −9
Original line number Original line Diff line number Diff line
@@ -1704,6 +1704,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 
		bxt_de_pll_enable(i915, vco);

		bxt_de_pll_enable(i915, vco);

}

}





static void dg2_cdclk_squash_program(struct drm_i915_private *i915,

				     u16 waveform)

{

	u32 squash_ctl = 0;



	if (waveform)

		squash_ctl = CDCLK_SQUASH_ENABLE |

			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;



	intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);

}



static void bxt_set_cdclk(struct drm_i915_private *dev_priv,

static void bxt_set_cdclk(struct drm_i915_private *dev_priv,

			  const struct intel_cdclk_config *cdclk_config,

			  const struct intel_cdclk_config *cdclk_config,

			  enum pipe pipe)

			  enum pipe pipe)
@@ -1751,15 +1763,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	else

	else

		clock = cdclk;

		clock = cdclk;





	if (HAS_CDCLK_SQUASH(dev_priv)) {

	if (HAS_CDCLK_SQUASH(dev_priv))

		u32 squash_ctl = 0;

		dg2_cdclk_squash_program(dev_priv, waveform);



		if (waveform)

			squash_ctl = CDCLK_SQUASH_ENABLE |

				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;



		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);

	}





	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |

	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |

		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |

		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |