Commit fcecdcd3 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer
Browse files

MIPS: Loongson64: Load built-in dtbs 



Load proper dtb according to firmware passed parameters and
CPU PRID.

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 87fcfa7b

arch/mips/include/asm/mach-loongson64/builtin_dtbs.h

0 → 100644
+13 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Copyright (C) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>

 *

 * Built-in Generic dtbs for MACH_LOONGSON64

 */



#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_

#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_



extern u32 __dtb_loongson3_4core_rs780e_begin[];

extern u32 __dtb_loongson3_8core_rs780e_begin[];

#endif

arch/mips/include/asm/mach-loongson64/loongson.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops; 
/* loongson-specific command line, env and memory initialization */

extern void __init prom_init_memory(void);

extern void __init prom_init_env(void);

extern void *loongson_fdt_blob;



/* irq operation functions */

extern void mach_irq_dispatch(unsigned int pending);

arch/mips/loongson64/env.c

+23 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <asm/bootinfo.h>

#include <loongson.h>

#include <boot_param.h>

#include <builtin_dtbs.h>

#include <workarounds.h>



u32 cpu_clock_freq;
@@ -120,6 +121,28 @@ void __init prom_init_env(void) 
		loongson_sysconf.cores_per_node - 1) /

		loongson_sysconf.cores_per_node;



	if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {

		switch (read_c0_prid() & PRID_REV_MASK) {

		case PRID_REV_LOONGSON3A_R1:

		case PRID_REV_LOONGSON3A_R2_0:

		case PRID_REV_LOONGSON3A_R2_1:

		case PRID_REV_LOONGSON3A_R3_0:

		case PRID_REV_LOONGSON3A_R3_1:

			loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;

			break;

		case PRID_REV_LOONGSON3B_R1:

		case PRID_REV_LOONGSON3B_R2:

			loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;

			break;

		default:

			break;

		}

	}





	if (!loongson_fdt_blob)

		pr_err("Failed to determine built-in Loongson64 dtb\n");



	loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;

	loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;

	loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;

arch/mips/loongson64/setup.c

+16 −0
Original line number Diff line number Diff line
@@ -8,9 +8,15 @@ 


#include <asm/wbflush.h>

#include <asm/bootinfo.h>

#include <linux/libfdt.h>

#include <linux/of_fdt.h>



#include <asm/prom.h>



#include <loongson.h>



void *loongson_fdt_blob;



static void wbflush_loongson(void)

{

	asm(".set\tpush\n\t"
@@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush); 


void __init plat_mem_setup(void)

{

	if (loongson_fdt_blob)

		__dt_setup_arch(loongson_fdt_blob);

}



void __init device_tree_init(void)

{

	if (!initial_boot_params)

		return;



	unflatten_and_copy_device_tree();

}