Commit fcd3e58f authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add debug option for dramclk_change_latency in apu 



[Why & How]
Support dramclk change latency change via debug option and add some
code isolation.

Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 06484134

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

+5 −0
Original line number Diff line number Diff line
@@ -379,6 +379,11 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
	dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;



	if ((int)(dcn3_01_soc.dram_clock_change_latency_us * 1000)

				!= dc->debug.dram_clock_change_latency_ns

			&& dc->debug.dram_clock_change_latency_ns) {

		dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0;

	}

	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);

}

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+17 −0
Original line number Diff line number Diff line
@@ -667,6 +667,12 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
	dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;



	if ((int)(dcn3_1_soc.dram_clock_change_latency_us * 1000)

				!= dc->debug.dram_clock_change_latency_ns

			&& dc->debug.dram_clock_change_latency_ns) {

		dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

	}



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);

	else
@@ -721,6 +727,12 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
	 */

	dcn3_15_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;



	if ((int)(dcn3_15_soc.dram_clock_change_latency_us * 1000)

				!= dc->debug.dram_clock_change_latency_ns

			&& dc->debug.dram_clock_change_latency_ns) {

		dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

	}



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN31);

	else
@@ -813,6 +825,11 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
		dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

	}

	if ((int)(dcn3_16_soc.dram_clock_change_latency_us * 1000)

				!= dc->debug.dram_clock_change_latency_ns

			&& dc->debug.dram_clock_change_latency_ns) {

		dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

	}



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

+5 −0
Original line number Diff line number Diff line
@@ -264,6 +264,11 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p 
		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

	}



	if ((int)(dcn3_14_soc.dram_clock_change_latency_us * 1000)

				!= dc->debug.dram_clock_change_latency_ns

			&& dc->debug.dram_clock_change_latency_ns) {

		dcn3_14_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

	}

	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);

	else