Loading arch/mips/include/asm/traps.h +1 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); Loading arch/mips/kernel/traps.c +4 −1 Original line number Diff line number Diff line Loading @@ -91,7 +91,7 @@ void (*board_nmi_handler_setup)(void); void (*board_ejtag_handler_setup)(void); void (*board_bind_eic_interrupt)(int irq, int regset); void (*board_ebase_setup)(void); void __cpuinitdata(*board_cache_error_setup)(void); static void show_raw_backtrace(unsigned long reg29) { Loading Loading @@ -1797,6 +1797,9 @@ void __init trap_init(void) set_except_vector(26, handle_dsp); if (board_cache_error_setup) board_cache_error_setup(); if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); Loading Loading
arch/mips/include/asm/traps.h +1 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); Loading
arch/mips/kernel/traps.c +4 −1 Original line number Diff line number Diff line Loading @@ -91,7 +91,7 @@ void (*board_nmi_handler_setup)(void); void (*board_ejtag_handler_setup)(void); void (*board_bind_eic_interrupt)(int irq, int regset); void (*board_ebase_setup)(void); void __cpuinitdata(*board_cache_error_setup)(void); static void show_raw_backtrace(unsigned long reg29) { Loading Loading @@ -1797,6 +1797,9 @@ void __init trap_init(void) set_except_vector(26, handle_dsp); if (board_cache_error_setup) board_cache_error_setup(); if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); Loading