Commit fc5d1a92 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/fixes-for-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD fixes from Miquel Raynal:
 "Raw NAND controller driver fixes:

   - meson:
      - Invalidate cache on polling ECC bit
      - Initialize struct with zeroes

   - nandsim: Artificially prevent sequential page reads

  ECC engine driver fixes:

   - mxic-ecc: Fix mxic_ecc_data_xfer_wait_for_completion() when irq is
     used

  Binging fixes:

   - jedec,spi-nor: Document CPOL/CPHA support"

* tag 'mtd/fixes-for-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: rawnand: meson: invalidate cache on polling ECC bit
  mtd: rawnand: nandsim: Artificially prevent sequential page reads
  dt-bindings: mtd: jedec,spi-nor: Document CPOL/CPHA support
  mtd: nand: mxic-ecc: Fix mxic_ecc_data_xfer_wait_for_completion() when irq is used
  mtd: rawnand: meson: initialize struct with zeroes
parents 197b6b60 e732e39e

Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

+7 −0
Original line number Diff line number Diff line
@@ -76,6 +76,13 @@ properties: 
      If "broken-flash-reset" is present then having this property does not

      make any difference.



  spi-cpol: true

  spi-cpha: true



dependencies:

  spi-cpol: [ spi-cpha ]

  spi-cpha: [ spi-cpol ]



unevaluatedProperties: false



examples:

drivers/mtd/nand/ecc-mxic.c

+1 −0
Original line number Diff line number Diff line
@@ -429,6 +429,7 @@ static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *mxic) 
		mxic_ecc_enable_int(mxic);

		ret = wait_for_completion_timeout(&mxic->complete,

						  msecs_to_jiffies(1000));

		ret = ret ? 0 : -ETIMEDOUT;

		mxic_ecc_disable_int(mxic);

	} else {

		ret = readl_poll_timeout(mxic->regs + INTRPT_STS, val,

drivers/mtd/nand/raw/meson_nand.c

+8 −2
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ struct meson_nfc { 


	dma_addr_t daddr;

	dma_addr_t iaddr;

	u32 info_bytes;



	unsigned long assigned_cs;

};
@@ -503,6 +504,7 @@ static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf, 
					 nfc->daddr, datalen, dir);

			return ret;

		}

		nfc->info_bytes = infolen;

		cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);

		writel(cmd, nfc->reg_base + NFC_REG_CMD);
@@ -520,8 +522,10 @@ static void meson_nfc_dma_buffer_release(struct nand_chip *nand, 
	struct meson_nfc *nfc = nand_get_controller_data(nand);



	dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);

	if (infolen)

	if (infolen) {

		dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);

		nfc->info_bytes = 0;

	}

}



static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
@@ -710,6 +714,8 @@ static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc, 
		usleep_range(10, 15);

		/* info is updated by nfc dma engine*/

		smp_rmb();

		dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes,

					DMA_FROM_DEVICE);

		ret = *info & ECC_COMPLETE;

	} while (!ret);

}
@@ -991,7 +997,7 @@ static const struct mtd_ooblayout_ops meson_ooblayout_ops = { 


static int meson_nfc_clk_init(struct meson_nfc *nfc)

{

	struct clk_parent_data nfc_divider_parent_data[1];

	struct clk_parent_data nfc_divider_parent_data[1] = {0};

	struct clk_init_data init = {0};

	int ret;

drivers/mtd/nand/raw/nandsim.c

+16 −1
Original line number Diff line number Diff line
@@ -2160,8 +2160,23 @@ static int ns_exec_op(struct nand_chip *chip, const struct nand_operation *op, 
	const struct nand_op_instr *instr = NULL;

	struct nandsim *ns = nand_get_controller_data(chip);



	if (check_only)

	if (check_only) {

		/* The current implementation of nandsim needs to know the

		 * ongoing operation when performing the address cycles. This

		 * means it cannot make the difference between a regular read

		 * and a continuous read. Hence, this hack to manually refuse

		 * supporting sequential cached operations.

		 */

		for (op_id = 0; op_id < op->ninstrs; op_id++) {

			instr = &op->instrs[op_id];

			if (instr->type == NAND_OP_CMD_INSTR &&

			    (instr->ctx.cmd.opcode == NAND_CMD_READCACHEEND ||

			     instr->ctx.cmd.opcode == NAND_CMD_READCACHESEQ))

				return -EOPNOTSUPP;

		}



		return 0;

	}



	ns->lines.ce = 1;