Commit fc44ff0a authored Mar 01, 2022 by Ben Walker Committed by Vinod Koul Apr 20, 2022

dmaengine: Document dmaengine_prep_dma_memset

Document this function to make clear the expected behavior of the
'value' parameter. It was intended to match the behavior of POSIX memset
as laid out here:

https://lore.kernel.org/dmaengine/YejrA5ZWZ3lTRO%2F1@matsya/



Signed-off-by: Ben Walker <benjamin.walker@intel.com>
Link: https://lore.kernel.org/r/20220301182551.883474-2-benjamin.walker@intel.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

parent 439b5e76

Documentation/driver-api/dmaengine/provider.rst

+6 −0

Original line number	Diff line number	Diff line
		@@ -206,6 +206,12 @@ Currently, the types available are:
		- The device is able to perform parity check using RAID6 P+Q
		algorithm against a memory buffer.

		- DMA_MEMSET

		- The device is able to fill memory with the provided pattern

		- The pattern is treated as a single byte signed value.

		- DMA_INTERRUPT

		- The device is able to trigger a dummy transfer that will

include/linux/dmaengine.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -1030,6 +1030,14 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
		return chan->device->device_prep_interleaved_dma(chan, xt, flags);
		}

		/**
		* dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
		* @chan: The channel to be used for this descriptor
		* @dest: Address of buffer to be set
		* @value: Treated as a single byte value that fills the destination buffer
		* @len: The total size of dest
		* @flags: DMA engine flags
		*/
		static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags)