Commit fc3d39d5 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

dt-bindings: clock: ti: Add clock-output-names for TI composite clocks



For the TI composite clocks, we currently have only the divider clock
list clock-output-names as an optional devicetree property. Let's add
clock-output-names for all the TI composite clock bindings.

This allows us to use clock-output-names for the clockctrl instance name
instead of relying on a custom compatible or non-standard node names.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Message-Id: <20220203112337.19821-3-tony@atomide.com>
parent 8ab42308
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+3 −0
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain

Optional properties:
- clock-output-names : from common clock binding.

Examples:
	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
+3 −0
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ Required properties:
- clocks : link phandles of component clocks
- #clock-cells : from common clock binding; shall be set to 0.

Optional properties:
- clock-output-names : from common clock binding.

Examples:

usb_l4_gate_ick: usb_l4_gate_ick {
+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ Required properties:
- clocks: parent clock.

Optional properties:
- clock-output-names : from common clock binding.
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
  see [2]
- reg: offset for the autoidle register of this clock, see [2]
+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ Required properties:
	ti,clkdm-gate-clock type

Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for programming the clock gate, invalid for
		 ti,clkdm-gate-clock type
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ Required properties:
- reg : base address for the control register

Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)

Examples:
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