Loading arch/arm/mm/cache-l2x0.c +4 −2 Original line number Diff line number Diff line Loading @@ -710,8 +710,10 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, revision < L310_CACHE_ID_RTL_R3P2) { u32 val = l2x0_saved_regs.prefetch_ctrl; /* I don't think bit23 is required here... but iMX6 does so */ if (val & (BIT(30) | BIT(23))) { val &= ~(BIT(30) | BIT(23)); if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL | L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) { val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL | L310_PREFETCH_CTRL_DBL_LINEFILL_INCR); l2x0_saved_regs.prefetch_ctrl = val; errata[n++] = "752271"; } Loading Loading
arch/arm/mm/cache-l2x0.c +4 −2 Original line number Diff line number Diff line Loading @@ -710,8 +710,10 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, revision < L310_CACHE_ID_RTL_R3P2) { u32 val = l2x0_saved_regs.prefetch_ctrl; /* I don't think bit23 is required here... but iMX6 does so */ if (val & (BIT(30) | BIT(23))) { val &= ~(BIT(30) | BIT(23)); if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL | L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) { val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL | L310_PREFETCH_CTRL_DBL_LINEFILL_INCR); l2x0_saved_regs.prefetch_ctrl = val; errata[n++] = "752271"; } Loading