Commit fc098fb4 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: update nbio v7_4 ip header files 



Add mmBIF_INTR_CNTL and its shift mask.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b8d312aa

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h

+2 −2
Original line number Diff line number Diff line
@@ -2793,8 +2793,8 @@ 
#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX                                                               2

#define mmBIF_FB_EN                                                                                    0x00ff

#define mmBIF_FB_EN_BASE_IDX                                                                           2

#define mmBIF_BUSY_DELAY_CNTR                                                                          0x0100

#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX                                                                 2

#define mmBIF_INTR_CNTL                                                                                0x0100

#define mmBIF_INTR_CNTL_BASE_IDX                                                                       2

#define mmBIF_MST_TRANS_PENDING_VF                                                                     0x0109

#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX                                                            2

#define mmBIF_SLV_TRANS_PENDING_VF                                                                     0x010a

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

+3 −3
Original line number Diff line number Diff line
@@ -20420,9 +20420,9 @@ 
#define BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                         0x1

#define BIF_FB_EN__FB_READ_EN_MASK                                                                            0x00000001L

#define BIF_FB_EN__FB_WRITE_EN_MASK                                                                           0x00000002L

//BIF_BUSY_DELAY_CNTR

#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT                                                                 0x0

#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK                                                                   0x0000003FL

//BIF_INTR_CNTL

#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                                0x0

#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                                  0x00000001L

//BIF_MST_TRANS_PENDING_VF

#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                                0x0

#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                                  0x7FFFFFFFL