Commit fbff5606 authored by Joey Gouly's avatar Joey Gouly Committed by Catalin Marinas
Browse files

KVM: arm64: Save/restore TCR2_EL1 



Define the new system register TCR2_EL1 and context switch it.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230606145859.697944-9-joey.gouly@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent e43454c4

arch/arm64/include/asm/kvm_host.h

+1 −0
Original line number Diff line number Diff line
@@ -279,6 +279,7 @@ enum vcpu_sysreg { 
	TTBR0_EL1,	/* Translation Table Base Register 0 */

	TTBR1_EL1,	/* Translation Table Base Register 1 */

	TCR_EL1,	/* Translation Control Register */

	TCR2_EL1,	/* Extended Translation Control Register */

	ESR_EL1,	/* Exception Syndrome Register */

	AFSR0_EL1,	/* Auxiliary Fault Status Register 0 */

	AFSR1_EL1,	/* Auxiliary Fault Status Register 1 */

arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h

+4 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) 
	ctxt_sys_reg(ctxt, TTBR0_EL1)	= read_sysreg_el1(SYS_TTBR0);

	ctxt_sys_reg(ctxt, TTBR1_EL1)	= read_sysreg_el1(SYS_TTBR1);

	ctxt_sys_reg(ctxt, TCR_EL1)	= read_sysreg_el1(SYS_TCR);

	if (cpus_have_final_cap(ARM64_HAS_TCR2))

		ctxt_sys_reg(ctxt, TCR2_EL1)	= read_sysreg_el1(SYS_TCR2);

	ctxt_sys_reg(ctxt, ESR_EL1)	= read_sysreg_el1(SYS_ESR);

	ctxt_sys_reg(ctxt, AFSR0_EL1)	= read_sysreg_el1(SYS_AFSR0);

	ctxt_sys_reg(ctxt, AFSR1_EL1)	= read_sysreg_el1(SYS_AFSR1);
@@ -114,6 +116,8 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) 
	write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1),	SYS_CPACR);

	write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1),	SYS_TTBR0);

	write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1),	SYS_TTBR1);

	if (cpus_have_final_cap(ARM64_HAS_TCR2))

		write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1),	SYS_TCR2);

	write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1),	SYS_ESR);

	write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1),	SYS_AFSR0);

	write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1),	SYS_AFSR1);

arch/arm64/kvm/sys_regs.c

+1 −0
Original line number Diff line number Diff line
@@ -1893,6 +1893,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },

	{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },

	{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },

	{ SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },



	PTRAUTH_KEY(APIA),

	PTRAUTH_KEY(APIB),