Commit fbeda19f authored May 13, 2009 by David Daney Committed by Ralf Baechle Jun 17, 2009

MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.



Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 9cffd154

arch/mips/include/asm/cpu-features.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -234,4 +234,8 @@
		#define cpu_scache_line_size() cpu_data[0].scache.linesz
		#endif

		#ifndef cpu_hwrena_impl_bits
		#define cpu_hwrena_impl_bits 0
		#endif

		#endif /* __ASM_CPU_FEATURES_H */

arch/mips/kernel/traps.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1502,7 +1502,7 @@ void __cpuinit per_cpu_trap_init(void)
		status_set);

		if (cpu_has_mips_r2) {
		unsigned int enable = 0x0000000f;
		unsigned int enable = 0x0000000f \| cpu_hwrena_impl_bits;

		if (!noulri && cpu_has_userlocal)
		enable \|= (1 << 29);