Commit fba56184 authored by Rob Herring's avatar Rob Herring
Browse files

dt-bindings: Fix incorrect 'reg' property sizes 



The examples template is a 'simple-bus' with a size of 1 cell for
had between 2 and 4 cells which really only errors on I2C or SPI type
devices with a single cell.

The easiest fix in most cases is to change the 'reg' property to for 1 cell
address and size. In some cases with child devices having 2 cells, that
doesn't make sense so a bus node is needed.

Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 1195b303

Documentation/devicetree/bindings/arm/coresight-cti.yaml

+1 −1
Original line number Diff line number Diff line
@@ -295,7 +295,7 @@ examples: 
  - |

    cti@20110000 {

      compatible = "arm,coresight-cti", "arm,primecell";

      reg = <0 0x20110000 0 0x1000>;

      reg = <0x20110000 0x1000>;



      clocks = <&soc_smc50mhz>;

      clock-names = "apb_pclk";

Documentation/devicetree/bindings/arm/renesas,prr.yaml

+1 −1
Original line number Diff line number Diff line
@@ -33,5 +33,5 @@ examples: 
  - |

    prr: chipid@ff000044 {

        compatible = "renesas,prr";

        reg = <0 0xff000044 0 4>;

        reg = <0xff000044 4>;

    };

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml

+1 −1
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ examples: 


    tegra_pmc: pmc@7000e400 {

              compatible = "nvidia,tegra210-pmc";

              reg = <0x0 0x7000e400 0x0 0x400>;

              reg = <0x7000e400 0x400>;

              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;

              clock-names = "pclk", "clk32k_in";

              #clock-cells = <1>;

Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ examples: 
  - |

    uart0: serial@58018000 {

         compatible = "snps,dw-apb-uart";

         reg = <0x0 0x58018000 0x0 0x2000>;

         reg = <0x58018000 0x2000>;

         clocks = <&clk 45>, <&clk 46>;

         clock-names = "baudclk", "apb_pclk";

         interrupts = <0 9 4>;

Documentation/devicetree/bindings/clock/fsl,plldig.yaml

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ examples: 
  - |

    dpclk: clock-display@f1f0000 {

        compatible = "fsl,ls1028a-plldig";

        reg = <0x0 0xf1f0000 0x0 0xffff>;

        reg = <0xf1f0000 0xffff>;

        #clock-cells = <0>;

        clocks = <&osc_27m>;

    };