Commit fb980ef7 authored by Alex Elder's avatar Alex Elder Committed by David S. Miller
Browse files

net: ipa: share field mask values for GSI general interrupt 



The GSI general interrupt is managed by three registers: enable;
status; and clear.  The three registers have same set of field bits
at the same locations.  Use a common set of field masks for all
three registers to avoid duplication.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d61bb716

drivers/net/ipa/gsi.c

+1 −1
Original line number Diff line number Diff line
@@ -271,7 +271,7 @@ static void gsi_irq_enable(struct gsi *gsi) 
	iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);



	/* Never enable GSI_BREAK_POINT */

	val = GSI_CNTXT_GSI_IRQ_ALL & ~EN_BREAK_POINT_FMASK;

	val = GSI_CNTXT_GSI_IRQ_ALL & ~BREAK_POINT_FMASK;

	iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);

}

drivers/net/ipa/gsi_reg.h

+6 −15
Original line number Diff line number Diff line
@@ -340,29 +340,20 @@ 
			GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)

#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \

			(0x0001f118 + 0x4000 * (ee))

#define BREAK_POINT_FMASK		GENMASK(0, 0)

#define BUS_ERROR_FMASK			GENMASK(1, 1)

#define CMD_FIFO_OVRFLOW_FMASK		GENMASK(2, 2)

#define MCS_STACK_OVRFLOW_FMASK		GENMASK(3, 3)



#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \

			GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)

#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \

			(0x0001f120 + 0x4000 * (ee))

#define EN_BREAK_POINT_FMASK		GENMASK(0, 0)

#define EN_BUS_ERROR_FMASK		GENMASK(1, 1)

#define EN_CMD_FIFO_OVRFLOW_FMASK	GENMASK(2, 2)

#define EN_MCS_STACK_OVRFLOW_FMASK	GENMASK(3, 3)

#define GSI_CNTXT_GSI_IRQ_ALL		GENMASK(3, 0)



#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \

			GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)

#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \

			(0x0001f128 + 0x4000 * (ee))

#define CLR_BREAK_POINT_FMASK		GENMASK(0, 0)

#define CLR_BUS_ERROR_FMASK		GENMASK(1, 1)

#define CLR_CMD_FIFO_OVRFLOW_FMASK	GENMASK(2, 2)

#define CLR_MCS_STACK_OVRFLOW_FMASK	GENMASK(3, 3)

/* The masks below are used for the general IRQ STTS, EN, and CLR registers */

#define BREAK_POINT_FMASK		GENMASK(0, 0)

#define BUS_ERROR_FMASK			GENMASK(1, 1)

#define CMD_FIFO_OVRFLOW_FMASK		GENMASK(2, 2)

#define MCS_STACK_OVRFLOW_FMASK		GENMASK(3, 3)

#define GSI_CNTXT_GSI_IRQ_ALL		GENMASK(3, 0)



#define GSI_CNTXT_INTSET_OFFSET \

			GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)