Loading Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +1 −1 Original line number Diff line number Diff line Loading @@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required, - "ext_i2s" - external I2S clock - optional, - "ext_gmac" - external GMAC clock - optional - "rmii_clkin" - external EMAC clock - optional Example: Clock controller node: Loading Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +2 −3 Original line number Diff line number Diff line Loading @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered Cells 4 and beyond are reserved for future use. When the 1st cell has a value of 0 or 1, cells 4 and beyond act as padding, and may be ignored. It is recommended that padding cells have a value of 0. Cells 4 and beyond are reserved for future use and must have a value of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: Loading Documentation/devicetree/bindings/rtc/s3c-rtc.txt +6 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,10 @@ Required properties: interrupt number is the rtc alarm interrupt and second interrupt number is the rtc tick interrupt. The number of cells representing a interrupt depends on the parent interrupt controller. - clocks: Must contain a list of phandle and clock specifier for the rtc and source clocks. - clock-names: Must contain "rtc" and "rtc_src" entries sorted in the same order as the clocks property. Example: Loading @@ -21,4 +25,6 @@ Example: compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <44 0 45 0>; clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; }; Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +1 −1 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ Optional properties: - fsl,uart-has-rtscts : Indicate the uart has rts and cts - fsl,irda-mode : Indicate the uart supports irda mode - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works is DCE mode by default. in DCE mode by default. Note: Each uart controller should have an alias correctly numbered in "aliases" node. Loading Documentation/filesystems/efivarfs.txt +7 −0 Original line number Diff line number Diff line Loading @@ -14,3 +14,10 @@ filesystem. efivarfs is typically mounted like this, mount -t efivarfs none /sys/firmware/efi/efivars Due to the presence of numerous firmware bugs where removing non-standard UEFI variables causes the system firmware to fail to POST, efivarfs files that are not well-known standardized variables are created as immutable files. This doesn't prevent removal - "chattr -i" will work - but it does prevent this kind of failure from being accomplished accidentally. Loading
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +1 −1 Original line number Diff line number Diff line Loading @@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required, - "ext_i2s" - external I2S clock - optional, - "ext_gmac" - external GMAC clock - optional - "rmii_clkin" - external EMAC clock - optional Example: Clock controller node: Loading
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +2 −3 Original line number Diff line number Diff line Loading @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered Cells 4 and beyond are reserved for future use. When the 1st cell has a value of 0 or 1, cells 4 and beyond act as padding, and may be ignored. It is recommended that padding cells have a value of 0. Cells 4 and beyond are reserved for future use and must have a value of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: Loading
Documentation/devicetree/bindings/rtc/s3c-rtc.txt +6 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,10 @@ Required properties: interrupt number is the rtc alarm interrupt and second interrupt number is the rtc tick interrupt. The number of cells representing a interrupt depends on the parent interrupt controller. - clocks: Must contain a list of phandle and clock specifier for the rtc and source clocks. - clock-names: Must contain "rtc" and "rtc_src" entries sorted in the same order as the clocks property. Example: Loading @@ -21,4 +25,6 @@ Example: compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <44 0 45 0>; clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; };
Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +1 −1 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ Optional properties: - fsl,uart-has-rtscts : Indicate the uart has rts and cts - fsl,irda-mode : Indicate the uart supports irda mode - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works is DCE mode by default. in DCE mode by default. Note: Each uart controller should have an alias correctly numbered in "aliases" node. Loading
Documentation/filesystems/efivarfs.txt +7 −0 Original line number Diff line number Diff line Loading @@ -14,3 +14,10 @@ filesystem. efivarfs is typically mounted like this, mount -t efivarfs none /sys/firmware/efi/efivars Due to the presence of numerous firmware bugs where removing non-standard UEFI variables causes the system firmware to fail to POST, efivarfs files that are not well-known standardized variables are created as immutable files. This doesn't prevent removal - "chattr -i" will work - but it does prevent this kind of failure from being accomplished accidentally.