Commit fb57f829 authored by Ladislav Michl's avatar Ladislav Michl Committed by Greg Kroah-Hartman
Browse files

usb: dwc3: dwc3-octeon: Verify clock divider 



Although valid USB clock divider will be calculated for all valid
Octeon core frequencies, make code formally correct limiting
divider not to be greater that 7 so it fits into H_CLKDIV_SEL
field.

Signed-off-by: default avatarLadislav Michl <ladis@linux-mips.org>
Reported-by: default avatarLinux Kernel Functional Testing <lkft@linaro.org>
Closes: https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log


Acked-by: default avatarThinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/ZNIM7tlBNdHFzXZG@lenoch


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ff33299e

drivers/usb/dwc3/dwc3-octeon.c

+6 −2
Original line number Diff line number Diff line
@@ -251,11 +251,11 @@ static int dwc3_octeon_get_divider(void) 
	while (div < ARRAY_SIZE(clk_div)) {

		uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];

		if (rate <= 300000000 && rate >= 150000000)

			break;

			return div;

		div++;

	}



	return div;

	return -EINVAL;

}



static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
@@ -289,6 +289,10 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon, 


	/* Step 4b: Select controller clock frequency. */

	div = dwc3_octeon_get_divider();

	if (div < 0) {

		dev_err(dev, "clock divider invalid\n");

		return div;

	}

	val = dwc3_octeon_readq(uctl_ctl_reg);

	val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;

	val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);