Commit fb533d0c authored by Scott Wood's avatar Scott Wood Committed by Kumar Gala
Browse files

[POWERPC] 8xx: Infrastructure code cleanup. 



1. Keep a global mpc8xx_immr mapping, rather than constantly
creating temporary mappings.
2. Look for new fsl,cpm1 and fsl,cpm1-pic names.
3. Always reset the CPM when not using the udbg console;
this is required in case the firmware initialized a device
that is incompatible with one that the kernel is about to
use.
4. Remove some superfluous casts and header includes.
5. Change a usage of IMAP_ADDR to get_immrbase().
6. Use phys_addr_t, not uint, for dpram_pbase.
7. Various sparse-related fixes, such as __iomem annotations.
8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything
useful beyond the generic cpuinfo handler.
9. Move prototypes for 8xx support functions from board files
to sysdev/commproc.h.

Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent ccf0d68e

arch/powerpc/platforms/8xx/m8xx_setup.c

+20 −70
Original line number Diff line number Diff line
@@ -10,57 +10,33 @@ 
 * bootup setup stuff..

 */



#include <linux/errno.h>

#include <linux/sched.h>

#include <linux/kernel.h>

#include <linux/mm.h>

#include <linux/stddef.h>

#include <linux/unistd.h>

#include <linux/ptrace.h>

#include <linux/slab.h>

#include <linux/user.h>

#include <linux/a.out.h>

#include <linux/tty.h>

#include <linux/major.h>

#include <linux/interrupt.h>

#include <linux/reboot.h>

#include <linux/init.h>

#include <linux/initrd.h>

#include <linux/ioport.h>

#include <linux/bootmem.h>

#include <linux/seq_file.h>

#include <linux/root_dev.h>

#include <linux/time.h>

#include <linux/rtc.h>

#include <linux/fsl_devices.h>



#include <asm/mmu.h>

#include <asm/reg.h>

#include <asm/io.h>

#include <asm/pgtable.h>

#include <asm/mpc8xx.h>

#include <asm/8xx_immap.h>

#include <asm/machdep.h>

#include <asm/time.h>

#include <asm/prom.h>

#include <asm/fs_pd.h>

#include <mm/mmu_decl.h>



#include "sysdev/mpc8xx_pic.h"

#include <sysdev/mpc8xx_pic.h>

#include <sysdev/commproc.h>



#ifdef CONFIG_PCMCIA_M8XX

struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;

#endif



void m8xx_calibrate_decr(void);

#ifdef CONFIG_8xx_WDT

extern void m8xx_wdt_handler_install(bd_t *bp);

#endif

extern int cpm_pic_init(void);

extern int cpm_get_irq(void);



/* A place holder for time base interrupts, if they are ever enabled. */

irqreturn_t timebase_interrupt(int irq, void * dev)

static irqreturn_t timebase_interrupt(int irq, void *dev)

{

	printk ("timebase_interrupt()\n");
@@ -77,7 +53,7 @@ static struct irqaction tbint_irqaction = { 
void __init __attribute__ ((weak))

init_internal_rtc(void)

{

	sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);

	sit8xx_t __iomem *sys_tmr = immr_map(im_sit);



	/* Disable the RTC one second and alarm interrupts. */

	clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
@@ -116,13 +92,13 @@ static int __init get_freq(char *name, unsigned long *val) 
void __init mpc8xx_calibrate_decr(void)

{

	struct device_node *cpu;

	cark8xx_t *clk_r1;

	car8xx_t *clk_r2;

	sitk8xx_t *sys_tmr1;

	sit8xx_t *sys_tmr2;

	cark8xx_t __iomem *clk_r1;

	car8xx_t __iomem *clk_r2;

	sitk8xx_t __iomem *sys_tmr1;

	sit8xx_t __iomem *sys_tmr2;

	int irq, virq;



	clk_r1 = (cark8xx_t *) immr_map(im_clkrstk);

	clk_r1 = immr_map(im_clkrstk);



	/* Unlock the SCCR. */

	out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
@@ -130,7 +106,7 @@ void __init mpc8xx_calibrate_decr(void) 
	immr_unmap(clk_r1);



	/* Force all 8xx processors to use divide by 16 processor clock. */

	clk_r2 = (car8xx_t *) immr_map(im_clkrst);

	clk_r2 = immr_map(im_clkrst);

	setbits32(&clk_r2->car_sccr, 0x02000000);

	immr_unmap(clk_r2);
@@ -164,7 +140,7 @@ void __init mpc8xx_calibrate_decr(void) 
	 * we guarantee the registers are locked, then we unlock them

	 * for our use.

	 */

	sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);

	sys_tmr1 = immr_map(im_sitk);

	out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);

	out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);

	out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
@@ -184,20 +160,13 @@ void __init mpc8xx_calibrate_decr(void) 
	virq= irq_of_parse_and_map(cpu, 0);

	irq = irq_map[virq].hwirq;



	sys_tmr2 = (sit8xx_t *) immr_map(im_sit);

	sys_tmr2 = immr_map(im_sit);

	out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |

					(TBSCR_TBF | TBSCR_TBE));

	immr_unmap(sys_tmr2);



	if (setup_irq(virq, &tbint_irqaction))

		panic("Could not allocate timer IRQ!");



#ifdef CONFIG_8xx_WDT

	/* Install watchdog timer handler early because it might be

	 * already enabled by the bootloader

	 */

	m8xx_wdt_handler_install(binfo);

#endif

}



/* The RTC on the MPC8xx is an internal register.
@@ -207,12 +176,12 @@ void __init mpc8xx_calibrate_decr(void) 


int mpc8xx_set_rtc_time(struct rtc_time *tm)

{

	sitk8xx_t *sys_tmr1;

	sit8xx_t *sys_tmr2;

	sitk8xx_t __iomem *sys_tmr1;

	sit8xx_t __iomem *sys_tmr2;

	int time;



	sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);

	sys_tmr2 = (sit8xx_t *) immr_map(im_sit);

	sys_tmr1 = immr_map(im_sitk);

	sys_tmr2 = immr_map(im_sit);

	time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,

	              tm->tm_hour, tm->tm_min, tm->tm_sec);
@@ -228,7 +197,7 @@ int mpc8xx_set_rtc_time(struct rtc_time *tm) 
void mpc8xx_get_rtc_time(struct rtc_time *tm)

{

	unsigned long data;

	sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);

	sit8xx_t __iomem *sys_tmr = immr_map(im_sit);



	/* Get time from the RTC. */

	data = in_be32(&sys_tmr->sit_rtc);
@@ -241,8 +210,7 @@ void mpc8xx_get_rtc_time(struct rtc_time *tm) 


void mpc8xx_restart(char *cmd)

{

	__volatile__ unsigned char dummy;

	car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);

	car8xx_t __iomem *clk_r = immr_map(im_clkrst);





	local_irq_disable();
@@ -252,26 +220,8 @@ void mpc8xx_restart(char *cmd) 
	*/

	mtmsr(mfmsr() & ~0x1000);



	dummy = in_8(&clk_r->res[0]);

	printk("Restart failed\n");

	while(1);

}



void mpc8xx_show_cpuinfo(struct seq_file *m)

{

	struct device_node *root;

	uint memsize = total_memory;

	const char *model = "";



	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");



	root = of_find_node_by_path("/");

	if (root)

		model = of_get_property(root, "model", NULL);

	seq_printf(m, "Machine\t\t: %s\n", model);

	of_node_put(root);



	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));

	in_8(&clk_r->res[0]);

	panic("Restart failed\n");

}



static void cpm_cascade(unsigned int irq, struct irq_desc *desc)

arch/powerpc/platforms/8xx/mpc86xads.h

+0 −3
Original line number Diff line number Diff line
@@ -29,9 +29,6 @@ 
#define CFG_PHYDEV_ADDR		((uint)0xff0a0000)

#define BCSR5			((uint)(CFG_PHYDEV_ADDR + 0x300))



#define IMAP_ADDR		(get_immrbase())

#define IMAP_SIZE		((uint)(64 * 1024))



#define MPC8xx_CPM_OFFSET	(0x9c0)

#define CPM_MAP_ADDR		(get_immrbase() + MPC8xx_CPM_OFFSET)

#define CPM_IRQ_OFFSET		16     // for compability with cpm_uart driver

arch/powerpc/platforms/8xx/mpc86xads_setup.c

+1 −9
Original line number Diff line number Diff line
@@ -37,14 +37,7 @@ 
#include <asm/fs_pd.h>

#include <asm/prom.h>



extern void cpm_reset(void);

extern void mpc8xx_show_cpuinfo(struct seq_file*);

extern void mpc8xx_restart(char *cmd);

extern void mpc8xx_calibrate_decr(void);

extern int mpc8xx_set_rtc_time(struct rtc_time *tm);

extern void mpc8xx_get_rtc_time(struct rtc_time *tm);

extern void m8xx_pic_init(void);

extern unsigned int mpc8xx_get_irq(void);

#include <sysdev/commproc.h>



static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);

static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
@@ -277,7 +270,6 @@ define_machine(mpc86x_ads) { 
	.probe			= mpc86xads_probe,

	.setup_arch		= mpc86xads_setup_arch,

	.init_IRQ		= m8xx_pic_init,

	.show_cpuinfo		= mpc8xx_show_cpuinfo,

	.get_irq		= mpc8xx_get_irq,

	.restart		= mpc8xx_restart,

	.calibrate_decr		= mpc8xx_calibrate_decr,

arch/powerpc/platforms/8xx/mpc885ads.h

+0 −3
Original line number Diff line number Diff line
@@ -29,9 +29,6 @@ 
#define CFG_PHYDEV_ADDR		((uint)0xff0a0000)

#define BCSR5			((uint)(CFG_PHYDEV_ADDR + 0x300))



#define IMAP_ADDR		(get_immrbase())

#define IMAP_SIZE		((uint)(64 * 1024))



#define MPC8xx_CPM_OFFSET	(0x9c0)

#define CPM_MAP_ADDR		(get_immrbase() + MPC8xx_CPM_OFFSET)

#define CPM_IRQ_OFFSET		16     // for compability with cpm_uart driver

arch/powerpc/platforms/8xx/mpc885ads_setup.c

+1 −9
Original line number Diff line number Diff line
@@ -38,14 +38,7 @@ 
#include <asm/fs_pd.h>

#include <asm/prom.h>



extern void cpm_reset(void);

extern void mpc8xx_show_cpuinfo(struct seq_file *);

extern void mpc8xx_restart(char *cmd);

extern void mpc8xx_calibrate_decr(void);

extern int mpc8xx_set_rtc_time(struct rtc_time *tm);

extern void mpc8xx_get_rtc_time(struct rtc_time *tm);

extern void m8xx_pic_init(void);

extern unsigned int mpc8xx_get_irq(void);

#include <sysdev/commproc.h>



static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi);

static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
@@ -430,7 +423,6 @@ define_machine(mpc885_ads) 
	.probe           = mpc885ads_probe,

	.setup_arch      = mpc885ads_setup_arch,

	.init_IRQ        = m8xx_pic_init,

	.show_cpuinfo    = mpc8xx_show_cpuinfo,

	.get_irq         = mpc8xx_get_irq,

	.restart         = mpc8xx_restart,

	.calibrate_decr  = mpc8xx_calibrate_decr,