Commit fb3989b0 authored by wenglianfa's avatar wenglianfa Committed by Chengchang Tang
Browse files

RDMA/hns: Fix an AEQE overflow error caused by untimely update of eq_db_ci 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAQEU6



----------------------------------------------------------------------

The CI is updated only after all AEQEs are processed in
the AEQ interrupt, leading to untimely updates and resulting
in AEQE overflow. Two optimization methods are proposed:

1. Set an upper limit for AEQE processing.
2. Move time-consuming operations to the bottom half of the
interrupt.

The mbx event is processed in the top half of the interrupt
to ensure timely handling. This is crucial for promptly setting
context->done to the complete state.

Leave the handling of QP errors in the top half of interrupt to
ensure timely change of QP status and execute flush_cqe().

Fixes: a5073d60 ("RDMA/hns: Add eq support of hip08")
Signed-off-by: default avatarwenglianfa <wenglianfa@huawei.com>
Signed-off-by: default avatarXinghai Cen <cenxinghai@h-partners.com>
parent e23f7612

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+44 −24
Original line number Diff line number Diff line
@@ -6700,11 +6700,10 @@ static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 
	return ret;

}



static void hns_roce_irq_work_handle(struct work_struct *work)

static void dump_aeqe_log(struct hns_roce_work *irq_work)

{

	struct hns_roce_work *irq_work =

				container_of(work, struct hns_roce_work, work);

	struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;

	struct hns_roce_dev *hr_dev = irq_work->hr_dev;

	struct ib_device *ibdev = &hr_dev->ib_dev;



	switch (irq_work->event_type) {

	case HNS_ROCE_EVENT_TYPE_PATH_MIG:
@@ -6748,6 +6747,8 @@ static void hns_roce_irq_work_handle(struct work_struct *work) 
	case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:

		ibdev_warn(ibdev, "DB overflow.\n");

		break;

	case HNS_ROCE_EVENT_TYPE_MB:

		break;

	case HNS_ROCE_EVENT_TYPE_FLR:

		ibdev_warn(ibdev, "Function level reset.\n");

		break;
@@ -6757,10 +6758,43 @@ static void hns_roce_irq_work_handle(struct work_struct *work) 
	case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:

		ibdev_err(ibdev, "invalid xrceth error.\n");

		break;

	default:

		ibdev_info(ibdev, "Undefined event %d.\n",

			   irq_work->event_type);

		break;

	}

}



static void hns_roce_irq_work_handle(struct work_struct *work)

{

	struct hns_roce_work *irq_work =

				container_of(work, struct hns_roce_work, work);

	struct hns_roce_dev *hr_dev = irq_work->hr_dev;

	int event_type = irq_work->event_type;

	u32 queue_num = irq_work->queue_num;



	switch (event_type) {

	case HNS_ROCE_EVENT_TYPE_PATH_MIG:

	case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:

	case HNS_ROCE_EVENT_TYPE_COMM_EST:

	case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:

	case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:

		hns_roce_qp_event(hr_dev, queue_num, event_type);

		break;

	case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:

	case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:

		hns_roce_srq_event(hr_dev, queue_num, event_type);

		break;

	case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:

	case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:

		hns_roce_cq_event(hr_dev, queue_num, event_type);

		break;

	default:

		break;

	}



	dump_aeqe_log(irq_work);



	kfree(irq_work);

}
@@ -6820,14 +6854,14 @@ static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 
static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,

				       struct hns_roce_eq *eq)

{

	struct device *dev = hr_dev->dev;

	struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);

	irqreturn_t aeqe_found = IRQ_NONE;

	int num_aeqes = 0;

	int event_type;

	u32 queue_num;

	int sub_type;



	while (aeqe) {

	while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) {

		/* Make sure we read AEQ entry after we have checked the

		 * ownership bit

		 */
@@ -6838,38 +6872,20 @@ static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 
		queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);



		switch (event_type) {

		case HNS_ROCE_EVENT_TYPE_PATH_MIG:

		case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:

		case HNS_ROCE_EVENT_TYPE_COMM_EST:

		case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:

		case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:

		case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:

		case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:

		case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:

		case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:

		case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:

			hns_roce_qp_event(hr_dev, queue_num, event_type);

			break;

		case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:

		case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:

			hns_roce_srq_event(hr_dev, queue_num, event_type);

			break;

		case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:

		case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:

			hns_roce_cq_event(hr_dev, queue_num, event_type);

			break;

		case HNS_ROCE_EVENT_TYPE_MB:

			hns_roce_cmd_event(hr_dev,

					le16_to_cpu(aeqe->event.cmd.token),

					aeqe->event.cmd.status,

					le64_to_cpu(aeqe->event.cmd.out_param));

			break;

		case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:

		case HNS_ROCE_EVENT_TYPE_FLR:

			break;

		default:

			dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",

				event_type, eq->eqn, eq->cons_index);

			break;

		}
@@ -6882,6 +6898,7 @@ static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 
		hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);



		aeqe = next_aeqe_sw_v2(eq);

		++num_aeqes;

	}



	update_eq_db(eq);
@@ -7432,6 +7449,9 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 
	int ret;

	int i;



	if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET)

		return -EINVAL;



	other_num = hr_dev->caps.num_other_vectors;

	comp_num = hr_dev->caps.num_comp_vectors;

	aeq_num = hr_dev->caps.num_aeq_vectors;

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+5 −0
Original line number Diff line number Diff line
@@ -85,6 +85,11 @@ 


#define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)



/* budget must be smaller than aeqe_depth to guarantee that we update

 * the ci before we polled all the entries in the EQ.

 */

#define HNS_AEQ_POLLING_BUDGET 64



enum {

	HNS_ROCE_CMD_FLAG_IN = BIT(0),

	HNS_ROCE_CMD_FLAG_OUT = BIT(1),