Commit fb12fbb1 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use intel_de_rmw() in bdw cdclk programming 



Replace the hand rolled rmw sequences with intel_de_rmw().

Jani pointed out that intel_de_rmw() skips the write if the
value does not change. That should be totally fine here, but
let's at least acknowledge the change in behaviour in case I'm
somehow wrong...

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210430153444.29270-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent b41df85a

drivers/gpu/drm/i915/display/intel_cdclk.c

+6 −11
Original line number Diff line number Diff line
@@ -746,7 +746,6 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
			  enum pipe pipe)

{

	int cdclk = cdclk_config->cdclk;

	u32 val;

	int ret;



	if (drm_WARN(&dev_priv->drm,
@@ -766,9 +765,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
		return;

	}



	val = intel_de_read(dev_priv, LCPLL_CTL);

	val |= LCPLL_CD_SOURCE_FCLK;

	intel_de_write(dev_priv, LCPLL_CTL, val);

	intel_de_rmw(dev_priv, LCPLL_CTL,

		     0, LCPLL_CD_SOURCE_FCLK);



	/*

	 * According to the spec, it should be enough to poll for this 1 us.
@@ -778,14 +776,11 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
			LCPLL_CD_SOURCE_FCLK_DONE, 100))

		drm_err(&dev_priv->drm, "Switching to FCLK failed\n");



	val = intel_de_read(dev_priv, LCPLL_CTL);

	val &= ~LCPLL_CLK_FREQ_MASK;

	val |= bdw_cdclk_freq_sel(cdclk);

	intel_de_write(dev_priv, LCPLL_CTL, val);

	intel_de_rmw(dev_priv, LCPLL_CTL,

		     LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));



	val = intel_de_read(dev_priv, LCPLL_CTL);

	val &= ~LCPLL_CD_SOURCE_FCLK;

	intel_de_write(dev_priv, LCPLL_CTL, val);

	intel_de_rmw(dev_priv, LCPLL_CTL,

		     LCPLL_CD_SOURCE_FCLK, 0);



	if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &

			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))