Merge remote-tracking branch 'spi/for-5.8' into spi-next

    "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs

    "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

						   BRCMSTB  SoCs

    "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"     : MSPI+BSPI on Cygnus, NSP

    "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"     : NS2 SoCs

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/mikrotik,rb4xx-spi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MikroTik RB4xx series SPI master

maintainers:

  - Gabor Juhos <juhosg@openwrt.org>

  - Bert Vermeulen <bert@biot.com>

allOf:

  - $ref: "spi-controller.yaml#"

properties:

  compatible:

    const: mikrotik,rb4xx-spi

  reg:

    maxItems: 1

required:

  - compatible

  - reg

examples:

  - |

    spi: spi@1f000000 {

        #address-cells = <1>;

        #size-cells = <0>;

        compatible = "mikrotik,rb4xx-spi";

        reg = <0x1f000000 0x10>;

    };

...

 No newline at end of file

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/renesas,rspi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)

maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - renesas,rspi-sh7757    # SH7757

          - const: renesas,rspi        # Legacy SH

      - items:

          - enum:

              - renesas,rspi-r7s72100  # RZ/A1H

              - renesas,rspi-r7s9210   # RZ/A2

          - const: renesas,rspi-rz     # RZ/A

      - items:

          - enum:

              - renesas,qspi-r8a7743   # RZ/G1M

              - renesas,qspi-r8a7744   # RZ/G1N

              - renesas,qspi-r8a7745   # RZ/G1E

              - renesas,qspi-r8a77470  # RZ/G1C

              - renesas,qspi-r8a7790   # R-Car H2

              - renesas,qspi-r8a7791   # R-Car M2-W

              - renesas,qspi-r8a7792   # R-Car V2H

              - renesas,qspi-r8a7793   # R-Car M2-N

              - renesas,qspi-r8a7794   # R-Car E2

          - const: renesas,qspi        # R-Car Gen2 and RZ/G1

  reg:

    maxItems: 1

  interrupts:

    oneOf:

      - items:

          - description: A combined interrupt

      - items:

          - description: Error interrupt (SPEI)

          - description: Receive Interrupt (SPRI)

          - description: Transmit Interrupt (SPTI)

  interrupt-names:

    oneOf:

      - items:

          - const: mux

      - items:

          - const: error

          - const: rx

          - const: tx

  clocks:

    maxItems: 1

  power-domains:

    maxItems: 1

  resets:

    maxItems: 1

  dmas:

    description:

      Must contain a list of pairs of references to DMA specifiers, one for

      transmission, and one for reception.

  dma-names:

    minItems: 2

    maxItems: 4

    items:

      enum:

        - tx

        - rx

  num-cs:

    description: |

      Total number of native chip selects.

      Hardware limitations related to chip selects:

        - When using GPIO chip selects, at least one native chip select must

          be left unused, as it will be driven anyway.

    minimum: 1

    maximum: 2

    default: 1

required:

  - compatible

  - reg

  - interrupts

  - clocks

  - power-domains

  - '#address-cells'

  - '#size-cells'

allOf:

  - $ref: spi-controller.yaml#

  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,rspi-rz

    then:

      properties:

        interrupts:

          minItems: 3

      required:

        - interrupt-names

  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,qspi

    then:

      required:

        - resets

examples:

  - |

    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a7791-sysc.h>

    qspi: spi@e6b10000 {

            compatible = "renesas,qspi-r8a7791", "renesas,qspi";

            reg = <0xe6b10000 0x2c>;

            interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&cpg CPG_MOD 917>;

            dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>;

            dma-names = "tx", "rx", "tx", "rx";

            power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;

            resets = <&cpg 917>;

            num-cs = <1>;

            #address-cells = <1>;

            #size-cells = <0>;

    };

Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.

Required properties:

- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or

  "jaguar2", or "amazon,alpine-dw-apb-ssi"

- reg : The register base for the controller. For "mscc,<soc>-spi", a second

  register set is required (named ICPU_CFG:SPI_MST)

- interrupts : One interrupt, used by the controller.

- #address-cells : <1>, as required by generic SPI binding.

- #size-cells : <0>, also as required by generic SPI binding.

- clocks : phandles for the clocks, see the description of clock-names below.

   The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock

   is optional. If a single clock is specified but no clock-name, it is the

   "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.

Optional properties:

- clock-names : Contains the names of the clocks:

    "ssi_clk", for the core clock used to generate the external SPI clock.

    "pclk", the interface clock, required for register access. If a clock domain

     used to enable this clock then it should be named "pclk_clkdomain".

- cs-gpios : Specifies the gpio pins to be used for chipselects.

- num-cs : The number of chipselects. If omitted, this will default to 4.

- reg-io-width : The I/O register width (in bytes) implemented by this

  device.  Supported values are 2 or 4 (the default).

Child nodes as per the generic SPI binding.

Example:

	spi@fff00000 {

		compatible = "snps,dw-apb-ssi";

		reg = <0xfff00000 0x1000>;

		interrupts = <0 154 4>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&spi_m_clk>;

		num-cs = <2>;

		cs-gpios = <&gpio0 13 0>,

			   <&gpio0 14 0>;

	};

# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface

maintainers:

  - Mark Brown <broonie@kernel.org>

allOf:

  - $ref: "spi-controller.yaml#"

  - if:

      properties:

        compatible:

          contains:

            enum:

              - mscc,ocelot-spi

              - mscc,jaguar2-spi

    then:

      properties:

        reg:

          minItems: 2

properties:

  compatible:

    oneOf:

      - description: Generic DW SPI Controller

        enum:

          - snps,dw-apb-ssi

          - snps,dwc-ssi-1.01a

      - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller

        items:

          - enum:

              - mscc,ocelot-spi

              - mscc,jaguar2-spi

          - const: snps,dw-apb-ssi

      - description: Amazon Alpine SPI Controller

        const: amazon,alpine-dw-apb-ssi

      - description: Renesas RZ/N1 SPI Controller

        items:

          - const: renesas,rzn1-spi

          - const: snps,dw-apb-ssi

      - description: Intel Keem Bay SPI Controller

        const: intel,keembay-ssi

  reg:

    minItems: 1

    items:

      - description: DW APB SSI controller memory mapped registers

      - description: SPI MST region map

  interrupts:

    maxItems: 1

  clocks:

    minItems: 1

    items:

      - description: SPI Controller reference clock source

      - description: APB interface clock source

  clock-names:

    minItems: 1

    items:

      - const: ssi_clk

      - const: pclk

  resets:

    maxItems: 1

  reset-names:

    const: spi

  reg-io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: I/O register width (in bytes) implemented by this device

    default: 4

    enum: [ 2, 4 ]

  num-cs:

    default: 4

    minimum: 1

    maximum: 4

  dmas:

    items:

      - description: TX DMA Channel

      - description: RX DMA Channel

  dma-names:

    items:

      - const: tx

      - const: rx

patternProperties:

  "^.*@[0-9a-f]+$":

    type: object

    properties:

      reg:

        minimum: 0

        maximum: 3

      spi-rx-bus-width:

        const: 1

      spi-tx-bus-width:

        const: 1

unevaluatedProperties: false

required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"

  - interrupts

  - clocks

examples:

  - |

    spi@fff00000 {

      compatible = "snps,dw-apb-ssi";

      reg = <0xfff00000 0x1000>;

      #address-cells = <1>;

      #size-cells = <0>;

      interrupts = <0 154 4>;

      clocks = <&spi_m_clk>;

      num-cs = <2>;

      cs-gpios = <&gpio0 13 0>,

                 <&gpio0 14 0>;

    };

...