Commit faedfa5b authored by Frank Wunderlich's avatar Frank Wunderlich Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add PCIe v3 nodes to rk3568 



Add nodes to rk356x devicetree to support PCIe v3.

Signed-off-by: default avatarPeter Geis <pgwipeout@gmail.com>
Signed-off-by: default avatarFrank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent a233ea1e

arch/arm64/boot/dts/rockchip/rk3568.dtsi

+122 −0
Original line number Original line Diff line number Diff line
@@ -42,6 +42,128 @@ 
		reg = <0x0 0xfe190200 0x0 0x20>;

		reg = <0x0 0xfe190200 0x0 0x20>;

	};

	};





	pcie30_phy_grf: syscon@fdcb8000 {

		compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";

		reg = <0x0 0xfdcb8000 0x0 0x10000>;

	};



	pcie30phy: phy@fe8c0000 {

		compatible = "rockchip,rk3568-pcie3-phy";

		reg = <0x0 0xfe8c0000 0x0 0x20000>;

		#phy-cells = <0>;

		clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,

			 <&cru PCLK_PCIE30PHY>;

		clock-names = "refclk_m", "refclk_n", "pclk";

		resets = <&cru SRST_PCIE30PHY>;

		reset-names = "phy";

		rockchip,phy-grf = <&pcie30_phy_grf>;

		status = "disabled";

	};



	pcie3x1: pcie@fe270000 {

		compatible = "rockchip,rk3568-pcie";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xf>;

		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,

			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,

			 <&cru CLK_PCIE30X1_AUX_NDFT>;

		clock-names = "aclk_mst", "aclk_slv",

			      "aclk_dbi", "pclk", "aux";

		device_type = "pci";

		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "sys", "pmc", "msg", "legacy", "err";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,

				<0 0 0 2 &pcie3x1_intc 1>,

				<0 0 0 3 &pcie3x1_intc 2>,

				<0 0 0 4 &pcie3x1_intc 3>;

		linux,pci-domain = <1>;

		num-ib-windows = <6>;

		num-ob-windows = <2>;

		max-link-speed = <3>;

		msi-map = <0x0 &gic 0x1000 0x1000>;

		num-lanes = <1>;

		phys = <&pcie30phy>;

		phy-names = "pcie-phy";

		power-domains = <&power RK3568_PD_PIPE>;

		reg = <0x3 0xc0400000 0x0 0x00400000>,

		      <0x0 0xfe270000 0x0 0x00010000>,

		      <0x3 0x7f000000 0x0 0x01000000>;

		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,

			 <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;

		reg-names = "dbi", "apb", "config";

		resets = <&cru SRST_PCIE30X1_POWERUP>;

		reset-names = "pipe";

		/* bifurcation; lane1 when using 1+1 */

		status = "disabled";



		pcie3x1_intc: legacy-interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;

		};

	};



	pcie3x2: pcie@fe280000 {

		compatible = "rockchip,rk3568-pcie";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xf>;

		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,

			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,

			 <&cru CLK_PCIE30X2_AUX_NDFT>;

		clock-names = "aclk_mst", "aclk_slv",

			      "aclk_dbi", "pclk", "aux";

		device_type = "pci";

		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "sys", "pmc", "msg", "legacy", "err";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,

				<0 0 0 2 &pcie3x2_intc 1>,

				<0 0 0 3 &pcie3x2_intc 2>,

				<0 0 0 4 &pcie3x2_intc 3>;

		linux,pci-domain = <2>;

		num-ib-windows = <6>;

		num-ob-windows = <2>;

		max-link-speed = <3>;

		msi-map = <0x0 &gic 0x2000 0x1000>;

		num-lanes = <2>;

		phys = <&pcie30phy>;

		phy-names = "pcie-phy";

		power-domains = <&power RK3568_PD_PIPE>;

		reg = <0x3 0xc0800000 0x0 0x00400000>,

		      <0x0 0xfe280000 0x0 0x00010000>,

		      <0x3 0xbf000000 0x0 0x01000000>;

		ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,

			 <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;

		reg-names = "dbi", "apb", "config";

		resets = <&cru SRST_PCIE30X2_POWERUP>;

		reset-names = "pipe";

		/* bifurcation; lane0 when using 1+1 */

		status = "disabled";



		pcie3x2_intc: legacy-interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;

		};

	};



	gmac0: ethernet@fe2a0000 {

	gmac0: ethernet@fe2a0000 {

		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";

		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";

		reg = <0x0 0xfe2a0000 0x0 0x10000>;

		reg = <0x0 0xfe2a0000 0x0 0x10000>;