Commit fae3bcc3 authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
Browse files

arm64: dts: imx8mp: move PCIe controller clock config to SoC dtsi 



The only difference in PCIe clock configuration between boards is how
the PCIe reference clock is generated. The refclock configuration is
fully contained in the PCIe PHY node, so the PCIe controller clocks
can be set up in the SoC dtsi, as there is no reason for any board to
use a different configuration.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0deefb5b

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

+0 −7
Original line number Diff line number Diff line
@@ -400,13 +400,6 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

		 <&clk IMX8MP_CLK_PCIE_ROOT>,

		 <&clk IMX8MP_CLK_HSIO_AXI>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;

	assigned-clock-rates = <10000000>;

	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;

	vpcie-supply = <&reg_pcie0>;

	status = "okay";

};

arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts

+0 −7
Original line number Diff line number Diff line
@@ -593,13 +593,6 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

		 <&clk IMX8MP_CLK_PCIE_ROOT>,

		 <&clk IMX8MP_CLK_HSIO_AXI>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;

	assigned-clock-rates = <10000000>;

	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;

	status = "okay";

};

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -1202,6 +1202,13 @@ 
			compatible = "fsl,imx8mp-pcie";

			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;

			reg-names = "dbi", "config";

			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

				 <&clk IMX8MP_CLK_PCIE_ROOT>,

				 <&clk IMX8MP_CLK_HSIO_AXI>;

			clock-names = "pcie", "pcie_aux", "pcie_bus";

			assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;

			assigned-clock-rates = <10000000>;

			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";